mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-14 02:30:37 +02:00
796a9d1091
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15242 3c298f89-4303-0410-b956-a3cf2f4a3e73
340 lines
7.9 KiB
C
340 lines
7.9 KiB
C
/*
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* BCM47XX support code for some chipcommon facilities (uart, jtagm)
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#include <typedefs.h>
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#include <bcmdefs.h>
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#include <osl.h>
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#include <sbutils.h>
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#include <bcmdevs.h>
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#include <bcmnvram.h>
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#include <sbconfig.h>
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#include <sbchipc.h>
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#include <sbextif.h>
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#include <hndchipc.h>
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#include <hndcpu.h>
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/* debug/trace */
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#define CC_ERROR(args)
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#ifdef BCMDBG
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#define CC_MSG(args) printf args
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#else
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#define CC_MSG(args)
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#endif /* BCMDBG */
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/* interested chipcommon interrupt source
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* - GPIO
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* - EXTIF
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* - ECI
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* - PMU
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* - UART
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*/
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#define MAX_CC_INT_SOURCE 5
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/* chipc secondary isr info */
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typedef struct {
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uint intmask; /* int mask */
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cc_isr_fn isr; /* secondary isr handler */
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void *cbdata; /* pointer to private data */
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} cc_isr_info_t;
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static cc_isr_info_t cc_isr_desc[MAX_CC_INT_SOURCE];
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/* chip common intmask */
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static uint32 cc_intmask = 0;
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static bool BCMINITFN(serial_exists) (osl_t * osh, uint8 * regs) {
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uint8 save_mcr, status1;
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save_mcr = R_REG(osh, ®s[UART_MCR]);
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W_REG(osh, ®s[UART_MCR], UART_MCR_LOOP | 0x0a);
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status1 = R_REG(osh, ®s[UART_MSR]) & 0xf0;
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W_REG(osh, ®s[UART_MCR], save_mcr);
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return (status1 == 0x90);
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}
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static void __init sb_extif_serial_init(sb_t * sbh, void *regs,
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sb_serial_init_fn add)
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{
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osl_t *osh = sb_osh(sbh);
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extifregs_t *eir = (extifregs_t *) regs;
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sbconfig_t *sb;
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ulong base;
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uint irq;
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int i, n;
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/* Determine external UART register base */
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sb = (sbconfig_t *) ((ulong) eir + SBCONFIGOFF);
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base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
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/* Determine IRQ */
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irq = sb_irq(sbh);
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/* Disable GPIO interrupt initially */
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W_REG(osh, &eir->gpiointpolarity, 0);
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W_REG(osh, &eir->gpiointmask, 0);
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/* Search for external UARTs */
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n = 2;
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for (i = 0; i < 2; i++) {
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regs = (void *)REG_MAP(base + (i * 8), 8);
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if (serial_exists(osh, regs)) {
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/* Set GPIO 1 to be the external UART IRQ */
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W_REG(osh, &eir->gpiointmask, 2);
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/* XXXDetermine external UART clock */
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if (add)
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add(regs, irq, 13500000, 0);
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}
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}
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/* Add internal UART if enabled */
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if (R_REG(osh, &eir->corecontrol) & CC_UE)
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if (add)
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add((void *)&eir->uartdata, irq, sb_clock(sbh), 2);
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}
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/*
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* Initializes UART access. The callback function will be called once
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* per found UART.
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*/
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void BCMINITFN(sb_serial_init) (sb_t * sbh, sb_serial_init_fn add) {
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osl_t *osh;
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void *regs;
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chipcregs_t *cc;
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uint32 rev, cap, pll, baud_base, div;
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uint irq;
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int i, n;
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osh = sb_osh(sbh);
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regs = sb_setcore(sbh, SB_EXTIF, 0);
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if (regs) {
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sb_extif_serial_init(sbh, regs, add);
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return;
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}
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cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0);
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ASSERT(cc);
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/* Determine core revision and capabilities */
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rev = sbh->ccrev;
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cap = sbh->cccaps;
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pll = cap & CC_CAP_PLL_MASK;
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/* Determine IRQ */
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irq = sb_irq(sbh);
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if (pll == PLL_TYPE1) {
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/* PLL clock */
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baud_base = sb_clock_rate(pll,
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R_REG(osh, &cc->clockcontrol_n),
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R_REG(osh, &cc->clockcontrol_m2));
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div = 1;
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} else {
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/* 5354 chip common uart uses a constant clock
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* frequency of 25MHz */
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if (sb_corerev(sbh) == 20) {
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/* Set the override bit so we don't divide it */
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W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
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baud_base = 25000000;
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} else if (rev >= 11 && rev != 15) {
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/* Fixed ALP clock */
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baud_base = sb_alp_clock(sbh);
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div = 1;
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/* Turn off UART clock before switching clock source */
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if (rev >= 21)
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AND_REG(osh, &cc->corecontrol, ~CC_UARTCLKEN);
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/* Set the override bit so we don't divide it */
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OR_REG(osh, &cc->corecontrol, CC_UARTCLKO);
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if (rev >= 21)
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OR_REG(osh, &cc->corecontrol, CC_UARTCLKEN);
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} else if (rev >= 3) {
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/* Internal backplane clock */
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baud_base = sb_clock(sbh);
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div = 2; /* Minimum divisor */
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W_REG(osh, &cc->clkdiv,
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((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
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} else {
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/* Fixed internal backplane clock */
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baud_base = 88000000;
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div = 48;
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}
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/* Clock source depends on strapping if UartClkOverride is unset */
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if ((rev > 0)
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&& ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
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if ((cap & CC_CAP_UCLKSEL) == CC_CAP_UINTCLK) {
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/* Internal divided backplane clock */
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baud_base /= div;
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} else {
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/* Assume external clock of 1.8432 MHz */
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baud_base = 1843200;
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}
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}
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}
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/* Add internal UARTs */
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n = cap & CC_CAP_UARTS_MASK;
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for (i = 0; i < n; i++) {
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/* Register offset changed after revision 0 */
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if (rev)
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regs = (void *)((ulong) & cc->uart0data + (i * 256));
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else
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regs = (void *)((ulong) & cc->uart0data + (i * 8));
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if (add)
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add(regs, irq, baud_base, 0);
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}
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}
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#if 0
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/*
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* Initialize jtag master and return handle for
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* jtag_rwreg. Returns NULL on failure.
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*/
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void *sb_jtagm_init(sb_t * sbh, uint clkd, bool exttap)
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{
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void *regs;
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if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
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chipcregs_t *cc = (chipcregs_t *) regs;
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uint32 tmp;
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/*
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* Determine jtagm availability from
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* core revision and capabilities.
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*/
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/*
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* Corerev 10 has jtagm, but the only chip
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* with it does not have a mips, and
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* the layout of the jtagcmd register is
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* different. We'll only accept >= 11.
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*/
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if (sbh->ccrev < 11)
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return (NULL);
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if ((sbh->cccaps & CC_CAP_JTAGP) == 0)
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return (NULL);
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/* Set clock divider if requested */
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if (clkd != 0) {
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tmp = R_REG(osh, &cc->clkdiv);
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tmp =
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(tmp & ~CLKD_JTAG) | ((clkd << CLKD_JTAG_SHIFT) &
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CLKD_JTAG);
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W_REG(osh, &cc->clkdiv, tmp);
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}
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/* Enable jtagm */
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tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
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W_REG(osh, &cc->jtagctrl, tmp);
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}
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return (regs);
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}
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void sb_jtagm_disable(osl_t * osh, void *h)
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{
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chipcregs_t *cc = (chipcregs_t *) h;
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W_REG(osh, &cc->jtagctrl, R_REG(osh, &cc->jtagctrl) & ~JCTRL_EN);
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}
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/*
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* Read/write a jtag register. Assumes a target with
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* 8 bit IR and 32 bit DR.
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*/
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#define IRWIDTH 8 /* Default Instruction Register width */
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#define DRWIDTH 32 /* Default Data Register width */
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uint32 jtag_rwreg(osl_t * osh, void *h, uint32 ir, uint32 dr)
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{
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chipcregs_t *cc = (chipcregs_t *) h;
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uint32 tmp;
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W_REG(osh, &cc->jtagir, ir);
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W_REG(osh, &cc->jtagdr, dr);
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tmp = JCMD_START | JCMD_ACC_IRDR |
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((IRWIDTH - 1) << JCMD_IRW_SHIFT) | (DRWIDTH - 1);
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W_REG(osh, &cc->jtagcmd, tmp);
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while (((tmp = R_REG(osh, &cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
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/* OSL_DELAY(1); */
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}
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tmp = R_REG(osh, &cc->jtagdr);
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return (tmp);
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}
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#endif
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/*
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* Interface to register chipc secondary isr
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*/
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bool
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BCMINITFN(sb_cc_register_isr) (sb_t * sbh, cc_isr_fn isr, uint32 ccintmask,
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void *cbdata) {
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bool done = FALSE;
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chipcregs_t *regs;
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uint origidx;
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uint i;
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/* Save the current core index */
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origidx = sb_coreidx(sbh);
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regs = sb_setcore(sbh, SB_CC, 0);
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ASSERT(regs);
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for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
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if (cc_isr_desc[i].isr == NULL) {
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cc_isr_desc[i].isr = isr;
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cc_isr_desc[i].cbdata = cbdata;
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cc_isr_desc[i].intmask = ccintmask;
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done = TRUE;
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break;
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}
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}
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if (done) {
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cc_intmask = R_REG(sb_osh(sbh), ®s->intmask);
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cc_intmask |= ccintmask;
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W_REG(sb_osh(sbh), ®s->intmask, cc_intmask);
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}
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/* restore original coreidx */
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sb_setcoreidx(sbh, origidx);
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return done;
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}
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/*
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* chipc primary interrupt handler
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*/
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void sb_cc_isr(sb_t * sbh, chipcregs_t * regs)
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{
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uint32 ccintstatus;
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uint32 intstatus;
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uint32 i;
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/* prior to rev 21 chipc interrupt means uart and gpio */
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if (sbh->ccrev >= 21)
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ccintstatus = R_REG(sb_osh(sbh), ®s->intstatus) & cc_intmask;
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else
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ccintstatus = (CI_UART | CI_GPIO);
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for (i = 0; i < MAX_CC_INT_SOURCE; i++) {
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if ((cc_isr_desc[i].isr != NULL) &&
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(intstatus = (cc_isr_desc[i].intmask & ccintstatus))) {
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(cc_isr_desc[i].isr) (cc_isr_desc[i].cbdata, intstatus);
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}
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}
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}
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