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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73
321 lines
6.7 KiB
C
321 lines
6.7 KiB
C
#ifndef __IDT_ETH_H__
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#define __IDT_ETH_H__
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/*******************************************************************************
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*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* Ethernet register definition.
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*
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* File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
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*
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* Author : Allen.Stichter@idt.com
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* Date : 20020605
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* Update :
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* $Log: eth.h,v $
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* Revision 1.3 2002/06/06 18:34:04 astichte
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* Added XXX_PhysicalAddress and XXX_VirtualAddress
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*
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* Revision 1.2 2002/06/05 18:19:46 astichte
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* Added
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*
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* Revision 1.1 2002/05/29 17:33:22 sysarch
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* jba File moved from vcode/include/idt/acacia
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*
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******************************************************************************/
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enum
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{
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ETH0_PhysicalAddress = 0x18060000,
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ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
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ETH0_VirtualAddress = 0xb8060000,
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ETH_VirtualAddress = ETH0_VirtualAddress, // Default
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} ;
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typedef struct
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{
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u32 ethintfc ;
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u32 ethfifott ;
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u32 etharc ;
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u32 ethhash0 ;
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u32 ethhash1 ;
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u32 ethu0 [4] ; // Reserved.
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u32 ethpfs ;
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u32 ethmcp ;
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u32 eth_u1 [10] ; // Reserved.
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u32 ethspare ;
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u32 eth_u2 [42] ; // Reserved.
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u32 ethsal0 ;
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u32 ethsah0 ;
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u32 ethsal1 ;
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u32 ethsah1 ;
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u32 ethsal2 ;
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u32 ethsah2 ;
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u32 ethsal3 ;
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u32 ethsah3 ;
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u32 ethrbc ;
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u32 ethrpc ;
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u32 ethrupc ;
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u32 ethrfc ;
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u32 ethtbc ;
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u32 ethgpf ;
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u32 eth_u9 [50] ; // Reserved.
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u32 ethmac1 ;
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u32 ethmac2 ;
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u32 ethipgt ;
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u32 ethipgr ;
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u32 ethclrt ;
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u32 ethmaxf ;
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u32 eth_u10 ; // Reserved.
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u32 ethmtest ;
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u32 miimcfg ;
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u32 miimcmd ;
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u32 miimaddr ;
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u32 miimwtd ;
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u32 miimrdd ;
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u32 miimind ;
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u32 eth_u11 ; // Reserved.
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u32 eth_u12 ; // Reserved.
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u32 ethcfsa0 ;
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u32 ethcfsa1 ;
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u32 ethcfsa2 ;
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} volatile *ETH_t;
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enum
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{
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ETHINTFC_en_b = 0,
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ETHINTFC_en_m = 0x00000001,
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ETHINTFC_its_b = 1,
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ETHINTFC_its_m = 0x00000002,
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ETHINTFC_rip_b = 2,
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ETHINTFC_rip_m = 0x00000004,
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ETHINTFC_jam_b = 3,
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ETHINTFC_jam_m = 0x00000008,
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ETHINTFC_ovr_b = 4,
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ETHINTFC_ovr_m = 0x00000010,
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ETHINTFC_und_b = 5,
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ETHINTFC_und_m = 0x00000020,
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ETHINTFC_iom_b = 6,
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ETHINTFC_iom_m = 0x000000c0,
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ETHFIFOTT_tth_b = 0,
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ETHFIFOTT_tth_m = 0x0000007f,
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ETHARC_pro_b = 0,
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ETHARC_pro_m = 0x00000001,
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ETHARC_am_b = 1,
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ETHARC_am_m = 0x00000002,
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ETHARC_afm_b = 2,
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ETHARC_afm_m = 0x00000004,
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ETHARC_ab_b = 3,
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ETHARC_ab_m = 0x00000008,
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ETHSAL_byte5_b = 0,
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ETHSAL_byte5_m = 0x000000ff,
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ETHSAL_byte4_b = 8,
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ETHSAL_byte4_m = 0x0000ff00,
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ETHSAL_byte3_b = 16,
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ETHSAL_byte3_m = 0x00ff0000,
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ETHSAL_byte2_b = 24,
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ETHSAL_byte2_m = 0xff000000,
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ETHSAH_byte1_b = 0,
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ETHSAH_byte1_m = 0x000000ff,
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ETHSAH_byte0_b = 8,
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ETHSAH_byte0_m = 0x0000ff00,
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ETHGPF_ptv_b = 0,
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ETHGPF_ptv_m = 0x0000ffff,
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ETHPFS_pfd_b = 0,
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ETHPFS_pfd_m = 0x00000001,
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ETHCFSA0_cfsa4_b = 0,
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ETHCFSA0_cfsa4_m = 0x000000ff,
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ETHCFSA0_cfsa5_b = 8,
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ETHCFSA0_cfsa5_m = 0x0000ff00,
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ETHCFSA1_cfsa2_b = 0,
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ETHCFSA1_cfsa2_m = 0x000000ff,
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ETHCFSA1_cfsa3_b = 8,
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ETHCFSA1_cfsa3_m = 0x0000ff00,
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ETHCFSA2_cfsa0_b = 0,
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ETHCFSA2_cfsa0_m = 0x000000ff,
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ETHCFSA2_cfsa1_b = 8,
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ETHCFSA2_cfsa1_m = 0x0000ff00,
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ETHMAC1_re_b = 0,
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ETHMAC1_re_m = 0x00000001,
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ETHMAC1_paf_b = 1,
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ETHMAC1_paf_m = 0x00000002,
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ETHMAC1_rfc_b = 2,
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ETHMAC1_rfc_m = 0x00000004,
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ETHMAC1_tfc_b = 3,
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ETHMAC1_tfc_m = 0x00000008,
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ETHMAC1_lb_b = 4,
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ETHMAC1_lb_m = 0x00000010,
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ETHMAC1_mr_b = 31,
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ETHMAC1_mr_m = 0x80000000,
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ETHMAC2_fd_b = 0,
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ETHMAC2_fd_m = 0x00000001,
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ETHMAC2_flc_b = 1,
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ETHMAC2_flc_m = 0x00000002,
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ETHMAC2_hfe_b = 2,
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ETHMAC2_hfe_m = 0x00000004,
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ETHMAC2_dc_b = 3,
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ETHMAC2_dc_m = 0x00000008,
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ETHMAC2_cen_b = 4,
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ETHMAC2_cen_m = 0x00000010,
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ETHMAC2_pe_b = 5,
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ETHMAC2_pe_m = 0x00000020,
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ETHMAC2_vpe_b = 6,
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ETHMAC2_vpe_m = 0x00000040,
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ETHMAC2_ape_b = 7,
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ETHMAC2_ape_m = 0x00000080,
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ETHMAC2_ppe_b = 8,
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ETHMAC2_ppe_m = 0x00000100,
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ETHMAC2_lpe_b = 9,
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ETHMAC2_lpe_m = 0x00000200,
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ETHMAC2_nb_b = 12,
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ETHMAC2_nb_m = 0x00001000,
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ETHMAC2_bp_b = 13,
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ETHMAC2_bp_m = 0x00002000,
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ETHMAC2_ed_b = 14,
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ETHMAC2_ed_m = 0x00004000,
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ETHIPGT_ipgt_b = 0,
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ETHIPGT_ipgt_m = 0x0000007f,
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ETHIPGR_ipgr2_b = 0,
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ETHIPGR_ipgr2_m = 0x0000007f,
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ETHIPGR_ipgr1_b = 8,
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ETHIPGR_ipgr1_m = 0x00007f00,
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ETHCLRT_maxret_b = 0,
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ETHCLRT_maxret_m = 0x0000000f,
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ETHCLRT_colwin_b = 8,
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ETHCLRT_colwin_m = 0x00003f00,
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ETHMAXF_maxf_b = 0,
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ETHMAXF_maxf_m = 0x0000ffff,
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ETHMTEST_tb_b = 2,
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ETHMTEST_tb_m = 0x00000004,
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ETHMCP_div_b = 0,
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ETHMCP_div_m = 0x000000ff,
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MIIMCFG_rsv_b = 0,
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MIIMCFG_rsv_m = 0x0000000c,
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MIIMCMD_rd_b = 0,
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MIIMCMD_rd_m = 0x00000001,
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MIIMCMD_scn_b = 1,
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MIIMCMD_scn_m = 0x00000002,
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MIIMADDR_regaddr_b = 0,
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MIIMADDR_regaddr_m = 0x0000001f,
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MIIMADDR_phyaddr_b = 8,
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MIIMADDR_phyaddr_m = 0x00001f00,
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MIIMWTD_wdata_b = 0,
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MIIMWTD_wdata_m = 0x0000ffff,
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MIIMRDD_rdata_b = 0,
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MIIMRDD_rdata_m = 0x0000ffff,
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MIIMIND_bsy_b = 0,
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MIIMIND_bsy_m = 0x00000001,
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MIIMIND_scn_b = 1,
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MIIMIND_scn_m = 0x00000002,
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MIIMIND_nv_b = 2,
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MIIMIND_nv_m = 0x00000004,
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} ;
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/*
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* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
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*/
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enum
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{
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ETHRX_fd_b = 0,
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ETHRX_fd_m = 0x00000001,
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ETHRX_ld_b = 1,
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ETHRX_ld_m = 0x00000002,
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ETHRX_rok_b = 2,
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ETHRX_rok_m = 0x00000004,
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ETHRX_fm_b = 3,
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ETHRX_fm_m = 0x00000008,
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ETHRX_mp_b = 4,
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ETHRX_mp_m = 0x00000010,
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ETHRX_bp_b = 5,
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ETHRX_bp_m = 0x00000020,
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ETHRX_vlt_b = 6,
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ETHRX_vlt_m = 0x00000040,
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ETHRX_cf_b = 7,
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ETHRX_cf_m = 0x00000080,
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ETHRX_ovr_b = 8,
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ETHRX_ovr_m = 0x00000100,
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ETHRX_crc_b = 9,
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ETHRX_crc_m = 0x00000200,
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ETHRX_cv_b = 10,
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ETHRX_cv_m = 0x00000400,
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ETHRX_db_b = 11,
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ETHRX_db_m = 0x00000800,
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ETHRX_le_b = 12,
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ETHRX_le_m = 0x00001000,
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ETHRX_lor_b = 13,
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ETHRX_lor_m = 0x00002000,
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ETHRX_ces_b = 14,
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ETHRX_ces_m = 0x00004000,
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ETHRX_length_b = 16,
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ETHRX_length_m = 0xffff0000,
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ETHTX_fd_b = 0,
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ETHTX_fd_m = 0x00000001,
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ETHTX_ld_b = 1,
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ETHTX_ld_m = 0x00000002,
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ETHTX_oen_b = 2,
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ETHTX_oen_m = 0x00000004,
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ETHTX_pen_b = 3,
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ETHTX_pen_m = 0x00000008,
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ETHTX_cen_b = 4,
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ETHTX_cen_m = 0x00000010,
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ETHTX_hen_b = 5,
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ETHTX_hen_m = 0x00000020,
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ETHTX_tok_b = 6,
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ETHTX_tok_m = 0x00000040,
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ETHTX_mp_b = 7,
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ETHTX_mp_m = 0x00000080,
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ETHTX_bp_b = 8,
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ETHTX_bp_m = 0x00000100,
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ETHTX_und_b = 9,
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ETHTX_und_m = 0x00000200,
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ETHTX_of_b = 10,
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ETHTX_of_m = 0x00000400,
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ETHTX_ed_b = 11,
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ETHTX_ed_m = 0x00000800,
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ETHTX_ec_b = 12,
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ETHTX_ec_m = 0x00001000,
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ETHTX_lc_b = 13,
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ETHTX_lc_m = 0x00002000,
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ETHTX_td_b = 14,
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ETHTX_td_m = 0x00004000,
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ETHTX_crc_b = 15,
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ETHTX_crc_m = 0x00008000,
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ETHTX_le_b = 16,
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ETHTX_le_m = 0x00010000,
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ETHTX_cc_b = 17,
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ETHTX_cc_m = 0x001E0000,
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} ;
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#endif // __IDT_ETH_H__
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