mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
73 lines
2.4 KiB
Diff
73 lines
2.4 KiB
Diff
From 9951cfc88b5d818391bebc7a56b678942b89721e Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 5 Jun 2011 23:38:45 +0200
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Subject: [PATCH 02/27] MIPS: ath79: Handle more MISC IRQs
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The AR724X SoCs have more IRQ sources hooked into the MISC IRQ controller.
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The patch adds support for them.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/2440/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/ath79/irq.c | 12 ++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++
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arch/mips/include/asm/mach-ath79/irq.h | 4 ++++
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3 files changed, 20 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsig
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else if (pending & MISC_INT_TIMER)
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generic_handle_irq(ATH79_MISC_IRQ_TIMER);
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+ else if (pending & MISC_INT_TIMER2)
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+ generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
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+
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+ else if (pending & MISC_INT_TIMER3)
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+ generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
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+
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+ else if (pending & MISC_INT_TIMER4)
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+ generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
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+
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else if (pending & MISC_INT_OHCI)
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generic_handle_irq(ATH79_MISC_IRQ_OHCI);
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@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsig
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else if (pending & MISC_INT_WDOG)
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generic_handle_irq(ATH79_MISC_IRQ_WDOG);
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+ else if (pending & MISC_INT_ETHSW)
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+ generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
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+
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else
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spurious_interrupt();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -130,6 +130,10 @@
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#define AR724X_RESET_REG_RESET_MODULE 0x1c
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+#define MISC_INT_ETHSW BIT(12)
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+#define MISC_INT_TIMER4 BIT(10)
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+#define MISC_INT_TIMER3 BIT(9)
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+#define MISC_INT_TIMER2 BIT(8)
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#define MISC_INT_DMA BIT(7)
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#define MISC_INT_OHCI BIT(6)
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#define MISC_INT_PERFC BIT(5)
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--- a/arch/mips/include/asm/mach-ath79/irq.h
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+++ b/arch/mips/include/asm/mach-ath79/irq.h
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@@ -30,6 +30,10 @@
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#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
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#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
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#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
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+#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
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+#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
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+#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
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+#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
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#include_next <irq.h>
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