mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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17c7b6c3fd
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73
145 lines
5.1 KiB
ArmAsm
145 lines
5.1 KiB
ArmAsm
#include "AT91RM9200_inc.h"
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/*---------------------------
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ARM Core Mode and Status Bits
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---------------------------*/
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.section start
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.text
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#define ARM_MODE_USER 0x10
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#define ARM_MODE_FIQ 0x11
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#define ARM_MODE_IRQ 0x12
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_ABORT 0x17
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#define ARM_MODE_UNDEF 0x1B
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#define ARM_MODE_SYS 0x1F
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#define I_BIT 0x80
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#define F_BIT 0x40
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#define T_BIT 0x20
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/*----------------------------------------------------------------------------
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Area Definition
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----------------
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Must be defined as function to put first in the code as it must be mapped
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at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
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_---------------------------------------------------------------------------*/
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.align 4
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.globl _start
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_start:
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/*----------------------------------------------------------------------------
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Exception vectors ( before Remap )
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------------------------------------
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These vectors are read at address 0.
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They absolutely requires to be in relative addresssing mode in order to
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guarantee a valid jump. For the moment, all are just looping (what may be
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dangerous in a final system). If an exception occurs before remap, this
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would result in an infinite loop.
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----------------------------------------------------------------------------*/
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b reset /* reset */
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b undefvec /* Undefined Instruction */
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b swivec /* Software Interrupt */
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b pabtvec /* Prefetch Abort */
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b dabtvec /* Data Abort */
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b rsvdvec /* reserved */
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b aicvec /* IRQ : read the AIC */
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b fiqvec /* FIQ */
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undefvec:
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swivec:
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pabtvec:
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dabtvec:
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rsvdvec:
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aicvec:
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fiqvec:
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b undefvec
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reset:
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#define MEMEND 0x00004000
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/* ----------------------------
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Setup the stack for each mode
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---------------------------- */
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#define IRQ_STACK_SIZE 0x10
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#define FIQ_STACK_SIZE 0x04
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#define ABT_STACK_SIZE 0x04
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#define UND_STACK_SIZE 0x04
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#define SVC_STACK_SIZE 0x10
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#define USER_STACK_SIZE 0x400
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ldr r0,= MEMEND
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/*- Set up Supervisor Mode and set Supervisor Mode Stack*/
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msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT
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mov r13, r0 /* Init stack Undef*/
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sub r0, r0, #SVC_STACK_SIZE
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/*- Set up Interrupt Mode and set IRQ Mode Stack*/
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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mov r13, r0 /* Init stack IRQ*/
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sub r0, r0, #IRQ_STACK_SIZE
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/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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mov r13, r0 /* Init stack FIQ*/
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sub r0, r0, #FIQ_STACK_SIZE
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/*- Set up Abort Mode and set Abort Mode Stack*/
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msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT
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mov r13, r0 /* Init stack Abort*/
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sub r0, r0, #ABT_STACK_SIZE
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/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/
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msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT
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mov r13, r0 /* Init stack Undef*/
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sub r0, r0, #UND_STACK_SIZE
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/*- Set up user Mode and set System Mode Stack*/
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msr CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT
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bic r0, r0, #3 /* Insure word alignement */
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mov sp, r0 /* Init stack System */
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ldr r0, = AT91F_LowLevelInit
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mov lr, pc
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bx r0
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/*----------------------------------------
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Read/modify/write CP15 control register
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----------------------------------------*/
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mrc p15, 0, r0, c1, c0,0 /* read cp15 control registre (cp15 r1) in r0 */
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ldr r3,= 0xC0000080 /* Reset bit :Little Endian end fast bus mode */
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ldr r4,= 0xC0001000 /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */
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bic r0, r0, r3
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orr r0, r0, r4
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mcr p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */
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/* Enable interrupts */
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msr CPSR_c, #ARM_MODE_SYS | F_BIT
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/*------------------------------------------------------------------------------
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- Branch on C code Main function (with interworking)
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----------------------------------------------------
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- Branch must be performed by an interworking call as either an ARM or Thumb
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- _start function must be supported. This makes the code not position-
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- independent. A Branch with link would generate errors
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----------------------------------------------------------------------------*/
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/*- Branch to _start by interworking*/
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ldr r4, = main
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mov lr, pc
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bx r4
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/*-----------------------------------------------------------------------------
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- Loop for ever
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---------------
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- End of application. Normally, never occur.
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- Could jump on Software Reset ( B 0x0 ).
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------------------------------------------------------------------------------*/
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End:
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b End
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