mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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ced0222eb7
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20610 3c298f89-4303-0410-b956-a3cf2f4a3e73
620 lines
15 KiB
C
620 lines
15 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Thomas Langer, Ralph Hempel
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/addrspace.h>
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#include <asm/ar9.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_HTTPD)
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#include <httpd.h>
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#endif
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extern ulong ifx_get_ddr_hz(void);
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extern ulong ifx_get_cpuclk(void);
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/* definitions for external PHYs / Switches */
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/* Split values into phy address and register address */
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#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
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/* IDs and registers of known external switches */
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#define ID_SAMURAI_0 0x1020
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#define ID_SAMURAI_1 0x0007
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#define SAMURAI_ID_REG0 0xA0
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#define SAMURAI_ID_REG1 0xA1
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#define ID_TANTOS 0x2599
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#define RGMII_MODE 0
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#define MII_MODE 1
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#define REV_MII_MODE 2
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#define RED_MII_MODE_IC 3 /*Input clock */
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#define RGMII_MODE_100MB 4
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#define TURBO_REV_MII_MODE 6 /*Turbo Rev Mii mode */
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#define RED_MII_MODE_OC 7 /*Output clock */
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#define RGMII_MODE_10MB 8
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#define mdelay(n) udelay((n)*1000)
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static void ar9_sw_chip_init(u8 port, u8 mode);
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static void ar9_enable_sw_port(u8 port, u8 state);
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static void ar9_configure_sw_port(u8 port, u8 mode);
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static u16 ar9_smi_reg_read(u16 reg);
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static u16 ar9_smi_reg_write(u16 reg, u16 data);
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static char * const name = "lq_cpe_eth";
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static int external_switch_init(void);
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void _machine_restart(void)
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{
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*AR9_RCU_RST_REQ |= AR9_RST_ALL;
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}
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#ifdef CONFIG_SYS_RAMBOOT
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phys_size_t initdram(int board_type)
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{
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return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
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}
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#elif defined(CONFIG_USE_DDR_RAM)
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phys_size_t initdram(int board_type)
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{
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return (CONFIG_SYS_MAX_RAM);
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}
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#else
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static ulong max_sdram_size(void) /* per Chip Select */
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{
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/* The only supported SDRAM data width is 16bit.
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*/
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#define CFG_DW 4
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/* The only supported number of SDRAM banks is 4.
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*/
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#define CFG_NB 4
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ulong cfgpb0 = *AR9_SDRAM_MC_CFGPB0;
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int cols = cfgpb0 & 0xF;
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int rows = (cfgpb0 & 0xF0) >> 4;
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ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
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return size;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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static long int dram_size(long int *base, long int maxsize)
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{
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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phys_size_t initdram(int board_type)
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{
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int rows, cols, best_val = *AR9_SDRAM_MC_CFGPB0;
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ulong size, max_size = 0;
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ulong our_address;
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/* load t9 into our_address */
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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* find out whether running from DRAM or Flash.
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*/
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if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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for (cols = 0x8; cols <= 0xC; cols++)
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{
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for (rows = 0xB; rows <= 0xD; rows++)
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{
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*AR9_SDRAM_MC_CFGPB0 = (0x14 << 8) |
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(rows << 4) | cols;
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size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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max_sdram_size());
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if (size > max_size)
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{
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best_val = *AR9_SDRAM_MC_CFGPB0;
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max_size = size;
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}
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}
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}
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*AR9_SDRAM_MC_CFGPB0 = best_val;
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return max_size;
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}
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#endif
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int checkboard (void)
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{
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unsigned long chipid = *AR9_MPS_CHIPID;
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int part_num;
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puts ("Board: ");
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part_num = AR9_MPS_CHIPID_PARTNUM_GET(chipid);
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switch (part_num)
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{
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case 0x16C:
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puts("ARX188 ");
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break;
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case 0x16D:
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puts("ARX168 ");
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break;
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case 0x16F:
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puts("ARX182 ");
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break;
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case 0x170:
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puts("GRX188 ");
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break;
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case 0x171:
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puts("GRX168 ");
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break;
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default:
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printf ("unknown, chip part number 0x%03X ", part_num);
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break;
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}
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printf ("V1.%ld, ", AR9_MPS_CHIPID_VERSION_GET(chipid));
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printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
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printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
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return 0;
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}
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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int board_early_init_f(void)
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{
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#ifdef CONFIG_EBU_ADDSEL0
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(*AR9_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
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#endif
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#ifdef CONFIG_EBU_ADDSEL1
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(*AR9_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
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#endif
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#ifdef CONFIG_EBU_ADDSEL2
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(*AR9_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
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#endif
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#ifdef CONFIG_EBU_ADDSEL3
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(*AR9_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
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#endif
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#ifdef CONFIG_EBU_BUSCON0
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(*AR9_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
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#endif
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#ifdef CONFIG_EBU_BUSCON1
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(*AR9_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
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#endif
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#ifdef CONFIG_EBU_BUSCON2
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(*AR9_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
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#endif
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#ifdef CONFIG_EBU_BUSCON3
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(*AR9_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
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#endif
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return 0;
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_IFX_ETOP)
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*AR9_PMU_PWDCR &= 0xFFFFEFDF;
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*AR9_PMU_PWDCR &= ~AR9_PMU_DMA; /* enable DMA from PMU */
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if (lq_eth_initialize(bis) < 0)
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return -1;
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*AR9_RCU_RST_REQ |= 1;
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udelay(200000);
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*AR9_RCU_RST_REQ &= (unsigned long)~1;
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udelay(1000);
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#ifdef CONFIG_EXTRA_SWITCH
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if (external_switch_init()<0)
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return -1;
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#endif /* CONFIG_EXTRA_SWITCH */
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#endif /* CONFIG_IFX_ETOP */
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return 0;
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}
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static void ar9_configure_sw_port(u8 port, u8 mode)
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{
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if(port)
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{
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if (mode == 1) //MII mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0xf000)) | 0x2000;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x2000;
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}
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else if(mode == 2 || mode == 6) //Rev Mii mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xf000);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xf000);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0xf000)) & ~0x2000;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xd000;
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}
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}
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else //Port 0
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{
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if (mode == 1) //MII mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR & ~(0x0303)) | 0x0100;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0100;
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}
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else if(mode ==2 || mode ==6) //Rev Mii mode
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{
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0x0303);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0x0303);
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*AR9_GPIO_P2_DIR = (*AR9_GPIO_P2_DIR | (0x0303)) & ~0x0100;
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0x0203;
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}
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}
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}
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/*
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Call this function to place either MAC port 0 or 1 into working mode.
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Parameters:
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port - select ports 0 or 1.
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state of interface : state
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0: RGMII
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1: MII
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2: Rev MII
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3: Reduce MII (input clock)
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4: RGMII 100mb
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5: Reserve
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6: Turbo Rev MII
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7: Reduce MII (output clock)
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*/
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void ar9_enable_sw_port(u8 port, u8 state)
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{
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REG32(AR9_SW_GCTL0) |= 0x80000000;
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if (port == 0)
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{
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REG32(AR9_SW_RGMII_CTL) &= 0xffcffc0e ;
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//#if AR9_REFBOARD_TANTOS
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REG32(0xbf20302c) &= 0xffff81ff;
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REG32(0xbf20302c) |= 4<<9 ;
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//#endif
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REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<8;
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if((state &0x3) == 0)
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{
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REG32(AR9_SW_RGMII_CTL) &= 0xfffffff3;
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if(state == 4)
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REG32(AR9_SW_RGMII_CTL) |= 0x4;
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else
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REG32(AR9_SW_RGMII_CTL) |= 0x8;
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}
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if(state == 6)
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REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<20));
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if(state == 7)
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REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<21));
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}
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// *AR9_PPE32_ETOP_CFG = *AR9_PPE32_ETOP_CFG & 0xfffffffe;
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else
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{
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REG32(AR9_SW_RGMII_CTL) &= 0xff303fff ;
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REG32(AR9_SW_RGMII_CTL) |= ((u32)(state &0x3))<<18;
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if((state &0x3) == 0)
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{
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REG32(AR9_SW_RGMII_CTL) &= 0xffffcfff;
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if(state == 4)
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REG32(AR9_SW_RGMII_CTL) |= 0x1000;
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else
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REG32(AR9_SW_RGMII_CTL) |= 0x2000;
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}
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if(state == 6)
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REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<22));
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if(state == 7)
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REG32(AR9_SW_RGMII_CTL) |= ((u32) (1<<23));
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}
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}
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void pci_reset(void)
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{
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int i,j;
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#define AR9_V1_PCI_RST_FIX 1
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#if AR9_V1_PCI_RST_FIX // 5th June 2008 Add GPIO19 to control EJTAG_TRST
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*AR9_GPIO_P1_ALTSEL0 = *AR9_GPIO_P1_ALTSEL0 & ~0x8;
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*AR9_GPIO_P1_ALTSEL1 = *AR9_GPIO_P1_ALTSEL1 & ~0x8;
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*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR | 0x8;
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*AR9_GPIO_P1_OD = *AR9_GPIO_P1_OD | 0x8;
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*AR9_GPIO_P1_OUT = *AR9_GPIO_P1_OUT | 0x8;
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*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 & ~0x4000;
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*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~0x4000;
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*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | 0x4000;
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*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | 0x4000;
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for(j=0;j<5;j++) {
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*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT & ~0x4000;
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for(i=0;i<0x10000;i++);
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*AR9_GPIO_P0_OUT = *AR9_GPIO_P0_OUT | 0x4000;
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for(i=0;i<0x10000;i++);
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}
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*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR & ~0x4000;
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*AR9_GPIO_P1_DIR = *AR9_GPIO_P1_DIR & ~0x8;
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#endif
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}
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static u16 ar9_smi_reg_read(u16 reg)
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{
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int i;
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while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
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REG32(AR9_SW_MDIO_CTL) = 0x8000| 0x2<<10 | ((u32) (reg&0x3ff)) ; /*0x10=MDIO_OP_READ*/
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for(i=0;i<0x3fff;i++);
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udelay(50);
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while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
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return((u16) (REG32(AR9_SW_MDIO_DATA)));
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}
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static u16 ar9_smi_reg_write(u16 reg, u16 data)
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{
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int i;
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while(REG32(AR9_SW_MDIO_CTL) & 0x8000);
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REG32(AR9_SW_MDIO_CTL) = 0x8000| (((u32) data)<<16) | 0x01<<10 | ((u32) (reg&0x3ff)) ; /*0x01=MDIO_OP_WRITE*/
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for(i=0;i<0x3fff;i++);
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udelay(50);
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return 0;
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}
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static void ar9_sw_chip_init(u8 port, u8 mode)
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{
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int i;
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u16 chipid;
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debug("\nsearching for switches ... ");
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asm("sync");
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pci_reset();
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/* 25mhz clock out */
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*AR9_CGU_IFCCR &= ~(3<<10);
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*AR9_GPIO_P0_ALTSEL0 = *AR9_GPIO_P0_ALTSEL0 | (1<<3);
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*AR9_GPIO_P0_ALTSEL1 = *AR9_GPIO_P0_ALTSEL1 & ~(1<<3);
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*AR9_GPIO_P0_DIR = *AR9_GPIO_P0_DIR | (1<<3);
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*AR9_GPIO_P0_OD = *AR9_GPIO_P0_OD | (1<<3);
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*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 & ~(1<<0);
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*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(1<<0);
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*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | (1<<0);
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*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | (1<<0);
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*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & 0xFFFBDFDF) ;
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*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR & ~(AR9_PMU_DMA | AR9_PMU_SWITCH));
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*AR9_PMU_PWDCR = (*AR9_PMU_PWDCR | AR9_PMU_USB0 | AR9_PMU_USB0_P);
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*AR9_GPIO_P2_OUT &= ~(1<<0);
|
||
asm("sync");
|
||
|
||
ar9_configure_sw_port(port, mode);
|
||
ar9_enable_sw_port(port, mode);
|
||
REG32(AR9_SW_P0_CTL) |= 0x400000; /* disable mdio polling for tantos */
|
||
asm("sync");
|
||
|
||
/*GPIO 55(P3.7) used as output, set high*/
|
||
*AR9_GPIO_P3_OD |=(1<<7);
|
||
*AR9_GPIO_P3_DIR |= (1<<7);
|
||
*AR9_GPIO_P3_ALTSEL0 &=~(1<<7);
|
||
*AR9_GPIO_P3_ALTSEL1 &=~(1<<7);
|
||
asm("sync");
|
||
udelay(10);
|
||
|
||
*AR9_GPIO_P3_OUT &= ~(1<<7);
|
||
for(i=0;i<1000;i++)
|
||
udelay(110);
|
||
*AR9_GPIO_P3_OUT |=(1<<7);
|
||
udelay(100);
|
||
|
||
if(port==0)
|
||
REG32(AR9_SW_P0_CTL) |= 0x40001;
|
||
else
|
||
REG32(AR9_SW_P1_CTL) |= 0x40001;
|
||
|
||
REG32(AR9_SW_P2_CTL) |= 0x40001;
|
||
REG32(AR9_SW_PMAC_HD_CTL) |= 0x40000; /* enable CRC */
|
||
|
||
*AR9_GPIO_P2_ALTSEL0 = *AR9_GPIO_P2_ALTSEL0 | (0xc00);
|
||
*AR9_GPIO_P2_ALTSEL1 = *AR9_GPIO_P2_ALTSEL1 & ~(0xc00);
|
||
*AR9_GPIO_P2_DIR = *AR9_GPIO_P2_DIR | 0xc00;
|
||
*AR9_GPIO_P2_OD = *AR9_GPIO_P2_OD | 0xc00;
|
||
|
||
asm("sync");
|
||
chipid = (unsigned short)(ar9_smi_reg_read(0x101));
|
||
printf("\nswitch chip id=%08x\n",chipid);
|
||
if (chipid != ID_TANTOS) {
|
||
debug("whatever detected\n");
|
||
ar9_smi_reg_write(0x1,0x840f);
|
||
ar9_smi_reg_write(0x3,0x840f);
|
||
ar9_smi_reg_write(0x5,0x840f);
|
||
ar9_smi_reg_write(0x7,0x840f);
|
||
ar9_smi_reg_write(0x8,0x840f);
|
||
ar9_smi_reg_write(0x12,0x3602);
|
||
#ifdef CLK_OUT2_25MHZ
|
||
ar9_smi_reg_write(0x33,0x4000);
|
||
#endif
|
||
} else { // Tantos switch ship
|
||
debug("Tantos switch detected\n");
|
||
ar9_smi_reg_write(0xa1,0x0004); /*port 5 force link up*/
|
||
ar9_smi_reg_write(0xc1,0x0004); /*port 6 force link up*/
|
||
ar9_smi_reg_write(0xf5,0x0BBB); /*port 4 duplex mode, flow control enable,1000Mbit/s*/
|
||
/*port 5 duplex mode, flow control enable, 1000Mbit/s*/
|
||
/*port 6 duplex mode, flow control enable, 1000Mbit/s*/
|
||
}
|
||
asm("sync");
|
||
|
||
/*reset GPHY*/
|
||
mdelay(200);
|
||
*AR9_RCU_RST_REQ |= (AR9_RCU_RST_REQ_DMA | AR9_RCU_RST_REQ_PPE) ;
|
||
udelay(50);
|
||
*AR9_GPIO_P2_OUT |= (1<<0);
|
||
}
|
||
|
||
static void ar9_dma_init(void)
|
||
{
|
||
/* select port */
|
||
*AR9_DMA_PS = 0;
|
||
|
||
/*
|
||
TXWGT 14:12 rw Port Weight for Transmit Direction (the default value <20>001<30>)
|
||
|
||
TXENDI 11:10 rw Endianness for Transmit Direction
|
||
Determine a byte swap between memory interface (left hand side) and
|
||
peripheral interface (right hand side).
|
||
00B B0_B1_B2_B3 No byte switching
|
||
01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
|
||
10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
|
||
|
||
RXENDI 9:8 rw Endianness for Receive Direction
|
||
Determine a byte swap between peripheral (left hand side) and memory
|
||
interface (right hand side).
|
||
00B B0_B1_B2_B3 No byte switching
|
||
01B B1_B0_B3_B2 B0B1B2B3 => B1B0B3B2
|
||
10B B2_B3_B0_B1 B0B1B2B3 => B2B3B0B1
|
||
11B B3_B2_B1_B0 B0B1B2B3 => B3B2B1B0
|
||
|
||
TXBL 5:4 rw Burst Length for Transmit Direction
|
||
Selects burst length for TX direction.
|
||
Others are reserved and will result in 2_WORDS burst length.
|
||
01B 2_WORDS 2 words
|
||
10B 4_WORDS 4 words
|
||
11B 8_WORDS 8 words
|
||
|
||
RXBL 3:2 rw Burst Length for Receive Direction
|
||
Selects burst length for RX direction.
|
||
Others are reserved and will result in 2_WORDS burst length.
|
||
01B 2_WORDS 2 words
|
||
10B 4_WORDS 4 words
|
||
11B 8_WORDS 8 words
|
||
*/
|
||
*AR9_DMA_PCTRL = 0x1f28;
|
||
}
|
||
|
||
#ifdef CONFIG_EXTRA_SWITCH
|
||
static int external_switch_init(void)
|
||
{
|
||
ar9_sw_chip_init(0, RGMII_MODE);
|
||
|
||
ar9_dma_init();
|
||
|
||
return 0;
|
||
}
|
||
#endif /* CONFIG_EXTRA_SWITCH */
|
||
|
||
#if defined(CONFIG_CMD_HTTPD)
|
||
int do_http_upgrade(const unsigned char *data, const ulong size)
|
||
{
|
||
char buf[128];
|
||
|
||
if(getenv ("ram_addr") == NULL)
|
||
return -1;
|
||
if(getenv ("kernel_addr") == NULL)
|
||
return -1;
|
||
/* check the image */
|
||
if(run_command("imi ${ram_addr}", 0) < 0) {
|
||
return -1;
|
||
}
|
||
/* write the image to the flash */
|
||
puts("http ugrade ...\n");
|
||
sprintf(buf, "era ${kernel_addr} +0x%x; cp.b ${ram_addr} ${kernel_addr} 0x%x", size, size);
|
||
return run_command(buf, 0);
|
||
}
|
||
|
||
int do_http_progress(const int state)
|
||
{
|
||
/* toggle LED's here */
|
||
switch(state) {
|
||
case HTTP_PROGRESS_START:
|
||
puts("http start\n");
|
||
break;
|
||
case HTTP_PROGRESS_TIMEOUT:
|
||
puts(".");
|
||
break;
|
||
case HTTP_PROGRESS_UPLOAD_READY:
|
||
puts("http upload ready\n");
|
||
break;
|
||
case HTTP_PROGRESS_UGRADE_READY:
|
||
puts("http ugrade ready\n");
|
||
break;
|
||
case HTTP_PROGRESS_UGRADE_FAILED:
|
||
puts("http ugrade failed\n");
|
||
break;
|
||
}
|
||
return 0;
|
||
}
|
||
|
||
unsigned long do_http_tmp_address(void)
|
||
{
|
||
char *s = getenv ("ram_addr");
|
||
if (s) {
|
||
ulong tmp = simple_strtoul (s, NULL, 16);
|
||
return tmp;
|
||
}
|
||
return 0 /*0x80a00000*/;
|
||
}
|
||
|
||
#endif
|