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git://projects.qi-hardware.com/openwrt-xburst.git
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05c930e80a
attention: if caches enabled the network is broken attention: the network of the flash image doesn't work because of enabled caches git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20606 3c298f89-4303-0410-b956-a3cf2f4a3e73
402 lines
9.6 KiB
C
402 lines
9.6 KiB
C
/*
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* Lantiq CPE device ethernet driver.
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* Supposed to work on Twinpass/Danube.
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*
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* Based on INCA-IP driver:
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Thomas Langer, Ralph Hempel
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <config.h>
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#include "ifx_etop.h"
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#if defined(CONFIG_AR9)
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#define TX_CHAN_NO 1
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#define RX_CHAN_NO 0
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#else
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#define TX_CHAN_NO 7
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#define RX_CHAN_NO 6
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#endif
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 8
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#define TOUT_LOOP 100
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typedef struct
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{
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union
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{
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struct
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{
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volatile u32 OWN :1;
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 reserved :3;
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volatile u32 Byteoffset :2;
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volatile u32 reserve :7;
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volatile u32 DataLen :16;
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}field;
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volatile u32 word;
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}status;
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volatile u32 DataPtr;
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} dma_rx_descriptor_t;
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typedef struct
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{
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union
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{
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struct
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{
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volatile u32 OWN :1;
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 Byteoffset :5;
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volatile u32 reserved :7;
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volatile u32 DataLen :16;
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}field;
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volatile u32 word;
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}status;
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volatile u32 DataPtr;
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} dma_tx_descriptor_t;
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static volatile dma_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
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static volatile dma_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
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static int tx_num, rx_num;
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static volatile IfxDMA_t *pDma = (IfxDMA_t *)CKSEG1ADDR(DANUBE_DMA_BASE);
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static int lq_eth_init(struct eth_device *dev, bd_t * bis);
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static int lq_eth_send(struct eth_device *dev, volatile void *packet,int length);
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static int lq_eth_recv(struct eth_device *dev);
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static void lq_eth_halt(struct eth_device *dev);
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static void lq_eth_init_chip(void);
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static void lq_eth_init_dma(void);
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static int lq_eth_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
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{
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u32 timeout = 50000;
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u32 phy, reg;
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if ((phyAddr > 0x1F) || (regAddr > 0x1F) || (retVal == NULL))
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return -1;
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phy = (phyAddr & 0x1F) << 21;
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reg = (regAddr & 0x1F) << 16;
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*ETOP_MDIO_ACC = 0xC0000000 | phy | reg;
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while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
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udelay(10);
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if (timeout==0) {
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*retVal = 0;
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return -1;
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}
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*retVal = *ETOP_MDIO_ACC & 0xFFFF;
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return 0;
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}
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static int lq_eth_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data)
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{
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u32 timeout = 50000;
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u32 phy, reg;
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if ((phyAddr > 0x1F) || (regAddr > 0x1F))
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return -1;
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phy = (phyAddr & 0x1F) << 21;
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reg = (regAddr & 0x1F) << 16;
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*ETOP_MDIO_ACC = 0x80000000 | phy | reg | data;
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while ((timeout--) && (*ETOP_MDIO_ACC & 0x80000000))
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udelay(10);
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if (timeout==0)
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return -1;
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return 0;
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}
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int lq_eth_initialize(bd_t * bis)
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{
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struct eth_device *dev;
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debug("Entered lq_eth_initialize()\n");
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if (!(dev = malloc (sizeof *dev))) {
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printf("Failed to allocate memory\n");
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return -1;
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}
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memset(dev, 0, sizeof(*dev));
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sprintf(dev->name, "lq_cpe_eth");
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dev->init = lq_eth_init;
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dev->halt = lq_eth_halt;
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dev->send = lq_eth_send;
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dev->recv = lq_eth_recv;
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eth_register(dev);
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#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
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/* register mii command access routines */
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miiphy_register(dev->name,
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lq_eth_miiphy_read, lq_eth_miiphy_write);
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#endif
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lq_eth_init_dma();
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lq_eth_init_chip();
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return 0;
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}
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static int lq_eth_init(struct eth_device *dev, bd_t * bis)
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{
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int i;
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uchar *enetaddr = dev->enetaddr;
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debug("lq_eth_init %x:%x:%x:%x:%x:%x\n",
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enetaddr[0], enetaddr[1], enetaddr[2], enetaddr[3], enetaddr[4], enetaddr[5]);
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*ENET_MAC_DA0 = (enetaddr[0]<<24) + (enetaddr[1]<<16) + (enetaddr[2]<< 8) + enetaddr[3];
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*ENET_MAC_DA1 = (enetaddr[4]<<24) + (enetaddr[5]<<16);
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*ENETS_CFG |= 1<<28; /* enable filter for unicast packets */
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tx_num=0;
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rx_num=0;
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for(i=0;i < NUM_RX_DESC; i++) {
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dma_rx_descriptor_t * rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[i]);
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rx_desc->status.word=0;
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rx_desc->status.field.OWN=1;
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rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
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rx_desc->DataPtr=(u32)CKSEG1ADDR(NetRxPackets[i]);
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NetRxPackets[i][0] = 0xAA;
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}
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/* Reset DMA */
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dma_writel(dma_cs, RX_CHAN_NO);
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dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
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dma_writel(dma_cpoll, 0x80000040);
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/*set descriptor base*/
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dma_writel(dma_cdba, (u32)rx_des_ring);
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dma_writel(dma_cdlen, NUM_RX_DESC);
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dma_writel(dma_cie, 0);
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dma_writel(dma_cctrl, 0x30000);
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for(i=0;i < NUM_TX_DESC; i++) {
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dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[i]);
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memset(tx_desc, 0, sizeof(tx_des_ring[0]));
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}
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dma_writel(dma_cs, TX_CHAN_NO);
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dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
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dma_writel(dma_cpoll, 0x80000040);
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dma_writel(dma_cdba, (u32)tx_des_ring);
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dma_writel(dma_cdlen, NUM_TX_DESC);
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dma_writel(dma_cie, 0);
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dma_writel(dma_cctrl, 0x30100);
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/* turn on DMA rx & tx channel
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*/
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dma_writel(dma_cs, RX_CHAN_NO);
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dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1); /*reset and turn on the channel*/
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return 0;
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}
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static void lq_eth_halt(struct eth_device *dev)
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{
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int i;
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debug("lq_eth_halt()\n");
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for(i=0;i<8;i++) {
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dma_writel(dma_cs, i);
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dma_writel(dma_cctrl, dma_readl(dma_cctrl) & ~1);/*stop the dma channel*/
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}
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}
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#ifdef DEBUG
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static void lq_dump(const u8 *data, const u32 length)
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{
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u32 i;
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debug("\n");
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for(i=0;i<length;i++) {
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debug("%02x ", data[i]);
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}
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debug("\n");
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}
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#endif
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static int lq_eth_send(struct eth_device *dev, volatile void *packet, int length)
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{
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int i;
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int res = -1;
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volatile dma_tx_descriptor_t * tx_desc = (dma_tx_descriptor_t *)CKSEG1ADDR(&tx_des_ring[tx_num]);
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if (length <= 0) {
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printf ("%s: bad packet size: %d\n", dev->name, length);
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goto Done;
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}
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for(i=0; tx_desc->status.field.OWN==1; i++) {
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if (i>=TOUT_LOOP) {
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printf("NO Tx Descriptor...");
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goto Done;
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}
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}
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tx_desc->status.field.Sop=1;
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tx_desc->status.field.Eop=1;
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tx_desc->status.field.C=0;
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tx_desc->DataPtr = (u32)CKSEG1ADDR(packet);
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if (length<60)
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tx_desc->status.field.DataLen = 60;
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else
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tx_desc->status.field.DataLen = (u32)length;
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flush_cache((u32)packet, tx_desc->status.field.DataLen);
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asm("SYNC");
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tx_desc->status.field.OWN=1;
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res=length;
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tx_num++;
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if (tx_num==NUM_TX_DESC) tx_num=0;
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#ifdef DEBUG
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lq_dump(tx_desc->DataPtr, tx_desc->status.field.DataLen);
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#endif
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dma_writel(dma_cs, TX_CHAN_NO);
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if (!(dma_readl(dma_cctrl) & 1)) {
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dma_writel(dma_cctrl, dma_readl(dma_cctrl) | 1);
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}
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Done:
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return res;
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}
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static int lq_eth_recv(struct eth_device *dev)
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{
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int length = 0;
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volatile dma_rx_descriptor_t * rx_desc;
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rx_desc = (dma_rx_descriptor_t *)CKSEG1ADDR(&rx_des_ring[rx_num]);
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if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) {
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return 0;
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}
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debug("rx");
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#ifdef DEBUG
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lq_dump(rx_desc->DataPtr, rx_desc->status.field.DataLen);
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#endif
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length = rx_desc->status.field.DataLen;
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if (length > 4) {
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invalidate_dcache_range((u32)CKSEG0ADDR(rx_desc->DataPtr), (u32) CKSEG0ADDR(rx_desc->DataPtr) + length);
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NetReceive(NetRxPackets[rx_num], length);
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} else {
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printf("ERROR: Invalid rx packet length.\n");
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}
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rx_desc->status.field.Sop=0;
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rx_desc->status.field.Eop=0;
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rx_desc->status.field.C=0;
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rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
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rx_desc->status.field.OWN=1;
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rx_num++;
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if (rx_num == NUM_RX_DESC)
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rx_num=0;
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return length;
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}
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static void lq_eth_init_chip(void)
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{
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*ETOP_MDIO_CFG &= ~0x6;
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*ENET_MAC_CFG = 0x187;
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// turn on port0, set to rmii and turn off port1.
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#ifdef CONFIG_RMII
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*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x0000000A;
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#else
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*ETOP_CFG = (*ETOP_CFG & 0xFFFFFFFC) | 0x00000008;
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#endif
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*ETOP_IG_PLEN_CTRL = 0x004005EE; // set packetlen.
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*ENET_MAC_CFG |= 1<<11; /*enable the crc*/
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return;
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}
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static void lq_eth_init_dma(void)
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{
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/* Reset DMA */
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dma_writel(dma_ctrl, dma_readl(dma_ctrl) | 1);
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dma_writel(dma_irnen, 0);/*disable all the interrupts first*/
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/* Clear Interrupt Status Register */
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dma_writel(dma_irncr, 0xfffff);
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/*disable all the dma interrupts*/
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dma_writel(dma_irnen, 0);
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/*disable channel 0 and channel 1 interrupts*/
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dma_writel(dma_cs, RX_CHAN_NO);
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dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
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dma_writel(dma_cpoll, 0x80000040);
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/*set descriptor base*/
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dma_writel(dma_cdba, (u32)rx_des_ring);
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dma_writel(dma_cdlen, NUM_RX_DESC);
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dma_writel(dma_cie, 0);
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dma_writel(dma_cctrl, 0x30000);
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dma_writel(dma_cs, TX_CHAN_NO);
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dma_writel(dma_cctrl, 0x2);/*fix me, need to reset this channel first?*/
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dma_writel(dma_cpoll, 0x80000040);
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dma_writel(dma_cdba, (u32)tx_des_ring);
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dma_writel(dma_cdlen, NUM_TX_DESC);
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dma_writel(dma_cie, 0);
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dma_writel(dma_cctrl, 0x30100);
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/*enable the poll function and set the poll counter*/
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//dma_writel(DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
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/*set port properties, enable endian conversion for switch*/
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dma_writel(dma_ps, 0);
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dma_writel(dma_pctrl, dma_readl(dma_pctrl) | (0xf<<8));/*enable 32 bit endian conversion*/
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return;
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}
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