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git://projects.qi-hardware.com/openwrt-xburst.git
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fb189822fc
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15918 3c298f89-4303-0410-b956-a3cf2f4a3e73
516 lines
12 KiB
C
516 lines
12 KiB
C
/*
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* HDQ generic GPIO bitbang driver using FIQ
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*
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* (C) 2006-2007 by Openmoko, Inc.
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* Author: Andy Green <andy@openmoko.com>
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/hdq.h>
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#define HDQ_READ 0
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#define HDQ_WRITE 0x80
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enum hdq_bitbang_states {
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HDQB_IDLE = 0,
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HDQB_TX_BREAK,
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HDQB_TX_BREAK_RECOVERY,
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HDQB_ADS_CALC,
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HDQB_ADS_LOW,
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HDQB_ADS_HIGH,
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HDQB_WAIT_RX,
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HDQB_DATA_RX_LOW,
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HDQB_DATA_RX_HIGH,
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HDQB_WAIT_TX,
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};
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static struct hdq_priv {
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u8 hdq_probed; /* nonzero after HDQ driver probed */
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struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */
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unsigned long hdq_gpio_pin; /* GTA02 = GPD14 which pin to meddle with */
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u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */
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u8 hdq_tx_data; /* data to tx for write action */
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u8 hdq_rx_data; /* data received in read action */
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u8 hdq_request_ctr; /* incremented by "user" to request a transfer */
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u8 hdq_transaction_ctr; /* incremented after each transfer */
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u8 hdq_error; /* 0 = no error */
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u8 hdq_ctr;
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u8 hdq_ctr2;
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u8 hdq_bit;
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u8 hdq_shifter;
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u8 hdq_tx_data_done;
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enum hdq_bitbang_states hdq_state;
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int reported_error;
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struct hdq_platform_data *pdata;
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} hdq_priv;
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static void hdq_bad(void)
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{
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if (!hdq_priv.reported_error)
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printk(KERN_ERR "HDQ error: %d\n", hdq_priv.hdq_error);
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hdq_priv.reported_error = 1;
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}
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static void hdq_good(void)
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{
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if (hdq_priv.reported_error)
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printk(KERN_INFO "HDQ responds again\n");
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hdq_priv.reported_error = 0;
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}
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int hdq_fiq_handler(void)
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{
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if (!hdq_priv.hdq_probed)
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return 0;
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switch (hdq_priv.hdq_state) {
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case HDQB_IDLE:
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if (hdq_priv.hdq_request_ctr == hdq_priv.hdq_transaction_ctr)
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break;
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hdq_priv.hdq_ctr = 250 / HDQ_SAMPLE_PERIOD_US;
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hdq_priv.pdata->gpio_set(0);
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hdq_priv.pdata->gpio_dir_out();
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hdq_priv.hdq_tx_data_done = 0;
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hdq_priv.hdq_state = HDQB_TX_BREAK;
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break;
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case HDQB_TX_BREAK: /* issue low for > 190us */
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if (--hdq_priv.hdq_ctr == 0) {
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hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
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hdq_priv.hdq_state = HDQB_TX_BREAK_RECOVERY;
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hdq_priv.pdata->gpio_set(1);
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}
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break;
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case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */
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if (--hdq_priv.hdq_ctr)
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break;
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hdq_priv.hdq_shifter = hdq_priv.hdq_ads;
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hdq_priv.hdq_bit = 8; /* 8 bits of ads / rw */
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hdq_priv.hdq_tx_data_done = 0; /* doing ads */
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/* fallthru on last one */
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case HDQB_ADS_CALC:
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if (hdq_priv.hdq_shifter & 1)
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hdq_priv.hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US;
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else
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hdq_priv.hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US;
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/* carefully precompute the other phase length */
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hdq_priv.hdq_ctr2 = (210 - (hdq_priv.hdq_ctr * HDQ_SAMPLE_PERIOD_US)) /
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HDQ_SAMPLE_PERIOD_US;
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hdq_priv.hdq_state = HDQB_ADS_LOW;
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hdq_priv.hdq_shifter >>= 1;
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hdq_priv.hdq_bit--;
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hdq_priv.pdata->gpio_set(0);
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break;
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case HDQB_ADS_LOW:
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if (--hdq_priv.hdq_ctr)
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break;
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hdq_priv.pdata->gpio_set(1);
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hdq_priv.hdq_state = HDQB_ADS_HIGH;
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break;
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case HDQB_ADS_HIGH:
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if (--hdq_priv.hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */
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break;
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if (hdq_priv.hdq_bit) { /* more bits to do */
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hdq_priv.hdq_state = HDQB_ADS_CALC;
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break;
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}
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/* no more bits, wait it out until hdq_priv.hdq_ctr2 exhausted */
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if (hdq_priv.hdq_ctr2)
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break;
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/* ok no more bits and very last state */
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hdq_priv.hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
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/* FIXME 0 = read */
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if (hdq_priv.hdq_ads & 0x80) { /* write the byte out */
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/* set delay before payload */
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hdq_priv.hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
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/* already high, no need to write */
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hdq_priv.hdq_state = HDQB_WAIT_TX;
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break;
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}
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/* read the next byte */
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hdq_priv.hdq_bit = 8; /* 8 bits of data */
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hdq_priv.hdq_ctr = 2500 / HDQ_SAMPLE_PERIOD_US;
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hdq_priv.hdq_state = HDQB_WAIT_RX;
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hdq_priv.pdata->gpio_dir_in();
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break;
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case HDQB_WAIT_TX: /* issue low for > 40us */
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if (--hdq_priv.hdq_ctr)
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break;
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if (!hdq_priv.hdq_tx_data_done) { /* was that the data sent? */
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hdq_priv.hdq_tx_data_done++;
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hdq_priv.hdq_shifter = hdq_priv.hdq_tx_data;
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hdq_priv.hdq_bit = 8; /* 8 bits of data */
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hdq_priv.hdq_state = HDQB_ADS_CALC; /* start sending */
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break;
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}
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hdq_priv.hdq_error = 0;
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hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
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hdq_priv.hdq_state = HDQB_IDLE; /* all tx is done */
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/* idle in input mode, it's pulled up by 10K */
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hdq_priv.pdata->gpio_dir_in();
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break;
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case HDQB_WAIT_RX: /* wait for battery to talk to us */
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if (hdq_priv.pdata->gpio_get() == 0) {
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/* it talks to us! */
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hdq_priv.hdq_ctr2 = 1;
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hdq_priv.hdq_bit = 8; /* 8 bits of data */
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/* timeout */
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hdq_priv.hdq_ctr = 500 / HDQ_SAMPLE_PERIOD_US;
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hdq_priv.hdq_state = HDQB_DATA_RX_LOW;
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break;
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}
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if (--hdq_priv.hdq_ctr == 0) { /* timed out, error */
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hdq_priv.hdq_error = 1;
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hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
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hdq_priv.hdq_state = HDQB_IDLE; /* abort */
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}
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break;
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/*
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* HDQ basically works by measuring the low time of the bit cell
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* 32-50us --> '1', 80 - 145us --> '0'
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*/
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case HDQB_DATA_RX_LOW:
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if (hdq_priv.pdata->gpio_get()) {
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hdq_priv.hdq_rx_data >>= 1;
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if (hdq_priv.hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US))
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hdq_priv.hdq_rx_data |= 0x80;
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if (--hdq_priv.hdq_bit == 0) {
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hdq_priv.hdq_error = 0;
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hdq_priv.hdq_transaction_ctr =
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hdq_priv.hdq_request_ctr;
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hdq_priv.hdq_state = HDQB_IDLE;
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} else
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hdq_priv.hdq_state = HDQB_DATA_RX_HIGH;
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/* timeout */
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hdq_priv.hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US;
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hdq_priv.hdq_ctr2 = 1;
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break;
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}
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hdq_priv.hdq_ctr2++;
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if (--hdq_priv.hdq_ctr)
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break;
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/* timed out, error */
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hdq_priv.hdq_error = 2;
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hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
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hdq_priv.hdq_state = HDQB_IDLE; /* abort */
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break;
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case HDQB_DATA_RX_HIGH:
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if (!hdq_priv.pdata->gpio_get()) {
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/* it talks to us! */
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hdq_priv.hdq_ctr2 = 1;
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/* timeout */
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hdq_priv.hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US;
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hdq_priv.hdq_state = HDQB_DATA_RX_LOW;
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break;
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}
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if (--hdq_priv.hdq_ctr)
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break;
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/* timed out, error */
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hdq_priv.hdq_error = 3;
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hdq_priv.hdq_transaction_ctr = hdq_priv.hdq_request_ctr;
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/* we're in input mode already */
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hdq_priv.hdq_state = HDQB_IDLE; /* abort */
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break;
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}
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/* Are we interested in keeping the FIQ source alive ? */
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if (hdq_priv.hdq_state != HDQB_IDLE)
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return 1;
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else
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return 0;
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}
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static int fiq_busy(void)
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{
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int request = (volatile u8)hdq_priv.hdq_request_ctr;
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int transact = (volatile u8)hdq_priv.hdq_transaction_ctr;
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return (request != transact);
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}
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int hdq_initialized(void)
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{
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return hdq_priv.hdq_probed;
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}
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EXPORT_SYMBOL_GPL(hdq_initialized);
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int hdq_read(int address)
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{
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int count_sleeps = 5;
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int ret = -ETIME;
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if (!hdq_priv.hdq_probed)
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return -EINVAL;
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mutex_lock(&hdq_priv.hdq_lock);
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hdq_priv.hdq_error = 0;
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hdq_priv.hdq_ads = address | HDQ_READ;
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hdq_priv.hdq_request_ctr++;
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hdq_priv.pdata->kick_fiq();
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/*
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* FIQ takes care of it while we block our calling process
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* But we're not spinning -- other processes run normally while
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* we wait for the result
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*/
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while (count_sleeps--) {
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msleep(10); /* valid transaction always completes in < 10ms */
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if (fiq_busy())
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continue;
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if (hdq_priv.hdq_error) {
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hdq_bad();
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goto done; /* didn't see a response in good time */
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}
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hdq_good();
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ret = hdq_priv.hdq_rx_data;
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goto done;
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}
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done:
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mutex_unlock(&hdq_priv.hdq_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(hdq_read);
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int hdq_write(int address, u8 data)
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{
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int count_sleeps = 5;
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int ret = -ETIME;
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if (!hdq_priv.hdq_probed)
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return -EINVAL;
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mutex_lock(&hdq_priv.hdq_lock);
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hdq_priv.hdq_error = 0;
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hdq_priv.hdq_ads = address | HDQ_WRITE;
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hdq_priv.hdq_tx_data = data;
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hdq_priv.hdq_request_ctr++;
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hdq_priv.pdata->kick_fiq();
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/*
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* FIQ takes care of it while we block our calling process
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* But we're not spinning -- other processes run normally while
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* we wait for the result
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*/
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while (count_sleeps--) {
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msleep(10); /* valid transaction always completes in < 10ms */
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if (fiq_busy())
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continue; /* something bad with FIQ */
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if (hdq_priv.hdq_error) {
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hdq_bad();
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goto done; /* didn't see a response in good time */
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}
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hdq_good();
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ret = 0;
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goto done;
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}
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done:
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mutex_unlock(&hdq_priv.hdq_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(hdq_write);
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/* sysfs */
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static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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int n;
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int v;
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u8 u8a[128]; /* whole address space for HDQ */
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char *end = buf;
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if (!hdq_priv.hdq_probed)
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return -EINVAL;
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/* the dump does not take care about 16 bit regs, because at this
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* bus level we don't know about the chip details
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*/
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for (n = 0; n < sizeof(u8a); n++) {
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v = hdq_read(n);
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if (v < 0)
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goto bail;
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u8a[n] = v;
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}
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for (n = 0; n < sizeof(u8a); n += 16) {
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hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0);
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end += strlen(end);
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*end++ = '\n';
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*end = '\0';
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}
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return (end - buf);
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bail:
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return sprintf(buf, "ERROR %d\n", v);
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}
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/* you write by <address> <data>, eg, "34 128" */
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#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
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static ssize_t hdq_sysfs_write(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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const char *end = buf + count;
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int address = atoi(buf);
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if (!hdq_priv.hdq_probed)
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return -EINVAL;
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while ((buf != end) && (*buf != ' '))
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buf++;
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if (buf >= end)
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return 0;
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while ((buf < end) && (*buf == ' '))
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buf++;
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if (buf >= end)
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return 0;
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hdq_write(address, atoi(buf));
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return count;
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}
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static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL);
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static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write);
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static struct attribute *hdq_sysfs_entries[] = {
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&dev_attr_dump.attr,
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&dev_attr_write.attr,
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NULL
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};
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static struct attribute_group hdq_attr_group = {
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.name = "hdq",
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.attrs = hdq_sysfs_entries,
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};
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#ifdef CONFIG_PM
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static int hdq_suspend(struct platform_device *pdev, pm_message_t state)
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{
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/* after 18s of this, the battery monitor will also go to sleep */
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hdq_priv.pdata->gpio_dir_in();
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hdq_priv.pdata->disable_fiq();
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return 0;
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}
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static int hdq_resume(struct platform_device *pdev)
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{
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hdq_priv.pdata->gpio_set(1);
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hdq_priv.pdata->gpio_dir_out();
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hdq_priv.pdata->enable_fiq();
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return 0;
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}
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#endif
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static int __init hdq_probe(struct platform_device *pdev)
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{
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struct resource *r = platform_get_resource(pdev, 0, 0);
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int ret;
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struct hdq_platform_data *pdata = pdev->dev.platform_data;
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if (!r || !pdata)
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return -EINVAL;
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platform_set_drvdata(pdev, NULL);
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mutex_init(&hdq_priv.hdq_lock);
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/* set our HDQ comms pin from the platform data */
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hdq_priv.hdq_gpio_pin = r->start;
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hdq_priv.pdata = pdata;
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hdq_priv.pdata->gpio_set(1);
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hdq_priv.pdata->gpio_dir_out();
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/* Initialize FIQ */
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if (hdq_priv.pdata->enable_fiq() < 0) {
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dev_err(&pdev->dev, "Could not enable FIQ source\n");
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return -EINVAL;
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}
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ret = sysfs_create_group(&pdev->dev.kobj, &hdq_attr_group);
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if (ret)
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return ret;
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hdq_priv.hdq_probed = 1; /* we are ready to do stuff now */
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/*
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* if wanted, users can defer registration of devices
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* that depend on HDQ until after we register, and can use our
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* device as parent so suspend-resume ordering is correct
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*/
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if (pdata->attach_child_devices)
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(pdata->attach_child_devices)(&pdev->dev);
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hdq_priv.pdata = pdata;
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return 0;
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}
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static int hdq_remove(struct platform_device *pdev)
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{
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sysfs_remove_group(&pdev->dev.kobj, &hdq_attr_group);
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return 0;
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}
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static struct platform_driver hdq_driver = {
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.probe = hdq_probe,
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.remove = hdq_remove,
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#ifdef CONFIG_PM
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.suspend = hdq_suspend,
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.resume = hdq_resume,
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#endif
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.driver = {
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.name = "hdq",
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},
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};
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static int __init hdq_init(void)
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{
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return platform_driver_register(&hdq_driver);
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}
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static void __exit hdq_exit(void)
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{
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platform_driver_unregister(&hdq_driver);
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}
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|
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module_init(hdq_init);
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module_exit(hdq_exit);
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|
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MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
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MODULE_DESCRIPTION("HDQ driver");
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