mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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8e7007124a
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14635 3c298f89-4303-0410-b956-a3cf2f4a3e73
292 lines
6.2 KiB
C
292 lines
6.2 KiB
C
/*
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* Atheros AR71xx SoC specific setup
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/serial_8250.h>
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#include <linux/bootmem.h>
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#include <asm/bootinfo.h>
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#include <asm/traps.h>
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/reboot.h> /* for _machine_{restart,halt} */
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#include <asm/mips_machine.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#include "devices.h"
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#define AR71XX_SYS_TYPE_LEN 64
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#define AR71XX_BASE_FREQ 40000000
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#define AR91XX_BASE_FREQ 5000000
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unsigned long ar71xx_mach_type;
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u32 ar71xx_cpu_freq;
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EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
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u32 ar71xx_ahb_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
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u32 ar71xx_ddr_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
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enum ar71xx_soc_type ar71xx_soc;
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EXPORT_SYMBOL_GPL(ar71xx_soc);
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int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
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struct ar71xx_pci_irq *map) __initdata;
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int (*ar71xx_pci_be_handler)(int is_fixup);
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static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
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static void ar71xx_restart(char *command)
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{
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ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
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for (;;)
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if (cpu_wait)
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cpu_wait();
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}
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static void ar71xx_halt(void)
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{
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while (1)
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cpu_wait();
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}
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static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int err = 0;
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if (ar71xx_pci_be_handler)
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err = ar71xx_pci_be_handler(is_fixup);
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return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
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}
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int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
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{
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if (!ar71xx_pci_bios_init)
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return 0;
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return ar71xx_pci_bios_init(nr_irqs, map);
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}
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static void __init ar71xx_detect_mem_size(void)
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{
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unsigned long size;
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for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
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size <<= 1 ) {
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if (!memcmp(ar71xx_detect_mem_size,
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ar71xx_detect_mem_size + size, 1024))
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break;
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}
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add_memory_region(0, size, BOOT_MEM_RAM);
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}
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static void __init ar71xx_detect_sys_type(void)
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{
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char *chip;
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u32 id;
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u32 rev;
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id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
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rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
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switch (id & REV_ID_CHIP_MASK) {
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case REV_ID_CHIP_AR7130:
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ar71xx_soc = AR71XX_SOC_AR7130;
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chip = "7130";
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break;
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case REV_ID_CHIP_AR7141:
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ar71xx_soc = AR71XX_SOC_AR7141;
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chip = "7141";
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break;
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case REV_ID_CHIP_AR7161:
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ar71xx_soc = AR71XX_SOC_AR7161;
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chip = "7161";
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break;
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case REV_ID_CHIP_AR9130:
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ar71xx_soc = AR71XX_SOC_AR9130;
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chip = "9130";
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break;
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case REV_ID_CHIP_AR9132:
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ar71xx_soc = AR71XX_SOC_AR9132;
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chip = "9132";
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break;
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default:
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panic("ar71xx: unknown chip id:0x%02x\n", id);
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}
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
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chip, rev, id);
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}
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static void __init ar91xx_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
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freq = div * AR91XX_BASE_FREQ;
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ar71xx_cpu_freq = freq;
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div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init ar71xx_detect_sys_frequency(void)
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{
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u32 pll;
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u32 freq;
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u32 div;
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pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
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freq = div * AR71XX_BASE_FREQ;
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div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
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ar71xx_cpu_freq = freq / div;
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div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
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ar71xx_ddr_freq = freq / div;
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div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
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ar71xx_ahb_freq = ar71xx_cpu_freq / div;
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}
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static void __init detect_sys_frequency(void)
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{
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ar71xx_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ar91xx_detect_sys_frequency();
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break;
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default:
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BUG();
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}
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}
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#ifdef CONFIG_AR71XX_EARLY_SERIAL
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static void __init ar71xx_early_serial_setup(void)
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{
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struct uart_port p;
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memset(&p, 0, sizeof(p));
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p.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
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p.iotype = UPIO_MEM32;
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p.uartclk = ar71xx_ahb_freq;
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p.irq = AR71XX_MISC_IRQ_UART;
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p.regshift = 2;
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p.mapbase = AR71XX_UART_BASE;
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early_serial_setup(&p);
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}
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#else
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static inline void ar71xx_early_serial_setup(void) {};
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#endif /* CONFIG_AR71XX_EARLY_SERIAL */
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const char *get_system_type(void)
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{
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return ar71xx_sys_type;
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}
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unsigned int __cpuinit get_c0_compare_irq(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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void __init plat_mem_setup(void)
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{
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set_io_port_base(KSEG1);
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ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
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AR71XX_DDR_CTRL_SIZE);
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ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
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AR71XX_PLL_SIZE);
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ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
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AR71XX_RESET_SIZE);
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ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
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ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
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AR71XX_USB_CTRL_SIZE);
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ar71xx_detect_mem_size();
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ar71xx_detect_sys_type();
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detect_sys_frequency();
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printk(KERN_INFO
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"%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
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ar71xx_sys_type,
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ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
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ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
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ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
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_machine_restart = ar71xx_restart;
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_machine_halt = ar71xx_halt;
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pm_power_off = ar71xx_halt;
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board_be_handler = ar71xx_be_handler;
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ar71xx_early_serial_setup();
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}
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void __init plat_time_init(void)
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{
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mips_hpt_frequency = ar71xx_cpu_freq / 2;
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}
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static int __init ar71xx_machine_setup(void)
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{
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ar71xx_gpio_init();
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ar71xx_add_device_uart();
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ar71xx_add_device_wdt();
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mips_machine_setup(ar71xx_mach_type);
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return 0;
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}
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arch_initcall(ar71xx_machine_setup);
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