mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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796a9d1091
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15242 3c298f89-4303-0410-b956-a3cf2f4a3e73
390 lines
14 KiB
C
390 lines
14 KiB
C
/*
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* Broadcom SiliconBackplane hardware register definitions.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _SBCONFIG_H
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#define _SBCONFIG_H
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#include "linuxver.h"
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif
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/*
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* SiliconBackplane Address Map.
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* All regions may not exist on all chips.
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*/
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#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
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#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
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#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
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#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
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#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
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#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
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#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
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#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
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#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
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#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
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#define SB_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
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#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
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#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
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#define SB_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
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#define SB_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
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#define SB_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
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#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
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#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
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#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
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#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
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#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
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* (2 ZettaBytes), low 32 bits
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*/
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#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
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* (2 ZettaBytes), high 32 bits
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*/
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#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
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#define SB_LED (SB_EXTIF_BASE + 0x00900000)
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/* enumeration space related defs */
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#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
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#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
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#define SB_MAXFUNCS 4 /* max. # functions per core */
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#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
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#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
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/* mips address */
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#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
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/*
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* Sonics Configuration Space Registers.
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*/
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#define SBIPSFLAG 0x08
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#define SBTPSFLAG 0x18
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#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
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#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
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#define SBADMATCH3 0x60
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#define SBADMATCH2 0x68
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#define SBADMATCH1 0x70
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#define SBIMSTATE 0x90
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#define SBINTVEC 0x94
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#define SBTMSTATELOW 0x98
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#define SBTMSTATEHIGH 0x9c
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#define SBBWA0 0xa0
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#define SBIMCONFIGLOW 0xa8
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#define SBIMCONFIGHIGH 0xac
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#define SBADMATCH0 0xb0
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#define SBTMCONFIGLOW 0xb8
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#define SBTMCONFIGHIGH 0xbc
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#define SBBCONFIG 0xc0
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#define SBBSTATE 0xc8
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#define SBACTCNFG 0xd8
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#define SBFLAGST 0xe8
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#define SBIDLOW 0xf8
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#define SBIDHIGH 0xfc
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/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
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* a few registers *below* that line. I think it would be very confusing to try
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* and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
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*/
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#define SBIMERRLOGA 0xea8
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#define SBIMERRLOG 0xeb0
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#define SBTMPORTCONNID0 0xed8
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#define SBTMPORTLOCK0 0xef8
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#ifndef _LANGUAGE_ASSEMBLY
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typedef volatile struct _sbconfig {
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uint32 PAD[2];
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uint32 sbipsflag; /* initiator port ocp slave flag */
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uint32 PAD[3];
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uint32 sbtpsflag; /* target port ocp slave flag */
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uint32 PAD[11];
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uint32 sbtmerrloga; /* (sonics >= 2.3) */
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uint32 PAD;
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uint32 sbtmerrlog; /* (sonics >= 2.3) */
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uint32 PAD[3];
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uint32 sbadmatch3; /* address match3 */
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uint32 PAD;
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uint32 sbadmatch2; /* address match2 */
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uint32 PAD;
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uint32 sbadmatch1; /* address match1 */
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uint32 PAD[7];
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uint32 sbimstate; /* initiator agent state */
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uint32 sbintvec; /* interrupt mask */
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uint32 sbtmstatelow; /* target state */
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uint32 sbtmstatehigh; /* target state */
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uint32 sbbwa0; /* bandwidth allocation table0 */
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uint32 PAD;
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uint32 sbimconfiglow; /* initiator configuration */
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uint32 sbimconfighigh; /* initiator configuration */
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uint32 sbadmatch0; /* address match0 */
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uint32 PAD;
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uint32 sbtmconfiglow; /* target configuration */
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uint32 sbtmconfighigh; /* target configuration */
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uint32 sbbconfig; /* broadcast configuration */
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uint32 PAD;
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uint32 sbbstate; /* broadcast state */
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uint32 PAD[3];
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uint32 sbactcnfg; /* activate configuration */
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uint32 PAD[3];
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uint32 sbflagst; /* current sbflags */
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uint32 PAD[3];
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uint32 sbidlow; /* identification */
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uint32 sbidhigh; /* identification */
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} sbconfig_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* sbipsflag */
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#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
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#define SBIPS_INT1_SHIFT 0
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#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
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#define SBIPS_INT2_SHIFT 8
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#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
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#define SBIPS_INT3_SHIFT 16
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#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
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#define SBIPS_INT4_SHIFT 24
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/* sbtpsflag */
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#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
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#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
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/* sbtmerrlog */
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#define SBTMEL_CM 0x00000007 /* command */
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#define SBTMEL_CI 0x0000ff00 /* connection id */
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#define SBTMEL_EC 0x0f000000 /* error code */
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#define SBTMEL_ME 0x80000000 /* multiple error */
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/* sbimstate */
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#define SBIM_PC 0xf /* pipecount */
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#define SBIM_AP_MASK 0x30 /* arbitration policy */
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#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
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#define SBIM_AP_TS 0x10 /* use timesliaces only */
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#define SBIM_AP_TK 0x20 /* use token only */
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#define SBIM_AP_RSV 0x30 /* reserved */
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#define SBIM_IBE 0x20000 /* inbanderror */
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#define SBIM_TO 0x40000 /* timeout */
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#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
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#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
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/* sbtmstatelow */
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#define SBTML_RESET 0x1 /* reset */
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#define SBTML_REJ_MASK 0x6 /* reject */
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#define SBTML_REJ_SHIFT 1
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#define SBTML_CLK 0x10000 /* clock enable */
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#define SBTML_FGC 0x20000 /* force gated clocks on */
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#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
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#define SBTML_PE 0x40000000 /* pme enable */
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#define SBTML_BE 0x80000000 /* bist enable */
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/* sbtmstatehigh */
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#define SBTMH_SERR 0x1 /* serror */
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#define SBTMH_INT 0x2 /* interrupt */
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#define SBTMH_BUSY 0x4 /* busy */
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#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
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#define SBTMH_FL_MASK 0x0fff0000 /* core-specific flags */
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#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
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#define SBTMH_GCR 0x20000000 /* gated clock request */
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#define SBTMH_BISTF 0x40000000 /* bist failed */
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#define SBTMH_BISTD 0x80000000 /* bist done */
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/* sbbwa0 */
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#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
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#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
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#define SBBWA_TAB1_SHIFT 16
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/* sbimconfiglow */
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#define SBIMCL_STO_MASK 0x7 /* service timeout */
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#define SBIMCL_RTO_MASK 0x70 /* request timeout */
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#define SBIMCL_RTO_SHIFT 4
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#define SBIMCL_CID_MASK 0xff0000 /* connection id */
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#define SBIMCL_CID_SHIFT 16
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/* sbimconfighigh */
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#define SBIMCH_IEM_MASK 0xc /* inband error mode */
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#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
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#define SBIMCH_TEM_SHIFT 4
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#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
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#define SBIMCH_BEM_SHIFT 6
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/* sbadmatch0 */
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#define SBAM_TYPE_MASK 0x3 /* address type */
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#define SBAM_AD64 0x4 /* reserved */
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#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
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#define SBAM_ADINT0_SHIFT 3
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#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
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#define SBAM_ADINT1_SHIFT 3
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#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
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#define SBAM_ADINT2_SHIFT 3
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#define SBAM_ADEN 0x400 /* enable */
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#define SBAM_ADNEG 0x800 /* negative decode */
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#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
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#define SBAM_BASE0_SHIFT 8
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#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
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#define SBAM_BASE1_SHIFT 12
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#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
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#define SBAM_BASE2_SHIFT 16
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/* sbtmconfiglow */
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#define SBTMCL_CD_MASK 0xff /* clock divide */
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#define SBTMCL_CO_MASK 0xf800 /* clock offset */
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#define SBTMCL_CO_SHIFT 11
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#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
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#define SBTMCL_IF_SHIFT 18
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#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
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#define SBTMCL_IM_SHIFT 24
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/* sbtmconfighigh */
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#define SBTMCH_BM_MASK 0x3 /* busy mode */
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#define SBTMCH_RM_MASK 0x3 /* retry mode */
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#define SBTMCH_RM_SHIFT 2
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#define SBTMCH_SM_MASK 0x30 /* stop mode */
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#define SBTMCH_SM_SHIFT 4
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#define SBTMCH_EM_MASK 0x300 /* sb error mode */
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#define SBTMCH_EM_SHIFT 8
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#define SBTMCH_IM_MASK 0xc00 /* int mode */
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#define SBTMCH_IM_SHIFT 10
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/* sbbconfig */
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#define SBBC_LAT_MASK 0x3 /* sb latency */
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#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
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#define SBBC_MAX0_SHIFT 16
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#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
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#define SBBC_MAX1_SHIFT 20
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/* sbbstate */
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#define SBBS_SRD 0x1 /* st reg disable */
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#define SBBS_HRD 0x2 /* hold reg disable */
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/* sbidlow */
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#define SBIDL_CS_MASK 0x3 /* config space */
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#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
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#define SBIDL_AR_SHIFT 3
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#define SBIDL_SYNCH 0x40 /* sync */
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#define SBIDL_INIT 0x80 /* initiator */
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#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
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#define SBIDL_MINLAT_SHIFT 8
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#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
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#define SBIDL_MAXLAT_SHIFT 12
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#define SBIDL_FIRST 0x10000 /* this initiator is first */
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#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
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#define SBIDL_CW_SHIFT 18
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#define SBIDL_TP_MASK 0xf00000 /* target ports */
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#define SBIDL_TP_SHIFT 20
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#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
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#define SBIDL_IP_SHIFT 24
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#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
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#define SBIDL_RV_SHIFT 28
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#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
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#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
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/* sbidhigh */
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#define SBIDH_RC_MASK 0x000f /* revision code */
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#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
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#define SBIDH_RCE_SHIFT 8
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#define SBCOREREV(sbidh) \
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((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
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#define SBIDH_CC_MASK 0x8ff0 /* core code */
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#define SBIDH_CC_SHIFT 4
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#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
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#define SBIDH_VC_SHIFT 16
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#define SB_COMMIT 0xfd8 /* update buffered registers value */
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/* vendor codes */
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#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
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/* core codes */
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#define SB_NODEV 0x700 /* Invalid coreid */
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#define SB_CC 0x800 /* chipcommon core */
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#define SB_ILINE20 0x801 /* iline20 core */
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#define SB_SDRAM 0x803 /* sdram core */
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#define SB_PCI 0x804 /* pci core */
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#define SB_MIPS 0x805 /* mips core */
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#define SB_ENET 0x806 /* enet mac core */
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#define SB_CODEC 0x807 /* v90 codec core */
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#define SB_USB 0x808 /* usb 1.1 host/device core */
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#define SB_ADSL 0x809 /* ADSL core */
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#define SB_ILINE100 0x80a /* iline100 core */
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#define SB_IPSEC 0x80b /* ipsec core */
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#define SB_PCMCIA 0x80d /* pcmcia core */
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#define SB_SOCRAM 0x80e /* internal memory core */
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#define SB_MEMC 0x80f /* memc sdram core */
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#define SB_EXTIF 0x811 /* external interface core */
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#define SB_D11 0x812 /* 802.11 MAC core */
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#define SB_MIPS33 0x816 /* mips3302 core */
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#define SB_USB11H 0x817 /* usb 1.1 host core */
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#define SB_USB11D 0x818 /* usb 1.1 device core */
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#define SB_USB20H 0x819 /* usb 2.0 host core */
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#define SB_USB20D 0x81a /* usb 2.0 device core */
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#define SB_SDIOH 0x81b /* sdio host core */
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#define SB_ROBO 0x81c /* roboswitch core */
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#define SB_ATA100 0x81d /* parallel ATA core */
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#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
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#define SB_GIGETH 0x81f /* gigabit ethernet core */
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#define SB_PCIE 0x820 /* pci express core */
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#define SB_MIMO 0x821 /* MIMO phy core */
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#define SB_SRAMC 0x822 /* SRAM controller core */
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#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
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#define SB_ARM7S 0x825 /* ARM7tdmi-s core */
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#define SB_SDIOD 0x829 /* SDIO device core */
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#define SB_ARMCM3 0x82a /* ARM Cortex M3 core */
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#define SB_OCP 0x830 /* OCP2OCP bridge core */
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#define SB_SC 0x831 /* shared common core */
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#define SB_AHB 0x832 /* OCP2AHB bridge core */
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#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
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/* Not an enumeration space register, but common to all cores to
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* communicate w/PMU regarding Silicon Backplane clocking.
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*/
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#define SB_CLK_CTL_ST 0x1e0 /* clock control and status */
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/* clk_ctl_st register */
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#define CCS_FORCEALP 0x00000001 /* force ALP request */
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#define CCS_FORCEHT 0x00000002 /* force HT request */
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#define CCS_FORCEILP 0x00000004 /* force ILP request */
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#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
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#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
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#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
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#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
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#define CCS_HTAVAIL 0x00020000 /* HT is available */
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#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
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#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
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/* Not really related to Silicon Backplane, but a couple of software
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* conventions for the use the flash space:
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*/
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/* Minumum amount of flash we support */
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#define FLASH_MIN 0x00020000 /* Minimum flash size */
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/* A boot/binary may have an embedded block that describes its size */
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#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
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#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
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#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
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#define BISZ_TXTST_IDX 1 /* 1: text start */
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#define BISZ_TXTEND_IDX 2 /* 2: text end */
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#define BISZ_DATAST_IDX 3 /* 3: data start */
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#define BISZ_DATAEND_IDX 4 /* 4: data end */
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#define BISZ_BSSST_IDX 5 /* 5: bss start */
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#define BISZ_BSSEND_IDX 6 /* 6: bss end */
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#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
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#endif /* _SBCONFIG_H */
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