mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 14:14:36 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27539 3c298f89-4303-0410-b956-a3cf2f4a3e73
969 lines
31 KiB
Diff
969 lines
31 KiB
Diff
--- a/configure.in
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+++ b/configure.in
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@@ -956,14 +956,15 @@ AC_DEFINE([VMMC],[1],[enable VMMC suppor
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AM_CONDITIONAL(DANUBE, false)
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AM_CONDITIONAL(AR9, false)
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AM_CONDITIONAL(VR9, false)
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+AM_CONDITIONAL(FALCON, false)
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AC_ARG_WITH(device,
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AC_HELP_STRING(
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- [--with-device=DANUBE|TWINPASS|AR9|VR9],
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+ [--with-device=DANUBE|TWINPASS|AR9|VR9|FALCON],
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[Set device type, default is DANUBE]
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),
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[
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if test "$withval" = yes; then
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- AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);
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+ AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);
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else
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case $withval in
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DANUBE)
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@@ -986,8 +987,13 @@ AC_ARG_WITH(device,
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AC_DEFINE([SYSTEM_VR9],[1],[enable VR9 specific code])
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AM_CONDITIONAL(VR9, true)
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;;
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+ FALCON)
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+ AC_MSG_RESULT(FALCON device is used);
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+ AC_DEFINE([SYSTEM_FALCON],[1],[enable FALCON specific code])
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+ AM_CONDITIONAL(FALCON, true)
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+ ;;
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*)
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- AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);
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+ AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);
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;;
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esac
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fi
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--- a/src/Makefile.am
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+++ b/src/Makefile.am
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@@ -70,6 +70,11 @@ drv_vmmc_SOURCES +=\
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mps/drv_mps_vmmc_ar9.c
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endif
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+if FALCON
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+drv_vmmc_SOURCES +=\
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+ mps/drv_mps_vmmc_falcon.c
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+endif
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+
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endif
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if PMC_SUPPORT
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--- a/drv_version.h
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+++ b/drv_version.h
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@@ -36,6 +36,10 @@
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#define MIN_FW_MAJORSTEP 2
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#define MIN_FW_MINORSTEP 1
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#define MIN_FW_HOTFIXSTEP 0
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+#elif defined(SYSTEM_FALCON)
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+#define MIN_FW_MAJORSTEP 0
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+#define MIN_FW_MINORSTEP 1
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+#define MIN_FW_HOTFIXSTEP 0
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#else
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#error unknown system
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#endif
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--- a/src/drv_vmmc_bbd.c
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+++ b/src/drv_vmmc_bbd.c
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@@ -34,6 +34,7 @@
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#define VMMC_WL_SDD_BASIC_CFG 0x04000400
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#define VMMC_WL_SDD_RING_CFG 0x04000500
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#define VMMC_WL_SDD_DCDC_CFG 0x04000C00
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+#define VMMC_WL_SDD_MWI_CFG 0x04000600
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#define IDLE_EXT_TOGGLE_SLEEP_MS 5
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@@ -52,6 +53,8 @@
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#define BBD_VMMC_MAGIC 0x41523921 /* "AR9" */
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#elif defined(SYSTEM_VR9)
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#define BBD_VMMC_MAGIC 0x56523921 /* "VR9" */
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+#elif defined(SYSTEM_FALCON)
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+#define BBD_VMMC_MAGIC 0x46414C43 /* "FALC" */
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#else
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#error system undefined
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#endif
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@@ -525,9 +528,6 @@ static IFX_int32_t VMMC_BBD_BlockHandler
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IFX_uint16_t slic_val;
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IFX_int32_t ret = IFX_SUCCESS;
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- TRACE(VMMC, DBG_LEVEL_LOW,
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- ("bbd block with tag 0x%04X passed\n", pBBDblock->tag));
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-
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/* for FXO line allowed blocks are FXO_CRAM and TRANSPARENT */
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if (pCh->pALM->line_type_fxs != IFX_TRUE)
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{
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@@ -686,6 +686,7 @@ static IFX_int32_t VMMC_BBD_BlockHandler
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break;
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}
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} /* if */
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+
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return ret;
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}
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@@ -1026,6 +1027,7 @@ static IFX_int32_t vmmc_BBD_WhiteListedC
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}
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case VMMC_WL_SDD_RING_CFG:
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case VMMC_WL_SDD_DCDC_CFG:
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+ case VMMC_WL_SDD_MWI_CFG:
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ret = CmdWrite (pCh->pParent, Msg.val, Msg.cmd.LENGTH);
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break;
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@@ -1068,7 +1070,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
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IFX_uint32_t countWords;
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IFX_uint32_t posBytes = 0;
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IFX_uint8_t lenBytes, *pByte;
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-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
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IFX_uint8_t padBytes = 0;
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#endif
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IFX_uint16_t cram_offset, cram_crc,
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@@ -1088,7 +1090,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
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#ifdef SYSTEM_DANUBE
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/* CMD1 is a COP command */
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pCmd[0] = (0x0200) | (pCh->nChannel - 1);
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-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
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/* SDD_Coef command */
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pCmd[0] = (0x0400) | (pCh->nChannel - 1);
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pCmd[1] = (0x0D00);
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@@ -1111,7 +1113,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
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pCmd[1] = ((cram_offset + (posBytes >> 1)) << 8);
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/* set CRAM data while taking care of endianess */
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cpb2w (&pCmd[2], &pByte[posBytes], lenBytes);
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-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
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/* calculate length to download (in words = 16bit),
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maximum allowed length for this message is 56 Bytes = 28 Words */
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if (countWords > ((MAX_CMD_WORD - CMD_HDR_CNT - 1)))
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@@ -1140,7 +1142,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
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/* write Data */
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#if defined SYSTEM_DANUBE
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ret = CmdWrite (pCh->pParent, (IFX_uint32_t *) pCmd, lenBytes);
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-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
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#if 1
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/* lenBytes + 2 bytes for block offset/length which are not calculated
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in the download progress */
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--- a/src/mps/drv_mps_version.h
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+++ b/src/mps/drv_mps_version.h
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@@ -17,7 +17,7 @@
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#define VERSIONSTEP 2
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#define VERS_TYPE 5
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-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
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#define IFX_MPS_PLATFORM_NAME "MIPS34KEc"
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#elif defined(SYSTEM_DANUBE)
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#define IFX_MPS_PLATFORM_NAME "MIPS24KEc"
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--- a/src/mps/drv_mps_vmmc_linux.c
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+++ b/src/mps/drv_mps_vmmc_linux.c
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@@ -2225,7 +2225,7 @@ IFX_int32_t __init ifx_mps_init_module (
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#if defined(CONFIG_MIPS) && !defined(CONFIG_MIPS_UNCACHED)
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#if defined(SYSTEM_DANUBE)
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bDoCacheOps = IFX_TRUE; /* on Danube always perform cache ops */
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-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
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/* on AR9/VR9 cache is configured by BSP;
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here we check whether the D-cache is shared or partitioned;
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1) in case of shared D-cache all cache operations are omitted;
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@@ -2255,7 +2255,8 @@ IFX_int32_t __init ifx_mps_init_module (
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/* reset the device before initializing the device driver */
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ifx_mps_reset ();
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- result = request_irq (INT_NUM_IM4_IRL18,
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+
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+ result = request_irq (INT_NUM_IM4_IRL18,
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#ifdef LINUX_2_6
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ifx_mps_ad0_irq, IRQF_DISABLED
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#else /* */
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@@ -2396,7 +2397,7 @@ IFX_int32_t __init ifx_mps_init_module (
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if (result = ifx_mps_init_gpt_danube ())
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return result;
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#endif /*DANUBE*/
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- TRACE (MPS, DBG_LEVEL_HIGH, ("Downloading Firmware...\n"));
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+ TRACE (MPS, DBG_LEVEL_HIGH, ("Downloading Firmware...\n"));
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ifx_mps_download_firmware (IFX_NULL, (mps_fw *) 0xa0a00000);
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udelay (500);
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TRACE (MPS, DBG_LEVEL_HIGH, ("Providing Buffers...\n"));
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--- /dev/null
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+++ b/src/mps/drv_mps_vmmc_falcon.c
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@@ -0,0 +1,463 @@
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+/******************************************************************************
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+
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+ Copyright (c) 2009
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+ Lantiq Deutschland GmbH
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+ Am Campeon 3; 85579 Neubiberg, Germany
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+
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+ For licensing information, see the file 'LICENSE' in the root folder of
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+ this software module.
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+
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+****************************************************************************
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+ Module : drv_mps_vmmc_falcon.c
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+ Description : This file contains the implementation of the FALC-ON specific
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+ driver functions.
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+*******************************************************************************/
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+
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+/* ============================= */
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+/* Includes */
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+/* ============================= */
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+#include "drv_config.h"
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+
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+#if defined(SYSTEM_FALCON) /* defined in drv_config.h */
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+
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+/* lib_ifxos headers */
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+#include "ifx_types.h"
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+#include "ifxos_linux_drv.h"
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+#include "ifxos_copy_user_space.h"
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+#include "ifxos_event.h"
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+#include "ifxos_lock.h"
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+#include "ifxos_select.h"
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+#include "ifxos_interrupt.h"
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+#include <linux/gpio.h>
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+#include <sys1_reg.h>
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+#include <falcon.h>
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+#include <falcon_irq.h>
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+#include <vpe.h>
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+#include <sysctrl.h>
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+void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = (void (*)(unsigned int, int))0xbf000290;
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+
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+#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
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+
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+/*#define USE_PLAIN_VOICE_FIRMWARE*/
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+/* board specific headers */
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+
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+/* device specific headers */
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+#include "drv_mps_vmmc.h"
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+#include "drv_mps_vmmc_dbg.h"
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+#include "drv_mps_vmmc_device.h"
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+
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+/* ============================= */
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+/* Local Macros & Definitions */
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+/* ============================= */
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+/* Firmware watchdog timer counter address */
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+#define VPE1_WDOG_CTR_ADDR ((IFX_uint32_t)((IFX_uint8_t* )IFX_MPS_SRAM + 432))
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+
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+/* Firmware watchdog timeout range, values in ms */
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+#define VPE1_WDOG_TMOUT_MIN 20
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+#define VPE1_WDOG_TMOUT_MAX 5000
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+
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+/* ============================= */
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+/* Global variable definition */
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+/* ============================= */
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+extern mps_comm_dev *pMPSDev;
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+
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+/* ============================= */
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+/* Global function declaration */
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+/* ============================= */
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+IFX_void_t ifx_mps_release (IFX_void_t);
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+extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);
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+extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);
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+IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count);
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+extern IFXOS_event_t fw_ready_evt;
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+/* ============================= */
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+/* Local function declaration */
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+/* ============================= */
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+static IFX_int32_t ifx_mps_fw_wdog_start_ar9(IFX_void_t);
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+
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+/* ============================= */
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+/* Local variable definition */
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+/* ============================= */
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+static IFX_int32_t vpe1_started = 0;
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+/* VMMC watchdog timer callback */
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+IFX_int32_t (*ifx_wdog_callback) (IFX_uint32_t flags) = IFX_NULL;
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+
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+/* ============================= */
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+/* Local function definition */
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+/* ============================= */
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+
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+/******************************************************************************
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+ * AR9 Specific Routines
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+ ******************************************************************************/
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+
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+/**
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+ * Start AR9 EDSP firmware watchdog mechanism.
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+ * Called after download and startup of VPE1.
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+ *
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+ * \param none
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+ * \return 0 IFX_SUCCESS
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+ * \return -1 IFX_ERROR
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+ * \ingroup Internal
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+ */
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+IFX_int32_t ifx_mps_fw_wdog_start_ar9()
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+{
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+ return IFX_SUCCESS;
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+}
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+
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+/**
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+ * Firmware download to Voice CPU
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+ * This function performs a firmware download to the coprocessor.
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+ *
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+ * \param pMBDev Pointer to mailbox device structure
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+ * \param pFWDwnld Pointer to firmware structure
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+ * \return 0 IFX_SUCCESS, firmware ready
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+ * \return -1 IFX_ERROR, firmware not downloaded.
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+ * \ingroup Internal
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+ */
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+IFX_int32_t ifx_mps_download_firmware (mps_mbx_dev *pMBDev, mps_fw *pFWDwnld)
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+{
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+ IFX_uint32_t mem, cksum;
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+ IFX_uint8_t crc;
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+ IFX_boolean_t bMemReqNotPresent = IFX_FALSE;
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+
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+ /* VCC register */
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+ /* dummy accesss on GTC for GPONC-55, otherwise upper bits are random on read */
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+ ltq_r32 ((u32 *)((KSEG1 | 0x1DC000B0)));
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+ /* NTR Frequency Select 1536 kHz per default or take existing,
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+ NTR Output Enable and NTR8K Output Enable */
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+ if ((ltq_r32 ((u32 *)(GPON_SYS_BASE + 0xBC)) & 7) == 0)
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+ ltq_w32_mask (0x10187, 0x183, (u32 *)(GPON_SYS_BASE + 0xBC));
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+ else
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+ ltq_w32_mask (0x10180, 0x180, (u32 *)(GPON_SYS_BASE + 0xBC));
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+#if 0
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+ /* BIU-ICU1-IM1_ISR - IM1:FSCT_CMP1=1 and FSC_ROOT=1
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+ (0x1f880328 = 0x00002800) */
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+ ltq_w32 (0x00002800, (u32 *)(GPON_ICU1_BASE + 0x30));
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+#endif
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+ /* copy FW footer from user space */
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+ if (IFX_NULL == IFXOS_CpyFromUser(pFW_img_data,
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+ pFWDwnld->data+pFWDwnld->length/4-sizeof(*pFW_img_data)/4,
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+ sizeof(*pFW_img_data)))
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+ {
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+ TRACE (MPS, DBG_LEVEL_HIGH,
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+ (KERN_ERR "[%s %s %d]: copy_from_user error\r\n",
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+ __FILE__, __func__, __LINE__));
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+ return IFX_ERROR;
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+ }
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+
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+ mem = pFW_img_data->mem;
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+
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+ /* memory requirement sanity check */
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+ if ((crc = ~((mem >> 16) + (mem >> 8) + mem)) != (mem >> 24))
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+ {
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+ TRACE (MPS, DBG_LEVEL_HIGH,
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+ ("[%s %s %d]: warning, image does not contain size - assuming 1MB!\n",
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+ __FILE__, __func__, __LINE__));
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+ mem = 1 * 1024 * 1024;
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+ bMemReqNotPresent = IFX_TRUE;
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+ }
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+ else
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+ {
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+ mem &= 0x00FFFFFF;
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+ }
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+
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+ /* check if FW image fits in available memory space */
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+ if (mem > vpe1_get_max_mem(0))
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+ {
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+ TRACE (MPS, DBG_LEVEL_HIGH,
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+ ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
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+ __FILE__, __func__, __LINE__, mem, vpe1_get_max_mem(0)));
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+ return IFX_ERROR;
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+ }
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+
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+ /* reset the driver */
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+ ifx_mps_reset ();
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+
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+ /* call BSP to get cpu1 base address */
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+ cpu1_base_addr = (IFX_uint32_t *)vpe1_get_load_addr(0);
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+
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+ /* check if CPU1 base address is sane
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+ \todo: check if address is 1MB aligned,
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+ also make it visible in a /proc fs */
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+ if (!cpu1_base_addr)
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+ {
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+ TRACE (MPS, DBG_LEVEL_HIGH,
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+ (KERN_ERR "IFX_MPS: CPU1 base address is invalid!\r\n"));
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+ return IFX_ERROR;
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+ }
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+ /* further use uncached value */
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+ cpu1_base_addr = (IFX_uint32_t *)KSEG1ADDR(cpu1_base_addr);
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+
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+ /* free all data buffers that might be currently used by FW */
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+ if (IFX_NULL != ifx_mps_bufman_freeall)
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+ {
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+ ifx_mps_bufman_freeall();
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+ }
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+
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+ if(FW_FORMAT_NEW)
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+ {
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+ /* adjust download length */
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+ pFWDwnld->length -= (sizeof(*pFW_img_data)-sizeof(IFX_uint32_t));
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+ }
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+ else
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+ {
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+ pFWDwnld->length -= sizeof(IFX_uint32_t);
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+
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+ /* handle unlikely case if FW image does not contain memory requirement -
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+ assumed for old format only */
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+ if (IFX_TRUE == bMemReqNotPresent)
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+ pFWDwnld->length += sizeof(IFX_uint32_t);
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+
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+ /* in case of old FW format always assume that FW is encrypted;
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+ use compile switch USE_PLAIN_VOICE_FIRMWARE for plain FW */
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+#ifndef USE_PLAIN_VOICE_FIRMWARE
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+ pFW_img_data->enc = 1;
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+#else
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+#warning Using unencrypted firmware!
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+ pFW_img_data->enc = 0;
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+#endif /* USE_PLAIN_VOICE_FIRMWARE */
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+ /* initializations for the old format */
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+ pFW_img_data->st_addr_crc = 2*sizeof(IFX_uint32_t) +
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+ FW_AR9_OLD_FMT_XCPT_AREA_SZ;
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+ pFW_img_data->en_addr_crc = pFWDwnld->length;
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+ pFW_img_data->fw_vers = 0;
|
|
+ pFW_img_data->magic = 0;
|
|
+ }
|
|
+
|
|
+ /* copy FW image to base address of CPU1 */
|
|
+ if (IFX_NULL ==
|
|
+ IFXOS_CpyFromUser ((IFX_void_t *)cpu1_base_addr,
|
|
+ (IFX_void_t *)pFWDwnld->data, pFWDwnld->length))
|
|
+ {
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH,
|
|
+ (KERN_ERR "[%s %s %d]: copy_from_user error\r\n", __FILE__,
|
|
+ __func__, __LINE__));
|
|
+ return IFX_ERROR;
|
|
+ }
|
|
+
|
|
+ /* process firmware decryption */
|
|
+ if (pFW_img_data->enc == 1)
|
|
+ {
|
|
+ if(FW_FORMAT_NEW)
|
|
+ {
|
|
+ /* adjust decryption length (avoid decrypting CRC32 checksum) */
|
|
+ pFWDwnld->length -= sizeof(IFX_uint32_t);
|
|
+ }
|
|
+ /* BootROM actually decrypts n+4 bytes if n bytes were passed for
|
|
+ decryption. Subtract sizeof(u32) from length to avoid decryption
|
|
+ of data beyond the FW image code */
|
|
+ pFWDwnld->length -= sizeof(IFX_uint32_t);
|
|
+ ifx_bsp_basic_mps_decrypt((unsigned int)cpu1_base_addr, pFWDwnld->length);
|
|
+ }
|
|
+
|
|
+ /* calculate CRC32 checksum over downloaded image */
|
|
+ cksum = ifx_mps_fw_crc32(cpu1_base_addr, pFW_img_data);
|
|
+
|
|
+ /* verify the checksum */
|
|
+ if(FW_FORMAT_NEW)
|
|
+ {
|
|
+ if (cksum != pFW_img_data->crc32)
|
|
+ {
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH,
|
|
+ ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
|
|
+ pFW_img_data->crc32, cksum));
|
|
+ /*return IFX_ERROR;*/
|
|
+ }
|
|
+ }
|
|
+ else
|
|
+ {
|
|
+ /* just store self-calculated checksum */
|
|
+ pFW_img_data->crc32 = cksum;
|
|
+ }
|
|
+
|
|
+ /* start VPE1 */
|
|
+ ifx_mps_release ();
|
|
+#if 0
|
|
+ /* start FW watchdog mechanism */
|
|
+ ifx_mps_fw_wdog_start_ar9();
|
|
+#endif
|
|
+ /* get FW version */
|
|
+ return ifx_mps_get_fw_version (0);
|
|
+}
|
|
+
|
|
+
|
|
+/**
|
|
+ * Restart CPU1
|
|
+ * This function restarts CPU1 by accessing the reset request register and
|
|
+ * reinitializes the mailbox.
|
|
+ *
|
|
+ * \return 0 IFX_SUCCESS, successful restart
|
|
+ * \return -1 IFX_ERROR, if reset failed
|
|
+ * \ingroup Internal
|
|
+ */
|
|
+IFX_int32_t ifx_mps_restart (IFX_void_t)
|
|
+{
|
|
+ /* raise reset request for CPU1 and reset driver structures */
|
|
+ ifx_mps_reset ();
|
|
+ /* Disable GPTC Interrupt to CPU1 */
|
|
+ ifx_mps_shutdown_gpt ();
|
|
+ /* re-configure GPTC */
|
|
+ ifx_mps_init_gpt ();
|
|
+ /* let CPU1 run */
|
|
+ ifx_mps_release ();
|
|
+ /* start FW watchdog mechanism */
|
|
+ ifx_mps_fw_wdog_start_ar9();
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH, ("IFX_MPS: Restarting firmware..."));
|
|
+ return ifx_mps_get_fw_version (0);
|
|
+}
|
|
+
|
|
+/**
|
|
+ * Shutdown MPS - stop VPE1
|
|
+ * This function stops VPE1
|
|
+ *
|
|
+ * \ingroup Internal
|
|
+ */
|
|
+IFX_void_t ifx_mps_shutdown (IFX_void_t)
|
|
+{
|
|
+ if (vpe1_started)
|
|
+ {
|
|
+ /* stop software watchdog timer */
|
|
+ vpe1_sw_wdog_stop (0);
|
|
+ /* clean up the BSP callback function */
|
|
+ vpe1_sw_wdog_register_reset_handler (IFX_NULL);
|
|
+ /* stop VPE1 */
|
|
+ vpe1_sw_stop (0);
|
|
+ vpe1_started = 0;
|
|
+ }
|
|
+ /* free GPTC */
|
|
+ ifx_mps_shutdown_gpt ();
|
|
+}
|
|
+
|
|
+/**
|
|
+ * Reset CPU1
|
|
+ * This function causes a reset of CPU1 by clearing the CPU0 boot ready bit
|
|
+ * in the reset request register RCU_RST_REQ.
|
|
+ * It does not change the boot configuration registers for CPU0 or CPU1.
|
|
+ *
|
|
+ * \return 0 IFX_SUCCESS, cannot fail
|
|
+ * \ingroup Internal
|
|
+ */
|
|
+IFX_void_t ifx_mps_reset (IFX_void_t)
|
|
+{
|
|
+ /* if VPE1 is already started, stop it */
|
|
+ if (vpe1_started)
|
|
+ {
|
|
+ /* stop software watchdog timer first */
|
|
+ vpe1_sw_wdog_stop (0);
|
|
+ vpe1_sw_stop (0);
|
|
+ vpe1_started = 0;
|
|
+ }
|
|
+
|
|
+ /* reset driver */
|
|
+ ifx_mps_reset_structures (pMPSDev);
|
|
+ ifx_mps_bufman_close ();
|
|
+ return;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * Let CPU1 run
|
|
+ * This function starts VPE1
|
|
+ *
|
|
+ * \return none
|
|
+ * \ingroup Internal
|
|
+ */
|
|
+IFX_void_t ifx_mps_release (IFX_void_t)
|
|
+{
|
|
+ IFX_int_t ret;
|
|
+ IFX_int32_t RetCode = 0;
|
|
+
|
|
+ /* Start VPE1 */
|
|
+ if (IFX_SUCCESS !=
|
|
+ vpe1_sw_start ((IFX_void_t *)cpu1_base_addr, 0, 0))
|
|
+ {
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH, (KERN_ERR "Error starting VPE1\r\n"));
|
|
+ return;
|
|
+ }
|
|
+ vpe1_started = 1;
|
|
+
|
|
+ /* sleep 3 seconds until FW is ready */
|
|
+ ret = IFXOS_EventWait (&fw_ready_evt, 3000, &RetCode);
|
|
+ if ((ret == IFX_ERROR) && (RetCode == 1))
|
|
+ {
|
|
+ /* timeout */
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH,
|
|
+ (KERN_ERR "[%s %s %d]: Timeout waiting for firmware ready.\r\n",
|
|
+ __FILE__, __func__, __LINE__));
|
|
+ /* recalculate and compare the firmware checksum */
|
|
+ ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
|
|
+ /* dump exception area on a console */
|
|
+ ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);
|
|
+ }
|
|
+}
|
|
+
|
|
+/**
|
|
+ * WDT callback.
|
|
+ * This function is called by BSP (module softdog_vpe) in case if software
|
|
+ * watchdog timer expiration is detected by BSP.
|
|
+ * This function needs to be registered at BSP as WDT callback using
|
|
+ * vpe1_sw_wdog_register_reset_handler() API.
|
|
+ *
|
|
+ * \return 0 IFX_SUCCESS, cannot fail
|
|
+ * \ingroup Internal
|
|
+ */
|
|
+IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count)
|
|
+{
|
|
+#ifdef DEBUG
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH,
|
|
+ ("MPS: watchdog callback! arg=0x%08x\r\n", wdog_cleared_ok_count));
|
|
+#endif /* DEBUG */
|
|
+
|
|
+ /* reset SmartSLIC is done by FW */
|
|
+ /* recalculate and compare the firmware checksum */
|
|
+ ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
|
|
+
|
|
+ /* dump exception area on a console */
|
|
+ ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);
|
|
+
|
|
+ if (IFX_NULL != ifx_wdog_callback)
|
|
+ {
|
|
+ /* call VMMC driver */
|
|
+ ifx_wdog_callback (wdog_cleared_ok_count);
|
|
+ }
|
|
+ else
|
|
+ {
|
|
+ TRACE (MPS, DBG_LEVEL_HIGH,
|
|
+ (KERN_WARNING "MPS: VMMC watchdog timer callback is NULL.\r\n"));
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/**
|
|
+ * Register WDT callback.
|
|
+ * This function is called by VMMC driver to register its callback in
|
|
+ * the MPS driver.
|
|
+ *
|
|
+ * \return 0 IFX_SUCCESS, cannot fail
|
|
+ * \ingroup Internal
|
|
+ */
|
|
+IFX_int32_t
|
|
+ifx_mps_register_wdog_callback (IFX_int32_t (*pfn) (IFX_uint32_t flags))
|
|
+{
|
|
+ ifx_wdog_callback = pfn;
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/**
|
|
+ Hardware setup on FALC ON
|
|
+*/
|
|
+void sys_hw_setup (void)
|
|
+{
|
|
+ /* Set INFRAC register bit 1: clock enable of the GPE primary clock. */
|
|
+ sys_gpe_hw_activate (0);
|
|
+ /* enable 1.5 V */
|
|
+ ltq_w32_mask (0xf, 0x0b, (u32 *)(GPON_SYS1_BASE | 0xbc));
|
|
+ /* SYS1-CLKEN:GPTC = 1 and MPS, no longer FSCT = 1 */
|
|
+ sys1_hw_activate (ACTS_MPS | ACTS_GPTC);
|
|
+ /* GPTC:CLC:RMC = 1 */
|
|
+ ltq_w32 (0x00000100, (u32 *)(KSEG1 | 0x1E100E00));
|
|
+}
|
|
+
|
|
+#ifndef VMMC_WITH_MPS
|
|
+EXPORT_SYMBOL (ifx_mps_register_wdog_callback);
|
|
+#endif /* !VMMC_WITH_MPS */
|
|
+
|
|
+#endif /* SYSTEM_FALCON */
|
|
--- a/src/mps/drv_mps_vmmc_common.c
|
|
+++ b/src/mps/drv_mps_vmmc_common.c
|
|
@@ -66,6 +66,10 @@ static void inline bsp_mask_and_ack_irq(
|
|
# include <asm/ifx/ifx_regs.h>
|
|
# include <asm/ifx/ifx_gptu.h>
|
|
#endif
|
|
+#if defined(SYSTEM_FALCON)
|
|
+#include <sys1_reg.h>
|
|
+#include <sysctrl.h>
|
|
+#endif
|
|
|
|
#include "drv_mps_vmmc.h"
|
|
#include "drv_mps_vmmc_dbg.h"
|
|
@@ -1156,7 +1160,12 @@ IFX_uint32_t ifx_mps_init_structures (mp
|
|
mailbox, * upstream and downstream direction. */
|
|
memset (
|
|
/* avoid to overwrite CPU boot registers */
|
|
+#if defined(SYSTEM_FALCON)
|
|
+ (IFX_void_t *) MBX_Memory +
|
|
+ 2 * sizeof (mps_boot_cfg_reg),
|
|
+#else
|
|
(IFX_void_t *) MBX_Memory,
|
|
+#endif
|
|
0,
|
|
sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
|
|
MBX_Memory->MBX_UPSTR_CMD_BASE =
|
|
@@ -2651,7 +2660,6 @@ IFX_void_t ifx_mps_enable_mailbox_int ()
|
|
#endif
|
|
|
|
*IFX_MPS_AD0ENR = Ad0Reg.val;
|
|
-
|
|
}
|
|
|
|
/**
|
|
@@ -2669,6 +2677,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
|
|
Ad0Reg.fld.cu_mbx = 0;
|
|
Ad0Reg.fld.du_mbx = 0;
|
|
*IFX_MPS_AD0ENR = Ad0Reg.val;
|
|
+
|
|
}
|
|
|
|
/**
|
|
@@ -2766,11 +2775,13 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
|
|
/* handle only enabled interrupts */
|
|
MPS_Ad0StatusReg.val &= *IFX_MPS_AD0ENR;
|
|
|
|
+#if !defined(SYSTEM_FALCON)
|
|
#ifdef LINUX_2_6
|
|
bsp_mask_and_ack_irq (irq);
|
|
#else /* */
|
|
mask_and_ack_danube_irq (irq);
|
|
#endif /* */
|
|
+#endif /* !defined(SYSTEM_FALCON) */
|
|
/* FW is up and ready to process commands */
|
|
if (MPS_Ad0StatusReg.fld.dl_end)
|
|
{
|
|
@@ -2919,11 +2930,13 @@ irqreturn_t ifx_mps_ad1_irq (IFX_int32_t
|
|
/* handle only enabled interrupts */
|
|
MPS_Ad1StatusReg.val &= *IFX_MPS_AD1ENR;
|
|
|
|
+#if !defined(SYSTEM_FALCON)
|
|
#ifdef LINUX_2_6
|
|
bsp_mask_and_ack_irq (irq);
|
|
#else /* */
|
|
mask_and_ack_danube_irq (irq);
|
|
#endif /* */
|
|
+#endif /* !defined(SYSTEM_FALCON) */
|
|
pMPSDev->event.MPS_Ad1Reg.val = MPS_Ad1StatusReg.val;
|
|
|
|
/* use callback function or queue wake up to notify about data reception */
|
|
@@ -2977,11 +2990,13 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
|
|
IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
|
|
/* handle only enabled interrupts */
|
|
MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
|
|
+#if !defined(SYSTEM_FALCON)
|
|
#ifdef LINUX_2_6
|
|
bsp_mask_and_ack_irq (irq);
|
|
#else /* */
|
|
mask_and_ack_danube_irq (irq);
|
|
#endif /* */
|
|
+#endif /* !defined(SYSTEM_FALCON) */
|
|
|
|
pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
|
|
#ifdef PRINT_ON_ERR_INTERRUPT
|
|
@@ -3126,6 +3141,7 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
|
|
*/
|
|
IFX_return_t ifx_mps_init_gpt ()
|
|
{
|
|
+#if !defined(SYSTEM_FALCON)
|
|
unsigned long flags;
|
|
IFX_uint32_t timer_flags, timer, loops = 0;
|
|
IFX_ulong_t count;
|
|
@@ -3134,7 +3150,11 @@ IFX_return_t ifx_mps_init_gpt ()
|
|
#else /* Danube */
|
|
timer = TIMER1B;
|
|
#endif /* SYSTEM_AR9 || SYSTEM_VR9 */
|
|
+#endif
|
|
|
|
+#if defined(SYSTEM_FALCON)
|
|
+ sys_hw_setup ();
|
|
+#else
|
|
/* calibration loop - required to syncronize GPTC interrupt with falling
|
|
edge of FSC clock */
|
|
timer_flags =
|
|
@@ -3179,7 +3199,7 @@ Probably already in use.\r\n", __FILE__,
|
|
#endif /* DEBUG */
|
|
|
|
IFXOS_UNLOCKINT (flags);
|
|
-
|
|
+#endif
|
|
return IFX_SUCCESS;
|
|
}
|
|
|
|
@@ -3194,6 +3214,9 @@ Probably already in use.\r\n", __FILE__,
|
|
*/
|
|
IFX_void_t ifx_mps_shutdown_gpt (IFX_void_t)
|
|
{
|
|
+#if defined(SYSTEM_FALCON)
|
|
+ sys1_hw_deactivate (ACTS_MPS);
|
|
+#else
|
|
IFX_uint32_t timer;
|
|
#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
timer = TIMER1A;
|
|
@@ -3202,6 +3225,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi
|
|
#endif /* SYSTEM_AR9 || SYSTEM_VR9 */
|
|
|
|
ifx_gptu_timer_free (timer);
|
|
+#endif
|
|
}
|
|
|
|
/**
|
|
--- a/src/mps/drv_mps_vmmc_device.h
|
|
+++ b/src/mps/drv_mps_vmmc_device.h
|
|
@@ -22,7 +22,12 @@
|
|
# include <lantiq_soc.h>
|
|
# include <gpio.h>
|
|
#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
|
|
+#if defined(SYSTEM_FALCON)
|
|
+#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1D004000)
|
|
+#else
|
|
#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
|
+#endif
|
|
+
|
|
#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
|
|
#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
|
|
#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
|
|
@@ -73,10 +78,11 @@
|
|
/* MPS Common defines */
|
|
/* ============================= */
|
|
|
|
-#define MPS_BASEADDRESS 0xBF107000
|
|
-#define MPS_RAD0SR MPS_BASEADDRESS + 0x0004
|
|
-
|
|
+#if defined(SYSTEM_FALCON)
|
|
+#define MBX_BASEADDRESS 0xBF200040
|
|
+#else
|
|
#define MBX_BASEADDRESS 0xBF200000
|
|
+#endif
|
|
#define VCPU_BASEADDRESS 0xBF208000 /* 0xBF108000 */
|
|
/*---------------------------------------------------------------------------*/
|
|
#if !defined(CONFIG_LANTIQ)
|
|
@@ -118,7 +124,6 @@
|
|
/*---------------------------------------------------------------------------*/
|
|
|
|
#ifdef CONFIG_MPS_EVENT_MBX
|
|
-
|
|
#define MBX_CMD_FIFO_SIZE 64 /**< Size of command FIFO in bytes */
|
|
#define MBX_DATA_UPSTRM_FIFO_SIZE 64
|
|
#define MBX_DATA_DNSTRM_FIFO_SIZE 128
|
|
@@ -294,6 +299,10 @@ typedef struct
|
|
#ifdef CONFIG_MPS_EVENT_MBX
|
|
typedef struct
|
|
{
|
|
+#if defined(SYSTEM_FALCON)
|
|
+ mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
|
|
+ mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
|
|
+#endif
|
|
volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE; /**< Upstream Command FIFO Base Address */
|
|
volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE; /**< Upstream Command FIFO size in byte */
|
|
volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE; /**< Downstream Command FIFO Base Address */
|
|
@@ -317,13 +326,19 @@ typedef struct
|
|
volatile IFX_uint32_t MBX_UPSTR_EVENT_WRITE; /**< Upstream Event FIFO Write Index */
|
|
volatile IFX_uint32_t MBX_EVENT[MBX_EVENT_DATA_WORDS];
|
|
volatile IFX_uint32_t reserved[4];
|
|
+#if !defined(SYSTEM_FALCON)
|
|
mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
|
|
mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
|
|
+#endif
|
|
} mps_mbx_reg;
|
|
|
|
#else /* */
|
|
typedef struct
|
|
{
|
|
+#if defined(SYSTEM_FALCON)
|
|
+ mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
|
|
+ mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
|
|
+#endif
|
|
volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE; /**< Upstream Command FIFO Base Address */
|
|
volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE; /**< Upstream Command FIFO size in byte */
|
|
volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE; /**< Downstream Command FIFO Base Address */
|
|
@@ -341,8 +356,10 @@ typedef struct
|
|
volatile IFX_uint32_t MBX_DNSTR_DATA_READ; /**< Downstream Data FIFO Read Index */
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volatile IFX_uint32_t MBX_DNSTR_DATA_WRITE; /**< Downstream Data FIFO Write Index */
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volatile IFX_uint32_t MBX_DATA[MBX_DATA_WORDS];
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+#if !defined(SYSTEM_FALCON)
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mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */
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|
mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */
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+#endif
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} mps_mbx_reg;
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|
#endif /* CONFIG_MPS_EVENT_MBX */
|
|
|
|
--- a/src/drv_api.h
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|
+++ b/src/drv_api.h
|
|
@@ -183,7 +183,7 @@
|
|
#endif
|
|
|
|
/* TAPI FXS Phone Detection feature is not available for Danube platform */
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|
-#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9))
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|
+#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON))
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|
#define VMMC_CFG_ADD_FEAT_PHONE_DETECTION VMMC_FEAT_PHONE_DETECTION
|
|
#else
|
|
#define VMMC_CFG_ADD_FEAT_PHONE_DETECTION 0
|
|
--- a/src/drv_vmmc_alm.c
|
|
+++ b/src/drv_vmmc_alm.c
|
|
@@ -800,7 +800,7 @@ IFX_void_t VMMC_ALM_Free_Ch_Structures (
|
|
}
|
|
|
|
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
/**
|
|
Check whether SmartSLIC is connected
|
|
|
|
@@ -836,7 +836,7 @@ IFX_boolean_t VMMC_ALM_SmartSLIC_IsConne
|
|
#endif /*SYSTEM_AR9 || SYSTEM_VR9*/
|
|
|
|
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
/**
|
|
Read the number of channels on the SmartSLIC.
|
|
|
|
@@ -1876,7 +1876,7 @@ IFX_int32_t VMMC_TAPI_LL_ALM_VMMC_Test_L
|
|
/* write updated message contents */
|
|
ret = CmdWrite (pDev, (IFX_uint32_t *)((IFX_void_t *)&debugCfg),
|
|
DCCTL_CMD_LEN);
|
|
-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
IFX_uint32_t dcctrlLoop[2];
|
|
IFX_uint32_t ch = (IFX_uint32_t)(pCh->nChannel - 1);
|
|
|
|
--- a/src/drv_vmmc_alm.h
|
|
+++ b/src/drv_vmmc_alm.h
|
|
@@ -65,7 +65,7 @@ extern IFX_void_t irq_VMMC_ALM_LineDisab
|
|
extern IFX_void_t VMMC_ALM_CorrectLinemodeCache (VMMC_CHANNEL *pCh,
|
|
IFX_uint16_t lm);
|
|
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
extern IFX_boolean_t VMMC_ALM_SmartSLIC_IsConnected (
|
|
VMMC_DEVICE *pDev);
|
|
|
|
--- a/src/drv_vmmc_init.c
|
|
+++ b/src/drv_vmmc_init.c
|
|
@@ -52,15 +52,6 @@
|
|
#include "ifx_pmu.h"
|
|
#endif /* PMU_SUPPORTED */
|
|
|
|
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
|
|
-# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
|
|
-# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
|
|
-# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
|
|
-# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
|
|
-# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
|
|
-# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
|
|
-#endif
|
|
-
|
|
/* ============================= */
|
|
/* Local Macros & Definitions */
|
|
/* ============================= */
|
|
@@ -820,7 +811,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(
|
|
MIN_FW_HOTFIXSTEP};
|
|
IFX_uint8_t tmp1, tmp2;
|
|
IFX_TAPI_RESOURCE nResource;
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
IFX_uint8_t nChannels, nFXOChannels;
|
|
#endif /*SYSTEM_AR9 || SYSTEM_VR9*/
|
|
IFX_int32_t ret = VMMC_statusOk;
|
|
@@ -874,7 +865,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(
|
|
pDev->bSmartSlic = IFX_FALSE;
|
|
pDev->bSlicSupportsIdleMode = IFX_FALSE;
|
|
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
if (VMMC_SUCCESS(ret))
|
|
{
|
|
/* Reduce the number of ALM channels in the capabilities if the SLIC
|
|
--- a/src/drv_vmmc_ioctl.c
|
|
+++ b/src/drv_vmmc_ioctl.c
|
|
@@ -273,7 +273,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP
|
|
case FIO_GET_VERS:
|
|
{
|
|
VMMC_IO_VERSION *pVers;
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
VMMC_SDD_REVISION_READ_t *pSDDVersCmd = IFX_NULL;
|
|
#endif /*SYSTEM_AR9 || SYSTEM_VR9*/
|
|
SYS_VER_t *pCmd;
|
|
@@ -322,7 +322,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP
|
|
pVers->nTapiVers = 3;
|
|
pVers->nDrvVers = MAJORSTEP << 24 | MINORSTEP << 16 |
|
|
VERSIONSTEP << 8 | VERS_TYPE;
|
|
-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
|
|
+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)
|
|
/* in case of SmartSLIC based systems, we can give some more
|
|
versions.*/
|
|
if (VMMC_ALM_SmartSLIC_IsConnected(pDev))
|