mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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937b6c47c1
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11071 3c298f89-4303-0410-b956-a3cf2f4a3e73
155 lines
3.6 KiB
C
155 lines
3.6 KiB
C
/*
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* arch/mips/ifxmips/setup.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2004 peng.liu@infineon.com
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*
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* Rewrite of Infineon IFXMips code, thanks to infineon for the support,
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* software and hardware
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*
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#include <linux/init.h>
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#include <asm/time.h>
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#include <asm/traps.h>
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#include <asm/cpu.h>
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#include <asm/irq.h>
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#include <asm/ifxmips/ifxmips.h>
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#include <asm/ifxmips/ifxmips_irq.h>
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#include <asm/ifxmips/ifxmips_pmu.h>
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static unsigned int r4k_offset; /* Amount to increment compare reg each time */
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static unsigned int r4k_cur; /* What counter should be at next timer irq */
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extern void ifxmips_reboot_setup (void);
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void prom_printf (const char * fmt, ...);
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void
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__init bus_error_init (void)
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{
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/* nothing yet */
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}
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unsigned int
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ifxmips_get_ddr_hz (void)
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{
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switch (readl(IFXMIPS_CGU_SYS) & 0x3)
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{
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case 0:
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return CLOCK_167M;
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case 1:
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return CLOCK_133M;
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case 2:
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return CLOCK_111M;
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}
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return CLOCK_83M;
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}
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EXPORT_SYMBOL(ifxmips_get_ddr_hz);
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unsigned int
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ifxmips_get_cpu_hz (void)
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{
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unsigned int ddr_clock = ifxmips_get_ddr_hz();
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switch (readl(IFXMIPS_CGU_SYS) & 0xc)
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{
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case 0:
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return CLOCK_333M;
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case 4:
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return ddr_clock;
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}
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return ddr_clock << 1;
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}
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EXPORT_SYMBOL(ifxmips_get_cpu_hz);
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unsigned int
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ifxmips_get_fpi_hz (void)
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{
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unsigned int ddr_clock = ifxmips_get_ddr_hz();
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if (readl(IFXMIPS_CGU_SYS) & 0x40)
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{
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return ddr_clock >> 1;
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}
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return ddr_clock;
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}
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EXPORT_SYMBOL(ifxmips_get_fpi_hz);
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unsigned int
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ifxmips_get_cpu_ver (void)
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{
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return readl(IFXMIPS_MCD_CHIPID) & 0xFFFFF000;
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}
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EXPORT_SYMBOL(ifxmips_get_cpu_ver);
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void
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ifxmips_time_init (void)
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{
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mips_hpt_frequency = ifxmips_get_cpu_hz() / 2;
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r4k_offset = mips_hpt_frequency / HZ;
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printk("mips_hpt_frequency:%d\n", mips_hpt_frequency);
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printk("r4k_offset: %08x(%d)\n", r4k_offset, r4k_offset);
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}
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int
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ifxmips_be_handler(struct pt_regs *regs, int is_fixup)
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{
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/*TODO*/
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printk(KERN_ERR "TODO: BUS error\n");
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return MIPS_BE_FATAL;
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}
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void __init
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plat_time_init (void)
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{
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r4k_cur = (read_c0_count() + r4k_offset);
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write_c0_compare(r4k_cur);
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ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
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writel(0x100, IFXMIPS_GPTU_GPT_CLC);
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writel(0xffff, IFXMIPS_GPTU_GPT_CAPREL);
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writel(0x80C0, IFXMIPS_GPTU_GPT_T6CON);
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}
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extern const char* get_system_type (void);
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void (*board_time_init)(void);
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void __init
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plat_mem_setup (void)
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{
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u32 status;
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prom_printf("This %s has a cpu rev of 0x%X\n", get_system_type(), ifxmips_get_cpu_ver());
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//TODO WHY ???
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/* clear RE bit*/
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status = read_c0_status();
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status &= (~(1<<25));
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write_c0_status(status);
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ifxmips_reboot_setup();
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board_time_init = ifxmips_time_init;
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board_be_handler = &ifxmips_be_handler;
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ioport_resource.start = IOPORT_RESOURCE_START;
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ioport_resource.end = IOPORT_RESOURCE_END;
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iomem_resource.start = IOMEM_RESOURCE_START;
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iomem_resource.end = IOMEM_RESOURCE_END;
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}
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