mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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19bc341ecf
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9898 3c298f89-4303-0410-b956-a3cf2f4a3e73
271 lines
8.3 KiB
C
271 lines
8.3 KiB
C
/******************************************************************************
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**
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** FILE NAME : danube_mei.h
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** PROJECT : Danube
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** MODULES : MEI
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**
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** DATE : 1 Jan 2006
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** AUTHOR : TC Chen
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** DESCRIPTION : MEI Driver
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** COPYRIGHT : Copyright (c) 2006
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Version $Date $Author $Comment
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*******************************************************************************/
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#ifndef _IFXMIPS_MEI_H
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#define _IFXMIPS_MEI_H
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#include "ifxmips_mei_app.h"
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#define IFXMIPS_MEI_DEBUG
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#define IFXMIPS_MEI_CMV_EXTRA
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#define IFXMIPS_MEI_MAJOR 106
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/*
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** Define where in ME Processor's memory map the Stratify chip lives
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*/
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#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
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// Mailboxes
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#define MSG_LENGTH 16 // x16 bits
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#define YES_REPLY 1
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#define NO_REPLY 0
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#define CMV_TIMEOUT 100 //jiffies
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#define MIB_INTERVAL 10000 //msec
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/*** Bit definitions ***/
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#define FALSE 0
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#define TRUE 1
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#define BIT0 1<<0
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#define BIT1 1<<1
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#define BIT2 1<<2
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#define BIT3 1<<3
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#define BIT4 1<<4
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#define BIT5 1<<5
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#define BIT6 1<<6
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#define BIT7 1<<7
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#define BIT8 1<<8
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#define BIT9 1<<9
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#define BIT10 1<<10
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#define BIT11 1<<11
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#define BIT12 1<<12
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#define BIT13 1<<13
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#define BIT14 1<<14
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#define BIT15 1<<15
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#define BIT16 1<<16
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#define BIT17 1<<17
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#define BIT18 1<<18
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#define BIT19 1<<19
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#define BIT20 1<<20
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#define BIT21 1<<21
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#define BIT22 1<<22
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#define BIT23 1<<23
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#define BIT24 1<<24
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#define BIT25 1<<25
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#define BIT26 1<<26
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#define BIT27 1<<27
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#define BIT28 1<<28
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#define BIT29 1<<29
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#define BIT30 1<<30
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#define BIT31 1<<31
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// ARC register addresss
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#define ARC_STATUS 0x0
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#define ARC_LP_START 0x2
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#define ARC_LP_END 0x3
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#define ARC_DEBUG 0x5
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#define ARC_INT_MASK 0x10A
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#define IRAM0_BASE (0x00000)
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#define IRAM1_BASE (0x04000)
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#define BRAM_BASE (0x0A000)
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#define ADSL_BASE (0x20000)
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#define CRI_BASE (ADSL_BASE + 0x11F00)
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#define CRI_CCR0 (CRI_BASE + 0x00)
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#define CRI_RST (CRI_BASE + 0x04*4)
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#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
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//
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#define IRAM0_ADDR_BIT_MASK 0xFFF
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#define IRAM1_ADDR_BIT_MASK 0xFFF
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#define BRAM_ADDR_BIT_MASK 0xFFF
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#define RX_DILV_ADDR_BIT_MASK 0x1FFF
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// CRI_CCR0 Register definitions
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#define CLK_2M_MODE_ENABLE BIT6
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#define ACL_CLK_MODE_ENABLE BIT4
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#define FDF_CLK_MODE_ENABLE BIT2
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#define STM_CLK_MODE_ENABLE BIT0
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// CRI_RST Register definitions
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#define FDF_SRST BIT3
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#define MTE_SRST BIT2
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#define FCI_SRST BIT1
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#define AAI_SRST BIT0
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// MEI_TO_ARC_INTERRUPT Register definitions
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#define MEI_TO_ARC_INT1 BIT3
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#define MEI_TO_ARC_INT0 BIT2
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#define MEI_TO_ARC_CS_DONE BIT1 //need to check
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#define MEI_TO_ARC_MSGAV BIT0
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// ARC_TO_MEI_INTERRUPT Register definitions
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#define ARC_TO_MEI_INT1 BIT8
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#define ARC_TO_MEI_INT0 BIT7
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#define ARC_TO_MEI_CS_REQ BIT6
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#define ARC_TO_MEI_DBG_DONE BIT5
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#define ARC_TO_MEI_MSGACK BIT4
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#define ARC_TO_MEI_NO_ACCESS BIT3
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#define ARC_TO_MEI_CHECK_AAITX BIT2
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#define ARC_TO_MEI_CHECK_AAIRX BIT1
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#define ARC_TO_MEI_MSGAV BIT0
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// ARC_TO_MEI_INTERRUPT_MASK Register definitions
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#define GP_INT1_EN BIT8
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#define GP_INT0_EN BIT7
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#define CS_REQ_EN BIT6
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#define DBG_DONE_EN BIT5
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#define MSGACK_EN BIT4
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#define NO_ACC_EN BIT3
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#define AAITX_EN BIT2
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#define AAIRX_EN BIT1
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#define MSGAV_EN BIT0
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#define MEI_SOFT_RESET BIT0
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#define HOST_MSTR BIT0
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#define JTAG_MASTER_MODE 0x0
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#define MEI_MASTER_MODE HOST_MSTR
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// MEI_DEBUG_DECODE Register definitions
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#define MEI_DEBUG_DEC_MASK (0x3)
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#define MEI_DEBUG_DEC_AUX_MASK (0x0)
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#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
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#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
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#define MEI_DEBUG_DEC_CORE_MASK (0x3)
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#define AUX_STATUS (0x0)
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// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
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// page swap requests.
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#define MEI_TO_ARC_MAILBOX (0xDFD0)
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#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
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#define ARC_TO_MEI_MAILBOX (0xDFA0)
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#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
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// Codeswap request messages are indicated by setting BIT31
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#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
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// Clear Eoc messages received are indicated by setting BIT17
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#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
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/*
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** Swap page header
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*/
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// Page must be loaded at boot time if size field has BIT31 set
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#define BOOT_FLAG (BIT31)
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#define BOOT_FLAG_MASK ~BOOT_FLAG
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#define FREE_RELOAD 1
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#define FREE_SHOWTIME 2
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#define FREE_ALL 3
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#define IFX_POP_EOC_DONE 0
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#define IFX_POP_EOC_FAIL -1
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#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered
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// marcos
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#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
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#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
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#define SET_BIT(reg, mask) reg |= (mask)
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#define CLEAR_BIT(reg, mask) reg &= (~mask)
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#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
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#define SET_BITS(reg, mask) SET_BIT(reg, mask)
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#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
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#define ALIGN_SIZE ( 1L<<10 ) //1K size align
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#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
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// swap marco
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#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
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#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
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// Swap page header describes size in 32-bit words, load location, and image offset
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// for program and/or data segments
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typedef struct _arc_swp_page_hdr {
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u32 p_offset; //Offset bytes of progseg from beginning of image
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u32 p_dest; //Destination addr of progseg on processor
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u32 p_size; //Size in 32-bitwords of program segment
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u32 d_offset; //Offset bytes of dataseg from beginning of image
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u32 d_dest; //Destination addr of dataseg on processor
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u32 d_size; //Size in 32-bitwords of data segment
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} ARC_SWP_PAGE_HDR;
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#ifdef CONFIG_PROC_FS
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typedef struct reg_entry {
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int *flag;
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char name[30]; // big enough to hold names
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char description[100]; // big enough to hold description
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unsigned short low_ino;
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} reg_entry_t;
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#endif
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/*
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** Swap image header
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*/
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#define GET_PROG 0 // Flag used for program mem segment
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#define GET_DATA 1 // Flag used for data mem segment
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// Image header contains size of image, checksum for image, and count of
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// page headers. Following that are 'count' page headers followed by
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// the code and/or data segments to be loaded
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typedef struct _arc_img_hdr {
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u32 size; // Size of binary image in bytes
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u32 checksum; // Checksum for image
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u32 count; // Count of swp pages in image
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ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
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} ARC_IMG_HDR;
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typedef struct smmu_mem_info {
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int type;
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unsigned long nCopy;
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unsigned long size;
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unsigned char *address;
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unsigned char *org_address;
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} smmu_mem_info_t;
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/*
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** Native size for the Stratiphy interface is 32-bits. All reads and writes
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** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
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** byte data. Read routines are provided. Write routines are probably a bad idea, as the
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** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
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** could very well have unintended results.
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*/
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MEI_ERROR meiCMV (u16 *, int, u16 *); // first arg is CMV to ARC, second to indicate whether need reply
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MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
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extern int ifx_mei_hdlc_send (char *hdlc_pkt, int hdlc_pkt_len);
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extern int ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len);
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#if defined(__KERNEL__) || defined (IFXMIPS_PORT_RTEMS)
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extern void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size,
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u16 * data, u16 * CMVMSG);
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int ifx_mei_hdlc_send (char *, int);
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int ifx_mei_hdlc_read (char *, int);
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#endif
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#endif
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