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git://projects.qi-hardware.com/openwrt-xburst.git
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343c185b7d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16547 3c298f89-4303-0410-b956-a3cf2f4a3e73
700 lines
20 KiB
Diff
700 lines
20 KiB
Diff
From e1618e943f60a4f8f778c4f7c389e2fa13eb0a83 Mon Sep 17 00:00:00 2001
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From: Kurt Mahan <kmahan@freescale.com>
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Date: Thu, 26 Jun 2008 16:29:56 -0600
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Subject: [PATCH] Add I2C support for the M5445x platforms.
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LTIBName: m5445x-i2c
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Signed-off-by: Kurt Mahan <kmahan@freescale.com>
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---
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drivers/i2c/busses/Kconfig | 10 +
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drivers/i2c/busses/Makefile | 1 +
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drivers/i2c/busses/i2c-mcf.c | 573 ++++++++++++++++++++++++++++++++++++++++++
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drivers/i2c/busses/i2c-mcf.h | 75 ++++++
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4 files changed, 659 insertions(+), 0 deletions(-)
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create mode 100644 drivers/i2c/busses/i2c-mcf.c
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create mode 100644 drivers/i2c/busses/i2c-mcf.h
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--- a/drivers/i2c/busses/Kconfig
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+++ b/drivers/i2c/busses/Kconfig
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@@ -302,6 +302,16 @@ config I2C_POWERMAC
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This support is also available as a module. If so, the module
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will be called i2c-powermac.
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+config I2C_MCF
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+ tristate "MCF ColdFire"
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+ depends on I2C && EXPERIMENTAL
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+ help
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+ If you say yes to this option, support will be included for the
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+ I2C on most ColdFire CPUs
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+
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+ This driver can also be built as a module. If so, the module
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+ will be called i2c-mcf.
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+
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config I2C_MPC
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tristate "MPC107/824x/85xx/52xx/86xx"
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depends on PPC32
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--- a/drivers/i2c/busses/Makefile
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+++ b/drivers/i2c/busses/Makefile
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@@ -53,6 +53,7 @@ obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3
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obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
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obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
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obj-$(CONFIG_I2C_MCF548x) += i2c-mcf548x.o
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+obj-$(CONFIG_I2C_MCF) += i2c-mcf.o
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ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
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EXTRA_CFLAGS += -DDEBUG
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--- /dev/null
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+++ b/drivers/i2c/busses/i2c-mcf.c
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@@ -0,0 +1,573 @@
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+/*
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+ i2c-mcf.c - Part of lm_sensors, Linux kernel modules for hardware monitoring
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+
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+ Copyright (c) 2005, Derek CL Cheung <derek.cheung@sympatico.ca>
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+ <http://www3.sympatico.ca/derek.cheung>
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+
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+ Copyright (c) 2006-2007, emlix
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+ Sebastian Hess <sh@emlix.com>
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+
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+ Copyright (c) 2006-2007 Freescale Semiconductor, Inc
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+ Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com>
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+ Matt Waddel <Matt.Waddel@freescale.com>
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program; if not, write to the Free Software
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+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+
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+ Changes:
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+ v0.1 26 March 2005
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+ Initial Release - developed on uClinux with 2.6.9 kernel
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+
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+ v0.2 29 May 2006
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+ Modified to be more generic and added support for
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+ i2c_master_xfer
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+
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+ This I2C adaptor supports the ColdFire CPU I2C module. Since most Coldfire
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+ CPUs' I2C module use the same register set (e.g., MCF5249), the code is very
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+ portable and re-usable to other Coldfire CPUs.
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+
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+ The transmission frequency is set at about 100KHz for the CPU board with
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+ 8MHz crystal. If the CPU board uses different system clock frequency, you
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+ should change the following line:
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+ static int __init i2c_coldfire_init(void)
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+ {
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+ .........
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+ // Set transmission frequency 0x15 = ~100kHz
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+ *MCF_I2C_I2FDR = 0x15;
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+ ........
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+ }
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+
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+ Remember to perform a dummy read to set the ColdFire CPU's I2C module for
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+ read before reading the actual byte from a device
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+
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+ The I2C_SM_BUS_BLOCK_DATA function are not yet ready but most lm_senors
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+ do not care
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+*/
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+
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/errno.h>
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+#include <linux/i2c.h>
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+#include <linux/delay.h>
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+#include <linux/string.h>
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+#include <asm/coldfire.h>
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+#include <asm/mcfsim.h>
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+#include <asm/types.h>
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+#include <linux/platform_device.h>
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+#include "i2c-mcf.h"
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+
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+
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+static struct i2c_algorithm coldfire_algorithm = {
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+ /*.name = "ColdFire I2C algorithm",
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+ .id = I2C_ALGO_SMBUS,*/
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+ .smbus_xfer = coldfire_i2c_access,
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+ .master_xfer = coldfire_i2c_master,
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+ .functionality = coldfire_func,
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+};
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+
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+
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+static struct i2c_adapter coldfire_adapter = {
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+ .owner = THIS_MODULE,
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+ .class = I2C_CLASS_HWMON,
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+ .algo = &coldfire_algorithm,
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+ .name = "ColdFire I2C adapter",
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+};
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+
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+
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+__u16 lastaddr;
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+__u16 lastop;
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+
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+static inline int coldfire_do_first_start(__u16 addr,__u16 flags)
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+{
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+ int err;
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+ /*
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+ * Generate a stop and put the I2C module into slave mode
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+ */
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
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+
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+ /*
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+ * Generate a new Start signal
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+ */
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+ err = coldfire_i2c_start(flags & I2C_M_RD ? I2C_SMBUS_READ : I2C_SMBUS_WRITE,
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+ addr, FIRST_START);
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+ if(err) return err;
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+
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+ lastaddr = addr;
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+ lastop = flags & I2C_M_RD; /* Ensure everything for new start */
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+ return 0;
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+}
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+
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+
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+/*
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+ * read one byte data from the I2C bus
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+ */
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+static int coldfire_read_data(u8 * const rxData, const enum I2C_ACK_TYPE ackType) {
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+
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+ int timeout;
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+
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MTX; /* master receive mode*/
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+
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+ if (ackType == NACK)
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+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /* generate NA */
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+ else
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK; /* generate ACK */
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+
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+
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+ /* read data from the I2C bus */
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+ *rxData = *MCF_I2C_I2DR;
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+
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+ /* printk(">>> %s I2DR data is %.2x \n", __FUNCTION__, *rxData); */
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+
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+ /* wait for data transfer to complete */
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+ timeout = 500;
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+ while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
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+ udelay(1);
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+ if (timeout <= 0)
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+ printk("%s - I2C IIF never set. Timeout is %d \n", __FUNCTION__,
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+ timeout);
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+
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+
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+ /* reset the interrupt bit */
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+ *MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
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+
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+ if (timeout <= 0 )
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+ return -1;
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+ else
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+ return 0;
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+
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+};
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+
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+
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+/*
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+ * write one byte data onto the I2C bus
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+ */
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+static int coldfire_write_data(const u8 txData) {
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+
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+ int timeout;
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+
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+ timeout = 500;
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+
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+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_MTX; /* I2C module into TX mode */
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+ *MCF_I2C_I2DR = txData; /* send the data */
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+
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+ /* wait for data transfer to complete */
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+ /* rely on the interrupt handling bit */
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+ timeout = 500;
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+ while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
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+ udelay(1);
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+ if (timeout <=0)
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+ printk("%s - I2C IIF never set. Timeout is %d \n", __FUNCTION__,
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+ timeout);
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+
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+
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+ /* reset the interrupt bit */
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+ *MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
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+
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+ if (timeout <= 0 )
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+ return -1;
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+ else
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+ return 0;
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+
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+};
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+
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+
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+
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+
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+/*
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+ * Generate I2C start or repeat start signal
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+ * Combine the 7 bit target_address and the R/W bit and put it onto the I2C bus
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+ */
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+static int coldfire_i2c_start(const char read_write, const u16 target_address, const enum I2C_START_TYPE start_type) {
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+
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+ int timeout;
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+
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+ /* printk(">>> %s START TYPE %s \n", __FUNCTION__,
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+ start_type == FIRST_START ? "FIRST_START":"REPEAT_START");*/
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+
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+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_IEN;
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+
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+ if (start_type == FIRST_START) {
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+ /* Make sure the I2C bus is idle */
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+ timeout = 500; /* 500us timeout */
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+ while (timeout-- && (*MCF_I2C_I2SR & MCF_I2C_I2SR_IBB))
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+ udelay(1);
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+ if (timeout <= 0) {
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+ printk("%s - I2C bus always busy in the past 500us timeout is %d \n", __FUNCTION__, timeout);
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+ goto check_rc;
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+ }
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+ /* generate a START and put the I2C module into MASTER TX mode*/
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+ *MCF_I2C_I2CR |= (MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX);
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+
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+ /* wait for bus busy to be set */
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+ timeout = 500;
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+ while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IBB))
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+ udelay(1);
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+ if (timeout <= 0) {
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+ printk("%s - I2C bus is never busy after START. Timeout is %d \n", __FUNCTION__, timeout);
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+ goto check_rc;
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+ }
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+
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+ } else {
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+ /* this is repeat START */
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+ udelay(500); /* need some delay before repeat start */
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+ *MCF_I2C_I2CR |= (MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_RSTA);
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+ }
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+
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+
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+ /* combine the R/W bit and the 7 bit target address and put it onto
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+ the I2C bus */
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+ *MCF_I2C_I2DR = ((target_address & 0x7F) << 1) | (read_write == I2C_SMBUS_WRITE ? 0x00 : 0x01);
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+
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+ /* wait for bus transfer to complete */
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+ /* when one byte transfer is completed, IIF set at the faling edge of
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+ the 9th clock */
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+ timeout = 500;
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+ while (timeout-- && !(*MCF_I2C_I2SR & MCF_I2C_I2SR_IIF))
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+ udelay(1);
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+ if (timeout <= 0)
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+ printk("%s - I2C IIF never set. Timeout is %d \n", __FUNCTION__, timeout);
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+
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+
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+check_rc:
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+ /* reset the interrupt bit */
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+ *MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF;
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+
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+ if (timeout <= 0)
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+ return -1;
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+ else
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+ return 0;
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+};
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+
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+
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+/*
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+ * 5282 SMBUS supporting functions
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+ */
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+
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+static s32 coldfire_i2c_access(struct i2c_adapter *adap, u16 addr,
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+ unsigned short flags, char read_write,
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+ u8 command, int size, union i2c_smbus_data *data)
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+{
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+ int rc = 0;
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+ u8 rxData, tempRxData[2];
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+
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+ switch (size) {
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+ case I2C_SMBUS_QUICK:
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+ rc = coldfire_i2c_start(read_write, addr, FIRST_START); /* generate START */
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+ break;
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+ case I2C_SMBUS_BYTE:
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+ rc = coldfire_i2c_start(read_write, addr, FIRST_START);
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+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_TXAK; /*generate NA */
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+ if (read_write == I2C_SMBUS_WRITE)
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+ rc += coldfire_write_data(command);
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+ else {
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+ coldfire_read_data(&rxData, NACK);/*dummy read*/
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+ rc += coldfire_read_data(&rxData, NACK);
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+ data->byte = rxData;
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+ }
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK; /* reset ACK bit */
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+ break;
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+ case I2C_SMBUS_BYTE_DATA:
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+ rc = coldfire_i2c_start(I2C_SMBUS_WRITE, addr, FIRST_START);
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+ rc += coldfire_write_data(command);
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+ if (read_write == I2C_SMBUS_WRITE)
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+ rc += coldfire_write_data(data->byte);
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+ else {
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+ /* This is SMBus READ Byte Data Request.
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+ Perform REPEAT START */
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+ rc += coldfire_i2c_start(I2C_SMBUS_READ, addr,
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+ REPEAT_START);
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+ coldfire_read_data(&rxData, ACK);/* dummy read*/
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+ /* Disable Acknowledge, generate STOP after
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+ next byte transfer */
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+ rc += coldfire_read_data(&rxData, NACK);
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+ data->byte = rxData;
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+ }
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK;/* reset to normal ACk */
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+ break;
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+ case I2C_SMBUS_PROC_CALL:
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+ case I2C_SMBUS_WORD_DATA:
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+ dev_info(&adap->dev, "size = I2C_SMBUS_WORD_DATA \n");
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+ rc = coldfire_i2c_start(I2C_SMBUS_WRITE, addr,
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+ FIRST_START);
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+ rc += coldfire_write_data(command);
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+ if (read_write == I2C_SMBUS_WRITE) {
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+ rc += coldfire_write_data(data->word & 0x00FF);
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+ rc += coldfire_write_data((data->word & 0x00FF) >> 8);
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+ } else {
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+ /* This is SMBUS READ WORD request.
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+ Peform REPEAT START */
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+ rc += coldfire_i2c_start(I2C_SMBUS_READ, addr,
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+ REPEAT_START);
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+ coldfire_read_data(&rxData, ACK);/* dummy read*/
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+ /* Disable Acknowledge, generate STOP after
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+ next byte transfer */
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+ /* read the MS byte from the device */
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+ rc += coldfire_read_data(&rxData, NACK);
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+ tempRxData[1] = rxData;
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+ /* read the LS byte from the device */
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+ rc += coldfire_read_data(&rxData, NACK);
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+ tempRxData[0] = rxData;
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+ /* the host driver expect little endian
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+ convention. Swap the byte */
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+ data->word = (tempRxData[0] << 8)|tempRxData[1];
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+ }
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK;
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+ break;
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+ case I2C_SMBUS_BLOCK_DATA:
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+ /* Not done yet */
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+ break;
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+ default:
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+ printk("Unsupported I2C size \n");
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+ rc = -1;
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+ break;
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+ };
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+
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+ /* Generate a STOP and put I2C module into slave mode */
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
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+
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+ /* restore interrupt */
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+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_IIEN;
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+
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+ if (rc < 0)
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+ return -1;
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+ else
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+ return 0;
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+};
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+
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+
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+/*
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+ * List the SMBUS functions supported by this I2C adaptor
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+ * Also tell the I2C Subsystem that we are able of master_xfer()
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+ */
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+static u32 coldfire_func(struct i2c_adapter *adapter)
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+{
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+ return(I2C_FUNC_SMBUS_QUICK |
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+ I2C_FUNC_SMBUS_BYTE |
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+ I2C_FUNC_SMBUS_PROC_CALL |
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+ I2C_FUNC_SMBUS_BYTE_DATA |
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+ I2C_FUNC_SMBUS_WORD_DATA |
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+ I2C_FUNC_I2C |
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+ I2C_FUNC_SMBUS_BLOCK_DATA);
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+};
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+
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+static int coldfire_i2c_master(struct i2c_adapter *adap,struct i2c_msg *msgs,
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+ int num)
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+{
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+ u8 dummyRead;
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+ struct i2c_msg *p;
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+ int i, err = 0;
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+ int ic=0;
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+
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+ lastaddr = 0;
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+ lastop = 8;
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+
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+ /* disable the IRQ, we are doing polling */
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+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_IIEN;
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+
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+ dev_dbg(&adap->dev,"Num of actions: %d\n", num);
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+
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+ for (i = 0; !err && i < num; i++) {
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+ p = &msgs[i];
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+
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+
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+ if (!p->len)
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+ {
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+ dev_dbg(&adap->dev,"p->len == 0!\n");
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+ continue;
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+ }
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+ /*
|
|
+ * Generate a new Start, if the target address differs from
|
|
+ * the last target, generate a stop in this case first
|
|
+ */
|
|
+ if(p->addr != lastaddr)
|
|
+ {
|
|
+ err = coldfire_do_first_start(p->addr,p->flags);
|
|
+ if(err)
|
|
+ {
|
|
+ dev_dbg(&adap->dev,"First Init failed!\n");
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ else if((p->flags & I2C_M_RD) != lastop)
|
|
+ {
|
|
+ /*
|
|
+ * If the Operational Mode changed, we need to do this
|
|
+ * here ...
|
|
+ */
|
|
+ dev_dbg(&adap->dev,"%s(): Direction changed, was: %d; is now: %d\n", __FUNCTION__, lastop, p->flags & I2C_M_RD);
|
|
+
|
|
+ /* Last op was an read, now it's write: complete stop
|
|
+ and reinit */
|
|
+ if (lastop & I2C_M_RD)
|
|
+ {
|
|
+ dev_dbg(&adap->dev,"%s(): The device is in read state, we must reset!\n", __FUNCTION__);
|
|
+ if((err = coldfire_do_first_start(p->addr,p->flags)))
|
|
+ break;
|
|
+ }
|
|
+ else
|
|
+ {
|
|
+ dev_dbg(&adap->dev,"%s(): We switchted to read mode\n",__FUNCTION__);
|
|
+ if((err = coldfire_i2c_start((p->flags & I2C_M_RD) ? I2C_SMBUS_READ : I2C_SMBUS_WRITE,
|
|
+ p->addr, REPEAT_START)))
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ lastop = p->flags & I2C_M_RD; /* Save the last op */
|
|
+ }
|
|
+
|
|
+ if (p->flags & I2C_M_RD)
|
|
+ {
|
|
+ /*
|
|
+ * When ever we get here, a new session was activated,
|
|
+ * so read a dummy byte
|
|
+ */
|
|
+ coldfire_read_data(&dummyRead, ACK);
|
|
+ /*
|
|
+ * read p->len -1 bytes with ACK to the slave,
|
|
+ * read the last byte without the ACK, to inform him
|
|
+ * about the stop afterwards
|
|
+ */
|
|
+ ic = 0;
|
|
+ while(!err && (ic < p->len-1 ))
|
|
+ {
|
|
+ err = coldfire_read_data(p->buf+ic, ACK );
|
|
+ ic++;
|
|
+ }
|
|
+ if(!err)
|
|
+ err = coldfire_read_data(p->buf+ic, NACK);
|
|
+ dev_dbg(&coldfire_adapter.dev,"read: %2x\n",p->buf[ic]);
|
|
+ }
|
|
+ else
|
|
+ {
|
|
+ if(p->len == 2)
|
|
+ dev_dbg(&coldfire_adapter.dev,"writing: 0x %2x %2x\n", p->buf[0], p->buf[1]);
|
|
+
|
|
+ /*
|
|
+ * Write data to the slave
|
|
+ */
|
|
+ for(ic=0; !err && ic < p->len; ic++)
|
|
+ {
|
|
+ err = coldfire_write_data(p->buf[ic]);
|
|
+ if(err)
|
|
+ {
|
|
+ dev_dbg(&coldfire_adapter.dev, "Failed to write data\n");
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * Put the device into slave mode to enable the STOP Generation
|
|
+ * (the RTC needs this)
|
|
+ */
|
|
+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_MSTA;
|
|
+
|
|
+ *MCF_I2C_I2CR &= ~MCF_I2C_I2CR_TXAK; /* reset the ACK bit */
|
|
+
|
|
+ /* restore interrupt */
|
|
+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_IIEN;
|
|
+
|
|
+ /* Return the number of messages processed, or the error code. */
|
|
+ if (err == 0)
|
|
+ err = num;
|
|
+ return err;
|
|
+}
|
|
+
|
|
+
|
|
+/*
|
|
+ * Initalize the 5282 I2C module
|
|
+ * Disable the 5282 I2C interrupt capability. Just use callback
|
|
+ */
|
|
+
|
|
+static int __init i2c_coldfire_init(void)
|
|
+{
|
|
+ int retval;
|
|
+ u8 dummyRead;
|
|
+
|
|
+#if defined(CONFIG_M532x) || defined(CONFIG_M5445X)
|
|
+ /*
|
|
+ * Initialize the GPIOs for I2C
|
|
+ */
|
|
+ MCF_GPIO_PAR_FECI2C |= (0
|
|
+ | MCF_GPIO_PAR_FECI2C_PAR_SDA(3)
|
|
+ | MCF_GPIO_PAR_FECI2C_PAR_SCL(3));
|
|
+#elif defined(CONFIG_M5253)
|
|
+ {
|
|
+ volatile u32 *reg;
|
|
+ /* GPIO Bit 41 = SCL0, Bit 42 = SDA0 */
|
|
+ reg = (volatile u32 *)(MCF_MBAR2 + MCFSIM2_GPIO1FUNC);
|
|
+ *reg &= 0xFFFFF9FF;
|
|
+ }
|
|
+#else
|
|
+ /* Initialize PASP0 and PASP1 to I2C functions, 5282 user guide 26-19 */
|
|
+ /* Port AS Pin Assignment Register (PASPAR) */
|
|
+ /* PASPA1 = 11 = AS1 pin is I2C SDA */
|
|
+ /* PASPA0 = 11 = AS0 pin is I2C SCL */
|
|
+ *MCF_GPIO_PASPAR |= 0x000F; /* u16 declaration */
|
|
+#endif
|
|
+
|
|
+
|
|
+ /* Set transmission frequency 0x15 = ~100kHz */
|
|
+ *MCF_I2C_I2FDR = 0x15;
|
|
+
|
|
+ /* set the 5282 I2C slave address though we never use it */
|
|
+ *MCF_I2C_I2ADR = 0x6A;
|
|
+
|
|
+ /* Enable I2C module and if IBB is set, do the special initialzation */
|
|
+ /* procedures as are documented at the 5282 User Guide page 24-11 */
|
|
+ *MCF_I2C_I2CR |= MCF_I2C_I2CR_IEN;
|
|
+ if ((*MCF_I2C_I2SR & MCF_I2C_I2SR_IBB) == 1) {
|
|
+ printk("%s - do special 5282 I2C init procedures \n",
|
|
+ __FUNCTION__);
|
|
+ *MCF_I2C_I2CR = 0x00;
|
|
+ *MCF_I2C_I2CR = 0xA0;
|
|
+ dummyRead = *MCF_I2C_I2DR;
|
|
+ *MCF_I2C_I2SR = 0x00;
|
|
+ *MCF_I2C_I2CR = 0x00;
|
|
+ }
|
|
+
|
|
+ /* default I2C mode is - slave and receive */
|
|
+ *MCF_I2C_I2CR &= ~(MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX);
|
|
+
|
|
+ coldfire_adapter.dev.parent = &platform_bus;
|
|
+ retval = i2c_add_adapter(&coldfire_adapter);
|
|
+
|
|
+ if (retval < 0)
|
|
+ printk("%s - return code is: %d \n", __FUNCTION__, retval);
|
|
+
|
|
+ return retval;
|
|
+};
|
|
+
|
|
+
|
|
+/*
|
|
+ * I2C module exit function
|
|
+ */
|
|
+
|
|
+static void __exit i2c_coldfire_exit(void)
|
|
+{
|
|
+ /* disable I2C and Interrupt */
|
|
+ *MCF_I2C_I2CR &= ~(MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_IIEN);
|
|
+ i2c_del_adapter(&coldfire_adapter);
|
|
+
|
|
+};
|
|
+
|
|
+
|
|
+MODULE_AUTHOR("Derek CL Cheung <derek.cheung@sympatico.ca>");
|
|
+MODULE_DESCRIPTION("MCF5282 I2C adaptor");
|
|
+MODULE_LICENSE("GPL");
|
|
+
|
|
+module_init(i2c_coldfire_init);
|
|
+module_exit(i2c_coldfire_exit);
|
|
--- /dev/null
|
|
+++ b/drivers/i2c/busses/i2c-mcf.h
|
|
@@ -0,0 +1,75 @@
|
|
+/*
|
|
+ i2c-mcf.h - header file for i2c-mcf.c
|
|
+
|
|
+ Copyright (c) 2005, Derek CL Cheung <derek.cheung@sympatico.ca>
|
|
+ <http://www3.sympatico.ca/derek.cheung>
|
|
+
|
|
+ Copyright (c) 2006-2007, emlix
|
|
+ Sebastian Hess <sh@emlix.com>
|
|
+
|
|
+ Copyright (c) 2006-2007 Freescale Semiconductor, Inc
|
|
+ Yaroslav Vinogradov <yaroslav.vinogradov@freescale.com>
|
|
+ Matt Waddel <Matt.Waddel@freescale.com>
|
|
+
|
|
+ This program is free software; you can redistribute it and/or modify
|
|
+ it under the terms of the GNU General Public License as published by
|
|
+ the Free Software Foundation; either version 2 of the License, or
|
|
+ (at your option) any later version.
|
|
+
|
|
+ This program is distributed in the hope that it will be useful,
|
|
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ GNU General Public License for more details.
|
|
+
|
|
+ You should have received a copy of the GNU General Public License
|
|
+ along with this program; if not, write to the Free Software
|
|
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
+
|
|
+ Changes:
|
|
+ v0.1 26 March 2005
|
|
+ Initial Release - developed on uClinux with 2.6.9 kernel
|
|
+ v0.2 29 May 2006
|
|
+ Modified to be more generic and added support for
|
|
+ i2c_master_xfer
|
|
+*/
|
|
+
|
|
+
|
|
+#ifndef __I2C_MCF_H__
|
|
+#define __I2C_MCF_H__
|
|
+
|
|
+enum I2C_START_TYPE { FIRST_START, REPEAT_START };
|
|
+enum I2C_ACK_TYPE { ACK, NACK};
|
|
+
|
|
+/* Function prototypes */
|
|
+static u32 coldfire_func(struct i2c_adapter *adapter);
|
|
+static s32 coldfire_i2c_access(struct i2c_adapter *adap, u16 address,
|
|
+ unsigned short flags, char read_write,
|
|
+ u8 command, int size, union i2c_smbus_data *data);
|
|
+static int coldfire_write_data(const u8 data);
|
|
+static int coldfire_i2c_start(const char read_write, const u16 target_address, const enum I2C_START_TYPE i2c_start);
|
|
+static int coldfire_read_data(u8 * const rxData, const enum I2C_ACK_TYPE ackType);
|
|
+static int coldfire_i2c_master(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
|
|
+void dumpReg(char *, u16 addr, u8 data);
|
|
+
|
|
+#define MCF_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
|
|
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
|
|
+
|
|
+/* I2C Control Register */
|
|
+#define MCF_I2C_I2CR_IEN (0x80) /* I2C enable */
|
|
+#define MCF_I2C_I2CR_IIEN (0x40) /* interrupt enable */
|
|
+#define MCF_I2C_I2CR_MSTA (0x20) /* master/slave mode */
|
|
+#define MCF_I2C_I2CR_MTX (0x10) /* transmit/receive mode */
|
|
+#define MCF_I2C_I2CR_TXAK (0x08) /* transmit acknowledge enable */
|
|
+#define MCF_I2C_I2CR_RSTA (0x04) /* repeat start */
|
|
+
|
|
+/* I2C Status Register */
|
|
+#define MCF_I2C_I2SR_ICF (0x80) /* data transfer bit */
|
|
+#define MCF_I2C_I2SR_IAAS (0x40) /* I2C addressed as a slave */
|
|
+#define MCF_I2C_I2SR_IBB (0x20) /* I2C bus busy */
|
|
+#define MCF_I2C_I2SR_IAL (0x10) /* aribitration lost */
|
|
+#define MCF_I2C_I2SR_SRW (0x04) /* slave read/write */
|
|
+#define MCF_I2C_I2SR_IIF (0x02) /* I2C interrupt */
|
|
+#define MCF_I2C_I2SR_RXAK (0x01) /* received acknowledge */
|
|
+
|
|
+/********************************************************************/
|
|
+#endif /* __I2C_MCF_H__ */
|