mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 14:31:53 +02:00
29ec26ff1b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21438 3c298f89-4303-0410-b956-a3cf2f4a3e73
548 lines
14 KiB
Diff
548 lines
14 KiB
Diff
From 88aacb09dfdf4d85c507757524166433204260e8 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 24 Apr 2010 12:14:46 +0200
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Subject: [PATCH] Add jz4740 nand driver
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---
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drivers/mtd/nand/Kconfig | 6 +
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drivers/mtd/nand/Makefile | 1 +
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drivers/mtd/nand/jz4740_nand.c | 444 +++++++++++++++++++++++++++++++++++++++
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include/linux/mtd/jz4740_nand.h | 34 +++
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include/mtd/mtd-abi.h | 2 +-
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5 files changed, 486 insertions(+), 1 deletions(-)
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create mode 100644 drivers/mtd/nand/jz4740_nand.c
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create mode 100644 include/linux/mtd/jz4740_nand.h
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diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
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index 42e5ea4..6f587b8 100644
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -488,4 +488,10 @@ config MTD_NAND_W90P910
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This enables the driver for the NAND Flash on evaluation board based
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on w90p910.
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+config MTD_NAND_JZ4740
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+ tristate "Support NAND Flash device on Jz4740 board"
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+ depends on SOC_JZ4740
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+ help
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+ Support NAND Flash device on Jz4740 board
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+
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endif # MTD_NAND
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diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
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index 1407bd1..e56bd52 100644
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -42,5 +42,6 @@ obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o
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obj-$(CONFIG_MTD_NAND_W90P910) += w90p910_nand.o
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obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
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obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
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+obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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nand-objs := nand_base.o nand_bbt.o
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diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
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new file mode 100644
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index 0000000..7b3477d
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--- /dev/null
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+++ b/drivers/mtd/nand/jz4740_nand.c
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@@ -0,0 +1,444 @@
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+/*
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+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4720/JZ4740 SoC NAND controller driver
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/ioport.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/mtd/partitions.h>
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+
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+#include <linux/mtd/jz4740_nand.h>
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+#include <linux/gpio.h>
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+
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+#define JZ_REG_NAND_CTRL 0x50
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+#define JZ_REG_NAND_ECC_CTRL 0x100
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+#define JZ_REG_NAND_DATA 0x104
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+#define JZ_REG_NAND_PAR0 0x108
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+#define JZ_REG_NAND_PAR1 0x10C
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+#define JZ_REG_NAND_PAR2 0x110
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+#define JZ_REG_NAND_IRQ_STAT 0x114
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+#define JZ_REG_NAND_IRQ_CTRL 0x118
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+#define JZ_REG_NAND_ERR(x) (0x11C + (x << 2))
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+
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+#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
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+#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
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+#define JZ_NAND_ECC_CTRL_RS BIT(2)
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+#define JZ_NAND_ECC_CTRL_RESET BIT(1)
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+#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
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+
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+#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
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+#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
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+#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
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+#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
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+#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
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+#define JZ_NAND_STATUS_ERROR BIT(0)
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+
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+#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1)
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+#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1)
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+
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+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
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+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
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+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
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+
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+struct jz_nand {
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+ struct mtd_info mtd;
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+ struct nand_chip chip;
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+ void __iomem *base;
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+ struct resource *mem;
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+
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+ struct jz_nand_platform_data *pdata;
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+ bool is_reading;
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+};
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+
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+static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
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+{
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+ return container_of(mtd, struct jz_nand, mtd);
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+}
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+
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+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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+{
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+ struct jz_nand *nand = mtd_to_jz_nand(mtd);
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+ struct nand_chip *chip = mtd->priv;
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+ uint32_t reg;
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+
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+ if (ctrl & NAND_CTRL_CHANGE) {
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+ BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
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+ if (ctrl & NAND_ALE)
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+ chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
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+ else if (ctrl & NAND_CLE)
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+ chip->IO_ADDR_W = JZ_NAND_CMD_ADDR;
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+ else
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+ chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
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+
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+ reg = readl(nand->base + JZ_REG_NAND_CTRL);
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+ if (ctrl & NAND_NCE)
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+ reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
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+ else
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+ reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
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+ writel(reg, nand->base + JZ_REG_NAND_CTRL);
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+ }
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+ if (dat != NAND_CMD_NONE)
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+ writeb(dat, chip->IO_ADDR_W);
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+}
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+
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+static int jz_nand_dev_ready(struct mtd_info *mtd)
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+{
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+ struct jz_nand *nand = mtd_to_jz_nand(mtd);
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+ return gpio_get_value_cansleep(nand->pdata->busy_gpio);
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+}
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+
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+static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
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+{
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+ struct jz_nand *nand = mtd_to_jz_nand(mtd);
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+ uint32_t reg;
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+
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+
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+ writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
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+ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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+
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+ reg |= JZ_NAND_ECC_CTRL_RESET;
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+ reg |= JZ_NAND_ECC_CTRL_ENABLE;
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+ reg |= JZ_NAND_ECC_CTRL_RS;
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+
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+ switch (mode) {
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+ case NAND_ECC_READ:
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+ reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
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+ nand->is_reading = true;
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+ break;
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+ case NAND_ECC_WRITE:
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+ reg |= JZ_NAND_ECC_CTRL_ENCODING;
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+ nand->is_reading = false;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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+}
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+
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+
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+static int jz_nand_calculate_ecc_rs(struct mtd_info* mtd, const uint8_t *dat,
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+ uint8_t *ecc_code)
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+{
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+ struct jz_nand *nand = mtd_to_jz_nand(mtd);
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+ uint32_t reg, status;
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+ int i;
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+ static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
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+ 0x8b, 0xff, 0xb7, 0x6f};
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+
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+ if (nand->is_reading)
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+ return 0;
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+
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+ do {
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+ status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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+ } while (!(status & JZ_NAND_STATUS_ENC_FINISH));
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+
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+ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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+ reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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+ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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+
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+ for (i = 0; i < 9; ++i)
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+ ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
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+
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+ /* If the written data is completly 0xff, we also want to write 0xff as
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+ * ecc, otherwise we will get in trouble when doing subpage writes. */
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+ if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
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+ memset(ecc_code, 0xff, 9);
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+
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+ return 0;
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+}
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+
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+/*#define printkd printk*/
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+#define printkd(...)
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+
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+static void correct_data(uint8_t *dat, int index, int mask)
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+{
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+ int offset = index & 0x7;
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+ uint16_t data;
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+ printkd("correct: ");
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+
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+ index += (index >> 3);
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+
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+ data = dat[index];
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+ data |= dat[index+1] << 8;
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+
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+ printkd("0x%x -> ", data);
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+
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+ mask ^= (data >> offset) & 0x1ff;
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+ data &= ~(0x1ff << offset);
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+ data |= (mask << offset);
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+
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+ printkd("0x%x\n", data);
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+
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+ dat[index] = data & 0xff;
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+ dat[index+1] = (data >> 8) & 0xff;
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+}
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+
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+static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
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+ uint8_t *read_ecc, uint8_t *calc_ecc)
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+{
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+ struct jz_nand *nand = mtd_to_jz_nand(mtd);
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+ int i, error_count, index;
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+ uint32_t reg, status, error;
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+ uint32_t t;
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+
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+ t = read_ecc[0];
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+
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+ if (t == 0xff) {
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+ for (i = 1; i < 9; ++i)
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+ t &= read_ecc[i];
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+
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+ t &= dat[0];
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+ t &= dat[nand->chip.ecc.size / 2];
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+ t &= dat[nand->chip.ecc.size - 1];
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+
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+ if (t == 0xff) {
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+ for (i = 1; i < nand->chip.ecc.size - 1; ++i)
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+ t &= dat[i];
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+ if (t == 0xff)
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+ return 0;
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+ }
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+ }
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+
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+ for (i = 0; i < 9; ++i)
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+ writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
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+
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+ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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+ reg |= JZ_NAND_ECC_CTRL_PAR_READY;
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+ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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+
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+ do {
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+ status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
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+ } while (!(status & JZ_NAND_STATUS_DEC_FINISH));
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+
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+ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
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+ reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
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+ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
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+
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+ if (status & JZ_NAND_STATUS_ERROR) {
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+ if (status & JZ_NAND_STATUS_UNCOR_ERROR) {
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+ printkd("uncorrectable ecc:");
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+ for (i = 0; i < 9; ++i)
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+ printkd(" 0x%x", read_ecc[i]);
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+ printkd("\n");
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+ printkd("uncorrectable data:");
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+ for (i = 0; i < 32; ++i)
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+ printkd(" 0x%x", dat[i]);
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+ printkd("\n");
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+ return -1;
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+ }
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+
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+ error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
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+
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+ printkd("error_count: %d %x\n", error_count, status);
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+
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+ for (i = 0; i < error_count; ++i) {
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+ error = readl(nand->base + JZ_REG_NAND_ERR(i));
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+ index = ((error >> 16) & 0x1ff) - 1;
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+ if (index >= 0 && index < 512)
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+ correct_data(dat, index, error & 0x1ff);
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+ }
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+
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+ return error_count;
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+ }
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+
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+ return 0;
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+}
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+
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+
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+
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+#ifdef CONFIG_MTD_CMDLINE_PARTS
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+static const char *part_probes[] = {"cmdline", NULL};
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+#endif
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+
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+static int __devinit jz_nand_probe(struct platform_device *pdev)
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+{
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+ int ret;
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+ struct jz_nand *nand;
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+ struct nand_chip *chip;
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+ struct mtd_info *mtd;
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+ struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
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+#ifdef CONFIG_MTD_PARTITIONS
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+ struct mtd_partition *partition_info;
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+ int num_partitions = 0;
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+#endif
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+
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+ nand = kzalloc(sizeof(*nand), GFP_KERNEL);
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+ if (!nand) {
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+ dev_err(&pdev->dev, "Failed to allocate device structure.\n");
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+ return -ENOMEM;
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+ }
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+
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+ nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!nand->mem) {
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+ dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
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+ ret = -ENOENT;
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+ goto err_free;
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+ }
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+
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+ nand->mem = request_mem_region(nand->mem->start,
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+ resource_size(nand->mem), pdev->name);
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+
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+ if (!nand->mem) {
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+ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
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+ ret = -EBUSY;
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+ goto err_free;
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+ }
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+
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+ nand->base = ioremap(nand->mem->start, resource_size(nand->mem));
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+
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+ if (!nand->base) {
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+ dev_err(&pdev->dev, "Failed to ioremap mmio memory region\n");
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+ ret = -EBUSY;
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+ goto err_release_mem;
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+ }
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+
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+ if (pdata && gpio_is_valid(pdata->busy_gpio)) {
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+ ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
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+ if (ret) {
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+ dev_err(&pdev->dev,
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+ "Failed to request busy gpio %d: %d\n",
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+ pdata->busy_gpio, ret);
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+ goto err_iounmap;
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+ }
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+ }
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+
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+ mtd = &nand->mtd;
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+ chip = &nand->chip;
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+ mtd->priv = chip;
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+ mtd->owner = THIS_MODULE;
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+ mtd->name = "jz4740-nand";
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+
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+ chip->ecc.hwctl = jz_nand_hwctl;
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+
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+ chip->ecc.calculate = jz_nand_calculate_ecc_rs;
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+ chip->ecc.correct = jz_nand_correct_ecc_rs;
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+ chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
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+ chip->ecc.size = 512;
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+ chip->ecc.bytes = 9;
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+ if (pdata)
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+ chip->ecc.layout = pdata->ecc_layout;
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+
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+ chip->chip_delay = 50;
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+ chip->cmd_ctrl = jz_nand_cmd_ctrl;
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+
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+ if (pdata && gpio_is_valid(pdata->busy_gpio))
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+ chip->dev_ready = jz_nand_dev_ready;
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+
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+ chip->IO_ADDR_R = JZ_NAND_DATA_ADDR;
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+ chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
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+
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+ nand->pdata = pdata;
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+ platform_set_drvdata(pdev, nand);
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+
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+ ret = nand_scan_ident(mtd, 1);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Failed to scan nand\n");
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+ goto err_gpio_free;
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+ }
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+
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+ if (pdata && pdata->ident_callback) {
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+ pdata->ident_callback(pdev, chip, &pdata->partitions,
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+ &pdata->num_partitions);
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+ }
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+
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+ ret = nand_scan_tail(mtd);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Failed to scan nand\n");
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+ goto err_gpio_free;
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+ }
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+
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+#ifdef CONFIG_MTD_PARTITIONS
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+#ifdef CONFIG_MTD_CMDLINE_PARTS
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+ num_partitions = parse_mtd_partitions(mtd, part_probes,
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+ &partition_info, 0);
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+#endif
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+ if (num_partitions <= 0 && pdata) {
|
|
+ num_partitions = pdata->num_partitions;
|
|
+ partition_info = pdata->partitions;
|
|
+ }
|
|
+
|
|
+ if (num_partitions > 0)
|
|
+ ret = add_mtd_partitions(mtd, partition_info, num_partitions);
|
|
+ else
|
|
+#endif
|
|
+ ret = add_mtd_device(mtd);
|
|
+
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "Failed to add mtd device\n");
|
|
+ goto err_nand_release;
|
|
+ }
|
|
+
|
|
+ dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
|
|
+
|
|
+ return 0;
|
|
+err_nand_release:
|
|
+ nand_release(&nand->mtd);
|
|
+err_gpio_free:
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+ gpio_free(pdata->busy_gpio);
|
|
+err_iounmap:
|
|
+ iounmap(nand->base);
|
|
+err_release_mem:
|
|
+ release_mem_region(nand->mem->start, resource_size(nand->mem));
|
|
+err_free:
|
|
+ kfree(nand);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void __devexit jz_nand_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct jz_nand *nand = platform_get_drvdata(pdev);
|
|
+
|
|
+ nand_release(&nand->mtd);
|
|
+
|
|
+ iounmap(nand->base);
|
|
+
|
|
+ release_mem_region(nand->mem->start, resource_size(nand->mem));
|
|
+
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+ kfree(nand);
|
|
+}
|
|
+
|
|
+struct platform_driver jz_nand_driver = {
|
|
+ .probe = jz_nand_probe,
|
|
+ .remove = __devexit_p(jz_nand_probe),
|
|
+ .driver = {
|
|
+ .name = "jz4740-nand",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init jz_nand_init(void)
|
|
+{
|
|
+ return platform_driver_register(&jz_nand_driver);
|
|
+}
|
|
+module_init(jz_nand_init);
|
|
+
|
|
+static void __exit jz_nand_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&jz_nand_driver);
|
|
+}
|
|
+module_exit(jz_nand_exit);
|
|
+
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
+MODULE_DESCRIPTION("NAND controller driver for JZ4720/JZ4740 SoC");
|
|
+MODULE_ALIAS("platform:jz4740-nand");
|
|
+MODULE_ALIAS("platform:jz4720-nand");
|
|
diff --git a/include/linux/mtd/jz4740_nand.h b/include/linux/mtd/jz4740_nand.h
|
|
new file mode 100644
|
|
index 0000000..8254e4c
|
|
--- /dev/null
|
|
+++ b/include/linux/mtd/jz4740_nand.h
|
|
@@ -0,0 +1,34 @@
|
|
+/*
|
|
+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
|
|
+ * JZ4720/JZ4740 SoC NAND controller driver
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License along
|
|
+ * with this program; if not, write to the Free Software Foundation, Inc.,
|
|
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
+ *
|
|
+ */
|
|
+
|
|
+#ifndef __JZ_NAND_H__
|
|
+#define __JZ_NAND_H__
|
|
+
|
|
+#include <linux/mtd/nand.h>
|
|
+#include <linux/mtd/partitions.h>
|
|
+
|
|
+struct jz_nand_platform_data {
|
|
+ int num_partitions;
|
|
+ struct mtd_partition *partitions;
|
|
+
|
|
+ struct nand_ecclayout *ecc_layout;
|
|
+
|
|
+ unsigned int busy_gpio;
|
|
+
|
|
+ void (*ident_callback)(struct platform_device *, struct nand_chip *,
|
|
+ struct mtd_partition **, int *num_partitions);
|
|
+};
|
|
+
|
|
+#endif
|
|
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
|
|
index be51ae2..cf90168 100644
|
|
--- a/include/mtd/mtd-abi.h
|
|
+++ b/include/mtd/mtd-abi.h
|
|
@@ -134,7 +134,7 @@ struct nand_oobfree {
|
|
*/
|
|
struct nand_ecclayout {
|
|
__u32 eccbytes;
|
|
- __u32 eccpos[64];
|
|
+ __u32 eccpos[72];
|
|
__u32 oobavail;
|
|
struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
|
|
};
|
|
--
|
|
1.5.6.5
|
|
|