mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-05 21:24:04 +02:00
e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
232 lines
6.1 KiB
Diff
232 lines
6.1 KiB
Diff
From 958e444a5a7750c407ed0c90af28f74295478e99 Mon Sep 17 00:00:00 2001
|
|
From: Rene Bolldorf <xsecute@googlemail.com>
|
|
Date: Thu, 17 Nov 2011 14:25:09 +0000
|
|
Subject: [PATCH 17/27] MIPS: Initial PCI support for Atheros 724x SoCs.
|
|
|
|
[ralf@linux-mips.org: Fixed the odd formatting of all break statements.]
|
|
|
|
Signed-off-by: Rene Bolldorf <xsecute@googlemail.com>
|
|
Cc: linux-mips@linux-mips.org
|
|
Cc: linux-kernel@vger.kernel.org
|
|
Patchwork: https://patchwork.linux-mips.org/patch/3019/
|
|
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
---
|
|
arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 +++
|
|
arch/mips/pci/Makefile | 1 +
|
|
arch/mips/pci/pci-ath724x.c | 174 ++++++++++++++++++++++++
|
|
3 files changed, 196 insertions(+), 0 deletions(-)
|
|
create mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h
|
|
create mode 100644 arch/mips/pci/pci-ath724x.c
|
|
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
|
|
@@ -0,0 +1,21 @@
|
|
+/*
|
|
+ * Atheros 724x PCI support
|
|
+ *
|
|
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ */
|
|
+
|
|
+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
|
|
+#define __ASM_MACH_ATH79_PCI_ATH724X_H
|
|
+
|
|
+struct ath724x_pci_data {
|
|
+ int irq;
|
|
+ void *pdata;
|
|
+};
|
|
+
|
|
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
|
|
+
|
|
+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
|
|
--- a/arch/mips/pci/Makefile
|
|
+++ b/arch/mips/pci/Makefile
|
|
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
|
|
obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
|
|
ops-bcm63xx.o
|
|
obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
|
|
+obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
|
|
|
|
#
|
|
# These are still pretty much in the old state, watch, go blind.
|
|
--- /dev/null
|
|
+++ b/arch/mips/pci/pci-ath724x.c
|
|
@@ -0,0 +1,174 @@
|
|
+/*
|
|
+ * Atheros 724x PCI support
|
|
+ *
|
|
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ */
|
|
+
|
|
+#include <linux/pci.h>
|
|
+#include <asm/mach-ath79/pci-ath724x.h>
|
|
+
|
|
+#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
|
|
+#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
|
|
+
|
|
+#define ATH724X_PCI_DEV_BASE 0x14000000
|
|
+#define ATH724X_PCI_MEM_BASE 0x10000000
|
|
+#define ATH724X_PCI_MEM_SIZE 0x08000000
|
|
+
|
|
+static DEFINE_SPINLOCK(ath724x_pci_lock);
|
|
+static struct ath724x_pci_data *pci_data;
|
|
+static int pci_data_size;
|
|
+
|
|
+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
|
|
+ int size, uint32_t *value)
|
|
+{
|
|
+ unsigned long flags, addr, tval, mask;
|
|
+
|
|
+ if (devfn)
|
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
|
+
|
|
+ if (where & (size - 1))
|
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
+
|
|
+ spin_lock_irqsave(&ath724x_pci_lock, flags);
|
|
+
|
|
+ switch (size) {
|
|
+ case 1:
|
|
+ addr = where & ~3;
|
|
+ mask = 0xff000000 >> ((where % 4) * 8);
|
|
+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
|
+ tval = tval & ~mask;
|
|
+ *value = (tval >> ((4 - (where % 4))*8));
|
|
+ break;
|
|
+ case 2:
|
|
+ addr = where & ~3;
|
|
+ mask = 0xffff0000 >> ((where % 4)*8);
|
|
+ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
|
|
+ tval = tval & ~mask;
|
|
+ *value = (tval >> ((4 - (where % 4))*8));
|
|
+ break;
|
|
+ case 4:
|
|
+ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
|
|
+ break;
|
|
+ default:
|
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
+
|
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
+ }
|
|
+
|
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
+
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
+}
|
|
+
|
|
+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
|
|
+ int size, uint32_t value)
|
|
+{
|
|
+ unsigned long flags, tval, addr, mask;
|
|
+
|
|
+ if (devfn)
|
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
|
+
|
|
+ if (where & (size - 1))
|
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
+
|
|
+ spin_lock_irqsave(&ath724x_pci_lock, flags);
|
|
+
|
|
+ switch (size) {
|
|
+ case 1:
|
|
+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
|
+ mask = 0xff000000 >> ((where % 4)*8);
|
|
+ tval = reg_read(addr);
|
|
+ tval = tval & ~mask;
|
|
+ tval |= (value << ((4 - (where % 4))*8)) & mask;
|
|
+ reg_write(addr, tval);
|
|
+ break;
|
|
+ case 2:
|
|
+ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
|
|
+ mask = 0xffff0000 >> ((where % 4)*8);
|
|
+ tval = reg_read(addr);
|
|
+ tval = tval & ~mask;
|
|
+ tval |= (value << ((4 - (where % 4))*8)) & mask;
|
|
+ reg_write(addr, tval);
|
|
+ break;
|
|
+ case 4:
|
|
+ reg_write((ATH724X_PCI_DEV_BASE + where), value);
|
|
+ break;
|
|
+ default:
|
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
+
|
|
+ return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
+ }
|
|
+
|
|
+ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
|
|
+
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
+}
|
|
+
|
|
+static struct pci_ops ath724x_pci_ops = {
|
|
+ .read = ath724x_pci_read,
|
|
+ .write = ath724x_pci_write,
|
|
+};
|
|
+
|
|
+static struct resource ath724x_io_resource = {
|
|
+ .name = "PCI IO space",
|
|
+ .start = 0,
|
|
+ .end = 0,
|
|
+ .flags = IORESOURCE_IO,
|
|
+};
|
|
+
|
|
+static struct resource ath724x_mem_resource = {
|
|
+ .name = "PCI memory space",
|
|
+ .start = ATH724X_PCI_MEM_BASE,
|
|
+ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
|
|
+ .flags = IORESOURCE_MEM,
|
|
+};
|
|
+
|
|
+static struct pci_controller ath724x_pci_controller = {
|
|
+ .pci_ops = &ath724x_pci_ops,
|
|
+ .io_resource = &ath724x_io_resource,
|
|
+ .mem_resource = &ath724x_mem_resource,
|
|
+};
|
|
+
|
|
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
|
|
+{
|
|
+ pci_data = data;
|
|
+ pci_data_size = size;
|
|
+}
|
|
+
|
|
+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
|
|
+{
|
|
+ unsigned int devfn = dev->devfn;
|
|
+ int irq = -1;
|
|
+
|
|
+ if (devfn > pci_data_size - 1)
|
|
+ return irq;
|
|
+
|
|
+ irq = pci_data[devfn].irq;
|
|
+
|
|
+ return irq;
|
|
+}
|
|
+
|
|
+int pcibios_plat_dev_init(struct pci_dev *dev)
|
|
+{
|
|
+ unsigned int devfn = dev->devfn;
|
|
+
|
|
+ if (devfn > pci_data_size - 1)
|
|
+ return PCIBIOS_DEVICE_NOT_FOUND;
|
|
+
|
|
+ dev->dev.platform_data = pci_data[devfn].pdata;
|
|
+
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
+}
|
|
+
|
|
+static int __init ath724x_pcibios_init(void)
|
|
+{
|
|
+ register_pci_controller(&ath724x_pci_controller);
|
|
+
|
|
+ return PCIBIOS_SUCCESSFUL;
|
|
+}
|
|
+
|
|
+arch_initcall(ath724x_pcibios_init);
|