mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-21 21:58:03 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23939 3c298f89-4303-0410-b956-a3cf2f4a3e73
87 lines
2.6 KiB
Diff
87 lines
2.6 KiB
Diff
From 3924996bab2845bdf9a9d16ff7c20445de1ab55d Mon Sep 17 00:00:00 2001
|
|
From: Nicolas Pitre <nico@fluxnic.net>
|
|
Date: Thu, 21 Oct 2010 15:48:33 -0400
|
|
Subject: [PATCH] [ARM] Kirkwood: restrict the scope of the PCIe reset workaround
|
|
|
|
Commit 21f0ba90a447 "orion/kirkwood: reset PCIe unit on boot" made the
|
|
reset of the PCIe unit unconditional. While this may fix problems on some
|
|
targets, this also causes problems on other targets.
|
|
|
|
Saeed Bishara <saeed@marvell.com> said about the original problem: "We
|
|
couln't pinpoint the root cause of this issue, actually we failed to
|
|
reproduce that issue."
|
|
|
|
So let's restrict the reset of the PCIe unit only to the target where
|
|
the original problem was observed.
|
|
|
|
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
|
|
---
|
|
arch/arm/mach-kirkwood/ts41x-setup.c | 14 +++++++++++++-
|
|
arch/arm/plat-orion/include/plat/pcie.h | 3 +++
|
|
arch/arm/plat-orion/pcie.c | 5 -----
|
|
3 files changed, 16 insertions(+), 6 deletions(-)
|
|
|
|
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
|
|
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
|
|
@@ -27,6 +27,10 @@
|
|
#include "mpp.h"
|
|
#include "tsx1x-common.h"
|
|
|
|
+/* for the PCIe reset workaround */
|
|
+#include <plat/pcie.h>
|
|
+
|
|
+
|
|
#define QNAP_TS41X_JUMPER_JP1 45
|
|
|
|
static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
|
|
@@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void)
|
|
|
|
static int __init ts41x_pci_init(void)
|
|
{
|
|
- if (machine_is_ts41x())
|
|
+ if (machine_is_ts41x()) {
|
|
+ /*
|
|
+ * Without this explicit reset, the PCIe SATA controller
|
|
+ * (Marvell 88sx7042/sata_mv) is known to stop working
|
|
+ * after a few minutes.
|
|
+ */
|
|
+ orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
|
|
+
|
|
kirkwood_pcie_init(KW_PCIE0);
|
|
+ }
|
|
|
|
return 0;
|
|
}
|
|
--- a/arch/arm/plat-orion/include/plat/pcie.h
|
|
+++ b/arch/arm/plat-orion/include/plat/pcie.h
|
|
@@ -11,12 +11,15 @@
|
|
#ifndef __PLAT_PCIE_H
|
|
#define __PLAT_PCIE_H
|
|
|
|
+struct pci_bus;
|
|
+
|
|
u32 orion_pcie_dev_id(void __iomem *base);
|
|
u32 orion_pcie_rev(void __iomem *base);
|
|
int orion_pcie_link_up(void __iomem *base);
|
|
int orion_pcie_x4_mode(void __iomem *base);
|
|
int orion_pcie_get_local_bus_nr(void __iomem *base);
|
|
void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
|
|
+void orion_pcie_reset(void __iomem *base);
|
|
void orion_pcie_setup(void __iomem *base,
|
|
struct mbus_dram_target_info *dram);
|
|
int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
|
|
--- a/arch/arm/plat-orion/pcie.c
|
|
+++ b/arch/arm/plat-orion/pcie.c
|
|
@@ -182,11 +182,6 @@ void __init orion_pcie_setup(void __iome
|
|
u32 mask;
|
|
|
|
/*
|
|
- * soft reset PCIe unit
|
|
- */
|
|
- orion_pcie_reset(base);
|
|
-
|
|
- /*
|
|
* Point PCIe unit MBUS decode windows to DRAM space.
|
|
*/
|
|
orion_pcie_setup_wins(base, dram);
|