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git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 14:24:03 +02:00
995 lines
22 KiB
C
995 lines
22 KiB
C
/*
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* linux/drivers/mmc/jz_mmc.c - JZ SD/MMC driver
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*
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* Copyright (C) 2005 - 2008 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mm.h>
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#include <linux/signal.h>
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#include <linux/pm.h>
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#include <linux/scatterlist.h>
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#include <asm/io.h>
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#include <asm/scatterlist.h>
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#include <asm/jzsoc.h>
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#include "jz_mmc.h"
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#define DRIVER_NAME "jz-mmc"
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#define NR_SG 1
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#if defined(CONFIG_SOC_JZ4725) || defined(CONFIG_SOC_JZ4720)
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#undef USE_DMA
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#else
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#define USE_DMA
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#endif
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struct jz_mmc_host {
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struct mmc_host *mmc;
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spinlock_t lock;
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struct {
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int len;
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int dir;
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} dma;
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struct {
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int index;
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int offset;
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int len;
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} pio;
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int irq;
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unsigned int clkrt;
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unsigned int cmdat;
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unsigned int imask;
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unsigned int power_mode;
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struct jz_mmc_platform_data *pdata;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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dma_addr_t sg_dma;
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struct jzsoc_dma_desc *sg_cpu;
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unsigned int dma_len;
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unsigned int dma_dir;
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struct pm_dev *pmdev;
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};
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static int r_type = 0;
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#define MMC_IRQ_MASK() \
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do { \
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REG_MSC_IMASK = 0xff; \
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REG_MSC_IREG = 0xff; \
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} while (0)
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static int rxdmachan = 0;
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static int txdmachan = 0;
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static int mmc_slot_enable = 0;
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/* Stop the MMC clock and wait while it happens */
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static inline int jz_mmc_stop_clock(void)
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{
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int timeout = 1000;
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REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
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while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
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timeout--;
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if (timeout == 0)
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return 0;
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udelay(1);
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}
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return MMC_NO_ERROR;
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}
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/* Start the MMC clock and operation */
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static inline int jz_mmc_start_clock(void)
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{
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REG_MSC_STRPCL =
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MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
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return MMC_NO_ERROR;
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}
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static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
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{
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u32 clkrt;
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u32 clk_src = is_sd ? 24000000 : 20000000;
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clkrt = 0;
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while (rate < clk_src) {
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clkrt++;
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clk_src >>= 1;
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}
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return clkrt;
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}
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/* Select the MMC clock frequency */
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static int jz_mmc_set_clock(u32 rate)
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{
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int clkrt;
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jz_mmc_stop_clock();
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__cpm_select_msc_clk(1); /* select clock source from CPM */
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clkrt = jz_mmc_calc_clkrt(1, rate);
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REG_MSC_CLKRT = clkrt;
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return MMC_NO_ERROR;
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}
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static void jz_mmc_enable_irq(struct jz_mmc_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask &= ~mask;
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REG_MSC_IMASK = host->imask;
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void jz_mmc_disable_irq(struct jz_mmc_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask |= mask;
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REG_MSC_IMASK = host->imask;
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spin_unlock_irqrestore(&host->lock, flags);
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}
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void jz_set_dma_block_size(int dmanr, int nbyte);
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#ifdef USE_DMA
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static inline void
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jz_mmc_start_dma(int chan, unsigned long phyaddr, int count, int mode)
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{
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unsigned long flags;
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flags = claim_dma_lock();
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disable_dma(chan);
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clear_dma_ff(chan);
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jz_set_dma_block_size(chan, 32);
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set_dma_mode(chan, mode);
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set_dma_addr(chan, phyaddr);
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set_dma_count(chan, count + 31);
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enable_dma(chan);
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release_dma_lock(flags);
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}
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static irqreturn_t jz_mmc_dma_rx_callback(int irq, void *devid)
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{
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int chan = rxdmachan;
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disable_dma(chan);
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if (__dmac_channel_address_error_detected(chan)) {
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printk(KERN_DEBUG "%s: DMAC address error.\n",
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__FUNCTION__);
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__dmac_channel_clear_address_error(chan);
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}
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if (__dmac_channel_transmit_end_detected(chan)) {
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__dmac_channel_clear_transmit_end(chan);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t jz_mmc_dma_tx_callback(int irq, void *devid)
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{
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int chan = txdmachan;
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disable_dma(chan);
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if (__dmac_channel_address_error_detected(chan)) {
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printk(KERN_DEBUG "%s: DMAC address error.\n",
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__FUNCTION__);
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__dmac_channel_clear_address_error(chan);
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}
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if (__dmac_channel_transmit_end_detected(chan)) {
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__dmac_channel_clear_transmit_end(chan);
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}
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return IRQ_HANDLED;
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}
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/* Prepare DMA to start data transfer from the MMC card */
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static void jz_mmc_rx_setup_data(struct jz_mmc_host *host,
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struct mmc_data *data)
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{
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unsigned int nob = data->blocks;
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int channelrx = rxdmachan;
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int i;
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u32 size;
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if (data->flags & MMC_DATA_STREAM)
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nob = 0xffff;
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REG_MSC_NOB = nob;
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REG_MSC_BLKLEN = data->blksz;
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size = nob * data->blksz;
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if (data->flags & MMC_DATA_READ) {
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host->dma.dir = DMA_FROM_DEVICE;
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} else {
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host->dma.dir = DMA_TO_DEVICE;
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}
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host->dma.len =
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dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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host->dma.dir);
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for (i = 0; i < host->dma.len; i++) {
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host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
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host->sg_cpu[i].dcmd = sg_dma_len(&data->sg[i]);
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dma_cache_wback_inv((unsigned long)
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CKSEG0ADDR(sg_dma_address(data->sg)) +
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data->sg->offset,
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host->sg_cpu[i].dcmd);
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jz_mmc_start_dma(channelrx, host->sg_cpu[i].dtadr,
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host->sg_cpu[i].dcmd, DMA_MODE_READ);
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}
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}
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/* Prepare DMA to start data transfer from the MMC card */
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static void jz_mmc_tx_setup_data(struct jz_mmc_host *host,
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struct mmc_data *data)
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{
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unsigned int nob = data->blocks;
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int channeltx = txdmachan;
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int i;
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u32 size;
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if (data->flags & MMC_DATA_STREAM)
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nob = 0xffff;
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REG_MSC_NOB = nob;
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REG_MSC_BLKLEN = data->blksz;
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size = nob * data->blksz;
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if (data->flags & MMC_DATA_READ) {
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host->dma.dir = DMA_FROM_DEVICE;
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} else {
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host->dma.dir = DMA_TO_DEVICE;
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}
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host->dma.len =
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dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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host->dma.dir);
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for (i = 0; i < host->dma.len; i++) {
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host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
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host->sg_cpu[i].dcmd = sg_dma_len(&data->sg[i]);
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dma_cache_wback_inv((unsigned long)
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CKSEG0ADDR(sg_dma_address(data->sg)) +
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data->sg->offset,
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host->sg_cpu[i].dcmd);
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jz_mmc_start_dma(channeltx, host->sg_cpu[i].dtadr,
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host->sg_cpu[i].dcmd, DMA_MODE_WRITE);
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}
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}
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#else
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static void jz_mmc_receive_pio(struct jz_mmc_host *host)
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{
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struct mmc_data *data = 0;
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int sg_len = 0, max = 0, count = 0;
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u32 *buf = 0;
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struct scatterlist *sg;
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unsigned int nob;
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data = host->mrq->data;
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nob = data->blocks;
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REG_MSC_NOB = nob;
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REG_MSC_BLKLEN = data->blksz;
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max = host->pio.len;
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if (host->pio.index < host->dma.len) {
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sg = &data->sg[host->pio.index];
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buf = sg_virt(sg) + host->pio.offset;
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/* This is the space left inside the buffer */
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sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
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/* Check to if we need less then the size of the sg_buffer */
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if (sg_len < max) max = sg_len;
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}
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max = max / 4;
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for(count = 0; count < max; count++) {
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while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY)
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;
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*buf++ = REG_MSC_RXFIFO;
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}
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host->pio.len -= count;
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host->pio.offset += count;
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if (sg_len && count == sg_len) {
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host->pio.index++;
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host->pio.offset = 0;
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}
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}
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static void jz_mmc_send_pio(struct jz_mmc_host *host)
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{
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struct mmc_data *data = 0;
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int sg_len, max, count = 0;
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u32 *wbuf = 0;
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struct scatterlist *sg;
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unsigned int nob;
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data = host->mrq->data;
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nob = data->blocks;
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REG_MSC_NOB = nob;
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REG_MSC_BLKLEN = data->blksz;
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/* This is the pointer to the data buffer */
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sg = &data->sg[host->pio.index];
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wbuf = sg_virt(sg) + host->pio.offset;
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/* This is the space left inside the buffer */
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sg_len = data->sg[host->pio.index].length - host->pio.offset;
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/* Check to if we need less then the size of the sg_buffer */
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max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
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max = max / 4;
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for(count = 0; count < max; count++ ) {
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while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL)
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;
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REG_MSC_TXFIFO = *wbuf++;
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}
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host->pio.len -= count;
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host->pio.offset += count;
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if (count == sg_len) {
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host->pio.index++;
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host->pio.offset = 0;
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}
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}
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static int
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jz_mmc_prepare_data(struct jz_mmc_host *host, struct mmc_data *data)
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{
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int datalen = data->blocks * data->blksz;
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host->dma.dir = DMA_BIDIRECTIONAL;
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host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
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data->sg_len, host->dma.dir);
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if (host->dma.len == 0)
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return -ETIMEDOUT;
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host->pio.index = 0;
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host->pio.offset = 0;
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host->pio.len = datalen;
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return 0;
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}
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#endif
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static int jz_mmc_cmd_done(struct jz_mmc_host *host, unsigned int stat);
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static void jz_mmc_finish_request(struct jz_mmc_host *host, struct mmc_request *mrq)
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{
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jz_mmc_stop_clock();
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host->mrq = NULL;
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host->cmd = NULL;
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host->data = NULL;
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mmc_request_done(host->mmc, mrq);
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}
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static void jz_mmc_start_cmd(struct jz_mmc_host *host,
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struct mmc_command *cmd, unsigned int cmdat)
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{
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u32 timeout = 0x3fffff;
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unsigned int stat;
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struct jz_mmc_host *hst = host;
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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/* stop MMC clock */
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jz_mmc_stop_clock();
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/* mask interrupts */
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REG_MSC_IMASK = 0xff;
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/* clear status */
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REG_MSC_IREG = 0xff;
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if (cmd->flags & MMC_RSP_BUSY)
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cmdat |= MSC_CMDAT_BUSY;
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#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
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switch (RSP_TYPE(mmc_resp_type(cmd))) {
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case RSP_TYPE(MMC_RSP_R1): /* r1,r1b, r6, r7 */
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cmdat |= MSC_CMDAT_RESPONSE_R1;
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r_type = 1;
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break;
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case RSP_TYPE(MMC_RSP_R3):
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cmdat |= MSC_CMDAT_RESPONSE_R3;
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r_type = 1;
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break;
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case RSP_TYPE(MMC_RSP_R2):
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cmdat |= MSC_CMDAT_RESPONSE_R2;
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r_type = 2;
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break;
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default:
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break;
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}
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REG_MSC_CMD = cmd->opcode;
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/* Set argument */
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#ifdef CONFIG_JZ_MMC_BUS_1
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if (cmd->opcode == 6) {
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/* set 1 bit sd card bus*/
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if (cmd->arg ==2)
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REG_MSC_ARG = 0;
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/* set 1 bit mmc card bus*/
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if (cmd->arg == 0x3b70101)
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REG_MSC_ARG = 0x3b70001;
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} else
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REG_MSC_ARG = cmd->arg;
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#else
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REG_MSC_ARG = cmd->arg;
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#endif
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/* Set command */
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REG_MSC_CMDAT = cmdat;
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/* Send command */
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jz_mmc_start_clock();
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while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES))
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;
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REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear irq flag */
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if (cmd->opcode == 12) {
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while (timeout-- && !(REG_MSC_IREG & MSC_IREG_PRG_DONE))
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;
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REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
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}
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if (!mmc_slot_enable) {
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/* It seems that MSC can't report the MSC_STAT_TIME_OUT_RES when
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* card was removed. We force to return here.
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*/
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cmd->error = -ETIMEDOUT;
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jz_mmc_finish_request(hst, hst->mrq);
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return;
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}
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if (SD_IO_SEND_OP_COND == cmd->opcode) {
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/*
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* Don't support SDIO card currently.
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*/
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cmd->error = -ETIMEDOUT;
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jz_mmc_finish_request(hst, hst->mrq);
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return;
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}
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/* Check for status */
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stat = REG_MSC_STAT;
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jz_mmc_cmd_done(hst, stat);
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if (host->data) {
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if (cmd->opcode == MMC_WRITE_BLOCK || cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
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#ifdef USE_DMA
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jz_mmc_tx_setup_data(host, host->data);
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#else
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jz_mmc_send_pio(host);
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else
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jz_mmc_receive_pio(host);
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#endif
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}
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}
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static int jz_mmc_cmd_done(struct jz_mmc_host *host, unsigned int stat)
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{
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struct mmc_command *cmd = host->cmd;
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int i, temp[16];
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u8 *buf;
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u32 data, v, w1, w2;
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if (!cmd)
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return 0;
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host->cmd = NULL;
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buf = (u8 *) temp;
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switch (r_type) {
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case 1:
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{
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data = REG_MSC_RES;
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buf[0] = (data >> 8) & 0xff;
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buf[1] = data & 0xff;
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data = REG_MSC_RES;
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buf[2] = (data >> 8) & 0xff;
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buf[3] = data & 0xff;
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data = REG_MSC_RES;
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buf[4] = data & 0xff;
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cmd->resp[0] =
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buf[1] << 24 | buf[2] << 16 | buf[3] << 8 |
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buf[4];
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break;
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}
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case 2:
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{
|
|
data = REG_MSC_RES;
|
|
v = data & 0xffff;
|
|
for (i = 0; i < 4; i++) {
|
|
data = REG_MSC_RES;
|
|
w1 = data & 0xffff;
|
|
data = REG_MSC_RES;
|
|
w2 = data & 0xffff;
|
|
cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
|
|
v = w2;
|
|
}
|
|
break;
|
|
}
|
|
case 0:
|
|
break;
|
|
}
|
|
if (stat & MSC_STAT_TIME_OUT_RES) {
|
|
printk("MSC_STAT_TIME_OUT_RES\n");
|
|
cmd->error = -ETIMEDOUT;
|
|
} else if (stat & MSC_STAT_CRC_RES_ERR && cmd->flags & MMC_RSP_CRC) {
|
|
printk("MSC_STAT_CRC\n");
|
|
if (cmd->opcode == MMC_ALL_SEND_CID ||
|
|
cmd->opcode == MMC_SEND_CSD ||
|
|
cmd->opcode == MMC_SEND_CID) {
|
|
/* a bogus CRC error can appear if the msb of
|
|
the 15 byte response is a one */
|
|
if ((cmd->resp[0] & 0x80000000) == 0)
|
|
cmd->error = -EILSEQ;
|
|
}
|
|
}
|
|
/*
|
|
* Did I mention this is Sick. We always need to
|
|
* discard the upper 8 bits of the first 16-bit word.
|
|
*/
|
|
if (host->data && cmd->error == 0)
|
|
jz_mmc_enable_irq(host, MSC_IMASK_DATA_TRAN_DONE);
|
|
else
|
|
jz_mmc_finish_request(host, host->mrq);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int jz_mmc_data_done(struct jz_mmc_host *host, unsigned int stat)
|
|
{
|
|
struct mmc_data *data = host->data;
|
|
|
|
if (!data)
|
|
return 0;
|
|
REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
|
|
jz_mmc_stop_clock();
|
|
dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
|
|
host->dma_dir);
|
|
if (stat & MSC_STAT_TIME_OUT_READ) {
|
|
printk("MMC/SD timeout, MMC_STAT 0x%x\n", stat);
|
|
data->error = -ETIMEDOUT;
|
|
} else if (REG_MSC_STAT &
|
|
(MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR)) {
|
|
printk("MMC/SD CRC error, MMC_STAT 0x%x\n", stat);
|
|
data->error = -EILSEQ;
|
|
}
|
|
/*
|
|
* There appears to be a hardware design bug here. There seems to
|
|
* be no way to find out how much data was transferred to the card.
|
|
* This means that if there was an error on any block, we mark all
|
|
* data blocks as being in error.
|
|
*/
|
|
if (data->error == 0)
|
|
data->bytes_xfered = data->blocks * data->blksz;
|
|
else
|
|
data->bytes_xfered = 0;
|
|
|
|
jz_mmc_disable_irq(host, MSC_IMASK_DATA_TRAN_DONE);
|
|
host->data = NULL;
|
|
if (host->mrq->stop) {
|
|
jz_mmc_stop_clock();
|
|
jz_mmc_start_cmd(host, host->mrq->stop, 0);
|
|
} else {
|
|
jz_mmc_finish_request(host, host->mrq);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static void jz_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
struct jz_mmc_host *host = mmc_priv(mmc);
|
|
unsigned int cmdat;
|
|
|
|
/* stop MMC clock */
|
|
jz_mmc_stop_clock();
|
|
|
|
/* Save current request for the future processing */
|
|
host->mrq = mrq;
|
|
host->data = mrq->data;
|
|
cmdat = host->cmdat;
|
|
host->cmdat &= ~MSC_CMDAT_INIT;
|
|
|
|
if (mrq->data) {
|
|
cmdat &= ~MSC_CMDAT_BUSY;
|
|
#ifdef USE_DMA
|
|
if ((mrq->cmd->opcode == 51) | (mrq->cmd->opcode == 8) | (mrq->cmd->opcode == 6))
|
|
|
|
cmdat |=
|
|
MSC_CMDAT_BUS_WIDTH_1BIT | MSC_CMDAT_DATA_EN |
|
|
MSC_CMDAT_DMA_EN;
|
|
else {
|
|
#ifdef CONFIG_JZ_MMC_BUS_1
|
|
cmdat &= ~MSC_CMDAT_BUS_WIDTH_4BIT;
|
|
cmdat |= MSC_CMDAT_BUS_WIDTH_1BIT | MSC_CMDAT_DATA_EN |
|
|
MSC_CMDAT_DMA_EN;
|
|
#else
|
|
cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_DMA_EN;
|
|
#endif
|
|
}
|
|
if (mrq->data->flags & MMC_DATA_WRITE)
|
|
cmdat |= MSC_CMDAT_WRITE;
|
|
|
|
if (mrq->data->flags & MMC_DATA_STREAM)
|
|
cmdat |= MSC_CMDAT_STREAM_BLOCK;
|
|
if (mrq->cmd->opcode != MMC_WRITE_BLOCK
|
|
&& mrq->cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK)
|
|
jz_mmc_rx_setup_data(host, mrq->data);
|
|
#else /*USE_DMA*/
|
|
|
|
if ((mrq->cmd->opcode == 51) | (mrq->cmd->opcode == 8) | (mrq->cmd->opcode == 6))
|
|
cmdat |= MSC_CMDAT_BUS_WIDTH_1BIT | MSC_CMDAT_DATA_EN;
|
|
else {
|
|
#ifdef CONFIG_JZ_MMC_BUS_1
|
|
cmdat &= ~MSC_CMDAT_BUS_WIDTH_4BIT;
|
|
cmdat |= MSC_CMDAT_BUS_WIDTH_1BIT | MSC_CMDAT_DATA_EN;
|
|
#else
|
|
cmdat |= MSC_CMDAT_DATA_EN;
|
|
#endif
|
|
}
|
|
if (mrq->data->flags & MMC_DATA_WRITE)
|
|
cmdat |= MSC_CMDAT_WRITE;
|
|
|
|
if (mrq->data->flags & MMC_DATA_STREAM)
|
|
cmdat |= MSC_CMDAT_STREAM_BLOCK;
|
|
jz_mmc_prepare_data(host, host->data);
|
|
#endif /*USE_DMA*/
|
|
}
|
|
jz_mmc_start_cmd(host, mrq->cmd, cmdat);
|
|
}
|
|
|
|
static irqreturn_t jz_mmc_irq(int irq, void *devid)
|
|
{
|
|
struct jz_mmc_host *host = devid;
|
|
unsigned int ireg;
|
|
int handled = 0;
|
|
|
|
ireg = REG_MSC_IREG;
|
|
|
|
if (ireg) {
|
|
unsigned stat = REG_MSC_STAT;
|
|
if (ireg & MSC_IREG_DATA_TRAN_DONE)
|
|
handled |= jz_mmc_data_done(host, stat);
|
|
}
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
/* Returns true if MMC slot is empty */
|
|
static int jz_mmc_slot_is_empty(int slot)
|
|
{
|
|
int empty;
|
|
|
|
empty = (__msc_card_detected(slot) == 0) ? 1 : 0;
|
|
|
|
if (empty) {
|
|
/* wait for card insertion */
|
|
#ifdef CONFIG_MIPS_JZ4740_LYRA
|
|
__gpio_as_irq_rise_edge(MSC_HOTPLUG_PIN);
|
|
#else
|
|
__gpio_as_irq_fall_edge(MSC_HOTPLUG_PIN);
|
|
#endif
|
|
} else {
|
|
/* wait for card removal */
|
|
#ifdef CONFIG_MIPS_JZ4740_LYRA
|
|
__gpio_as_irq_fall_edge(MSC_HOTPLUG_PIN);
|
|
#else
|
|
__gpio_as_irq_rise_edge(MSC_HOTPLUG_PIN);
|
|
#endif
|
|
}
|
|
|
|
return empty;
|
|
}
|
|
|
|
static irqreturn_t jz_mmc_detect_irq(int irq, void *devid)
|
|
{
|
|
struct jz_mmc_host *host = (struct jz_mmc_host *) devid;
|
|
|
|
if (jz_mmc_slot_is_empty(0)) {
|
|
mmc_slot_enable = 0;
|
|
mmc_detect_change(host->mmc, 50);
|
|
} else {
|
|
mmc_slot_enable = 1;
|
|
mmc_detect_change(host->mmc, 50);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int jz_mmc_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct jz_mmc_host *host = mmc_priv(mmc);
|
|
|
|
if (host->pdata && host->pdata->get_ro)
|
|
return host->pdata->get_ro(mmc_dev(mmc));
|
|
/* Host doesn't support read only detection so assume writeable */
|
|
return 0;
|
|
}
|
|
|
|
/* set clock and power */
|
|
static void jz_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct jz_mmc_host *host = mmc_priv(mmc);
|
|
|
|
if (ios->clock)
|
|
jz_mmc_set_clock(ios->clock);
|
|
else
|
|
jz_mmc_stop_clock();
|
|
|
|
if (host->power_mode != ios->power_mode) {
|
|
host->power_mode = ios->power_mode;
|
|
|
|
if (ios->power_mode == MMC_POWER_ON)
|
|
host->cmdat |= CMDAT_INIT;
|
|
}
|
|
|
|
if ((ios->bus_width == MMC_BUS_WIDTH_4) || (ios->bus_width == MMC_BUS_WIDTH_8))
|
|
host->cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
|
|
else
|
|
host->cmdat &= ~MSC_CMDAT_BUS_WIDTH_4BIT;
|
|
}
|
|
|
|
static const struct mmc_host_ops jz_mmc_ops = {
|
|
.request = jz_mmc_request,
|
|
.get_ro = jz_mmc_get_ro,
|
|
.set_ios = jz_mmc_set_ios,
|
|
};
|
|
|
|
static int jz_mmc_probe(struct platform_device *pdev)
|
|
{
|
|
int retval;
|
|
struct mmc_host *mmc;
|
|
struct jz_mmc_host *host = NULL;
|
|
int irq;
|
|
struct resource *r;
|
|
|
|
__gpio_as_msc();
|
|
__msc_init_io();
|
|
__msc_enable_power();
|
|
|
|
__msc_reset();
|
|
|
|
/* On reset, stop MMC clock */
|
|
jz_mmc_stop_clock();
|
|
|
|
MMC_IRQ_MASK();
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (!r || irq < 0)
|
|
return -ENXIO;
|
|
|
|
r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
|
|
if (!r)
|
|
return -EBUSY;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct jz_mmc_host), &pdev->dev);
|
|
if (!mmc) {
|
|
retval = -ENOMEM;
|
|
goto out;
|
|
}
|
|
mmc->ops = &jz_mmc_ops;
|
|
mmc->f_min = MMC_CLOCK_SLOW;
|
|
mmc->f_max = SD_CLOCK_FAST;
|
|
/*
|
|
* We can do SG-DMA, but we don't because we never know how much
|
|
* data we successfully wrote to the card.
|
|
*/
|
|
mmc->max_phys_segs = NR_SG;
|
|
/*
|
|
* Our hardware DMA can handle a maximum of one page per SG entry.
|
|
*/
|
|
mmc->max_seg_size = PAGE_SIZE;
|
|
/*
|
|
* Block length register is 10 bits.
|
|
*/
|
|
mmc->max_blk_size = 1023;
|
|
/*
|
|
* Block count register is 16 bits.
|
|
*/
|
|
mmc->max_blk_count = 65535;
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
host->pdata = pdev->dev.platform_data;
|
|
mmc->ocr_avail = host->pdata ?
|
|
host->pdata->ocr_mask : MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
host->mmc->caps =
|
|
MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED
|
|
| MMC_CAP_MMC_HIGHSPEED;
|
|
/*
|
|
*MMC_CAP_4_BIT_DATA (1 << 0) The host can do 4 bit transfers
|
|
*
|
|
*/
|
|
host->sg_cpu =
|
|
dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma,
|
|
GFP_KERNEL);
|
|
if (!host->sg_cpu) {
|
|
retval = -ENOMEM;
|
|
goto out;
|
|
}
|
|
spin_lock_init(&host->lock);
|
|
host->irq = JZ_IRQ_MSC;
|
|
host->imask = 0xff;
|
|
/*
|
|
* Ensure that the host controller is shut down, and setup
|
|
* with our defaults.
|
|
*/
|
|
retval = request_irq(JZ_IRQ_MSC, jz_mmc_irq, 0, "MMC/SD", host);
|
|
if (retval) {
|
|
printk(KERN_ERR "MMC/SD: can't request MMC/SD IRQ\n");
|
|
return retval;
|
|
}
|
|
jz_mmc_slot_is_empty(0);
|
|
/* Request card detect interrupt */
|
|
|
|
retval = request_irq(MSC_HOTPLUG_IRQ, jz_mmc_detect_irq, 0, //SA_INTERRUPT,
|
|
"MMC card detect", host);
|
|
if (retval) {
|
|
printk(KERN_ERR "MMC/SD: can't request card detect IRQ\n");
|
|
goto err1;
|
|
}
|
|
#ifdef USE_DMA
|
|
/* Request MMC Rx DMA channel */
|
|
rxdmachan =
|
|
jz_request_dma(DMA_ID_MSC_RX, "MMC Rx", jz_mmc_dma_rx_callback,
|
|
0, host);
|
|
if (rxdmachan < 0) {
|
|
printk(KERN_ERR "jz_request_dma failed for MMC Rx\n");
|
|
goto err2;
|
|
}
|
|
|
|
/* Request MMC Tx DMA channel */
|
|
txdmachan =
|
|
jz_request_dma(DMA_ID_MSC_TX, "MMC Tx", jz_mmc_dma_tx_callback,
|
|
0, host);
|
|
if (txdmachan < 0) {
|
|
printk(KERN_ERR "jz_request_dma failed for MMC Tx\n");
|
|
goto err3;
|
|
}
|
|
#endif
|
|
platform_set_drvdata(pdev, mmc);
|
|
mmc_add_host(mmc);
|
|
printk("JZ SD/MMC card driver registered\n");
|
|
|
|
/* Detect card during initialization */
|
|
#ifdef CONFIG_SOC_JZ4740
|
|
if (!jz_mmc_slot_is_empty(0)) {
|
|
mmc_slot_enable = 1;
|
|
mmc_detect_change(host->mmc, 0);
|
|
}
|
|
#endif
|
|
return 0;
|
|
|
|
err1:free_irq(JZ_IRQ_MSC, &host);
|
|
#ifdef USE_DMA
|
|
err2:jz_free_dma(rxdmachan);
|
|
err3:jz_free_dma(txdmachan);
|
|
#endif
|
|
out:
|
|
if (host) {
|
|
if (host->sg_cpu)
|
|
dma_free_coherent(&pdev->dev, PAGE_SIZE,
|
|
host->sg_cpu, host->sg_dma);
|
|
}
|
|
if (mmc)
|
|
mmc_free_host(mmc);
|
|
return -1;
|
|
}
|
|
|
|
static int jz_mmc_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (mmc) {
|
|
struct jz_mmc_host *host = mmc_priv(mmc);
|
|
|
|
if (host->pdata && host->pdata->exit)
|
|
host->pdata->exit(&pdev->dev, mmc);
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
jz_mmc_stop_clock();
|
|
__msc_disable_power();
|
|
jz_free_dma(rxdmachan);
|
|
jz_free_dma(txdmachan);
|
|
free_irq(JZ_IRQ_MSC, host);
|
|
mmc_free_host(mmc);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
pm_message_t state;
|
|
static int jz_mmc_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
__msc_disable_power();
|
|
if (mmc)
|
|
ret = mmc_suspend_host(mmc, state);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int jz_mmc_resume(struct platform_device *dev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
int ret = 0;
|
|
#if 0
|
|
/*for sandisk BB0807011816D and other strange cards*/
|
|
int i;
|
|
|
|
for(i = 104; i < 110; i++)
|
|
__gpio_as_input(i);
|
|
|
|
/* perhaps you should mdelay more */
|
|
mdelay(1000);
|
|
__gpio_as_msc();
|
|
#endif
|
|
__msc_init_io();
|
|
__msc_enable_power();
|
|
__msc_reset();
|
|
|
|
if (!jz_mmc_slot_is_empty(0)) {
|
|
mmc_slot_enable = 1;
|
|
mmc_detect_change(mmc, 10);
|
|
}
|
|
|
|
if (mmc)
|
|
ret = mmc_resume_host(mmc);
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define jz_mmc_suspend NULL
|
|
#define jz_mmc_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver jz_mmc_driver = {
|
|
.probe = jz_mmc_probe,
|
|
.remove = jz_mmc_remove,
|
|
.suspend = jz_mmc_suspend,
|
|
.resume = jz_mmc_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init jz_mmc_init(void)
|
|
{
|
|
return platform_driver_register(&jz_mmc_driver);
|
|
}
|
|
|
|
static void __exit jz_mmc_exit(void)
|
|
{
|
|
platform_driver_unregister(&jz_mmc_driver);
|
|
}
|
|
|
|
module_init(jz_mmc_init);
|
|
module_exit(jz_mmc_exit);
|
|
|
|
MODULE_DESCRIPTION("JZ47XX SD/Multimedia Card Interface Driver");
|
|
MODULE_LICENSE("GPL");
|