mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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c4723d07e6
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33571 3c298f89-4303-0410-b956-a3cf2f4a3e73
248 lines
6.2 KiB
C
248 lines
6.2 KiB
C
/*
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* Ralink RT305x SoC specific setup
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/ramips_gpio.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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void __iomem * rt305x_sysc_base;
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void __iomem * rt305x_memc_base;
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enum rt305x_soc_type rt305x_soc;
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static unsigned long rt5350_get_mem_size(void)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
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unsigned long ret;
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u32 t;
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t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
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t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
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RT5350_SYSCFG0_DRAM_SIZE_MASK;
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switch (t) {
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case RT5350_SYSCFG0_DRAM_SIZE_2M:
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ret = 2 * 1024 * 1024;
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break;
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case RT5350_SYSCFG0_DRAM_SIZE_8M:
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ret = 8 * 1024 * 1024;
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break;
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case RT5350_SYSCFG0_DRAM_SIZE_16M:
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ret = 16 * 1024 * 1024;
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break;
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case RT5350_SYSCFG0_DRAM_SIZE_32M:
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ret = 32 * 1024 * 1024;
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break;
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case RT5350_SYSCFG0_DRAM_SIZE_64M:
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ret = 64 * 1024 * 1024;
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break;
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default:
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panic("rt5350: invalid DRAM size: %u", t);
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break;
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}
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return ret;
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}
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void __init ramips_soc_prom_init(void)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
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const char *name = "unknown";
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u32 n0;
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u32 n1;
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u32 id;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
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unsigned long icache_sets;
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icache_sets = (read_c0_config1() >> 22) & 7;
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if (icache_sets == 1) {
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rt305x_soc = RT305X_SOC_RT3050;
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name = "RT3050";
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} else {
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rt305x_soc = RT305X_SOC_RT3052;
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name = "RT3052";
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}
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} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
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rt305x_soc = RT305X_SOC_RT3350;
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name = "RT3350";
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} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
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rt305x_soc = RT305X_SOC_RT3352;
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name = "RT3352";
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} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
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rt305x_soc = RT305X_SOC_RT5350;
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name = "RT5350";
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} else {
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panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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}
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id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
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snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s id:%u rev:%u",
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name,
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(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
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(id & CHIP_ID_REV_MASK));
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ramips_mem_base = RT305X_SDRAM_BASE;
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if (soc_is_rt5350()) {
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ramips_get_mem_size = rt5350_get_mem_size;
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} else if (soc_is_rt305x() || soc_is_rt3350() ) {
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ramips_mem_size_min = RT305X_MEM_SIZE_MIN;
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ramips_mem_size_max = RT305X_MEM_SIZE_MAX;
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} else if (soc_is_rt3352()) {
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ramips_mem_size_min = RT3352_MEM_SIZE_MIN;
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ramips_mem_size_max = RT3352_MEM_SIZE_MAX;
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} else {
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BUG();
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}
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}
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static struct ramips_gpio_chip rt305x_gpio_chips[] = {
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{
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.chip = {
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.label = "RT305X-GPIO0",
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.base = 0,
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.ngpio = 24,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x00,
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[RAMIPS_GPIO_REG_EDGE] = 0x04,
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[RAMIPS_GPIO_REG_RENA] = 0x08,
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[RAMIPS_GPIO_REG_FENA] = 0x0c,
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[RAMIPS_GPIO_REG_DATA] = 0x20,
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[RAMIPS_GPIO_REG_DIR] = 0x24,
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[RAMIPS_GPIO_REG_POL] = 0x28,
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[RAMIPS_GPIO_REG_SET] = 0x2c,
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[RAMIPS_GPIO_REG_RESET] = 0x30,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x34,
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},
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.map_base = RT305X_PIO_BASE,
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.map_size = RT305X_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT305X-GPIO1",
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.base = 24,
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.ngpio = 16,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x38,
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[RAMIPS_GPIO_REG_EDGE] = 0x3c,
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[RAMIPS_GPIO_REG_RENA] = 0x40,
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[RAMIPS_GPIO_REG_FENA] = 0x44,
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[RAMIPS_GPIO_REG_DATA] = 0x48,
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[RAMIPS_GPIO_REG_DIR] = 0x4c,
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[RAMIPS_GPIO_REG_POL] = 0x50,
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[RAMIPS_GPIO_REG_SET] = 0x54,
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[RAMIPS_GPIO_REG_RESET] = 0x58,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
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},
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.map_base = RT305X_PIO_BASE,
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.map_size = RT305X_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT305X-GPIO2",
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.base = 40,
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.ngpio = 12,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x60,
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[RAMIPS_GPIO_REG_EDGE] = 0x64,
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[RAMIPS_GPIO_REG_RENA] = 0x68,
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[RAMIPS_GPIO_REG_FENA] = 0x6c,
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[RAMIPS_GPIO_REG_DATA] = 0x70,
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[RAMIPS_GPIO_REG_DIR] = 0x74,
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[RAMIPS_GPIO_REG_POL] = 0x78,
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[RAMIPS_GPIO_REG_SET] = 0x7c,
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[RAMIPS_GPIO_REG_RESET] = 0x80,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x84,
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},
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.map_base = RT305X_PIO_BASE,
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.map_size = RT305X_PIO_SIZE,
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},
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};
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static struct ramips_gpio_data rt305x_gpio_data = {
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.chips = rt305x_gpio_chips,
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.num_chips = ARRAY_SIZE(rt305x_gpio_chips),
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};
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static void rt305x_gpio_reserve(int first, int last)
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{
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for (; first <= last; first++)
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gpio_request(first, "reserved");
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}
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void __init rt305x_gpio_init(u32 mode)
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{
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u32 t;
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rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
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ramips_gpio_init(&rt305x_gpio_data);
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if ((mode & RT305X_GPIO_MODE_I2C) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
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if ((mode & RT305X_GPIO_MODE_SPI) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
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t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
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t &= RT305X_GPIO_MODE_UART0_MASK;
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switch (t) {
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case RT305X_GPIO_MODE_UARTF:
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case RT305X_GPIO_MODE_PCM_UARTF:
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case RT305X_GPIO_MODE_PCM_I2S:
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case RT305X_GPIO_MODE_I2S_UARTF:
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rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
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break;
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case RT305X_GPIO_MODE_PCM_GPIO:
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rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
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break;
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case RT305X_GPIO_MODE_GPIO_UARTF:
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case RT305X_GPIO_MODE_GPIO_I2S:
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rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
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break;
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}
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if ((mode & RT305X_GPIO_MODE_UART1) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
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RT305X_GPIO_UART1_RXD);
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if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
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if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
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RT305X_GPIO_MDIO_MDIO);
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if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
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RT305X_GPIO_SDRAM_MD31);
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if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
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RT305X_GPIO_GE0_RXCLK);
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}
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