mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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f679e4f7e6
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20561 3c298f89-4303-0410-b956-a3cf2f4a3e73
92 lines
4.9 KiB
C
92 lines
4.9 KiB
C
/*
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* Lantiq switch ethernet driver for Danube family.
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*
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* Based on INCA-IP driver:
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __DRIVERS_IFX_SW_H__
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#define __DRIVERS_IFX_SW_H__
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#define DANUBE_PPE32_BASE 0xBE180000
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#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
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#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
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#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
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#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
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#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
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#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
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#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
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#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
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#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
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#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
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#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
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#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
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#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
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#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
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#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
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#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
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#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
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#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
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#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
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#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
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#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
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#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
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#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
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#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
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#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
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#define DANUBE_DMA_BASE 0xBE104100
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typedef struct IfxDMA_s
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{
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unsigned long dma_clc; /*0x0000*/
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unsigned long dma_rsvd1[1]; /* for mapping */ /*0x0004*/
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unsigned long dma_id; /*0x0008*/
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unsigned long dma_rsvd2[1]; /* for mapping */ /*0x000C*/
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unsigned long dma_ctrl; /*0x0010*/
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unsigned long dma_cpoll; /*0x0014*/
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unsigned long dma_cs; /*0x0018*/
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unsigned long dma_cctrl; /*0x001C*/
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unsigned long dma_cdba; /*0x0020*/
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unsigned long dma_cdlen; /*0x0024*/
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unsigned long dma_cis; /*0x0028*/
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unsigned long dma_cie; /*0x002C*/
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unsigned long dma_rsvd3[4]; /* for mapping */ /*0x0030*/
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unsigned long dma_ps; /*0x0040*/
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unsigned long dma_pctrl; /*0x0044*/
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unsigned long dma_rsvd4[43]; /* for mapping */ /*0x0048*/
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unsigned long dma_irnen; /*0x00F4*/
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unsigned long dma_irncr; /*0x00F8*/
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unsigned long dma_irnicr; /*0x00FC*/
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} IfxDMA_t;
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/* Register access macros */
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#define dma_readl(reg) \
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readl(&pDma->reg)
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#define dma_writel(reg,value) \
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writel((value), &pDma->reg)
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int lq_eth_initialize(bd_t * bis);
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#endif /* __DRIVERS_IFX_SW_H__ */
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