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openwrt-xburst/target/linux/s3c24xx/patches-2.6.28/001-merge-openmoko.patch
nbd 6189f5619b s3c24xx: unbreak openmoko merge patch (mmc changes) 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@14927 3c298f89-4303-0410-b956-a3cf2f4a3e73
2009-03-17 19:10:36 +00:00

149976 lines
4.7 MiB
Raw Blame History

Merge OpenMoko kernel patches
git://git.openmoko.org/git/kernel.git#andy-tracking
mb@homer Thu Jan 1 22:58:51 UTC 2009
---
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -69,12 +69,12 @@
/*
* Make sure we clear all existing interrupts
*/
- writel(0, base + VIC_VECT_ADDR);
+ writel(0, base + VIC_PL190_VECT_ADDR);
for (i = 0; i < 19; i++) {
unsigned int value;
- value = readl(base + VIC_VECT_ADDR);
- writel(value, base + VIC_VECT_ADDR);
+ value = readl(base + VIC_PL190_VECT_ADDR);
+ writel(value, base + VIC_PL190_VECT_ADDR);
}
for (i = 0; i < 16; i++) {
@@ -82,7 +82,7 @@
writel(VIC_VECT_CNTL_ENABLE | i, reg);
}
- writel(32, base + VIC_DEF_VECT_ADDR);
+ writel(32, base + VIC_PL190_DEF_VECT_ADDR);
for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i;
--- /dev/null
+++ b/arch/arm/configs/gta02-moredrivers-defconfig
@@ -0,0 +1,2107 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc4
+# Mon Dec 29 12:13:48 2008
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_FIQ=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-mokodev"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ASHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_MARKERS=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=m
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=m
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+CONFIG_PLAT_S3C24XX=y
+CONFIG_S3C2410_CLOCK=y
+CONFIG_CPU_S3C244X=y
+CONFIG_S3C24XX_PWM=y
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+CONFIG_MACH_SMDK=y
+CONFIG_MACH_NEO1973=y
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=2
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+
+#
+# S3C2400 Machines
+#
+CONFIG_CPU_S3C2410=y
+CONFIG_CPU_S3C2410_DMA=y
+CONFIG_S3C2410_PM=y
+CONFIG_S3C2410_GPIO=y
+CONFIG_S3C2410_PWM=y
+
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+# CONFIG_MACH_TCT_HAMMER is not set
+# CONFIG_MACH_VR1000 is not set
+CONFIG_MACH_QT2410=y
+# CONFIG_MACH_NEO1973_GTA01 is not set
+
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_JIVE is not set
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+CONFIG_CPU_S3C2440=y
+CONFIG_S3C2440_DMA=y
+CONFIG_S3C2440_C_FIQ=y
+
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+CONFIG_ARCH_S3C2440=y
+# CONFIG_MACH_NEXCODER_2440 is not set
+CONFIG_SMDK2440_CPU2440=y
+# CONFIG_MACH_AT2440EVB is not set
+CONFIG_MACH_NEO1973_GTA02=y
+# CONFIG_NEO1973_GTA02_2440 is not set
+CONFIG_CPU_S3C2442=y
+
+#
+# S3C2442 Machines
+#
+CONFIG_SMDK2440_CPU2442=y
+
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=200
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CT_ACCT is not set
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+# CONFIG_NF_NAT_FTP is not set
+# CONFIG_NF_NAT_IRC is not set
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+# CONFIG_NF_NAT_SIP is not set
+CONFIG_IP_NF_MANGLE=m
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+# CONFIG_IP6_NF_RAW is not set
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+# CONFIG_BRIDGE_EBT_IP6 is not set
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_MULTIQ is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_S3C2410=y
+CONFIG_MTD_NAND_S3C2410_DEBUG=y
+CONFIG_MTD_NAND_S3C2410_HWECC=y
+# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_LOW_MEMORY_KILLER=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=y
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_HSO is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_NEO1973=y
+CONFIG_KEYBOARD_QT2410=y
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FILTER=y
+CONFIG_TOUCHSCREEN_FILTER_GROUP=y
+CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
+CONFIG_TOUCHSCREEN_FILTER_MEAN=y
+CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+CONFIG_TOUCHSCREEN_S3C2410=y
+# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_PCAP7200 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_LIS302DL=y
+CONFIG_INPUT_PCF50633_PMU=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_NR_TTY_DEVICES=6
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=3
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2440=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF50606 is not set
+# CONFIG_SENSORS_PCF50633 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL256X is not set
+CONFIG_PCA9632=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_S3C24XX is not set
+CONFIG_SPI_S3C24XX_GPIO=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_DEBUG=y
+CONFIG_PDA_POWER=y
+CONFIG_APM_POWER=y
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_BATTERY_BQ27000_HDQ=y
+CONFIG_GTA02_HDQ=y
+CONFIG_CHARGER_PCF50633=y
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=m
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+CONFIG_MFD_PCF50633=y
+CONFIG_PCF50633_ADC=y
+CONFIG_PCF50633_GPIO=y
+# CONFIG_MFD_PCF50606 is not set
+CONFIG_MFD_GLAMO=y
+CONFIG_MFD_GLAMO_FB=y
+CONFIG_MFD_GLAMO_SPI_GPIO=y
+CONFIG_MFD_GLAMO_SPI_FB=y
+CONFIG_MFD_GLAMO_MCI=y
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C2410=y
+# CONFIG_FB_S3C2410_DEBUG is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+# CONFIG_BACKLIGHT_PWM is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+CONFIG_DISPLAY_JBT6K74=y
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+CONFIG_SND_PCM_XRUN_DEBUG=y
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_S3C24XX_SOC=y
+CONFIG_SND_S3C24XX_SOC_I2S=y
+CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=y
+# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8753=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+CONFIG_USB_PRINTER=m
+# CONFIG_USB_WDM is not set
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+# CONFIG_USB_SERIAL_CH341 is not set
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+# CONFIG_USB_SERIAL_IUU is not set
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_SERIAL_OMNINET=m
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+CONFIG_USB_BERRY_CHARGE=m
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+CONFIG_USB_GADGET_S3C2410=y
+CONFIG_USB_S3C2410=y
+CONFIG_USB_S3C2410_DEBUG=y
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_AR6000_WLAN=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_S3C=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_S3C24XX=m
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+CONFIG_LEDS_NEO1973_VIBRATOR=y
+CONFIG_LEDS_NEO1973_GTA02=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_DEBUG=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_PCF50633=y
+# CONFIG_RTC_DRV_PCF50606 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=m
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+
+#
+# Android
+#
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_POWER=y
+CONFIG_ANDROID_POWER_STAT=y
+CONFIG_ANDROID_POWER_ALARM=y
+CONFIG_ANDROID_LOGGER=y
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+# CONFIG_ANDROID_TIMED_GPIO is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_PCF50633=y
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=y
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4DEV_COMPAT=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+# CONFIG_PROVE_LOCKING is not set
+CONFIG_LOCKDEP=y
+CONFIG_LOCK_STAT=y
+CONFIG_DEBUG_LOCKDEP=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+CONFIG_DEBUG_SG=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+CONFIG_DYNAMIC_PRINTK_DEBUG=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_S3C_UART=2
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
--- /dev/null
+++ b/arch/arm/configs/gta02-packaging-defconfig
@@ -0,0 +1,2111 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc4
+# Wed Dec 10 11:09:39 2008
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_FIQ=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-mokodev"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ASHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_MARKERS=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=m
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=m
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+CONFIG_ARCH_S3C2410=y
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+CONFIG_PLAT_S3C24XX=y
+CONFIG_S3C2410_CLOCK=y
+CONFIG_CPU_S3C244X=y
+CONFIG_S3C24XX_PWM=y
+CONFIG_S3C2410_DMA=y
+# CONFIG_S3C2410_DMA_DEBUG is not set
+CONFIG_MACH_SMDK=y
+CONFIG_MACH_NEO1973=y
+CONFIG_PLAT_S3C=y
+CONFIG_CPU_LLSERIAL_S3C2410=y
+CONFIG_CPU_LLSERIAL_S3C2440=y
+
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_WATCHDOG is not set
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=2
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+
+#
+# S3C2400 Machines
+#
+CONFIG_CPU_S3C2410=y
+CONFIG_CPU_S3C2410_DMA=y
+CONFIG_S3C2410_PM=y
+CONFIG_S3C2410_GPIO=y
+CONFIG_S3C2410_PWM=y
+
+#
+# S3C2410 Machines
+#
+# CONFIG_ARCH_SMDK2410 is not set
+# CONFIG_ARCH_H1940 is not set
+# CONFIG_MACH_N30 is not set
+# CONFIG_ARCH_BAST is not set
+# CONFIG_MACH_OTOM is not set
+# CONFIG_MACH_AML_M5900 is not set
+# CONFIG_MACH_TCT_HAMMER is not set
+# CONFIG_MACH_VR1000 is not set
+CONFIG_MACH_QT2410=y
+# CONFIG_MACH_NEO1973_GTA01 is not set
+
+#
+# S3C2412 Machines
+#
+# CONFIG_MACH_JIVE is not set
+# CONFIG_MACH_SMDK2413 is not set
+# CONFIG_MACH_SMDK2412 is not set
+# CONFIG_MACH_VSTMS is not set
+CONFIG_CPU_S3C2440=y
+CONFIG_S3C2440_DMA=y
+CONFIG_S3C2440_C_FIQ=y
+
+#
+# S3C2440 Machines
+#
+# CONFIG_MACH_ANUBIS is not set
+# CONFIG_MACH_OSIRIS is not set
+# CONFIG_MACH_RX3715 is not set
+CONFIG_ARCH_S3C2440=y
+# CONFIG_MACH_NEXCODER_2440 is not set
+CONFIG_SMDK2440_CPU2440=y
+# CONFIG_MACH_AT2440EVB is not set
+CONFIG_MACH_NEO1973_GTA02=y
+# CONFIG_NEO1973_GTA02_2440 is not set
+CONFIG_CPU_S3C2442=y
+
+#
+# S3C2442 Machines
+#
+CONFIG_SMDK2440_CPU2442=y
+
+#
+# S3C2443 Machines
+#
+# CONFIG_MACH_SMDK2443 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=200
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="unused -- bootloader passes ATAG list"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+# CONFIG_IPV6_MIP6 is not set
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+# CONFIG_NF_NAT_AMANDA is not set
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_TARGET_HL=m
+# CONFIG_IP6_NF_RAW is not set
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+# CONFIG_BRIDGE_EBT_IP6 is not set
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=y
+CONFIG_BRIDGE=y
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=y
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_MULTIQ is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_LEDS=y
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_S3C2410=y
+CONFIG_MTD_NAND_S3C2410_DEBUG=y
+CONFIG_MTD_NAND_S3C2410_HWECC=y
+# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_LOW_MEMORY_KILLER=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_HSO is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_NEO1973=y
+CONFIG_KEYBOARD_QT2410=y
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FILTER=y
+CONFIG_TOUCHSCREEN_FILTER_GROUP=y
+CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
+CONFIG_TOUCHSCREEN_FILTER_MEAN=y
+CONFIG_TOUCHSCREEN_FILTER_LINEAR=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+CONFIG_TOUCHSCREEN_S3C2410=y
+# CONFIG_TOUCHSCREEN_S3C2410_DEBUG is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_PCAP7200 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_LIS302DL=y
+CONFIG_INPUT_PCF50633_PMU=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_NR_TTY_DEVICES=6
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=3
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C2410=y
+CONFIG_SERIAL_S3C2440=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF50606 is not set
+# CONFIG_SENSORS_PCF50633 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL256X is not set
+CONFIG_PCA9632=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_S3C24XX is not set
+CONFIG_SPI_S3C24XX_GPIO=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_DEBUG=y
+CONFIG_PDA_POWER=y
+CONFIG_APM_POWER=y
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_BATTERY_BQ27000_HDQ=y
+CONFIG_GTA02_HDQ=y
+CONFIG_CHARGER_PCF50633=y
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_S3C2410_WATCHDOG=m
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+CONFIG_MFD_PCF50633=y
+CONFIG_PCF50633_ADC=y
+CONFIG_PCF50633_GPIO=y
+# CONFIG_MFD_PCF50606 is not set
+CONFIG_MFD_GLAMO=y
+CONFIG_MFD_GLAMO_FB=y
+CONFIG_MFD_GLAMO_SPI_GPIO=y
+CONFIG_MFD_GLAMO_SPI_FB=y
+CONFIG_MFD_GLAMO_MCI=y
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C2410=y
+# CONFIG_FB_S3C2410_DEBUG is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_LTV350QV=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+# CONFIG_BACKLIGHT_PWM is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+CONFIG_DISPLAY_JBT6K74=y
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+CONFIG_SND_PCM_XRUN_DEBUG=y
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_S3C24XX_SOC=m
+CONFIG_SND_S3C24XX_SOC_I2S=m
+CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753=m
+# CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650 is not set
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8753=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+CONFIG_HID_PID=y
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_BRIGHT=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DELL=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+# CONFIG_USB_WDM is not set
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+# CONFIG_USB_STORAGE_ISD200 is not set
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+# CONFIG_USB_SERIAL_CH341 is not set
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+CONFIG_USB_SERIAL_CP2101=m
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+# CONFIG_USB_SERIAL_IUU is not set
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+CONFIG_USB_SERIAL_SAFE_PADDED=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+CONFIG_USB_BERRY_CHARGE=m
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+CONFIG_USB_TRANCEVIBRATOR=m
+CONFIG_USB_IOWARRIOR=m
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+CONFIG_USB_GADGET_S3C2410=y
+CONFIG_USB_S3C2410=y
+CONFIG_USB_S3C2410_DEBUG=y
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_AR6000_WLAN=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+# CONFIG_MMC_SPI is not set
+CONFIG_MMC_S3C=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_S3C24XX=m
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PCA955X is not set
+CONFIG_LEDS_NEO1973_VIBRATOR=y
+CONFIG_LEDS_NEO1973_GTA02=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_DEBUG=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_PCF50633=y
+# CONFIG_RTC_DRV_PCF50606 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_S3C=m
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+
+#
+# Android
+#
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_POWER=y
+CONFIG_ANDROID_POWER_STAT=y
+CONFIG_ANDROID_POWER_ALARM=y
+CONFIG_ANDROID_LOGGER=y
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+# CONFIG_ANDROID_TIMED_GPIO is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_PCF50633=y
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=y
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4DEV_COMPAT=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=m
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+# CONFIG_PROVE_LOCKING is not set
+CONFIG_LOCKDEP=y
+CONFIG_LOCK_STAT=y
+CONFIG_DEBUG_LOCKDEP=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+CONFIG_DEBUG_SG=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_LATENCYTOP=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+CONFIG_DYNAMIC_PRINTK_DEBUG=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_S3C_UART=2
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
--- /dev/null
+++ b/arch/arm/configs/gta03_defconfig
@@ -0,0 +1,1548 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc4
+# Fri Dec 12 12:07:49 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_ASHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+CONFIG_ARCH_S3C64XX=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+CONFIG_MACH_NEO1973=y
+CONFIG_PLAT_S3C64XX=y
+CONFIG_CPU_S3C6400_INIT=y
+CONFIG_CPU_S3C6400_CLOCK=y
+CONFIG_S3C64XX_SETUP_I2C0=y
+CONFIG_S3C64XX_SETUP_I2C1=y
+CONFIG_S3C64XX_SETUP_FB_24BPP=y
+CONFIG_PLAT_S3C=y
+
+#
+# Boot options
+#
+CONFIG_S3C_BOOT_ERROR_RESET=y
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+
+#
+# Power management
+#
+# CONFIG_S3C2410_PM_DEBUG is not set
+# CONFIG_S3C2410_PM_CHECK is not set
+CONFIG_S3C_LOWLEVEL_UART_PORT=3
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_S3C_GPIO_CFG_S3C24XX=y
+CONFIG_S3C_GPIO_CFG_S3C64XX=y
+CONFIG_S3C_DEV_HSMMC=y
+CONFIG_S3C_DEV_HSMMC1=y
+CONFIG_S3C_DEV_I2C1=y
+CONFIG_S3C_DEV_FB=y
+CONFIG_CPU_S3C6410=y
+CONFIG_S3C6410_SETUP_SDHCI=y
+# CONFIG_MACH_SMDK6410 is not set
+CONFIG_MACH_OPENMOKO_GTA03=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_VIC=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+# CONFIG_NF_CONNTRACK is not set
+CONFIG_NETFILTER_XTABLES=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_IP6_NF_QUEUE is not set
+CONFIG_IP6_NF_IPTABLES=m
+# CONFIG_IP6_NF_MATCH_AH is not set
+# CONFIG_IP6_NF_MATCH_EUI64 is not set
+# CONFIG_IP6_NF_MATCH_FRAG is not set
+# CONFIG_IP6_NF_MATCH_OPTS is not set
+# CONFIG_IP6_NF_MATCH_HL is not set
+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
+# CONFIG_IP6_NF_MATCH_MH is not set
+# CONFIG_IP6_NF_MATCH_RT is not set
+# CONFIG_IP6_NF_TARGET_LOG is not set
+# CONFIG_IP6_NF_FILTER is not set
+# CONFIG_IP6_NF_MANGLE is not set
+# CONFIG_IP6_NF_RAW is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=y
+CONFIG_NL80211=y
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+CONFIG_MTD_ONENAND_GENERIC=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_LOW_MEMORY_KILLER=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_KEYBOARD_NEO1973=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_FILTER=y
+CONFIG_TOUCHSCREEN_FILTER_GROUP=y
+CONFIG_TOUCHSCREEN_FILTER_MEDIAN=y
+CONFIG_TOUCHSCREEN_FILTER_MEAN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+CONFIG_INPUT_MISC=y
+CONFIG_TOUCHSCREEN_PCAP7200=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+CONFIG_INPUT_LIS302DL=y
+CONFIG_INPUT_PCF50633_PMU=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_NR_TTY_DEVICES=6
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=4
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C6400=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF50606 is not set
+# CONFIG_SENSORS_PCF50633 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL256X is not set
+CONFIG_PCA9632=y
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_BQ27000_HDQ is not set
+CONFIG_CHARGER_PCF50633=y
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+CONFIG_MFD_PCF50633=y
+CONFIG_PCF50633_ADC=y
+CONFIG_PCF50633_GPIO=y
+# CONFIG_MFD_PCF50606 is not set
+# CONFIG_MFD_GLAMO is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S3C=y
+# CONFIG_FB_S3C_DEBUG_REGWRITE is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_DISPLAY_JBT6K74 is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_COMPAT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_AR6000_WLAN is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+# CONFIG_LEDS_CLASS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_PCF50633=y
+# CONFIG_RTC_DRV_PCF50606 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+
+#
+# Android
+#
+CONFIG_ANDROID_BINDER_IPC=y
+# CONFIG_ANDROID_POWER is not set
+CONFIG_ANDROID_LOGGER=y
+# CONFIG_ANDROID_RAM_CONSOLE is not set
+# CONFIG_ANDROID_TIMED_GPIO is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+CONFIG_REGULATOR_PCF50633=y
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+CONFIG_DYNAMIC_PRINTK_DEBUG=y
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=3
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
--- /dev/null
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -0,0 +1,845 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc3
+# Mon Nov 3 10:10:30 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+CONFIG_ARCH_S3C64XX=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+CONFIG_PLAT_S3C64XX=y
+CONFIG_CPU_S3C6400_INIT=y
+CONFIG_CPU_S3C6400_CLOCK=y
+CONFIG_S3C64XX_SETUP_I2C0=y
+CONFIG_S3C64XX_SETUP_I2C1=y
+CONFIG_PLAT_S3C=y
+
+#
+# Boot options
+#
+CONFIG_S3C_BOOT_ERROR_RESET=y
+
+#
+# Power management
+#
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_S3C_GPIO_CFG_S3C24XX=y
+CONFIG_S3C_GPIO_CFG_S3C64XX=y
+CONFIG_S3C_DEV_HSMMC=y
+CONFIG_S3C_DEV_HSMMC1=y
+CONFIG_S3C_DEV_I2C1=y
+CONFIG_CPU_S3C6410=y
+CONFIG_S3C6410_SETUP_SDHCI=y
+CONFIG_MACH_SMDK6410=y
+CONFIG_SMDK6410_SD_CH0=y
+# CONFIG_SMDK6410_SD_CH1 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_ARM_VIC=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=4
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_S3C6400=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_S3C2410=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+CONFIG_AT24=y
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_COMPAT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_S3C=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=0
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -498,6 +498,13 @@
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
the Samsung SMDK2410 development board (and derivatives).
+config ARCH_S3C64XX
+ bool "Samsung S3C64XX"
+ select GENERIC_GPIO
+ select HAVE_CLK
+ help
+ Samsung S3C64XX series based systems
+
config ARCH_SHARK
bool "Shark"
select ISA
@@ -590,6 +597,7 @@
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
+source "arch/arm/plat-s3c64xx/Kconfig"
source "arch/arm/plat-s3c/Kconfig"
if ARCH_S3C2410
@@ -601,6 +609,11 @@
source "arch/arm/mach-s3c2443/Kconfig"
endif
+if ARCH_S3C64XX
+source "arch/arm/mach-s3c6400/Kconfig"
+source "arch/arm/mach-s3c6410/Kconfig"
+endif
+
source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-imx/Kconfig"
@@ -1256,6 +1269,8 @@
source "drivers/uwb/Kconfig"
+source "drivers/ar6000/Kconfig"
+
source "drivers/mmc/Kconfig"
source "drivers/memstick/Kconfig"
@@ -1268,6 +1283,8 @@
source "drivers/dma/Kconfig"
+source "drivers/android/Kconfig"
+
source "drivers/dca/Kconfig"
source "drivers/auxdisplay/Kconfig"
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -106,6 +106,8 @@
*(.got) /* Global offset table */
}
+ NOTES
+
RODATA
_etext = .; /* End of text and rodata section */
--- a/arch/arm/mach-s3c2410/clock.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/clock.c
- *
- * Copyright (c) 2006 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410,S3C2440,S3C2442 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/sysdev.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/serial_core.h>
-#include <linux/io.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-
-#include <plat/regs-serial.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/s3c2410.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-int s3c2410_clkcon_enable(struct clk *clk, int enable)
-{
- unsigned int clocks = clk->ctrlbit;
- unsigned long clkcon;
-
- clkcon = __raw_readl(S3C2410_CLKCON);
-
- if (enable)
- clkcon |= clocks;
- else
- clkcon &= ~clocks;
-
- /* ensure none of the special function bits set */
- clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
-
- __raw_writel(clkcon, S3C2410_CLKCON);
-
- return 0;
-}
-
-static int s3c2410_upll_enable(struct clk *clk, int enable)
-{
- unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
- unsigned long orig = clkslow;
-
- if (enable)
- clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
- else
- clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
-
- __raw_writel(clkslow, S3C2410_CLKSLOW);
-
- /* if we started the UPLL, then allow to settle */
-
- if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
- udelay(200);
-
- return 0;
-}
-
-/* standard clock definitions */
-
-static struct clk init_clocks_disable[] = {
- {
- .name = "nand",
- .id = -1,
- .parent = &clk_h,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_NAND,
- }, {
- .name = "sdi",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_SDI,
- }, {
- .name = "adc",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_ADC,
- }, {
- .name = "i2c",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_IIC,
- }, {
- .name = "iis",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_IIS,
- }, {
- .name = "spi",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_SPI,
- }
-};
-
-static struct clk init_clocks[] = {
- {
- .name = "lcd",
- .id = -1,
- .parent = &clk_h,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_LCDC,
- }, {
- .name = "gpio",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_GPIO,
- }, {
- .name = "usb-host",
- .id = -1,
- .parent = &clk_h,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_USBH,
- }, {
- .name = "usb-device",
- .id = -1,
- .parent = &clk_h,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_USBD,
- }, {
- .name = "timers",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_PWMT,
- }, {
- .name = "uart",
- .id = 0,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_UART0,
- }, {
- .name = "uart",
- .id = 1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_UART1,
- }, {
- .name = "uart",
- .id = 2,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_UART2,
- }, {
- .name = "rtc",
- .id = -1,
- .parent = &clk_p,
- .enable = s3c2410_clkcon_enable,
- .ctrlbit = S3C2410_CLKCON_RTC,
- }, {
- .name = "watchdog",
- .id = -1,
- .parent = &clk_p,
- .ctrlbit = 0,
- }, {
- .name = "usb-bus-host",
- .id = -1,
- .parent = &clk_usb_bus,
- }, {
- .name = "usb-bus-gadget",
- .id = -1,
- .parent = &clk_usb_bus,
- },
-};
-
-/* s3c2410_baseclk_add()
- *
- * Add all the clocks used by the s3c2410 or compatible CPUs
- * such as the S3C2440 and S3C2442.
- *
- * We cannot use a system device as we are needed before any
- * of the init-calls that initialise the devices are actually
- * done.
-*/
-
-int __init s3c2410_baseclk_add(void)
-{
- unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
- unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
- struct clk *clkp;
- struct clk *xtal;
- int ret;
- int ptr;
-
- clk_upll.enable = s3c2410_upll_enable;
-
- if (s3c24xx_register_clock(&clk_usb_bus) < 0)
- printk(KERN_ERR "failed to register usb bus clock\n");
-
- /* register clocks from clock array */
-
- clkp = init_clocks;
- for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
- /* ensure that we note the clock state */
-
- clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
-
- ret = s3c24xx_register_clock(clkp);
- if (ret < 0) {
- printk(KERN_ERR "Failed to register clock %s (%d)\n",
- clkp->name, ret);
- }
- }
-
- /* We must be careful disabling the clocks we are not intending to
- * be using at boot time, as subsystems such as the LCD which do
- * their own DMA requests to the bus can cause the system to lockup
- * if they where in the middle of requesting bus access.
- *
- * Disabling the LCD clock if the LCD is active is very dangerous,
- * and therefore the bootloader should be careful to not enable
- * the LCD clock if it is not needed.
- */
-
- /* install (and disable) the clocks we do not need immediately */
-
- clkp = init_clocks_disable;
- for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-
- ret = s3c24xx_register_clock(clkp);
- if (ret < 0) {
- printk(KERN_ERR "Failed to register clock %s (%d)\n",
- clkp->name, ret);
- }
-
- s3c2410_clkcon_enable(clkp, 0);
- }
-
- /* show the clock-slow value */
-
- xtal = clk_get(NULL, "xtal");
-
- printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
- print_mhz(clk_get_rate(xtal) /
- ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
- (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
- (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
- (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
-
- return 0;
-}
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -25,12 +25,12 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
[DMACH_XD0] = {
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h
@@ -0,0 +1,60 @@
+#ifndef _LINUX_FIQ_IPC_H
+#define _LINUX_FIQ_IPC_H
+
+/*
+ * this defines the struct which is used to communicate between the FIQ
+ * world and the normal linux kernel world. One of these structs is
+ * statically defined for you in the monolithic kernel so the FIQ ISR code
+ * can safely touch it any any time.
+ *
+ * You also want to include this file in your kernel module that wants to
+ * communicate with your FIQ code. Add any kinds of vars that are used by
+ * the FIQ ISR and the module in here.
+ *
+ * To get you started there is just an int that is incremented every FIQ
+ * you can remove this when you are ready to customize, but it is useful
+ * for testing
+ */
+
+#include <mach/pwm.h>
+#include <plat/regs-timer.h>
+
+extern u8 fiq_ready;
+
+enum hdq_bitbang_states {
+ HDQB_IDLE = 0,
+ HDQB_TX_BREAK,
+ HDQB_TX_BREAK_RECOVERY,
+ HDQB_ADS_CALC,
+ HDQB_ADS_LOW,
+ HDQB_ADS_HIGH,
+ HDQB_WAIT_RX,
+ HDQB_DATA_RX_LOW,
+ HDQB_DATA_RX_HIGH,
+ HDQB_WAIT_TX,
+};
+
+struct fiq_ipc {
+ /* vibrator */
+ unsigned long vib_gpio_pin; /* which pin to meddle with */
+ u8 vib_pwm; /* 0 = OFF -- will ensure GPIO deasserted and stop FIQ */
+ u8 vib_pwm_latched;
+
+ /* hdq */
+ u8 hdq_probed; /* nonzero after HDQ driver probed */
+ struct mutex hdq_lock; /* if you want to use hdq, you have to take lock */
+ unsigned long hdq_gpio_pin; /* GTA02 = GPD14 which pin to meddle with */
+ u8 hdq_ads; /* b7..b6 = register address, b0 = r/w */
+ u8 hdq_tx_data; /* data to tx for write action */
+ u8 hdq_rx_data; /* data received in read action */
+ u8 hdq_request_ctr; /* incremented by "user" to request a transfer */
+ u8 hdq_transaction_ctr; /* incremented after each transfer */
+ u8 hdq_error; /* 0 = no error */
+};
+
+/* actual definition lives in arch/arm/mach-s3c2440/fiq_c_isr.c */
+extern struct fiq_ipc fiq_ipc;
+extern unsigned long _fiq_count_fiqs;
+extern void fiq_kick(void); /* provoke a FIQ "immediately" */
+
+#endif /* _LINUX_FIQ_IPC_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C2410 - GPIO core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_CORE_H
+#define __ASM_ARCH_GPIO_CORE_H __FILE__
+
+/* currently we just include the platform support */
+#include <plat/gpio-core.h>
+
+#endif /* __ASM_ARCH_GPIO_CORE_H */
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -15,4 +15,14 @@
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
+/* These two defines should be removed as soon as the
+ * generic irq handling makes it upstream */
+#include <mach/hardware.h>
+#define gpio_to_irq(gpio) s3c2410_gpio_getirq(gpio)
+#define irq_to_gpio(irq) s3c2410_gpio_irq2pin(irq)
+/* -- cut to here when generic irq makes it */
+
#include <asm-generic/gpio.h>
+#include <mach/gpio-nrs.h>
+
+#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - GPIO bank numbering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
+
+#define S3C2410_GPIO_BANKA (32*0)
+#define S3C2410_GPIO_BANKB (32*1)
+#define S3C2410_GPIO_BANKC (32*2)
+#define S3C2410_GPIO_BANKD (32*3)
+#define S3C2410_GPIO_BANKE (32*4)
+#define S3C2410_GPIO_BANKF (32*5)
+#define S3C2410_GPIO_BANKG (32*6)
+#define S3C2410_GPIO_BANKH (32*7)
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gta01.h
@@ -0,0 +1,74 @@
+#ifndef _GTA01_H
+#define _GTA01_H
+
+#include <mach/regs-gpio.h>
+#include <mach/irqs.h>
+
+/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
+#define GTA01v3_SYSTEM_REV 0x00000130
+#define GTA01v4_SYSTEM_REV 0x00000140
+#define GTA01Bv2_SYSTEM_REV 0x00000220
+#define GTA01Bv3_SYSTEM_REV 0x00000230
+#define GTA01Bv4_SYSTEM_REV 0x00000240
+
+/* Backlight */
+
+extern void gta01bl_deferred_resume(void);
+
+struct gta01bl_machinfo {
+ unsigned int default_intensity;
+ unsigned int max_intensity;
+ unsigned int limit_mask;
+ unsigned int defer_resume_backlight;
+};
+
+/* Definitions common to all revisions */
+#define GTA01_GPIO_BACKLIGHT S3C2410_GPB0
+#define GTA01_GPIO_GPS_PWRON S3C2410_GPB1
+#define GTA01_GPIO_MODEM_RST S3C2410_GPB6
+#define GTA01_GPIO_MODEM_ON S3C2410_GPB7
+#define GTA01_GPIO_LCD_RESET S3C2410_GPC6
+#define GTA01_GPIO_PMU_IRQ S3C2410_GPG8
+#define GTA01_GPIO_JACK_INSERT S3C2410_GPF4
+#define GTA01_GPIO_nSD_DETECT S3C2410_GPF5
+#define GTA01_GPIO_AUX_KEY S3C2410_GPF6
+#define GTA01_GPIO_HOLD_KEY S3C2410_GPF7
+#define GTA01_GPIO_VIBRATOR_ON S3C2410_GPG11
+
+#define GTA01_IRQ_MODEM IRQ_EINT1
+#define GTA01_IRQ_JACK_INSERT IRQ_EINT4
+#define GTA01_IRQ_nSD_DETECT IRQ_EINT5
+#define GTA01_IRQ_AUX_KEY IRQ_EINT6
+#define GTA01_IRQ_PCF50606 IRQ_EINT16
+
+/* GTA01v3 */
+#define GTA01v3_GPIO_nGSM_EN S3C2410_GPG9
+
+/* GTA01v4 */
+#define GTA01_GPIO_MODEM_DNLOAD S3C2410_GPG0
+
+/* GTA01Bv2 */
+#define GTA01Bv2_GPIO_nGSM_EN S3C2410_GPF2
+#define GTA01Bv2_GPIO_VIBRATOR_ON S3C2410_GPB10
+
+/* GTA01Bv3 */
+#define GTA01_GPIO_GPS_EN_3V3 S3C2410_GPG9
+
+#define GTA01_GPIO_SDMMC_ON S3C2410_GPB2
+#define GTA01_GPIO_BT_EN S3C2410_GPB5
+#define GTA01_GPIO_AB_DETECT S3C2410_GPB8
+#define GTA01_GPIO_USB_PULLUP S3C2410_GPB9
+#define GTA01_GPIO_USB_ATTACH S3C2410_GPB10
+
+#define GTA01_GPIO_GPS_EN_2V8 S3C2410_GPG9
+#define GTA01_GPIO_GPS_EN_3V S3C2410_GPG10
+#define GTA01_GPIO_GPS_RESET S3C2410_GPC0
+
+/* GTA01Bv4 */
+#define GTA01Bv4_GPIO_nNAND_WP S3C2410_GPA16
+#define GTA01Bv4_GPIO_VIBRATOR_ON S3C2410_GPB3
+#define GTA01Bv4_GPIO_PMU_IRQ S3C2410_GPG1
+
+#define GTA01Bv4_IRQ_PCF50606 IRQ_EINT9
+
+#endif /* _GTA01_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gta02.h
@@ -0,0 +1,113 @@
+#ifndef _GTA02_H
+#define _GTA02_H
+
+#include <mach/regs-gpio.h>
+#include <mach/irqs.h>
+
+#include <linux/mfd/pcf50633/core.h>
+
+/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
+#define GTA02v1_SYSTEM_REV 0x00000310
+#define GTA02v2_SYSTEM_REV 0x00000320
+#define GTA02v3_SYSTEM_REV 0x00000330
+#define GTA02v4_SYSTEM_REV 0x00000340
+#define GTA02v5_SYSTEM_REV 0x00000350
+#define GTA02v6_SYSTEM_REV 0x00000360
+
+#define GTA02_GPIO_n3DL_GSM S3C2410_GPA13 /* v1 + v2 + v3 only */
+
+#define GTA02_GPIO_PWR_LED1 S3C2410_GPB0
+#define GTA02_GPIO_PWR_LED2 S3C2410_GPB1
+#define GTA02_GPIO_AUX_LED S3C2410_GPB2
+#define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB3
+#define GTA02v1_GPIO_GPS_PWRON S3C2410_GPB4 /* v1 only */
+#define GTA02_GPIO_MODEM_RST S3C2410_GPB5
+#define GTA02_GPIO_BT_EN S3C2410_GPB6
+#define GTA02_GPIO_MODEM_ON S3C2410_GPB7
+#define GTA02v1_GPIO_EN_AGPS3V S3C2410_GPB8 /* v1 only */
+#define GTA02_GPIO_EXTINT8 S3C2410_GPB8
+#define GTA02_GPIO_USB_PULLUP S3C2410_GPB9
+
+#define GTA02v1_GPIO_nGPS_RST S3C2410_GPC0 /* v1 only */
+#define GTA02v12_GPIO_PIO3 S3C2410_GPC5 /* v1 + v2 only */
+#define GTA02_GPIO_PIO5 S3C2410_GPC5 /* v3 + v4 only */
+#define GTA02_GPIO_LCD_RESET S3C2410_GPC6 /* v1 + v2 only */
+#define GTA02v12_GPIO_PIO2 S3C2410_GPC7 /* v1 + v2 only */
+#define GTA02v2_nUSB_FLT S3C2410_GPC9 /* v2 only */
+#define GTA02v2_nUSB_OC S3C2410_GPC10 /* v2 only */
+#define GTA02v2_nGSM_OC S3C2410_GPC12 /* v2 only */
+
+#define GTA02v3_GPIO_nG1_CS S3C2410_GPD12 /* v3 + v4 only */
+#define GTA02v3_GPIO_nG2_CS S3C2410_GPD13 /* v3 + v4 only */
+#define GTA02v5_GPIO_HDQ S3C2410_GPD14 /* v5 + */
+
+#define GTA02_GPIO_nG1_INT S3C2410_GPF0
+#define GTA02_GPIO_IO1 S3C2410_GPF1
+#define GTA02v1_GPIO_nG2_INT S3C2410_GPF2 /* v1 only */
+#define GTA02_GPIO_PIO_2 S3C2410_GPF2 /* v2 + v3 + v4 only */
+#define GTA02_GPIO_JACK_INSERT S3C2410_GPF4
+#define GTA02v1_GPIO_nSD_DETECT S3C2410_GPF5 /* v1 only */
+#define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF5 /* v2 + v3 + v4 only */
+#define GTA02_GPIO_AUX_KEY S3C2410_GPF6
+#define GTA02_GPIO_HOLD_KEY S3C2410_GPF7
+
+#define GTA02_GPIO_3D_IRQ S3C2410_GPG4
+#define GTA02v1_GPIO_nG1_CS S3C2410_GPG8 /* v1 only */
+#define GTA02v2_GPIO_nG2_INT S3C2410_GPG8 /* v2 + v3 + v4 only */
+#define GTA02v3_GPIO_nUSB_OC S3C2410_GPG9 /* v3 + v4 only */
+#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG10 /* v3 + v4 only */
+#define GTA02v1_GPIO_nG2_CS S3C2410_GPG11 /* v1 only */
+#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG11 /* v3 + v4 only */
+
+#define GTA02v1_GPIO_3D_RESET S3C2440_GPJ0 /* v1 only */
+#define GTA02v2_GPIO_BAT_ID S3C2440_GPJ0 /* v2 only */
+#define GTA02v1_GPIO_WLAN_GPIO8 S3C2440_GPJ1 /* v1 only */
+#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */
+#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2
+#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */
+#define GTA02v1_GPIO_KEEPACT S3C2440_GPJ3 /* v1 only */
+#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */
+#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4
+#define GTA02_GPIO_3D_RESET S3C2440_GPJ5
+#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */
+#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7
+#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8
+#define GTA02_GPIO_KEEPACT S3C2440_GPJ8
+#define GTA02v1_GPIO_AMP_SHUT S3C2440_GPJ9 /* v1 only */
+#define GTA02v2_nG1_CS S3C2440_GPJ9 /* v2 only */
+#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10
+#define GTA02v2_nG2_CS S3C2440_GPJ10 /* v2 only */
+#define GTA02v1_GPIO_INT0 S3C2440_GPJ11 /* v1 only */
+#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */
+#define GTA02v1_GPIO_nGSM_EN S3C2440_GPJ12 /* v1 only */
+#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */
+
+#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
+#define GTA02_IRQ_MODEM IRQ_EINT1
+#define GTA02v1_IRQ_GSENSOR_2 IRQ_EINT2 /* v1 only */
+#define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */
+#define GTA02_IRQ_nJACK_INSERT IRQ_EINT4
+#define GTA02v1_IRQ_nSD_CD IRQ_EINT5 /* v1 only */
+#define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5
+#define GTA02_IRQ_AUX IRQ_EINT6
+#define GTA02_IRQ_nHOLD IRQ_EINT7
+#define GTA02v1_IRQ_nSIM_CD IRQ_EINT8 /* v1 only */
+#define GTA02_IRQ_PCF50633 IRQ_EINT9
+#define GTA02_IRQ_3D IRQ_EINT12
+#define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */
+#define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */
+#define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */
+#define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */
+
+/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
+#define GTA02_PCB_ID1_0 S3C2410_GPC13
+#define GTA02_PCB_ID1_1 S3C2410_GPC15
+#define GTA02_PCB_ID1_2 S3C2410_GPD0
+#define GTA02_PCB_ID2_0 S3C2410_GPD3
+#define GTA02_PCB_ID2_1 S3C2410_GPD4
+
+int gta02_get_pcb_revision(void);
+
+extern struct pcf50633_platform_data gta02_pcf_pdata;
+
+#endif /* _GTA02_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gta02-pm-wlan.h
@@ -0,0 +1 @@
+void gta02_wlan_power(int on);
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -12,9 +12,9 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
-#ifndef __ASM_ARM_IRQ_H
-#error "Do not include this directly, instead #include <asm/irq.h>"
-#endif
+//#ifndef __ASM_ARM_IRQ_H
+//#error "Do not include this directly, instead #include <asm/irq.h>"
+//#endif
/* we keep the first set of CPU IRQs out of the range of
* the ISA space, so that the PC104 has them to itself
@@ -84,7 +84,7 @@
#define IRQ_EINT22 S3C2410_IRQ(50)
#define IRQ_EINT23 S3C2410_IRQ(51)
-
+#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
#define IRQ_LCD_FIFO S3C2410_IRQ(52)
@@ -134,6 +134,8 @@
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
+#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
+
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
@@ -155,12 +157,47 @@
#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
#ifdef CONFIG_CPU_S3C2443
-#define NR_IRQS (IRQ_S3C2443_AC97+1)
+#define _NR_IRQS (IRQ_S3C2443_AC97+1)
#else
-#define NR_IRQS (IRQ_S3C2440_AC97+1)
+#define _NR_IRQS (IRQ_S3C2440_AC97+1)
#endif
+/* compatibility define. */
+#define IRQ_UART3 IRQ_S3C2443_UART3
+#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
+#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
+#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
+
/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
#define FIQ_START IRQ_EINT0
+
+/*
+ * The next 16 interrupts are for board specific purposes. Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these. If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.
+ */
+#define IRQ_BOARD_START _NR_IRQS
+#define IRQ_BOARD_END (_NR_IRQS + 10)
+
+#if defined(CONFIG_MACH_NEO1973_GTA02)
+#define NR_IRQS (IRQ_BOARD_END)
+#else
+#define NR_IRQS (IRQ_BOARD_START)
+#endif
+
+/* Neo1973 GTA02 interrupts */
+#define NEO1973_GTA02_IRQ(x) (IRQ_BOARD_START + (x))
+#define IRQ_GLAMO(x) NEO1973_GTA02_IRQ(x)
+#define IRQ_GLAMO_HOSTBUS IRQ_GLAMO(0)
+#define IRQ_GLAMO_JPEG IRQ_GLAMO(1)
+#define IRQ_GLAMO_MPEG IRQ_GLAMO(2)
+#define IRQ_GLAMO_MPROC1 IRQ_GLAMO(3)
+#define IRQ_GLAMO_MPROC0 IRQ_GLAMO(4)
+#define IRQ_GLAMO_CMDQUEUE IRQ_GLAMO(5)
+#define IRQ_GLAMO_2D IRQ_GLAMO(6)
+#define IRQ_GLAMO_MMC IRQ_GLAMO(7)
+#define IRQ_GLAMO_RISC IRQ_GLAMO(8)
+
#endif /* __ASM_ARCH_IRQ_H */
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -13,34 +13,20 @@
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H
+#include <plat/map-base.h>
#include <plat/map.h>
#define S3C2410_ADDR(x) S3C_ADDR(x)
-/* interrupt controller is the first thing we put in, to make
- * the assembly code for the irq detection easier
- */
-#define S3C24XX_VA_IRQ S3C_VA_IRQ
-#define S3C2410_PA_IRQ (0x4A000000)
-#define S3C24XX_SZ_IRQ SZ_1M
-
-/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C2410_PA_MEMCTRL (0x48000000)
-#define S3C24XX_SZ_MEMCTRL SZ_1M
-
/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)
-#define S3C24XX_SZ_USBHOST SZ_1M
/* DMA controller */
#define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M
/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR S3C_VA_SYS
#define S3C2410_PA_CLKPWR (0x4C000000)
-#define S3C24XX_SZ_CLKPWR SZ_1M
/* LCD controller */
#define S3C2410_PA_LCD (0x4D000000)
@@ -48,48 +34,12 @@
/* NAND flash controller */
#define S3C2410_PA_NAND (0x4E000000)
-#define S3C24XX_SZ_NAND SZ_1M
-
-/* UARTs */
-#define S3C24XX_VA_UART S3C_VA_UART
-#define S3C2410_PA_UART (0x50000000)
-#define S3C24XX_SZ_UART SZ_1M
-
-/* Timers */
-#define S3C24XX_VA_TIMER S3C_VA_TIMER
-#define S3C2410_PA_TIMER (0x51000000)
-#define S3C24XX_SZ_TIMER SZ_1M
-
-/* USB Device port */
-#define S3C2410_PA_USBDEV (0x52000000)
-#define S3C24XX_SZ_USBDEV SZ_1M
-
-/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-#define S3C2410_PA_WATCHDOG (0x53000000)
-#define S3C24XX_SZ_WATCHDOG SZ_1M
/* IIC hardware controller */
#define S3C2410_PA_IIC (0x54000000)
-#define S3C24XX_SZ_IIC SZ_1M
/* IIS controller */
#define S3C2410_PA_IIS (0x55000000)
-#define S3C24XX_SZ_IIS SZ_1M
-
-/* GPIO ports */
-
-/* the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 maping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
-*/
-
-#define S3C2410_PA_GPIO (0x56000000)
-#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
-#define S3C24XX_SZ_GPIO SZ_1M
/* RTC */
#define S3C2410_PA_RTC (0x57000000)
@@ -97,15 +47,12 @@
/* ADC */
#define S3C2410_PA_ADC (0x58000000)
-#define S3C24XX_SZ_ADC SZ_1M
/* SPI */
#define S3C2410_PA_SPI (0x59000000)
-#define S3C24XX_SZ_SPI SZ_1M
/* SDI */
#define S3C2410_PA_SDI (0x5A000000)
-#define S3C24XX_SZ_SDI SZ_1M
/* CAMIF */
#define S3C2440_PA_CAMIF (0x4F000000)
@@ -120,13 +67,6 @@
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2443_SZ_HSMMC (256)
-/* ISA style IO, for each machine to sort out mappings for, if it
- * implements it. We reserve two 16M regions for ISA.
- */
-
-#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
-
/* physical addresses of all the chip-select areas */
#define S3C2410_CS0 (0x00000000)
@@ -152,27 +92,16 @@
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
-#define S3C24XX_PA_IIC S3C2410_PA_IIC
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
+#define S3C24XX_PA_SDI S3C2410_PA_SDI
+#define S3C24XX_PA_NAND S3C2410_PA_NAND
-/* deal with the registers that move under the 2412/2413 */
-
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-#ifndef __ASSEMBLY__
-extern void __iomem *s3c24xx_va_gpio2;
-#endif
-#ifdef CONFIG_CPU_S3C2412_ONLY
-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
-#else
-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
-#endif
-#else
-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
-#endif
+#define S3C_PA_IIC S3C2410_PA_IIC
+#define S3C_PA_UART S3C24XX_PA_UART
+#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#endif /* __ASM_ARCH_MAP_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/mci.h
@@ -0,0 +1,13 @@
+#ifndef _ARCH_MCI_H
+#define _ARCH_MCI_H
+
+struct s3c24xx_mci_pdata {
+ unsigned int gpio_detect;
+ unsigned int gpio_wprotect;
+ unsigned long ocr_avail;
+ unsigned int do_dma;
+ void (*set_power)(unsigned char power_mode,
+ unsigned short vdd);
+};
+
+#endif /* _ARCH_NCI_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/neo1973-pm-gsm.h
@@ -0,0 +1 @@
+extern int gta_gsm_interrupts;
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/pwm.h
@@ -0,0 +1,46 @@
+#ifndef __S3C2410_PWM_H
+#define __S3C2410_PWM_H
+
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <mach/io.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <plat/regs-timer.h>
+#include <mach/gta01.h>
+
+enum pwm_timer {
+ PWM0,
+ PWM1,
+ PWM2,
+ PWM3,
+ PWM4
+};
+
+struct s3c2410_pwm {
+ enum pwm_timer timerid;
+ struct clk *pclk;
+ unsigned long pclk_rate;
+ unsigned long prescaler;
+ unsigned long divider;
+ unsigned long counter;
+ unsigned long comparer;
+};
+
+struct s3c24xx_pwm_platform_data{
+ /* callback to attach platform children (to enforce suspend / resume
+ * ordering */
+ void (*attach_child_devices)(struct device *parent_device);
+};
+
+int s3c2410_pwm_init(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_enable(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_disable(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_start(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_stop(struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *s3c2410_pwm);
+int s3c2410_pwm_dumpregs(void);
+
+#endif /* __S3C2410_PWM_H */
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -42,13 +42,6 @@
#define S3C2410_CLKCON_IIS (1<<17)
#define S3C2410_CLKCON_SPI (1<<18)
-#define S3C2410_PLLCON_MDIVSHIFT 12
-#define S3C2410_PLLCON_PDIVSHIFT 4
-#define S3C2410_PLLCON_SDIVSHIFT 0
-#define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
-#define S3C2410_PLLCON_PDIVMASK ((1<<5)-1)
-#define S3C2410_PLLCON_SDIVMASK 3
-
/* DCLKCON register addresses in gpio.h */
#define S3C2410_DCLKCON_DCLK0EN (1<<0)
@@ -76,32 +69,6 @@
#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
-#ifndef __ASSEMBLY__
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
-{
- unsigned int mdiv, pdiv, sdiv;
- uint64_t fvco;
-
- mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
- pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
- sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
-
- mdiv &= S3C2410_PLLCON_MDIVMASK;
- pdiv &= S3C2410_PLLCON_PDIVMASK;
- sdiv &= S3C2410_PLLCON_SDIVMASK;
-
- fvco = (uint64_t)baseclk * (mdiv + 8);
- do_div(fvco, (pdiv + 2) << sdiv);
-
- return (unsigned int)fvco;
-}
-
-#endif /* __ASSEMBLY__ */
-
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
/* extra registers */
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -14,16 +14,7 @@
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H
-#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
-
-#define S3C2410_GPIO_BANKA (32*0)
-#define S3C2410_GPIO_BANKB (32*1)
-#define S3C2410_GPIO_BANKC (32*2)
-#define S3C2410_GPIO_BANKD (32*3)
-#define S3C2410_GPIO_BANKE (32*4)
-#define S3C2410_GPIO_BANKF (32*5)
-#define S3C2410_GPIO_BANKG (32*6)
-#define S3C2410_GPIO_BANKH (32*7)
+#include <mach/gpio-nrs.h>
#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
@@ -1053,13 +1044,6 @@
#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
-/* values for S3C2410_EXTINT0/1/2 */
-#define S3C2410_EXTINT_LOWLEV (0x00)
-#define S3C2410_EXTINT_HILEV (0x01)
-#define S3C2410_EXTINT_FALLEDGE (0x02)
-#define S3C2410_EXTINT_RISEEDGE (0x04)
-#define S3C2410_EXTINT_BOTHEDGE (0x06)
-
/* interrupt filtering conrrol for EINT16..EINT23 */
#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
--- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
@@ -30,6 +30,7 @@
#define S3C2410_SDIFSTA (0x38)
#define S3C2410_SDIDATA (0x3C)
+#define S3C2410_SDIDATA_BYTE (0x3C)
#define S3C2410_SDIIMSK (0x40)
#define S3C2440_SDIDATA (0x40)
@@ -37,6 +38,8 @@
#define S3C2440_SDICON_SDRESET (1<<8)
#define S3C2440_SDICON_MMCCLOCK (1<<5)
+#define S3C2440_SDIDATA_BYTE (0x48)
+
#define S3C2410_SDICON_BYTEORDER (1<<4)
#define S3C2410_SDICON_SDIOIRQ (1<<3)
#define S3C2410_SDICON_RWAITEN (1<<2)
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/s3c24xx-serial.h
@@ -0,0 +1,5 @@
+#include <linux/resume-dependency.h>
+
+extern void s3c24xx_serial_console_set_silence(int silence);
+extern void s3c24xx_serial_register_resume_dependency(struct resume_dependency *
+ resume_dependency, int uart_index);
--- a/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi-gpio.h
@@ -21,7 +21,15 @@
int num_chipselect;
int bus_num;
- void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
+ /*
+ * FIXME: board_size and board_info DO NOT belong here.
+ * These were already removed upstream... but we still rely on them
+ * so leave for now and revisit this.
+ */
+ unsigned long board_size;
+ struct spi_board_info *board_info;
+
+ void (*chip_select)(struct s3c2410_spigpio_info *spi, int csid, int cs);
};
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -22,5 +22,12 @@
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
};
+/* Standard setup / suspend routines for SPI GPIO pins. */
+
+extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
+ int enable);
+
+extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
+ int enable);
#endif /* __ASM_ARCH_SPI_H */
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h
@@ -13,7 +13,7 @@
#include <mach/hardware.h>
#include <linux/io.h>
-#include <asm/plat-s3c/regs-watchdog.h>
+#include <plat/regs-watchdog.h>
#include <mach/regs-clock.h>
#include <linux/clk.h>
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/tick.h
@@ -0,0 +1,15 @@
+/* linux/arch/arm/mach-s3c2410/include/mach/tick.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C2410 - timer tick support
+ */
+
+#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
+
+static inline int s3c24xx_ostimer_pending(void)
+{
+ return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4;
+}
--- a/arch/arm/mach-s3c2410/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/timex.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-
-
-#define CLOCK_TICK_RATE 12000000
-
-
-#endif /* __ASM_ARCH_TIMEX_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/ts.h
@@ -0,0 +1,35 @@
+/* arch/arm/mach-s3c2410/include/mach/ts.h
+ *
+ * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * Changelog:
+ * 24-Mar-2005 RTP Created file
+ * 03-Aug-2005 RTP Renamed to ts.h
+ */
+
+#ifndef __ASM_ARM_TS_H
+#define __ASM_ARM_TS_H
+
+#include <linux/ts_filter.h>
+
+struct s3c2410_ts_mach_info {
+ int delay;
+ int presc;
+ /* array of pointers to filter APIs we want to use, in order
+ * ends on first NULL, all NULL is OK
+ */
+ struct ts_filter_api *filter_sequence[MAX_TS_FILTER_CHAIN];
+ /* array of configuration ints, one for each filter above */
+ void *filter_config[MAX_TS_FILTER_CHAIN];
+};
+
+void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info);
+
+#endif /* __ASM_ARM_TS_H */
+
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -1,3 +1,4 @@
+
/* arch/arm/mach-s3c2410/include/mach/uncompress.h
*
* Copyright (c) 2003, 2007 Simtec Electronics
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
- *
- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 vmalloc definition
-*/
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END (0xE0000000)
-
-#endif /* __ASM_ARCH_VMALLOC_H */
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -9,6 +9,7 @@
depends on ARCH_S3C2410
select S3C2410_CLOCK
select S3C2410_GPIO
+ select S3C2410_PWM
select CPU_LLSERIAL_S3C2410
select S3C2410_PM if PM
help
@@ -32,11 +33,6 @@
help
GPIO code for S3C2410 and similar processors
-config S3C2410_CLOCK
- bool
- help
- Clock code for the S3C2410, and similar processors
-
config SIMTEC_NOR
bool
help
@@ -49,6 +45,12 @@
Internal node for machines with an BAST style IDE
interface
+config S3C2410_PWM
+ bool
+ help
+ PWM timer code for the S3C2410, and similar processors
+
+
menu "S3C2410 Machines"
config ARCH_SMDK2410
@@ -84,6 +86,7 @@
select PM_SIMTEC if PM
select SIMTEC_NOR
select MACH_BAST_IDE
+ select S3C24XX_DCLK
select ISA
help
Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -121,6 +124,7 @@
config MACH_VR1000
bool "Thorcom VR1000"
select PM_SIMTEC if PM
+ select S3C24XX_DCLK
select SIMTEC_NOR
select MACH_BAST_IDE
select CPU_S3C2410
@@ -130,7 +134,16 @@
config MACH_QT2410
bool "QT2410"
select CPU_S3C2410
+ select DISPLAY_JBT6K74
help
Say Y here if you are using the Armzone QT2410
+config MACH_NEO1973_GTA01
+ bool "FIC Neo1973 GSM Phone (GTA01 Hardware)"
+ select CPU_S3C2410
+ select MACH_NEO1973
+ select SENSORS_PCF50606
+ help
+ Say Y here if you are using the FIC Neo1973 GSM Phone
+
endmenu
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -52,6 +52,7 @@
#include <mach/regs-lcd.h>
#include <mach/regs-gpio.h>
+#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@@ -150,7 +151,7 @@
#endif
&s3c_device_adc,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
@@ -233,6 +234,7 @@
#ifdef CONFIG_FB_S3C2410
s3c24xx_fb_set_platdata(&amlm5900_fb_info);
#endif
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
}
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -44,8 +44,8 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
#include <mach/fb.h>
#include <linux/mtd/mtd.h>
@@ -406,7 +406,7 @@
* standard 100KHz i2c bus frequency
*/
-static struct s3c2410_platform_i2c bast_i2c_info = {
+static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
@@ -553,7 +553,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&bast_device_dm9k,
@@ -588,7 +588,8 @@
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_nand.dev.platform_data = &bast_nand_info;
- s3c_device_i2c.dev.platform_data = &bast_i2c_info;
+
+ s3c_i2c0_set_platdata(&bast_i2c_info);
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);
--- /dev/null
+++ b/arch/arm/mach-s3c2410/mach-gta01.c
@@ -0,0 +1,786 @@
+/*
+ * linux/arch/arm/mach-s3c2410/mach-gta01.c
+ *
+ * S3C2410 Machine Support for the FIC Neo1973 GTA01
+ *
+ * Copyright (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/serial_core.h>
+#include <mach/ts.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/mmc/host.h>
+
+#include <linux/pcf50606.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/fb.h>
+#include <mach/mci.h>
+#include <mach/spi.h>
+#include <mach/spi-gpio.h>
+#include <mach/usb-control.h>
+
+#include <mach/gta01.h>
+
+#include <plat/regs-serial.h>
+#include <plat/nand.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/udc.h>
+#include <plat/iic.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+#include <mach/neo1973-pm-gsm.h>
+
+#include <linux/jbt6k74.h>
+
+#include <linux/ts_filter_mean.h>
+#include <linux/ts_filter_median.h>
+
+
+static struct map_desc gta01_iodesc[] __initdata = {
+ {
+ .virtual = 0xe0000000,
+ .pfn = __phys_to_pfn(S3C2410_CS3+0x01000000),
+ .length = SZ_1M,
+ .type = MT_DEVICE
+ },
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+/* UFCON for the gta01 sets the FIFO trigger level at 4, not 8 */
+#define UFCON_GTA01_PORT0 S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg gta01_uartcfgs[] = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON_GTA01_PORT0,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+};
+
+/* PMU driver info */
+
+static int pmu_callback(struct device *dev, unsigned int feature,
+ enum pmu_event event)
+{
+ switch (feature) {
+ case PCF50606_FEAT_ACD:
+ switch (event) {
+ case PMU_EVT_INSERT:
+ pcf50606_charge_fast(pcf50606_global, 1);
+ break;
+ case PMU_EVT_REMOVE:
+ pcf50606_charge_fast(pcf50606_global, 0);
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static struct pcf50606_platform_data gta01_pcf_pdata = {
+ .used_features = PCF50606_FEAT_EXTON |
+ PCF50606_FEAT_MBC |
+ PCF50606_FEAT_BBC |
+ PCF50606_FEAT_RTC |
+ PCF50606_FEAT_WDT |
+ PCF50606_FEAT_CHGCUR |
+ PCF50606_FEAT_BATVOLT |
+ PCF50606_FEAT_BATTEMP,
+ .onkey_seconds_required = 3,
+ .cb = &pmu_callback,
+ .r_fix_batt = 10000,
+ .r_fix_batt_par = 10000,
+ .r_sense_milli = 220,
+ .rails = {
+ [PCF50606_REGULATOR_D1REG] = {
+ .name = "bt_3v15",
+ .voltage = {
+ .init = 3150,
+ .max = 3150,
+ },
+ },
+ [PCF50606_REGULATOR_D2REG] = {
+ .name = "gl_2v5",
+ .voltage = {
+ .init = 2500,
+ .max = 2500,
+ },
+ },
+ [PCF50606_REGULATOR_D3REG] = {
+ .name = "stby_1v8",
+ .flags = PMU_VRAIL_F_SUSPEND_ON,
+ .voltage = {
+ .init = 1800,
+ .max = 2100,
+ },
+ },
+ [PCF50606_REGULATOR_DCD] = {
+ .name = "gl_1v5",
+ .voltage = {
+ .init = 1500,
+ .max = 1500,
+ },
+ },
+ [PCF50606_REGULATOR_DCDE] = {
+ .name = "io_3v3",
+ .flags = PMU_VRAIL_F_SUSPEND_ON,
+ .voltage = {
+ .init = 3300,
+ .max = 3330,
+ },
+ },
+ [PCF50606_REGULATOR_DCUD] = {
+ .name = "core_1v8",
+ .flags = PMU_VRAIL_F_SUSPEND_ON,
+ .voltage = {
+ .init = 2100,
+ .max = 2100,
+ },
+ },
+ [PCF50606_REGULATOR_IOREG] = {
+ .name = "codec_3v3",
+ .voltage = {
+ .init = 3300,
+ .max = 3300,
+ },
+ },
+ [PCF50606_REGULATOR_LPREG] = {
+ .name = "lcm_3v3",
+ .voltage = {
+ .init = 3300,
+ .max = 3300,
+ },
+ }
+ },
+};
+
+static void cfg_pmu_vrail(struct pmu_voltage_rail *vrail, char *name,
+ unsigned int flags, unsigned int init,
+ unsigned int max)
+{
+ vrail->name = name;
+ vrail->flags = flags;
+ vrail->voltage.init = init;
+ vrail->voltage.max = max;
+}
+
+static void mangle_pmu_pdata_by_system_rev(void)
+{
+ switch (system_rev) {
+ case GTA01Bv4_SYSTEM_REV:
+ gta01_pcf_pdata.used_features |= PCF50606_FEAT_ACD;
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
+ .name = "user1";
+ gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
+ .flags &= ~PMU_VRAIL_F_SUSPEND_ON;
+ gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG]
+ .flags = PMU_VRAIL_F_UNUSED;
+ break;
+ case GTA01v4_SYSTEM_REV:
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCUD],
+ "core_1v8", PMU_VRAIL_F_SUSPEND_ON, 1800, 1800);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D1REG],
+ "vrf_3v", 0, 3000, 3000);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG],
+ "vtcxo_2v8", 0, 2800, 2800);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCD],
+ "gl_3v5", 0, 3500, 3500);
+ break;
+ case GTA01v3_SYSTEM_REV:
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D1REG],
+ "vrf_3v", 0, 3000, 3000);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D2REG],
+ "sd_3v3", 0, 3300, 3300);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_D3REG],
+ "codec_3v3", 0, 3300, 3300);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCD],
+ "gpsio_3v3", 0, 3300, 3300);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_DCUD],
+ "core_1v8", PMU_VRAIL_F_SUSPEND_ON, 1800, 1800);
+ cfg_pmu_vrail(&gta01_pcf_pdata.rails[PCF50606_REGULATOR_IOREG],
+ "vtcxo_2v8", 0, 2800, 2800);
+ break;
+ }
+}
+
+static struct resource gta01_pmu_resources[] = {
+ [0] = {
+ .flags = IORESOURCE_IRQ,
+ .start = GTA01_IRQ_PCF50606,
+ .end = GTA01_IRQ_PCF50606,
+ },
+};
+
+struct platform_device gta01_pmu_dev = {
+ .name = "pcf50606",
+ .num_resources = ARRAY_SIZE(gta01_pmu_resources),
+ .resource = gta01_pmu_resources,
+ .dev = {
+ .platform_data = &gta01_pcf_pdata,
+ },
+};
+
+/* LCD driver info */
+
+/* Configuration for 480x640 toppoly TD028TTEC1.
+ * Do not mark this as __initdata or it will break! */
+static struct s3c2410fb_display gta01_displays[] = {
+ {
+ .type = S3C2410_LCDCON1_TFT,
+ .width = 43,
+ .height = 58,
+ .xres = 480,
+ .yres = 640,
+ .bpp = 16,
+
+ .pixclock = 40000, /* HCLK/4 */
+ .left_margin = 104,
+ .right_margin = 8,
+ .hsync_len = 8,
+ .upper_margin = 2,
+ .lower_margin = 16,
+ .vsync_len = 2,
+ .lcdcon5 = S3C2410_LCDCON5_FRM565 |
+ S3C2410_LCDCON5_INVVCLK |
+ S3C2410_LCDCON5_INVVLINE |
+ S3C2410_LCDCON5_INVVFRAME |
+ S3C2410_LCDCON5_PWREN |
+ S3C2410_LCDCON5_HWSWP,
+ },
+ {
+ .type = S3C2410_LCDCON1_TFT,
+ .width = 43,
+ .height = 58,
+ .xres = 480,
+ .yres = 640,
+ .bpp = 32,
+
+ .pixclock = 40000, /* HCLK/4 */
+ .left_margin = 104,
+ .right_margin = 8,
+ .hsync_len = 8,
+ .upper_margin = 2,
+ .lower_margin = 16,
+ .vsync_len = 2,
+ .lcdcon5 = S3C2410_LCDCON5_FRM565 |
+ S3C2410_LCDCON5_INVVCLK |
+ S3C2410_LCDCON5_INVVLINE |
+ S3C2410_LCDCON5_INVVFRAME |
+ S3C2410_LCDCON5_PWREN |
+ S3C2410_LCDCON5_HWSWP,
+ },
+ {
+ .type = S3C2410_LCDCON1_TFT,
+ .width = 43,
+ .height = 58,
+ .xres = 240,
+ .yres = 320,
+ .bpp = 16,
+
+ .pixclock = 40000, /* HCLK/4 */
+ .left_margin = 104,
+ .right_margin = 8,
+ .hsync_len = 8,
+ .upper_margin = 2,
+ .lower_margin = 16,
+ .vsync_len = 2,
+ .lcdcon5 = S3C2410_LCDCON5_FRM565 |
+ S3C2410_LCDCON5_INVVCLK |
+ S3C2410_LCDCON5_INVVLINE |
+ S3C2410_LCDCON5_INVVFRAME |
+ S3C2410_LCDCON5_PWREN |
+ S3C2410_LCDCON5_HWSWP,
+ },
+};
+
+static struct s3c2410fb_mach_info gta01_lcd_cfg __initdata = {
+ .displays = gta01_displays,
+ .num_displays = ARRAY_SIZE(gta01_displays),
+ .default_display = 0,
+
+ .lpcsel = ((0xCE6) & ~7) | 1<<4,
+};
+
+static struct platform_device *gta01_devices[] __initdata = {
+ &s3c_device_usb,
+ &s3c_device_lcd,
+ &s3c_device_wdt,
+ &s3c_device_i2c0,
+ &s3c_device_iis,
+ &s3c_device_sdi,
+ &s3c_device_usbgadget,
+ &s3c_device_nand,
+ &s3c_device_ts,
+};
+
+static struct s3c2410_nand_set gta01_nand_sets[] = {
+ [0] = {
+ .name = "neo1973-nand",
+ .nr_chips = 1,
+ .flags = S3C2410_NAND_BBT,
+ },
+};
+
+static struct s3c2410_platform_nand gta01_nand_info = {
+ .tacls = 20,
+ .twrph0 = 60,
+ .twrph1 = 20,
+ .nr_sets = ARRAY_SIZE(gta01_nand_sets),
+ .sets = gta01_nand_sets,
+};
+
+static void gta01_mmc_set_power(unsigned char power_mode, unsigned short vdd)
+{
+ int bit;
+ int mv = 1700; /* 1.7V for MMC_VDD_165_195 */
+
+ printk(KERN_DEBUG "mmc_set_power(power_mode=%u, vdd=%u)\n",
+ power_mode, vdd);
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ switch (power_mode) {
+ case MMC_POWER_OFF:
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D2REG, 0);
+ break;
+ case MMC_POWER_ON:
+ /* translate MMC_VDD_* VDD bit to mv */
+ for (bit = 8; bit != 24; bit++)
+ if (vdd == (1 << bit))
+ mv += 100 * (bit - 4);
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_D2REG, mv);
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D2REG, 1);
+ break;
+ }
+ break;
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ switch (power_mode) {
+ case MMC_POWER_OFF:
+ neo1973_gpb_setpin(GTA01_GPIO_SDMMC_ON, 1);
+ break;
+ case MMC_POWER_ON:
+ neo1973_gpb_setpin(GTA01_GPIO_SDMMC_ON, 0);
+ break;
+ }
+ break;
+ }
+}
+
+static struct s3c24xx_mci_pdata gta01_mmc_cfg = {
+ .gpio_detect = GTA01_GPIO_nSD_DETECT,
+ .set_power = &gta01_mmc_set_power,
+ .ocr_avail = MMC_VDD_165_195|MMC_VDD_20_21|
+ MMC_VDD_21_22|MMC_VDD_22_23|MMC_VDD_23_24|
+ MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
+ MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
+ MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33,
+};
+
+static void gta01_udc_command(enum s3c2410_udc_cmd_e cmd)
+{
+ printk(KERN_DEBUG "%s(%d)\n", __func__, cmd);
+
+ switch (cmd) {
+ case S3C2410_UDC_P_ENABLE:
+ neo1973_gpb_setpin(GTA01_GPIO_USB_PULLUP, 1);
+ break;
+ case S3C2410_UDC_P_DISABLE:
+ neo1973_gpb_setpin(GTA01_GPIO_USB_PULLUP, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+/* use a work queue, since I2C API inherently schedules
+ * and we get called in hardirq context from UDC driver */
+
+struct vbus_draw {
+ struct work_struct work;
+ int ma;
+};
+static struct vbus_draw gta01_udc_vbus_drawer;
+
+static void __gta01_udc_vbus_draw(struct work_struct *work)
+{
+ /* this is a fix to work around boot-time ordering problems if the
+ * s3c2410_udc is initialized before the pcf50606 driver has defined
+ * pcf50606_global */
+ if (!pcf50606_global)
+ return;
+
+ if (gta01_udc_vbus_drawer.ma >= 500) {
+ /* enable fast charge */
+ printk(KERN_DEBUG "udc: enabling fast charge\n");
+ pcf50606_charge_fast(pcf50606_global, 1);
+ } else {
+ /* disable fast charge */
+ printk(KERN_DEBUG "udc: disabling fast charge\n");
+ pcf50606_charge_fast(pcf50606_global, 0);
+ }
+}
+
+static void gta01_udc_vbus_draw(unsigned int ma)
+{
+ gta01_udc_vbus_drawer.ma = ma;
+ schedule_work(&gta01_udc_vbus_drawer.work);
+}
+
+static struct s3c2410_udc_mach_info gta01_udc_cfg = {
+ .vbus_draw = gta01_udc_vbus_draw,
+};
+
+
+/* touchscreen configuration */
+
+static struct ts_filter_median_configuration gta01_ts_median_config = {
+ .extent = 31,
+ .decimation_below = 24,
+ .decimation_threshold = 8 * 3,
+ .decimation_above = 12,
+};
+
+static struct ts_filter_mean_configuration gta01_ts_mean_config = {
+ .bits_filter_length = 5,
+ .averaging_threshold = 12
+};
+
+static struct s3c2410_ts_mach_info gta01_ts_cfg = {
+ .delay = 10000,
+ .presc = 0xff, /* slow as we can go */
+ .filter_sequence = {
+ [0] = &ts_filter_median_api,
+ [1] = &ts_filter_mean_api,
+ },
+ .filter_config = {
+ [0] = &gta01_ts_median_config,
+ [1] = &gta01_ts_mean_config,
+ },
+};
+
+
+/* SPI */
+
+static void gta01_jbt6k74_reset(int devidx, int level)
+{
+ /* empty place holder; gta01 does not yet use this */
+ printk(KERN_DEBUG "gta01_jbt6k74_reset\n");
+}
+
+static void gta01_jbt6k74_resuming(int devidx)
+{
+ gta01bl_deferred_resume();
+}
+
+const struct jbt6k74_platform_data gta01_jbt6k74_pdata = {
+ .reset = gta01_jbt6k74_reset,
+ .resuming = gta01_jbt6k74_resuming,
+};
+
+static struct spi_board_info gta01_spi_board_info[] = {
+ {
+ .modalias = "jbt6k74",
+ .platform_data = &gta01_jbt6k74_pdata,
+ /* controller_data */
+ /* irq */
+ .max_speed_hz = 10 * 1000 * 1000,
+ .bus_num = 1,
+ /* chip_select */
+ },
+};
+
+static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int csidx, int cs)
+{
+ switch (cs) {
+ case BITBANG_CS_ACTIVE:
+ s3c2410_gpio_setpin(S3C2410_GPG3, 0);
+ break;
+ case BITBANG_CS_INACTIVE:
+ s3c2410_gpio_setpin(S3C2410_GPG3, 1);
+ break;
+ }
+}
+
+static struct s3c2410_spigpio_info spi_gpio_cfg = {
+ .pin_clk = S3C2410_GPG7,
+ .pin_mosi = S3C2410_GPG6,
+ .pin_miso = S3C2410_GPG5,
+ .board_size = ARRAY_SIZE(gta01_spi_board_info),
+ .board_info = gta01_spi_board_info,
+ .chip_select = &spi_gpio_cs,
+ .num_chipselect = 2, /*** Should be 1 or 2 for gta01? ***/
+};
+
+static struct resource s3c_spi_lcm_resource[] = {
+ [0] = {
+ .start = S3C2410_GPG3,
+ .end = S3C2410_GPG3,
+ },
+ [1] = {
+ .start = S3C2410_GPG5,
+ .end = S3C2410_GPG5,
+ },
+ [2] = {
+ .start = S3C2410_GPG6,
+ .end = S3C2410_GPG6,
+ },
+ [3] = {
+ .start = S3C2410_GPG7,
+ .end = S3C2410_GPG7,
+ },
+};
+
+struct platform_device s3c_device_spi_lcm = {
+ .name = "spi_s3c24xx_gpio",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_spi_lcm_resource),
+ .resource = s3c_spi_lcm_resource,
+ .dev = {
+ .platform_data = &spi_gpio_cfg,
+ },
+};
+
+static struct gta01bl_machinfo backlight_machinfo = {
+ .default_intensity = 1,
+ .max_intensity = 1,
+ .limit_mask = 1,
+ .defer_resume_backlight = 1,
+};
+
+static struct resource gta01_bl_resources[] = {
+ [0] = {
+ .start = GTA01_GPIO_BACKLIGHT,
+ .end = GTA01_GPIO_BACKLIGHT,
+ },
+};
+
+struct platform_device gta01_bl_dev = {
+ .name = "gta01-bl",
+ .num_resources = ARRAY_SIZE(gta01_bl_resources),
+ .resource = gta01_bl_resources,
+ .dev = {
+ .platform_data = &backlight_machinfo,
+ },
+};
+
+static struct resource gta01_led_resources[] = {
+ [0] = {
+ .start = GTA01_GPIO_VIBRATOR_ON,
+ .end = GTA01_GPIO_VIBRATOR_ON,
+ },
+};
+
+struct platform_device gta01_led_dev = {
+ .name = "neo1973-vibrator",
+ .num_resources = ARRAY_SIZE(gta01_led_resources),
+ .resource = gta01_led_resources,
+};
+
+static struct resource gta01_button_resources[] = {
+ [0] = {
+ .start = GTA01_GPIO_AUX_KEY,
+ .end = GTA01_GPIO_AUX_KEY,
+ },
+ [1] = {
+ .start = GTA01_GPIO_HOLD_KEY,
+ .end = GTA01_GPIO_HOLD_KEY,
+ },
+ [2] = {
+ .start = GTA01_GPIO_JACK_INSERT,
+ .end = GTA01_GPIO_JACK_INSERT,
+ },
+ [3] = {
+ .start = 0,
+ .end = 0,
+ },
+ [4] = {
+ .start = 0,
+ .end = 0,
+ },
+};
+
+struct platform_device gta01_button_dev = {
+ .name = "neo1973-button",
+ .num_resources = ARRAY_SIZE(gta01_button_resources),
+ .resource = gta01_button_resources,
+};
+
+static struct platform_device gta01_pm_gsm_dev = {
+ .name = "neo1973-pm-gsm",
+};
+
+/* USB */
+static struct s3c2410_hcd_info gta01_usb_info = {
+ .port[0] = {
+ .flags = S3C_HCDFLG_USED,
+ },
+ .port[1] = {
+ .flags = 0,
+ },
+};
+
+static void __init gta01_map_io(void)
+{
+ s3c24xx_init_io(gta01_iodesc, ARRAY_SIZE(gta01_iodesc));
+ s3c24xx_init_clocks(12*1000*1000);
+ s3c24xx_init_uarts(gta01_uartcfgs, ARRAY_SIZE(gta01_uartcfgs));
+}
+
+static irqreturn_t gta01_modem_irq(int irq, void *param)
+{
+ printk(KERN_DEBUG "GSM wakeup interrupt (IRQ %d)\n", irq);
+ gta_gsm_interrupts++;
+ return IRQ_HANDLED;
+}
+
+static void __init gta01_machine_init(void)
+{
+ int rc;
+
+ if (system_rev == GTA01v4_SYSTEM_REV ||
+ system_rev == GTA01Bv2_SYSTEM_REV ||
+ system_rev == GTA01Bv3_SYSTEM_REV ||
+ system_rev == GTA01Bv4_SYSTEM_REV) {
+ gta01_udc_cfg.udc_command = gta01_udc_command;
+ gta01_mmc_cfg.ocr_avail = MMC_VDD_32_33;
+ }
+
+ s3c_device_usb.dev.platform_data = &gta01_usb_info;
+ s3c_device_nand.dev.platform_data = &gta01_nand_info;
+ s3c_device_sdi.dev.platform_data = &gta01_mmc_cfg;
+
+ s3c24xx_fb_set_platdata(&gta01_lcd_cfg);
+
+ INIT_WORK(&gta01_udc_vbus_drawer.work, __gta01_udc_vbus_draw);
+ s3c24xx_udc_set_platdata(&gta01_udc_cfg);
+ s3c_i2c0_set_platdata(NULL);
+ set_s3c2410ts_info(&gta01_ts_cfg);
+
+ /* Set LCD_RESET / XRES to high */
+ s3c2410_gpio_cfgpin(S3C2410_GPC6, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_setpin(S3C2410_GPC6, 1);
+
+ /* SPI chip select is gpio output */
+ s3c2410_gpio_cfgpin(S3C2410_GPG3, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_setpin(S3C2410_GPG3, 1);
+ platform_device_register(&s3c_device_spi_lcm);
+
+ platform_device_register(&gta01_bl_dev);
+ platform_device_register(&gta01_button_dev);
+ platform_device_register(&gta01_pm_gsm_dev);
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ /* just use the default (GTA01_IRQ_PCF50606) */
+ break;
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ /* just use the default (GTA01_IRQ_PCF50606) */
+ gta01_led_resources[0].start =
+ gta01_led_resources[0].end = GTA01Bv2_GPIO_VIBRATOR_ON;
+ break;
+ case GTA01Bv4_SYSTEM_REV:
+ gta01_pmu_resources[0].start =
+ gta01_pmu_resources[0].end = GTA01Bv4_IRQ_PCF50606;
+ gta01_led_resources[0].start =
+ gta01_led_resources[0].end = GTA01Bv4_GPIO_VIBRATOR_ON;
+ break;
+ }
+ mangle_pmu_pdata_by_system_rev();
+ platform_device_register(&gta01_pmu_dev);
+ platform_device_register(&gta01_led_dev);
+
+ platform_add_devices(gta01_devices, ARRAY_SIZE(gta01_devices));
+
+ s3c2410_pm_init();
+
+ set_irq_type(GTA01_IRQ_MODEM, IRQ_TYPE_EDGE_RISING);
+ rc = request_irq(GTA01_IRQ_MODEM, gta01_modem_irq, IRQF_DISABLED,
+ "modem", NULL);
+ enable_irq_wake(GTA01_IRQ_MODEM);
+ printk(KERN_DEBUG "Enabled GSM wakeup IRQ %d (rc=%d)\n",
+ GTA01_IRQ_MODEM, rc);
+}
+
+MACHINE_START(NEO1973_GTA01, "GTA01")
+ .phys_io = S3C2410_PA_UART,
+ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+ .boot_params = S3C2410_SDRAM_PA + 0x100,
+ .map_io = gta01_map_io,
+ .init_irq = s3c24xx_init_irq,
+ .init_machine = gta01_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -38,11 +38,13 @@
#include <mach/h1940.h>
#include <mach/h1940-latch.h>
#include <mach/fb.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
+#include <plat/iic.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
+#include <plat/pll.h>
#include <plat/pm.h>
static struct map_desc h1940_iodesc[] __initdata = {
@@ -129,6 +131,11 @@
.vbus_pin_inverted = 1,
};
+static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
+ .delay = 10000,
+ .presc = 49,
+ .oversampling_shift = 2,
+};
/**
* Set lcd on or off
@@ -183,9 +190,10 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
+ &s3c_device_ts,
&s3c_device_leds,
&s3c_device_bluetooth,
};
@@ -201,7 +209,7 @@
#ifdef CONFIG_PM_H1940
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
- s3c2410_pm_init();
+ s3c_pm_init();
}
static void __init h1940_init_irq(void)
@@ -214,7 +222,9 @@
u32 tmp;
s3c24xx_fb_set_platdata(&h1940_fb_info);
+ set_s3c2410ts_info(&h1940_ts_cfg);
s3c24xx_udc_set_platdata(&h1940_udc_cfg);
+ s3c_i2c0_set_platdata(NULL);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
@@ -223,10 +233,9 @@
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
- tmp = (
- 0x78 << S3C2410_PLLCON_MDIVSHIFT)
- | (0x02 << S3C2410_PLLCON_PDIVSHIFT)
- | (0x03 << S3C2410_PLLCON_SDIVSHIFT);
+ tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
+ | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
+ | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
writel(tmp, S3C2410_UPLLCON);
platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -40,14 +40,14 @@
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/iic.h>
#include <plat/regs-serial.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/s3c2410.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
static struct map_desc n30_iodesc[] __initdata = {
/* nothing here yet */
@@ -320,7 +320,7 @@
static struct platform_device *n30_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usb,
&s3c_device_usbgadget,
@@ -332,7 +332,7 @@
static struct platform_device *n35_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&n35_button_device,
@@ -501,7 +501,7 @@
static void __init n30_init(void)
{
s3c24xx_fb_set_platdata(&n30_fb_info);
- s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
+ s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
s3c24xx_udc_set_platdata(&n30_udc_cfg);
/* Turn off suspend on both USB ports, and switch the
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -35,6 +35,7 @@
#include <plat/s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
+#include <plat/iic.h>
#include <plat/cpu.h>
static struct map_desc otom11_iodesc[] __initdata = {
@@ -94,7 +95,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&otom_device_nor,
@@ -109,6 +110,7 @@
static void __init otom11_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
}
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
*
- * Copyright (C) 2006 by OpenMoko, Inc.
+ * Copyright (C) 2006 by Openmoko, Inc.
* Author: Harald Welte <laforge@openmoko.org>
* All rights reserved.
*
@@ -50,10 +50,11 @@
#include <mach/leds-gpio.h>
#include <plat/regs-serial.h>
#include <mach/fb.h>
-#include <asm/plat-s3c/nand.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/nand.h>
+#include <plat/udc.h>
#include <mach/spi.h>
#include <mach/spi-gpio.h>
+#include <plat/iic.h>
#include <plat/common-smdk.h>
#include <plat/devs.h>
@@ -213,7 +214,7 @@
/* SPI */
-static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
+static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int csidx, int cs)
{
switch (cs) {
case BITBANG_CS_ACTIVE:
@@ -247,7 +248,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_sdi,
&s3c_device_usbgadget,
@@ -320,6 +321,24 @@
__setup("tft=", qt2410_tft_setup);
+static struct resource qt2410_button_resources[] = {
+ [0] = {
+ .start = S3C2410_GPF0,
+ .end = S3C2410_GPF0,
+ },
+ [1] = {
+ .start = S3C2410_GPF2,
+ .end = S3C2410_GPF2,
+ },
+};
+
+struct platform_device qt2410_button_dev = {
+ .name ="qt2410-button",
+ .num_resources = ARRAY_SIZE(qt2410_button_resources),
+ .resource = qt2410_button_resources,
+};
+
+
static void __init qt2410_map_io(void)
{
s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
@@ -349,11 +368,12 @@
s3c2410_gpio_setpin(S3C2410_GPB0, 1);
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
+ s3c_i2c0_set_platdata(NULL);
s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
- s3c2410_pm_init();
+ s3c_pm_init();
}
MACHINE_START(QT2410, "QT2410")
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -47,6 +47,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
+#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@@ -89,7 +90,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
};
@@ -102,6 +103,7 @@
static void __init smdk2410_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
smdk_machine_init();
}
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -45,6 +45,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
+#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@@ -127,7 +128,7 @@
static struct platform_device *tct_hammer_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
@@ -146,6 +147,7 @@
static void __init tct_hammer_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
}
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -47,6 +47,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
+#include <plat/iic.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
@@ -334,7 +335,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_adc,
&serial_device,
&vr1000_dm9k0,
@@ -384,6 +385,7 @@
static void __init vr1000_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
i2c_register_board_info(0, vr1000_i2c_devs,
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -15,7 +15,8 @@
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
obj-$(CONFIG_S3C2410_GPIO) += gpio.o
-obj-$(CONFIG_S3C2410_CLOCK) += clock.o
+#obj-$(CONFIG_S3C2410_CLOCK) += clock.o
+obj-$(CONFIG_S3C2410_PWM) += pwm.o
# Machine support
@@ -38,3 +39,5 @@
# machine additions
obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o
+obj-$(CONFIG_MACH_NEO1973_GTA01)+= mach-gta01.o
+
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -37,21 +37,14 @@
#include <plat/cpu.h>
#include <plat/pm.h>
-#ifdef CONFIG_S3C2410_PM_DEBUG
-extern void pm_dbg(const char *fmt, ...);
-#define DBG(fmt...) pm_dbg(fmt)
-#else
-#define DBG(fmt...) printk(KERN_DEBUG fmt)
-#endif
-
static void s3c2410_pm_prepare(void)
{
/* ensure at least GSTATUS3 has the resume address */
- __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3);
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
- DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
- DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
+ S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
+ S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
if (machine_is_h1940()) {
void *base = phys_to_virt(H1940_SUSPEND_CHECK);
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pwm.c
@@ -0,0 +1,288 @@
+/*
+ * arch/arm/mach-s3c2410/3c2410-pwm.c
+ *
+ * Copyright (c) by Javi Roman <javiroman@kernel-labs.org>
+ * for the Openmoko Project.
+ *
+ * S3C2410A SoC PWM support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <mach/hardware.h>
+#include <plat/regs-timer.h>
+#include <mach/pwm.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_PM
+ static unsigned long standby_reg_tcon;
+ static unsigned long standby_reg_tcfg0;
+ static unsigned long standby_reg_tcfg1;
+#endif
+
+int s3c2410_pwm_disable(struct s3c2410_pwm *pwm)
+{
+ unsigned long tcon;
+
+ /* stop timer */
+ tcon = __raw_readl(S3C2410_TCON);
+ tcon &= 0xffffff00;
+ __raw_writel(tcon, S3C2410_TCON);
+
+ clk_disable(pwm->pclk);
+ clk_put(pwm->pclk);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_disable);
+
+int s3c2410_pwm_init(struct s3c2410_pwm *pwm)
+{
+ pwm->pclk = clk_get(NULL, "timers");
+ if (IS_ERR(pwm->pclk))
+ return PTR_ERR(pwm->pclk);
+
+ clk_enable(pwm->pclk);
+ pwm->pclk_rate = clk_get_rate(pwm->pclk);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_init);
+
+int s3c2410_pwm_enable(struct s3c2410_pwm *pwm)
+{
+ unsigned long tcfg0, tcfg1, tcnt, tcmp;
+
+ /* control registers bits */
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
+ tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+ /* divider & scaler slection */
+ switch (pwm->timerid) {
+ case PWM0:
+ tcfg1 &= ~S3C2410_TCFG1_MUX0_MASK;
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
+ break;
+ case PWM1:
+ tcfg1 &= ~S3C2410_TCFG1_MUX1_MASK;
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
+ break;
+ case PWM2:
+ tcfg1 &= ~S3C2410_TCFG1_MUX2_MASK;
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+ break;
+ case PWM3:
+ tcfg1 &= ~S3C2410_TCFG1_MUX3_MASK;
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+ break;
+ case PWM4:
+ /* timer four is not capable of doing PWM */
+ break;
+ default:
+ clk_disable(pwm->pclk);
+ clk_put(pwm->pclk);
+ return -1;
+ }
+
+ /* divider & scaler values */
+ tcfg1 |= pwm->divider;
+ __raw_writel(tcfg1, S3C2410_TCFG1);
+
+ switch (pwm->timerid) {
+ case PWM0:
+ case PWM1:
+ tcfg0 |= pwm->prescaler;
+ __raw_writel(tcfg0, S3C2410_TCFG0);
+ break;
+ default:
+ if ((tcfg0 | pwm->prescaler) != tcfg0) {
+ printk(KERN_WARNING "not changing prescaler of PWM %u,"
+ " since it's shared with timer4 (clock tick)\n",
+ pwm->timerid);
+ }
+ break;
+ }
+
+ /* timer count and compare buffer initial values */
+ tcnt = pwm->counter;
+ tcmp = pwm->comparer;
+
+ __raw_writel(tcnt, S3C2410_TCNTB(pwm->timerid));
+ __raw_writel(tcmp, S3C2410_TCMPB(pwm->timerid));
+
+ /* ensure timer is stopped */
+ s3c2410_pwm_stop(pwm);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_enable);
+
+int s3c2410_pwm_start(struct s3c2410_pwm *pwm)
+{
+ unsigned long tcon;
+
+ tcon = __raw_readl(S3C2410_TCON);
+
+ switch (pwm->timerid) {
+ case PWM0:
+ tcon |= S3C2410_TCON_T0START;
+ tcon &= ~S3C2410_TCON_T0MANUALUPD;
+ break;
+ case PWM1:
+ tcon |= S3C2410_TCON_T1START;
+ tcon &= ~S3C2410_TCON_T1MANUALUPD;
+ break;
+ case PWM2:
+ tcon |= S3C2410_TCON_T2START;
+ tcon &= ~S3C2410_TCON_T2MANUALUPD;
+ break;
+ case PWM3:
+ tcon |= S3C2410_TCON_T3START;
+ tcon &= ~S3C2410_TCON_T3MANUALUPD;
+ break;
+ case PWM4:
+ /* timer four is not capable of doing PWM */
+ default:
+ return -ENODEV;
+ }
+
+ __raw_writel(tcon, S3C2410_TCON);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_start);
+
+int s3c2410_pwm_stop(struct s3c2410_pwm *pwm)
+{
+ unsigned long tcon;
+
+ tcon = __raw_readl(S3C2410_TCON);
+
+ switch (pwm->timerid) {
+ case PWM0:
+ tcon &= ~0x00000000;
+ tcon |= S3C2410_TCON_T0RELOAD;
+ tcon |= S3C2410_TCON_T0MANUALUPD;
+ break;
+ case PWM1:
+ tcon &= ~0x00000080;
+ tcon |= S3C2410_TCON_T1RELOAD;
+ tcon |= S3C2410_TCON_T1MANUALUPD;
+ break;
+ case PWM2:
+ tcon &= ~0x00000800;
+ tcon |= S3C2410_TCON_T2RELOAD;
+ tcon |= S3C2410_TCON_T2MANUALUPD;
+ break;
+ case PWM3:
+ tcon &= ~0x00008000;
+ tcon |= S3C2410_TCON_T3RELOAD;
+ tcon |= S3C2410_TCON_T3MANUALUPD;
+ break;
+ case PWM4:
+ /* timer four is not capable of doing PWM */
+ default:
+ return -ENODEV;
+ }
+
+ __raw_writel(tcon, S3C2410_TCON);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_stop);
+
+int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *pwm)
+{
+ __raw_writel(reg_value, S3C2410_TCMPB(pwm->timerid));
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_duty_cycle);
+
+int s3c2410_pwm_dumpregs(void)
+{
+ printk(KERN_INFO "TCON: %08lx, TCFG0: %08lx, TCFG1: %08lx\n",
+ (unsigned long) __raw_readl(S3C2410_TCON),
+ (unsigned long) __raw_readl(S3C2410_TCFG0),
+ (unsigned long) __raw_readl(S3C2410_TCFG1));
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(s3c2410_pwm_dumpregs);
+
+static int __init s3c24xx_pwm_probe(struct platform_device *pdev)
+{
+ struct s3c24xx_pwm_platform_data *pdata = pdev->dev.platform_data;
+
+ dev_info(&pdev->dev, "s3c24xx_pwm is registered \n");
+
+ /* if platform was interested, give him a chance to register
+ * platform devices that switch power with us as the parent
+ * at registration time -- ensures suspend / resume ordering
+ */
+ if (pdata)
+ if (pdata->attach_child_devices)
+ (pdata->attach_child_devices)(&pdev->dev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c24xx_pwm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ /* PWM config should be kept in suspending */
+ standby_reg_tcon = __raw_readl(S3C2410_TCON);
+ standby_reg_tcfg0 = __raw_readl(S3C2410_TCFG0);
+ standby_reg_tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+ return 0;
+}
+
+static int s3c24xx_pwm_resume(struct platform_device *pdev)
+{
+ __raw_writel(standby_reg_tcon, S3C2410_TCON);
+ __raw_writel(standby_reg_tcfg0, S3C2410_TCFG0);
+ __raw_writel(standby_reg_tcfg1, S3C2410_TCFG1);
+
+ return 0;
+}
+#else
+#define sc32440_pwm_suspend NULL
+#define sc32440_pwm_resume NULL
+#endif
+
+static struct platform_driver s3c24xx_pwm_driver = {
+ .driver = {
+ .name = "s3c24xx_pwm",
+ .owner = THIS_MODULE,
+ },
+ .probe = s3c24xx_pwm_probe,
+ .suspend = s3c24xx_pwm_suspend,
+ .resume = s3c24xx_pwm_resume,
+};
+
+static int __init s3c24xx_pwm_init(void)
+{
+ return platform_driver_register(&s3c24xx_pwm_driver);
+}
+
+static void __exit s3c24xx_pwm_exit(void)
+{
+}
+
+MODULE_AUTHOR("Javi Roman <javiroman@kernel-labs.org>");
+MODULE_LICENSE("GPL");
+
+module_init(s3c24xx_pwm_init);
+module_exit(s3c24xx_pwm_exit);
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
+#include <linux/clk.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
@@ -28,6 +29,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
+#include <plat/cpu-freq.h>
+
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
@@ -35,6 +38,7 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
+#include <plat/pll.h>
/* Initial IO mappings */
@@ -59,25 +63,28 @@
* machine specific initialisation.
*/
-void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size)
+void __init s3c2410_map_io(void)
{
- /* register our io-tables */
-
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
- iotable_init(mach_desc, mach_size);
}
-void __init s3c2410_init_clocks(int xtal)
+void __init_or_cpufreq s3c2410_setup_clocks(void)
{
+ struct clk *xtal_clk;
unsigned long tmp;
+ unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
+ xtal_clk = clk_get(NULL, "xtal");
+ xtal = clk_get_rate(xtal_clk);
+ clk_put(xtal_clk);
+
/* now we've got our machine bits initialised, work out what
* clocks we've got */
- fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
+ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
tmp = __raw_readl(S3C2410_CLKDIVN);
@@ -95,7 +102,13 @@
* console to use them
*/
- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
+ s3c24xx_setup_clocks(fclk, hclk, pclk);
+}
+
+void __init s3c2410_init_clocks(int xtal)
+{
+ s3c24xx_register_baseclocks(xtal);
+ s3c2410_setup_clocks();
s3c2410_baseclk_add();
}
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -93,12 +93,6 @@
/* clock selections */
-/* CPU EXTCLK input */
-static struct clk clk_ext = {
- .name = "extclk",
- .id = -1,
-};
-
static struct clk clk_erefclk = {
.name = "erefclk",
.id = -1,
@@ -773,5 +767,6 @@
s3c2412_clkcon_enable(clkp, 0);
}
+ s3c_pwmclk_init();
return 0;
}
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -26,13 +26,13 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <asm/plat-s3c24xx/regs-s3c2412-iis.h>
#include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -31,8 +31,8 @@
#include <asm/mach/irq.h>
#include <plat/regs-serial.h>
-#include <asm/plat-s3c/nand.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
#include <mach/regs-power.h>
#include <mach/regs-gpio.h>
@@ -52,7 +52,8 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
+#include <plat/iic.h>
static struct map_desc jive_iodesc[] __initdata = {
};
@@ -450,14 +451,14 @@
/* I2C bus and device configuration. */
-static struct s3c2410_platform_i2c jive_i2c_cfg = {
+static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
.max_freq = 80 * 1000,
.bus_freq = 50 * 1000,
.flags = S3C_IICFLG_FILTER,
.sda_delay = 2,
};
-static struct i2c_board_info jive_i2c_devs[] = {
+static struct i2c_board_info jive_i2c_devs[] __initdata = {
[0] = {
I2C_BOARD_INFO("lis302dl", 0x1c),
.irq = IRQ_EINT14,
@@ -470,7 +471,7 @@
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_lcd,
&jive_device_lcdspi,
&jive_device_wm8750,
@@ -492,7 +493,7 @@
* correct address to resume from. */
__raw_writel(0x2BED, S3C2412_INFORM0);
- __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
return 0;
}
@@ -628,7 +629,7 @@
/* initialise the power management now we've setup everything. */
- s3c2410_pm_init();
+ s3c_pm_init();
s3c_device_nand.dev.platform_data = &jive_nand_info;
@@ -663,7 +664,7 @@
spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
- s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
+ s3c_i2c0_set_platdata(&jive_i2c_cfg);
i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
pm_power_off = jive_power_off;
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -37,7 +37,8 @@
#include <mach/regs-lcd.h>
#include <mach/idle.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
+#include <plat/iic.h>
#include <mach/fb.h>
#include <plat/s3c2410.h>
@@ -105,7 +106,7 @@
&s3c_device_usb,
//&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
};
@@ -142,6 +143,7 @@
s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
smdk_machine_init();
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -39,7 +39,8 @@
#include <mach/idle.h>
#include <mach/fb.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/iic.h>
+#include <plat/nand.h>
#include <plat/s3c2410.h>
#include <plat/s3c2412.h>
@@ -122,7 +123,7 @@
static struct platform_device *vstms_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_nand,
@@ -151,6 +152,7 @@
static void __init vstms_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
}
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -85,7 +85,7 @@
static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state)
{
- s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+ s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
return 0;
}
@@ -98,7 +98,7 @@
tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
__raw_writel(tmp, S3C2412_PWRCFG);
- s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
+ s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep));
return 0;
}
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
@@ -33,13 +34,15 @@
#include <mach/reset.h>
#include <mach/idle.h>
+#include <plat/cpu-freq.h>
+
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-power.h>
#include <mach/regs-gpio.h>
#include <mach/regs-gpioj.h>
#include <mach/regs-dsc.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
#include <mach/regs-s3c2412.h>
#include <plat/s3c2412.h>
@@ -47,6 +50,7 @@
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/pm.h>
+#include <plat/pll.h>
#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -136,7 +140,7 @@
* machine specific initialisation.
*/
-void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size)
+void __init s3c2412_map_io(void)
{
/* move base of IO */
@@ -153,20 +157,25 @@
/* register our io-tables */
iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
- iotable_init(mach_desc, mach_size);
}
-void __init s3c2412_init_clocks(int xtal)
+void __init_or_cpufreq s3c2412_setup_clocks(void)
{
+ struct clk *xtal_clk;
unsigned long tmp;
+ unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
+ xtal_clk = clk_get(NULL, "xtal");
+ xtal = clk_get_rate(xtal_clk);
+ clk_put(xtal_clk);
+
/* now we've got our machine bits initialised, work out what
* clocks we've got */
- fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2);
+ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
clk_mpll.rate = fclk;
@@ -183,11 +192,17 @@
printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
+ s3c24xx_setup_clocks(fclk, hclk, pclk);
+}
+
+void __init s3c2412_init_clocks(int xtal)
+{
/* initialise the clocks here, to allow other things like the
* console to use them
*/
- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
+ s3c24xx_register_baseclocks(xtal);
+ s3c2412_setup_clocks();
s3c2412_baseclk_add();
}
@@ -216,5 +231,8 @@
{
printk("S3C2412: Initialising architecture\n");
+ /* make sure SD/MMC driver can distinguish 2412 from 2410 */
+ s3c_device_sdi.name = "s3c2412-sdi";
+
return sysdev_register(&s3c2412_sysdev);
}
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/bits.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) Samsung Electroincs 2003
+ * Author: SW.LEE <hitchcar@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __SW_BITS_H
+#define __SW_BITS_H
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+#endif
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/camif.c
@@ -0,0 +1,1047 @@
+/*
+ * Copyright (C) 2004 Samsung Electronics
+ * SW.LEE <hitchcar@samsung.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/miscdevice.h>
+#include <linux/wait.h>
+#include <linux/miscdevice.h>
+#include <asm/io.h>
+#include <asm/semaphore.h>
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#ifdef CONFIG_ARCH_S3C24A0A
+#include <asm/arch/S3C24A0.h>
+#include <asm/arch/clocks.h>
+#else
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-gpioj.h>
+#include <asm/arch/regs-irq.h>
+#endif
+
+#include "cam_reg.h"
+//#define SW_DEBUG
+#define CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#include "camif.h"
+#include "miscdevice.h"
+
+static int camif_dma_burst(camif_cfg_t *);
+static int camif_scaler(camif_cfg_t *);
+
+/* For SXGA Image */
+#define RESERVE_MEM 15*1024*1024
+#define YUV_MEM 10*1024*1024
+#define RGB_MEM (RESERVE_MEM - YUV_MEM)
+
+static int camif_malloc(camif_cfg_t *cfg)
+{
+ unsigned int t_size;
+ unsigned int daon = cfg->target_x *cfg->target_y;
+
+ if(cfg->dma_type & CAMIF_CODEC) {
+ if (cfg->fmt & CAMIF_OUT_YCBCR420) {
+ t_size = daon * 3 / 2 ;
+ }
+ else { t_size = daon * 2; /* CAMIF_OUT_YCBCR422 */ }
+ t_size = t_size *cfg->pp_num;
+
+#ifndef SAMSUNG_SXGA_CAM
+ cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
+ t_size, &cfg->pp_phys_buf,
+ GFP_KERNEL);
+#else
+ printk(KERN_INFO "Reserving High RAM Addresses \n");
+ cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM);
+ cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf, YUV_MEM);
+#endif
+
+ if ( !cfg->pp_virt_buf ) {
+ printk(KERN_ERR"CAMERA:Failed to request YCBCR MEM\n");
+ return -ENOMEM;
+ }
+ memset(cfg->pp_virt_buf, 0, t_size);
+ cfg->pp_totalsize = t_size;
+ return 0;
+ }
+ if ( cfg->dma_type & CAMIF_PREVIEW ) {
+ if (cfg->fmt & CAMIF_RGB16)
+ t_size = daon * 2; /* 4byte per two pixel*/
+ else {
+ assert(cfg->fmt & CAMIF_RGB24);
+ t_size = daon * 4; /* 4byte per one pixel */
+ }
+ t_size = t_size * cfg->pp_num;
+#ifndef SAMSUNG_SXGA_CAM
+ cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
+ t_size, &cfg->pp_phys_buf,
+ GFP_KERNEL);
+#else
+ printk(KERN_INFO "Reserving High RAM Addresses \n");
+ cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM ) + YUV_MEM;
+ cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf,RGB_MEM);
+#endif
+ if ( !cfg->pp_virt_buf ) {
+ printk(KERN_ERR"CAMERA:Failed to request RGB MEM\n");
+ return -ENOMEM;
+ }
+ memset(cfg->pp_virt_buf, 0, t_size);
+ cfg->pp_totalsize = t_size;
+ return 0;
+ }
+
+ return 0; /* Never come. */
+}
+
+static int camif_demalloc(camif_cfg_t *cfg)
+{
+#ifndef SAMSUNG_SXGA_CAM
+ if ( cfg->pp_virt_buf ) {
+ dma_free_coherent(cfg->v->dev, cfg->pp_totalsize,
+ cfg->pp_virt_buf, cfg->pp_phys_buf);
+ cfg->pp_virt_buf = 0;
+ }
+#else
+ iounmap(cfg->pp_virt_buf);
+ cfg->pp_virt_buf = 0;
+#endif
+ return 0;
+}
+
+/*
+ * advise a person to use this func in ISR
+ * index value indicates the next frame count to be used
+ */
+int camif_g_frame_num(camif_cfg_t *cfg)
+{
+ int index = 0;
+
+ if (cfg->dma_type & CAMIF_CODEC ) {
+ index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
+ DPRINTK("CAMIF_CODEC frame %d \n", index);
+ }
+ else {
+ assert(cfg->dma_type & CAMIF_PREVIEW );
+ index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
+ DPRINTK("CAMIF_PREVIEW frame %d 0x%08X \n", index,
+ readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
+ }
+ cfg->now_frame_num = (index + 2) % 4; /* When 4 PingPong */
+ return index; /* meaningless */
+}
+
+static int camif_pp_codec(camif_cfg_t *cfg)
+{
+ u32 i, c_size; /* Cb,Cr size */
+ u32 one_p_size;
+ u32 daon = cfg->target_x * cfg->target_y;
+ if (cfg->fmt & CAMIF_OUT_YCBCR420)
+ c_size = daon / 4;
+ else {
+ assert(cfg->fmt & CAMIF_OUT_YCBCR422);
+ c_size = daon / 2;
+ }
+ switch ( cfg->pp_num ) {
+ case 1 :
+ for (i =0 ; i < 4; i++) {
+ cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
+ cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
+ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
+ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
+ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
+ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
+ writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
+ writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
+ writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
+ }
+ break;
+ case 2:
+#define TRY (( i%2 ) ? 1 :0)
+ one_p_size = daon + 2*c_size;
+ for (i = 0; i < 4 ; i++) {
+ cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
+ cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
+ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
+ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
+ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
+ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
+ writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
+ writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
+ writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
+ }
+ break;
+ case 4:
+ one_p_size = daon + 2*c_size;
+ for (i = 0; i < 4 ; i++) {
+ cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
+ cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
+ cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
+ cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
+ cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
+ cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
+ writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
+ writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
+ writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
+ }
+ break;
+ default:
+ printk("Invalid PingPong Number %d \n",cfg->pp_num);
+ panic("halt\n");
+}
+ return 0;
+}
+
+/* RGB Buffer Allocation */
+static int camif_pp_preview(camif_cfg_t *cfg)
+{
+ int i;
+ u32 daon = cfg->target_x * cfg->target_y;
+
+ if(cfg->fmt & CAMIF_RGB24)
+ daon = daon * 4 ;
+ else {
+ assert (cfg->fmt & CAMIF_RGB16);
+ daon = daon *2;
+ }
+ switch ( cfg->pp_num ) {
+ case 1:
+ for ( i = 0; i < 4 ; i++ ) {
+ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf ;
+ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf ;
+ writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
+ }
+ break;
+ case 2:
+ for ( i = 0; i < 4 ; i++) {
+ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + TRY * daon;
+ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + TRY * daon;
+ writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
+ }
+ break;
+ case 4:
+ for ( i = 0; i < 4 ; i++) {
+ cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * daon;
+ cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * daon;
+ writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
+ }
+ break;
+ default:
+ printk("Invalid PingPong Number %d \n",cfg->pp_num);
+ panic("halt\n");
+ }
+ return 0;
+}
+
+static int camif_pingpong(camif_cfg_t *cfg)
+{
+ if (cfg->dma_type & CAMIF_CODEC ) {
+ camif_pp_codec(cfg);
+ }
+
+ if ( cfg->dma_type & CAMIF_PREVIEW) {
+ camif_pp_preview(cfg);
+ }
+ return 0;
+}
+
+
+/*********** Image Convert *******************************/
+/* Return Format
+ * Supported by Hardware
+ * V4L2_PIX_FMT_YUV420,
+ * V4L2_PIX_FMT_YUV422P,
+ * V4L2_PIX_FMT_BGR32 (BGR4)
+ * -----------------------------------
+ * V4L2_PIX_FMT_RGB565(X)
+ * Currenly 2byte --> BGR656 Format
+ * S3C2440A,S3C24A0 supports vairants with reversed FMT_RGB565
+ i.e blue toward the least, red towards the most significant bit
+ -- by SW.LEE
+ */
+
+
+/*
+ * After calling camif_g_frame_num,
+ * this func must be called
+ */
+u8 * camif_g_frame(camif_cfg_t *cfg)
+{
+ u8 * ret = NULL;
+ int cnt = cfg->now_frame_num;
+
+ if(cfg->dma_type & CAMIF_PREVIEW) {
+ ret = cfg->img_buf[cnt].virt_rgb;
+ }
+ if (cfg->dma_type & CAMIF_CODEC) {
+ ret = cfg->img_buf[cnt].virt_y;
+ }
+ return ret;
+}
+
+/* This function must be called in module initial time */
+static int camif_source_fmt(camif_gc_t *gc)
+{
+ u32 cmd = 0;
+
+ /* Configure CISRCFMT --Source Format */
+ if (gc->itu_fmt & CAMIF_ITU601) {
+ cmd = CAMIF_ITU601;
+ }
+ else {
+ assert ( gc->itu_fmt & CAMIF_ITU656);
+ cmd = CAMIF_ITU656;
+ }
+ cmd |= SOURCE_HSIZE(gc->source_x)| SOURCE_VSIZE(gc->source_y);
+ /* Order422 */
+ cmd |= gc->order422;
+ writel(cmd, camregs + S3C2440_CAM_REG_CISRCFMT);
+
+ return 0 ;
+}
+
+
+/*
+ * Codec Input YCBCR422 will be Fixed
+ */
+static int camif_target_fmt(camif_cfg_t *cfg)
+{
+ u32 cmd = 0;
+
+ if (cfg->dma_type & CAMIF_CODEC) {
+ /* YCBCR setting */
+ cmd = TARGET_HSIZE(cfg->target_x)| TARGET_VSIZE(cfg->target_y);
+ if ( cfg->fmt & CAMIF_OUT_YCBCR420 ) {
+ cmd |= OUT_YCBCR420|IN_YCBCR422;
+ }
+ else {
+ assert(cfg->fmt & CAMIF_OUT_YCBCR422);
+ cmd |= OUT_YCBCR422|IN_YCBCR422;
+ }
+ writel(cmd | cfg->flip, camregs + S3C2440_CAM_REG_CICOTRGFMT);
+
+ } else {
+ assert(cfg->dma_type & CAMIF_PREVIEW);
+ writel(TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip,
+ camregs + S3C2440_CAM_REG_CIPRTRGFMT);
+ }
+ return 0;
+}
+
+void camif_change_flip(camif_cfg_t *cfg)
+{
+ u32 cmd = readl(camregs + S3C2440_CAM_REG_CICOTRGFMT);
+
+ cmd &= ~(BIT14|BIT15);
+ cmd |= cfg->flip;
+
+ writel(cmd, camregs + S3C2440_CAM_REG_CICOTRGFMT);
+}
+
+
+
+/* Must:
+ * Before calling this function,
+ * you must use "camif_dynamic_open"
+ * If you want to enable both CODEC and preview
+ * you must do it at the same time.
+ */
+int camif_capture_start(camif_cfg_t *cfg)
+{
+ u32 n_cmd = 0; /* Next Command */
+
+ switch(cfg->exec) {
+ case CAMIF_BOTH_DMA_ON:
+ camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
+ writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
+ SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
+ writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
+ SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
+ n_cmd = CAMIF_CAP_PREVIEW_ON | CAMIF_CAP_CODEC_ON;
+ break;
+ case CAMIF_DMA_ON:
+ camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
+ if (cfg->dma_type&CAMIF_CODEC) {
+ writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
+ SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
+ n_cmd = CAMIF_CAP_CODEC_ON;
+ } else {
+ writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
+ SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
+ n_cmd = CAMIF_CAP_PREVIEW_ON;
+ }
+
+ /* wait until Sync Time expires */
+ /* First settting, to wait VSYNC fall */
+ /* By VESA spec,in 640x480 @60Hz
+ MAX Delay Time is around 64us which "while" has.*/
+ while(VSYNC & readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
+ break;
+ default:
+ break;
+}
+ writel(n_cmd | CAMIF_CAP_ON, camregs + S3C2440_CAM_REG_CIIMGCPT);
+ return 0;
+}
+
+
+int camif_capture_stop(camif_cfg_t *cfg)
+{
+ u32 n_cmd = readl(camregs + S3C2440_CAM_REG_CIIMGCPT); /* Next Command */
+
+ switch(cfg->exec) {
+ case CAMIF_BOTH_DMA_OFF:
+ writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
+ ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
+ writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
+ ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
+ n_cmd = 0;
+ break;
+ case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
+ case CAMIF_DMA_OFF:
+ if (cfg->dma_type&CAMIF_CODEC) {
+ writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
+ ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
+ n_cmd &= ~CAMIF_CAP_CODEC_ON;
+ if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
+ n_cmd = 0;
+ } else {
+ writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
+ ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
+ n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
+ if (!(n_cmd & CAMIF_CAP_CODEC_ON))
+ n_cmd = 0;
+ }
+ break;
+ default:
+ panic("Unexpected \n");
+ }
+ writel(n_cmd, camregs + S3C2440_CAM_REG_CIIMGCPT);
+
+ if (cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ */
+ if (cfg->dma_type & CAMIF_CODEC)
+ writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
+ LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
+ else
+ writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
+ LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
+ }
+#if 0
+ else { /* to make internal state machine of CAMERA stop */
+ camif_reset(CAMIF_RESET, 0);
+ }
+#endif
+ return 0;
+}
+
+
+/* LastIRQEn is autoclear */
+void camif_last_irq_en(camif_cfg_t *cfg)
+{
+ if ((cfg->exec == CAMIF_BOTH_DMA_ON) || (cfg->dma_type & CAMIF_CODEC))
+ writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
+ LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
+
+ if ((cfg->exec == CAMIF_BOTH_DMA_ON) || !(cfg->dma_type & CAMIF_CODEC))
+ writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
+ LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
+}
+
+static int
+camif_scaler_internal(u32 srcWidth, u32 dstWidth, u32 *ratio, u32 *shift)
+{
+ if(srcWidth>=64*dstWidth){
+ printk(KERN_ERR"CAMERA:out of prescaler range: srcWidth /dstWidth = %d(< 64)\n",
+ srcWidth/dstWidth);
+ return 1;
+ }
+ else if(srcWidth>=32*dstWidth){
+ *ratio=32;
+ *shift=5;
+ }
+ else if(srcWidth>=16*dstWidth){
+ *ratio=16;
+ *shift=4;
+ }
+ else if(srcWidth>=8*dstWidth){
+ *ratio=8;
+ *shift=3;
+ }
+ else if(srcWidth>=4*dstWidth){
+ *ratio=4;
+ *shift=2;
+ }
+ else if(srcWidth>=2*dstWidth){
+ *ratio=2;
+ *shift=1;
+ }
+ else {
+ *ratio=1;
+ *shift=0;
+ }
+ return 0;
+}
+
+
+int camif_g_fifo_status(camif_cfg_t *cfg)
+{
+ u32 reg;
+
+ if (cfg->dma_type & CAMIF_CODEC) {
+ u32 flag = CO_OVERFLOW_Y | CO_OVERFLOW_CB | CO_OVERFLOW_CR;
+ reg = readl(camregs + S3C2440_CAM_REG_CICOSTATUS);
+ if (reg & flag) {
+ printk("CODEC: FIFO error(0x%08x) and corrected\n",reg);
+ /* FIFO Error Count ++ */
+ writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
+ CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR,
+ camregs + S3C2440_CAM_REG_CIWDOFST);
+
+ writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
+ ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
+ camregs + S3C2440_CAM_REG_CIWDOFST);
+ return 1; /* Error */
+ }
+ }
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ u32 flag = PR_OVERFLOW_CB | PR_OVERFLOW_CR;
+ reg = readl(camregs + S3C2440_CAM_REG_CIPRSTATUS);
+ if (reg & flag) {
+ printk("PREVIEW:FIFO error(0x%08x) and corrected\n",reg);
+ writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
+ CO_FIFO_CB | CO_FIFO_CR,
+ camregs + S3C2440_CAM_REG_CIWDOFST);
+
+ writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
+ ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
+ camregs + S3C2440_CAM_REG_CIWDOFST);
+ /* FIFO Error Count ++ */
+ return 1; /* Error */
+ }
+ }
+ return 0; /* No Error */
+}
+
+
+/* Policy:
+ * if codec or preview define the win offset,
+ * other must follow that value.
+ */
+int camif_win_offset(camif_gc_t *gc )
+{
+ u32 h = gc->win_hor_ofst;
+ u32 v = gc->win_ver_ofst;
+
+ /*Clear Overflow */
+ writel(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR | PR_FIFO_CB | PR_FIFO_CB,
+ camregs + S3C2440_CAM_REG_CIWDOFST);
+ writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
+
+ if (!h && !v) {
+ writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
+ return 0;
+ }
+
+ writel(WINOFEN | WINHOROFST(h) | WINVEROFST(v), camregs + S3C2440_CAM_REG_CIWDOFST);
+ return 0;
+}
+
+/*
+ * when you change the resolution in a specific camera,
+ * sometimes, it is necessary to change the polarity
+ * -- SW.LEE
+ */
+static void camif_polarity(camif_gc_t *gc)
+{
+ u32 cmd = readl(camregs + S3C2440_CAM_REG_CIGCTRL);;
+
+ cmd = cmd & ~(BIT26|BIT25|BIT24); /* clear polarity */
+ if (gc->polarity_pclk)
+ cmd |= GC_INVPOLPCLK;
+ if (gc->polarity_vsync)
+ cmd |= GC_INVPOLVSYNC;
+ if (gc->polarity_href)
+ cmd |= GC_INVPOLHREF;
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
+ cmd, camregs + S3C2440_CAM_REG_CIGCTRL);
+}
+
+
+int camif_dynamic_open(camif_cfg_t *cfg)
+{
+ camif_win_offset(cfg->gc);
+ camif_polarity(cfg->gc);
+
+ if(camif_scaler(cfg)) {
+ printk(KERN_ERR "CAMERA:Preview Scaler, Change WinHorOfset or Target Size\n");
+ return 1;
+ }
+ camif_target_fmt(cfg);
+ if (camif_dma_burst(cfg)) {
+ printk(KERN_ERR "CAMERA:DMA Busrt Length Error \n");
+ return 1;
+ }
+ if(camif_malloc(cfg) ) {
+ printk(KERN_ERR " Instead of using consistent_alloc()\n"
+ " lease use dedicated memory allocation for DMA memory\n");
+ return -1;
+ }
+ camif_pingpong(cfg);
+ return 0;
+}
+
+int camif_dynamic_close(camif_cfg_t *cfg)
+{
+ camif_demalloc(cfg);
+ return 0;
+}
+
+static int camif_target_area(camif_cfg_t *cfg)
+{
+ u32 rect = cfg->target_x * cfg->target_y;
+
+ if (cfg->dma_type & CAMIF_CODEC)
+ writel(rect, camregs + S3C2440_CAM_REG_CICOTAREA);
+
+ if (cfg->dma_type & CAMIF_PREVIEW)
+ writel(rect, camregs + S3C2440_CAM_REG_CIPRTAREA);
+
+ return 0;
+}
+
+static int inline camif_hw_reg(camif_cfg_t *cfg)
+{
+ u32 cmd = 0;
+
+ if (cfg->dma_type & CAMIF_CODEC) {
+ writel(PRE_SHIFT(cfg->sc.shfactor) |
+ PRE_HRATIO(cfg->sc.prehratio) |
+ PRE_VRATIO(cfg->sc.prevratio),
+ camregs + S3C2440_CAM_REG_CICOSCPRERATIO);
+ writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
+ PRE_DST_HEIGHT(cfg->sc.predst_y),
+ camregs + S3C2440_CAM_REG_CICOSCPREDST);
+
+ /* Differ from Preview */
+ if (cfg->sc.scalerbypass)
+ cmd |= SCALERBYPASS;
+ if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
+ cmd |= BIT30|BIT29;
+ writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) |
+ MAIN_VRATIO(cfg->sc.mainvratio),
+ camregs + S3C2440_CAM_REG_CICOSCCTRL);
+ return 0;
+ }
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ writel(PRE_SHIFT(cfg->sc.shfactor) |
+ PRE_HRATIO(cfg->sc.prehratio) |
+ PRE_VRATIO(cfg->sc.prevratio),
+ camregs + S3C2440_CAM_REG_CIPRSCPRERATIO);
+ writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
+ PRE_DST_HEIGHT(cfg->sc.predst_y),
+ camregs + S3C2440_CAM_REG_CIPRSCPREDST);
+ /* Differ from Codec */
+ if (cfg->fmt & CAMIF_RGB24)
+ cmd |= RGB_FMT24;
+ if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
+ cmd |= BIT29 | BIT28;
+ writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) | S_METHOD |
+ MAIN_VRATIO(cfg->sc.mainvratio),
+ camregs + S3C2440_CAM_REG_CIPRSCCTRL);
+ return 0;
+ }
+
+ panic("CAMERA:DMA_TYPE Wrong \n");
+ return 0;
+}
+
+
+/* Configure Pre-scaler control & main scaler control register */
+static int camif_scaler(camif_cfg_t *cfg)
+{
+ int tx = cfg->target_x, ty = cfg->target_y;
+ int sx, sy;
+
+ if (tx <= 0 || ty <= 0)
+ panic("CAMERA: Invalid target size \n");
+
+ sx = cfg->gc->source_x - 2 * cfg->gc->win_hor_ofst;
+ sy = cfg->gc->source_y - 2 * cfg->gc->win_ver_ofst;
+ if (sx <= 0 || sy <= 0)
+ panic("CAMERA: Invalid source size \n");
+
+ cfg->sc.modified_src_x = sx;
+ cfg->sc.modified_src_y = sy;
+
+ /* Pre-scaler control register 1 */
+ camif_scaler_internal(sx, tx, &cfg->sc.prehratio, &cfg->sc.hfactor);
+ camif_scaler_internal(sy, ty, &cfg->sc.prevratio, &cfg->sc.vfactor);
+
+ if (cfg->dma_type & CAMIF_PREVIEW)
+ if ((sx / cfg->sc.prehratio) > 640) {
+ printk(KERN_INFO "CAMERA: Internal Preview line "
+ "buffer is 640 pixels\n");
+ return 1; /* Error */
+ }
+
+ cfg->sc.shfactor = 10 - (cfg->sc.hfactor + cfg->sc.vfactor);
+ /* Pre-scaler control register 2 */
+ cfg->sc.predst_x = sx / cfg->sc.prehratio;
+ cfg->sc.predst_y = sy / cfg->sc.prevratio;
+
+ /* Main-scaler control register */
+ cfg->sc.mainhratio = (sx << 8) / (tx << cfg->sc.hfactor);
+ cfg->sc.mainvratio = (sy << 8) / (ty << cfg->sc.vfactor);
+ DPRINTK(" sx %d, sy %d tx %d ty %d \n", sx, sy, tx, ty);
+ DPRINTK(" hfactor %d vfactor %d \n",cfg->sc.hfactor, cfg->sc.vfactor);
+
+ cfg->sc.scaleup_h = (sx <= tx) ? 1: 0;
+ cfg->sc.scaleup_v = (sy <= ty) ? 1: 0;
+ if (cfg->sc.scaleup_h != cfg->sc.scaleup_v)
+ printk(KERN_ERR "scaleup_h must be same to scaleup_v \n");
+
+ camif_hw_reg(cfg);
+ camif_target_area(cfg);
+
+ return 0;
+}
+
+/******************************************************
+ CalculateBurstSize - Calculate the busrt lengths
+ Description:
+ - dstHSize: the number of the byte of H Size.
+********************************************************/
+static void camif_g_bsize(u32 hsize, u32 *mburst, u32 *rburst)
+{
+ u32 tmp;
+
+ tmp = (hsize / 4) % 16;
+ switch(tmp) {
+ case 0:
+ *mburst=16;
+ *rburst=16;
+ break;
+ case 4:
+ *mburst=16;
+ *rburst=4;
+ break;
+ case 8:
+ *mburst=16;
+ *rburst=8;
+ break;
+ default:
+ tmp=(hsize / 4) % 8;
+ switch(tmp) {
+ case 0:
+ *mburst = 8;
+ *rburst = 8;
+ break;
+ case 4:
+ *mburst = 8;
+ *rburst = 4;
+ default:
+ *mburst = 4;
+ tmp = (hsize / 4) % 4;
+ *rburst= (tmp) ? tmp: 4;
+ break;
+ }
+ break;
+ }
+}
+
+/* SXGA 1028x1024*/
+/* XGA 1024x768 */
+/* SVGA 800x600 */
+/* VGA 640x480 */
+/* CIF 352x288 */
+/* QVGA 320x240 */
+/* QCIF 176x144 */
+/* ret val
+ 1 : DMA Size Error
+*/
+#define BURST_ERR 1
+static int camif_dma_burst(camif_cfg_t *cfg)
+{
+ int width = cfg->target_x;
+
+ if (cfg->dma_type & CAMIF_CODEC ) {
+ u32 yburst_m, yburst_r;
+ u32 cburst_m, cburst_r;
+ /* CODEC DMA WIDHT is multiple of 16 */
+ if (width % 16)
+ return BURST_ERR; /* DMA Burst Length Error */
+ camif_g_bsize(width, &yburst_m, &yburst_r);
+ camif_g_bsize(width / 2, &cburst_m, &cburst_r);
+
+ writel(YBURST_M(yburst_m) | CBURST_M(cburst_m) |
+ YBURST_R(yburst_r) | CBURST_R(cburst_r),
+ camregs + S3C2440_CAM_REG_CICOCTRL);
+ }
+
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ u32 rgburst_m, rgburst_r;
+ if(cfg->fmt == CAMIF_RGB24) {
+ if (width % 2)
+ return BURST_ERR; /* DMA Burst Length Error */
+ camif_g_bsize(width*4,&rgburst_m,&rgburst_r);
+ } else { /* CAMIF_RGB16 */
+ if ((width / 2) %2)
+ return BURST_ERR; /* DMA Burst Length Error */
+ camif_g_bsize(width*2,&rgburst_m,&rgburst_r);
+ }
+
+ writel(RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r),
+ camregs + S3C2440_CAM_REG_CIPRCTRL);
+ }
+ return 0;
+}
+
+static int camif_gpio_init(void)
+{
+#ifdef CONFIG_ARCH_S3C24A0A
+ /* S3C24A0A has the dedicated signal pins for Camera */
+#else
+ s3c2410_gpio_cfgpin(S3C2440_GPJ0, S3C2440_GPJ0_CAMDATA0);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ1, S3C2440_GPJ1_CAMDATA1);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ2, S3C2440_GPJ2_CAMDATA2);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ3, S3C2440_GPJ3_CAMDATA3);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ4, S3C2440_GPJ4_CAMDATA4);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ5, S3C2440_GPJ5_CAMDATA5);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ6, S3C2440_GPJ6_CAMDATA6);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ7, S3C2440_GPJ7_CAMDATA7);
+
+ s3c2410_gpio_cfgpin(S3C2440_GPJ8, S3C2440_GPJ8_CAMPCLK);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ9, S3C2440_GPJ9_CAMVSYNC);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ10, S3C2440_GPJ10_CAMHREF);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ11, S3C2440_GPJ11_CAMCLKOUT);
+ s3c2410_gpio_cfgpin(S3C2440_GPJ12, S3C2440_GPJ12_CAMRESET);
+#endif
+ return 0;
+}
+
+
+#define ROUND_ADD 0x100000
+
+#ifdef CONFIG_ARCH_S3C24A0A
+int camif_clock_init(camif_gc_t *gc)
+{
+ unsigned int upll, camclk_div, camclk;
+
+ if (!gc) camclk = 24000000;
+ else {
+ camclk = gc->camclk;
+ if (camclk > 48000000)
+ printk(KERN_ERR "Wrong Camera Clock\n");
+ }
+
+ CLKCON |= CLKCON_CAM_UPLL | CLKCON_CAM_HCLK;
+ upll = get_bus_clk(GET_UPLL);
+ printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
+ UPLLCON = FInsrt(56, fPLL_MDIV) | FInsrt(2, fPLL_PDIV)| FInsrt(1, fPLL_SDIV);
+ upll = get_bus_clk(GET_UPLL);
+
+ camclk_div = (upll+ROUND_ADD) / camclk - 1;
+ CLKDIVN = (CLKDIVN & 0xFF) | CLKDIVN_CAM(camclk_div);
+ printk(KERN_INFO"CAMERA:upll %d MACRO 0x%08X CLKDIVN 0x%08X \n",
+ upll, CLKDIVN_CAM(camclk_div), CLKDIVN);
+ writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT); /* Dummy ? */
+
+ return 0;
+}
+#else
+int camif_clock_init(camif_gc_t *gc)
+{
+ unsigned int camclk;
+ struct clk *clk_camif = clk_get(NULL, "camif");
+ struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
+
+ if (!gc)
+ camclk = 24000000;
+ else {
+ camclk = gc->camclk;
+ if (camclk > 48000000)
+ printk(KERN_ERR "Wrong Camera Clock\n");
+ }
+
+ clk_set_rate(clk_camif, camclk);
+
+ clk_enable(clk_camif);
+ clk_enable(clk_camif_upll);
+
+
+#if 0
+ CLKCON |= CLKCON_CAMIF;
+ upll = elfin_get_bus_clk(GET_UPLL);
+ printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
+ {
+ UPLLCON = FInsrt(60, fPLL_MDIV) | FInsrt(4, fPLL_PDIV)| FInsrt(1, fPLL_SDIV);
+ CLKDIVN |= DIVN_UPLL; /* For USB */
+ upll = elfin_get_bus_clk(GET_UPLL);
+ }
+
+ camclk_div = (upll+ROUND_ADD) /(camclk * 2) -1;
+ CAMDIVN = CAMCLK_SET_DIV|(camclk_div&0xf);
+ printk(KERN_INFO "CAMERA:upll %08d cam_clk %08d CAMDIVN 0x%08x \n",upll,camclk, CAMDIVN);
+#endif
+ writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT); /* Dummy ? */
+
+ return 0;
+}
+#endif
+
+/*
+ Reset Camera IP in CPU
+ Reset External Sensor
+ */
+void camif_reset(int is, int delay)
+{
+ switch (is) {
+ case CAMIF_RESET:
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
+ GC_SWRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ mdelay(1);
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
+ ~GC_SWRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ break;
+ case CAMIF_EX_RESET_AH: /*Active High */
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
+ ~GC_CAMRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ udelay(200);
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
+ GC_CAMRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ udelay(delay);
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
+ ~GC_CAMRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ break;
+ case CAMIF_EX_RESET_AL: /*Active Low */
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
+ GC_CAMRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ udelay(200);
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
+ ~GC_CAMRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ udelay(delay);
+ writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
+ GC_CAMRST,
+ camregs + S3C2440_CAM_REG_CIGCTRL);
+ break;
+ default:
+ break;
+ }
+}
+
+/* For Camera Operation,
+ * we can give the high priority to REQ2 of ARBITER1
+ */
+
+/* Please move me into proper place
+ * camif_gc_t is not because "rmmod imgsenor" will delete the instance of camif_gc_t
+ */
+static u32 old_priority;
+
+static void camif_bus_priority(int flag)
+{
+ if (flag) {
+#ifdef CONFIG_ARCH_S3C24A0A
+ old_priority = PRIORITY0;
+ PRIORITY0 = PRIORITY_I_FIX;
+ PRIORITY1 = PRIORITY_I_FIX;
+
+#else
+ old_priority = readl(S3C2410_PRIORITY);
+ writel(readl(S3C2410_PRIORITY) & ~(3<<7), S3C2410_PRIORITY);
+ writel(readl(S3C2410_PRIORITY) | (1<<7), S3C2410_PRIORITY); /* Arbiter 1, REQ2 first */
+ writel(readl(S3C2410_PRIORITY) & ~(1<<1), S3C2410_PRIORITY); /* Disable Priority Rotate */
+#endif
+ }
+ else {
+#ifdef CONFIG_ARCH_S3C24A0A
+ PRIORITY0 = old_priority;
+ PRIORITY1 = old_priority;
+#else
+ writel(old_priority, S3C2410_PRIORITY);
+#endif
+ }
+}
+
+static void inline camif_clock_off(void)
+{
+#if defined (CONFIG_ARCH_S3C24A0A)
+ writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
+
+ CLKCON &= ~CLKCON_CAM_UPLL;
+ CLKCON &= ~CLKCON_CAM_HCLK;
+#else
+ struct clk *clk_camif = clk_get(NULL, "camif");
+ struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
+
+ writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
+
+ clk_disable(clk_camif);
+ clk_disable(clk_camif_upll);
+#endif
+}
+
+
+/* Init external image sensor
+ * Before make some value into image senor,
+ * you must set up the pixel clock.
+ */
+void camif_setup_sensor(void)
+{
+ camif_reset(CAMIF_RESET, 0);
+ camif_gpio_init();
+ camif_clock_init(NULL);
+/* Sometimes ,Before loading I2C module, we need the reset signal */
+#ifdef CONFIG_ARCH_S3C24A0A
+ camif_reset(CAMIF_EX_RESET_AL,1000);
+#else
+ camif_reset(CAMIF_EX_RESET_AH,1000);
+#endif
+}
+
+void camif_hw_close(camif_cfg_t *cfg)
+{
+ camif_bus_priority(0);
+ camif_clock_off();
+}
+
+void camif_hw_open(camif_gc_t *gc)
+{
+ camif_source_fmt(gc);
+ camif_win_offset(gc);
+ camif_bus_priority(1);
+}
+
+
+
+/*
+ * Local variables:
+ * tab-width: 8
+ * c-indent-level: 8
+ * c-basic-offset: 8
+ * c-set-style: "K&R"
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/camif_fsm.c
@@ -0,0 +1,432 @@
+/*
+ Copyright (C) 2004 Samsung Electronics
+ SW.LEE <hitchcar@sec.samsung.com>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+*/
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/init.h>
+#include <linux/pagemap.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/semaphore.h>
+#include <linux/miscdevice.h>
+
+#define CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#include "camif.h"
+
+//#define SW_DEBUG
+static void camif_start_p_with_c(camif_cfg_t *cfg);
+
+#include "camif.h"
+const char *fsm_version =
+ "$Id: camif_fsm.c,v 1.3 2004/04/27 10:26:28 swlee Exp $";
+
+
+/*
+ * FSM function is the place where Synchronization in not necessary
+ * because IRS calls this functions.
+ */
+
+ssize_t camif_p_1fsm_start(camif_cfg_t *cfg)
+{
+ //camif_reset(CAMIF_RESET,0);
+ cfg->exec = CAMIF_DMA_ON;
+ camif_capture_start(cfg);
+ camif_last_irq_en(cfg);
+ cfg->status = CAMIF_STARTED;
+ cfg->fsm = CAMIF_1nd_INT;
+ return 0;
+}
+
+
+ssize_t camif_p_2fsm_start(camif_cfg_t *cfg)
+{
+ camif_reset(CAMIF_RESET,0);/* FIFO Count goes to zero */
+ cfg->exec = CAMIF_DMA_ON;
+ camif_capture_start(cfg);
+ cfg->status = CAMIF_STARTED;
+ cfg->fsm = CAMIF_1nd_INT;
+ return 0;
+}
+
+
+ssize_t camif_4fsm_start(camif_cfg_t *cfg)
+{
+ camif_reset(CAMIF_RESET,0); /* FIFO Count goes to zero */
+ cfg->exec = CAMIF_DMA_ON;
+ camif_capture_start(cfg);
+ cfg->status = CAMIF_STARTED;
+ cfg->fsm = CAMIF_1nd_INT;
+ cfg->perf.frames = 0;
+ return 0;
+}
+
+
+/* Policy:
+ cfg->perf.frames set in camif_fsm.c
+ cfg->status set in video-driver.c
+ */
+
+/*
+ * Don't insert camif_reset(CAM_RESET, 0 ) into this func
+ */
+ssize_t camif_p_stop(camif_cfg_t *cfg)
+{
+ cfg->exec = CAMIF_DMA_OFF;
+// cfg->status = CAMIF_STOPPED;
+ camif_capture_stop(cfg);
+ cfg->perf.frames = 0; /* Dupplicated ? */
+ return 0;
+}
+
+/* When C working, P asks C to play togehter */
+/* Only P must call this function */
+void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other)
+{
+// cfg->gc->other = get_camif(CODEC_MINOR);
+ cfg->gc->other = other;
+ camif_start_p_with_c(cfg);
+}
+
+static void camif_start_p_with_c(camif_cfg_t *cfg)
+{
+ camif_cfg_t *other = (camif_cfg_t *)cfg->gc->other;
+ /* Preview Stop */
+ cfg->exec = CAMIF_DMA_OFF;
+ camif_capture_stop(cfg);
+ /* Start P and C */
+ camif_reset(CAMIF_RESET, 0);
+ cfg->exec =CAMIF_BOTH_DMA_ON;
+ camif_capture_start(cfg);
+ cfg->fsm = CAMIF_1nd_INT; /* For Preview */
+ if(!other) panic("Unexpected Error \n");
+ other->fsm = CAMIF_1nd_INT; /* For Preview */
+}
+
+static void camif_auto_restart(camif_cfg_t *cfg)
+{
+// if (cfg->dma_type & CAMIF_CODEC) return;
+ if (cfg->auto_restart)
+ camif_start_p_with_c(cfg);
+}
+
+
+/* Supposed that PREVIEW already running
+ * request PREVIEW to start with Codec
+ */
+static int camif_check_global(camif_cfg_t *cfg)
+{
+ int ret = 0;
+
+ if (down_interruptible(&cfg->gc->lock))
+ return -ERESTARTSYS;
+ if ( cfg->gc->status & CWANT2START ) {
+ cfg->gc->status &= ~CWANT2START;
+ cfg->auto_restart = 1;
+ ret = 1;
+ }
+ else {
+ ret = 0; /* There is no codec */
+ cfg->auto_restart = 0; /* Duplicated ..Dummy */
+ }
+
+ up(&cfg->gc->lock);
+
+ return ret;
+}
+
+/*
+ * 1nd INT : Start Interrupt
+ * Xnd INT : enable Last IRQ : pingpong get the valid data
+ * Ynd INT : Stop Codec or Preview : pingpong get the valid data
+ * Znd INT : Last IRQ : valid data
+ */
+#define CHECK_FREQ 5
+int camif_enter_p_4fsm(camif_cfg_t *cfg)
+{
+ int ret = 0;
+
+ cfg->perf.frames++;
+ if (cfg->fsm == CAMIF_NORMAL_INT)
+ if (cfg->perf.frames % CHECK_FREQ == 0)
+ ret = camif_check_global(cfg);
+ if (ret > 0) cfg->fsm = CAMIF_Xnd_INT; /* Codec wait for Preview */
+
+ switch (cfg->fsm) {
+ case CAMIF_1nd_INT: /* Start IRQ */
+ cfg->fsm = CAMIF_NORMAL_INT;
+ ret = INSTANT_SKIP;
+ DPRINTK(KERN_INFO "1nd INT \n");
+ break;
+ case CAMIF_NORMAL_INT:
+ cfg->status = CAMIF_INT_HAPPEN;
+ cfg->fsm = CAMIF_NORMAL_INT;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "NORMAL INT \n");
+ break;
+ case CAMIF_Xnd_INT:
+ camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
+ cfg->status = CAMIF_INT_HAPPEN;
+ cfg->fsm = CAMIF_Ynd_INT;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "Xnd INT \n");
+ break;
+ case CAMIF_Ynd_INT: /* Capture Stop */
+ cfg->exec = CAMIF_DMA_OFF;
+ cfg->status = CAMIF_INT_HAPPEN;
+ camif_capture_stop(cfg);
+ cfg->fsm = CAMIF_Znd_INT;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "Ynd INT \n");
+ break;
+ case CAMIF_Znd_INT: /* LAST IRQ (Dummy IRQ */
+ cfg->fsm = CAMIF_DUMMY_INT;
+ cfg->status = CAMIF_INT_HAPPEN;
+ ret = INSTANT_GO;
+ camif_auto_restart(cfg); /* Automatically Restart Camera */
+ DPRINTK(KERN_INFO "Znd INT \n");
+ break;
+ case CAMIF_DUMMY_INT:
+ cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
+ ret = INSTANT_SKIP;
+// DPRINTK(KERN_INFO "Dummy INT \n");
+ break;
+ default:
+ printk(KERN_INFO "Unexpect INT %d \n",cfg->fsm);
+ ret = INSTANT_SKIP;
+ break;
+ }
+ return ret;
+}
+
+
+/*
+ * NO autorestart included in this function
+ */
+int camif_enter_c_4fsm(camif_cfg_t *cfg)
+{
+ int ret;
+
+ cfg->perf.frames++;
+#if 0
+ if ( (cfg->fsm==CAMIF_NORMAL_INT)
+ && (cfg->perf.frames>cfg->restart_limit-1)
+ )
+ cfg->fsm = CAMIF_Xnd_INT;
+#endif
+ switch (cfg->fsm) {
+ case CAMIF_1nd_INT: /* Start IRQ */
+ cfg->fsm = CAMIF_NORMAL_INT;
+// cfg->status = CAMIF_STARTED; /* need this to meet auto-restart */
+ ret = INSTANT_SKIP;
+ DPRINTK(KERN_INFO "1nd INT \n");
+ break;
+ case CAMIF_NORMAL_INT:
+ cfg->status = CAMIF_INT_HAPPEN;
+ cfg->fsm = CAMIF_NORMAL_INT;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "NORMALd INT \n");
+ break;
+ case CAMIF_Xnd_INT:
+ camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
+ cfg->status = CAMIF_INT_HAPPEN;
+ cfg->fsm = CAMIF_Ynd_INT;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "Xnd INT \n");
+ break;
+ case CAMIF_Ynd_INT: /* Capture Stop */
+ cfg->exec = CAMIF_DMA_OFF;
+ cfg->status = CAMIF_INT_HAPPEN;
+ camif_capture_stop(cfg);
+ cfg->fsm = CAMIF_Znd_INT;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "Ynd INT \n");
+ break;
+ case CAMIF_Znd_INT: /* LAST IRQ (Dummy IRQ */
+ cfg->fsm = CAMIF_DUMMY_INT;
+ cfg->status = CAMIF_INT_HAPPEN;
+ ret = INSTANT_GO;
+ DPRINTK(KERN_INFO "Znd INT \n");
+ break;
+ case CAMIF_DUMMY_INT:
+ cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
+ ret = INSTANT_SKIP;
+ break;
+ default:
+ printk(KERN_INFO "Unexpect INT %d \n",cfg->fsm);
+ ret = INSTANT_SKIP;
+ break;
+ }
+ return ret;
+}
+
+/* 4 Interrups State Machine is for two pingpong
+ * 1nd INT : Start Interrupt
+ * Xnd INT : enable Last IRQ : pingpong get the valid data
+ * Ynd INT : Stop Codec or Preview : pingpong get the valid data
+ * Znd INT : Last IRQ : valid data
+ *
+ * Note:
+ * Before calling this func, you must call camif_reset
+ */
+
+int camif_enter_2fsm(camif_cfg_t *cfg) /* Codec FSM */
+{
+ int ret;
+
+ cfg->perf.frames++;
+ switch (cfg->fsm) {
+ case CAMIF_1nd_INT: /* Start IRQ */
+ cfg->fsm = CAMIF_Xnd_INT;
+ ret = INSTANT_SKIP;
+// printk(KERN_INFO "1nd INT \n");
+ break;
+ case CAMIF_Xnd_INT:
+ camif_last_irq_en(cfg);/* IRQ for Enabling LAST IRQ */
+ cfg->now_frame_num = 0;
+ cfg->status = CAMIF_INT_HAPPEN;
+ cfg->fsm = CAMIF_Ynd_INT;
+ ret = INSTANT_GO;
+// printk(KERN_INFO "2nd INT \n");
+ break;
+ case CAMIF_Ynd_INT: /* Capture Stop */
+ cfg->exec = CAMIF_DMA_OFF;
+ cfg->now_frame_num = 1;
+ cfg->status = CAMIF_INT_HAPPEN;
+ camif_capture_stop(cfg);
+ cfg->fsm = CAMIF_Znd_INT;
+ ret = INSTANT_GO;
+// printk(KERN_INFO "Ynd INT \n");
+ break;
+ case CAMIF_Znd_INT: /* LAST IRQ (Dummy IRQ */
+ cfg->now_frame_num = 0;
+// cfg->fsm = CAMIF_DUMMY_INT;
+ cfg->status = CAMIF_INT_HAPPEN;
+ ret = INSTANT_GO;
+// printk(KERN_INFO "Znd INT \n");
+ break;
+ case CAMIF_DUMMY_INT:
+ cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
+ ret = INSTANT_SKIP;
+ printk(KERN_INFO "Dummy INT \n");
+ break;
+ default: /* CAMIF_PENDING_INT */
+ printk(KERN_INFO "Unexpect INT \n");
+ ret = INSTANT_SKIP;
+ break;
+ }
+ return ret;
+}
+
+
+/* 2 Interrups State Machine is for one pingpong
+ * 1nd INT : Stop Codec or Preview : pingpong get the valid data
+ * 2nd INT : Last IRQ : dummy data
+ */
+int camif_enter_1fsm(camif_cfg_t *cfg) /* Codec FSM */
+{
+ int ret;
+
+ cfg->perf.frames++;
+ switch (cfg->fsm) {
+ case CAMIF_Ynd_INT: /* IRQ for Enabling LAST IRQ */
+ cfg->exec = CAMIF_DMA_OFF;
+ camif_capture_stop(cfg);
+ cfg->fsm = CAMIF_Znd_INT;
+ ret = INSTANT_SKIP;
+ // printk(KERN_INFO "Ynd INT \n");
+ break;
+ case CAMIF_Znd_INT: /* LAST IRQ (Dummy IRQ */
+ cfg->fsm = CAMIF_DUMMY_INT;
+ cfg->status = CAMIF_INT_HAPPEN;
+ ret = INSTANT_GO;
+ // printk(KERN_INFO "Znd INT \n");
+ break;
+ case CAMIF_DUMMY_INT:
+ cfg->status = CAMIF_STOPPED; /* Dupplicate ? */
+ ret = INSTANT_SKIP;
+ printk(KERN_INFO "Dummy INT \n");
+ break;
+ default:
+ printk(KERN_INFO "Unexpect INT \n");
+ ret = INSTANT_SKIP;
+ break;
+ }
+ return ret;
+}
+
+
+/*
+ * GLOBAL STATUS CONTROL FUNCTION
+ *
+ */
+
+
+/* Supposed that PREVIEW already running
+ * request PREVIEW to start with Codec
+ */
+int camif_callback_start(camif_cfg_t *cfg)
+{
+ int doit = 1;
+ while (doit) {
+ if (down_interruptible(&cfg->gc->lock)) {
+ return -ERESTARTSYS;
+ }
+ cfg->gc->status = CWANT2START;
+ cfg->gc->other = cfg;
+ up(&cfg->gc->lock);
+ doit = 0;
+ }
+ return 0;
+}
+
+/*
+ * Return status of Preview Machine
+ ret value :
+ 0: Preview is not working
+ X: Codec must follow PREVIEW start
+*/
+int camif_check_preview(camif_cfg_t *cfg)
+{
+ int ret = 0;
+
+ if (down_interruptible(&cfg->gc->lock)) {
+ ret = -ERESTARTSYS;
+ return ret;
+ }
+ if (cfg->gc->user == 1) ret = 0;
+ // else if (cfg->gc->status & PNOTWORKING) ret = 0;
+ else ret = 1;
+ up(&cfg->gc->lock);
+ return ret;
+}
+
+
+
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/camif.h
@@ -0,0 +1,304 @@
+/*
+ FIMC2.0 Camera Header File
+
+ Copyright (C) 2003 Samsung Electronics (SW.LEE: hitchcar@samsung.com)
+
+ Author : SW.LEE <hitchcar@samsung.com>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+*
+*/
+
+
+#ifndef __FIMC20_CAMIF_H_
+#define __FIMC20_CAMIF_H_
+
+#ifdef __KERNEL__
+
+#include "bits.h"
+#include "videodev.h"
+#include <asm/types.h>
+#include <linux/i2c.h>
+
+#endif /* __KERNEL__ */
+
+#ifndef O_NONCAP
+#define O_NONCAP O_TRUNC
+#endif
+
+/* Codec or Preview Status */
+#define CAMIF_STARTED BIT1
+#define CAMIF_STOPPED BIT2
+#define CAMIF_INT_HAPPEN BIT3
+
+/* Codec or Preview : Interrupt FSM */
+#define CAMIF_1nd_INT BIT7
+#define CAMIF_Xnd_INT BIT8
+#define CAMIF_Ynd_INT BIT9
+#define CAMIF_Znd_INT BIT10
+#define CAMIF_NORMAL_INT BIT11
+#define CAMIF_DUMMY_INT BIT12
+#define CAMIF_PENDING_INT 0
+
+
+/* CAMIF RESET Definition */
+#define CAMIF_RESET BIT0
+#define CAMIF_EX_RESET_AL BIT1 /* Active Low */
+#define CAMIF_EX_RESET_AH BIT2 /* Active High */
+
+
+enum camif_itu_fmt {
+ CAMIF_ITU601 = BIT31,
+ CAMIF_ITU656 = 0
+};
+
+/* It is possbie to use two device simultaneously */
+enum camif_dma_type {
+ CAMIF_PREVIEW = BIT0,
+ CAMIF_CODEC = BIT1,
+};
+
+enum camif_order422 {
+ CAMIF_YCBYCR = 0,
+ CAMIF_YCRYCB = BIT14,
+ CAMIF_CBYCRY = BIT15,
+ CAMIF_CRYCBY = BIT14 | BIT15
+};
+
+enum flip_mode {
+ CAMIF_FLIP = 0,
+ CAMIF_FLIP_X = BIT14,
+ CAMIF_FLIP_Y = BIT15,
+ CAMIF_FLIP_MIRROR = BIT14 |BIT15,
+};
+
+enum camif_codec_fmt {
+ /* Codec part */
+ CAMIF_IN_YCBCR420 = BIT0, /* Currently IN_YCBCR format fixed */
+ CAMIF_IN_YCBCR422 = BIT1,
+ CAMIF_OUT_YCBCR420 = BIT4,
+ CAMIF_OUT_YCBCR422 = BIT5,
+ /* Preview Part */
+ CAMIF_RGB16 = BIT2,
+ CAMIF_RGB24 = BIT3,
+};
+
+enum camif_capturing {
+ CAMIF_BOTH_DMA_ON = BIT4,
+ CAMIF_DMA_ON = BIT3,
+ CAMIF_BOTH_DMA_OFF = BIT1,
+ CAMIF_DMA_OFF = BIT0,
+ /*------------------------*/
+ CAMIF_DMA_OFF_L_IRQ= BIT5,
+};
+
+typedef struct camif_performance
+{
+ int frames;
+ int framesdropped;
+ __u64 bytesin;
+ __u64 bytesout;
+ __u32 reserved[4];
+} camif_perf_t;
+
+
+typedef struct {
+ dma_addr_t phys_y;
+ dma_addr_t phys_cb;
+ dma_addr_t phys_cr;
+ u8 *virt_y;
+ u8 *virt_cb;
+ u8 *virt_cr;
+ dma_addr_t phys_rgb;
+ u8 *virt_rgb;
+}img_buf_t;
+
+
+/* this structure convers the CIWDOFFST, prescaler, mainscaler */
+typedef struct {
+ u32 modified_src_x; /* After windows applyed to source_x */
+ u32 modified_src_y;
+ u32 hfactor;
+ u32 vfactor;
+ u32 shfactor; /* SHfactor = 10 - ( hfactor + vfactor ) */
+ u32 prehratio;
+ u32 prevratio;
+ u32 predst_x;
+ u32 predst_y;
+ u32 scaleup_h;
+ u32 scaleup_v;
+ u32 mainhratio;
+ u32 mainvratio;
+ u32 scalerbypass; /* only codec */
+} scaler_t;
+
+
+enum v4l2_status {
+ CAMIF_V4L2_INIT = BIT0,
+ CAMIF_v4L2_DIRTY = BIT1,
+};
+
+
+/* Global Status Definition */
+#define PWANT2START BIT0
+#define CWANT2START BIT1
+#define BOTH_STARTED (PWANT2START|CWANT2START)
+#define PNOTWORKING BIT4
+#define C_WORKING BIT5
+
+typedef struct {
+ struct semaphore lock;
+ enum camif_itu_fmt itu_fmt;
+ enum camif_order422 order422;
+ u32 win_hor_ofst;
+ u32 win_ver_ofst;
+ u32 camclk; /* External Image Sensor Camera Clock */
+ u32 source_x;
+ u32 source_y;
+ u32 polarity_pclk;
+ u32 polarity_vsync;
+ u32 polarity_href;
+ struct i2c_client *sensor;
+ u32 user; /* MAX 2 (codec, preview) */
+ u32 old_priority; /* BUS PRIORITY register */
+ u32 status;
+ u32 init_sensor;/* initializing sensor */
+ void *other; /* Codec camif_cfg_t */
+ u32 reset_type; /* External Sensor Reset Type */
+ u32 reset_udelay;
+} camif_gc_t; /* gobal control register */
+
+
+/* when App want to change v4l2 parameter,
+ * we instantly store it into v4l2_t v2
+ * and then reflect it to hardware
+ */
+typedef struct v4l2 {
+ struct v4l2_fmtdesc *fmtdesc;
+ struct v4l2_pix_format fmt; /* current pixel format */
+ struct v4l2_input input;
+ struct video_picture picture;
+ enum v4l2_status status;
+ int used_fmt ; /* used format index */
+} v4l2_t;
+
+
+typedef struct camif_c_t {
+ struct video_device *v;
+ /* V4L2 param only for v4l2 driver */
+ v4l2_t v2;
+ camif_gc_t *gc; /* Common between Codec and Preview */
+ /* logical parameter */
+ wait_queue_head_t waitq;
+ u32 status; /* Start/Stop */
+ u32 fsm; /* Start/Stop */
+ u32 open_count; /* duplicated */
+ int irq;
+ char shortname[16];
+ u32 target_x;
+ u32 target_y;
+ scaler_t sc;
+ enum flip_mode flip;
+ enum camif_dma_type dma_type;
+ /* 4 pingpong Frame memory */
+ u8 *pp_virt_buf;
+ dma_addr_t pp_phys_buf;
+ u32 pp_totalsize;
+ u32 pp_num; /* used pingpong memory number */
+ img_buf_t img_buf[4];
+ enum camif_codec_fmt fmt;
+ enum camif_capturing exec;
+ camif_perf_t perf;
+ u32 now_frame_num;
+ u32 auto_restart; /* Only For Preview */
+} camif_cfg_t;
+
+#ifdef SW_DEBUG
+#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+
+#ifdef SW_DEBUG
+#define assert(expr) \
+ if(!(expr)) { \
+ printk( "Assertion failed! %s,%s,%s,line=%d\n", \
+ #expr,__FILE__,__FUNCTION__,__LINE__); \
+ }
+#else
+#define assert(expr)
+#endif
+
+
+
+extern int camif_capture_start(camif_cfg_t *);
+extern int camif_capture_stop(camif_cfg_t *);
+extern int camif_g_frame_num(camif_cfg_t *);
+extern u8 * camif_g_frame(camif_cfg_t *);
+extern int camif_win_offset(camif_gc_t *);
+extern void camif_hw_open(camif_gc_t *);
+extern void camif_hw_close(camif_cfg_t *);
+extern int camif_dynamic_open(camif_cfg_t *);
+extern int camif_dynamic_close(camif_cfg_t *);
+extern void camif_reset(int,int);
+extern void camif_setup_sensor(void);
+extern int camif_g_fifo_status(camif_cfg_t *);
+extern void camif_last_irq_en(camif_cfg_t *);
+extern void camif_change_flip(camif_cfg_t *);
+
+
+/* Todo
+ * API Interface function to both Character and V4L2 Drivers
+ */
+extern int camif_do_write(struct file *,const char *, size_t, loff_t *);
+extern int camif_do_ioctl(struct inode *, struct file *,unsigned int, void *);
+
+
+/*
+ * API for Decoder (S5x532, OV7620..)
+ */
+void camif_register_decoder(struct i2c_client *);
+void camif_unregister_decoder(struct i2c_client*);
+
+
+
+/* API for FSM */
+#define INSTANT_SKIP 0
+#define INSTANT_GO 1
+
+extern ssize_t camif_p_1fsm_start(camif_cfg_t *);
+extern ssize_t camif_p_2fsm_start(camif_cfg_t *);
+extern ssize_t camif_4fsm_start(camif_cfg_t *);
+extern ssize_t camif_p_stop(camif_cfg_t *);
+extern int camif_enter_p_4fsm(camif_cfg_t *);
+extern int camif_enter_c_4fsm(camif_cfg_t *);
+extern int camif_enter_2fsm(camif_cfg_t *);
+extern int camif_enter_1fsm(camif_cfg_t *);
+extern int camif_check_preview(camif_cfg_t *);
+extern int camif_callback_start(camif_cfg_t *);
+extern int camif_clock_init(camif_gc_t *);
+
+/*
+ * V4L2 Part
+ */
+#define VID_HARDWARE_SAMSUNG_FIMC20 236
+
+
+
+
+
+#endif
+
+
+/*
+ * Local variables:
+ * tab-width: 8
+ * c-indent-level: 8
+ * c-basic-offset: 8
+ * c-set-style: "K&R"
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/cam_reg.h
@@ -0,0 +1,234 @@
+ /*----------------------------------------------------------
+ * (C) 2004 Samsung Electronics
+ * SW.LEE < hitchcar@samsung.com>
+ *
+ ----------------------------------------------------------- */
+
+#ifndef __FIMC20_CAMERA_H__
+#define __FIMC20_CAMERA_H__
+
+extern u32 * camregs;
+
+#ifdef CONFIG_ARCH_S3C24A0
+#define CAM_BASE_ADD 0x48000000
+#else /* S3C2440A */
+#define CAM_BASE_ADD 0x4F000000
+#endif
+
+#if ! defined(FExtr)
+#define UData(Data) ((unsigned long) (Data))
+#define FExtr(Data, Field) \
+ ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+#define FInsrt(Value, Field) \
+ (UData (Value) << FShft (Field))
+#define FSize(Field) ((Field) >> 16)
+#define FShft(Field) ((Field) & 0x0000FFFF)
+#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field) (UData (1) << FShft (Field))
+#define Fld(Size, Shft) (((Size) << 16) + (Shft))
+#endif
+
+/*
+ * CAMERA IP
+ * P-port is used as RGB Capturing device which including scale and crop
+ * those who want to see(preview ) the image on display needs RGB image.
+ *
+ * C-port is used as YCbCr(4:2:0, 4:2:2) Capturing device which including the scale and crop
+ * the prefix of C-port have the meaning of "Codec" ex. mpeg4, h263.. which requries the
+ YCBCB format not RGB
+ */
+
+#define S3C2440_CAM_REG_CISRCFMT (0x00) // RW Input Source Format
+#define S3C2440_CAM_REG_CIWDOFST (0x04) // Window offset register
+#define S3C2440_CAM_REG_CIGCTRL (0x08) // Global control register
+#define S3C2440_CAM_REG_CICOYSA0 (0x18) // Y 1 st frame start ads
+#define S3C2440_CAM_REG_CICOYSA1 (0x1C) // Y 2 nd frame start ads
+#define S3C2440_CAM_REG_CICOYSA2 (0x20) // Y 3 rd frame start ads
+#define S3C2440_CAM_REG_CICOYSA3 (0x24) // Y 4 th frame start ads
+#define S3C2440_CAM_REG_CICOCBSA0 (0x28) // Cb 1 st frame start ads
+#define S3C2440_CAM_REG_CICOCBSA1 (0x2C) // Cb 2 nd frame start ads
+#define S3C2440_CAM_REG_CICOCBSA2 (0x30) // Cb 3 rd frame start ads
+#define S3C2440_CAM_REG_CICOCBSA3 (0x34) // Cb 4 th frame start ads
+#define S3C2440_CAM_REG_CICOCRSA0 (0x38) // Cr 1 st frame start ads
+#define S3C2440_CAM_REG_CICOCRSA1 (0x3C) // Cr 2 nd frame start ads
+#define S3C2440_CAM_REG_CICOCRSA2 (0x40) // Cr 3 rd frame start ads
+#define S3C2440_CAM_REG_CICOCRSA3 (0x44) // Cr 4 th frame start ads
+#define S3C2440_CAM_REG_CICOTRGFMT (0x48) // Target img format of codec
+#define S3C2440_CAM_REG_CICOCTRL (0x4C) // Codec DMA control related
+#define S3C2440_CAM_REG_CICOSCPRERATIO (0x50) // Codec pre-scaler ratio
+#define S3C2440_CAM_REG_CICOSCPREDST (0x54) // Codec pre-scaler dest
+#define S3C2440_CAM_REG_CICOSCCTRL (0x58) // Codec main-scaler control
+#define S3C2440_CAM_REG_CICOTAREA (0x5C) // Codec pre-scaler dest
+#define S3C2440_CAM_REG_CICOSTATUS (0x64) // Codec path status
+#define S3C2440_CAM_REG_CIPRCLRSA0 (0x6C) // RGB 1 st frame start ads
+#define S3C2440_CAM_REG_CIPRCLRSA1 (0x70) // RGB 2 nd frame start ads
+#define S3C2440_CAM_REG_CIPRCLRSA2 (0x74) // RGB 3 rd frame start ads
+#define S3C2440_CAM_REG_CIPRCLRSA3 (0x78) // RGB 4 th frame start ads
+#define S3C2440_CAM_REG_CIPRTRGFMT (0x7C) // Target img fmt of preview
+#define S3C2440_CAM_REG_CIPRCTRL (0x80) // Preview DMA ctl related
+#define S3C2440_CAM_REG_CIPRSCPRERATIO (0x84) // Preview pre-scaler ratio
+#define S3C2440_CAM_REG_CIPRSCPREDST (0x88) // Preview pre-scaler dest
+#define S3C2440_CAM_REG_CIPRSCCTRL (0x8C) // Preview main-scaler ctl
+#define S3C2440_CAM_REG_CIPRTAREA (0x90) // Preview pre-scaler dest
+#define S3C2440_CAM_REG_CIPRSTATUS (0x98) // Preview path status
+#define S3C2440_CAM_REG_CIIMGCPT (0xA0) // Image capture enable cmd
+
+#define S3C2440_CAM_REG_CICOYSA(__x) (0x18 + (__x)*4 )
+#define S3C2440_CAM_REG_CICOCBSA(__x) (0x28 + (__x)*4 )
+#define S3C2440_CAM_REG_CICOCRSA(__x) (0x38 + (__x)*4 )
+#define S3C2440_CAM_REG_CIPRCLRSA(__x) (0x6C + (__x)*4 )
+
+/* CISRCFMT BitField */
+#define SRCFMT_ITU601 BIT31
+#define SRCFMT_ITU656 0
+#define SRCFMT_UVOFFSET_128 BIT30
+#define fCAM_SIZE_H Fld(13, 16)
+#define fCAM_SIZE_V Fld(13, 0)
+#define SOURCE_HSIZE(x) FInsrt((x), fCAM_SIZE_H)
+#define SOURCE_VSIZE(x) FInsrt((x), fCAM_SIZE_V)
+
+
+/* Window Option Register */
+#define WINOFEN BIT31
+#define CO_FIFO_Y BIT30
+#define CO_FIFO_CB BIT15
+#define CO_FIFO_CR BIT14
+#define PR_FIFO_CB BIT13
+#define PR_FIFO_CR BIT12
+#define fWINHOR Fld(11, 16)
+#define fWINVER Fld(11, 0)
+#define WINHOROFST(x) FInsrt((x), fWINHOR)
+#define WINVEROFST(x) FInsrt((x), fWINVER)
+
+/* Global Control Register */
+#define GC_SWRST BIT31
+#define GC_CAMRST BIT30
+#define GC_INVPOLPCLK BIT26
+#define GC_INVPOLVSYNC BIT25
+#define GC_INVPOLHREF BIT24
+
+/*--------------------------------------------------
+ REGISTER BIT FIELD DEFINITION TO
+ YCBCR and RGB
+----------------------------------------------------*/
+/* Codec Target Format Register */
+#define IN_YCBCR420 0
+#define IN_YCBCR422 BIT31
+#define OUT_YCBCR420 0
+#define OUT_YCBCR422 BIT30
+
+#if 0
+#define FLIP_NORMAL 0
+#define FLIP_X (BIT14)
+#define FLIP_Y (BIT15)
+#define FLIP_MIRROR (BIT14|BIT15)
+#endif
+
+/** BEGIN ************************************/
+/* Cotents: Common in both P and C port */
+#define fTARGET_HSIZE Fld(13,16)
+#define TARGET_HSIZE(x) FInsrt((x), fTARGET_HSIZE)
+#define fTARGET_VSIZE Fld(13,0)
+#define TARGET_VSIZE(x) FInsrt((x), fTARGET_VSIZE)
+#define FLIP_X_MIRROR BIT14
+#define FLIP_Y_MIRROR BIT15
+#define FLIP_180_MIRROR (BIT14 | BIT15)
+/** END *************************************/
+
+/* Codec DMA Control Register */
+#define fYBURST_M Fld(5,19)
+#define fYBURST_R Fld(5,14)
+#define fCBURST_M Fld(5,9)
+#define fCBURST_R Fld(5,4)
+#define YBURST_M(x) FInsrt((x), fYBURST_M)
+#define CBURST_M(x) FInsrt((x), fCBURST_M)
+#define YBURST_R(x) FInsrt((x), fYBURST_R)
+#define CBURST_R(x) FInsrt((x), fCBURST_R)
+#define LAST_IRQ_EN BIT2 /* Common in both P and C port */
+/*
+ * Check the done signal of capturing image for JPEG
+ * !!! AutoClear Bit
+ */
+
+
+/* (Codec, Preview ) Pre-Scaler Control Register 1 */
+#define fSHIFT Fld(4,28)
+#define PRE_SHIFT(x) FInsrt((x), fSHIFT)
+#define fRATIO_H Fld(7,16)
+#define PRE_HRATIO(x) FInsrt((x), fRATIO_H)
+#define fRATIO_V Fld(7,0)
+#define PRE_VRATIO(x) FInsrt((x), fRATIO_V)
+
+/* (Codec, Preview ) Pre-Scaler Control Register 2*/
+#define fDST_WIDTH Fld(12,16)
+#define fDST_HEIGHT Fld(12,0)
+#define PRE_DST_WIDTH(x) FInsrt((x), fDST_WIDTH)
+#define PRE_DST_HEIGHT(x) FInsrt((x), fDST_HEIGHT)
+
+
+/* (Codec, Preview) Main-scaler control Register */
+#define S_METHOD BIT31 /* Sampling method only for P-port */
+#define SCALERSTART BIT15
+/* Codec scaler bypass for upper 2048x2048
+ where ImgCptEn_CoSC and ImgCptEn_PrSC should be 0
+*/
+
+#define SCALERBYPASS BIT31
+#define RGB_FMT24 BIT30
+#define RGB_FMT16 0
+
+/*
+#define SCALE_UP_H BIT29
+#define SCALE_UP_V BIT28
+*/
+
+#define fMAIN_HRATIO Fld(9, 16)
+#define MAIN_HRATIO(x) FInsrt((x), fMAIN_HRATIO)
+
+#define SCALER_START BIT15
+
+#define fMAIN_VRATIO Fld(9, 0)
+#define MAIN_VRATIO(x) FInsrt((x), fMAIN_VRATIO)
+
+/* (Codec, Preview ) DMA Target AREA Register */
+#define fCICOTAREA Fld(26,0)
+#define TARGET_DMA_AREA(x) FInsrt((x), fCICOTAREA)
+
+/* Preview DMA Control Register */
+#define fRGBURST_M Fld(5,19)
+#define fRGBURST_R Fld(5,14)
+#define RGBURST_M(x) FInsrt((x), fRGBURST_M)
+#define RGBURST_R(x) FInsrt((x), fRGBURST_R)
+
+
+/* (Codec, Preview) Status Register */
+#define CO_OVERFLOW_Y BIT31
+#define CO_OVERFLOW_CB BIT30
+#define CO_OVERFLOW_CR BIT29
+#define PR_OVERFLOW_CB BIT31
+#define PR_OVERFLOW_CR BIT30
+
+#define VSYNC BIT28
+
+#define fFRAME_CNT Fld(2,26)
+#define FRAME_CNT(x) FExtr((x),fFRAME_CNT)
+
+#define WIN_OFF_EN BIT25
+#define fFLIP_MODE Fld(2,23)
+#define FLIP_MODE(x) EExtr((x), fFLIP_MODE)
+#define CAP_STATUS_CAMIF BIT22
+#define CAP_STATUS_CODEC BIT21
+#define CAP_STATUS_PREVIEW BIT21
+#define VSYNC_A BIT20
+#define VSYNC_B BIT19
+
+/* Image Capture Enable Regiser */
+#define CAMIF_CAP_ON BIT31
+#define CAMIF_CAP_CODEC_ON BIT30
+#define CAMIF_CAP_PREVIEW_ON BIT29
+
+
+
+
+#endif /* S3C2440_CAMER_H */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/imgsensor.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright (C) 2004 Samsung Electronics
+ * SW.LEE <hitchcar@samsung.com>
+ *
+ * Copyright (C) 2000 Russell King : pcf8583.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Driver for FIMC20 Camera Decoder
+ */
+
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+
+
+#ifdef CONFIG_ARCH_S3C24A0A
+#else
+//#include <asm/arch/S3C2440.h>
+#endif
+
+#define SW_DEBUG
+#define CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#include "camif.h"
+#include "sensor.h"
+
+#ifndef SAMSUNG_SXGA_CAM
+#include "s5x532_rev36.h"
+#else
+#include "sxga.h"
+#endif
+
+static struct i2c_driver s5x532_driver;
+static camif_gc_t data = {
+ itu_fmt: CAMIF_ITU601,
+ order422: CAMIF_YCBYCR,
+ camclk: 24000000,
+#ifndef SAMSUNG_SXGA_CAM
+ source_x: 640,
+ source_y: 480,
+ win_hor_ofst: 112,
+ win_ver_ofst: 20,
+#else
+ source_x: 1280,
+ source_y: 1024,
+ win_hor_ofst: 0,
+ win_ver_ofst: 0,
+#endif
+ polarity_pclk:1,
+ polarity_href:0,
+#ifdef CONFIG_ARCH_S3C24A0A
+ reset_type:CAMIF_EX_RESET_AL, /* Active Low */
+#else
+ reset_type:CAMIF_EX_RESET_AH, /* Ref board has inverted signal */
+#endif
+ reset_udelay:2000,
+};
+
+#define CAM_ID 0x5a
+
+static unsigned short ignore = I2C_CLIENT_END;
+static unsigned short normal_addr[] = { (CAM_ID>>1), I2C_CLIENT_END };
+static struct i2c_client_address_data addr_data = {
+ normal_i2c: normal_addr,
+ probe: &ignore,
+ ignore: &ignore,
+};
+
+s5x532_t s5x532_regs_mirror[S5X532_REGS];
+
+unsigned char
+s5x532_read(struct i2c_client *client, unsigned char subaddr)
+{
+ int ret;
+ unsigned char buf[1];
+ struct i2c_msg msg ={ client->addr, 0, 1, buf};
+ buf[0] = subaddr;
+
+ ret = i2c_transfer(client->adapter,&msg, 1) == 1 ? 0 : -EIO;
+ if (ret == -EIO) {
+ printk(" I2C write Error \n");
+ return -EIO;
+ }
+
+ msg.flags = I2C_M_RD;
+ ret = i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
+
+ return buf[0];
+}
+
+
+static int
+s5x532_write(struct i2c_client *client,
+ unsigned char subaddr, unsigned char val)
+{
+ unsigned char buf[2];
+ struct i2c_msg msg = { client->addr, 0, 2, buf};
+
+ buf[0]= subaddr;
+ buf[1]= val;
+
+ return i2c_transfer(client->adapter, &msg, 1) == 1 ? 0 : -EIO;
+}
+
+void inline s5x532_init(struct i2c_client *sam_client)
+{
+ int i;
+
+ printk(KERN_ERR "s5x532_init \n");
+ for (i = 0; i < S5X532_INIT_REGS; i++) {
+ s5x532_write(sam_client,
+ s5x532_reg[i].subaddr, s5x532_reg[i].value );
+ }
+
+#ifdef YOU_WANT_TO_CHECK_IMG_SENSOR
+ for (i = 0; i < S5X532_INIT_REGS;i++) {
+ if ( s5x532_reg[i].subaddr == PAGE_ADDRESS ) {
+ s5x532_write(sam_client,
+ s5x532_reg[i].subaddr, s5x532_reg[i].value);
+
+ printk(KERN_ERR "Page: Subaddr %02x = 0x%02x\n",
+ s5x532_reg[i].subaddr, s5x532_regs_mirror[i].value);
+
+
+ } else
+ {
+ s5x532_regs_mirror[i].subaddr = s5x532_reg[i].subaddr;
+ s5x532_regs_mirror[i].value =
+ s5x532_read(sam_client,s5x532_reg[i].subaddr);
+ printk(KERN_ERR "Subaddr %02x = 0x%02x\n",
+ s5x532_reg[i].subaddr, s5x532_regs_mirror[i].value);
+ }
+ }
+#endif
+
+}
+
+static int
+s5x532_attach(struct i2c_adapter *adap, int addr, int kind)
+{
+ struct i2c_client *c;
+
+ c = kmalloc(sizeof(*c), GFP_KERNEL);
+ if (!c) return -ENOMEM;
+
+ strcpy(c->name, "S5X532");
+// c->id = s5x532_driver.id;
+ c->flags = 0 /* I2C_CLIENT_ALLOW_USE */;
+ c->addr = addr;
+ c->adapter = adap;
+ c->driver = &s5x532_driver;
+ data.sensor = c;
+ i2c_set_clientdata(c, &data);
+
+ camif_register_decoder(c);
+ return i2c_attach_client(c);
+}
+
+static int s5x532_probe(struct i2c_adapter *adap)
+{
+ return i2c_probe(adap, &addr_data, s5x532_attach);
+}
+
+static int s5x532_detach(struct i2c_client *client)
+{
+ i2c_detach_client(client);
+ camif_unregister_decoder(client);
+ return 0;
+}
+
+static int
+s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
+{
+ switch (cmd) {
+ case SENSOR_INIT:
+ s5x532_init(client);
+ printk(KERN_INFO "CAMERA: S5X532 Sensor initialized\n");
+ break;
+ case USER_ADD:
+ /* MOD_INC_USE_COUNT; uh.. 2.6 deals with this, old-timer */
+ break;
+ case USER_EXIT:
+ /* MOD_DEC_USE_COUNT; */
+ break;
+/* Todo
+ case SENSOR_BRIGHTNESS:
+ change_sensor();
+ break;
+*/
+ default:
+ panic("Unexpect Sensor Command \n");
+ break;
+ }
+ return 0;
+}
+
+static struct i2c_driver s5x532_driver = {
+ driver: { name: "S5X532" },
+ id: 0, /* optional in i2c-id.h I2C_ALGO_S3C, */
+ attach_adapter: s5x532_probe,
+ detach_client: s5x532_detach,
+ command: s5x532_command
+};
+
+static void iic_gpio_port(void)
+{
+/* FIXME: no gpio config for i2c !!!
+#ifdef CONFIG_ARCH_S3C24A0A
+#else
+ GPECON &= ~(0xf <<28);
+ GPECON |= 0xa <<28;
+#endif
+*/
+}
+
+static __init int camif_sensor_init(void)
+{
+ iic_gpio_port();
+ return i2c_add_driver(&s5x532_driver);
+}
+
+
+static __init void camif_sensor_exit(void)
+{
+ i2c_del_driver(&s5x532_driver);
+}
+
+module_init(camif_sensor_init)
+module_exit(camif_sensor_exit)
+
+MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
+MODULE_DESCRIPTION("I2C Client Driver For Fimc2.0 MISC Driver");
+MODULE_LICENSE("GPL");
+
+
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/Kconfig
@@ -0,0 +1,7 @@
+
+config S3C2440_CAMERA
+ bool "S3C24xx Camera interface"
+ depends on ARCH_S3C2410
+ help
+ Camera driver for S3C2440 camera unit
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_S3C2440_CAMERA) += \
+ videodev.o \
+ imgsensor.o \
+ video-driver.o \
+ camif.o \
+ camif_fsm.o \
+ qt-driver.o
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/miscdevice.h
@@ -0,0 +1,18 @@
+
+ /*----------------------------------------------------------
+ * (C) 2004 Samsung Electronics
+ * SW.LEE < hitchcar@samsung.com>
+ *
+ ----------------------------------------------------------- */
+
+#ifndef _LINUX_S3C_MISCDEVICE_H
+#define _LINUX_S3C_MISCDEVICE_H
+
+#define CODEC_MINOR 212
+#define PREVIEW_MINOR 213
+
+
+
+
+
+#endif
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/qt-driver.c
@@ -0,0 +1,172 @@
+/*
+ * SW.LEE <hitchcar@samsung.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/irq.h>
+#include <asm/semaphore.h>
+#include <linux/miscdevice.h>
+
+//#define SW_DEBUG
+
+#define CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#include "camif.h"
+#include "miscdevice.h"
+#include "cam_reg.h"
+#include "sensor.h"
+#include "userapp.h"
+
+extern camif_cfg_t * get_camif(int nr);
+
+
+/************************* Sharp Zarus API **************************
+* refering to Camera Driver API for SL-5000D/SL-5600 revision 1.00
+* April 11, 2002.
+ SW.LEE <hitchcar@sec.samsung.com>
+ I want to use Sharp Camera Application.
+*
+*/
+
+#define READ_MODE_STATUS 0x1
+#define READ_MODE_IMAGE 0x0
+#define CAPTURE_SPEED
+#define H_FLIP
+#define V_FLIP
+typedef enum sharp_readmode
+{
+ IMAGE = 0, STATUS = 1,
+ FASTER = 0, BETTER = 2,
+ XNOFLIP = 0, XFLIP = 4,
+ YNOFLIP = 0, YFLIP = 8,
+ AUTOMATICFLIP = -1
+} ReadMode_t;
+
+
+static struct sharp_param_t {
+ ReadMode_t readMode;
+ char CameraStatus[4];
+} sharp_param = { STATUS, {'s','m','c','A'}};
+
+
+camif_param_t qt_parm = { 640,480,240,320,16,0};
+
+static void setReadMode(const char *b,size_t count)
+{
+ int i = *(b+2) - 48 ;
+ if ( 4 == count ) {
+ i = (*(b+3) - 48) + i * 10;
+ }
+
+ // DPRINTK(" setReadMode %s conversion value %d \n",b , i);
+ if ( i & STATUS ) {
+ // DPRINTK(" STATUS MODE \n");
+ sharp_param.readMode = i;
+ }
+ else {
+ // DPRINTK(" IMAGE MODE \n");
+ sharp_param.readMode = i;
+ }
+}
+
+
+
+
+extern ssize_t camif_p_read(struct file *, char *, size_t , loff_t *);
+
+ssize_t z_read(struct file *f, char *buf, size_t count, loff_t *pos)
+{
+ size_t end;
+
+ if (sharp_param.readMode & STATUS ) {
+ buf[0] = sharp_param.CameraStatus[0];
+ buf[1] = sharp_param.CameraStatus[1];
+ buf[2] = sharp_param.CameraStatus[2];
+ buf[3] = sharp_param.CameraStatus[3];
+ end = 4;
+ return end;
+ }
+ else { /* Image ReadMode */
+ /*
+ if (( sharp_param.readMode & (BETTER|X FLIP|YFLIP)))
+ DPRINTK(" Not Supporting BETTER|XFLIP|YFLIP\n");
+ */
+ return camif_p_read(f,buf,count,pos);
+ }
+}
+
+static void z_config(camif_cfg_t *cfg,int x, int y)
+{
+ cfg->target_x = x;
+ cfg->target_y = y;
+ cfg->fmt = CAMIF_RGB16;
+ if (camif_dynamic_open(cfg)) {
+ panic(" Eror Happens \n");
+ }
+}
+
+
+ssize_t z_write(struct file *f, const char *b, size_t c, loff_t *pos)
+{
+ int array[5];
+ int zoom = 1;
+ camif_cfg_t *cfg;
+
+ cfg = get_camif(MINOR(f->f_dentry->d_inode->i_rdev));
+// DPRINTK(" param %s count %d \n",b, c );
+
+ switch(*b) {
+ case 'M':
+ setReadMode(b, c);
+ break;
+ case 'B': /* Clear the latch flag of shutter button */
+ DPRINTK(" clear latch flag of camera's shutter button\n");
+ sharp_param.CameraStatus[0]='s';
+ break;
+ case 'Y': /* I don't know how to set Shutter pressed */
+ DPRINTK(" set latch flag n");
+ sharp_param.CameraStatus[0]='S';
+ break;
+ case 'S': /* Camera Image Resolution */
+ case 'R': /* Donot support Rotation */
+ DPRINTK(" param %s count %d \n",b, c );
+ get_options((char *)(b+2), 5, array);
+ if ( array[3] == 512 ) zoom = 2;
+ z_config(cfg, array[1] * zoom , array[2] * zoom );
+ camif_4fsm_start(cfg);
+ break;
+ case 'C':
+ DPRINTK(" param %s count %d \n",b, c );
+ DPRINTK(" Start the camera to capture \n");
+ sharp_param.CameraStatus[2]='C';
+ camif_4fsm_start(cfg);
+ break;
+ default:
+ printk("Unexpected param %s count %d \n",b, c );
+ }
+
+ return c;
+}
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/qt.h
@@ -0,0 +1,18 @@
+/*
+ * SW.LEE <hitchcar@samsung.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __Z_API_H_
+#define __Z_API_H_
+
+extern ssize_t z_read(struct file *f, char *buf, size_t count, loff_t *pos);
+extern ssize_t z_write(struct file *f, const char *b, size_t c, loff_t *pos);
+
+
+
+#endif
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/s5x532.h
@@ -0,0 +1,143 @@
+/*
+ * 2004 (C) Samsung Electronics
+ * SW.LEE <hitchcar@sec.samsung.com>
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+
+#ifndef _SMDK2440_S5X532_H_
+#define _SMDK2440_S5X532_H_
+
+
+#define CHIP_DELAY 0xFF
+
+typedef struct samsung_t{
+ unsigned char subaddr;
+ unsigned char value;
+ unsigned char page;
+} s5x532_t;
+
+s5x532_t s5x532_reg[] = {
+ // page 5
+ {0xec,0x05},
+ {0x08,0x55,0x5},
+ {0x0a,0x75,0x5},
+ {0x0c,0x90,0x5},
+ {0x0e,0x18,0x5},
+ {0x12,0x09,0x5},
+ {0x14,0x9d,0x5},
+ {0x16,0x90,0x5},
+ {0x1a,0x18,0x5},
+ {0x1c,0x0c,0x5},
+ {0x1e,0x09,0x5},
+ {0x20,0x06,0x5},
+ {0x22,0x20,0x5},
+ {0x2a,0x00,0x5},
+ {0x2d,0x04,0x5},
+ {0x12,0x24,0x5},
+ // page 3
+ {0xec,0x03,0x3},
+ {0x0c,0x09,0x3},
+ {0x6c,0x09,0x3},
+ {0x2b,0x10,0x3}, // momo clock inversion
+ // page 2
+ {0xec,0x02,0x2},
+ {0x03,0x09,0x2},
+ {0x05,0x08,0x2},
+ {0x06,0x01,0x2},
+ {0x07,0xf8,0x2},
+ {0x15,0x25,0x2},
+ {0x30,0x29,0x2},
+ {0x36,0x12,0x2},
+ {0x38,0x04,0x2},
+ {0x1b,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
+ {0x1c,0x77,0x2}, // 24MHz : 0x77, 12MHz : 0x22
+ // page 1
+ {0xec,0x01,0x1},
+ {0x00,0x03,0x1}, //
+ {0x0a,0x08,0x1}, // 0x0-QQVGA, 0x06-CIF, 0x02-QCIF, 0x08-VGA, 0x04-QVGA, 0x0a-SXGA
+ {0x0c,0x00,0x1}, // Pattern selectio. 0-CIS, 1-Color bar, 2-Ramp, 3-Blue screen
+ {0x10,0x27,0x1},
+ // 0x21-ITU-R656(CrYCbY), 0x25-ITU-R601(CrYCbY), 0x26-ITU-R601(YCbYCr)
+ {0x50,0x21,0x1}, // Hblank
+ {0x51,0x00,0x1}, // Hblank
+ {0x52,0xA1,0x1}, // Hblank
+ {0x53,0x02,0x1}, // Hblank
+ {0x54,0x01,0x1}, // Vblank
+ {0x55,0x00,0x1}, // Vblank
+ {0x56,0xE1,0x1}, // Vblank
+ {0x57,0x01,0x1}, // Vblank
+ {0x58,0x21,0x1}, // Hsync
+ {0x59,0x00,0x1}, // Hsync
+ {0x5a,0xA1,0x1}, // Hsync
+ {0x5b,0x02,0x1}, // Hsync
+ {0x5c,0x03,0x1}, // Vref
+ {0x5d,0x00,0x1}, // Vref
+ {0x5e,0x05,0x1}, // Vref
+ {0x5f,0x00,0x1}, // Vref
+ {0x70,0x0E,0x1},
+ {0x71,0xD6,0x1},
+ {0x72,0x30,0x1},
+ {0x73,0xDB,0x1},
+ {0x74,0x0E,0x1},
+ {0x75,0xD6,0x1},
+ {0x76,0x18,0x1},
+ {0x77,0xF5,0x1},
+ {0x78,0x0E,0x1},
+ {0x79,0xD6,0x1},
+ {0x7a,0x28,0x1},
+ {0x7b,0xE6,0x1},
+ {0x50,0x00,0x1},
+ {0x5c,0x00,0x1},
+
+ // page 0
+ {0xec,0x00,0x0},
+ {0x79,0x01,0x0},
+ {0x58,0x90,0x0},
+ {0x59,0xA0,0x0},
+ {0x5a,0x50,0x0},
+ {0x5b,0x70,0x0},
+ {0x5c,0xD0,0x0},
+ {0x5d,0xC0,0x0},
+ {0x5e,0x28,0x0},
+ {0x5f,0x08,0x0},
+ {0x50,0x90,0x0},
+ {0x51,0xA0,0x0},
+ {0x52,0x50,0x0},
+ {0x53,0x70,0x0},
+ {0x54,0xD0,0x0},
+ {0x55,0xC0,0x0},
+ {0x56,0x28,0x0},
+ {0x57,0x00,0x0},
+ {0x48,0x90,0x0},
+ {0x49,0xA0,0x0},
+ {0x4a,0x50,0x0},
+ {0x4b,0x70,0x0},
+ {0x4c,0xD0,0x0},
+ {0x4d,0xC0,0x0},
+ {0x4e,0x28,0x0},
+ {0x4f,0x08,0x0},
+ {0x72,0x82,0x0}, // main clock = 24MHz:0xd2, 16M:0x82, 12M:0x54
+ {0x75,0x05,0x0} // absolute vertical mirror. junon
+
+};
+
+
+#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
+#define S5X532_RISC_REGS 0xEB
+#define S5X532_ISP_REGS 0xFB /* S5C7323X */
+#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
+
+
+#define PAGE_ADDRESS 0xEC
+
+//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
+#define S5X532_REGS (0x1000)
+
+
+
+#endif
+
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/s5x532_rev36.h
@@ -0,0 +1,208 @@
+/*
+ * 2004 (C) Samsung Electronics
+ * SW.LEE <hitchcar@sec.samsung.com>
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+
+#ifndef _SMDK2440_S5X532_H_
+#define _SMDK2440_S5X532_H_
+
+
+#define CHIP_DELAY 0xFF
+
+typedef struct samsung_t{
+ unsigned char subaddr;
+ unsigned char value;
+ unsigned char page;
+} s5x532_t;
+
+s5x532_t s5x532_reg[] = {
+
+ //=============== page0 ===============//
+ {0xec,0x00,0x00},
+ {0x02,0x00,0x00},
+ {0x14,0x60,0x00},
+ {0x15,0x60,0x00},
+ {0x16,0x60,0x00},
+ {0x1b,0x20,0x00},
+ {0x1c,0x20,0x00},
+ {0x1d,0x20,0x00},
+ {0x1e,0x20,0x00},
+ {0x72,0xdc,0x00},
+ {0x73,0x11,0x00},
+ {0x76,0x82,0x00},
+ {0x77,0x90,0x00},
+ {0x78,0x6c,0x00},
+ {0x0a,0x02,0x00},
+ {0x34,0x0d,0x00},
+ {0x35,0x0a,0x00},
+ {0x36,0x05,0x00},
+ {0x37,0x05,0x00},
+ {0x38,0x06,0x00},
+ {0x39,0x08,0x00},
+ {0x3A,0x0d,0x00},
+ {0x3B,0x0d,0x00},
+ {0x3C,0x18,0x00},
+ {0x3D,0xE0,0x00},
+ {0x3E,0x20,0x00},
+ {0x66,0x02,0x00},
+ {0x6c,0x40,0x00},
+ {0x7c,0x01,0x00},
+ {0x0D,0x24,0x00},
+ {0x40,0x1B,0x00},
+ {0x41,0x4F,0x00},
+ {0x42,0x24,0x00},
+ {0x43,0x3E,0x00},
+ {0x44,0x32,0x00},
+ {0x45,0x30,0x00},
+ {0x48,0xa0,0x00},
+ {0x49,0xd0,0x00},
+ {0x4A,0x28,0x00},
+ {0x4B,0x7d,0x00},
+ {0x4C,0xd0,0x00},
+ {0x4D,0xe0,0x00},
+ {0x4E,0x1a,0x00},
+ {0x4F,0xa0,0x00},
+ {0x50,0xc0,0x00},
+ {0x51,0xc0,0x00},
+ {0x52,0x42,0x00},
+ {0x53,0x7e,0x00},
+ {0x54,0xc0,0x00},
+ {0x55,0xf0,0x00},
+ {0x56,0x1e,0x00},
+ {0x57,0xe0,0x00},
+ {0x58,0xc0,0x00},
+ {0x59,0xa0,0x00},
+ {0x5A,0x4a,0x00},
+ {0x5B,0x7e,0x00},
+ {0x5C,0xc0,0x00},
+ {0x5D,0xf0,0x00},
+ {0x5E,0x2a,0x00},
+ {0x5F,0x10,0x00},
+ {0x79,0x00,0x00},
+ {0x7a,0x00,0x00},
+ {0xe0,0x0f,0x00},
+ {0xe3,0x14,0x00},
+ {0xe5,0x48,0x00},
+ {0xe7,0x58,0x00},
+
+ //=============== page1 ===============//
+ {0xec,0x01,0x01},
+ {0x10,0x05,0x01},
+ {0x20,0xde,0x01},
+ {0x0b,0x06,0x01},
+ {0x30,0x00,0x01},
+ {0x31,0x00,0x01},
+ {0x32,0x00,0x01},
+ {0x24,0x28,0x01},
+ {0x25,0x3F,0x01},
+ {0x26,0x65,0x01},
+ {0x27,0xA1,0x01},
+ {0x28,0xFF,0x01},
+ {0x29,0x96,0x01},
+ {0x2A,0x85,0x01},
+ {0x2B,0xFF,0x01},
+ {0x2C,0x00,0x01},
+ {0x2D,0x1B,0x01},
+ {0xB0,0x28,0x01},
+ {0xB1,0x3F,0x01},
+ {0xB2,0x65,0x01},
+ {0xB3,0xA1,0x01},
+ {0xB4,0xFF,0x01},
+ {0xB5,0x96,0x01},
+ {0xB6,0x85,0x01},
+ {0xB7,0xFF,0x01},
+ {0xB8,0x00,0x01},
+ {0xB9,0x1B,0x01},
+ {0x15,0x15,0x01},
+ {0x18,0x85,0x01},
+ {0x1f,0x05,0x01},
+ {0x87,0x40,0x01},
+ {0x37,0x60,0x01},
+ {0x38,0xd5,0x01},
+ {0x48,0xa0,0x01},
+ {0x61,0x54,0x01},
+ {0x62,0x54,0x01},
+ {0x63,0x14,0x01},
+ {0x64,0x14,0x01},
+ {0x6d,0x12,0x01},
+ {0x78,0x09,0x01},
+ {0x79,0xD7,0x01},
+ {0x7A,0x14,0x01},
+ {0x7B,0xEE,0x01},
+
+ //=============== page2 ===============//
+ {0xec,0x02,0x02},
+ {0x2c,0x76,0x02},
+ {0x25,0x25,0x02},
+ {0x27,0x27,0x02},
+ {0x30,0x29,0x02},
+ {0x36,0x08,0x02},
+ {0x38,0x04,0x02},
+
+ //=============== page3 ===============//
+ {0xec,0x03,0x03},
+ {0x08,0x00,0x03},
+ {0x09,0x33,0x03},
+
+ //=============== page4 ===============//
+ {0xec,0x04,0x04},
+ {0x00,0x21,0x04},
+ {0x01,0x00,0x04},
+ {0x02,0x9d,0x04},
+ {0x03,0x02,0x04},
+ {0x04,0x04,0x04},
+ {0x05,0x00,0x04},
+ {0x06,0x1f,0x04},
+ {0x07,0x02,0x04},
+ {0x08,0x21,0x04},
+ {0x09,0x00,0x04},
+ {0x0a,0x9d,0x04},
+ {0x0b,0x02,0x04},
+ {0x0c,0x04,0x04},
+ {0x0d,0x00,0x04},
+ {0x0e,0x20,0x04},
+ {0x0f,0x02,0x04},
+ {0x1b,0x3c,0x04},
+ {0x1c,0x3c,0x04},
+
+ //=============== page5 ===============//
+ {0xec,0x05,0x05},
+ {0x1f,0x00,0x05},
+ {0x08,0x59,0x05},
+ {0x0a,0x71,0x05},
+ {0x1e,0x23,0x05},
+ {0x0e,0x3c,0x05},
+
+ //=============== page7 ===============//
+ {0xec,0x07,0x07},
+ {0x11,0xfe,0x07},
+
+ // added by junon
+ {0xec,0x01,0x07},
+ {0x10,0x26,0x07},
+ // 0x21-ITU-R656(CbYCrY), 0x25-ITU-R601(CbYCrY), 0x26-ITU-R601(YCrYCb)
+
+
+};
+
+
+#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
+#define S5X532_RISC_REGS 0xEB
+#define S5X532_ISP_REGS 0xFB /* S5C7323X */
+#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
+
+
+#define PAGE_ADDRESS 0xEC
+
+//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
+#define S5X532_REGS (0x1000)
+
+
+
+#endif
+
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/sensor.h
@@ -0,0 +1,20 @@
+/*
+ *
+ * Copyright (C) 2004 Samsung Electronics
+ * SW.LEE <hitchcar@sec.samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SENSOR_CMD_H_
+#define __SENSOR_CMD_H_
+
+#include "bits.h"
+
+#define SENSOR_INIT BIT0
+#define USER_ADD BIT1
+#define USER_EXIT BIT2
+
+#endif
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/sxga.h
@@ -0,0 +1,504 @@
+/*
+ * 2004 (C) Samsung Electronics
+ * SW.LEE <hitchcar@sec.samsung.com>
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+
+#ifndef _SAMSUNG_SXGA_H_
+#define _SAMSUNG_SXGA_H_
+
+
+#define CHIP_DELAY 0xFF
+
+typedef struct samsung_t{
+ unsigned char subaddr;
+ unsigned char value;
+ unsigned char page;
+} s5x532_t;
+
+s5x532_t s5x532_reg[] = {
+ // page 0
+ {0xec,0x00,0x0},
+ {0x0c,0x38,0x0},
+ {0x0d,0x24,0x0},
+ {0x13,0x10,0x0},
+ {0x14,0x10,0x0},
+ {0x15,0x10,0x0},
+ {0x16,0x10,0x0},
+ {0x17,0x20,0x0},
+ {0x18,0x30,0x0},
+ {0x19,0x30,0x0},
+ {0x1a,0x10,0x0},
+ {0x1b,0x10,0x0},
+
+ {0x2d,0x40,0x0},
+ {0x3e,0x10,0x0},
+ {0x34,0x0a,0x0},
+ {0x39,0x04,0x0},
+ {0x3a,0x02,0x0},
+ {0x31,0x05,0x0},
+
+ {0x40,0x1d,0x0},
+ {0x41,0x50,0x0},
+ {0x42,0x24,0x0},
+ {0x43,0x3f,0x0},
+ {0x44,0x30,0x0},
+ {0x45,0x31,0x0},
+
+ {0x48,0xa0,0x0},
+ {0x49,0xc0,0x0},
+ {0x4a,0x58,0x0},
+ {0x4b,0x50,0x0},
+ {0x4c,0xb0,0x0},
+ {0x4d,0xc0,0x0},
+ {0x4e,0x30,0x0},
+ {0x4f,0x20,0x0},
+
+ {0x50,0xa0,0x0},
+ {0x51,0xc0,0x0},
+ {0x52,0x50,0x0},
+ {0x53,0x60,0x0},
+ {0x54,0xb0,0x0},
+ {0x55,0xc0,0x0},
+ {0x56,0x20,0x0},
+ {0x57,0x08,0x0},
+// {0x72,0x50,0x0}, // Clock 16
+ {0x72,0x78,0x0}, // Clock 24Mhz
+// {0x72,0xf0,0x0}, // Clock 48Mhz
+ // page 1
+ {0xec,0x01,0x1},
+ {0x10,0x17,0x1}, // ITU-R601
+ /*
+ [3:2] : out_sel
+ 00 : 656
+ 01 : 601
+ 10 : RGB
+ 11 : CIS
+ [1] : YC_SEL
+ [0] : CBCR_SEL
+ */
+
+ {0x0b,0x06,0x1}, // 6
+ {0x20,0xa8,0x1}, //b0); // Highlight C Supp 040215
+ {0x22,0x26,0x1}, //2f); 040225
+
+ {0x24,0x08,0x1}, //00); //1F); 040226
+ {0x25,0x10,0x1}, //10); //34);
+ {0x26,0x40,0x1}, //56);
+ {0x27,0x80,0x1}, //8D);
+ {0x28,0x2c,0x1}, //E7);
+ {0x29,0xd6,0x1}, //7C);
+ {0x2A,0x0c,0x1}, //70);
+ {0x2B,0xFF,0x1}, //FF);
+ {0x2C,0x00,0x1}, //00);
+ {0x2D,0x5f,0x1}, //1B);
+ //
+ {0xB0,0x08,0x1}, //00); //1F); 040226
+ {0xB1,0x10,0x1}, //10); //34);50
+ {0xB2,0x40,0x1}, //36);
+ {0xB3,0x80,0x1}, //6D);
+ {0xB4,0x2c,0x1}, //b7);
+ {0xB5,0xd6,0x1}, //7C);
+ {0xB6,0x0c,0x1}, //70);
+ {0xB7,0xFF,0x1}, //FF);
+ {0xB8,0x00,0x1}, //00);
+ {0xB9,0x5f,0x1}, //1B);
+
+
+ {0xc2,0x01,0x1}, // shading On
+ {0xc3,0x80,0x1},
+ {0xc4,0x02,0x1},
+ {0xc5,0x00,0x1},
+ {0xc6,0x01,0x1},
+ {0xc7,0x00,0x1},
+ {0xc8,0x05,0x1},
+ {0xc9,0x00,0x1},
+ {0xca,0x04,0x1},
+
+ // shading 5
+ {0xd0,0xb5,0x1},
+ {0xd1,0x9c,0x1},
+ {0xd2,0x8d,0x1},
+ {0xd3,0x84,0x1},
+ {0xd4,0x84,0x1},
+ {0xd5,0x91,0x1},
+ {0xd6,0xa0,0x1},
+ {0xd7,0xb5,0x1},
+
+ {0xd8,0xc0,0x1},
+ {0xd9,0xa6,0x1},
+ {0xda,0x93,0x1},
+ {0xdb,0x85,0x1},
+ {0xdc,0x85,0x1},
+ {0xdd,0x90,0x1},
+ {0xde,0xa0,0x1},
+ {0xdf,0xb8,0x1},
+
+ // Page 2
+ {0xec,0x02,0x02},
+
+ {0x2d,0x02,0x02},
+ {0x20,0x13,0x02},
+ {0x21,0x13,0x2},
+ {0x22,0x13,0x2},
+ {0x23,0x13,0x2},
+ {0x2e,0x85,0x2},
+ {0x2f,0x34,0x2},
+ {0x30,0x00,0x2},
+ {0x28,0x94,0x2},
+
+
+ // page 3
+ {0xec,0x03,0x03},
+ {0x10,0x00,0x3},
+ {0x20,0x00,0x3},
+ {0x21,0x20,0x3},
+ {0x22,0x00,0x3},
+ {0x23,0x00,0x3},
+ {0x40,0x20,0x3},
+ {0x41,0x20,0x3},
+ {0x42,0x20,0x3},
+ {0x43,0x20,0x3},
+ {0x60,0x00,0x3},
+ {0x61,0x00,0x3},
+ {0x62,0x00,0x3},
+ {0x63,0x00,0x3},
+ {0x64,0x04,0x3},
+ {0x65,0x1C,0x3},
+ {0x66,0x05,0x3},
+ {0x67,0x1C,0x3},
+ {0x68,0x00,0x3},
+ {0x69,0x2D,0x3},
+ {0x6a,0x00,0x3},
+ {0x6b,0x72,0x3},
+ {0x6c,0x00,0x3},
+ {0x6d,0x00,0x3},
+ {0x6e,0x16,0x3}, // 2.38
+ {0x6f,0x16,0x3}, // 2.38
+ {0x70,0x00,0x3},
+ {0x71,0x00,0x3},
+ {0x72,0x45,0x3},
+ {0x73,0x00,0x3},
+ {0x74,0x1C,0x3},
+ {0x75,0x05,0x3},
+
+ {0x80,0x00,0x3}, //for 0.02 _ 44
+ {0x81,0x00,0x3},
+ {0x82,0x00,0x3},
+ {0x83,0x00,0x3},
+ {0x84,0x04,0x3},
+ {0x85,0x1c,0x3},
+ {0x86,0x05,0x3},
+ {0x87,0x1c,0x3},
+ {0x88,0x00,0x3},
+ {0x89,0x2d,0x3},
+ {0x8a,0x00,0x3},
+ {0x8b,0xcc,0x3},
+ {0x8c,0x00,0x3},
+ {0x8d,0x00,0x3},
+ {0x8e,0x08,0x3},
+ {0x8f,0x08,0x3},
+ {0x90,0x01,0x3},
+ {0x91,0x00,0x3},
+ {0x92,0x91,0x3},
+ {0x93,0x00,0x3},
+ {0x94,0x88,0x3},
+ {0x95,0x02,0x3},
+
+
+
+ // page 4
+ {0xec,0x04,0x04},
+ {0x3f,0x09,0x04}, // VGA : old board :0x08 , new board ; 0X09
+ {0x18,0x00,0x04}, // sxga
+ {0x1c,0x41,0x04},
+ {0x20,0x41,0x04}, // vga center 040215
+ {0x22,0xc1,0x04},// a1);
+ {0x23,0x02,0x04},
+ {0x28,0x41,0x04},
+ {0x2a,0xc1,0x04},// a1);
+ {0x2b,0x02,0x04},
+
+ {0x3c,0x0b,0x04}, //f); // vga
+ {0x58,0x11,0x04},
+ {0x5c,0x14,0x04},
+ {0x60,0x21,0x04},
+ {0x61,0x00,0x04},
+ {0x62,0xB1,0x04},
+ {0x63,0x02,0x04},
+ {0x64,0x01,0x04},
+ {0x65,0x00,0x04},
+ {0x66,0x01,0x04},
+ {0x67,0x02,0x04},
+ {0x68,0x21,0x04},
+ {0x69,0x00,0x04},
+ {0x6a,0xB1,0x04},
+ {0x6b,0x02,0x04},
+ {0x6c,0x01,0x04},
+ {0x6d,0x00,0x04},
+ {0x6e,0x01,0x04},
+ {0x6f,0x02,0x04},
+ {0x70,0x2D,0x04},
+ {0x71,0x00,0x04},
+ {0x72,0xd3,0x04}, // 14
+ {0x73,0x05,0x04}, // 15
+ {0x74,0x1C,0x04},
+ {0x75,0x05,0x04},
+ {0x76,0x1b,0x04}, // HendL
+ {0x77,0x0b,0x04}, // HendH
+ {0x78,0x01,0x04}, // 5.00
+ {0x79,0x80,0x04}, // 5.2a
+ {0x7a,0x33,0x04},
+ {0x7b,0x00,0x04},
+ {0x7c,0x38,0x04}, // 5.0e
+ {0x7d,0x03,0x04},
+ {0x7e,0x00,0x04},
+ {0x7f,0x0A,0x04},
+
+ {0x80,0x2e,0x04},
+ {0x81,0x00,0x04},
+ {0x82,0xae,0x04},
+ {0x83,0x02,0x04},
+ {0x84,0x00,0x04},
+ {0x85,0x00,0x04},
+ {0x86,0x01,0x04},
+ {0x87,0x02,0x04},
+ {0x88,0x2e,0x04},
+ {0x89,0x00,0x04},
+ {0x8a,0xae,0x04},
+ {0x8b,0x02,0x04},
+ {0x8c,0x1c,0x04},
+ {0x8d,0x00,0x04},
+ {0x8e,0x04,0x04},
+ {0x8f,0x02,0x04},
+ {0x90,0x2d,0x04},
+ {0x91,0x00,0x04},
+ {0x92,0xa5,0x04},
+ {0x93,0x00,0x04},
+ {0x94,0x88,0x04},
+ {0x95,0x02,0x04},
+ {0x96,0xb3,0x04},
+ {0x97,0x06,0x04},
+ {0x98,0x01,0x04},
+ {0x99,0x00,0x04},
+ {0x9a,0x33,0x04},
+ {0x9b,0x30,0x04},
+ {0x9c,0x50,0x04},
+ {0x9d,0x30,0x04},
+ {0x9e,0x01,0x04},
+ {0x9f,0x08,0x04},
+
+ // page 5
+ {0xec,0x05,0x05},
+ {0x5a,0x22,0x05},
+
+ // page 6
+ {0xec,0x06,0x06},
+ {0x14,0x1e,0x06},
+ {0x15,0xb4,0x04},
+ {0x16,0x25,0x04},
+ {0x17,0x74,0x04},
+
+ {0x10,0x48,0x04},
+ {0x11,0xa0,0x04},
+ {0x12,0x40,0x04}, // 040216 AE1 window ÁÙÀÓ
+ {0x13,0x70,0x04},
+
+ {0x1a,0x29,0x04}, // 040217 AWB window ÁÙÀÓ
+ {0x30,0x40,0x04},
+ {0x31,0xa2,0x04},
+ {0x32,0x50,0x04},
+ {0x33,0xbc,0x04},
+ {0x34,0x10,0x04},
+ {0x35,0xd2,0x04},
+ {0x36,0x18,0x04},
+ {0x37,0xf5,0x04},
+ {0x38,0x10,0x04},
+ {0x39,0xd3,0x04},
+ {0x3a,0x1a,0x04},
+ {0x3b,0xf0,0x04},
+
+ // page 7
+ {0xec,0x07,0x07},
+ {0x08,0xff,0x7},
+ {0x38,0x01,0x7}, //07); 040315
+ {0x39,0x01,0x7}, //02); //4); 040223 040315
+ {0x11,0xfe,0x7}, //fe); // green -2 040303
+ {0x2a,0x20,0x7},
+ {0x2b,0x20,0x7},
+ {0x2c,0x10,0x7},
+ {0x2d,0x00,0x7},
+ {0x2e,0xf0,0x7},
+ {0x2f,0xd0,0x7},
+ {0x3a,0xf0,0x7},
+ {0x23,0x07,0x7}, // for ESD
+
+ // page 0
+ {0xec,0x00,0x00},
+ {0x8a,0x04,0x00},
+
+ // page 1
+ {0xec,0x01,0x01},
+ {0xe5,0xb0,0x01},
+ {0xe5,0xb0,0x01},
+ {0xc2,0x01,0x01},
+
+ {0x61,0x7b,0x01},
+ {0x62,0x7b,0x01},
+ {0x63,0x1b,0x01},
+ {0x64,0x1b,0x01},
+
+ // page 0
+ {0xec,0x00,0x00},
+ {0x7e,0x04,0x00},
+
+ // page 4
+ {0xec,0x04,0x04},
+ {0x04,0x02,0x04},
+ {0x06,0x02,0x04},
+
+ // page 1
+ {0xec,0x01,0x01},
+ {0x10,0x05,0x01},
+ {0x54,0x02,0x01},
+ {0x56,0x02,0x01},
+
+ // page 3
+ {0xec,0x03,0x03},
+ {0x0e,0x08,0x03},
+ {0x0f,0x08,0x03},
+
+ // page 4
+ {0xec,0x04,0x04},
+ {0x00,0x30,0x04},
+ {0x0a,0x30,0x04},
+
+ // page 5
+ {0xec,0x05,0x05},
+ {0x08,0x33,0x05},
+
+ // page 0
+ {0xec,0x00,0x00},
+ {0x02,0x00,0x00},
+
+ // page 4
+//scale out
+ {0xec,0x04,0x04},
+ {0x02,0x20,0x04},
+ {0x1c,0x4f,0x04},
+
+ // page 1
+ {0xec,0x01,0x01},
+ {0x52,0x20,0x01},
+
+ // page 5
+ {0xec,0x05,0x05},
+ {0x0e,0x4f,0x05},
+
+//ae speed
+ // page 0
+ {0xec,0x00,0x00},
+ {0x92,0x80,0x00},
+ {0x93,0x02,0x00},
+ {0x94,0x04,0x00},
+ {0x95,0x04,0x00},
+ {0x96,0x04,0x00},
+ {0x97,0x04,0x00},
+ {0x9b,0x47,0x00},
+
+ {0xec,0x00,0x00},
+ {0x40,0x17,0x00},
+ {0x41,0x4c,0x00},
+ {0x42,0x1d,0x00},
+ {0x43,0x3e,0x00},
+ {0x44,0x2a,0x00},
+ {0x45,0x2d,0x00},
+
+ {0xec,0x01,0x01},
+ {0x20,0xd0,0x01}, //high light color reference
+
+ {0xec,0x00,0x00},
+ {0x7e,0x00,0x00},
+ {0x73,0x11,0x00}, // 41
+ {0x78,0x78,0x00},
+
+ {0xec,0x07,0x07},
+ {0x1b,0x3e,0x07},
+
+ {0xec,0x00,0x00},
+ {0x48,0xA0,0x00}, //s48C0
+ {0x49,0xB0,0x00}, //s49B0
+ {0x4a,0x30,0x00}, //s4a20
+ {0x4b,0x70,0x00}, //s4b70
+ {0x4c,0xD0,0x00}, //s4cA0
+ {0x4d,0xB0,0x00}, //s4dB0
+ {0x4e,0x30,0x00}, //s4e30
+ {0x4f,0xF0,0x00}, //s4fF0
+ {0x50,0xA0,0x00}, //s50D0
+ {0x51,0xB0,0x00}, //s51B0
+ {0x52,0x25,0x00}, //s5210
+ {0x53,0x70,0x00}, //s5370
+ {0x54,0xD0,0x00}, //s5490
+ {0x55,0xD0,0x00}, //s55B0
+ {0x56,0x3A,0x00}, //s5640
+ {0x57,0xD0,0x00}, //s57D0
+ {0x58,0xA0,0x00}, //s58D0
+ {0x59,0xA0,0x00}, //s59B0
+ {0x5a,0x32,0x00}, //s5a0A
+ {0x5b,0x7A,0x00}, //s5b7A
+ {0x5c,0xB0,0x00}, //s5c90
+ {0x5d,0xC0,0x00}, //s5dC0
+ {0x5e,0x3E,0x00}, //s5e4A
+ {0x5f,0xfa,0x00}, //s5fD0
+
+ // gamma
+ {0xec,0x01,0x01},
+ {0x24,0x31,0x01},
+ {0x25,0x4C,0x01},
+ {0x26,0x75,0x01},
+ {0x27,0xB5,0x01},
+ {0x28,0x17,0x01},
+ {0x29,0xAE,0x01},
+ {0x2A,0x97,0x01},
+ {0x2B,0xFF,0x01},
+ {0x2C,0x00,0x01},
+ {0x2D,0x5B,0x01},
+
+ {0xB0,0x31,0x01},
+ {0xB1,0x4C,0x01},
+ {0xB2,0x75,0x01},
+ {0xB3,0xB5,0x01},
+ {0xB4,0x17,0x01},
+ {0xB5,0xAE,0x01},
+ {0xB6,0x97,0x01},
+ {0xB7,0xFF,0x01},
+ {0xB8,0x00,0x01},
+ {0xB9,0x5B,0x01},
+
+ {0xec,0x00,0x00},
+ {0x77,0xb0,0x00},
+ {0x39,0x06,0x00},
+ {0x3a,0x08,0x00},
+
+};
+
+
+#define S5X532_INIT_REGS (sizeof(s5x532_reg)/sizeof(s5x532_reg[0]))
+#define S5X532_RISC_REGS 0xEB
+#define S5X532_ISP_REGS 0xFB /* S5C7323X */
+#define S5X532_CIS_REGS 0x2F /* S5K437LA03 */
+
+
+#define PAGE_ADDRESS 0xEC
+
+//#define S5X532_REGS (S5X532_RISC_REGS+S5X532_ISP_REGS+S5X532_CIS_REGS)
+#define S5X532_REGS (0x1000)
+
+
+
+#endif
+
+
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/userapp.h
@@ -0,0 +1,44 @@
+/*
+ Character Driver API Interface
+
+ Copyright (C) 2003 Samsung Electronics (SW.LEE: hitchcar@samsung.com)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+*/
+
+#ifndef __FIMC20_CAMIF_USR_APP_H_
+#define __FIMC20_CAMIF_USR_APP_H_
+
+
+/*
+ * IOCTL Command for Character Driver
+ */
+
+#define CMD_CAMERA_INIT 0x23
+/* Test Application Usage */
+typedef struct {
+ int src_x;
+ int src_y;
+ int dst_x;
+ int dst_y;
+ int bpp;
+ int flip;
+} camif_param_t;
+
+
+
+#endif
+
+
+/*
+ * Local variables:
+ * tab-width: 8
+ * c-indent-level: 8
+ * c-basic-offset: 8
+ * c-set-style: "K&R"
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/v4l2_api.c
@@ -0,0 +1,311 @@
+/*
+ * . 2004-01-03: SW.LEE <hitchcar@sec.samsung.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License 2. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <linux/tqueue.h>
+#include <linux/locks.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/miscdevice.h>
+#include <linux/wait.h>
+
+#include <asm/io.h>
+#include <asm/semaphore.h>
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+
+#include <asm/arch/cpu_s3c2440.h>
+#include <asm/arch/S3C2440.h>
+
+#include "camif.h"
+#include "videodev.h"
+
+/*
+ Codec_formats/Preview_format[0] must be same to initial value of
+ preview_init_param/codec_init_param
+*/
+
+const struct v4l2_fmtdesc codec_formats[] = {
+ {
+ .index = 0,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+// .flags = FORMAT_FLAGS_PLANAR,
+ .description = "4:2:2, planar, Y-Cb-Cr",
+ .pixelformat = V4L2_PIX_FMT_YUV422P,
+
+ },{
+ .index = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+// .flags = FORMAT_FLAGS_PLANAR,
+ .name = "4:2:0, planar, Y-Cb-Cr",
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ }
+};
+
+
+/* Todo
+ FIMC V4L2_PIX_FMT_RGB565 is not same to that of V4L2spec
+ and so we need image convert to FIMC V4l2_PIX_FMT_RGB565.
+*/
+const struct v4l2_fmtdesc preview_formats[] = {
+ {
+ .index = 1,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+ .description = "16 bpp RGB, le",
+ .fourcc = V4L2_PIX_FMT_RGB565,
+// .flags = FORMAT_FLAGS_PACKED,
+ },
+ {
+ .index = 0,
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+// .flags = FORMAT_FLAGS_PACKED,
+ .description = "32 bpp RGB, le",
+ .fourcc = V4L2_PIX_FMT_BGR32,
+ }
+}
+
+#define NUM_F ARRARY_SIZE(preview_formats)
+
+
+/*
+ * This function and v4l2 structure made for V4L2 API functions
+ * App <--> v4l2 <--> logical param <--> hardware
+ */
+static int camif_get_v4l2(camif_cfg_t *cfg)
+{
+ return 0;
+}
+
+
+/*
+** Gives the depth of a video4linux2 fourcc aka pixel format in bits.
+*/
+static int pixfmt2depth(int pixfmt,int *fmtptr)
+{
+ int fmt, depth;
+
+ switch (pixfmt) {
+ case V4L2_PIX_FMT_RGB565:
+ case V4L2_PIX_FMT_RGB565X:
+ fmt = CAMIF_RGB_16;
+ depth = 16;
+ break;
+ case V4L2_PIX_FMT_BGR24: /* Not tested */
+ case V4L2_PIX_FMT_RGB24:
+ fmt = CAMIF_RGB_24;
+ depth = 24;
+ break;
+ case V4L2_PIX_FMT_BGR32:
+ case V4L2_PIX_FMT_RGB32:
+ fmt = CAMIF_RGB_24;
+ depth 32;
+ break;
+ case V4L2_PIX_FMT_GREY: /* Not tested */
+ fmt = CAMIF_OUT_YCBCR420;
+ depth = 8;
+ break;
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_YUV422P:
+ fmt = CAMIF_OUT_YCBCR422;
+ depth = 16;
+ break;
+ case V4L2_PIX_FMT_YUV420:
+ fmt = CAMIF_OUT_YCBCR420;
+ depth = 12;
+ break;
+ }
+ if (fmtptr) *fmtptr = fmt;
+ return depth;
+}
+
+
+
+static int camif_s_v4l2(camif_cfg_t *cfg)
+{
+ int num = cfg->v2.used_fmt;
+
+ if ( !(cfg->v2.status&CAMIF_V4L2_INIT)) {
+ int depth;
+ int fourcc = v2.fmtdesc[num].pixelformat;
+
+ /* To define v4l2_fmtsdesc */
+ if (cfg->dma_type == CAMIF_CODEC)
+ cfg->v2->fmtdesc = codec_formats;
+ else
+ cfg->v2->fmtdesc = preview_formats;
+
+ /* To define v4l2_format used currently */
+ cfg->v2.fmt.width = cfg->target_x;
+ cfg->v2.fmt.height = cfg->target_y;
+ cfg->v2.fmt.field = V4L2_FIELD_NONE;
+ cfg->v2.fmt.pixelformat = fourcc;
+ depth = pixfmt2depth(fourcc,NULL);
+ cfg->v2.fmt.bytesperline= cfg->v2.fmt.width*depth >> 3;
+ cfg->v2.fmt.sizeimage =
+ cfg->v2.fmt.height * cfg->v2.fmt.bytesperline;
+
+ /* To define v4l2_input */
+ cfg->v2.input.index = 0;
+ if (cfg->dma_type == CAMIF_CODEC)
+ snprintf(cfg->v2.input.name, 31, "CAMIF CODEC");
+ else
+ snprintf(cfg->v2.input.name, 31, "CAMIF PREVIEW");
+ cfg->v2.input.type = V4L2_INPUT_TYPE_CAMERA;
+
+ /* Write the Status of v4l2 machine */
+ cfg->v2.status |= CAMIF_V4L2_INIT;
+ }
+ return 0;
+}
+
+
+static int camif_g_fmt(camif_cfg_t *cfg, struct v4l2_format *f)
+{
+ int size = sizeof(struct v4l2_pix_format);
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ memset(&f->fmt.pix,0,size);
+ memcpy(&f->fmt.pix,&cfg->v2.fmt,size);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
+
+/* Copy v4l2 parameter into other element of camif_cfg_t */
+static int camif_s_try(camif_cfg_t *cfg, int f)
+{
+ int fmt;
+ cfg->target_x = cfg->v2.fmt.width;
+ cfg->target_y = cfg->v2.fmt.height;
+ pixfmt2depth(cfg->v2.fmt.pixelformat,&fmt);
+ cfg->fmt = fmt;
+ camif_dynamic_conf(cfg);
+}
+
+
+static int camif_s_fmt(camif_cfg_t *cfg, struct v4l2_format *f)
+{
+ int retval;
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ {
+ /* update our state informations */
+// down(&fh->cap.lock);
+ cfg->v2.fmt = f->pix;
+ cfg->v2.status |= CAMIF_v4L2_DIRTY;
+ camif_dynamic_conf(cfg);
+ cfg->v2.status &= ~CAMIF_v4L2_DIRTY; /* dummy ? */
+// up(&fh->cap.lock);
+
+ return 0;
+ }
+ default:
+ return -EINVAL;
+ }
+
+}
+
+/* Refer ioctl of videodeX.c and bttv-driver.c */
+int camif_do_ioctl
+(struct inode *inode, struct file *file,unsigned int cmd, void * arg)
+{
+ camif_cfg_t *cfg = file->private_data;
+ int ret = 0;
+
+ switch (cmd) {
+ case VIDIOC_QUERYCAP:
+ {
+ struct v4l2_capability *cap = arg;
+
+ strcpy(cap->driver,"Fimc Camera");
+ strlcpy(cap->card,cfg->v->name,sizeof(cap->card));
+ sprintf(cap->bus_info,"FIMC 2.0 AHB Bus");
+ cap->version = 0;
+ cap->capabilities =
+ V4L2_CAP_VIDEO_CAPTURE |V4L2_CAP_READWRITE;
+ return 0;
+ }
+ case VIDIOC_G_FMT:
+ {
+ struct v4l2_format *f = arg;
+ return camif_g_fmt(cfg,f);
+ }
+ case VIDIOC_S_FMT:
+ {
+ struct v4l2_format *f = arg;
+ return camif_s_fmt(cfg,f);
+ }
+
+ case VIDIOC_ENUM_FMT:
+ {
+ struct v4l2_fmtdesc *f = arg;
+ enum v4l2_buf_type type = f->type;
+ int index = f->index;
+
+ if (index >= NUM_F)
+ return -EINVAL;
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ break;
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ default:
+ return -EINVAL;
+ }
+ memset(f,0,sizeof(*f));
+ memcpy(f,cfg->v2.fmtdesc+index,sizeof(*f));
+ return 0;
+ }
+ case VIDIOC_G_INPUT:
+ {
+ u32 *i = arg;
+ *i = cfg->v2.input;
+ return 0;
+ }
+ case VIDIOC_S_INPUT:
+ {
+ int index = *((int *)arg);
+ if (index != 0)
+ return -EINVAL;
+ cfg->v2.input.index = index;
+ return 0;
+ }
+
+ default:
+ return -ENOIOCTLCMD; /* errno.h */
+ } /* End of Switch */
+
+
+}
+
+
+
+
+
+
+
+/*
+ * Local variables:
+ * tab-width: 8
+ * c-indent-level: 8
+ * c-basic-offset: 8
+ * c-set-style: "K&R"
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/videodev2.h
@@ -0,0 +1,938 @@
+#ifndef __LINUX_VIDEODEV2_H
+#define __LINUX_VIDEODEV2_H
+/*
+ * Video for Linux Two
+ *
+ * Header file for v4l or V4L2 drivers and applications, for
+ * Linux kernels 2.2.x or 2.4.x.
+ *
+ * See http://bytesex.org/v4l/ for API specs and other
+ * v4l2 documentation.
+ *
+ * Author: Bill Dirks <bdirks@pacbell.net>
+ * Justin Schoeman
+ * et al.
+ */
+#ifdef __KERNEL__
+#include <linux/time.h> /* need struct timeval */
+#endif
+
+/*
+ * M I S C E L L A N E O U S
+ */
+
+/* Four-character-code (FOURCC) */
+#define v4l2_fourcc(a,b,c,d)\
+ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * E N U M S
+ */
+enum v4l2_field {
+ V4L2_FIELD_ANY = 0, /* driver can choose from none,
+ top, bottom, interlaced
+ depending on whatever it thinks
+ is approximate ... */
+ V4L2_FIELD_NONE = 1, /* this device has no fields ... */
+ V4L2_FIELD_TOP = 2, /* top field only */
+ V4L2_FIELD_BOTTOM = 3, /* bottom field only */
+ V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */
+ V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one
+ buffer, top-bottom order */
+ V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */
+ V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into
+ separate buffers */
+};
+#define V4L2_FIELD_HAS_TOP(field) \
+ ((field) == V4L2_FIELD_TOP ||\
+ (field) == V4L2_FIELD_INTERLACED ||\
+ (field) == V4L2_FIELD_SEQ_TB ||\
+ (field) == V4L2_FIELD_SEQ_BT)
+#define V4L2_FIELD_HAS_BOTTOM(field) \
+ ((field) == V4L2_FIELD_BOTTOM ||\
+ (field) == V4L2_FIELD_INTERLACED ||\
+ (field) == V4L2_FIELD_SEQ_TB ||\
+ (field) == V4L2_FIELD_SEQ_BT)
+#define V4L2_FIELD_HAS_BOTH(field) \
+ ((field) == V4L2_FIELD_INTERLACED ||\
+ (field) == V4L2_FIELD_SEQ_TB ||\
+ (field) == V4L2_FIELD_SEQ_BT)
+
+enum v4l2_buf_type {
+ V4L2_BUF_TYPE_VIDEO_CAPTURE = 1,
+ V4L2_BUF_TYPE_VIDEO_OUTPUT = 2,
+ V4L2_BUF_TYPE_VIDEO_OVERLAY = 3,
+ V4L2_BUF_TYPE_VBI_CAPTURE = 4,
+ V4L2_BUF_TYPE_VBI_OUTPUT = 5,
+ V4L2_BUF_TYPE_PRIVATE = 0x80,
+};
+
+enum v4l2_ctrl_type {
+ V4L2_CTRL_TYPE_INTEGER = 1,
+ V4L2_CTRL_TYPE_BOOLEAN = 2,
+ V4L2_CTRL_TYPE_MENU = 3,
+ V4L2_CTRL_TYPE_BUTTON = 4,
+};
+
+enum v4l2_tuner_type {
+ V4L2_TUNER_RADIO = 1,
+ V4L2_TUNER_ANALOG_TV = 2,
+};
+
+enum v4l2_memory {
+ V4L2_MEMORY_MMAP = 1,
+ V4L2_MEMORY_USERPTR = 2,
+ V4L2_MEMORY_OVERLAY = 3,
+};
+
+/* see also http://vektor.theorem.ca/graphics/ycbcr/ */
+enum v4l2_colorspace {
+ /* ITU-R 601 -- broadcast NTSC/PAL */
+ V4L2_COLORSPACE_SMPTE170M = 1,
+
+ /* 1125-Line (US) HDTV */
+ V4L2_COLORSPACE_SMPTE240M = 2,
+
+ /* HD and modern captures. */
+ V4L2_COLORSPACE_REC709 = 3,
+
+ /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */
+ V4L2_COLORSPACE_BT878 = 4,
+
+ /* These should be useful. Assume 601 extents. */
+ V4L2_COLORSPACE_470_SYSTEM_M = 5,
+ V4L2_COLORSPACE_470_SYSTEM_BG = 6,
+
+ /* I know there will be cameras that send this. So, this is
+ * unspecified chromaticities and full 0-255 on each of the
+ * Y'CbCr components
+ */
+ V4L2_COLORSPACE_JPEG = 7,
+
+ /* For RGB colourspaces, this is probably a good start. */
+ V4L2_COLORSPACE_SRGB = 8,
+};
+
+enum v4l2_priority {
+ V4L2_PRIORITY_UNSET = 0, /* not initialized */
+ V4L2_PRIORITY_BACKGROUND = 1,
+ V4L2_PRIORITY_INTERACTIVE = 2,
+ V4L2_PRIORITY_RECORD = 3,
+ V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE,
+};
+
+struct v4l2_rect {
+ __s32 left;
+ __s32 top;
+ __s32 width;
+ __s32 height;
+};
+
+struct v4l2_fract {
+ __u32 numerator;
+ __u32 denominator;
+};
+
+/*
+ * D R I V E R C A P A B I L I T I E S
+ */
+struct v4l2_capability
+{
+ __u8 driver[16]; /* i.e. "bttv" */
+ __u8 card[32]; /* i.e. "Hauppauge WinTV" */
+ __u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */
+ __u32 version; /* should use KERNEL_VERSION() */
+ __u32 capabilities; /* Device capabilities */
+ __u32 reserved[4];
+};
+
+/* Values for 'capabilities' field */
+#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */
+#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */
+#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */
+#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a VBI capture device */
+#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a VBI output device */
+#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */
+
+#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */
+#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */
+#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */
+
+#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */
+#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */
+#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */
+
+/*
+ * V I D E O I M A G E F O R M A T
+ */
+
+struct v4l2_pix_format
+{
+ __u32 width;
+ __u32 height;
+ __u32 pixelformat;
+ enum v4l2_field field;
+ __u32 bytesperline; /* for padding, zero if unused */
+ __u32 sizeimage;
+ enum v4l2_colorspace colorspace;
+ __u32 priv; /* private data, depends on pixelformat */
+};
+
+/* Pixel format FOURCC depth Description */
+#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R','G','B','1') /* 8 RGB-3-3-2 */
+#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R','G','B','O') /* 16 RGB-5-5-5 */
+#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R','G','B','P') /* 16 RGB-5-6-5 */
+#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16 RGB-5-5-5 BE */
+#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R','G','B','R') /* 16 RGB-5-6-5 BE */
+#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B','G','R','3') /* 24 BGR-8-8-8 */
+#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R','G','B','3') /* 24 RGB-8-8-8 */
+#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B','G','R','4') /* 32 BGR-8-8-8-8 */
+#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R','G','B','4') /* 32 RGB-8-8-8-8 */
+#define V4L2_PIX_FMT_GREY v4l2_fourcc('G','R','E','Y') /* 8 Greyscale */
+#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */
+#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */
+#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y','U','Y','V') /* 16 YUV 4:2:2 */
+#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U','Y','V','Y') /* 16 YUV 4:2:2 */
+#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16 YVU422 planar */
+#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16 YVU411 planar */
+#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y','4','1','P') /* 12 YUV 4:1:1 */
+
+/* two planes -- one Y, one Cr + Cb interleaved */
+#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N','V','1','2') /* 12 Y/CbCr 4:2:0 */
+#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N','V','2','1') /* 12 Y/CrCb 4:2:0 */
+
+/* The following formats are not defined in the V4L2 specification */
+#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y','U','V','9') /* 9 YUV 4:1:0 */
+#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y','U','1','2') /* 12 YUV 4:2:0 */
+#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y','Y','U','V') /* 16 YUV 4:2:2 */
+#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H','I','2','4') /* 8 8-bit color */
+
+/* compressed formats */
+#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M','J','P','G') /* Motion-JPEG */
+#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J','P','E','G') /* JFIF JPEG */
+#define V4L2_PIX_FMT_DV v4l2_fourcc('d','v','s','d') /* 1394 */
+#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M','P','E','G') /* MPEG */
+
+/* Vendor-specific formats */
+#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W','N','V','A') /* Winnov hw compress */
+
+/*
+ * F O R M A T E N U M E R A T I O N
+ */
+struct v4l2_fmtdesc
+{
+ __u32 index; /* Format number */
+ enum v4l2_buf_type type; /* buffer type */
+ __u32 flags;
+ __u8 description[32]; /* Description string */
+ __u32 pixelformat; /* Format fourcc */
+ __u32 reserved[4];
+};
+
+#define V4L2_FMT_FLAG_COMPRESSED 0x0001
+
+
+/*
+ * T I M E C O D E
+ */
+struct v4l2_timecode
+{
+ __u32 type;
+ __u32 flags;
+ __u8 frames;
+ __u8 seconds;
+ __u8 minutes;
+ __u8 hours;
+ __u8 userbits[4];
+};
+
+/* Type */
+#define V4L2_TC_TYPE_24FPS 1
+#define V4L2_TC_TYPE_25FPS 2
+#define V4L2_TC_TYPE_30FPS 3
+#define V4L2_TC_TYPE_50FPS 4
+#define V4L2_TC_TYPE_60FPS 5
+
+/* Flags */
+#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */
+#define V4L2_TC_FLAG_COLORFRAME 0x0002
+#define V4L2_TC_USERBITS_field 0x000C
+#define V4L2_TC_USERBITS_USERDEFINED 0x0000
+#define V4L2_TC_USERBITS_8BITCHARS 0x0008
+/* The above is based on SMPTE timecodes */
+
+
+/*
+ * C O M P R E S S I O N P A R A M E T E R S
+ */
+#if 0
+/* ### generic compression settings don't work, there is too much
+ * ### codec-specific stuff. Maybe reuse that for MPEG codec settings
+ * ### later ... */
+struct v4l2_compression
+{
+ __u32 quality;
+ __u32 keyframerate;
+ __u32 pframerate;
+ __u32 reserved[5];
+
+/* what we'll need for MPEG, extracted from some postings on
+ the v4l list (Gert Vervoort, PlasmaJohn).
+
+system stream:
+ - type: elementary stream(ES), packatised elementary stream(s) (PES)
+ program stream(PS), transport stream(TS)
+ - system bitrate
+ - PS packet size (DVD: 2048 bytes, VCD: 2324 bytes)
+ - TS video PID
+ - TS audio PID
+ - TS PCR PID
+ - TS system information tables (PAT, PMT, CAT, NIT and SIT)
+ - (MPEG-1 systems stream vs. MPEG-2 program stream (TS not supported
+ by MPEG-1 systems)
+
+audio:
+ - type: MPEG (+Layer I,II,III), AC-3, LPCM
+ - bitrate
+ - sampling frequency (DVD: 48 Khz, VCD: 44.1 KHz, 32 kHz)
+ - Trick Modes? (ff, rew)
+ - Copyright
+ - Inverse Telecine
+
+video:
+ - picturesize (SIF, 1/2 D1, 2/3 D1, D1) and PAL/NTSC norm can be set
+ through excisting V4L2 controls
+ - noise reduction, parameters encoder specific?
+ - MPEG video version: MPEG-1, MPEG-2
+ - GOP (Group Of Pictures) definition:
+ - N: number of frames per GOP
+ - M: distance between reference (I,P) frames
+ - open/closed GOP
+ - quantiser matrix: inter Q matrix (64 bytes) and intra Q matrix (64 bytes)
+ - quantiser scale: linear or logarithmic
+ - scanning: alternate or zigzag
+ - bitrate mode: CBR (constant bitrate) or VBR (variable bitrate).
+ - target video bitrate for CBR
+ - target video bitrate for VBR
+ - maximum video bitrate for VBR - min. quantiser value for VBR
+ - max. quantiser value for VBR
+ - adaptive quantisation value
+ - return the number of bytes per GOP or bitrate for bitrate monitoring
+
+*/
+};
+#endif
+
+struct v4l2_jpegcompression
+{
+ int quality;
+
+ int APPn; /* Number of APP segment to be written,
+ * must be 0..15 */
+ int APP_len; /* Length of data in JPEG APPn segment */
+ char APP_data[60]; /* Data in the JPEG APPn segment. */
+
+ int COM_len; /* Length of data in JPEG COM segment */
+ char COM_data[60]; /* Data in JPEG COM segment */
+
+ __u32 jpeg_markers; /* Which markers should go into the JPEG
+ * output. Unless you exactly know what
+ * you do, leave them untouched.
+ * Inluding less markers will make the
+ * resulting code smaller, but there will
+ * be fewer aplications which can read it.
+ * The presence of the APP and COM marker
+ * is influenced by APP_len and COM_len
+ * ONLY, not by this property! */
+
+#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */
+#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */
+#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */
+#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */
+#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will
+ * allways use APP0 */
+};
+
+
+/*
+ * M E M O R Y - M A P P I N G B U F F E R S
+ */
+struct v4l2_requestbuffers
+{
+ __u32 count;
+ enum v4l2_buf_type type;
+ enum v4l2_memory memory;
+ __u32 reserved[2];
+};
+
+struct v4l2_buffer
+{
+ __u32 index;
+ enum v4l2_buf_type type;
+ __u32 bytesused;
+ __u32 flags;
+ enum v4l2_field field;
+ struct timeval timestamp;
+ struct v4l2_timecode timecode;
+ __u32 sequence;
+
+ /* memory location */
+ enum v4l2_memory memory;
+ union {
+ __u32 offset;
+ unsigned long userptr;
+ } m;
+ __u32 length;
+
+ __u32 reserved[2];
+};
+
+/* Flags for 'flags' field */
+#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */
+#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */
+#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */
+#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */
+#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */
+#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */
+#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */
+
+/*
+ * O V E R L A Y P R E V I E W
+ */
+struct v4l2_framebuffer
+{
+ __u32 capability;
+ __u32 flags;
+/* FIXME: in theory we should pass something like PCI device + memory
+ * region + offset instead of some physical address */
+ void* base;
+ struct v4l2_pix_format fmt;
+};
+/* Flags for the 'capability' field. Read only */
+#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001
+#define V4L2_FBUF_CAP_CHROMAKEY 0x0002
+#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004
+#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008
+/* Flags for the 'flags' field. */
+#define V4L2_FBUF_FLAG_PRIMARY 0x0001
+#define V4L2_FBUF_FLAG_OVERLAY 0x0002
+#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004
+
+struct v4l2_clip
+{
+ struct v4l2_rect c;
+ struct v4l2_clip *next;
+};
+
+struct v4l2_window
+{
+ struct v4l2_rect w;
+ enum v4l2_field field;
+ __u32 chromakey;
+ struct v4l2_clip *clips;
+ __u32 clipcount;
+ void *bitmap;
+};
+
+
+/*
+ * C A P T U R E P A R A M E T E R S
+ */
+struct v4l2_captureparm
+{
+ __u32 capability; /* Supported modes */
+ __u32 capturemode; /* Current mode */
+ struct v4l2_fract timeperframe; /* Time per frame in .1us units */
+ __u32 extendedmode; /* Driver-specific extensions */
+ __u32 readbuffers; /* # of buffers for read */
+ __u32 reserved[4];
+};
+/* Flags for 'capability' and 'capturemode' fields */
+#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */
+#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */
+
+struct v4l2_outputparm
+{
+ __u32 capability; /* Supported modes */
+ __u32 outputmode; /* Current mode */
+ struct v4l2_fract timeperframe; /* Time per frame in seconds */
+ __u32 extendedmode; /* Driver-specific extensions */
+ __u32 writebuffers; /* # of buffers for write */
+ __u32 reserved[4];
+};
+
+/*
+ * I N P U T I M A G E C R O P P I N G
+ */
+
+struct v4l2_cropcap {
+ enum v4l2_buf_type type;
+ struct v4l2_rect bounds;
+ struct v4l2_rect defrect;
+ struct v4l2_fract pixelaspect;
+};
+
+struct v4l2_crop {
+ enum v4l2_buf_type type;
+ struct v4l2_rect c;
+};
+
+/*
+ * A N A L O G V I D E O S T A N D A R D
+ */
+
+typedef __u64 v4l2_std_id;
+
+/* one bit for each */
+#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001)
+#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002)
+#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004)
+#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008)
+#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010)
+#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020)
+#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040)
+#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080)
+
+#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100)
+#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200)
+#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400)
+#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800)
+
+#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000)
+#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000)
+
+#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000)
+#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000)
+#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000)
+#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000)
+#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000)
+#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000)
+#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000)
+
+/* ATSC/HDTV */
+#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000)
+#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000)
+
+/* some common needed stuff */
+#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\
+ V4L2_STD_PAL_B1 |\
+ V4L2_STD_PAL_G)
+#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\
+ V4L2_STD_PAL_D1 |\
+ V4L2_STD_PAL_K)
+#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\
+ V4L2_STD_PAL_DK |\
+ V4L2_STD_PAL_H |\
+ V4L2_STD_PAL_I)
+#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\
+ V4L2_STD_NTSC_M_JP)
+#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\
+ V4L2_STD_SECAM_D |\
+ V4L2_STD_SECAM_G |\
+ V4L2_STD_SECAM_H |\
+ V4L2_STD_SECAM_K |\
+ V4L2_STD_SECAM_K1 |\
+ V4L2_STD_SECAM_L)
+
+#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\
+ V4L2_STD_PAL_60 |\
+ V4L2_STD_NTSC)
+#define V4L2_STD_625_50 (V4L2_STD_PAL |\
+ V4L2_STD_PAL_N |\
+ V4L2_STD_PAL_Nc |\
+ V4L2_STD_SECAM)
+
+#define V4L2_STD_UNKNOWN 0
+#define V4L2_STD_ALL (V4L2_STD_525_60 |\
+ V4L2_STD_625_50)
+
+struct v4l2_standard
+{
+ __u32 index;
+ v4l2_std_id id;
+ __u8 name[24];
+ struct v4l2_fract frameperiod; /* Frames, not fields */
+ __u32 framelines;
+ __u32 reserved[4];
+};
+
+
+/*
+ * V I D E O I N P U T S
+ */
+struct v4l2_input
+{
+ __u32 index; /* Which input */
+ __u8 name[32]; /* Label */
+ __u32 type; /* Type of input */
+ __u32 audioset; /* Associated audios (bitfield) */
+ __u32 tuner; /* Associated tuner */
+ v4l2_std_id std;
+ __u32 status;
+ __u32 reserved[4];
+};
+/* Values for the 'type' field */
+#define V4L2_INPUT_TYPE_TUNER 1
+#define V4L2_INPUT_TYPE_CAMERA 2
+
+/* field 'status' - general */
+#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */
+#define V4L2_IN_ST_NO_SIGNAL 0x00000002
+#define V4L2_IN_ST_NO_COLOR 0x00000004
+
+/* field 'status' - analog */
+#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */
+#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */
+
+/* field 'status' - digital */
+#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */
+#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */
+#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */
+
+/* field 'status' - VCR and set-top box */
+#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */
+#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */
+#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */
+
+/*
+ * V I D E O O U T P U T S
+ */
+struct v4l2_output
+{
+ __u32 index; /* Which output */
+ __u8 name[32]; /* Label */
+ __u32 type; /* Type of output */
+ __u32 audioset; /* Associated audios (bitfield) */
+ __u32 modulator; /* Associated modulator */
+ v4l2_std_id std;
+ __u32 reserved[4];
+};
+/* Values for the 'type' field */
+#define V4L2_OUTPUT_TYPE_MODULATOR 1
+#define V4L2_OUTPUT_TYPE_ANALOG 2
+#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3
+
+/*
+ * C O N T R O L S
+ */
+struct v4l2_control
+{
+ __u32 id;
+ __s32 value;
+};
+
+/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */
+struct v4l2_queryctrl
+{
+ __u32 id;
+ enum v4l2_ctrl_type type;
+ __u8 name[32]; /* Whatever */
+ __s32 minimum; /* Note signedness */
+ __s32 maximum;
+ __s32 step;
+ __s32 default_value;
+ __u32 flags;
+ __u32 reserved[2];
+};
+
+/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */
+struct v4l2_querymenu
+{
+ __u32 id;
+ __u32 index;
+ __u8 name[32]; /* Whatever */
+ __u32 reserved;
+};
+
+/* Control flags */
+#define V4L2_CTRL_FLAG_DISABLED 0x0001
+#define V4L2_CTRL_FLAG_GRABBED 0x0002
+
+/* Control IDs defined by V4L2 */
+#define V4L2_CID_BASE 0x00980900
+/* IDs reserved for driver specific controls */
+#define V4L2_CID_PRIVATE_BASE 0x08000000
+
+#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0)
+#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1)
+#define V4L2_CID_SATURATION (V4L2_CID_BASE+2)
+#define V4L2_CID_HUE (V4L2_CID_BASE+3)
+#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5)
+#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6)
+#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7)
+#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8)
+#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9)
+#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10)
+#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11)
+#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12)
+#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13)
+#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14)
+#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15)
+#define V4L2_CID_GAMMA (V4L2_CID_BASE+16)
+#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* ? Not sure */
+#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17)
+#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18)
+#define V4L2_CID_GAIN (V4L2_CID_BASE+19)
+#define V4L2_CID_HFLIP (V4L2_CID_BASE+20)
+#define V4L2_CID_VFLIP (V4L2_CID_BASE+21)
+#define V4L2_CID_HCENTER (V4L2_CID_BASE+22)
+#define V4L2_CID_VCENTER (V4L2_CID_BASE+23)
+#define V4L2_CID_LASTP1 (V4L2_CID_BASE+24) /* last CID + 1 */
+
+/*
+ * T U N I N G
+ */
+struct v4l2_tuner
+{
+ __u32 index;
+ __u8 name[32];
+ enum v4l2_tuner_type type;
+ __u32 capability;
+ __u32 rangelow;
+ __u32 rangehigh;
+ __u32 rxsubchans;
+ __u32 audmode;
+ __s32 signal;
+ __s32 afc;
+ __u32 reserved[4];
+};
+
+struct v4l2_modulator
+{
+ __u32 index;
+ __u8 name[32];
+ __u32 capability;
+ __u32 rangelow;
+ __u32 rangehigh;
+ __u32 txsubchans;
+ __u32 reserved[4];
+};
+
+/* Flags for the 'capability' field */
+#define V4L2_TUNER_CAP_LOW 0x0001
+#define V4L2_TUNER_CAP_NORM 0x0002
+#define V4L2_TUNER_CAP_STEREO 0x0010
+#define V4L2_TUNER_CAP_LANG2 0x0020
+#define V4L2_TUNER_CAP_SAP 0x0020
+#define V4L2_TUNER_CAP_LANG1 0x0040
+
+/* Flags for the 'rxsubchans' field */
+#define V4L2_TUNER_SUB_MONO 0x0001
+#define V4L2_TUNER_SUB_STEREO 0x0002
+#define V4L2_TUNER_SUB_LANG2 0x0004
+#define V4L2_TUNER_SUB_SAP 0x0004
+#define V4L2_TUNER_SUB_LANG1 0x0008
+
+/* Values for the 'audmode' field */
+#define V4L2_TUNER_MODE_MONO 0x0000
+#define V4L2_TUNER_MODE_STEREO 0x0001
+#define V4L2_TUNER_MODE_LANG2 0x0002
+#define V4L2_TUNER_MODE_SAP 0x0002
+#define V4L2_TUNER_MODE_LANG1 0x0003
+
+struct v4l2_frequency
+{
+ __u32 tuner;
+ enum v4l2_tuner_type type;
+ __u32 frequency;
+ __u32 reserved[8];
+};
+
+/*
+ * A U D I O
+ */
+struct v4l2_audio
+{
+ __u32 index;
+ __u8 name[32];
+ __u32 capability;
+ __u32 mode;
+ __u32 reserved[2];
+};
+/* Flags for the 'capability' field */
+#define V4L2_AUDCAP_STEREO 0x00001
+#define V4L2_AUDCAP_AVL 0x00002
+
+/* Flags for the 'mode' field */
+#define V4L2_AUDMODE_AVL 0x00001
+
+struct v4l2_audioout
+{
+ __u32 index;
+ __u8 name[32];
+ __u32 capability;
+ __u32 mode;
+ __u32 reserved[2];
+};
+
+/*
+ * D A T A S E R V I C E S ( V B I )
+ *
+ * Data services API by Michael Schimek
+ */
+
+struct v4l2_vbi_format
+{
+ __u32 sampling_rate; /* in 1 Hz */
+ __u32 offset;
+ __u32 samples_per_line;
+ __u32 sample_format; /* V4L2_PIX_FMT_* */
+ __s32 start[2];
+ __u32 count[2];
+ __u32 flags; /* V4L2_VBI_* */
+ __u32 reserved[2]; /* must be zero */
+};
+
+/* VBI flags */
+#define V4L2_VBI_UNSYNC (1<< 0)
+#define V4L2_VBI_INTERLACED (1<< 1)
+
+
+/*
+ * A G G R E G A T E S T R U C T U R E S
+ */
+
+/* Stream data format
+ */
+struct v4l2_format
+{
+ enum v4l2_buf_type type;
+ union
+ {
+ struct v4l2_pix_format pix; // V4L2_BUF_TYPE_VIDEO_CAPTURE
+ struct v4l2_window win; // V4L2_BUF_TYPE_VIDEO_OVERLAY
+ struct v4l2_vbi_format vbi; // V4L2_BUF_TYPE_VBI_CAPTURE
+ __u8 raw_data[200]; // user-defined
+ } fmt;
+};
+
+
+/* Stream type-dependent parameters
+ */
+struct v4l2_streamparm
+{
+ enum v4l2_buf_type type;
+ union
+ {
+ struct v4l2_captureparm capture;
+ struct v4l2_outputparm output;
+ __u8 raw_data[200]; /* user-defined */
+ } parm;
+};
+
+
+
+/*
+ * I O C T L C O D E S F O R V I D E O D E V I C E S
+ *
+ */
+#define VIDIOC_QUERYCAP _IOR ('V', 0, struct v4l2_capability)
+#define VIDIOC_RESERVED _IO ('V', 1)
+#define VIDIOC_ENUM_FMT _IOWR ('V', 2, struct v4l2_fmtdesc)
+#define VIDIOC_G_FMT _IOWR ('V', 4, struct v4l2_format)
+#define VIDIOC_S_FMT _IOWR ('V', 5, struct v4l2_format)
+#if 0
+#define VIDIOC_G_COMP _IOR ('V', 6, struct v4l2_compression)
+#define VIDIOC_S_COMP _IOW ('V', 7, struct v4l2_compression)
+#endif
+#define VIDIOC_REQBUFS _IOWR ('V', 8, struct v4l2_requestbuffers)
+#define VIDIOC_QUERYBUF _IOWR ('V', 9, struct v4l2_buffer)
+#define VIDIOC_G_FBUF _IOR ('V', 10, struct v4l2_framebuffer)
+#define VIDIOC_S_FBUF _IOW ('V', 11, struct v4l2_framebuffer)
+#define VIDIOC_OVERLAY _IOW ('V', 14, int)
+#define VIDIOC_QBUF _IOWR ('V', 15, struct v4l2_buffer)
+#define VIDIOC_DQBUF _IOWR ('V', 17, struct v4l2_buffer)
+#define VIDIOC_STREAMON _IOW ('V', 18, int)
+#define VIDIOC_STREAMOFF _IOW ('V', 19, int)
+#define VIDIOC_G_PARM _IOWR ('V', 21, struct v4l2_streamparm)
+#define VIDIOC_S_PARM _IOWR ('V', 22, struct v4l2_streamparm)
+#define VIDIOC_G_STD _IOR ('V', 23, v4l2_std_id)
+#define VIDIOC_S_STD _IOW ('V', 24, v4l2_std_id)
+#define VIDIOC_ENUMSTD _IOWR ('V', 25, struct v4l2_standard)
+#define VIDIOC_ENUMINPUT _IOWR ('V', 26, struct v4l2_input)
+#define VIDIOC_G_CTRL _IOWR ('V', 27, struct v4l2_control)
+#define VIDIOC_S_CTRL _IOWR ('V', 28, struct v4l2_control)
+#define VIDIOC_G_TUNER _IOWR ('V', 29, struct v4l2_tuner)
+#define VIDIOC_S_TUNER _IOW ('V', 30, struct v4l2_tuner)
+#define VIDIOC_G_AUDIO _IOR ('V', 33, struct v4l2_audio)
+#define VIDIOC_S_AUDIO _IOW ('V', 34, struct v4l2_audio)
+#define VIDIOC_QUERYCTRL _IOWR ('V', 36, struct v4l2_queryctrl)
+#define VIDIOC_QUERYMENU _IOWR ('V', 37, struct v4l2_querymenu)
+#define VIDIOC_G_INPUT _IOR ('V', 38, int)
+#define VIDIOC_S_INPUT _IOWR ('V', 39, int)
+#define VIDIOC_G_OUTPUT _IOR ('V', 46, int)
+#define VIDIOC_S_OUTPUT _IOWR ('V', 47, int)
+#define VIDIOC_ENUMOUTPUT _IOWR ('V', 48, struct v4l2_output)
+#define VIDIOC_G_AUDOUT _IOR ('V', 49, struct v4l2_audioout)
+#define VIDIOC_S_AUDOUT _IOW ('V', 50, struct v4l2_audioout)
+#define VIDIOC_G_MODULATOR _IOWR ('V', 54, struct v4l2_modulator)
+#define VIDIOC_S_MODULATOR _IOW ('V', 55, struct v4l2_modulator)
+#define VIDIOC_G_FREQUENCY _IOWR ('V', 56, struct v4l2_frequency)
+#define VIDIOC_S_FREQUENCY _IOW ('V', 57, struct v4l2_frequency)
+#define VIDIOC_CROPCAP _IOR ('V', 58, struct v4l2_cropcap)
+#define VIDIOC_G_CROP _IOWR ('V', 59, struct v4l2_crop)
+#define VIDIOC_S_CROP _IOW ('V', 60, struct v4l2_crop)
+#define VIDIOC_G_JPEGCOMP _IOR ('V', 61, struct v4l2_jpegcompression)
+#define VIDIOC_S_JPEGCOMP _IOW ('V', 62, struct v4l2_jpegcompression)
+#define VIDIOC_QUERYSTD _IOR ('V', 63, v4l2_std_id)
+#define VIDIOC_TRY_FMT _IOWR ('V', 64, struct v4l2_format)
+#define VIDIOC_ENUMAUDIO _IOWR ('V', 65, struct v4l2_audio)
+#define VIDIOC_ENUMAUDOUT _IOWR ('V', 66, struct v4l2_audioout)
+#define VIDIOC_G_PRIORITY _IOR ('V', 67, enum v4l2_priority)
+#define VIDIOC_S_PRIORITY _IOW ('V', 68, enum v4l2_priority)
+
+/* for compatibility, will go away some day */
+#define VIDIOC_OVERLAY_OLD _IOWR ('V', 14, int)
+#define VIDIOC_S_PARM_OLD _IOW ('V', 22, struct v4l2_streamparm)
+#define VIDIOC_S_CTRL_OLD _IOW ('V', 28, struct v4l2_control)
+#define VIDIOC_G_AUDIO_OLD _IOWR ('V', 33, struct v4l2_audio)
+#define VIDIOC_G_AUDOUT_OLD _IOWR ('V', 49, struct v4l2_audioout)
+
+#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */
+
+
+#ifdef __KERNEL__
+/*
+ *
+ * V 4 L 2 D R I V E R H E L P E R A P I
+ *
+ * Some commonly needed functions for drivers (v4l2-common.o module)
+ */
+#include <linux/fs.h>
+
+/* Video standard functions */
+extern unsigned int v4l2_video_std_fps(struct v4l2_standard *vs);
+extern int v4l2_video_std_construct(struct v4l2_standard *vs,
+ int id, char *name);
+
+/* prority handling */
+struct v4l2_prio_state {
+ atomic_t prios[4];
+};
+int v4l2_prio_init(struct v4l2_prio_state *global);
+int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local,
+ enum v4l2_priority new);
+int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local);
+int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local);
+enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global);
+int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
+
+/* names for fancy debug output */
+extern char *v4l2_field_names[];
+extern char *v4l2_type_names[];
+extern char *v4l2_ioctl_names[];
+
+/* Compatibility layer interface -- v4l1-compat module */
+typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg);
+int v4l_compat_translate_ioctl(struct inode *inode, struct file *file,
+ int cmd, void *arg, v4l2_kioctl driver_ioctl);
+
+#endif /* __KERNEL__ */
+#endif /* __LINUX_VIDEODEV2_H */
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/videodev.c
@@ -0,0 +1,332 @@
+/*
+ * Video capture interface for Linux Character Device Driver.
+ * based on
+ * Alan Cox, <alan@redhat.com> video4linux
+ *
+ * Author: SW.LEE <hitchcar@samsung.com>
+ * 2004 (C) Samsung Electronics
+ * Modified for S3C2440/S3C24A0 Interface
+ *
+ * This file is released under the GPLv2
+ */
+
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/smp_lock.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kmod.h>
+#include <linux/slab.h>
+/* #include <linux/devfs_fs_kernel.h> */
+#include <linux/miscdevice.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/semaphore.h>
+
+
+
+#define CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#include "camif.h"
+#include "miscdevice.h"
+
+
+static DECLARE_MUTEX(videodev_lock);
+
+const char *fimc_version = "$Id: videodev.c,v 1.1.1.1 2004/04/27 03:52:50 swlee Exp $";
+
+#define VIDEO_NAME "video4linux"
+
+
+#define VIDEO_NUM_DEVICES 2
+static struct video_device *video_device[VIDEO_NUM_DEVICES];
+
+static inline struct video_device * get_vd(int nr)
+{
+ if ( nr == CODEC_MINOR)
+ return video_device[0];
+ else {
+ assert ( nr & PREVIEW_MINOR);
+ return video_device[1];
+ }
+}
+
+static inline void set_vd ( struct video_device * vd, int nr)
+{
+ if ( nr == CODEC_MINOR)
+ video_device[0] = vd;
+ else {
+ assert ( nr & PREVIEW_MINOR);
+ video_device[1] = vd;
+ }
+}
+
+static inline int video_release(struct inode *inode, struct file *f)
+{
+ int minor = MINOR(inode->i_rdev);
+ struct video_device *vfd;
+
+ vfd = get_vd(minor);
+#if 1 /* needed until all drivers are fixed */
+ if (!vfd->release)
+ return 0;
+#endif
+ vfd->release(vfd);
+ return 0;
+}
+
+struct video_device* video_devdata(struct file *file)
+{
+ return video_device[iminor(file->f_dentry->d_inode)];
+}
+
+
+/*
+ * Open a video device.
+ */
+static int video_open(struct inode *inode, struct file *file)
+{
+ int minor = MINOR(inode->i_rdev);
+ int err = 0;
+ struct video_device *vfl;
+ struct file_operations const *old_fops;
+
+ down(&videodev_lock);
+
+ vfl = get_vd(minor);
+
+ old_fops = file->f_op;
+ file->f_op = fops_get(vfl->fops);
+ if(file->f_op->open)
+ err = file->f_op->open(inode,file);
+ if (err) {
+ fops_put(file->f_op);
+ file->f_op = fops_get(old_fops);
+ }
+ fops_put(old_fops);
+ up(&videodev_lock);
+ return err;
+}
+
+/*
+ * open/release helper functions -- handle exclusive opens
+ */
+extern int video_exclusive_open(struct inode *inode, struct file *file)
+{
+ struct video_device *vfl = get_vd(MINOR(inode->i_rdev));
+ int retval = 0;
+
+ mutex_lock(&vfl->lock);
+ if (vfl->users) {
+ retval = -EBUSY;
+ } else {
+ vfl->users++;
+ }
+ mutex_unlock(&vfl->lock);
+ return retval;
+}
+
+extern int video_exclusive_release(struct inode *inode, struct file *file)
+{
+ struct video_device *vfl = get_vd(MINOR(inode->i_rdev));
+ vfl->users--;
+ return 0;
+}
+
+int
+video_usercopy(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg,
+ int (*func)(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg))
+{
+ char sbuf[128];
+ void *mbuf = NULL;
+ void *parg = NULL;
+ int err = -EINVAL;
+
+ // cmd = video_fix_command(cmd);
+
+ /* Copy arguments into temp kernel buffer */
+ switch (_IOC_DIR(cmd)) {
+ case _IOC_NONE:
+ parg = (void *)arg;
+ break;
+ case _IOC_READ:
+ case _IOC_WRITE:
+ case (_IOC_WRITE | _IOC_READ):
+ if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
+ parg = sbuf;
+ } else {
+ /* too big to allocate from stack */
+ mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL);
+ if (NULL == mbuf)
+ return -ENOMEM;
+ parg = mbuf;
+ }
+
+ err = -EFAULT;
+ if (_IOC_DIR(cmd) & _IOC_WRITE)
+ if (copy_from_user(parg, (void *)arg, _IOC_SIZE(cmd)))
+ goto out;
+ break;
+ }
+
+ /* call driver */
+ err = func(inode, file, cmd, parg);
+ if (err == -ENOIOCTLCMD)
+ err = -EINVAL;
+ if (err < 0)
+ goto out;
+
+ /* Copy results into user buffer */
+ switch (_IOC_DIR(cmd))
+ {
+ case _IOC_READ:
+ case (_IOC_WRITE | _IOC_READ):
+ if (copy_to_user((void *)arg, parg, _IOC_SIZE(cmd)))
+ err = -EFAULT;
+ break;
+ }
+
+out:
+ if (mbuf)
+ kfree(mbuf);
+ return err;
+}
+
+
+static struct file_operations video_fops=
+{
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .open = video_open,
+ .release = video_release,
+};
+
+static struct miscdevice codec_dev = {
+ minor: CODEC_MINOR,
+ name : "codec",
+ fops : &video_fops
+};
+
+static struct miscdevice preview_dev = {
+ minor: PREVIEW_MINOR,
+ name : "preview",
+ fops : &video_fops
+};
+
+
+/**
+ * video_register_device - register video4linux devices
+ * @vfd: video device structure we want to register
+ * @type: type of device to register
+ * @nr: minor number
+ *
+ * Zero is returned on success.
+ * type : ignored.
+ * nr :
+ * 0 Codec index
+ * 1 Preview index
+ */
+int video_register_device(struct video_device *vfd, int type, int nr)
+{
+ int ret=0;
+
+ /* pick a minor number */
+ down(&videodev_lock);
+ set_vd (vfd, nr);
+ vfd->minor=nr;
+ up(&videodev_lock);
+
+ switch (vfd->minor) {
+ case CODEC_MINOR:
+ ret = misc_register(&codec_dev);
+ if (ret) {
+ printk(KERN_ERR
+ "can't misc_register : codec on minor=%d\n", CODEC_MINOR);
+ panic(" Give me misc codec \n");
+ }
+ break;
+ case PREVIEW_MINOR:
+ ret = misc_register(&preview_dev);
+ if (ret) {
+ printk(KERN_ERR
+ "can't misc_register (preview) on minor=%d\n", PREVIEW_MINOR);
+ panic(" Give me misc codec \n");
+ }
+ break;
+ }
+
+#if 0 /* needed until all drivers are fixed */
+ if (!vfd->release)
+ printk(KERN_WARNING "videodev: \"%s\" has no release callback. "
+ "Please fix your driver for proper sysfs support, see "
+ "http://lwn.net/Articles/36850/\n", vfd->name);
+#endif
+ return 0;
+}
+
+/**
+ * video_unregister_device - unregister a video4linux device
+ * @vfd: the device to unregister
+ *
+ * This unregisters the passed device and deassigns the minor
+ * number. Future open calls will be met with errors.
+ */
+
+void video_unregister_device(struct video_device *vfd)
+{
+ down(&videodev_lock);
+
+ if(get_vd(vfd->minor)!=vfd)
+ panic("videodev: bad unregister");
+
+ if (vfd->minor== CODEC_MINOR)
+ misc_deregister(&codec_dev);
+ else
+ misc_deregister(&preview_dev);
+ set_vd (NULL, vfd->minor);
+ up(&videodev_lock);
+}
+
+
+/*
+ * Initialise video for linux
+ */
+
+static int __init videodev_init(void)
+{
+// printk(KERN_INFO "FIMC2.0 Built:"__DATE__" "__TIME__"\n%s\n",fimc_version);
+ return 0;
+}
+
+static void __exit videodev_exit(void)
+{
+}
+
+module_init(videodev_init)
+module_exit(videodev_exit)
+
+EXPORT_SYMBOL(video_register_device);
+EXPORT_SYMBOL(fimc_version);
+EXPORT_SYMBOL(video_unregister_device);
+EXPORT_SYMBOL(video_usercopy);
+EXPORT_SYMBOL(video_exclusive_open);
+EXPORT_SYMBOL(video_exclusive_release);
+
+
+MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
+MODULE_DESCRIPTION("VideoDev For FIMC2.0 MISC Drivers");
+MODULE_LICENSE("GPL");
+
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/videodev.h
@@ -0,0 +1,108 @@
+//#ifndef __LINUX_S3C_VIDEODEV_H
+//#define __LINUX_S3C_VIDEODEV_H
+
+#include <linux/types.h>
+#include <linux/version.h>
+#include <media/v4l2-dev.h>
+
+#if 0
+struct video_device
+{
+ /* device info */
+ // struct device *dev;
+ char name[32];
+ int type; /* v4l1 */
+ int type2; /* v4l2 */
+ int hardware;
+ int minor;
+
+ /* device ops + callbacks */
+ struct file_operations *fops;
+ void (*release)(struct video_device *vfd);
+
+
+#if 1 /* to be removed in 2.7.x */
+ /* obsolete -- fops->owner is used instead */
+ struct module *owner;
+ /* dev->driver_data will be used instead some day.
+ * Use the video_{get|set}_drvdata() helper functions,
+ * so the switch over will be transparent for you.
+ * Or use {pci|usb}_{get|set}_drvdata() directly. */
+ void *priv;
+#endif
+
+ /* for videodev.c intenal usage -- please don't touch */
+ int users; /* video_exclusive_{open|close} ... */
+ struct semaphore lock; /* ... helper function uses these */
+ char devfs_name[64]; /* devfs */
+ // struct class_device class_dev; /* sysfs */
+};
+
+#define VIDEO_MAJOR 81
+
+#define VFL_TYPE_GRABBER 0
+
+
+extern int video_register_device(struct video_device *, int type, int nr);
+extern void video_unregister_device(struct video_device *);
+extern struct video_device* video_devdata(struct file*);
+
+
+
+struct video_picture
+{
+ __u16 brightness;
+ __u16 hue;
+ __u16 colour;
+ __u16 contrast;
+ __u16 whiteness; /* Black and white only */
+ __u16 depth; /* Capture depth */
+ __u16 palette; /* Palette in use */
+#define VIDEO_PALETTE_GREY 1 /* Linear greyscale */
+#define VIDEO_PALETTE_HI240 2 /* High 240 cube (BT848) */
+#define VIDEO_PALETTE_RGB565 3 /* 565 16 bit RGB */
+#define VIDEO_PALETTE_RGB24 4 /* 24bit RGB */
+#define VIDEO_PALETTE_RGB32 5 /* 32bit RGB */
+#define VIDEO_PALETTE_RGB555 6 /* 555 15bit RGB */
+#define VIDEO_PALETTE_YUV422 7 /* YUV422 capture */
+#define VIDEO_PALETTE_YUYV 8
+#define VIDEO_PALETTE_UYVY 9 /* The great thing about standards is ... */
+#define VIDEO_PALETTE_YUV420 10
+#define VIDEO_PALETTE_YUV411 11 /* YUV411 capture */
+#define VIDEO_PALETTE_RAW 12 /* RAW capture (BT848) */
+#define VIDEO_PALETTE_YUV422P 13 /* YUV 4:2:2 Planar */
+#define VIDEO_PALETTE_YUV411P 14 /* YUV 4:1:1 Planar */
+#define VIDEO_PALETTE_YUV420P 15 /* YUV 4:2:0 Planar */
+#define VIDEO_PALETTE_YUV410P 16 /* YUV 4:1:0 Planar */
+#define VIDEO_PALETTE_PLANAR 13 /* start of planar entries */
+#define VIDEO_PALETTE_COMPONENT 7 /* start of component entries */
+};
+
+extern int video_exclusive_open(struct inode *inode, struct file *file);
+extern int video_exclusive_release(struct inode *inode, struct file *file);
+extern int video_usercopy(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg,
+ int (*func)(struct inode *inode, struct file *file,
+ unsigned int cmd, void *arg));
+
+
+
+
+#define VID_TYPE_CAPTURE 1 /* Can capture */
+#define VID_TYPE_CLIPPING 32 /* Can clip */
+#define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */
+#define VID_TYPE_SCALES 128 /* Scalable */
+#define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */
+
+
+
+#endif
+//#endif
+
+#define VID_HARDWARE_SAMSUNG_FIMC 255
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- /dev/null
+++ b/arch/arm/mach-s3c2440/camera/video-driver.c
@@ -0,0 +1,624 @@
+/*
+ Copyright (C) 2004 Samsung Electronics
+ SW.LEE <hitchcar@sec.samsung.com>
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+*/
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/major.h>
+#include <linux/slab.h>
+#include <linux/poll.h>
+#include <linux/signal.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/irq.h>
+#include <asm/semaphore.h>
+#include <linux/miscdevice.h>
+#include <asm/arch/irqs.h>
+
+//#define SW_DEBUG
+#define CONFIG_VIDEO_V4L1_COMPAT
+#include <linux/videodev.h>
+#include "camif.h"
+#include "miscdevice.h"
+#include "cam_reg.h"
+#include "sensor.h"
+#include "userapp.h"
+
+#ifdef Z_API
+#include "qt.h"
+#endif
+
+/* Codec and Preview */
+#define CAMIF_NUM 2
+static camif_cfg_t fimc[CAMIF_NUM];
+u32 *camregs;
+
+static const char *driver_version =
+ "$Id: video-driver.c,v 1.9 2004/06/02 03:10:36 swlee Exp $";
+extern const char *fimc_version;
+extern const char *fsm_version;
+
+extern void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other);
+
+camif_cfg_t * get_camif(int nr)
+{
+ camif_cfg_t *ret = NULL;
+ switch(nr) {
+ case CODEC_MINOR:
+ ret = &fimc[0];
+ break;
+ case PREVIEW_MINOR:
+ ret = &fimc[1];
+ break;
+ default:
+ panic("Unknow Minor Number \n");
+ }
+ return ret;
+}
+
+
+static int camif_codec_start(camif_cfg_t *cfg)
+{
+ int ret = 0;
+ ret =camif_check_preview(cfg);
+ switch(ret) {
+ case 0: /* Play alone */
+ DPRINTK("Start Alone \n");
+ camif_4fsm_start(cfg);
+ cfg->gc->status |= C_WORKING;
+ break;
+ case -ERESTARTSYS: /* Busy , retry */
+ //DPRINTK("Error \n");
+ printk("Error \n");
+ break;
+ case 1:
+ DPRINTK("need callback \n");
+ ret = camif_callback_start(cfg);
+ if(ret < 0 ) {
+ printk(KERN_INFO "Busy RESTART \n");
+ return ret; /* Busy, retry */
+ }
+ break;
+ }
+ return ret;
+}
+
+
+ssize_t camif_write (struct file *f, const char *b, size_t c,loff_t *offset)
+{
+ camif_cfg_t *cfg;
+
+ c = 0; /* return value */
+ DPRINTK("\n");
+ cfg = get_camif(MINOR(f->f_dentry->d_inode->i_rdev));
+ switch (*b) {
+ case 'O':
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ if (cfg->gc->status & C_WORKING) {
+ camif_start_c_with_p(cfg,get_camif(CODEC_MINOR));
+ }
+ else {
+ camif_4fsm_start(cfg);
+ }
+ }
+ else{
+ c = camif_codec_start(cfg);
+ if(c < 0) c = 1; /* Error and neet to retry */
+ }
+
+ break;
+ case 'X':
+ camif_p_stop(cfg);
+ break;
+ default:
+ panic("CAMERA:camif_write: Unexpected Param\n");
+ }
+ DPRINTK("end\n");
+
+ return c;
+}
+
+
+ssize_t camif_p_read(struct file *file, char *buf, size_t count, loff_t *pos)
+{
+ camif_cfg_t *cfg = NULL;
+ size_t end;
+
+ cfg = get_camif(MINOR(file->f_dentry->d_inode->i_rdev));
+ cfg->status = CAMIF_STARTED;
+
+ if (wait_event_interruptible(cfg->waitq,cfg->status == CAMIF_INT_HAPPEN))
+ return -ERESTARTSYS;
+
+ cfg->status = CAMIF_STOPPED;
+ end = min_t(size_t, cfg->pp_totalsize /cfg->pp_num, count);
+ if (copy_to_user(buf, camif_g_frame(cfg), end))
+ return -EFAULT;
+
+ return end;
+}
+
+
+static ssize_t
+camif_c_read(struct file *file, char *buf, size_t count, loff_t *pos)
+{
+ camif_cfg_t *cfg = NULL;
+ size_t end;
+
+ /* cfg = file->private_data; */
+ cfg = get_camif(MINOR(file->f_dentry->d_inode->i_rdev));
+#if 0
+ if(file->f_flags & O_NONBLOCK) {
+ printk(KERN_ERR"Don't Support NON_BLOCK \n");
+ }
+#endif
+
+ /* Change the below wait_event_interruptible func */
+ if (wait_event_interruptible(cfg->waitq,cfg->status == CAMIF_INT_HAPPEN))
+ return -ERESTARTSYS;
+ cfg->status = CAMIF_STOPPED;
+ end = min_t(size_t, cfg->pp_totalsize /cfg->pp_num, count);
+ if (copy_to_user(buf, camif_g_frame(cfg), end))
+ return -EFAULT;
+ return end;
+}
+
+
+static irqreturn_t camif_c_irq(int irq, void *dev_id)
+{
+ camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
+
+ DPRINTK("\n");
+ camif_g_fifo_status(cfg);
+ camif_g_frame_num(cfg);
+ if(camif_enter_c_4fsm(cfg) != INSTANT_SKIP)
+ wake_up_interruptible(&cfg->waitq);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t camif_p_irq(int irq, void *dev_id)
+{
+ camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
+
+ DPRINTK("\n");
+ camif_g_fifo_status(cfg);
+ camif_g_frame_num(cfg);
+ if(camif_enter_p_4fsm(cfg) != INSTANT_SKIP)
+ wake_up_interruptible(&cfg->waitq);
+#if 0
+ if( (cfg->perf.frames % 5) == 0)
+ DPRINTK("5\n");
+#endif
+
+ return IRQ_HANDLED;
+}
+
+static void camif_release_irq(camif_cfg_t *cfg)
+{
+ disable_irq(cfg->irq);
+ free_irq(cfg->irq, cfg);
+}
+
+static int camif_irq_request(camif_cfg_t *cfg)
+{
+ int ret = 0;
+
+ if (cfg->dma_type & CAMIF_CODEC) {
+ if ((ret = request_irq(cfg->irq, camif_c_irq,
+ 0, cfg->shortname, cfg))) {
+ printk("request_irq(CAM_C) failed.\n");
+ }
+ }
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ if ((ret = request_irq(cfg->irq, camif_p_irq,
+ 0, cfg->shortname, cfg))) {
+ printk("request_irq(CAM_P) failed.\n");
+ }
+ }
+ return 0;
+}
+
+static void camif_init_sensor(camif_cfg_t *cfg)
+{
+ camif_gc_t *gc = cfg->gc;
+ if (!gc->sensor)
+ panic("CAMERA:I2C Client(Img Sensor)Not registered\n");
+ if(!gc->init_sensor) {
+ camif_reset(gc->reset_type, gc->reset_udelay);
+ gc->sensor->driver->command(gc->sensor,SENSOR_INIT,NULL);
+ gc->init_sensor = 1; /*sensor init done */
+ }
+ gc->sensor->driver->command(gc->sensor, USER_ADD, NULL);
+}
+
+static int camif_open(struct inode *inode, struct file *file)
+{
+ int err;
+ camif_cfg_t * cfg = get_camif(MINOR(inode->i_rdev));
+
+ if(cfg->dma_type & CAMIF_PREVIEW) {
+ if(down_interruptible(&cfg->gc->lock))
+ return -ERESTARTSYS;
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ cfg->gc->status &= ~PNOTWORKING;
+ }
+ up(&cfg->gc->lock);
+ }
+ err = video_exclusive_open(inode,file);
+ cfg->gc->user++;
+ cfg->status = CAMIF_STOPPED;
+ if (err < 0) return err;
+ if (file->f_flags & O_NONCAP ) {
+ printk("Don't Support Non-capturing open \n");
+ return 0;
+ }
+ file->private_data = cfg;
+ camif_irq_request(cfg);
+ camif_init_sensor(cfg);
+ return 0;
+}
+
+#if 0
+static void print_pregs(void)
+{
+ printk(" CISRCFMT 0x%08X \n", CISRCFMT);
+ printk(" CIWDOFST 0x%08X \n", CIWDOFST);
+ printk(" CIGCTRL 0x%08X \n", CIGCTRL);
+ printk(" CIPRTRGFMT 0x%08X \n", CIPRTRGFMT);
+ printk(" CIPRCTRL 0x%08X \n", CIPRCTRL);
+ printk(" CIPRSCPRERATIO 0x%08X \n", CIPRSCPRERATIO);
+ printk(" CIPRSCPREDST 0x%08X \n", CIPRSCPREDST);
+ printk(" CIPRSCCTRL 0x%08X \n", CIPRSCCTRL);
+ printk(" CIPRTAREA 0x%08X \n", CIPRTAREA);
+ printk(" CIPRSTATUS 0x%08X \n", CIPRSTATUS);
+ printk(" CIIMGCPT 0x%08X \n", CIIMGCPT);
+}
+
+static void print_cregs(void)
+{
+ printk(" CISRCFMT 0x%08X \n", CISRCFMT);
+ printk(" CIWDOFST 0x%08X \n", CIWDOFST);
+ printk(" CIGCTRL 0x%08X \n", CIGCTRL);
+ printk(" CICOCTRL 0x%8X \n", CICOCTRL);
+ printk(" CICOSCPRERATIO 0x%08X \n", CICOSCPRERATIO);
+ printk(" CICOSCPREDST 0x%08X \n", CICOSCPREDST);
+ printk(" CICOSCCTRL 0x%08X \n", CICOSCCTRL);
+ printk(" CICOTAREA 0x%08X \n", CICOTAREA);
+ printk(" CICOSTATUS 0x%8X \n", CICOSTATUS);
+ printk(" CIIMGCPT 0x%08X \n", CIIMGCPT);
+}
+#endif
+
+
+static int camif_release(struct inode *inode, struct file *file)
+{
+ camif_cfg_t * cfg = get_camif(MINOR(inode->i_rdev));
+
+ //DPRINTK(" cfg->status 0x%0X cfg->gc->status 0x%0X \n", cfg->status,cfg->gc->status );
+ if (cfg->dma_type & CAMIF_PREVIEW) {
+ if(down_interruptible(&cfg->gc->lock))
+ return -ERESTARTSYS;
+ cfg->gc->status &= ~PWANT2START;
+ cfg->gc->status |= PNOTWORKING;
+ up(&cfg->gc->lock);
+ }
+ else {
+ cfg->gc->status &= ~CWANT2START; /* No need semaphore */
+ }
+ camif_dynamic_close(cfg);
+ camif_release_irq(cfg);
+ video_exclusive_release(inode,file);
+ camif_p_stop(cfg);
+ cfg->gc->sensor->driver->command(cfg->gc->sensor, USER_EXIT, NULL);
+ cfg->gc->user--;
+ cfg->status = CAMIF_STOPPED;
+ return 0;
+}
+
+static void fimc_config(camif_cfg_t *cfg,u32 x, u32 y, int bpp)
+{
+ cfg->target_x = x;
+ cfg->target_y = y;
+
+ switch (bpp) {
+ case 16:
+ cfg->fmt = CAMIF_RGB16;
+ break;
+ case 24:
+ cfg->fmt = CAMIF_RGB24;
+ break;
+ case 420:
+ cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
+ break;
+ case 422:
+ cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR422;
+ break;
+ default:
+ panic("Wrong BPP \n");
+ }
+}
+
+
+static int
+camif_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ int ret = 0;
+ camif_cfg_t *cfg = file->private_data;
+ camif_param_t par;
+
+ switch (cmd) {
+ case CMD_CAMERA_INIT:
+ if (copy_from_user(&par,(camif_param_t *)arg,
+ sizeof(camif_param_t)))
+ return -EFAULT;
+ fimc_config(cfg,par.dst_x, par.dst_y, par.bpp);
+ if (camif_dynamic_open(cfg)) {
+ printk(" Eror Happens \n");
+ ret = -1;
+ }
+
+ switch (par.flip) {
+ case 3 :
+ cfg->flip = CAMIF_FLIP_MIRROR;
+ break;
+ case 1 :
+ cfg->flip = CAMIF_FLIP_X;
+ break;
+ case 2 :
+ cfg->flip = CAMIF_FLIP_Y;
+ break;
+ case 0 :
+ default:
+ cfg->flip = CAMIF_FLIP;
+ }
+ break;
+ /* Todo
+ case CMD_SENSOR_BRIGHTNESS:
+ cfg->gc->sensor->driver->command(cfg->gc->sensor, SENSOR_BRIGHTNESS, NULL);
+ break;
+ */
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+
+#if 0
+static int camif_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+// camif_cfg_t *cfg = file->private_data;
+
+
+ switch (cmd) {
+/* case Some_other_action */
+ default:
+ return video_usercopy(inode, file, cmd, arg, camif_do_ioctl);
+ }
+}
+#endif
+
+static struct file_operations camif_c_fops =
+{
+ .owner = THIS_MODULE,
+ .open = camif_open,
+ .release = camif_release,
+ .ioctl = camif_ioctl,
+ .read = camif_c_read,
+ .write = camif_write,
+};
+
+static struct file_operations camif_p_fops =
+{
+ .owner = THIS_MODULE,
+ .open = camif_open,
+ .release = camif_release,
+ .ioctl = camif_ioctl,
+#ifdef Z_API
+ .read = z_read,
+ .write = z_write,
+#else
+ .read = camif_p_read,
+ .write = camif_write,
+#endif
+};
+
+static struct video_device codec_template =
+{
+ .name = "CODEC_IF",
+ .type = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
+/* .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
+ .fops = &camif_c_fops,
+// .release = camif_release
+ .minor = -1,
+};
+
+static struct video_device preview_template =
+{
+ .name = "PREVIEW_IF",
+ .type = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
+/* .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
+ .fops = &camif_p_fops,
+ .minor = -1,
+};
+
+static int preview_init(camif_cfg_t *cfg)
+{
+ char name[16]="CAM_PREVIEW";
+
+ memset(cfg, 0, sizeof(camif_cfg_t));
+ cfg->target_x = 640;
+ cfg->target_y = 480;
+ cfg->pp_num = 4;
+ cfg->dma_type = CAMIF_PREVIEW;
+ cfg->fmt = CAMIF_RGB16;
+ cfg->flip = CAMIF_FLIP_Y;
+ cfg->v = &preview_template;
+ mutex_init(&cfg->v->lock);
+ cfg->irq = IRQ_S3C2440_CAM_P;
+
+ strcpy(cfg->shortname,name);
+ init_waitqueue_head(&cfg->waitq);
+ cfg->status = CAMIF_STOPPED;
+ return cfg->status;
+}
+
+static int codec_init(camif_cfg_t *cfg)
+{
+ char name[16]="CAM_CODEC";
+
+ memset(cfg, 0, sizeof(camif_cfg_t));
+ cfg->target_x = 176;
+ cfg->target_y = 144;
+ cfg->pp_num = 4;
+ cfg->dma_type = CAMIF_CODEC;
+ cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
+ cfg->flip = CAMIF_FLIP_X;
+ cfg->v = &codec_template;
+ mutex_init(&cfg->v->lock);
+ cfg->irq = IRQ_S3C2440_CAM_C;
+ strcpy(cfg->shortname,name);
+ init_waitqueue_head(&cfg->waitq);
+ cfg->status = CAMIF_STOPPED;
+ return cfg->status;
+}
+
+static void camif_init(void)
+{
+ camif_setup_sensor();
+}
+
+
+
+static void print_version(void)
+{
+ printk(KERN_INFO"FIMC built:"__DATE__ " "__TIME__"\n%s\n%s\n%s\n",
+ fimc_version, driver_version,fsm_version);
+}
+
+
+static int camif_m_in(void)
+{
+ int ret = -EINVAL;
+ camif_cfg_t * cfg;
+
+ printk(KERN_INFO"Starting S3C2440 Camera Driver\n");
+
+ camregs = ioremap(CAM_BASE_ADD, 0x100);
+ if (!camregs) {
+ printk(KERN_ERR"Unable to map camera regs\n");
+ ret = -ENOMEM;
+ goto bail1;
+ }
+
+ camif_init();
+ cfg = get_camif(CODEC_MINOR);
+ codec_init(cfg);
+
+ ret = video_register_device(cfg->v,0,CODEC_MINOR);
+ if (ret) {
+ printk(KERN_ERR"Couldn't register codec driver.\n");
+ goto bail2;
+ }
+ cfg = get_camif(PREVIEW_MINOR);
+ preview_init(cfg);
+ ret = video_register_device(cfg->v,0,PREVIEW_MINOR);
+ if (ret) {
+ printk(KERN_ERR"Couldn't register preview driver.\n");
+ goto bail3; /* hm seems it us unregistered the once */
+ }
+
+ print_version();
+ return 0;
+
+bail3:
+ video_unregister_device(cfg->v);
+bail2:
+ iounmap(camregs);
+ camregs = NULL;
+bail1:
+ return ret;
+}
+
+static void unconfig_device(camif_cfg_t *cfg)
+{
+ video_unregister_device(cfg->v);
+ camif_hw_close(cfg);
+ iounmap(camregs);
+ //memset(cfg, 0, sizeof(camif_cfg_t));
+ camregs = NULL;
+}
+
+static void camif_m_out(void) /* module out */
+{
+ camif_cfg_t *cfg;
+
+ cfg = get_camif(CODEC_MINOR);
+ unconfig_device(cfg);
+ cfg = get_camif(PREVIEW_MINOR);
+ unconfig_device(cfg);
+
+ return;
+}
+
+void camif_register_decoder(struct i2c_client *ptr)
+{
+ camif_cfg_t *cfg;
+ void * data = i2c_get_clientdata(ptr);
+
+ cfg =get_camif(CODEC_MINOR);
+ cfg->gc = (camif_gc_t *)(data);
+
+ cfg =get_camif(PREVIEW_MINOR);
+ cfg->gc = (camif_gc_t *)(data);
+
+ sema_init(&cfg->gc->lock, 1); /* global lock for both Codec and Preview */
+ cfg->gc->status |= PNOTWORKING; /* Default Value */
+ camif_hw_open(cfg->gc);
+}
+
+void camif_unregister_decoder(struct i2c_client *ptr)
+{
+ camif_gc_t *gc;
+ void * data = i2c_get_clientdata(ptr);
+
+ gc = (camif_gc_t *)(data);
+ gc->init_sensor = 0; /* need to modify */
+}
+
+module_init(camif_m_in);
+module_exit(camif_m_out);
+
+EXPORT_SYMBOL(camif_register_decoder);
+EXPORT_SYMBOL(camif_unregister_decoder);
+
+MODULE_AUTHOR("SW.LEE <hitchcar@sec.samsung.com>");
+MODULE_DESCRIPTION("Video-Driver For Fimc2.0 MISC Drivers");
+MODULE_LICENSE("GPL");
+
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -25,12 +25,12 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
[DMACH_XD0] = {
--- /dev/null
+++ b/arch/arm/mach-s3c2440/fiq_c_isr.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2007 Andy Green <andy@warmcat.com>
+ * S3C modfifications
+ * Copyright 2008 Andy Green <andy@openmoko.com>
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <mach/hardware.h>
+#include <asm/fiq.h>
+#include "fiq_c_isr.h"
+#include <linux/sysfs.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+
+#include <plat/cpu.h>
+#include <plat/irq.h>
+
+#include <mach/pwm.h>
+#include <plat/regs-timer.h>
+
+/*
+ * Major Caveats for using FIQ
+ * ---------------------------
+ *
+ * 1) it CANNOT touch any vmalloc()'d memory, only memory
+ * that was kmalloc()'d. Static allocations in the monolithic kernel
+ * are kmalloc()'d so they are okay. You can touch memory-mapped IO, but
+ * the pointer for it has to have been stored in kmalloc'd memory. The
+ * reason for this is simple: every now and then Linux turns off interrupts
+ * and reorders the paging tables. If a FIQ happens during this time, the
+ * virtual memory space can be partly or entirely disordered or missing.
+ *
+ * 2) Because vmalloc() is used when a module is inserted, THIS FIQ
+ * ISR HAS TO BE IN THE MONOLITHIC KERNEL, not a module. But the way
+ * it is set up, you can all to enable and disable it from your module
+ * and intercommunicate with it through struct fiq_ipc
+ * fiq_ipc which you can define in
+ * asm/archfiq_ipc_type.h. The reason is the same as above, a
+ * FIQ could happen while even the ISR is not present in virtual memory
+ * space due to pagetables being changed at the time.
+ *
+ * 3) You can't call any Linux API code except simple macros
+ * - understand that FIQ can come in at any time, no matter what
+ * state of undress the kernel may privately be in, thinking it
+ * locked the door by turning off interrupts... FIQ is an
+ * unstoppable monster force (which is its value)
+ * - they are not vmalloc()'d memory safe
+ * - they might do crazy stuff like sleep: FIQ pisses fire and
+ * is not interested in 'sleep' that the weak seem to need
+ * - calling APIs from FIQ can re-enter un-renterable things
+ * - summary: you cannot interoperate with linux APIs directly in the FIQ ISR
+ *
+ * If you follow these rules, it is fantastic, an extremely powerful, solid,
+ * genuine hard realtime feature.
+ *
+ */
+
+/* more than enough to cover our jump instruction to the isr */
+#define SIZEOF_FIQ_JUMP 4
+
+#define FIQ_VECTOR 0xffff001c
+
+/* we put the stack at the area after the FIQ vector */
+#define FIQ_STACK_SIZE 256
+
+/* only one FIQ ISR possible, okay to do these here */
+u32 _fiq_ack_mask; /* used by isr exit define */
+unsigned long _fiq_count_fiqs; /* used by isr exit define */
+static int _fiq_irq; /* private ; irq index we were started with, or 0 */
+struct s3c2410_pwm pwm_timer_fiq;
+int _fiq_timer_index;
+u16 _fiq_timer_divisor;
+u8 fiq_ready;
+
+/* this function must live in the monolithic kernel somewhere! A module is
+ * NOT good enough!
+ */
+extern void __attribute__ ((naked)) s3c2440_fiq_isr(void);
+
+static void fiq_set_vector_and_regs(void);
+
+
+/* this is copied into the hard FIQ vector during init */
+
+static void __attribute__ ((naked)) s3c2440_FIQ_Branch(void)
+{
+ asm __volatile__ (
+ "mov pc, r8 ; "
+ );
+}
+
+/* sysfs */
+
+static ssize_t show_count(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%ld\n", _fiq_count_fiqs);
+}
+
+static DEVICE_ATTR(count, 0444, show_count, NULL);
+
+static struct attribute *s3c2440_fiq_sysfs_entries[] = {
+ &dev_attr_count.attr,
+ NULL
+};
+
+static struct attribute_group s3c2440_fiq_attr_group = {
+ .name = "fiq",
+ .attrs = s3c2440_fiq_sysfs_entries,
+};
+
+/*
+ * call this from your kernel module to set up the FIQ ISR to service FIQs,
+ * You need to have configured your FIQ input pin before anything will happen
+ *
+ * call it with, eg, IRQ_TIMER3 from asm-arm/arch-s3c2410/irqs.h
+ *
+ * you still need to clear the source interrupt in S3C2410_INTMSK to get
+ * anything good happening
+ */
+static int fiq_init_irq_source(int irq_index_fiq)
+{
+ int rc = 0;
+
+ if (!irq_index_fiq) /* no interrupt */
+ goto bail;
+
+ local_fiq_disable();
+
+ _fiq_irq = irq_index_fiq;
+ _fiq_ack_mask = 1 << (irq_index_fiq - S3C2410_CPUIRQ_OFFSET);
+ _fiq_timer_index = (irq_index_fiq - IRQ_TIMER0);
+
+ /* set up the timer to operate as a pwm device */
+
+ rc = s3c2410_pwm_init(&pwm_timer_fiq);
+ if (rc)
+ goto bail;
+
+ pwm_timer_fiq.timerid = PWM0 + _fiq_timer_index;
+ pwm_timer_fiq.prescaler = (6 - 1) / 2;
+ pwm_timer_fiq.divider = S3C2410_TCFG1_MUX3_DIV2;
+ /* default rate == ~32us */
+ pwm_timer_fiq.counter = pwm_timer_fiq.comparer = 3000;
+
+ rc = s3c2410_pwm_enable(&pwm_timer_fiq);
+ if (rc)
+ goto bail;
+
+ s3c2410_pwm_start(&pwm_timer_fiq);
+
+ _fiq_timer_divisor = 0xffff; /* so kick will work initially */
+
+ /* let our selected interrupt be a magic FIQ interrupt */
+ __raw_writel(_fiq_ack_mask, S3C2410_INTMOD);
+
+ /* it's ready to go as soon as we unmask the source in S3C2410_INTMSK */
+ local_fiq_enable();
+bail:
+ return rc;
+}
+
+
+/* call this from your kernel module to disable generation of FIQ actions */
+static void fiq_disable_irq_source(void)
+{
+ /* nothing makes FIQ any more */
+ __raw_writel(0, S3C2410_INTMOD);
+ local_fiq_disable();
+ _fiq_irq = 0; /* no active source interrupt now either */
+}
+
+/*
+ * fiq_kick() forces a FIQ event to happen shortly after leaving the routine
+ */
+void fiq_kick(void)
+{
+ unsigned long flags;
+ u32 tcon;
+
+ if (!fiq_ready) {
+ printk(KERN_ERR "fiq_kick called before fiq probed\n");
+ return;
+ }
+
+ /* we have to take care about FIQ because this modification is
+ * non-atomic, FIQ could come in after the read and before the
+ * writeback and its changes to the register would be lost
+ * (platform INTMSK mod code is taken care of already)
+ */
+ local_save_flags(flags);
+ local_fiq_disable();
+ /* allow FIQs to resume */
+ __raw_writel(__raw_readl(S3C2410_INTMSK) &
+ ~(1 << (_fiq_irq - S3C2410_CPUIRQ_OFFSET)),
+ S3C2410_INTMSK);
+ tcon = __raw_readl(S3C2410_TCON) & ~S3C2410_TCON_T3START;
+ /* fake the timer to a count of 1 */
+ __raw_writel(1, S3C2410_TCNTB(_fiq_timer_index));
+ __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD, S3C2410_TCON);
+ __raw_writel(tcon | S3C2410_TCON_T3MANUALUPD | S3C2410_TCON_T3START,
+ S3C2410_TCON);
+ __raw_writel(tcon | S3C2410_TCON_T3START, S3C2410_TCON);
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL_GPL(fiq_kick);
+
+
+
+
+static int __init sc32440_fiq_probe(struct platform_device *pdev)
+{
+ struct resource *r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ struct sc32440_fiq_platform_data *pdata = pdev->dev.platform_data;
+ int ret;
+
+ if (!r)
+ return -EIO;
+
+ /* configure for the interrupt we are meant to use */
+ printk(KERN_INFO "Enabling FIQ using irq %d\n", r->start);
+
+ fiq_set_vector_and_regs();
+ fiq_init_irq_source(r->start);
+
+ ret = sysfs_create_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
+ if (ret)
+ return ret;
+
+ fiq_ready = 1;
+
+ /*
+ * if wanted, users can defer registration of devices
+ * that depend on FIQ until after we register, and can use our
+ * device as parent so suspend-resume ordering is correct
+ */
+ if (pdata->attach_child_devices)
+ (pdata->attach_child_devices)(&pdev->dev);
+
+ return 0;
+}
+
+static int sc32440_fiq_remove(struct platform_device *pdev)
+{
+ fiq_disable_irq_source();
+ sysfs_remove_group(&pdev->dev.kobj, &s3c2440_fiq_attr_group);
+
+ return 0;
+}
+
+static void fiq_set_vector_and_regs(void)
+{
+ struct pt_regs regs;
+
+ /* prep the special FIQ mode regs */
+ memset(&regs, 0, sizeof(regs));
+ regs.ARM_r8 = (unsigned long)s3c2440_fiq_isr;
+ regs.ARM_r10 = FIQ_VECTOR + SIZEOF_FIQ_JUMP;
+ regs.ARM_sp = FIQ_VECTOR + SIZEOF_FIQ_JUMP + FIQ_STACK_SIZE - 4;
+
+ /* copy our jump to the real ISR into the hard vector address */
+ set_fiq_handler(s3c2440_FIQ_Branch, SIZEOF_FIQ_JUMP);
+
+ /* set up the special FIQ-mode-only registers from our regs */
+ set_fiq_regs(&regs);
+}
+
+#ifdef CONFIG_PM
+static int sc32440_fiq_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ /* nothing makes FIQ any more */
+ __raw_writel(0, S3C2410_INTMOD);
+ local_fiq_disable();
+
+ return 0;
+}
+
+static int sc32440_fiq_resume(struct platform_device *pdev)
+{
+ fiq_set_vector_and_regs();
+ fiq_init_irq_source(_fiq_irq);
+ return 0;
+}
+#else
+#define sc32440_fiq_suspend NULL
+#define sc32440_fiq_resume NULL
+#endif
+
+static struct platform_driver sc32440_fiq_driver = {
+ .driver = {
+ .name = "sc32440_fiq",
+ .owner = THIS_MODULE,
+ },
+
+ .probe = sc32440_fiq_probe,
+ .remove = __devexit_p(sc32440_fiq_remove),
+ .suspend = sc32440_fiq_suspend,
+ .resume = sc32440_fiq_resume,
+};
+
+static int __init sc32440_fiq_init(void)
+{
+ fiq_set_vector_and_regs();
+
+ return platform_driver_register(&sc32440_fiq_driver);
+}
+
+static void __exit sc32440_fiq_exit(void)
+{
+ fiq_disable_irq_source();
+}
+
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_LICENSE("GPL");
+
+module_init(sc32440_fiq_init);
+module_exit(sc32440_fiq_exit);
--- /dev/null
+++ b/arch/arm/mach-s3c2440/fiq_c_isr.h
@@ -0,0 +1,76 @@
+#ifndef _LINUX_FIQ_C_ISR_H
+#define _LINUX_FIQ_C_ISR_H
+
+#include <mach/regs-irq.h>
+#include <linux/platform_device.h>
+
+extern unsigned long _fiq_count_fiqs;
+extern u32 _fiq_ack_mask;
+extern int _fiq_timer_index;
+extern u16 _fiq_timer_divisor;
+
+/* platform data */
+
+struct sc32440_fiq_platform_data {
+ /*
+ * give an opportunity to use us as parent for
+ * devices that depend on us
+ */
+ void (*attach_child_devices)(struct device *parent_device);
+};
+
+/* This CANNOT be implemented in a module -- it has to be used in code
+ * included in the monolithic kernel
+ */
+
+#define FIQ_HANDLER_START() \
+void __attribute__ ((naked)) s3c2440_fiq_isr(void) \
+{\
+ /*\
+ * you can declare local vars here, take care to set the frame size\
+ * below accordingly if there are more than a few dozen bytes of them\
+ */\
+
+/* stick your locals here :-)
+ * Do NOT initialize them here! define them and initialize them after
+ * FIQ_HANDLER_ENTRY() is done.
+ */
+
+#define FIQ_HANDLER_ENTRY(LOCALS, FRAME) \
+ const int _FIQ_FRAME_SIZE = FRAME; \
+ /* entry takes care to store registers we will be treading on here */\
+ asm __volatile__ (\
+ /* stash FIQ and r0-r8 normal regs */\
+ "stmdb sp!, {r0-r12, lr};"\
+ /* allow SP to get some space */\
+ "sub sp, sp, %1 ;"\
+ /* !! THIS SETS THE FRAME, adjust to > sizeof locals */\
+ "sub fp, sp, %0 ;"\
+ :\
+ : "rI" (LOCALS), "rI" (FRAME)\
+ :"r9"\
+ );
+
+/* stick your ISR code here and then end with... */
+
+#define FIQ_HANDLER_END() \
+ _fiq_count_fiqs++;\
+ __raw_writel(_fiq_ack_mask, S3C2410_SRCPND);\
+\
+ /* exit back to normal mode restoring everything */\
+ asm __volatile__ (\
+ /* pop our allocation */\
+ "add sp, sp, %0 ;"\
+ /* return FIQ regs back to pristine state\
+ * and get normal regs back\
+ */\
+ "ldmia sp!, {r0-r12, lr};"\
+\
+ /* return */\
+ "subs pc, lr, #4;"\
+ : \
+ : "rI" (_FIQ_FRAME_SIZE) \
+ );\
+}
+
+#endif /* _LINUX_FIQ_C_ISR_H */
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -22,12 +22,20 @@
help
Support for S3C2440 specific DMA code5A
+config S3C2440_C_FIQ
+ bool "FIQ ISR support in C"
+ depends on ARCH_S3C2410
+ select FIQ
+ help
+ Support for S3C2440 FIQ support in C -- see
+ ./arch/arm/mach-s3c2440/fiq_c_isr.c
menu "S3C2440 Machines"
config MACH_ANUBIS
bool "Simtec Electronics ANUBIS"
select CPU_S3C2440
+ select S3C24XX_DCLK
select PM_SIMTEC if PM
select HAVE_PATA_PLATFORM
help
@@ -37,6 +45,7 @@
config MACH_OSIRIS
bool "Simtec IM2440D20 (OSIRIS) module"
select CPU_S3C2440
+ select S3C24XX_DCLK
select PM_SIMTEC if PM
help
Say Y here if you are using the Simtec IM2440D20 module, also
@@ -74,5 +83,30 @@
help
Say Y here if you are using the AT2440EVB development board
+config MACH_NEO1973_GTA02
+ bool "FIC Neo1973 GSM Phone (GTA02 Hardware)"
+ select CPU_S3C2442
+ select MFD_PCF50633
+ select INPUT_PCF50633_PMU
+ select PCF50633_ADC
+ select PCF50633_GPIO
+ select RTC_DRV_PCF50633
+ select REGULATOR_PCF50633
+ select CHARGER_PCF50633
+ select POWER_SUPPLY
+ select GTA02_HDQ
+ select MACH_NEO1973
+ help
+ Say Y here if you are using the FIC Neo1973 GSM Phone
+
+config NEO1973_GTA02_2440
+ bool "Old FIC Neo1973 GTA02 hardware using S3C2440 CPU"
+ depends on MACH_NEO1973_GTA02
+ select CPU_S3C2440
+ help
+ Say Y here if you are using an early hardware revision
+ of the FIC/Openmoko Neo1973 GTA02 GSM Phone.
+
endmenu
+#source "arch/arm/mach-s3c2440/camera/Kconfig"
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -39,7 +39,8 @@
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@@ -404,7 +405,7 @@
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&anubis_device_ide0,
@@ -468,6 +469,7 @@
static void __init anubis_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
i2c_register_board_info(0, anubis_i2c_devs,
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -35,7 +35,8 @@
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@@ -166,7 +167,7 @@
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&at2440evb_device_eth,
@@ -183,6 +184,7 @@
static void __init at2440evb_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
}
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -0,0 +1,1778 @@
+/*
+ * linux/arch/arm/mach-s3c2440/mach-gta02.c
+ *
+ * S3C2440 Machine Support for the FIC GTA02 (Neo1973)
+ *
+ * Copyright (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/glamo.h>
+#include <linux/spi/spi_bitbang.h>
+#include <linux/mmc/host.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+
+#include <linux/i2c.h>
+#include <linux/backlight.h>
+#include <linux/regulator/machine.h>
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/led.h>
+
+#include <linux/lis302dl.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/io.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/fb.h>
+#include <mach/mci.h>
+#include <mach/ts.h>
+#include <mach/spi.h>
+#include <mach/spi-gpio.h>
+#include <mach/usb-control.h>
+#include <mach/regs-mem.h>
+
+#include <mach/gta02.h>
+
+#include <plat/regs-serial.h>
+#include <plat/nand.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/udc.h>
+#include <plat/iic.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+#include <mach/neo1973-pm-gsm.h>
+#include <mach/gta02-pm-wlan.h>
+
+#include <linux/jbt6k74.h>
+
+#include <linux/glamofb.h>
+
+#include <mach/fiq_ipc_gta02.h>
+#include "fiq_c_isr.h"
+#include <linux/gta02_hdq.h>
+#include <linux/bq27000_battery.h>
+
+#include <linux/i2c.h>
+
+#include "../plat-s3c24xx/neo1973_pm_gps.h"
+
+#include <linux/ts_filter_linear.h>
+#include <linux/ts_filter_mean.h>
+#include <linux/ts_filter_median.h>
+#include <linux/ts_filter_group.h>
+
+/* arbitrates which sensor IRQ owns the shared SPI bus */
+static spinlock_t motion_irq_lock;
+
+/* define FIQ IPC struct */
+/*
+ * contains stuff FIQ ISR modifies and normal kernel code can see and use
+ * this is defined in <arch/arm/mach-s3c2410/include/mach/fiq_ipc_gta02.h>, you should customize
+ * the definition in there and include the same definition in your kernel
+ * module that wants to interoperate with your FIQ code.
+ */
+struct fiq_ipc fiq_ipc;
+EXPORT_SYMBOL(fiq_ipc);
+
+#define DIVISOR_FROM_US(x) ((x) << 3)
+
+#define FIQ_DIVISOR_VIBRATOR DIVISOR_FROM_US(100)
+
+#ifdef CONFIG_GTA02_HDQ
+/* HDQ specific */
+#define HDQ_SAMPLE_PERIOD_US 20
+/* private HDQ FSM state -- all other info interesting for caller in fiq_ipc */
+static enum hdq_bitbang_states hdq_state;
+static u8 hdq_ctr;
+static u8 hdq_ctr2;
+static u8 hdq_bit;
+static u8 hdq_shifter;
+static u8 hdq_tx_data_done;
+
+#define FIQ_DIVISOR_HDQ DIVISOR_FROM_US(HDQ_SAMPLE_PERIOD_US)
+#endif
+/* define FIQ ISR */
+
+FIQ_HANDLER_START()
+/* define your locals here -- no initializers though */
+ u16 divisor;
+FIQ_HANDLER_ENTRY(64, 64)
+/* Your ISR here :-) */
+ divisor = 0xffff;
+
+ /* Vibrator servicing */
+
+ if (fiq_ipc.vib_pwm_latched || fiq_ipc.vib_pwm) { /* not idle */
+ if (((u8)_fiq_count_fiqs) == fiq_ipc.vib_pwm_latched)
+ neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 0);
+ if (((u8)_fiq_count_fiqs) == 0) {
+ fiq_ipc.vib_pwm_latched = fiq_ipc.vib_pwm;
+ if (fiq_ipc.vib_pwm_latched)
+ neo1973_gpb_setpin(fiq_ipc.vib_gpio_pin, 1);
+ }
+ divisor = FIQ_DIVISOR_VIBRATOR;
+ }
+
+#ifdef CONFIG_GTA02_HDQ
+ /* HDQ servicing */
+
+ switch (hdq_state) {
+ case HDQB_IDLE:
+ if (fiq_ipc.hdq_request_ctr == fiq_ipc.hdq_transaction_ctr)
+ break;
+ hdq_ctr = 210 / HDQ_SAMPLE_PERIOD_US;
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
+ s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
+ hdq_tx_data_done = 0;
+ hdq_state = HDQB_TX_BREAK;
+ break;
+
+ case HDQB_TX_BREAK: /* issue low for > 190us */
+ if (--hdq_ctr == 0) {
+ hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
+ hdq_state = HDQB_TX_BREAK_RECOVERY;
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
+ }
+ break;
+
+ case HDQB_TX_BREAK_RECOVERY: /* issue low for > 40us */
+ if (--hdq_ctr)
+ break;
+ hdq_shifter = fiq_ipc.hdq_ads;
+ hdq_bit = 8; /* 8 bits of ads / rw */
+ hdq_tx_data_done = 0; /* doing ads */
+ /* fallthru on last one */
+ case HDQB_ADS_CALC:
+ if (hdq_shifter & 1)
+ hdq_ctr = 50 / HDQ_SAMPLE_PERIOD_US;
+ else
+ hdq_ctr = 120 / HDQ_SAMPLE_PERIOD_US;
+ /* carefully precompute the other phase length */
+ hdq_ctr2 = (210 - (hdq_ctr * HDQ_SAMPLE_PERIOD_US)) /
+ HDQ_SAMPLE_PERIOD_US;
+ hdq_state = HDQB_ADS_LOW;
+ hdq_shifter >>= 1;
+ hdq_bit--;
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
+ break;
+
+ case HDQB_ADS_LOW:
+ if (--hdq_ctr)
+ break;
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
+ hdq_state = HDQB_ADS_HIGH;
+ break;
+
+ case HDQB_ADS_HIGH:
+ if (--hdq_ctr2 > 1) /* account for HDQB_ADS_CALC */
+ break;
+ if (hdq_bit) { /* more bits to do */
+ hdq_state = HDQB_ADS_CALC;
+ break;
+ }
+ /* no more bits, wait it out until hdq_ctr2 exhausted */
+ if (hdq_ctr2)
+ break;
+ /* ok no more bits and very last state */
+ hdq_ctr = 60 / HDQ_SAMPLE_PERIOD_US;
+ /* FIXME 0 = read */
+ if (fiq_ipc.hdq_ads & 0x80) { /* write the byte out */
+ /* set delay before payload */
+ hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
+ /* already high, no need to write */
+ hdq_state = HDQB_WAIT_TX;
+ break;
+ }
+ /* read the next byte */
+ hdq_bit = 8; /* 8 bits of data */
+ hdq_ctr = 3000 / HDQ_SAMPLE_PERIOD_US;
+ hdq_state = HDQB_WAIT_RX;
+ s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT);
+ break;
+
+ case HDQB_WAIT_TX: /* issue low for > 40us */
+ if (--hdq_ctr)
+ break;
+ if (!hdq_tx_data_done) { /* was that the data sent? */
+ hdq_tx_data_done++;
+ hdq_shifter = fiq_ipc.hdq_tx_data;
+ hdq_bit = 8; /* 8 bits of data */
+ hdq_state = HDQB_ADS_CALC; /* start sending */
+ break;
+ }
+ fiq_ipc.hdq_error = 0;
+ fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
+ hdq_state = HDQB_IDLE; /* all tx is done */
+ /* idle in input mode, it's pulled up by 10K */
+ s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_INPUT);
+ break;
+
+ case HDQB_WAIT_RX: /* wait for battery to talk to us */
+ if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin) == 0) {
+ /* it talks to us! */
+ hdq_ctr2 = 1;
+ hdq_bit = 8; /* 8 bits of data */
+ /* timeout */
+ hdq_ctr = 300 / HDQ_SAMPLE_PERIOD_US;
+ hdq_state = HDQB_DATA_RX_LOW;
+ break;
+ }
+ if (--hdq_ctr == 0) { /* timed out, error */
+ fiq_ipc.hdq_error = 1;
+ fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
+ hdq_state = HDQB_IDLE; /* abort */
+ }
+ break;
+
+ /*
+ * HDQ basically works by measuring the low time of the bit cell
+ * 32-50us --> '1', 80 - 145us --> '0'
+ */
+
+ case HDQB_DATA_RX_LOW:
+ if (s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) {
+ fiq_ipc.hdq_rx_data >>= 1;
+ if (hdq_ctr2 <= (65 / HDQ_SAMPLE_PERIOD_US))
+ fiq_ipc.hdq_rx_data |= 0x80;
+
+ if (--hdq_bit == 0) {
+ fiq_ipc.hdq_error = 0;
+ fiq_ipc.hdq_transaction_ctr =
+ fiq_ipc.hdq_request_ctr;
+
+ hdq_state = HDQB_IDLE;
+ } else
+ hdq_state = HDQB_DATA_RX_HIGH;
+ /* timeout */
+ hdq_ctr = 1000 / HDQ_SAMPLE_PERIOD_US;
+ hdq_ctr2 = 1;
+ break;
+ }
+ hdq_ctr2++;
+ if (--hdq_ctr)
+ break;
+ /* timed out, error */
+ fiq_ipc.hdq_error = 2;
+ fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
+ hdq_state = HDQB_IDLE; /* abort */
+ break;
+
+ case HDQB_DATA_RX_HIGH:
+ if (!s3c2410_gpio_getpin(fiq_ipc.hdq_gpio_pin)) {
+ /* it talks to us! */
+ hdq_ctr2 = 1;
+ /* timeout */
+ hdq_ctr = 400 / HDQ_SAMPLE_PERIOD_US;
+ hdq_state = HDQB_DATA_RX_LOW;
+ break;
+ }
+ if (--hdq_ctr)
+ break;
+ /* timed out, error */
+ fiq_ipc.hdq_error = 3;
+ fiq_ipc.hdq_transaction_ctr = fiq_ipc.hdq_request_ctr;
+
+ /* we're in input mode already */
+ hdq_state = HDQB_IDLE; /* abort */
+ break;
+ }
+
+ if (hdq_state != HDQB_IDLE) /* ie, not idle */
+ if (divisor > FIQ_DIVISOR_HDQ)
+ divisor = FIQ_DIVISOR_HDQ; /* keep us going */
+#endif
+
+ /* disable further timer interrupts if nobody has any work
+ * or adjust rate according to who still has work
+ *
+ * CAUTION: it means forground code must disable FIQ around
+ * its own non-atomic S3C2410_INTMSK changes... not common
+ * thankfully and taken care of by the fiq-basis patch
+ */
+ if (divisor == 0xffff) /* mask the fiq irq source */
+ __raw_writel(__raw_readl(S3C2410_INTMSK) | _fiq_ack_mask,
+ S3C2410_INTMSK);
+ else /* still working, maybe at a different rate */
+ __raw_writel(divisor, S3C2410_TCNTB(_fiq_timer_index));
+ _fiq_timer_divisor = divisor;
+
+FIQ_HANDLER_END()
+
+
+/*
+ * this gets called every 1ms when we paniced.
+ */
+
+static long gta02_panic_blink(long count)
+{
+ long delay = 0;
+ static long last_blink;
+ static char led;
+
+ if (count - last_blink < 100) /* 200ms period, fast blink */
+ return 0;
+
+ led ^= 1;
+ s3c2410_gpio_cfgpin(GTA02_GPIO_AUX_LED, S3C2410_GPIO_OUTPUT);
+ neo1973_gpb_setpin(GTA02_GPIO_AUX_LED, led);
+
+ last_blink = count;
+ return delay;
+}
+
+
+/**
+ * returns PCB revision information in b9,b8 and b2,b1,b0
+ * Pre-GTA02 A6 returns 0x000
+ * GTA02 A6 returns 0x101
+ * ...
+ */
+
+int gta02_get_pcb_revision(void)
+{
+ int n;
+ int u = 0;
+ static unsigned long pinlist[] = {
+ GTA02_PCB_ID1_0,
+ GTA02_PCB_ID1_1,
+ GTA02_PCB_ID1_2,
+ GTA02_PCB_ID2_0,
+ GTA02_PCB_ID2_1,
+ };
+ static int pin_offset[] = {
+ 0, 1, 2, 8, 9
+ };
+
+ for (n = 0 ; n < ARRAY_SIZE(pinlist); n++) {
+ /*
+ * set the PCB version GPIO to be pulled-down input
+ * force low briefly first
+ */
+ s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_setpin(pinlist[n], 0);
+ /* misnomer: it is a pullDOWN in 2442 */
+ s3c2410_gpio_pullup(pinlist[n], 1);
+ s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_INPUT);
+
+ udelay(10);
+
+ if (s3c2410_gpio_getpin(pinlist[n]))
+ u |= 1 << pin_offset[n];
+
+ /*
+ * when not being interrogated, all of the revision GPIO
+ * are set to output HIGH without pulldown so no current flows
+ * if they are NC or pulled up.
+ */
+ s3c2410_gpio_setpin(pinlist[n], 1);
+ s3c2410_gpio_cfgpin(pinlist[n], S3C2410_GPIO_OUTPUT);
+ /* misnomer: it is a pullDOWN in 2442 */
+ s3c2410_gpio_pullup(pinlist[n], 0);
+ }
+
+ return u;
+}
+
+struct platform_device gta02_version_device = {
+ .name = "neo1973-version",
+ .num_resources = 0,
+};
+
+struct platform_device gta02_resume_reason_device = {
+ .name = "neo1973-resume",
+ .num_resources = 0,
+};
+
+struct platform_device gta02_memconfig_device = {
+ .name = "neo1973-memconfig",
+ .num_resources = 0,
+};
+
+static struct map_desc gta02_iodesc[] __initdata = {
+ {
+ .virtual = 0xe0000000,
+ .pfn = __phys_to_pfn(S3C2410_CS3+0x01000000),
+ .length = SZ_1M,
+ .type = MT_DEVICE
+ },
+};
+
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg gta02_uartcfgs[] = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+
+};
+
+/* BQ27000 Battery */
+
+static int gta02_get_charger_online_status(void)
+{
+ struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
+
+ return pcf->mbc.usb_online;
+}
+
+static int gta02_get_charger_active_status(void)
+{
+ struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
+
+ return pcf->mbc.usb_active;
+}
+
+
+struct bq27000_platform_data bq27000_pdata = {
+ .name = "battery",
+ .rsense_mohms = 20,
+ .hdq_read = gta02hdq_read,
+ .hdq_write = gta02hdq_write,
+ .hdq_initialized = gta02hdq_initialized,
+ .get_charger_online_status = gta02_get_charger_online_status,
+ .get_charger_active_status = gta02_get_charger_active_status
+};
+
+struct platform_device bq27000_battery_device = {
+ .name = "bq27000-battery",
+ .dev = {
+ .platform_data = &bq27000_pdata,
+ },
+};
+
+#define ADC_NOM_CHG_DETECT_1A 6
+#define ADC_NOM_CHG_DETECT_USB 43
+
+static void
+gta02_configure_pmu_for_charger(struct pcf50633 *pcf, void *unused, int res)
+{
+ int ma;
+
+ /* Interpret charger type */
+ if (res < ((ADC_NOM_CHG_DETECT_USB + ADC_NOM_CHG_DETECT_1A) / 2)) {
+
+ /* Stop GPO driving out now that we have a IA charger */
+ pcf50633_gpio_set(pcf, PCF50633_GPO, 0);
+
+ ma = 1000;
+ } else
+ ma = 100;
+
+ pcf50633_mbc_usb_curlim_set(pcf, ma);
+}
+
+static struct delayed_work gta02_charger_work;
+static int gta02_usb_vbus_draw;
+
+static void gta02_charger_worker(struct work_struct *work)
+{
+ struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
+
+ if (gta02_usb_vbus_draw) {
+ pcf50633_mbc_usb_curlim_set(pcf, gta02_usb_vbus_draw);
+ return;
+ } else {
+ pcf50633_adc_async_read(pcf,
+ PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16,
+ gta02_configure_pmu_for_charger, NULL);
+ return;
+ }
+}
+
+#define GTA02_CHARGER_CONFIGURE_TIMEOUT ((3000 * HZ) / 1000)
+static void gta02_pmu_event_callback(struct pcf50633 *pcf, int irq)
+{
+ if (irq == PCF50633_IRQ_USBINS) {
+ schedule_delayed_work(&gta02_charger_work,
+ GTA02_CHARGER_CONFIGURE_TIMEOUT);
+ return;
+ } else if (irq == PCF50633_IRQ_USBREM) {
+ cancel_delayed_work_sync(&gta02_charger_work);
+ gta02_usb_vbus_draw = 0;
+ }
+}
+
+static struct platform_device gta01_pm_gps_dev = {
+ .name = "neo1973-pm-gps",
+};
+
+static struct platform_device gta01_pm_bt_dev = {
+ .name = "neo1973-pm-bt",
+};
+
+static struct platform_device gta02_pm_gsm_dev = {
+ .name = "neo1973-pm-gsm",
+};
+
+/* this is called when pc50633 is probed, unfortunately quite late in the
+ * day since it is an I2C bus device. Here we can belatedly define some
+ * platform devices with the advantage that we can mark the pcf50633 as the
+ * parent. This makes them get suspended and resumed with their parent
+ * the pcf50633 still around.
+ */
+
+static struct platform_device gta02_glamo_dev;
+static void mangle_glamo_res_by_system_rev(void);
+
+static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);
+static void gta02_pmu_regulator_registered(struct pcf50633 *pcf, int id);
+
+static struct platform_device gta02_pm_wlan_dev = {
+ .name = "gta02-pm-wlan",
+};
+
+static struct regulator_consumer_supply ldo4_consumers[] = {
+ {
+ .dev = &gta01_pm_bt_dev.dev,
+ .supply = "BT_3V2",
+ },
+};
+
+static struct regulator_consumer_supply ldo5_consumers[] = {
+ {
+ .dev = &gta01_pm_gps_dev.dev,
+ .supply = "RF_3V",
+ },
+};
+
+/*
+ * We need this dummy thing to fill the regulator consumers
+ */
+static struct platform_device gta02_mmc_dev = {
+ /* details filled in by glamo core */
+};
+
+static struct regulator_consumer_supply hcldo_consumers[] = {
+ {
+ .dev = &gta02_mmc_dev.dev,
+ .supply = "SD_3V3",
+ },
+};
+
+static char *gta02_batteries[] = {
+ "battery",
+};
+
+struct pcf50633_platform_data gta02_pcf_pdata = {
+ .resumers = {
+ [0] = PCF50633_INT1_USBINS |
+ PCF50633_INT1_USBREM |
+ PCF50633_INT1_ALARM,
+ [1] = PCF50633_INT2_ONKEYF,
+ [2] = PCF50633_INT3_ONKEY1S,
+ [3] = PCF50633_INT4_LOWSYS |
+ PCF50633_INT4_LOWBAT |
+ PCF50633_INT4_HIGHTMP,
+ },
+
+ .batteries = gta02_batteries,
+ .num_batteries = ARRAY_SIZE(gta02_batteries),
+
+ .reg_init_data = {
+ [PCF50633_REGULATOR_AUTO] = {
+ .constraints = {
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .boot_on = 1,
+ .apply_uV = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_DOWN1] = {
+ .constraints = {
+ .min_uV = 1300000,
+ .max_uV = 1600000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .boot_on = 1,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_DOWN2] = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ .boot_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_HCLDO] = {
+ .constraints = {
+ .min_uV = 2000000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .boot_on = 1,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = hcldo_consumers,
+ },
+ [PCF50633_REGULATOR_LDO1] = {
+ .constraints = {
+ .min_uV = 1300000,
+ .max_uV = 1300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_LDO2] = {
+ .constraints = {
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_LDO3] = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_LDO4] = {
+ .constraints = {
+ .min_uV = 3200000,
+ .max_uV = 3200000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = ldo4_consumers,
+ },
+ [PCF50633_REGULATOR_LDO5] = {
+ .constraints = {
+ .min_uV = 1500000,
+ .max_uV = 1500000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = ldo5_consumers,
+ },
+ [PCF50633_REGULATOR_LDO6] = {
+ .constraints = {
+ .min_uV = 0,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ },
+ .num_consumer_supplies = 0,
+ },
+ [PCF50633_REGULATOR_MEMLDO] = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+
+ },
+ .probe_done = gta02_pmu_attach_child_devices,
+ .regulator_registered = gta02_pmu_regulator_registered,
+ .mbc_event_callback = gta02_pmu_event_callback,
+};
+
+static void mangle_pmu_pdata_by_system_rev(void)
+{
+ struct regulator_init_data *reg_init_data;
+
+ reg_init_data = gta02_pcf_pdata.reg_init_data;
+
+ switch (system_rev) {
+ case GTA02v1_SYSTEM_REV:
+ /* FIXME: this is only in v1 due to wrong PMU variant */
+ reg_init_data[PCF50633_REGULATOR_DOWN2]
+ .constraints.state_mem.enabled = 1;
+ break;
+ case GTA02v2_SYSTEM_REV:
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ reg_init_data[PCF50633_REGULATOR_LDO1]
+ .constraints.min_uV = 3300000;
+ reg_init_data[PCF50633_REGULATOR_LDO1]
+ .constraints.min_uV = 3300000;
+ reg_init_data[PCF50633_REGULATOR_LDO1]
+ .constraints.state_mem.enabled = 0;
+
+ reg_init_data[PCF50633_REGULATOR_LDO5]
+ .constraints.min_uV = 3000000;
+ reg_init_data[PCF50633_REGULATOR_LDO5]
+ .constraints.max_uV = 3000000;
+
+ reg_init_data[PCF50633_REGULATOR_LDO6]
+ .constraints.min_uV = 3000000;
+ reg_init_data[PCF50633_REGULATOR_LDO6]
+ .constraints.max_uV = 3000000;
+ reg_init_data[PCF50633_REGULATOR_LDO6]
+ .constraints.apply_uV = 1;
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef CONFIG_GTA02_HDQ
+/* HDQ */
+
+static void gta02_hdq_attach_child_devices(struct device *parent_device)
+{
+ switch (system_rev) {
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ bq27000_battery_device.dev.parent = parent_device;
+ platform_device_register(&bq27000_battery_device);
+ break;
+ default:
+ break;
+ }
+}
+
+static struct resource gta02_hdq_resources[] = {
+ [0] = {
+ .start = GTA02v5_GPIO_HDQ,
+ .end = GTA02v5_GPIO_HDQ,
+ },
+};
+
+struct gta02_hdq_platform_data gta02_hdq_platform_data = {
+ .attach_child_devices = gta02_hdq_attach_child_devices
+};
+
+struct platform_device gta02_hdq_device = {
+ .name = "gta02-hdq",
+ .num_resources = 1,
+ .resource = gta02_hdq_resources,
+ .dev = {
+ .platform_data = &gta02_hdq_platform_data,
+ },
+};
+#endif
+
+/* vibrator (child of FIQ) */
+
+static struct resource gta02_vibrator_resources[] = {
+ [0] = {
+ .start = GTA02_GPIO_VIBRATOR_ON,
+ .end = GTA02_GPIO_VIBRATOR_ON,
+ },
+};
+
+static struct platform_device gta02_vibrator_dev = {
+ .name = "neo1973-vibrator",
+ .num_resources = ARRAY_SIZE(gta02_vibrator_resources),
+ .resource = gta02_vibrator_resources,
+};
+
+/* FIQ, used PWM regs, so not child of PWM */
+
+static void gta02_fiq_attach_child_devices(struct device *parent_device)
+{
+#ifdef CONFIG_GTA02_HDQ
+ switch (system_rev) {
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ gta02_hdq_device.dev.parent = parent_device;
+ platform_device_register(&gta02_hdq_device);
+ gta02_vibrator_dev.dev.parent = parent_device;
+ platform_device_register(&gta02_vibrator_dev);
+ break;
+ default:
+ break;
+ }
+#endif
+}
+
+
+static struct resource sc32440_fiq_resources[] = {
+ [0] = {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_TIMER3,
+ .end = IRQ_TIMER3,
+ },
+};
+
+struct sc32440_fiq_platform_data gta02_sc32440_fiq_platform_data = {
+ .attach_child_devices = gta02_fiq_attach_child_devices
+};
+
+struct platform_device sc32440_fiq_device = {
+ .name = "sc32440_fiq",
+ .num_resources = 1,
+ .resource = sc32440_fiq_resources,
+ .dev = {
+ .platform_data = &gta02_sc32440_fiq_platform_data,
+ },
+};
+
+/* NOR Flash */
+
+#define GTA02_FLASH_BASE 0x18000000 /* GCS3 */
+#define GTA02_FLASH_SIZE 0x200000 /* 2MBytes */
+
+static struct physmap_flash_data gta02_nor_flash_data = {
+ .width = 2,
+};
+
+static struct resource gta02_nor_flash_resource = {
+ .start = GTA02_FLASH_BASE,
+ .end = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device gta02_nor_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &gta02_nor_flash_data,
+ },
+ .resource = &gta02_nor_flash_resource,
+ .num_resources = 1,
+};
+
+
+struct platform_device s3c24xx_pwm_device = {
+ .name = "s3c24xx_pwm",
+ .num_resources = 0,
+};
+
+static struct i2c_board_info gta02_i2c_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("pcf50633", 0x73),
+ .irq = GTA02_IRQ_PCF50633,
+ .platform_data = &gta02_pcf_pdata,
+ },
+};
+
+static struct s3c2410_nand_set gta02_nand_sets[] = {
+ [0] = {
+ .name = "neo1973-nand",
+ .nr_chips = 1,
+ .flags = S3C2410_NAND_BBT,
+ },
+};
+
+/* choose a set of timings derived from S3C@2442B MCP54
+ * data sheet (K5D2G13ACM-D075 MCP Memory)
+ */
+
+static struct s3c2410_platform_nand gta02_nand_info = {
+ .tacls = 0,
+ .twrph0 = 25,
+ .twrph1 = 15,
+ .nr_sets = ARRAY_SIZE(gta02_nand_sets),
+ .sets = gta02_nand_sets,
+ .software_ecc = 1,
+};
+
+
+static void gta02_s3c_mmc_set_power(unsigned char power_mode,
+ unsigned short vdd)
+{
+ gta02_wlan_power(
+ power_mode == MMC_POWER_ON ||
+ power_mode == MMC_POWER_UP);
+}
+
+
+static struct s3c24xx_mci_pdata gta02_s3c_mmc_cfg = {
+ .set_power = gta02_s3c_mmc_set_power,
+};
+
+static void gta02_udc_command(enum s3c2410_udc_cmd_e cmd)
+{
+ switch (cmd) {
+ case S3C2410_UDC_P_ENABLE:
+ printk(KERN_DEBUG "%s S3C2410_UDC_P_ENABLE\n", __func__);
+ neo1973_gpb_setpin(GTA02_GPIO_USB_PULLUP, 1);
+ break;
+ case S3C2410_UDC_P_DISABLE:
+ printk(KERN_DEBUG "%s S3C2410_UDC_P_DISABLE\n", __func__);
+ neo1973_gpb_setpin(GTA02_GPIO_USB_PULLUP, 0);
+ break;
+ case S3C2410_UDC_P_RESET:
+ printk(KERN_DEBUG "%s S3C2410_UDC_P_RESET\n", __func__);
+ /* FIXME! */
+ break;
+ default:
+ break;
+ }
+}
+
+/* get PMU to set USB current limit accordingly */
+
+static void gta02_udc_vbus_draw(unsigned int ma)
+{
+ if (!gta02_pcf_pdata.pcf) {
+ printk(KERN_ERR "********** NULL gta02_pcf_pdata.pcf *****\n");
+ return;
+ }
+
+ gta02_usb_vbus_draw = ma;
+
+ schedule_delayed_work(&gta02_charger_work,
+ GTA02_CHARGER_CONFIGURE_TIMEOUT);
+}
+
+static struct s3c2410_udc_mach_info gta02_udc_cfg = {
+ .vbus_draw = gta02_udc_vbus_draw,
+ .udc_command = gta02_udc_command,
+
+};
+
+
+/* touchscreen configuration */
+
+static struct ts_filter_linear_configuration gta02_ts_linear_config = {
+ .constants = {1, 0, 0, 0, 1, 0, 1}, /* don't modify coords */
+ .coord0 = 0,
+ .coord1 = 1,
+};
+
+static struct ts_filter_group_configuration gta02_ts_group_config = {
+ .extent = 12,
+ .close_enough = 10,
+ .threshold = 6, /* at least half of the points in a group */
+ .attempts = 10,
+};
+
+static struct ts_filter_median_configuration gta02_ts_median_config = {
+ .extent = 20,
+ .decimation_below = 3,
+ .decimation_threshold = 8 * 3,
+ .decimation_above = 4,
+};
+
+static struct ts_filter_mean_configuration gta02_ts_mean_config = {
+ .bits_filter_length = 2, /* 4 points */
+};
+
+static struct s3c2410_ts_mach_info gta02_ts_cfg = {
+ .delay = 10000,
+ .presc = 0xff, /* slow as we can go */
+ .filter_sequence = {
+ [0] = &ts_filter_group_api,
+ [1] = &ts_filter_median_api,
+ [2] = &ts_filter_mean_api,
+ [3] = &ts_filter_linear_api,
+ },
+ .filter_config = {
+ [0] = &gta02_ts_group_config,
+ [1] = &gta02_ts_median_config,
+ [2] = &gta02_ts_mean_config,
+ [3] = &gta02_ts_linear_config,
+ },
+};
+
+
+static void gta02_bl_set_intensity(int intensity)
+{
+ struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
+ int old_intensity = pcf50633_reg_read(pcf, PCF50633_REG_LEDOUT);
+ int ret;
+
+ intensity >>= 2;
+
+ if (intensity == old_intensity)
+ return;
+
+ /* We can't do this anywhere else */
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 5);
+
+ if (!(pcf50633_reg_read(pcf, PCF50633_REG_LEDENA) & 3))
+ old_intensity = 0;
+
+ /*
+ * The PCF50633 cannot handle LEDOUT = 0 (datasheet p60)
+ * if seen, you have to re-enable the LED unit
+ */
+ if (!intensity || !old_intensity)
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0);
+
+ if (!intensity) /* illegal to set LEDOUT to 0 */
+ ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
+ 2);
+ else
+ ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_LEDOUT, 0x3f,
+ intensity);
+
+ if (intensity)
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 2);
+
+}
+
+static struct generic_bl_info gta02_bl_info = {
+ .name = "gta02-bl",
+ .max_intensity = 0xff,
+ .default_intensity = 0xff,
+ .set_bl_intensity = gta02_bl_set_intensity,
+};
+
+static struct platform_device gta02_bl_dev = {
+ .name = "generic-bl",
+ .id = 1,
+ .dev = {
+ .platform_data = &gta02_bl_info,
+ },
+};
+
+/* SPI: LCM control interface attached to Glamo3362 */
+
+static void gta02_jbt6k74_reset(int devidx, int level)
+{
+ glamo_lcm_reset(level);
+}
+
+static void gta02_jbt6k74_probe_completed(struct device *dev)
+{
+ struct pcf50633 *pcf = gta02_pcf_pdata.pcf;
+
+ /* Switch on backlight. Qi does not do it for us */
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x01);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
+
+ gta02_bl_dev.dev.parent = dev;
+ platform_device_register(&gta02_bl_dev);
+}
+
+const struct jbt6k74_platform_data jbt6k74_pdata = {
+ .reset = gta02_jbt6k74_reset,
+ .probe_completed = gta02_jbt6k74_probe_completed,
+};
+
+static struct spi_board_info gta02_spi_board_info[] = {
+ {
+ .modalias = "jbt6k74",
+ /* platform_data */
+ .platform_data = &jbt6k74_pdata,
+ /* controller_data */
+ /* irq */
+ .max_speed_hz = 100 * 1000,
+ .bus_num = 2,
+ /* chip_select */
+ },
+};
+
+#if 0 /* currently this is not used and we use gpio spi */
+static struct glamo_spi_info glamo_spi_cfg = {
+ .board_size = ARRAY_SIZE(gta02_spi_board_info),
+ .board_info = gta02_spi_board_info,
+};
+#endif /* 0 */
+
+static struct glamo_spigpio_info glamo_spigpio_cfg = {
+ .pin_clk = GLAMO_GPIO10_OUTPUT,
+ .pin_mosi = GLAMO_GPIO11_OUTPUT,
+ .pin_cs = GLAMO_GPIO12_OUTPUT,
+ .pin_miso = 0,
+ .board_size = ARRAY_SIZE(gta02_spi_board_info),
+ .board_info = gta02_spi_board_info,
+};
+
+/* SPI: Accelerometers attached to SPI of s3c244x */
+
+/*
+ * Situation is that Linux SPI can't work in an interrupt context, so we
+ * implement our own bitbang here. Arbitration is needed because not only
+ * can this interrupt happen at any time even if foreground wants to use
+ * the bitbang API from Linux, but multiple motion sensors can be on the
+ * same SPI bus, and multiple interrupts can happen.
+ *
+ * Foreground / interrupt arbitration is okay because the interrupts are
+ * disabled around all the foreground SPI code.
+ *
+ * Interrupt / Interrupt arbitration is evidently needed, otherwise we
+ * lose edge-triggered service after a while due to the two sensors sharing
+ * the SPI bus having irqs at the same time eventually.
+ *
+ * Servicing is typ 75 - 100us at 400MHz.
+ */
+
+/* #define DEBUG_SPEW_MS */
+#define MG_PER_SAMPLE 18
+
+struct lis302dl_platform_data lis302_pdata_top;
+struct lis302dl_platform_data lis302_pdata_bottom;
+
+/*
+ * generic SPI RX and TX bitbang
+ * only call with interrupts off!
+ */
+
+static void __gta02_lis302dl_bitbang(struct lis302dl_info *lis, u8 *tx,
+ int tx_bytes, u8 *rx, int rx_bytes)
+{
+ struct lis302dl_platform_data *pdata = lis->pdata;
+ int n;
+ u8 shifter = 0;
+ unsigned long other_cs;
+
+ /*
+ * Huh... "quirk"... CS on this device is not really "CS" like you can
+ * expect.
+ *
+ * When it is 0 it selects SPI interface mode.
+ * When it is 1 it selects I2C interface mode.
+ *
+ * Because we have 2 devices on one interface we have to make sure
+ * that the "disabled" device (actually in I2C mode) don't think we're
+ * talking to it.
+ *
+ * When we talk to the "enabled" device, the "disabled" device sees
+ * the clocks as I2C clocks, creating havoc.
+ *
+ * I2C sees MOSI going LOW while CLK HIGH as a START action, thus we
+ * must ensure this is never issued.
+ */
+
+ if (&lis302_pdata_top == pdata)
+ other_cs = lis302_pdata_bottom.pin_chip_select;
+ else
+ other_cs = lis302_pdata_top.pin_chip_select;
+
+ s3c2410_gpio_setpin(other_cs, 1);
+ s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
+ s3c2410_gpio_setpin(pdata->pin_clk, 1);
+ s3c2410_gpio_setpin(pdata->pin_chip_select, 0);
+
+ /* send the register index, r/w and autoinc bits */
+ for (n = 0; n < (tx_bytes << 3); n++) {
+ if (!(n & 7))
+ shifter = ~tx[n >> 3];
+ s3c2410_gpio_setpin(pdata->pin_clk, 0);
+ s3c2410_gpio_setpin(pdata->pin_mosi, !(shifter & 0x80));
+ s3c2410_gpio_setpin(pdata->pin_clk, 1);
+ shifter <<= 1;
+ }
+
+ for (n = 0; n < (rx_bytes << 3); n++) { /* 8 bits each */
+ s3c2410_gpio_setpin(pdata->pin_clk, 0);
+ shifter <<= 1;
+ if (s3c2410_gpio_getpin(pdata->pin_miso))
+ shifter |= 1;
+ if ((n & 7) == 7)
+ rx[n >> 3] = shifter;
+ s3c2410_gpio_setpin(pdata->pin_clk, 1);
+ }
+ s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
+ s3c2410_gpio_setpin(other_cs, 1);
+}
+
+
+static int gta02_lis302dl_bitbang_read_reg(struct lis302dl_info *lis, u8 reg)
+{
+ u8 data = 0xc0 | reg; /* read, autoincrement */
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ __gta02_lis302dl_bitbang(lis, &data, 1, &data, 1);
+
+ local_irq_restore(flags);
+
+ return data;
+}
+
+static void gta02_lis302dl_bitbang_write_reg(struct lis302dl_info *lis, u8 reg,
+ u8 val)
+{
+ u8 data[2] = { 0x00 | reg, val }; /* write, no autoincrement */
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ __gta02_lis302dl_bitbang(lis, &data[0], 2, NULL, 0);
+
+ local_irq_restore(flags);
+
+}
+
+
+void gta02_lis302dl_suspend_io(struct lis302dl_info *lis, int resume)
+{
+ struct lis302dl_platform_data *pdata = lis->pdata;
+
+ if (!resume) {
+ /*
+ * we don't want to power them with a high level
+ * because GSENSOR_3V3 is not up during suspend
+ */
+ s3c2410_gpio_setpin(pdata->pin_chip_select, 0);
+ s3c2410_gpio_setpin(pdata->pin_clk, 0);
+ s3c2410_gpio_setpin(pdata->pin_mosi, 0);
+ /* misnomer: it is a pullDOWN in 2442 */
+ s3c2410_gpio_pullup(pdata->pin_miso, 1);
+ return;
+ }
+
+ /* back to normal */
+ s3c2410_gpio_setpin(pdata->pin_chip_select, 1);
+ s3c2410_gpio_setpin(pdata->pin_clk, 1);
+ /* misnomer: it is a pullDOWN in 2442 */
+ s3c2410_gpio_pullup(pdata->pin_miso, 0);
+
+ s3c2410_gpio_cfgpin(pdata->pin_chip_select, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(pdata->pin_clk, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(pdata->pin_mosi, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(pdata->pin_miso, S3C2410_GPIO_INPUT);
+
+}
+
+
+
+struct lis302dl_platform_data lis302_pdata_top = {
+ .name = "lis302-1 (top)",
+ .pin_chip_select= S3C2410_GPD12,
+ .pin_clk = S3C2410_GPG7,
+ .pin_mosi = S3C2410_GPG6,
+ .pin_miso = S3C2410_GPG5,
+ .interrupt = GTA02_IRQ_GSENSOR_1,
+ .open_drain = 1, /* altered at runtime by PCB rev */
+ .lis302dl_bitbang = __gta02_lis302dl_bitbang,
+ .lis302dl_bitbang_reg_read = gta02_lis302dl_bitbang_read_reg,
+ .lis302dl_bitbang_reg_write = gta02_lis302dl_bitbang_write_reg,
+ .lis302dl_suspend_io = gta02_lis302dl_suspend_io,
+};
+
+struct lis302dl_platform_data lis302_pdata_bottom = {
+ .name = "lis302-2 (bottom)",
+ .pin_chip_select= S3C2410_GPD13,
+ .pin_clk = S3C2410_GPG7,
+ .pin_mosi = S3C2410_GPG6,
+ .pin_miso = S3C2410_GPG5,
+ .interrupt = GTA02_IRQ_GSENSOR_2,
+ .open_drain = 1, /* altered at runtime by PCB rev */
+ .lis302dl_bitbang = __gta02_lis302dl_bitbang,
+ .lis302dl_bitbang_reg_read = gta02_lis302dl_bitbang_read_reg,
+ .lis302dl_bitbang_reg_write = gta02_lis302dl_bitbang_write_reg,
+ .lis302dl_suspend_io = gta02_lis302dl_suspend_io,
+};
+
+
+static struct platform_device s3c_device_spi_acc1 = {
+ .name = "lis302dl",
+ .id = 1,
+ .dev = {
+ .platform_data = &lis302_pdata_top,
+ },
+};
+
+static struct platform_device s3c_device_spi_acc2 = {
+ .name = "lis302dl",
+ .id = 2,
+ .dev = {
+ .platform_data = &lis302_pdata_bottom,
+ },
+};
+
+static struct resource gta02_led_resources[] = {
+ {
+ .name = "gta02-power:orange",
+ .start = GTA02_GPIO_PWR_LED1,
+ .end = GTA02_GPIO_PWR_LED1,
+ }, {
+ .name = "gta02-power:blue",
+ .start = GTA02_GPIO_PWR_LED2,
+ .end = GTA02_GPIO_PWR_LED2,
+ }, {
+ .name = "gta02-aux:red",
+ .start = GTA02_GPIO_AUX_LED,
+ .end = GTA02_GPIO_AUX_LED,
+ },
+};
+
+struct platform_device gta02_led_dev = {
+ .name = "gta02-led",
+ .num_resources = ARRAY_SIZE(gta02_led_resources),
+ .resource = gta02_led_resources,
+};
+
+static struct resource gta02_button_resources[] = {
+ [0] = {
+ .start = GTA02_GPIO_AUX_KEY,
+ .end = GTA02_GPIO_AUX_KEY,
+ },
+ [1] = {
+ .start = GTA02_GPIO_HOLD_KEY,
+ .end = GTA02_GPIO_HOLD_KEY,
+ },
+ [2] = {
+ .start = GTA02_GPIO_JACK_INSERT,
+ .end = GTA02_GPIO_JACK_INSERT,
+ },
+ [3] = {
+ .start = 0,
+ .end = 0,
+ },
+ [4] = {
+ .start = 0,
+ .end = 0,
+ },
+};
+
+static struct platform_device gta02_button_dev = {
+ .name = "neo1973-button",
+ .num_resources = ARRAY_SIZE(gta02_button_resources),
+ .resource = gta02_button_resources,
+};
+
+
+static struct platform_device gta02_pm_usbhost_dev = {
+ .name = "neo1973-pm-host",
+};
+
+
+/* USB */
+static struct s3c2410_hcd_info gta02_usb_info = {
+ .port[0] = {
+ .flags = S3C_HCDFLG_USED,
+ },
+ .port[1] = {
+ .flags = 0,
+ },
+};
+
+static int glamo_irq_is_wired(void)
+{
+ int rc;
+ int count = 0;
+
+ /*
+ * GTA02 S-Media IRQs prior to A5 are broken due to a lack of
+ * a pullup on the INT# line. Check for the bad behaviour.
+ */
+ s3c2410_gpio_setpin(S3C2410_GPG4, 0);
+ s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_OUTP);
+ s3c2410_gpio_cfgpin(S3C2410_GPG4, S3C2410_GPG4_INP);
+ /*
+ * we force it low ourselves for a moment and resume being input.
+ * If there is a pullup, it won't stay low for long. But if the
+ * level converter is there as on < A5 revision, the weak keeper
+ * on the input of the LC will hold the line low indefinitiely
+ */
+ do
+ rc = s3c2410_gpio_getpin(S3C2410_GPG4);
+ while ((!rc) && ((count++) < 10));
+ if (rc) { /* it got pulled back up, it's good */
+ printk(KERN_INFO "Detected S-Media IRQ# pullup, "
+ "enabling interrupt\n");
+ return 0;
+ } else /* Gah we can't work with this level converter */
+ printk(KERN_WARNING "** Detected bad IRQ# circuit found"
+ " on pre-A5 GTA02: S-Media interrupt disabled **\n");
+ return -ENODEV;
+}
+
+static int gta02_glamo_can_set_mmc_power(void)
+{
+ switch (system_rev) {
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Smedia Glamo 3362 */
+
+/*
+ * we crank down SD Card clock dynamically when GPS is powered
+ */
+
+static int gta02_glamo_mci_use_slow(void)
+{
+ return neo1973_pm_gps_is_on();
+}
+
+static void gta02_glamo_external_reset(int level)
+{
+ s3c2410_gpio_setpin(GTA02_GPIO_3D_RESET, level);
+ s3c2410_gpio_cfgpin(GTA02_GPIO_3D_RESET, S3C2410_GPIO_OUTPUT);
+}
+
+static struct glamofb_platform_data gta02_glamo_pdata = {
+ .width = 43,
+ .height = 58,
+ /* 24.5MHz --> 40.816ns */
+ .pixclock = 40816,
+ .left_margin = 8,
+ .right_margin = 16,
+ .upper_margin = 2,
+ .lower_margin = 16,
+ .hsync_len = 8,
+ .vsync_len = 2,
+ .fb_mem_size = 0x400000, /* glamo has 8 megs of SRAM. we use 4 */
+ .xres = {
+ .min = 240,
+ .max = 640,
+ .defval = 480,
+ },
+ .yres = {
+ .min = 320,
+ .max = 640,
+ .defval = 640,
+ },
+ .bpp = {
+ .min = 16,
+ .max = 16,
+ .defval = 16,
+ },
+ //.spi_info = &glamo_spi_cfg,
+ .spigpio_info = &glamo_spigpio_cfg,
+
+ /* glamo MMC function platform data */
+ .mmc_dev = &gta02_mmc_dev,
+ .glamo_can_set_mci_power = gta02_glamo_can_set_mmc_power,
+ .glamo_mci_use_slow = gta02_glamo_mci_use_slow,
+ .glamo_irq_is_wired = glamo_irq_is_wired,
+ .glamo_external_reset = gta02_glamo_external_reset
+};
+
+static struct resource gta02_glamo_resources[] = {
+ [0] = {
+ .start = S3C2410_CS1,
+ .end = S3C2410_CS1 + 0x1000000 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = GTA02_IRQ_3D,
+ .end = GTA02_IRQ_3D,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = GTA02v1_GPIO_3D_RESET,
+ .end = GTA02v1_GPIO_3D_RESET,
+ },
+};
+
+static struct platform_device gta02_glamo_dev = {
+ .name = "glamo3362",
+ .num_resources = ARRAY_SIZE(gta02_glamo_resources),
+ .resource = gta02_glamo_resources,
+ .dev = {
+ .platform_data = &gta02_glamo_pdata,
+ },
+};
+
+static void mangle_glamo_res_by_system_rev(void)
+{
+ switch (system_rev) {
+ case GTA02v1_SYSTEM_REV:
+ break;
+ default:
+ gta02_glamo_resources[2].start = GTA02_GPIO_3D_RESET;
+ gta02_glamo_resources[2].end = GTA02_GPIO_3D_RESET;
+ break;
+ }
+
+ switch (system_rev) {
+ case GTA02v1_SYSTEM_REV:
+ case GTA02v2_SYSTEM_REV:
+ case GTA02v3_SYSTEM_REV:
+ /* case GTA02v4_SYSTEM_REV: - FIXME: handle this later */
+ /* The hardware is missing a pull-up resistor and thus can't
+ * support the Smedia Glamo IRQ */
+ gta02_glamo_resources[1].start = 0;
+ gta02_glamo_resources[1].end = 0;
+ break;
+ }
+}
+
+static void __init gta02_map_io(void)
+{
+ s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
+ s3c24xx_init_clocks(12000000);
+ s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+}
+
+static irqreturn_t gta02_modem_irq(int irq, void *param)
+{
+ printk(KERN_DEBUG "modem wakeup interrupt\n");
+ gta_gsm_interrupts++;
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t ar6000_wow_irq(int irq, void *param)
+{
+ printk(KERN_DEBUG "ar6000_wow interrupt\n");
+ return IRQ_HANDLED;
+}
+
+/*
+ * hardware_ecc=1|0
+ */
+static char hardware_ecc_str[4] __initdata = "";
+
+static int __init hardware_ecc_setup(char *str)
+{
+ if (str)
+ strlcpy(hardware_ecc_str, str, sizeof(hardware_ecc_str));
+ return 1;
+}
+
+__setup("hardware_ecc=", hardware_ecc_setup);
+
+/* these are the guys that don't need to be children of PMU */
+
+static struct platform_device *gta02_devices[] __initdata = {
+ &gta02_version_device,
+ &s3c_device_usb,
+ &s3c_device_wdt,
+ &gta02_memconfig_device,
+ &s3c_device_sdi,
+ &s3c_device_usbgadget,
+ &s3c_device_nand,
+ &gta02_nor_flash,
+
+ &sc32440_fiq_device,
+ &s3c24xx_pwm_device,
+ &gta02_led_dev,
+ &gta02_pm_wlan_dev, /* not dependent on PMU */
+
+ &s3c_device_iis,
+ &s3c_device_i2c0,
+};
+
+/* these guys DO need to be children of PMU */
+
+static struct platform_device *gta02_devices_pmu_children[] = {
+ &s3c_device_ts, /* input 1 */
+ &gta02_pm_gsm_dev,
+ &gta02_pm_usbhost_dev,
+ &s3c_device_spi_acc1, /* input 2 */
+ &s3c_device_spi_acc2, /* input 3 */
+ &gta02_button_dev, /* input 4 */
+ &gta02_resume_reason_device,
+};
+
+static void gta02_pmu_regulator_registered(struct pcf50633 *pcf, int id)
+{
+ struct platform_device *regulator, *pdev;
+
+ regulator = pcf->pmic.pdev[id];
+
+ switch(id) {
+ case PCF50633_REGULATOR_LDO4:
+ pdev = &gta01_pm_bt_dev;
+ break;
+ case PCF50633_REGULATOR_LDO5:
+ pdev = &gta01_pm_gps_dev;
+ break;
+ case PCF50633_REGULATOR_HCLDO:
+ pdev = &gta02_glamo_dev;
+ break;
+ default:
+ return;
+ }
+
+ pdev->dev.parent = &regulator->dev;
+ platform_device_register(pdev);
+}
+
+/* this is called when pc50633 is probed, unfortunately quite late in the
+ * day since it is an I2C bus device. Here we can belatedly define some
+ * platform devices with the advantage that we can mark the pcf50633 as the
+ * parent. This makes them get suspended and resumed with their parent
+ * the pcf50633 still around.
+ */
+
+static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)
+{
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)
+ gta02_devices_pmu_children[n]->dev.parent = pcf->dev;
+
+ mangle_glamo_res_by_system_rev();
+ platform_add_devices(gta02_devices_pmu_children,
+ ARRAY_SIZE(gta02_devices_pmu_children));
+}
+
+
+static void __init gta02_machine_init(void)
+{
+ int rc;
+
+ /* set the panic callback to make AUX blink fast */
+ panic_blink = gta02_panic_blink;
+
+ switch (system_rev) {
+ case GTA02v6_SYSTEM_REV:
+ /* we need push-pull interrupt from motion sensors */
+ lis302_pdata_top.open_drain = 0;
+ lis302_pdata_bottom.open_drain = 0;
+ break;
+ default:
+ break;
+ }
+
+ spin_lock_init(&motion_irq_lock);
+ INIT_DELAYED_WORK(&gta02_charger_work, gta02_charger_worker);
+
+ /* Glamo chip select optimization */
+/* *((u32 *)(S3C2410_MEMREG(((1 + 1) << 2)))) = 0x1280; */
+
+ /* do not force soft ecc if we are asked to use hardware_ecc */
+ if (hardware_ecc_str[0] == '1')
+ gta02_nand_info.software_ecc = 0;
+
+ s3c_device_usb.dev.platform_data = &gta02_usb_info;
+ s3c_device_nand.dev.platform_data = &gta02_nand_info;
+ s3c_device_sdi.dev.platform_data = &gta02_s3c_mmc_cfg;
+
+ /* acc sensor chip selects */
+ s3c2410_gpio_setpin(S3C2410_GPD12, 1);
+ s3c2410_gpio_cfgpin(S3C2410_GPD12, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_setpin(S3C2410_GPD13, 1);
+ s3c2410_gpio_cfgpin(S3C2410_GPD13, S3C2410_GPIO_OUTPUT);
+
+ s3c24xx_udc_set_platdata(&gta02_udc_cfg);
+ s3c_i2c0_set_platdata(NULL);
+ set_s3c2410ts_info(&gta02_ts_cfg);
+
+ mangle_glamo_res_by_system_rev();
+
+ i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
+
+ mangle_pmu_pdata_by_system_rev();
+
+ platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
+
+ s3c_pm_init();
+
+ /* Make sure the modem can wake us up */
+ set_irq_type(GTA02_IRQ_MODEM, IRQ_TYPE_EDGE_RISING);
+ rc = request_irq(GTA02_IRQ_MODEM, gta02_modem_irq, IRQF_DISABLED,
+ "modem", NULL);
+ if (rc < 0)
+ printk(KERN_ERR "GTA02: can't request GSM modem wakeup IRQ\n");
+ enable_irq_wake(GTA02_IRQ_MODEM);
+
+ /* Make sure the wifi module can wake us up*/
+ set_irq_type(GTA02_IRQ_WLAN_GPIO1, IRQ_TYPE_EDGE_RISING);
+ rc = request_irq(GTA02_IRQ_WLAN_GPIO1, ar6000_wow_irq, IRQF_DISABLED,
+ "ar6000", NULL);
+
+ if (rc < 0)
+ printk(KERN_ERR "GTA02: can't request ar6k wakeup IRQ\n");
+ enable_irq_wake(GTA02_IRQ_WLAN_GPIO1);
+}
+
+void DEBUG_LED(int n)
+{
+// int *p = NULL;
+ switch (n) {
+ case 0:
+ neo1973_gpb_setpin(GTA02_GPIO_PWR_LED1, 1);
+ break;
+ case 1:
+ neo1973_gpb_setpin(GTA02_GPIO_PWR_LED2, 1);
+ break;
+ default:
+ neo1973_gpb_setpin(GTA02_GPIO_AUX_LED, 1);
+ break;
+ }
+// printk(KERN_ERR"die %d\n", *p);
+}
+EXPORT_SYMBOL_GPL(DEBUG_LED);
+
+MACHINE_START(NEO1973_GTA02, "GTA02")
+ .phys_io = S3C2410_PA_UART,
+ .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
+ .boot_params = S3C2410_SDRAM_PA + 0x100,
+ .map_io = gta02_map_io,
+ .init_irq = s3c24xx_init_irq,
+ .init_machine = gta02_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -37,6 +37,7 @@
//#include <asm/debug-ll.h>
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
+#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@@ -107,7 +108,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_camif,
@@ -142,6 +143,7 @@
static void __init nexcoder_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
};
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -37,7 +37,8 @@
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
+#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@@ -335,7 +336,7 @@
/* Standard Osiris devices */
static struct platform_device *osiris_devices[] __initdata = {
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_wdt,
&s3c_device_nand,
&osiris_pcmcia,
@@ -398,6 +399,8 @@
sysdev_class_register(&osiris_pm_sysclass);
sysdev_register(&osiris_pm_sysdev);
+ s3c_i2c0_set_platdata(NULL);
+
i2c_register_board_info(0, osiris_i2c_devs,
ARRAY_SIZE(osiris_i2c_devs));
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -42,7 +42,7 @@
#include <mach/regs-lcd.h>
#include <mach/h1940.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
#include <mach/fb.h>
#include <plat/clock.h>
@@ -179,7 +179,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_nand,
};
@@ -203,7 +203,7 @@
#ifdef CONFIG_PM_H1940
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
#endif
- s3c2410_pm_init();
+ s3c_pm_init();
s3c24xx_fb_set_platdata(&rx3715_fb_info);
platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
+#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@@ -152,7 +153,7 @@
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
- &s3c_device_i2c,
+ &s3c_device_i2c0,
&s3c_device_iis,
};
@@ -166,6 +167,7 @@
static void __init smdk2440_machine_init(void)
{
s3c24xx_fb_set_platdata(&smdk2440_fb_info);
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
smdk_machine_init();
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -13,6 +13,7 @@
obj-$(CONFIG_CPU_S3C2440) += irq.o
obj-$(CONFIG_CPU_S3C2440) += clock.o
obj-$(CONFIG_S3C2440_DMA) += dma.o
+obj-$(CONFIG_S3C2440_C_FIQ) += fiq_c_isr.o
# Machine support
@@ -22,3 +23,6 @@
obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
+obj-$(CONFIG_MACH_HXD8) += mach-hxd8.o
+obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
+
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -46,6 +46,9 @@
s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT;
+ /* make sure SD/MMC driver can distinguish 2440 from 2410 */
+ s3c_device_sdi.name = "s3c2440-sdi";
+
/* register our system device for everything else */
return sysdev_register(&s3c2440_sysdev);
--- a/arch/arm/mach-s3c2442/Kconfig
+++ b/arch/arm/mach-s3c2442/Kconfig
@@ -6,10 +6,11 @@
config CPU_S3C2442
bool
- depends on ARCH_S3C2410
+ depends on CPU_S3C2440
select S3C2410_CLOCK
select S3C2410_GPIO
select S3C2410_PM if PM
+ select S3C2440_DMA if S3C2410_DMA
select CPU_S3C244X
select CPU_LLSERIAL_S3C2440
help
--- a/arch/arm/mach-s3c2442/s3c2442.c
+++ b/arch/arm/mach-s3c2442/s3c2442.c
@@ -21,6 +21,7 @@
#include <plat/s3c2442.h>
#include <plat/cpu.h>
+#include <plat/devs.h>
static struct sys_device s3c2442_sysdev = {
.cls = &s3c2442_sysclass,
@@ -30,5 +31,8 @@
{
printk("S3C2442: Initialising architecture\n");
+ /* make sure SD/MMC driver can distinguish 2440 from 2410 */
+ s3c_device_sdi.name = "s3c2440-sdi";
+
return sysdev_register(&s3c2442_sysdev);
}
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -39,6 +39,8 @@
#include <mach/regs-s3c2443-clock.h>
+#include <plat/cpu-freq.h>
+
#include <plat/s3c2443.h>
#include <plat/clock.h>
#include <plat/cpu.h>
@@ -145,12 +147,6 @@
/* clock selections */
-/* CPU EXTCLK input */
-static struct clk clk_ext = {
- .name = "ext",
- .id = -1,
-};
-
static struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
@@ -165,14 +161,6 @@
};
#endif
-static struct clk clk_epllref;
-
-static struct clk clk_epll = {
- .name = "epll",
- .parent = &clk_epllref,
- .id = -1,
-};
-
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
.id = -1,
@@ -1011,22 +999,20 @@
&clk_prediv,
};
-void __init s3c2443_init_clocks(int xtal)
+void __init_or_cpufreq s3c2443_setup_clocks(void)
{
- unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+ struct clk *xtal_clk;
+ unsigned long xtal;
unsigned long pll;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
- struct clk *clkp;
- int ret;
- int ptr;
- /* s3c2443 parents h and p clocks from prediv */
- clk_h.parent = &clk_prediv;
- clk_p.parent = &clk_prediv;
+ xtal_clk = clk_get(NULL, "xtal");
+ xtal = clk_get_rate(xtal_clk);
+ clk_put(xtal_clk);
pll = s3c2443_get_mpll(mpllcon, xtal);
clk_msysclk.rate = pll;
@@ -1036,13 +1022,29 @@
hclk /= s3c2443_get_hdiv(clkdiv0);
pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
+ s3c24xx_setup_clocks(fclk, hclk, pclk);
printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
(mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
print_mhz(pll), print_mhz(fclk),
print_mhz(hclk), print_mhz(pclk));
+ s3c24xx_setup_clocks(fclk, hclk, pclk);
+}
+
+void __init s3c2443_init_clocks(int xtal)
+{
+ struct clk *clkp;
+ unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
+ int ret;
+ int ptr;
+
+ /* s3c2443 parents h and p clocks from prediv */
+ clk_h.parent = &clk_prediv;
+ clk_p.parent = &clk_prediv;
+
+ s3c24xx_register_baseclocks(xtal);
+ s3c2443_setup_clocks();
s3c2443_clk_initparents();
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
@@ -1056,7 +1058,7 @@
}
clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
-
+ clk_epll.parent = &clk_epllref;
clk_usb_bus.parent = &clk_usb_bus_host;
/* ensure usb bus clock is within correct rate of 48MHz */
@@ -1105,4 +1107,6 @@
(clkp->enable)(clkp, 0);
}
+
+ s3c_pwmclk_init();
}
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -26,12 +26,12 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <asm/plat-s3c24xx/regs-iis.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
#define MAP(x) { \
[0] = (x) | DMA_CH_VALID, \
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -24,6 +24,7 @@
bool "SMDK2443"
select CPU_S3C2443
select MACH_SMDK
+ select S3C_DEV_HSMMC
help
Say Y here if you are using an SMDK2443
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
+#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@@ -103,8 +104,8 @@
static struct platform_device *smdk2443_devices[] __initdata = {
&s3c_device_wdt,
- &s3c_device_i2c,
- &s3c_device_hsmmc,
+ &s3c_device_i2c0,
+ &s3c_device_hsmmc0,
};
static void __init smdk2443_map_io(void)
@@ -116,6 +117,7 @@
static void __init smdk2443_machine_init(void)
{
+ s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
smdk_machine_init();
}
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -81,10 +81,9 @@
* machine specific initialisation.
*/
-void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size)
+void __init s3c2443_map_io(void)
{
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
- iotable_init(mach_desc, mach_size);
}
/* need to register class before we actually register the device, and
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
@@ -0,0 +1,28 @@
+/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+
+ .macro addruart, rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1
+ ldreq \rx, = S3C24XX_PA_UART
+ ldrne \rx, = S3C24XX_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+ add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
+#endif
+ .endm
+
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+
+#include <plat/debug-macro.S>
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/io.h
@@ -0,0 +1,16 @@
+/* arch/arm/mach-s3c24a0/include/mach/io.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben-linux@fluff.org>
+ *
+ * IO access and mapping routines for the S3C24A0
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No current ISA/PCI bus support. */
+#define __io(a) ((void __iomem *)(a))
+#define __mem_pci(a) (a)
+
+#endif
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef __ASM_ARCH_24A0_IRQS_H
+#define __ASM_ARCH_24A0_IRQS_H __FILE__
+
+#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
+/* for generic entry-macro.S */
+#define IRQ_EINT0 IRQ_EINT0t2
+
+#define IRQ_EINT3t6 S3C2410_IRQ(1)
+#define IRQ_EINT7t10 S3C2410_IRQ(2)
+#define IRQ_EINT11t14 S3C2410_IRQ(3)
+#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
+#define IRQ_TICK S3C2410_IRQ(5)
+#define IRQ_DCTQ S3C2410_IRQ(6)
+#define IRQ_MC S3C2410_IRQ(7)
+#define IRQ_ME S3C2410_IRQ(8) /* 24 */
+#define IRQ_KEYPAD S3C2410_IRQ(9)
+#define IRQ_TIMER0 S3C2410_IRQ(10)
+#define IRQ_TIMER1 S3C2410_IRQ(11)
+#define IRQ_TIMER2 S3C2410_IRQ(12)
+#define IRQ_TIMER3_4 S3C2410_IRQ(13)
+#define IRQ_OS_TIMER IRQ_TIMER3_4
+#define IRQ_LCD S3C2410_IRQ(14)
+#define IRQ_CAM_C S3C2410_IRQ(15)
+#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
+#define IRQ_UART0 S3C2410_IRQ(17)
+#define IRQ_CAM_P S3C2410_IRQ(18)
+#define IRQ_MODEM S3C2410_IRQ(19)
+#define IRQ_DMA S3C2410_IRQ(20)
+#define IRQ_SDI S3C2410_IRQ(21)
+#define IRQ_SPI0 S3C2410_IRQ(22)
+#define IRQ_UART1 S3C2410_IRQ(23)
+#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
+#define IRQ_USBD S3C2410_IRQ(25)
+#define IRQ_USBH S3C2410_IRQ(26)
+#define IRQ_IIC S3C2410_IRQ(27)
+#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
+#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
+#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
+#define IRQ_ADC_PEN S3C2410_IRQ(31)
+
+/* interrupts generated from the external interrupts sources */
+#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
+#define IRQ_EINT1 S3C2410_IRQ(33)
+#define IRQ_EINT2 S3C2410_IRQ(34)
+#define IRQ_EINT3 S3C2410_IRQ(35)
+#define IRQ_EINT4 S3C2410_IRQ(36)
+#define IRQ_EINT5 S3C2410_IRQ(37)
+#define IRQ_EINT6 S3C2410_IRQ(38)
+#define IRQ_EINT7 S3C2410_IRQ(39)
+#define IRQ_EINT8 S3C2410_IRQ(40)
+#define IRQ_EINT9 S3C2410_IRQ(41)
+#define IRQ_EINT10 S3C2410_IRQ(42)
+#define IRQ_EINT11 S3C2410_IRQ(43)
+#define IRQ_EINT12 S3C2410_IRQ(44)
+#define IRQ_EINT13 S3C2410_IRQ(45)
+#define IRQ_EINT14 S3C2410_IRQ(46)
+#define IRQ_EINT15 S3C2410_IRQ(47)
+#define IRQ_EINT16 S3C2410_IRQ(48)
+#define IRQ_EINT17 S3C2410_IRQ(49)
+#define IRQ_EINT18 S3C2410_IRQ(50)
+
+#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
+
+/* SUB IRQS */
+#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
+#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
+#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
+
+#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
+#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
+#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
+
+#define IRQ_S3CUART_RX2 (0x0)
+#define IRQ_S3CUART_TX2 (0x0)
+#define IRQ_S3CUART_ERR2 (0x0)
+
+
+#define IRQ_IRDA S3C2410_IRQ(57)
+#define IRQ_MSTICK S3C2410_IRQ(58)
+#define IRQ_RESERVED0 S3C2410_IRQ(59)
+#define IRQ_RESERVED1 S3C2410_IRQ(60)
+#define IRQ_RESERVED2 S3C2410_IRQ(61)
+#define IRQ_TIMER3 S3C2410_IRQ(62)
+#define IRQ_TIMER4 S3C2410_IRQ(63)
+#define IRQ_WDT S3C2410_IRQ(64)
+#define IRQ_BATFLT S3C2410_IRQ(65)
+#define IRQ_POST S3C2410_IRQ(66)
+#define IRQ_DISP_FIFO S3C2410_IRQ(67)
+#define IRQ_PENUP S3C2410_IRQ(68)
+#define IRQ_PENDN S3C2410_IRQ(69)
+#define IRQ_ADC S3C2410_IRQ(70)
+#define IRQ_DISP_FRAME S3C2410_IRQ(71)
+#define IRQ_NFLASH S3C2410_IRQ(72)
+#define IRQ_AC97 S3C2410_IRQ(73)
+#define IRQ_SPI1 S3C2410_IRQ(74)
+#define IRQ_VLX S3C2410_IRQ(75)
+#define IRQ_DMA0 S3C2410_IRQ(76)
+#define IRQ_DMA1 S3C2410_IRQ(77)
+#define IRQ_DMA2 S3C2410_IRQ(78)
+#define IRQ_DMA3 S3C2410_IRQ(79)
+
+#define IRQ_TC (0x0)
+
+#define NR_IRQS (IRQ_DMA3+1)
+
+#endif /* __ASM_ARCH_24A0_IRQS_H */
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -0,0 +1,85 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
+ *
+ * Copyright 2003,2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24A0 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_24A0_MAP_H
+#define __ASM_ARCH_24A0_MAP_H __FILE__
+
+#include <plat/map-base.h>
+#include <plat/map.h>
+
+#define S3C24A0_PA_IO_BASE (0x40000000)
+#define S3C24A0_PA_CLKPWR (0x40000000)
+#define S3C24A0_PA_IRQ (0x40200000)
+#define S3C24A0_PA_DMA (0x40400000)
+#define S3C24A0_PA_MEMCTRL (0x40C00000)
+#define S3C24A0_PA_NAND (0x40C00000)
+#define S3C24A0_PA_SROM (0x40C20000)
+#define S3C24A0_PA_SDRAM (0x40C40000)
+#define S3C24A0_PA_BUSM (0x40CE0000)
+#define S3C24A0_PA_USBHOST (0x41000000)
+#define S3C24A0_PA_MODEMIF (0x41180000)
+#define S3C24A0_PA_IRDA (0x41800000)
+#define S3C24A0_PA_TIMER (0x44000000)
+#define S3C24A0_PA_WATCHDOG (0x44100000)
+#define S3C24A0_PA_RTC (0x44200000)
+#define S3C24A0_PA_UART (0x44400000)
+#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
+#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
+#define S3C24A0_PA_SPI (0x44500000)
+#define S3C24A0_PA_IIC (0x44600000)
+#define S3C24A0_PA_IIS (0x44700000)
+#define S3C24A0_PA_GPIO (0x44800000)
+#define S3C24A0_PA_KEYIF (0x44900000)
+#define S3C24A0_PA_USBDEV (0x44A00000)
+#define S3C24A0_PA_AC97 (0x45000000)
+#define S3C24A0_PA_ADC (0x45800000)
+#define S3C24A0_PA_SDI (0x46000000)
+#define S3C24A0_PA_MS (0x46100000)
+#define S3C24A0_PA_LCD (0x4A000000)
+#define S3C24A0_PA_VPOST (0x4A100000)
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C24A0_CS0 (0x00000000)
+#define S3C24A0_CS1 (0x04000000)
+#define S3C24A0_CS2 (0x08000000)
+#define S3C24A0_CS3 (0x0C000000)
+#define S3C24A0_CS4 (0x10000000)
+#define S3C24A0_CS5 (0x40000000)
+
+#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
+
+/* Use a single interface for common resources between S3C24XX cpus */
+
+#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
+#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
+#define S3C24XX_PA_DMA S3C24A0_PA_DMA
+#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
+#define S3C24XX_PA_LCD S3C24A0_PA_LCD
+#define S3C24XX_PA_UART S3C24A0_PA_UART
+#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
+#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
+#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
+#define S3C24XX_PA_IIS S3C24A0_PA_IIS
+#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
+#define S3C24XX_PA_RTC S3C24A0_PA_RTC
+#define S3C24XX_PA_ADC S3C24A0_PA_ADC
+#define S3C24XX_PA_SPI S3C24A0_PA_SPI
+#define S3C24XX_PA_SDI S3C24A0_PA_SDI
+#define S3C24XX_PA_NAND S3C24A0_PA_NAND
+
+#define S3C_PA_UART S3C24A0_PA_UART
+#define S3C_PA_IIC S3C24A0_PA_IIC
+
+#endif /* __ASM_ARCH_24A0_MAP_H */
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/memory.h
@@ -0,0 +1,19 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
+ * from linux/include/asm-arm/arch-rpc/memory.h
+ *
+ * Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_24A0_MEMORY_H
+#define __ASM_ARCH_24A0_MEMORY_H __FILE__
+
+#define PHYS_OFFSET UL(0x10000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
@@ -0,0 +1,88 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C24A0 clock register definitions
+*/
+
+#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
+#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
+
+#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
+#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
+#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
+#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
+#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
+
+/* CLKCON register bits */
+
+#define S3C24A0_CLKCON_VLX (1<<29)
+#define S3C24A0_CLKCON_VPOST (1<<28)
+#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
+#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
+#define S3C24A0_CLKCON_VPOSTIF (1<<25)
+#define S3C24A0_CLKCON_MPEG4IF (1<<24)
+#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
+#define S3C24A0_CLKCON_LCDC (1<<22)
+#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
+#define S3C24A0_CLKCON_MPEG4 (1<<20)
+#define S3C24A0_CLKCON_KEYPAD (1<<19)
+#define S3C24A0_CLKCON_ADC (1<<18)
+#define S3C24A0_CLKCON_SDI (1<<17)
+#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
+#define S3C24A0_CLKCON_USBD (1<<15)
+#define S3C24A0_CLKCON_GPIO (1<<14)
+#define S3C24A0_CLKCON_IIS (1<<13)
+#define S3C24A0_CLKCON_IIC (1<<12)
+#define S3C24A0_CLKCON_SPI (1<<11)
+#define S3C24A0_CLKCON_UART1 (1<<10)
+#define S3C24A0_CLKCON_UART0 (1<<9)
+#define S3C24A0_CLKCON_PWMT (1<<8)
+#define S3C24A0_CLKCON_USBH (1<<7)
+#define S3C24A0_CLKCON_AC97 (1<<6)
+#define S3C24A0_CLKCON_IrDA (1<<4)
+#define S3C24A0_CLKCON_IDLE (1<<2)
+#define S3C24A0_CLKCON_MON (1<<1)
+#define S3C24A0_CLKCON_STOP (1<<0)
+
+/* CLKSRC register bits */
+
+#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
+#define S3C24A0_CLKSRC_UPLL (1<<7)
+#define S3C24A0_CLKSRC_MPLL (1<<5)
+#define S3C24A0_CLKSRC_EXT (1<<4)
+
+/* Use a single interface with the common code, for s3c24xx */
+
+#define S3C2410_MPLLCON S3C24A0_MPLLCON
+#define S3C2410_UPLLCON S3C24A0_UPLLCON
+#define S3C2410_CLKCON S3C24A0_CLKCON
+#define S3C2410_CLKSLOW S3C24A0_CLKSRC
+#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
+
+#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
+#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
+#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
+#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
+#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
+#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
+#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
+#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
+#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
+#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
+#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
+#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
+#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
+#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
+
+#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
+#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
+#define S3C2410_CLKSLOW_SLOW (0xFF)
+#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
+
+#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+
+#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
+#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
+
+
+#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
+#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
+
+#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
+#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
+
+#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
+
+
+
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/system.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24A0 - System function defines and includes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+
+#include <mach/map.h>
+
+static void arch_idle(void)
+{
+ /* currently no specific idle support. */
+}
+
+void (*s3c24xx_reset_hook)(void);
+
+#include <asm/plat-s3c24xx/system-reset.h>
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/tick.h
@@ -0,0 +1,15 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C24A0 - timer tick support
+ */
+
+#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
+
+static inline int s3c24xx_ostimer_pending(void)
+{
+ return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
+}
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/timex.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
--- /dev/null
+++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
@@ -0,0 +1,17 @@
+/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
+ *
+ * Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
+
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C24A0 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S
@@ -0,0 +1,39 @@
+/* arch/arm/mach-s3c6400/include/mach/debug-macro.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+
+ /* note, for the boot process to work we have to keep the UART
+ * virtual address aligned to an 1MiB boundary for the L1
+ * mapping the head code makes. We keep the UART virtual address
+ * aligned and add in the offset when we load the value here.
+ */
+
+ .macro addruart, rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1
+ ldreq \rx, = S3C_PA_UART
+ ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+#if CONFIG_DEBUG_S3C_UART != 0
+ add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+#endif
+ .endm
+
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+
+#include <plat/debug-macro.S>
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - DMA support
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_IRQ_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S
@@ -0,0 +1,44 @@
+/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Low-level IRQ helper macros for the Samsung S3C64XX series
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/irqs.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =S3C_VA_VIC0
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+ @ check the vic0
+ mov \irqnr, # S3C_IRQ_OFFSET + 31
+ ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
+ teq \irqstat, #0
+
+ @ otherwise try vic1
+ addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+ addeq \irqnr, \irqnr, #32
+ ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+ teqeq \irqstat, #0
+
+ clzne \irqstat, \irqstat
+ subne \irqnr, \irqnr, \irqstat
+ .endm
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/gpio-core.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_CORE_H
+#define __ASM_ARCH_GPIO_CORE_H __FILE__
+
+/* currently we just include the platform support */
+#include <plat/gpio-core.h>
+
+#endif /* __ASM_ARCH_GPIO_CORE_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/gpio.h
@@ -0,0 +1,96 @@
+/* arch/arm/mach-s3c6400/include/mach/gpio.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C6400 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
+#define gpio_to_irq __gpio_to_irq
+
+/* GPIO bank sizes */
+#define S3C64XX_GPIO_A_NR (8)
+#define S3C64XX_GPIO_B_NR (7)
+#define S3C64XX_GPIO_C_NR (8)
+#define S3C64XX_GPIO_D_NR (5)
+#define S3C64XX_GPIO_E_NR (5)
+#define S3C64XX_GPIO_F_NR (16)
+#define S3C64XX_GPIO_G_NR (7)
+#define S3C64XX_GPIO_H_NR (10)
+#define S3C64XX_GPIO_I_NR (16)
+#define S3C64XX_GPIO_J_NR (12)
+#define S3C64XX_GPIO_K_NR (16)
+#define S3C64XX_GPIO_L_NR (15)
+#define S3C64XX_GPIO_M_NR (6)
+#define S3C64XX_GPIO_N_NR (16)
+#define S3C64XX_GPIO_O_NR (16)
+#define S3C64XX_GPIO_P_NR (15)
+#define S3C64XX_GPIO_Q_NR (9)
+
+/* GPIO bank numbes */
+
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+
+#define S3C64XX_GPIO_NEXT(__gpio) \
+ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s3c_gpio_number {
+ S3C64XX_GPIO_A_START = 0,
+ S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
+ S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
+ S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
+ S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
+ S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
+ S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
+ S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
+ S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
+ S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
+ S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
+ S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
+ S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
+ S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
+ S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
+ S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
+ S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
+};
+
+/* S3C64XX GPIO number definitions. */
+
+#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
+#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
+#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
+#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
+#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
+#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
+#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
+#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
+#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
+#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
+#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
+#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
+#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
+#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
+#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
+#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
+#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
+
+/* the end of the S3C64XX specific gpios */
+#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
+#define S3C_GPIO_END S3C64XX_GPIO_END
+
+/* define the number of gpios we need to the one after the GPQ() range */
+#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
+
+#include <asm-generic/gpio.h>
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/hardware.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - Hardware support
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_IRQ_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/irqs.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/irqs.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - IRQ definitions
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#ifndef __ASM_ARM_IRQ_H
+#error "Do not include this directly, instead #include <asm/irq.h>"
+#endif
+
+#include <plat/irqs.h>
+
+#endif /* __ASM_ARCH_IRQ_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -0,0 +1,71 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/map.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/* HSMMC units */
+#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
+#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
+#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
+#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
+
+#define S3C_PA_UART (0x7F005000)
+#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
+#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
+#define S3C_PA_UART2 (S3C_PA_UART + 0x800)
+#define S3C_PA_UART3 (S3C_PA_UART + 0xC00)
+#define S3C_UART_OFFSET (0x400)
+
+/* See notes on UART VA mapping in debug-macro.S */
+#define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
+
+#define S3C_VA_UART0 S3C_VA_UARTx(0)
+#define S3C_VA_UART1 S3C_VA_UARTx(1)
+#define S3C_VA_UART2 S3C_VA_UARTx(2)
+#define S3C_VA_UART3 S3C_VA_UARTx(3)
+
+#define S3C64XX_PA_FB (0x77100000)
+#define S3C64XX_PA_SYSCON (0x7E00F000)
+#define S3C64XX_PA_TIMER (0x7F006000)
+#define S3C64XX_PA_IIC0 (0x7F004000)
+#define S3C64XX_PA_IIC1 (0x7F00F000)
+
+#define S3C64XX_PA_GPIO (0x7F008000)
+#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000)
+#define S3C64XX_SZ_GPIO SZ_4K
+
+#define S3C64XX_PA_SDRAM (0x50000000)
+#define S3C64XX_PA_VIC0 (0x71200000)
+#define S3C64XX_PA_VIC1 (0x71300000)
+
+#define S3C64XX_PA_MODEM (0x74108000)
+#define S3C64XX_VA_MODEM S3C_ADDR(0x00600000)
+
+/* place VICs close together */
+#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00)
+#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
+
+/* compatibiltiy defines. */
+#define S3C_PA_TIMER S3C64XX_PA_TIMER
+#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
+#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
+#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
+#define S3C_PA_IIC S3C64XX_PA_IIC0
+#define S3C_PA_IIC1 S3C64XX_PA_IIC1
+#define S3C_PA_FB S3C64XX_PA_FB
+
+#endif /* __ASM_ARCH_6400_MAP_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/memory.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s3c6400/include/mach/memory.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET UL(0x50000000)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64xx - pwm clock and timer support
+ */
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+ return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+ return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+ return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+ return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - clock register compatibility with s3c24xx
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/regs-clock.h>
+
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
@@ -0,0 +1,259 @@
+/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - new-style framebuffer register definitions
+ *
+ * This is the register set for the new style framebuffer interface
+ * found from the S3C2443 onwards and specifically the S3C64XX series
+ * S3C6400 and S3C6410.
+ *
+ * The file contains the cpu specific items which change between whichever
+ * architecture is selected. See <plat/regs-fb.h> for the core definitions
+ * that are the same.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* include the core definitions here, in case we really do need to
+ * override them at a later date.
+*/
+
+#include <plat/regs-fb.h>
+
+#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN (1 << 15)
+
+/* Video timing controls */
+#define VIDTCON0 (0x10)
+#define VIDTCON1 (0x14)
+#define VIDTCON2 (0x18)
+
+/* Window position controls */
+
+#define WINCON(_win) (0x20 + ((_win) * 4))
+
+/* OSD1 and OSD4 do not have register D */
+
+#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
+#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
+#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
+#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
+
+/* Video buffer addresses */
+
+#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
+#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
+#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
+#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
+#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
+
+#define VIDINTCON0 (0x130)
+
+#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
+
+/* WINCONx */
+
+#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT (26)
+#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
+
+#define WINCONx_ENLOCAL (1 << 22)
+#define WINCONx_BUFSTATUS (1 << 21)
+#define WINCONx_BUFSEL (1 << 20)
+#define WINCONx_BUFAUTOEN (1 << 19)
+#define WINCONx_YCbCr (1 << 13)
+
+#define WINCON1_LOCALSEL_CAMIF (1 << 23)
+
+#define WINCON2_LOCALSEL_CAMIF (1 << 23)
+#define WINCON2_BLD_PIX (1 << 6)
+
+#define WINCON2_ALPHA_SEL (1 << 1)
+#define WINCON2_BPPMODE_MASK (0xf << 2)
+#define WINCON2_BPPMODE_SHIFT (2)
+#define WINCON2_BPPMODE_1BPP (0x0 << 2)
+#define WINCON2_BPPMODE_2BPP (0x1 << 2)
+#define WINCON2_BPPMODE_4BPP (0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
+
+#define WINCON3_BLD_PIX (1 << 6)
+
+#define WINCON3_ALPHA_SEL (1 << 1)
+#define WINCON3_BPPMODE_MASK (0xf << 2)
+#define WINCON3_BPPMODE_SHIFT (2)
+#define WINCON3_BPPMODE_1BPP (0x0 << 2)
+#define WINCON3_BPPMODE_2BPP (0x1 << 2)
+#define WINCON3_BPPMODE_4BPP (0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
+
+#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
+
+#define DITHMODE (0x170)
+#define WINxMAP(_win) (0x180 + ((_win) * 4))
+
+
+#define DITHMODE_R_POS_MASK (0x3 << 5)
+#define DITHMODE_R_POS_SHIFT (5)
+#define DITHMODE_R_POS_8BIT (0x0 << 5)
+#define DITHMODE_R_POS_6BIT (0x1 << 5)
+#define DITHMODE_R_POS_5BIT (0x2 << 5)
+
+#define DITHMODE_G_POS_MASK (0x3 << 3)
+#define DITHMODE_G_POS_SHIFT (3)
+#define DITHMODE_G_POS_8BIT (0x0 << 3)
+#define DITHMODE_G_POS_6BIT (0x1 << 3)
+#define DITHMODE_G_POS_5BIT (0x2 << 3)
+
+#define DITHMODE_B_POS_MASK (0x3 << 1)
+#define DITHMODE_B_POS_SHIFT (1)
+#define DITHMODE_B_POS_8BIT (0x0 << 1)
+#define DITHMODE_B_POS_6BIT (0x1 << 1)
+#define DITHMODE_B_POS_5BIT (0x2 << 1)
+
+#define DITHMODE_DITH_EN (1 << 0)
+
+#define WPALCON (0x1A0)
+
+#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
+#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
+#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
+
+/* Palette registers */
+
+#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
+#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
+#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
+#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
+#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
+
+/* system specific implementation code for palette sizes, and other
+ * information that changes depending on which architecture is being
+ * compiled.
+*/
+
+/* return true if window _win has OSD register D */
+#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
+
+static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
+{
+ if (win < 2)
+ return 256;
+ if (win < 4)
+ return 16;
+ if (win == 4)
+ return 4;
+
+ BUG(); /* shouldn't get here */
+}
+
+static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
+{
+ /* all windows can do 1/2 bpp */
+
+ if ((bpp == 25 || bpp == 19) && win == 0)
+ return 0; /* win 0 does not have 19 or 25bpp modes */
+
+ if (bpp == 4 && win == 4)
+ return 0;
+
+ if (bpp == 8 && (win >= 3))
+ return 0; /* win 3/4 cannot do 8bpp in any mode */
+
+ return 1;
+}
+
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+ switch (window) {
+ case 0: return WIN0_PAL(reg);
+ case 1: return WIN1_PAL(reg);
+ case 2: return WIN2_PAL(reg);
+ case 3: return WIN3_PAL(reg);
+ case 4: return WIN4_PAL(reg);
+ }
+
+ BUG();
+}
+
+static inline int s3c_fb_pal_is16(unsigned int window)
+{
+ return window > 1;
+}
+
+struct s3c_fb_palette {
+ struct fb_bitfield r;
+ struct fb_bitfield g;
+ struct fb_bitfield b;
+ struct fb_bitfield a;
+};
+
+static inline void s3c_fb_init_palette(unsigned int window,
+ struct s3c_fb_palette *palette)
+{
+ if (window < 2) {
+ /* Windows 0/1 are 8/8/8 or A/8/8/8 */
+ palette->r.offset = 16;
+ palette->r.length = 8;
+ palette->g.offset = 8;
+ palette->g.length = 8;
+ palette->b.offset = 0;
+ palette->b.length = 8;
+ } else {
+ /* currently we assume RGB 5/6/5 */
+ palette->r.offset = 11;
+ palette->r.length = 5;
+ palette->g.offset = 5;
+ palette->g.length = 6;
+ palette->b.offset = 0;
+ palette->b.length = 5;
+ }
+}
+
+/* Notes on per-window bpp settings
+ *
+ * Value Win0 Win1 Win2 Win3 Win 4
+ * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
+ * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
+ * 0010 4(P) 4(P) 4(P) 4(P) -none-
+ * 0011 8(P) 8(P) -none- -none- -none-
+ * 0100 -none- 8(A232) 8(A232) -none- -none-
+ * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
+ * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
+ * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
+ * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
+ * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
+ * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
+ * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
+ * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
+ * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
+ * 1110 -none- -none- -none- -none- -none-
+ * 1111 -none- -none- -none- -none- -none-
+*/
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-irq.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <asm/hardware/vic.h>
+
+#endif /* __ASM_ARCH_6400_REGS_IRQ_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/system.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/system.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - system implementation
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <linux/io.h>
+#include <mach/map.h>
+
+#include <plat/regs-sys.h>
+#include <plat/regs-syscon-power.h>
+
+static void arch_idle(void)
+{
+ unsigned long flags;
+ u32 mode;
+
+ /* ensure that if we execute the cpu idle sequence that we
+ * go into idle mode instead of powering off. */
+
+ local_irq_save(flags);
+ mode = __raw_readl(S3C64XX_PWR_CFG);
+ mode &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+ mode |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
+ __raw_writel(mode, S3C64XX_PWR_CFG);
+
+ local_irq_restore(flags);
+
+ cpu_do_idle();
+}
+
+static void arch_reset(char mode)
+{
+ /* nothing here yet */
+}
+
+#endif /* __ASM_ARCH_IRQ_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/tick.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s3c6400/include/mach/tick.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - Timer tick support definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TICK_H
+#define __ASM_ARCH_TICK_H __FILE__
+
+/* note, the timer interrutps turn up in 2 places, the vic and then
+ * the timer block. We take the VIC as the base at the moment.
+ */
+static inline u32 s3c24xx_ostimer_pending(void)
+{
+ u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
+ return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0));
+}
+
+#define TICK_MAX (0xffffffff)
+
+#endif /* __ASM_ARCH_6400_TICK_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/uncompress.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-s3c6400/include/mach/uncompress.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C6400 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <mach/map.h>
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
+{
+ /* we do not need to do any cpu detection here at the moment. */
+ fifo_mask = S3C2440_UFSTAT_TXMASK;
+ fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6400/Kconfig
@@ -0,0 +1,8 @@
+# arch/arm/mach-s3c6400/Kconfig
+#
+# Copyright 2008 Openmoko, Inc.
+# Simtec Electronics, Ben Dooks <ben@simtec.co.uk>
+#
+# Licensed under GPLv2
+
+# Currently nothing here, this will be added later
--- /dev/null
+++ b/arch/arm/mach-s3c6400/Makefile
@@ -0,0 +1,15 @@
+# arch/arm/mach-s3c6400/Makefile
+#
+# Copyright 2008 Openmoko, Inc.
+# Copyright 2008 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y :=
+obj-m :=
+obj-n :=
+obj- :=
+
+# Core support for S3C6400 system
+
+obj-n += blank.o
--- /dev/null
+++ b/arch/arm/mach-s3c6400/Makefile.boot
@@ -0,0 +1,2 @@
+ zreladdr-y := 0x50008000
+params_phys-y := 0x50000100
--- /dev/null
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -0,0 +1,101 @@
+/* linux/arch/arm/mach-s3c6410/cpu.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/regs-serial.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s3c6400.h>
+#include <plat/s3c6410.h>
+
+/* Initial IO mappings */
+
+static struct map_desc s3c6410_iodesc[] __initdata = {
+};
+
+/* s3c6410_map_io
+ *
+ * register the standard cpu IO areas
+*/
+
+void __init s3c6410_map_io(void)
+{
+ iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
+
+ /* initialise device information early */
+ s3c6410_default_sdhci0();
+ s3c6410_default_sdhci1();
+
+ /* the i2c devices are directly compatible with s3c2440 */
+ s3c_i2c0_setname("s3c2440-i2c");
+ s3c_i2c1_setname("s3c2440-i2c");
+}
+
+void __init s3c6410_init_clocks(int xtal)
+{
+ printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+ s3c24xx_register_baseclocks(xtal);
+ s3c64xx_register_clocks();
+ s3c6400_register_clocks();
+ s3c6400_setup_clocks();
+}
+
+void __init s3c6410_init_irq(void)
+{
+ /* VIC0 is missing IRQ7, VIC1 is fully populated. */
+ s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
+}
+
+struct sysdev_class s3c6410_sysclass = {
+ .name = "s3c6410-core",
+};
+
+static struct sys_device s3c6410_sysdev = {
+ .cls = &s3c6410_sysclass,
+};
+
+static int __init s3c6410_core_init(void)
+{
+ return sysdev_class_register(&s3c6410_sysclass);
+}
+
+core_initcall(s3c6410_core_init);
+
+int __init s3c6410_init(void)
+{
+ printk("S3C6410: Initialising architecture\n");
+
+ return sysdev_register(&s3c6410_sysdev);
+}
--- /dev/null
+++ b/arch/arm/mach-s3c6410/include/mach/om-gta03.h
@@ -0,0 +1,91 @@
+/*
+ * GTA03 GPIO Mappings
+ *
+ * (C) 2008 by Openmoko Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#ifndef _OM_GTA03_H
+#define _OM_GTA03_H
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <linux/mfd/pcf50633/core.h>
+
+extern struct pcf50633_platform_data om_gta03_pcf_pdata;
+
+/* ATAG_REVISION from bootloader */
+#define GTA03v1_SYSTEM_REV 0x00000001
+
+#define GTA03_GPIO_VIBRATOR_ON S3C64XX_GPF(13)
+#define GTA03_GPIO_CLKOUT S3C64XX_GPF(14)
+
+#define GTA03_GPIO_ACCEL_MISO S3C64XX_GPC(0)
+#define GTA03_GPIO_ACCEL_CLK S3C64XX_GPC(1)
+#define GTA03_GPIO_ACCEL_MOSI S3C64XX_GPC(2)
+
+#define GTA03_GPIO_LCM_MISO S3C64XX_GPC(4)
+#define GTA03_GPIO_LCM_CLK S3C64XX_GPC(5)
+#define GTA03_GPIO_LCM_MOSI S3C64XX_GPC(6)
+#define GTA03_GPIO_LCM_CS S3C64XX_GPC(7)
+
+#define GTA03_GPIO_BTPCM_SHARED_SCLK S3C64XX_GPE(0)
+#define GTA03_GPIO_BTPCM_SHARED_EXTCLK S3C64XX_GPE(1)
+#define GTA03_GPIO_BTPCM_SHARED_FSYNC S3C64XX_GPE(2)
+#define GTA03_GPIO_BTPCM_SHARED_SIN S3C64XX_GPE(3)
+#define GTA03_GPIO_BTPCM_SHARED_SOUT S3C64XX_GPE(4)
+
+#define GTA03_GPIO_WLAN_RESET S3C64XX_GPH(6)
+#define GTA03_GPIO_HDQ S3C64XX_GPH(7)
+#define GTA03_GPIO_WLAN_PWRDN S3C64XX_GPH(8)
+
+#define GTA03_GPIO_VERSION2 S3C64XX_GPI(0)
+#define GTA03_GPIO_VERSION1 S3C64XX_GPI(1)
+#define GTA03_GPIO_VERSION0 S3C64XX_GPI(8)
+
+#define GTA03_GPIO_NWLAN_POWER S3C64XX_GPK(0)
+#define GTA03_GPIO_MODEN_ON S3C64XX_GPK(2)
+
+#define GTA03_GPIO_TP_RESET S3C64XX_GPM(0)
+#define GTA03_GPIO_GPS_LNA_EN S3C64XX_GPM(2)
+
+#define GTA03_GPIO_USB_FLT S3C64XX_GPM(4)
+#define GTA03_GPIO_USB_OC S3C64XX_GPM(5)
+
+#define GTA03_GPIO_ACCEL_INT1 S3C64XX_GPN(0)
+#define GTA03_GPIO_KEY_MINUS S3C64XX_GPN(1)
+#define GTA03_GPIO_KEY_PLUS S3C64XX_GPN(2)
+#define GTA03_GPIO_PWR_IND S3C64XX_GPN(3)
+#define GTA03_GPIO_PWR_IRQ S3C64XX_GPN(4)
+#define GTA03_GPIO_TOUCH S3C64XX_GPN(5)
+#define GTA03_GPIO_JACK_INSERT S3C64XX_GPN(6)
+#define GTA03_GPIO_GPS_INT S3C64XX_GPN(7)
+#define GTA03_GPIO_HOLD S3C64XX_GPN(8)
+#define GTA03_GPIO_WLAN_WAKEUP S3C64XX_GPN(9)
+#define GTA03_GPIO_ACCEL_INT2 S3C64XX_GPN(10)
+#define GTA03_GPIO_IO1 S3C64XX_GPN(11)
+#define GTA03_GPIO_NONKEYWAKE S3C64XX_GPN(12)
+
+#define GTA03_GPIO_N_MODEM_RESET S3C64XX_GPO(1)
+
+#define GTA03_IRQ_GSENSOR_1 S3C_EINT(0)
+#define GTA03_IRQ_KEY_MINUS S3C_EINT(1)
+#define GTA03_IRQ_KEY_PLUS S3C_EINT(2)
+#define GTA03_IRQ_PWR_IND S3C_EINT(3)
+#define GTA03_IRQ_PMU S3C_EINT(4)
+#define GTA03_IRQ_TOUCH S3C_EINT(5)
+#define GTA03_IRQ_JACK_INSERT S3C_EINT(6)
+#define GTA03_IRQ_GPS_INT S3C_EINT(7)
+#define GTA03_IRQ_NHOLD S3C_EINT(8)
+#define GTA03_IRQ_WLAN_WAKEUP S3C_EINT(9)
+#define GTA03_IRQ_GSENSOR_2 S3C_EINT(10)
+#define GTA03_IRQ_IO1 S3C_EINT(11)
+#define GTA03_IRQ_NONKEYWAKE S3C_EINT(12)
+
+#endif /* _OM_GTA03_H */
--- /dev/null
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -0,0 +1,80 @@
+# arch/arm/mach-s3c6410/Kconfig
+#
+# Copyright 2008 Openmoko, Inc.
+# Copyright 2008 Simtec Electronics
+#
+# Licensed under GPLv2
+
+# Configuration options for the S3C6410 CPU
+
+config CPU_S3C6410
+ bool
+ select CPU_S3C6400_INIT
+ select CPU_S3C6400_CLOCK
+ help
+ Enable S3C6410 CPU support
+
+config S3C6410_SETUP_SDHCI
+ bool
+ help
+ Internal helper functions for S3C6410 based SDHCI systems
+
+config MACH_SMDK6410
+ bool "SMDK6410"
+ select CPU_S3C6410
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_I2C1
+ select S3C_DEV_FB
+ select S3C6410_SETUP_SDHCI
+ select S3C64XX_SETUP_I2C1
+ select S3C64XX_SETUP_FB_24BPP
+ help
+ Machine support for the Samsung SMDK6410
+
+# At least some of the SMDK6410s were shipped with the card detect
+# for the MMC/SD slots connected to the same input. This means that
+# either the boards need to be altered to have channel0 to an alternate
+# configuration or that only one slot can be used.
+
+choice
+ prompt "SMDK6410 MMC/SD slot setup"
+ depends on MACH_SMDK6410
+
+config SMDK6410_SD_CH0
+ bool "Use channel 0 only"
+ depends on MACH_SMDK6410
+ help
+ Select CON7 (channel 0) as the MMC/SD slot, as
+ at least some SMDK6410 boards come with the
+ resistors fitted so that the card detects for
+ channels 0 and 1 are the same.
+
+config SMDK6410_SD_CH1
+ bool "Use channel 1 only"
+ depends on MACH_SMDK6410
+ help
+ Select CON6 (channel 1) as the MMC/SD slot, as
+ at least some SMDK6410 boards come with the
+ resistors fitted so that the card detects for
+ channels 0 and 1 are the same.
+
+endchoice
+
+config MACH_OPENMOKO_GTA03
+ bool "Openmoko GTA03 Phone"
+ select CPU_S3C6410
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_I2C1
+ select S3C6410_SETUP_SDHCI
+ select S3C64XX_SETUP_I2C1
+ select S3C_DEV_FB
+ select S3C64XX_SETUP_FB_24BPP
+# select SENSORS_PCF50633
+ select POWER_SUPPLY
+# select GTA02_HDQ
+ select MACH_NEO1973
+ help
+ Machine support for the Openmoko GTA03 Phone
+
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-om-gta03.c
@@ -0,0 +1,654 @@
+/* linux/arch/arm/mach-s3c6410/mach-om_gta03.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Andy Green <andy@openmoko.org>
+ *
+ * based on mach_om_gta03.c which is
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/lis302dl.h>
+
+#include <video/platform_lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/pm.h>
+
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+/* #include <plat/udc.h> */
+#include <linux/i2c.h>
+#include <linux/backlight.h>
+#include <linux/regulator/machine.h>
+
+#include <mach/om-gta03.h>
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/led.h>
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg om_gta03_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+};
+
+
+/*
+ * Situation is that Linux SPI can't work in an interrupt context, so we
+ * implement our own bitbang here. Arbitration is needed because not only
+ * can this interrupt happen at any time even if foreground wants to use
+ * the bitbang API from Linux, but multiple motion sensors can be on the
+ * same SPI bus, and multiple interrupts can happen.
+ *
+ * Foreground / interrupt arbitration is okay because the interrupts are
+ * disabled around all the foreground SPI code.
+ *
+ * Interrupt / Interrupt arbitration is evidently needed, otherwise we
+ * lose edge-triggered service after a while due to the two sensors sharing
+ * the SPI bus having irqs at the same time eventually.
+ *
+ * Servicing is typ 75 - 100us at 400MHz.
+ */
+
+/* #define DEBUG_SPEW_MS */
+#define MG_PER_SAMPLE 18
+
+struct lis302dl_platform_data lis302_pdata;
+
+/*
+ * generic SPI RX and TX bitbang
+ * only call with interrupts off!
+ */
+
+static void __gta03_lis302dl_bitbang(struct lis302dl_info *lis, u8 *tx,
+ int tx_bytes, u8 *rx, int rx_bytes)
+{
+ struct lis302dl_platform_data *pdata = lis->pdata;
+ int n;
+ u8 shifter = 0;
+
+ gpio_direction_output(pdata->pin_chip_select, 1);
+ gpio_direction_output(pdata->pin_clk, 1);
+ gpio_direction_output(pdata->pin_chip_select, 0);
+
+ /* send the register index, r/w and autoinc bits */
+ for (n = 0; n < (tx_bytes << 3); n++) {
+ if (!(n & 7))
+ shifter = ~tx[n >> 3];
+ gpio_direction_output(pdata->pin_clk, 0);
+ gpio_direction_output(pdata->pin_mosi, !(shifter & 0x80));
+ gpio_direction_output(pdata->pin_clk, 1);
+ shifter <<= 1;
+ }
+
+ for (n = 0; n < (rx_bytes << 3); n++) { /* 8 bits each */
+ gpio_direction_output(pdata->pin_clk, 0);
+ shifter <<= 1;
+ if (gpio_direction_input(pdata->pin_miso))
+ shifter |= 1;
+ if ((n & 7) == 7)
+ rx[n >> 3] = shifter;
+ gpio_direction_output(pdata->pin_clk, 1);
+ }
+ gpio_direction_output(pdata->pin_chip_select, 1);
+}
+
+
+static int gta03_lis302dl_bitbang_read_reg(struct lis302dl_info *lis, u8 reg)
+{
+ u8 data = 0xc0 | reg; /* read, autoincrement */
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ __gta03_lis302dl_bitbang(lis, &data, 1, &data, 1);
+
+ local_irq_restore(flags);
+
+ return data;
+}
+
+static void gta03_lis302dl_bitbang_write_reg(struct lis302dl_info *lis, u8 reg,
+ u8 val)
+{
+ u8 data[2] = { 0x00 | reg, val }; /* write, no autoincrement */
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ __gta03_lis302dl_bitbang(lis, &data[0], 2, NULL, 0);
+
+ local_irq_restore(flags);
+
+}
+
+
+void gta03_lis302dl_suspend_io(struct lis302dl_info *lis, int resume)
+{
+ struct lis302dl_platform_data *pdata = lis->pdata;
+
+ if (!resume) {
+ /*
+ * we don't want to power them with a high level
+ * because GSENSOR_3V3 is not up during suspend
+ */
+ gpio_direction_output(pdata->pin_chip_select, 0);
+ gpio_direction_output(pdata->pin_clk, 0);
+ gpio_direction_output(pdata->pin_mosi, 0);
+ s3c_gpio_setpull(pdata->pin_miso, S3C_GPIO_PULL_DOWN);
+
+ return;
+ }
+
+ /* back to normal */
+ gpio_direction_output(pdata->pin_chip_select, 1);
+ gpio_direction_output(pdata->pin_clk, 1);
+ s3c_gpio_setpull(pdata->pin_miso, S3C_GPIO_PULL_NONE);
+
+ s3c_gpio_cfgpin(pdata->pin_chip_select, S3C_GPIO_SFN(1));
+ s3c_gpio_cfgpin(pdata->pin_clk, S3C_GPIO_SFN(1));
+ s3c_gpio_cfgpin(pdata->pin_mosi, S3C_GPIO_SFN(1));
+ s3c_gpio_cfgpin(pdata->pin_miso, S3C_GPIO_SFN(0));
+
+}
+
+struct lis302dl_platform_data lis302_pdata = {
+ .name = "lis302",
+ .pin_chip_select= S3C64XX_GPC(3), /* NC */
+ .pin_clk = GTA03_GPIO_ACCEL_CLK,
+ .pin_mosi = GTA03_GPIO_ACCEL_MOSI,
+ .pin_miso = GTA03_GPIO_ACCEL_MISO,
+ .interrupt = GTA03_IRQ_GSENSOR_1,
+ .open_drain = 0,
+ .lis302dl_bitbang = __gta03_lis302dl_bitbang,
+ .lis302dl_bitbang_reg_read = gta03_lis302dl_bitbang_read_reg,
+ .lis302dl_bitbang_reg_write = gta03_lis302dl_bitbang_write_reg,
+ .lis302dl_suspend_io = gta03_lis302dl_suspend_io,
+};
+
+static struct platform_device s3c_device_spi_acc1 = {
+ .name = "lis302dl",
+ .id = 1,
+ .dev = {
+ .platform_data = &lis302_pdata,
+ },
+};
+
+
+
+/* framebuffer and LCD setup. */
+
+/* GPF15 = LCD backlight control
+ * GPF13 => Panel power
+ * GPN5 = LCD nRESET signal
+ * PWM_TOUT1 => backlight brightness
+ */
+
+static void om_gta03_lcd_power_set(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+
+}
+
+static struct plat_lcd_data om_gta03_lcd_power_data = {
+ .set_power = om_gta03_lcd_power_set,
+};
+
+static struct platform_device om_gta03_lcd_powerdev = {
+ .name = "platform-lcd",
+ .dev.parent = &s3c_device_fb.dev,
+ .dev.platform_data = &om_gta03_lcd_power_data,
+};
+
+static struct s3c_fb_pd_win om_gta03_fb_win0 = {
+ /* this is to ensure we use win0 */
+ .win_mode = {
+ .pixclock = 40816,
+ .left_margin = 8,
+ .right_margin = 16,
+ .upper_margin = 2,
+ .lower_margin = 16,
+ .hsync_len = 8,
+ .vsync_len = 2,
+ .xres = 640,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+};
+
+static struct s3c_fb_platdata om_gta03_lcd_pdata __initdata = {
+ .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
+ .win[0] = &om_gta03_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+
+struct map_desc om_gta03_6410_iodesc[] = {};
+
+static struct resource om_gta03_button_resources[] = {
+ [0] = {
+ .start = 0,
+ .end = 0,
+ },
+ [1] = {
+ .start = GTA03_GPIO_HOLD,
+ .end = GTA03_GPIO_HOLD,
+ },
+ [2] = {
+ .start = GTA03_GPIO_JACK_INSERT,
+ .end = GTA03_GPIO_JACK_INSERT,
+ },
+ [3] = {
+ .start = GTA03_GPIO_KEY_PLUS,
+ .end = GTA03_GPIO_KEY_PLUS,
+ },
+ [4] = {
+ .start = GTA03_GPIO_KEY_MINUS,
+ .end = GTA03_GPIO_KEY_MINUS,
+ },
+};
+
+static struct platform_device om_gta03_button_dev = {
+ .name = "neo1973-button",
+ .num_resources = ARRAY_SIZE(om_gta03_button_resources),
+ .resource = om_gta03_button_resources,
+};
+
+
+/********************** PMU ***************************/
+/*
+ * GTA03 PMU Mapping info
+ *
+ * name maxcurr default Nom consumers
+ *
+ * AUTO 1100mA ON 3.3V 3.3V Main 3.3V rail
+ * DOWN1 500mA ON 1.2V 1.2V CPU VddARM, VddINT, VddMPLL, VddOTGI
+ * DOWN2 500mA ON 1.8V 1.8V CPU VddAlive via LDO, Memories, WLAN
+ * LED 25mA OFF 18V Backlight
+ * HCLDO 200mA OFF 2.8V Camera 2V8
+ * LDO1 50mA ON 3.3V 3.3V Accel
+ * LDO2 50mA OFF 1.5V Camera 1V5
+ * LDO3 50mA OFF 3.3V CODEC 3.3V
+ * LDO4 150mA ON 2.8V 2.7V uSD power
+ * LDO5 150mA OFF 3.0V GPS 3V
+ * LDO6 50mA ON 3.0V 3.0V LCM 3V
+ *
+ */
+
+
+/* PMU driver info */
+
+
+static struct regulator_consumer_supply ldo4_consumers[] = {
+ {
+ .dev = &s3c_device_hsmmc0.dev,
+ .supply = "SD_3V",
+ },
+};
+
+static struct platform_device om_gta03_features_dev = {
+ .name = "om-gta03",
+};
+
+static struct regulator_consumer_supply ldo5_consumers[] = {
+ {
+ .dev = &om_gta03_features_dev.dev,
+ .supply = "RF_3V",
+ },
+};
+
+
+static void om_gta03_pmu_event_callback(struct pcf50633 *pcf, int irq)
+{
+#if 0
+ if (irq == PCF50633_IRQ_USBINS) {
+ schedule_delayed_work(&gta02_charger_work,
+ GTA02_CHARGER_CONFIGURE_TIMEOUT);
+ return;
+ } else if (irq == PCF50633_IRQ_USBREM) {
+ cancel_delayed_work_sync(&gta02_charger_work);
+ pcf50633_mbc_usb_curlim_set(pcf, 0);
+ gta02_usb_vbus_draw = 0;
+ }
+
+ bq27000_charging_state_change(&bq27000_battery_device);
+#endif
+}
+
+
+static void om_gta03_pcf50633_attach_child_devices(struct pcf50633 *pcf);
+static void om_gta03_pmu_regulator_registered(struct pcf50633 *pcf, int id);
+
+struct pcf50633_platform_data om_gta03_pcf_pdata = {
+
+ .resumers = {
+ [0] = PCF50633_INT1_USBINS |
+ PCF50633_INT1_USBREM |
+ PCF50633_INT1_ALARM,
+ [1] = PCF50633_INT2_ONKEYF,
+ [2] = PCF50633_INT3_ONKEY1S
+ },
+
+ .reg_init_data = {
+ /* GTA03: Main 3.3V rail */
+ [PCF50633_REGULATOR_AUTO] = {
+ .constraints = {
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* GTA03: CPU core power */
+ [PCF50633_REGULATOR_DOWN1] = {
+ .constraints = {
+ .min_uV = 900000,
+ .max_uV = 1200000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* GTA03: Memories */
+ [PCF50633_REGULATOR_DOWN2] = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* GTA03: Camera 2V8 */
+ [PCF50633_REGULATOR_HCLDO] = {
+ .constraints = {
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ },
+ .num_consumer_supplies = 0,
+/* .consumer_supplies = hcldo_consumers, */
+ },
+
+ /* GTA03: Accel 3V3 */
+ [PCF50633_REGULATOR_LDO1] = {
+ .constraints = {
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* GTA03: Camera 1V5 */
+ [PCF50633_REGULATOR_LDO2] = {
+ .constraints = {
+ .min_uV = 1500000,
+ .max_uV = 1500000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* GTA03: Codec 3.3V */
+ [PCF50633_REGULATOR_LDO3] = {
+ .constraints = {
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* GTA03: uSD Power */
+ [PCF50633_REGULATOR_LDO4] = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = ldo4_consumers,
+ },
+ /* GTA03: GPS 3V */
+ [PCF50633_REGULATOR_LDO5] = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = 1,
+ .consumer_supplies = ldo5_consumers,
+ },
+ /* GTA03: LCM 3V */
+ [PCF50633_REGULATOR_LDO6] = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+ /* power for memories in suspend */
+ [PCF50633_REGULATOR_MEMLDO] = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = 0,
+ },
+
+ },
+ .probe_done = om_gta03_pcf50633_attach_child_devices,
+ .regulator_registered = om_gta03_pmu_regulator_registered,
+ .mbc_event_callback = om_gta03_pmu_event_callback,
+};
+
+
+static struct i2c_board_info om_gta03_i2c_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("pcf50633", 0x73),
+ .irq = GTA03_IRQ_PMU,
+ .platform_data = &om_gta03_pcf_pdata,
+ },
+ {
+ I2C_BOARD_INFO("pcap7200", 0x0a),
+ .irq = GTA03_IRQ_TOUCH,
+ },
+
+};
+
+
+static struct platform_device *om_gta03_devices[] __initdata = {
+ &s3c_device_fb,
+ &s3c_device_i2c0,
+ &s3c_device_hsmmc1, /* SDIO to WLAN */
+};
+
+
+static void om_gta03_pmu_regulator_registered(struct pcf50633 *pcf, int id)
+{
+ struct platform_device *regulator, *pdev;
+
+ regulator = pcf->pmic.pdev[id];
+
+ switch(id) {
+ case PCF50633_REGULATOR_LDO4:
+ pdev = &s3c_device_hsmmc0;
+ break;
+ case PCF50633_REGULATOR_LDO5: /* GPS regulator */
+ pdev = &om_gta03_features_dev;
+ break;
+ case PCF50633_REGULATOR_LDO6:
+ pdev = &om_gta03_lcd_powerdev;
+ break;
+ default:
+ return;
+ }
+
+ pdev->dev.parent = &regulator->dev;
+ platform_device_register(pdev);
+}
+
+static struct platform_device *om_gta03_devices_pmu_children[] = {
+ &om_gta03_button_dev,
+ &s3c_device_spi_acc1, /* relies on PMU reg for power */
+};
+
+/* this is called when pc50633 is probed, unfortunately quite late in the
+ * day since it is an I2C bus device. Here we can belatedly define some
+ * platform devices with the advantage that we can mark the pcf50633 as the
+ * parent. This makes them get suspended and resumed with their parent
+ * the pcf50633 still around.
+ */
+
+static void om_gta03_pcf50633_attach_child_devices(struct pcf50633 *pcf)
+{
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(om_gta03_devices_pmu_children); n++)
+ om_gta03_devices_pmu_children[n]->dev.parent = pcf->dev;
+
+ platform_add_devices(om_gta03_devices_pmu_children,
+ ARRAY_SIZE(om_gta03_devices_pmu_children));
+
+ /* Switch on backlight. Qi does not do it for us */
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x3f);
+
+}
+
+
+
+extern void s3c64xx_init_io(struct map_desc *, int);
+
+static void __init om_gta03_map_io(void)
+{
+ s3c64xx_init_io(om_gta03_6410_iodesc, ARRAY_SIZE(om_gta03_6410_iodesc));
+ s3c24xx_init_clocks(12000000);
+ s3c24xx_init_uarts(om_gta03_uartcfgs, ARRAY_SIZE(om_gta03_uartcfgs));
+}
+
+static void __init om_gta03_machine_init(void)
+{
+ s3c_pm_init();
+
+ s3c_i2c0_set_platdata(NULL);
+ s3c_fb_set_platdata(&om_gta03_lcd_pdata);
+
+ s3c_gpio_setpull(S3C64XX_GPH(0), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPH(1), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPH(2), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPH(3), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPH(4), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPH(5), S3C_GPIO_PULL_UP);
+
+
+ i2c_register_board_info(0, om_gta03_i2c_devs,
+ ARRAY_SIZE(om_gta03_i2c_devs));
+
+ platform_add_devices(om_gta03_devices, ARRAY_SIZE(om_gta03_devices));
+}
+
+MACHINE_START(OPENMOKO_GTA03, "OM-GTA03")
+ /* Maintainer: Andy Green <andy@openmoko.com> */
+ .phys_io = S3C_PA_UART & 0xfff00000,
+ .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+ .boot_params = S3C64XX_PA_SDRAM + 0x100,
+
+ .init_irq = s3c6410_init_irq,
+ .map_io = om_gta03_map_io,
+ .init_machine = om_gta03_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
+
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -0,0 +1,205 @@
+/* linux/arch/arm/mach-s3c6410/mach-smdk6410.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+
+#include <video/platform_lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-modem.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-sys.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/pm.h>
+
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
+#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
+#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+
+static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = 0x3c5,
+ .ulcon = 0x03,
+ .ufcon = 0x51,
+ },
+};
+
+/* framebuffer and LCD setup. */
+
+/* GPF15 = LCD backlight control
+ * GPF13 => Panel power
+ * GPN5 = LCD nRESET signal
+ * PWM_TOUT1 => backlight brightness
+ */
+
+static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power) {
+ gpio_direction_output(S3C64XX_GPF(13), 1);
+ gpio_direction_output(S3C64XX_GPF(15), 1);
+
+ /* fire nRESET on power up */
+ gpio_direction_output(S3C64XX_GPN(5), 0);
+ msleep(10);
+ gpio_direction_output(S3C64XX_GPN(5), 1);
+ msleep(1);
+ } else {
+ gpio_direction_output(S3C64XX_GPF(15), 0);
+ gpio_direction_output(S3C64XX_GPF(13), 0);
+ }
+}
+
+static struct plat_lcd_data smdk6410_lcd_power_data = {
+ .set_power = smdk6410_lcd_power_set,
+};
+
+static struct platform_device smdk6410_lcd_powerdev = {
+ .name = "platform-lcd",
+ .dev.parent = &s3c_device_fb.dev,
+ .dev.platform_data = &smdk6410_lcd_power_data,
+};
+
+static struct s3c_fb_pd_win smdk6410_fb_win0 = {
+ /* this is to ensure we use win0 */
+ .win_mode = {
+ .pixclock = 41094,
+ .left_margin = 8,
+ .right_margin = 13,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+};
+
+/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
+static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
+ .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
+ .win[0] = &smdk6410_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+struct map_desc smdk6410_iodesc[] = {};
+
+static struct platform_device *smdk6410_devices[] __initdata = {
+#ifdef CONFIG_SMDK6410_SD_CH0
+ &s3c_device_hsmmc0,
+#endif
+#ifdef CONFIG_SMDK6410_SD_CH1
+ &s3c_device_hsmmc1,
+#endif
+ &s3c_device_i2c0,
+ &s3c_device_i2c1,
+ &s3c_device_fb,
+ &smdk6410_lcd_powerdev,
+};
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+ { I2C_BOARD_INFO("24c08", 0x50), },
+ { I2C_BOARD_INFO("WM8580", 0X1b), },
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+ { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
+};
+
+static void __init smdk6410_map_io(void)
+{
+ u32 tmp;
+
+ s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
+ s3c24xx_init_clocks(12000000);
+ s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+
+ /* set the LCD type */
+
+ tmp = __raw_readl(S3C64XX_SPCON);
+ tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+ tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+ __raw_writel(tmp, S3C64XX_SPCON);
+
+ /* remove the lcd bypass */
+ tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+ tmp &= ~MIFPCON_LCD_BYPASS;
+ __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+static void __init smdk6410_machine_init(void)
+{
+ s3c_pm_init();
+
+ s3c_i2c0_set_platdata(NULL);
+ s3c_i2c1_set_platdata(NULL);
+ s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+
+ i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+ i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+ platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
+}
+
+MACHINE_START(SMDK6410, "SMDK6410")
+ /* Maintainer: Ben Dooks <ben@fluff.org> */
+ .phys_io = S3C_PA_UART & 0xfff00000,
+ .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+ .boot_params = S3C64XX_PA_SDRAM + 0x100,
+
+ .init_irq = s3c6410_init_irq,
+ .map_io = smdk6410_map_io,
+ .init_machine = smdk6410_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
--- /dev/null
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -0,0 +1,26 @@
+# arch/arm/plat-s3c6410/Makefile
+#
+# Copyright 2008 Openmoko, Inc.
+# Copyright 2008 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y :=
+obj-m :=
+obj-n :=
+obj- :=
+
+# Core support for S3C6410 system
+
+obj-$(CONFIG_CPU_S3C6410) += cpu.o
+
+# Helper and device support
+
+obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
+obj-$(CONFIG_MACH_OPENMOKO_GTA03) += mach-om-gta03.o \
+ om-gta03-features.o
+
--- /dev/null
+++ b/arch/arm/mach-s3c6410/om-gta03-features.c
@@ -0,0 +1,344 @@
+/*
+ * Support for features of Openmoko GTA03
+ *
+ * (C) 2008 by Openmoko Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * Somewhat based on the GTA01 / 02 neo1973_pm_ stuff mainly by Harald Welte
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <mach/om-gta03.h>
+#include <asm/mach-types.h>
+
+#include <linux/regulator/consumer.h>
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mmc/host.h>
+
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+
+#include <plat/gpio-cfg.h>
+
+enum feature {
+ OM_GTA03_GPS, /* power to GPS section and LNA */
+ OM_GTA03_WLAN_BT, /* WLAN and BT Module */
+ OM_GTA03_GSM, /* GSM module */
+ OM_GTA03_USBHOST, /* USB Host power generation */
+ OM_GTA03_VIB, /* Vibrator */
+
+ OM_GTA03_FEATURE_COUNT /* always last */
+};
+
+
+struct om_gta03_feature_info {
+ const char * name;
+ int depower_on_suspend;
+ int on;
+};
+
+static struct om_gta03_feature_info feature_info[OM_GTA03_FEATURE_COUNT] = {
+ [OM_GTA03_GPS] = { "gps_power", 1, 0 },
+ [OM_GTA03_WLAN_BT] = { "wlan_bt_power", 1, 0 },
+ [OM_GTA03_GSM] = { "gsm_power", 0, 0 },
+ [OM_GTA03_USBHOST] = { "usbhost_power", 1, 0 },
+ [OM_GTA03_VIB] = { "vibrator_power", 1, 0 },
+};
+
+static struct regulator *gps_regulator;
+
+
+
+static void om_gta03_features_pwron_set_on(enum feature feature)
+{
+ int gpio;
+
+ switch (feature) {
+ case OM_GTA03_GPS:
+ regulator_enable(gps_regulator);
+ /* enable LNA */
+ gpio_direction_output(GTA03_GPIO_GPS_LNA_EN, 1);
+ break;
+ case OM_GTA03_WLAN_BT:
+
+ for (gpio = S3C64XX_GPH(0); gpio < S3C64XX_GPH(6); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); /* sdio */
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ }
+ /* assert reset */
+ s3c_gpio_setpull(GTA03_GPIO_WLAN_RESET, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_WLAN_RESET, S3C_GPIO_SFN(1));
+ gpio_direction_output(GTA03_GPIO_WLAN_RESET, 0);
+
+ /* "full power down (active low)" -- deassert it*/
+ gpio_direction_output(GTA03_GPIO_WLAN_PWRDN, 1);
+ s3c_gpio_setpull(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_SFN(1));
+
+ /* enable P-Channel mosfet switch for power */
+ gpio_direction_output(GTA03_GPIO_NWLAN_POWER, 0);
+ s3c_gpio_setpull(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_SFN(1));
+ msleep(50);
+ /* deassert reset */
+ gpio_direction_output(GTA03_GPIO_WLAN_RESET, 1);
+ msleep(1500);
+ sdhci_s3c_force_presence_change(&s3c_device_hsmmc1);
+ break;
+ case OM_GTA03_GSM:
+ /* give power to GSM module */
+ s3c_gpio_setpull(GTA03_GPIO_N_MODEM_RESET, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_N_MODEM_RESET, S3C_GPIO_SFN(1));
+ gpio_direction_output(GTA03_GPIO_N_MODEM_RESET, 0);
+
+ gpio_direction_output(GTA03_GPIO_MODEN_ON, 0);
+ s3c_gpio_setpull(GTA03_GPIO_MODEN_ON, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_MODEN_ON, S3C_GPIO_SFN(1));
+ msleep(1);
+ gpio_direction_output(GTA03_GPIO_N_MODEM_RESET, 1);
+ break;
+ case OM_GTA03_USBHOST:
+ pcf50633_gpio_set(om_gta03_pcf_pdata.pcf, PCF50633_GPO, 1);
+ break;
+ case OM_GTA03_VIB:
+ gpio_direction_output(GTA03_GPIO_VIBRATOR_ON, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static void om_gta03_features_pwron_set_off(enum feature feature)
+{
+ int gpio;
+
+ switch (feature) {
+ case OM_GTA03_GPS:
+ /* disable LNA */
+ gpio_direction_output(GTA03_GPIO_GPS_LNA_EN, 0);
+ regulator_disable(gps_regulator);
+ break;
+ case OM_GTA03_WLAN_BT:
+ gpio_direction_output(GTA03_GPIO_WLAN_RESET, 0);
+ s3c_gpio_setpull(GTA03_GPIO_WLAN_RESET, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_WLAN_RESET, S3C_GPIO_SFN(1));
+
+ gpio_direction_output(GTA03_GPIO_WLAN_PWRDN, 0);
+ s3c_gpio_setpull(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_WLAN_PWRDN, S3C_GPIO_SFN(1));
+ msleep(500);
+ /* remove power from WLAN / BT module */
+ gpio_direction_output(GTA03_GPIO_NWLAN_POWER, 1);
+ s3c_gpio_setpull(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_NWLAN_POWER, S3C_GPIO_SFN(1));
+
+ sdhci_s3c_force_presence_change(&s3c_device_hsmmc1);
+ for (gpio = S3C64XX_GPH(0); gpio < S3C64XX_GPH(6); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); /* input */
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_DOWN);
+ }
+ break;
+ case OM_GTA03_GSM:
+ /* remove power from WLAN / BT module */
+ gpio_direction_output(GTA03_GPIO_MODEN_ON, 1);
+ s3c_gpio_setpull(GTA03_GPIO_MODEN_ON, S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(GTA03_GPIO_MODEN_ON, S3C_GPIO_SFN(1));
+ break;
+ case OM_GTA03_USBHOST:
+ pcf50633_gpio_set(om_gta03_pcf_pdata.pcf, PCF50633_GPO, 0);
+ break;
+ case OM_GTA03_VIB:
+ gpio_direction_output(GTA03_GPIO_VIBRATOR_ON, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+static void om_gta03_features_pwron_set(enum feature feature, int on)
+{
+ if ((on) && (!feature_info[feature].on))
+ om_gta03_features_pwron_set_on(feature);
+ else
+ if ((!on) && (feature_info[feature].on))
+ om_gta03_features_pwron_set_off(feature);
+}
+
+static ssize_t om_gta03_feature_read(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int on;
+ int feature = 0;
+ int hit = 0;
+
+ while (!hit && feature < OM_GTA03_FEATURE_COUNT) {
+ if (!strcmp(attr->attr.name, feature_info[feature].name))
+ hit = 1;
+ else
+ feature++;
+ }
+
+ if (!hit)
+ return -EINVAL;
+
+ switch (feature) {
+ case OM_GTA03_GPS:
+ on = regulator_is_enabled(gps_regulator);
+ break;
+ case OM_GTA03_USBHOST:
+ on = pcf50633_gpio_get(om_gta03_pcf_pdata.pcf, PCF50633_GPO);
+ break;
+ default:
+ on = feature_info[feature].on;
+ }
+
+ *buf++ = '0' + on;
+ *buf++='\n';
+ *buf = '\0';
+
+ return 3;
+}
+
+static ssize_t om_gta03_feature_write(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int on = !!simple_strtoul(buf, NULL, 10);
+ int feature = 0;
+ int hit = 0;
+
+ while (!hit && feature < OM_GTA03_FEATURE_COUNT) {
+ if (!strcmp(attr->attr.name, feature_info[feature].name))
+ hit = 1;
+ else
+ feature++;
+ }
+
+ if (!hit)
+ return -EINVAL;
+
+ om_gta03_features_pwron_set(feature, on);
+ feature_info[feature].on = on;
+
+ return count;
+}
+
+
+static DEVICE_ATTR(gps_power, 0644, om_gta03_feature_read,
+ om_gta03_feature_write);
+
+static DEVICE_ATTR(wlan_bt_power, 0644, om_gta03_feature_read,
+ om_gta03_feature_write);
+
+static DEVICE_ATTR(gsm_power, 0644, om_gta03_feature_read,
+ om_gta03_feature_write);
+
+static DEVICE_ATTR(usbhost_power, 0644, om_gta03_feature_read,
+ om_gta03_feature_write);
+
+static DEVICE_ATTR(vibrator_power, 0644, om_gta03_feature_read,
+ om_gta03_feature_write);
+
+
+static struct attribute *om_gta03_features_sysfs_entries[] = {
+ &dev_attr_gps_power.attr,
+ &dev_attr_wlan_bt_power.attr,
+ &dev_attr_gsm_power.attr,
+ &dev_attr_usbhost_power.attr,
+ &dev_attr_vibrator_power.attr,
+ NULL
+};
+
+
+static struct attribute_group om_gta03_features_attr_group = {
+ .name = NULL,
+ .attrs = om_gta03_features_sysfs_entries,
+};
+
+static int __init om_gta03_features_probe(struct platform_device *pdev)
+{
+ gps_regulator = regulator_get(&pdev->dev, "RF_3V");
+ dev_info(&pdev->dev, "starting\n");
+
+ return sysfs_create_group(&pdev->dev.kobj,
+ &om_gta03_features_attr_group);
+}
+
+static int om_gta03_features_remove(struct platform_device *pdev)
+{
+
+ regulator_put(gps_regulator);
+ sysfs_remove_group(&pdev->dev.kobj, &om_gta03_features_attr_group);
+
+ return 0;
+}
+
+
+#ifdef CONFIG_PM
+static int om_gta03_features_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ int feature;
+
+ for (feature = 0; feature < OM_GTA03_FEATURE_COUNT; feature++)
+ if (feature_info[feature].depower_on_suspend)
+ om_gta03_features_pwron_set_off(feature);
+
+ return 0;
+}
+
+static int om_gta03_features_resume(struct platform_device *pdev)
+{
+ int feature;
+
+ for (feature = 0; feature < OM_GTA03_FEATURE_COUNT; feature++)
+ if (feature_info[feature].depower_on_suspend)
+ if (feature_info[feature].on)
+ om_gta03_features_pwron_set_on(feature);
+
+ return 0;
+}
+#else
+#define om_gta03_features_suspend NULL
+#define om_gta03_features_resume NULL
+#endif
+
+static struct platform_driver om_gta03_features_driver = {
+ .probe = om_gta03_features_probe,
+ .remove = om_gta03_features_remove,
+ .suspend = om_gta03_features_suspend,
+ .resume = om_gta03_features_resume,
+ .driver = {
+ .name = "om-gta03",
+ },
+};
+
+static int __devinit om_gta03_features_init(void)
+{
+ return platform_driver_register(&om_gta03_features_driver);
+}
+
+static void om_gta03_features_exit(void)
+{
+ platform_driver_unregister(&om_gta03_features_driver);
+}
+
+module_init(om_gta03_features_init);
+module_exit(om_gta03_features_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Openmoko GTA03 Feature Driver");
--- /dev/null
+++ b/arch/arm/mach-s3c6410/setup-sdhci.c
@@ -0,0 +1,103 @@
+/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <mach/gpio.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s3c6410_hsmmc_clksrcs[4] = {
+ [0] = "hsmmc",
+ [1] = "hsmmc",
+ [2] = "mmc_bus",
+ /* [3] = "48m", - note not succesfully used yet */
+};
+
+void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+ unsigned int gpio;
+ unsigned int end;
+
+ end = S3C64XX_GPG(2 + width);
+
+ /* Set all the necessary GPG pins to special-function 0 */
+ for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ }
+
+ /* FIXME this needs defining in machine as to if we even have CD */
+ s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
+ s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
+}
+
+void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
+ void __iomem *r,
+ struct mmc_ios *ios,
+ struct mmc_card *card)
+{
+ u32 ctrl2, ctrl3;
+
+ /* don't need to alter anything acording to card-type */
+
+ writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
+
+ ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+ ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+ S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+ S3C_SDHCI_CTRL2_ENFBCLKRX |
+ S3C_SDHCI_CTRL2_DFCNT_NONE |
+ S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+ if (ios->clock < 25 * 1000000)
+ ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+ S3C_SDHCI_CTRL3_FCSEL2 |
+ S3C_SDHCI_CTRL3_FCSEL1 |
+ S3C_SDHCI_CTRL3_FCSEL0);
+ else
+ ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+ printk(KERN_INFO "%s: %p CTRL 2=%08x, 3=%08x\n", __func__, r, ctrl2, ctrl3);
+ writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+ writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
+
+void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+ unsigned int gpio;
+ unsigned int end;
+
+ end = S3C64XX_GPH(2 + width);
+
+ /* Set all the necessary GPG pins to special-function 0 */
+ for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ }
+
+// s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+// s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
+}
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -121,7 +121,10 @@
machine-$(CONFIG_ARCH_OMAP3) := omap2
plat-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
+ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
+ machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
+ plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_IMX) := imx
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -183,14 +183,14 @@
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
MACH_VERSATILE_AB || ARCH_OMAP730 || \
ARCH_OMAP16XX || MACH_REALVIEW_EB || \
- ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
+ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \
ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
ARCH_OMAP730 || ARCH_OMAP16XX || \
- ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
+ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_S3C24A0 || \
ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
@@ -400,9 +400,10 @@
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"
- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || ARCH_S3C64XX
default y if ARCH_MX3
default y if ARCH_MSM
+ default y if ARCH_S3C64XX
select CPU_32v6
select CPU_ABRT_EV6
select CPU_PABRT_NOIFAR
--- /dev/null
+++ b/arch/arm/plat-s3c/clock.c
@@ -0,0 +1,369 @@
+/* linux/arch/arm/plat-s3c24xx/clock.c
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX Core clock control support
+ *
+ * Based on, and code from linux/arch/arm/mach-versatile/clock.c
+ **
+ ** Copyright (C) 2004 ARM Limited.
+ ** Written by Deep Blue Solutions Limited.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+
+#include <plat/cpu-freq.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* clock information */
+
+static LIST_HEAD(clocks);
+
+/* We originally used an mutex here, but some contexts (see resume)
+ * are calling functions such as clk_set_parent() with IRQs disabled
+ * causing an BUG to be triggered.
+ */
+DEFINE_SPINLOCK(clocks_lock);
+
+/* enable and disable calls for use with the clk struct */
+
+static int clk_null_enable(struct clk *clk, int enable)
+{
+ return 0;
+}
+
+/* Clock API calls */
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ struct clk *p;
+ struct clk *clk = ERR_PTR(-ENOENT);
+ int idno;
+
+ if (dev == NULL || dev->bus != &platform_bus_type)
+ idno = -1;
+ else
+ idno = to_platform_device(dev)->id;
+
+ spin_lock(&clocks_lock);
+
+ list_for_each_entry(p, &clocks, list) {
+ if (p->id == idno &&
+ strcmp(id, p->name) == 0 &&
+ try_module_get(p->owner)) {
+ clk = p;
+ break;
+ }
+ }
+
+ /* check for the case where a device was supplied, but the
+ * clock that was being searched for is not device specific */
+
+ if (IS_ERR(clk)) {
+ list_for_each_entry(p, &clocks, list) {
+ if (p->id == -1 && strcmp(id, p->name) == 0 &&
+ try_module_get(p->owner)) {
+ clk = p;
+ break;
+ }
+ }
+ }
+
+ spin_unlock(&clocks_lock);
+ return clk;
+}
+
+void clk_put(struct clk *clk)
+{
+ module_put(clk->owner);
+}
+
+int clk_enable(struct clk *clk)
+{
+ if (IS_ERR(clk) || clk == NULL)
+ return -EINVAL;
+
+ clk_enable(clk->parent);
+
+ spin_lock(&clocks_lock);
+
+ if ((clk->usage++) == 0)
+ (clk->enable)(clk, 1);
+
+ spin_unlock(&clocks_lock);
+ return 0;
+}
+
+void clk_disable(struct clk *clk)
+{
+ if (IS_ERR(clk) || clk == NULL)
+ return;
+
+ spin_lock(&clocks_lock);
+
+ if ((--clk->usage) == 0)
+ (clk->enable)(clk, 0);
+
+ spin_unlock(&clocks_lock);
+ clk_disable(clk->parent);
+}
+
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ if (IS_ERR(clk))
+ return 0;
+
+ if (clk->rate != 0)
+ return clk->rate;
+
+ if (clk->get_rate != NULL)
+ return (clk->get_rate)(clk);
+
+ if (clk->parent != NULL)
+ return clk_get_rate(clk->parent);
+
+ return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ if (!IS_ERR(clk) && clk->round_rate)
+ return (clk->round_rate)(clk, rate);
+
+ return rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret;
+
+ if (IS_ERR(clk))
+ return -EINVAL;
+
+ /* We do not default just do a clk->rate = rate as
+ * the clock may have been made this way by choice.
+ */
+
+ WARN_ON(clk->set_rate == NULL);
+
+ if (clk->set_rate == NULL)
+ return -EINVAL;
+
+ spin_lock(&clocks_lock);
+ ret = (clk->set_rate)(clk, rate);
+ spin_unlock(&clocks_lock);
+
+ return ret;
+}
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ return clk->parent;
+}
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ int ret = 0;
+
+ if (IS_ERR(clk))
+ return -EINVAL;
+
+ spin_lock(&clocks_lock);
+
+ if (clk->set_parent)
+ ret = (clk->set_parent)(clk, parent);
+
+ spin_unlock(&clocks_lock);
+
+ return ret;
+}
+
+EXPORT_SYMBOL(clk_get);
+EXPORT_SYMBOL(clk_put);
+EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_disable);
+EXPORT_SYMBOL(clk_get_rate);
+EXPORT_SYMBOL(clk_round_rate);
+EXPORT_SYMBOL(clk_set_rate);
+EXPORT_SYMBOL(clk_get_parent);
+EXPORT_SYMBOL(clk_set_parent);
+
+/* base clocks */
+
+static int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+ clk->rate = rate;
+ return 0;
+}
+
+struct clk clk_xtal = {
+ .name = "xtal",
+ .id = -1,
+ .rate = 0,
+ .parent = NULL,
+ .ctrlbit = 0,
+};
+
+struct clk clk_ext = {
+ .name = "ext",
+ .id = -1,
+};
+
+struct clk clk_epll = {
+ .name = "epll",
+ .id = -1,
+};
+
+struct clk clk_mpll = {
+ .name = "mpll",
+ .id = -1,
+ .set_rate = clk_default_setrate,
+};
+
+struct clk clk_upll = {
+ .name = "upll",
+ .id = -1,
+ .parent = NULL,
+ .ctrlbit = 0,
+};
+
+struct clk clk_f = {
+ .name = "fclk",
+ .id = -1,
+ .rate = 0,
+ .parent = &clk_mpll,
+ .ctrlbit = 0,
+ .set_rate = clk_default_setrate,
+};
+
+struct clk clk_h = {
+ .name = "hclk",
+ .id = -1,
+ .rate = 0,
+ .parent = NULL,
+ .ctrlbit = 0,
+ .set_rate = clk_default_setrate,
+};
+
+struct clk clk_p = {
+ .name = "pclk",
+ .id = -1,
+ .rate = 0,
+ .parent = NULL,
+ .ctrlbit = 0,
+ .set_rate = clk_default_setrate,
+};
+
+struct clk clk_usb_bus = {
+ .name = "usb-bus",
+ .id = -1,
+ .rate = 0,
+ .parent = &clk_upll,
+};
+
+
+
+struct clk s3c24xx_uclk = {
+ .name = "uclk",
+ .id = -1,
+};
+
+/* initialise the clock system */
+
+int s3c24xx_register_clock(struct clk *clk)
+{
+ clk->owner = THIS_MODULE;
+
+ if (clk->enable == NULL)
+ clk->enable = clk_null_enable;
+
+ /* add to the list of available clocks */
+
+ /* Quick check to see if this clock has already been registered. */
+ BUG_ON(clk->list.prev != clk->list.next);
+
+ spin_lock(&clocks_lock);
+ list_add(&clk->list, &clocks);
+ spin_unlock(&clocks_lock);
+
+ return 0;
+}
+
+int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
+{
+ int fails = 0;
+
+ for (; nr_clks > 0; nr_clks--, clks++) {
+ if (s3c24xx_register_clock(*clks) < 0)
+ fails++;
+ }
+
+ return fails;
+}
+
+/* initalise all the clocks */
+
+int __init s3c24xx_register_baseclocks(unsigned long xtal)
+{
+ printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
+
+ clk_xtal.rate = xtal;
+
+ /* register our clocks */
+
+ if (s3c24xx_register_clock(&clk_xtal) < 0)
+ printk(KERN_ERR "failed to register master xtal\n");
+
+ if (s3c24xx_register_clock(&clk_mpll) < 0)
+ printk(KERN_ERR "failed to register mpll clock\n");
+
+ if (s3c24xx_register_clock(&clk_upll) < 0)
+ printk(KERN_ERR "failed to register upll clock\n");
+
+ if (s3c24xx_register_clock(&clk_f) < 0)
+ printk(KERN_ERR "failed to register cpu fclk\n");
+
+ if (s3c24xx_register_clock(&clk_h) < 0)
+ printk(KERN_ERR "failed to register cpu hclk\n");
+
+ if (s3c24xx_register_clock(&clk_p) < 0)
+ printk(KERN_ERR "failed to register cpu pclk\n");
+
+ return 0;
+}
+
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-fb.c
@@ -0,0 +1,72 @@
+/* linux/arch/arm/plat-s3c/dev-fb.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for framebuffer device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+
+#include <plat/fb.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_fb_resource[] = {
+ [0] = {
+ .start = S3C_PA_FB,
+ .end = S3C_PA_FB + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_LCD_VSYNC,
+ .end = IRQ_LCD_VSYNC,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_LCD_FIFO,
+ .end = IRQ_LCD_FIFO,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = IRQ_LCD_SYSTEM,
+ .end = IRQ_LCD_SYSTEM,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_fb = {
+ .name = "s3c-fb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_fb_resource),
+ .resource = s3c_fb_resource,
+ .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
+ .dev.coherent_dma_mask = 0xffffffffUL,
+};
+
+void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
+{
+ struct s3c_fb_platdata *npd;
+
+ if (!pd) {
+ printk(KERN_ERR "%s: no platform data\n", __func__);
+ return;
+ }
+
+ npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+ s3c_device_fb.dev.platform_data = npd;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-hsmmc1.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for hsmmc device 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#define S3C_SZ_HSMMC (0x1000)
+
+static struct resource s3c_hsmmc1_resource[] = {
+ [0] = {
+ .start = S3C_PA_HSMMC1,
+ .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_HSMMC1,
+ .end = IRQ_HSMMC1,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
+
+struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
+ .max_width = 4,
+ .host_caps = (MMC_CAP_4_BIT_DATA |
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+
+struct platform_device s3c_device_hsmmc1 = {
+ .name = "s3c-sdhci",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
+ .resource = s3c_hsmmc1_resource,
+ .dev = {
+ .dma_mask = &s3c_device_hsmmc1_dmamask,
+ .coherent_dma_mask = 0xffffffffUL,
+ .platform_data = &s3c_hsmmc1_def_platdata,
+ },
+};
+
+void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+ struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
+
+ set->max_width = pd->max_width;
+
+ if (pd->cfg_gpio)
+ set->cfg_gpio = pd->cfg_gpio;
+ if (pd->cfg_card)
+ set->cfg_card = pd->cfg_card;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-hsmmc.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for hsmmc devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+#define S3C_SZ_HSMMC (0x1000)
+
+static struct resource s3c_hsmmc_resource[] = {
+ [0] = {
+ .start = S3C_PA_HSMMC0,
+ .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_HSMMC0,
+ .end = IRQ_HSMMC0,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
+
+struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
+ .max_width = 4,
+ .host_caps = (MMC_CAP_4_BIT_DATA |
+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+
+struct platform_device s3c_device_hsmmc0 = {
+ .name = "s3c-sdhci",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
+ .resource = s3c_hsmmc_resource,
+ .dev = {
+ .dma_mask = &s3c_device_hsmmc_dmamask,
+ .coherent_dma_mask = 0xffffffffUL,
+ .platform_data = &s3c_hsmmc0_def_platdata,
+ },
+};
+
+void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+ struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
+
+ set->max_width = pd->max_width;
+
+ if (pd->cfg_gpio)
+ set->cfg_gpio = pd->cfg_gpio;
+ if (pd->cfg_card)
+ set->cfg_card = pd->cfg_card;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-i2c0.c
@@ -0,0 +1,71 @@
+/* linux/arch/arm/plat-s3c/dev-i2c0.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for i2c device 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC,
+ .end = S3C_PA_IIC + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC,
+ .end = IRQ_IIC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c0 = {
+ .name = "s3c2410-i2c",
+#ifdef CONFIG_S3C_DEV_I2C1
+ .id = 0,
+#else
+ .id = -1,
+#endif
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
+ .flags = 0,
+ .slave_addr = 0x10,
+ .bus_freq = 100*1000,
+ .max_freq = 400*1000,
+ .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+};
+
+void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data0;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c0_cfg_gpio;
+
+ s3c_device_i2c0.dev.platform_data = npd;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-i2c1.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-s3c/dev-i2c1.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series device definition for i2c device 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+ [0] = {
+ .start = S3C_PA_IIC1,
+ .end = S3C_PA_IIC1 + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_IIC1,
+ .end = IRQ_IIC1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device s3c_device_i2c1 = {
+ .name = "s3c2410-i2c",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(s3c_i2c_resource),
+ .resource = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
+ .flags = 0,
+ .bus_num = 1,
+ .slave_addr = 0x10,
+ .bus_freq = 100*1000,
+ .max_freq = 400*1000,
+ .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+};
+
+void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+ struct s3c2410_platform_i2c *npd;
+
+ if (!pd)
+ pd = &default_i2c_data1;
+
+ npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+ if (!npd)
+ printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+ else if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c1_cfg_gpio;
+
+ s3c_device_i2c1.dev.platform_data = npd;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/gpio.c
@@ -0,0 +1,156 @@
+/* linux/arch/arm/plat-s3c/gpio.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/gpio-core.h>
+
+#ifdef CONFIG_S3C_GPIO_TRACK
+struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
+
+static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
+{
+ unsigned int gpn;
+ int i;
+
+ gpn = chip->chip.base;
+ for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
+ BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
+ s3c_gpios[gpn] = chip;
+ }
+}
+#endif /* CONFIG_S3C_GPIO_TRACK */
+
+/* Default routines for controlling GPIO, based on the original S3C24XX
+ * GPIO functions which deal with the case where each gpio bank of the
+ * chip is as following:
+ *
+ * base + 0x00: Control register, 2 bits per gpio
+ * gpio n: 2 bits starting at (2*n)
+ * 00 = input, 01 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ * bit n: data bit n
+*/
+
+static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ unsigned long flags;
+ unsigned long con;
+
+ local_irq_save(flags);
+
+ con = __raw_readl(base + 0x00);
+ con &= ~(3 << (offset * 2));
+
+ __raw_writel(con, base + 0x00);
+
+ local_irq_restore(flags);
+ return 0;
+}
+
+static int s3c_gpiolib_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ unsigned long flags;
+ unsigned long dat;
+ unsigned long con;
+
+ local_irq_save(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+ if (value)
+ dat |= 1 << offset;
+ __raw_writel(dat, base + 0x04);
+
+ con = __raw_readl(base + 0x00);
+ con &= ~(3 << (offset * 2));
+ con |= 1 << (offset * 2);
+
+ __raw_writel(con, base + 0x00);
+ __raw_writel(dat, base + 0x04);
+
+ local_irq_restore(flags);
+ return 0;
+}
+
+static void s3c_gpiolib_set(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ unsigned long flags;
+ unsigned long dat;
+
+ local_irq_save(flags);
+
+ dat = __raw_readl(base + 0x04);
+ dat &= ~(1 << offset);
+ if (value)
+ dat |= 1 << offset;
+ __raw_writel(dat, base + 0x04);
+
+ local_irq_restore(flags);
+}
+
+static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ unsigned long val;
+
+ val = __raw_readl(ourchip->base + 0x04);
+ val >>= offset;
+ val &= 1;
+
+ return val;
+}
+
+__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
+{
+ struct gpio_chip *gc = &chip->chip;
+ int ret;
+
+ BUG_ON(!chip->base);
+ BUG_ON(!gc->label);
+ BUG_ON(!gc->ngpio);
+
+ if (!gc->direction_input)
+ gc->direction_input = s3c_gpiolib_input;
+ if (!gc->direction_output)
+ gc->direction_output = s3c_gpiolib_output;
+ if (!gc->set)
+ gc->set = s3c_gpiolib_set;
+ if (!gc->get)
+ gc->get = s3c_gpiolib_get;
+
+#ifdef CONFIG_PM
+ if (chip->pm != NULL) {
+ if (!chip->pm->save || !chip->pm->resume)
+ printk(KERN_ERR "gpio: %s has missing PM functions\n",
+ gc->label);
+ } else
+ printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
+#endif
+
+ /* gpiochip_add() prints own failure message on error. */
+ ret = gpiochip_add(gc);
+ if (ret >= 0)
+ s3c_gpiolib_track(chip);
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/gpio-config.c
@@ -0,0 +1,163 @@
+/* linux/arch/arm/plat-s3c/gpio-config.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO configuration core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
+{
+ struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+ unsigned long flags;
+ int offset;
+ int ret;
+
+ if (!chip)
+ return -EINVAL;
+
+ offset = pin - chip->chip.base;
+
+ local_irq_save(flags);
+ ret = s3c_gpio_do_setcfg(chip, offset, config);
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
+{
+ struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+ unsigned long flags;
+ int offset, ret;
+
+ if (!chip)
+ return -EINVAL;
+
+ offset = pin - chip->chip.base;
+
+ local_irq_save(flags);
+ ret = s3c_gpio_do_setpull(chip, offset, pull);
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
+int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int cfg)
+{
+ void __iomem *reg = chip->base;
+ unsigned int shift = off;
+ u32 con;
+
+ if (s3c_gpio_is_cfg_special(cfg)) {
+ cfg &= 0xf;
+
+ /* Map output to 0, and SFN2 to 1 */
+ cfg -= 1;
+ if (cfg > 1)
+ return -EINVAL;
+
+ cfg <<= shift;
+ }
+
+ con = __raw_readl(reg);
+ con &= ~(0x1 << shift);
+ con |= cfg;
+ __raw_writel(con, reg);
+
+ return 0;
+}
+
+int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int cfg)
+{
+ void __iomem *reg = chip->base;
+ unsigned int shift = off * 2;
+ u32 con;
+
+ if (s3c_gpio_is_cfg_special(cfg)) {
+ cfg &= 0xf;
+ if (cfg > 3)
+ return -EINVAL;
+
+ cfg <<= shift;
+ }
+
+ con = __raw_readl(reg);
+ con &= ~(0x3 << shift);
+ con |= cfg;
+ __raw_writel(con, reg);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
+int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int cfg)
+{
+ void __iomem *reg = chip->base;
+ unsigned int shift = (off & 7) * 4;
+ u32 con;
+
+ if (off < 8 && chip->chip.ngpio >= 8)
+ reg -= 4;
+
+ if (s3c_gpio_is_cfg_special(cfg)) {
+ cfg &= 0xf;
+ cfg <<= shift;
+ }
+
+ con = __raw_readl(reg);
+ con &= ~(0xf << shift);
+ con |= cfg;
+ __raw_writel(con, reg);
+
+ return 0;
+}
+#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
+
+#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
+int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
+ unsigned int off, s3c_gpio_pull_t pull)
+{
+ void __iomem *reg = chip->base + 0x08;
+ int shift = off * 2;
+ u32 pup;
+
+ pup = __raw_readl(reg);
+ pup &= ~(3 << shift);
+ pup |= pull << shift;
+ __raw_writel(pup, reg);
+
+ return 0;
+}
+
+s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
+ unsigned int off)
+{
+ void __iomem *reg = chip->base + 0x08;
+ int shift = off * 2;
+ u32 pup = __raw_readl(reg);
+
+ pup >>= shift;
+ pup &= 0x3;
+ return (__force s3c_gpio_pull_t)pup;
+}
+#endif
--- /dev/null
+++ b/arch/arm/plat-s3c/include/mach/io.h
@@ -0,0 +1,18 @@
+/* arch/arm/plat-s3c/include/mach/io.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben-linux@fluff.org>
+ *
+ * Default IO routines for plat-s3c based systems, such as S3C24A0
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No current ISA/PCI bus support. */
+#define __io(a) ((void __iomem *)(a))
+#define __mem_pci(a) (a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif
--- /dev/null
+++ b/arch/arm/plat-s3c/include/mach/timex.h
@@ -0,0 +1,26 @@
+/* arch/arm/mach-s3c2410/include/mach/timex.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+
+#define CLOCK_TICK_RATE 12000000
+
+
+#endif /* __ASM_ARCH_TIMEX_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/plat-s3c/include/mach/vmalloc.h
+ *
+ * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/clock.h
@@ -0,0 +1,88 @@
+/* linux/arch/arm/plat-s3c/include/plat/clock.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ * http://www.simtec.co.uk/products/SWLINUX/
+ * Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/spinlock.h>
+
+struct clk {
+ struct list_head list;
+ struct module *owner;
+ struct clk *parent;
+ const char *name;
+ int id;
+ int usage;
+ unsigned long rate;
+ unsigned long ctrlbit;
+
+ int (*enable)(struct clk *, int enable);
+ int (*set_rate)(struct clk *c, unsigned long rate);
+ unsigned long (*get_rate)(struct clk *c);
+ unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+ int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+/* other clocks which may be registered by board support */
+
+extern struct clk s3c24xx_dclk0;
+extern struct clk s3c24xx_dclk1;
+extern struct clk s3c24xx_clkout0;
+extern struct clk s3c24xx_clkout1;
+extern struct clk s3c24xx_uclk;
+
+extern struct clk clk_usb_bus;
+
+/* core clock support */
+
+extern struct clk clk_f;
+extern struct clk clk_h;
+extern struct clk clk_p;
+extern struct clk clk_mpll;
+extern struct clk clk_upll;
+extern struct clk clk_epll;
+extern struct clk clk_xtal;
+extern struct clk clk_ext;
+
+/* S3C64XX specific clocks */
+extern struct clk clk_27m;
+extern struct clk clk_48m;
+
+/* exports for arch/arm/mach-s3c2410
+ *
+ * Please DO NOT use these outside of arch/arm/mach-s3c2410
+*/
+
+extern spinlock_t clocks_lock;
+
+extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
+
+extern int s3c24xx_register_clock(struct clk *clk);
+extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
+
+extern int s3c24xx_register_baseclocks(unsigned long xtal);
+
+extern void s3c64xx_register_clocks(void);
+
+extern void s3c24xx_setup_clocks(unsigned long fclk,
+ unsigned long hclk,
+ unsigned long pclk);
+
+extern void s3c2410_setup_clocks(void);
+extern void s3c2412_setup_clocks(void);
+extern void s3c244x_setup_clocks(void);
+extern void s3c2443_setup_clocks(void);
+
+/* S3C64XX specific functions and clocks */
+
+extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
+
+/* Init for pwm clock code */
+
+extern void s3c_pwmclk_init(void);
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h
@@ -0,0 +1,94 @@
+/* arch/arm/plat-s3c/include/plat/cpu-freq.h
+ *
+ * Copyright (c) 2006,2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C CPU frequency scaling support - driver and board
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/cpufreq.h>
+
+struct s3c_cpufreq_info;
+struct s3c_cpufreq_board;
+struct s3c_iotimings;
+
+struct s3c_freq {
+ unsigned long fclk;
+ unsigned long armclk;
+ unsigned long hclk_tns; /* in 10ths of ns */
+ unsigned long hclk;
+ unsigned long pclk;
+};
+
+/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
+ * notification can use this information that is not provided by just
+ * having the core frequency alone.
+ */
+
+struct s3c_cpufreq_freqs {
+ struct cpufreq_freqs freqs;
+ struct s3c_freq old;
+ struct s3c_freq new;
+};
+
+#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
+
+struct s3c_clkdivs {
+ int p_divisor; /* fclk / pclk */
+ int h_divisor; /* fclk / hclk */
+ int arm_divisor; /* not all cpus have this. */
+ unsigned char dvs; /* using dvs mode to arm. */
+};
+
+#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
+
+struct s3c_pllval {
+ unsigned long freq;
+ unsigned long pll_reg;
+};
+
+struct s3c_cpufreq_config {
+ struct s3c_freq freq;
+ struct s3c_pllval pll;
+ struct s3c_clkdivs divs;
+ struct s3c_cpufreq_info *info; /* for core, not drivers */
+ struct s3c_cpufreq_board *board;
+};
+
+/* s3c_cpufreq_board
+ *
+ * per-board configuraton information, such as memory refresh and
+ * how to initialise IO timings.
+ */
+struct s3c_cpufreq_board {
+ unsigned int refresh; /* refresh period in ns */
+ unsigned int auto_io:1; /* automatically init io timings. */
+ unsigned int need_io:1; /* set if needs io timing support. */
+
+ /* any non-zero field in here is taken as an upper limit. */
+ struct s3c_freq max; /* frequency limits */
+};
+
+/* Things depending on frequency scaling. */
+#ifdef CONFIG_CPU_FREQ_S3C
+#define __init_or_cpufreq
+#else
+#define __init_or_cpufreq __init
+#endif
+
+/* Board functions */
+
+#ifdef CONFIG_CPU_FREQ_S3C
+extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
+#else
+
+static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
+{
+ return 0;
+}
+#endif /* CONFIG_CPU_FREQ_S3C */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -0,0 +1,74 @@
+/* linux/arch/arm/plat-s3c/include/plat/cpu.h
+ *
+ * Copyright (c) 2004-2005 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for S3C24XX CPU support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* todo - fix when rmk changes iodescs to use `void __iomem *` */
+
+#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
+
+#ifndef MHZ
+#define MHZ (1000*1000)
+#endif
+
+#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
+
+/* forward declaration */
+struct s3c24xx_uart_resources;
+struct platform_device;
+struct s3c2410_uartcfg;
+struct map_desc;
+
+/* per-cpu initialisation function table. */
+
+struct cpu_table {
+ unsigned long idcode;
+ unsigned long idmask;
+ void (*map_io)(void);
+ void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
+ void (*init_clocks)(int xtal);
+ int (*init)(void);
+ const char *name;
+};
+
+extern void s3c_init_cpu(unsigned long idcode,
+ struct cpu_table *cpus, unsigned int cputab_size);
+
+/* core initialisation functions */
+
+extern void s3c24xx_init_irq(void);
+extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
+
+extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
+extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
+
+extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+
+extern void s3c24xx_init_clocks(int xtal);
+
+extern void s3c24xx_init_uartdevs(char *name,
+ struct s3c24xx_uart_resources *res,
+ struct s3c2410_uartcfg *cfg, int no);
+
+/* timer for 2410/2440 */
+
+struct sys_timer;
+extern struct sys_timer s3c24xx_timer;
+
+/* system device classes */
+
+extern struct sysdev_class s3c2410_sysclass;
+extern struct sysdev_class s3c2412_sysclass;
+extern struct sysdev_class s3c2440_sysclass;
+extern struct sysdev_class s3c2442_sysclass;
+extern struct sysdev_class s3c2443_sysclass;
+extern struct sysdev_class s3c6410_sysclass;
+extern struct sysdev_class s3c64xx_sysclass;
+
--- a/arch/arm/plat-s3c/include/plat/debug-macro.S
+++ b/arch/arm/plat-s3c/include/plat/debug-macro.S
@@ -20,7 +20,7 @@
.endm
#ifndef fifo_level
-#define fifo_level fifo_level_s3c2410
+#define fifo_level fifo_level_s3c2440
#endif
.macro fifo_full_s3c2440 rd, rx
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -0,0 +1,55 @@
+/* linux/include/asm-arm/plat-s3c24xx/devs.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for s3c2410 standard platform devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/platform_device.h>
+
+struct s3c24xx_uart_resources {
+ struct resource *resources;
+ unsigned long nr_resources;
+};
+
+extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
+extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
+
+extern struct platform_device *s3c24xx_uart_devs[];
+extern struct platform_device *s3c24xx_uart_src[];
+
+extern struct platform_device s3c_device_timer[];
+
+extern struct platform_device s3c_device_fb;
+extern struct platform_device s3c_device_usb;
+extern struct platform_device s3c_device_lcd;
+extern struct platform_device s3c_device_wdt;
+extern struct platform_device s3c_device_i2c0;
+extern struct platform_device s3c_device_i2c1;
+extern struct platform_device s3c_device_iis;
+extern struct platform_device s3c_device_rtc;
+extern struct platform_device s3c_device_adc;
+extern struct platform_device s3c_device_sdi;
+extern struct platform_device s3c_device_hsmmc0;
+extern struct platform_device s3c_device_hsmmc1;
+extern struct platform_device s3c_device_hsmmc2;
+
+extern struct platform_device s3c_device_spi0;
+extern struct platform_device s3c_device_spi1;
+
+extern struct platform_device s3c_device_nand;
+
+extern struct platform_device s3c_device_usbgadget;
+
+extern struct platform_device s3c_device_ts;
+
+/* s3c2440 specific devices */
+
+#ifdef CONFIG_CPU_S3C2440
+
+extern struct platform_device s3c_device_camif;
+#endif
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/fb.h
@@ -0,0 +1,73 @@
+/* linux/arch/arm/plat-s3c/include/plat/fb.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - FB platform data definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C_FB_H
+#define __PLAT_S3C_FB_H __FILE__
+
+/**
+ * struct s3c_fb_pd_win - per window setup data
+ * @win_mode: The display parameters to initialise (not for window 0)
+ * @virtual_x: The virtual X size.
+ * @virtual_y: The virtual Y size.
+ */
+struct s3c_fb_pd_win {
+ struct fb_videomode win_mode;
+
+ unsigned short default_bpp;
+ unsigned short max_bpp;
+ unsigned short virtual_x;
+ unsigned short virtual_y;
+};
+
+/**
+ * struct s3c_fb_platdata - S3C driver platform specific information
+ * @setup_gpio: Setup the external GPIO pins to the right state to transfer
+ * the data from the display system to the connected display
+ * device.
+ * @vidcon0: The base vidcon0 values to control the panel data format.
+ * @vidcon1: The base vidcon1 values to control the panel data output.
+ * @win: The setup data for each hardware window, or NULL for unused.
+ * @display_mode: The LCD output display mode.
+ *
+ * The platform data supplies the video driver with all the information
+ * it requires to work with the display(s) attached to the machine. It
+ * controls the initial mode, the number of display windows (0 is always
+ * the base framebuffer) that are initialised etc.
+ *
+ */
+struct s3c_fb_platdata {
+ void (*setup_gpio)(void);
+
+ struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
+
+ u32 vidcon0;
+ u32 vidcon1;
+};
+
+/**
+ * s3c_fb_set_platdata() - Setup the FB device with platform data.
+ * @pd: The platform data to set. The data is copied from the passed structure
+ * so the machine data can mark the data __initdata so that any unused
+ * machines will end up dumping their data at runtime.
+ */
+extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
+
+/**
+ * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s3c64xx_fb_gpio_setup_24bpp(void);
+
+#endif /* __PLAT_S3C_FB_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/gpio-cfg.h
@@ -0,0 +1,110 @@
+/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - GPIO pin configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* This file contains the necessary definitions to get the basic gpio
+ * pin configuration done such as setting a pin to input or output or
+ * changing the pull-{up,down} configurations.
+ */
+
+/* Note, this interface is being added to the s3c64xx arch first and will
+ * be added to the s3c24xx systems later.
+ */
+
+#ifndef __PLAT_GPIO_CFG_H
+#define __PLAT_GPIO_CFG_H __FILE__
+
+typedef unsigned int __bitwise__ s3c_gpio_pull_t;
+
+/* forward declaration if gpio-core.h hasn't been included */
+struct s3c_gpio_chip;
+
+/**
+ * struct s3c_gpio_cfg GPIO configuration
+ * @cfg_eint: Configuration setting when used for external interrupt source
+ * @get_pull: Read the current pull configuration for the GPIO
+ * @set_pull: Set the current pull configuraiton for the GPIO
+ * @set_config: Set the current configuration for the GPIO
+ * @get_config: Read the current configuration for the GPIO
+ *
+ * Each chip can have more than one type of GPIO bank available and some
+ * have different capabilites even when they have the same control register
+ * layouts. Provide an point to vector control routine and provide any
+ * per-bank configuration information that other systems such as the
+ * external interrupt code will need.
+ */
+struct s3c_gpio_cfg {
+ unsigned int cfg_eint;
+
+ s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
+ int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
+ s3c_gpio_pull_t pull);
+
+ unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
+ int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
+ unsigned config);
+};
+
+#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
+#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
+
+/* Defines for generic pin configurations */
+#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
+#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
+#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
+
+#define s3c_gpio_is_cfg_special(_cfg) \
+ (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
+
+/**
+ * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
+ * @pin pin The pin number to configure.
+ * @pin to The configuration for the pin's function.
+ *
+ * Configure which function is actually connected to the external
+ * pin, such as an gpio input, output or some form of special function
+ * connected to an internal peripheral block.
+ */
+extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
+
+/* Define values for the pull-{up,down} available for each gpio pin.
+ *
+ * These values control the state of the weak pull-{up,down} resistors
+ * available on most pins on the S3C series. Not all chips support both
+ * up or down settings, and it may be dependant on the chip that is being
+ * used to whether the particular mode is available.
+ */
+#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
+#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
+#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
+
+/**
+ * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
+ * @pin: The pin number to configure the pull resistor.
+ * @pull: The configuration for the pull resistor.
+ *
+ * This function sets the state of the pull-{up,down} resistor for the
+ * specified pin. It will return 0 if successfull, or a negative error
+ * code if the pin cannot support the requested pull setting.
+*/
+extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
+ * @pin: The pin number to get the settings for
+ *
+ * Read the pull resistor value for the specified pin.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
+
+#endif /* __PLAT_GPIO_CFG_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h
@@ -0,0 +1,176 @@
+/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - GPIO pin configuration helper definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* This is meant for core cpu support, machine or other driver files
+ * should not be including this header.
+ */
+
+#ifndef __PLAT_GPIO_CFG_HELPERS_H
+#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
+
+/* As a note, all gpio configuration functions are entered exclusively, either
+ * with the relevant lock held or the system prevented from doing anything else
+ * by disabling interrupts.
+*/
+
+static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int config)
+{
+ return (chip->config->set_config)(chip, off, config);
+}
+
+static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
+ unsigned int off, s3c_gpio_pull_t pull)
+{
+ return (chip->config->set_pull)(chip, off, pull);
+}
+
+/**
+ * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @cfg: The configuration value to set.
+ *
+ * This helper deal with the GPIO cases where the control register
+ * has two bits of configuration per gpio, which have the following
+ * functions:
+ * 00 = input
+ * 01 = output
+ * 1x = special function
+*/
+extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int cfg);
+
+/**
+ * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @cfg: The configuration value to set.
+ *
+ * This helper deal with the GPIO cases where the control register
+ * has one bit of configuration for the gpio, where setting the bit
+ * means the pin is in special function mode and unset means output.
+*/
+extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int cfg);
+
+/**
+ * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @cfg: The configuration value to set.
+ *
+ * This helper deal with the GPIO cases where the control register has 4 bits
+ * of control per GPIO, generally in the form of:
+ * 0000 = Input
+ * 0001 = Output
+ * others = Special functions (dependant on bank)
+ *
+ * Note, since the code to deal with the case where there are two control
+ * registers instead of one, we do not have a seperate set of functions for
+ * each case.
+*/
+extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
+ unsigned int off, unsigned int cfg);
+
+
+/* Pull-{up,down} resistor controls.
+ *
+ * S3C2410,S3C2440,S3C24A0 = Pull-UP,
+ * S3C2412,S3C2413 = Pull-Down
+ * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
+ * S3C2443 = Pull-Both [not same as S3C6400]
+ */
+
+/**
+ * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @param: pull: The pull mode being requested.
+ *
+ * This is a helper function for the case where we have GPIOs with one
+ * bit configuring the presence of a pull-up resistor.
+ */
+extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+ unsigned int off, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
+ * @chip: The gpio chip that is being configured
+ * @off: The offset for the GPIO being configured
+ * @param: pull: The pull mode being requested
+ *
+ * This is a helper function for the case where we have GPIOs with one
+ * bit configuring the presence of a pull-down resistor.
+ */
+extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
+ unsigned int off, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @param: pull: The pull mode being requested.
+ *
+ * This is a helper function for the case where we have GPIOs with two
+ * bits configuring the presence of a pull resistor, in the following
+ * order:
+ * 00 = No pull resistor connected
+ * 01 = Pull-up resistor connected
+ * 10 = Pull-down resistor connected
+ */
+extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
+ unsigned int off, s3c_gpio_pull_t pull);
+
+
+/**
+ * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
+ * @chip: The gpio chip that the GPIO pin belongs to
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-{up,down} resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_upown.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
+ unsigned int off);
+
+/**
+ * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
+ * @chip: The gpio chip that is being configured.
+ * @off: The offset for the GPIO being configured.
+ * @param: pull: The pull mode being requested.
+ *
+ * This is a helper function for the case where we have GPIOs with two
+ * bits configuring the presence of a pull resistor, in the following
+ * order:
+ * 00 = Pull-up resistor connected
+ * 10 = Pull-down resistor connected
+ * x1 = No pull up resistor
+ */
+extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
+ unsigned int off, s3c_gpio_pull_t pull);
+
+/**
+ * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
+ * @chip: The gpio chip that the GPIO pin belongs to.
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-{up,down} resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_upown.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
+ unsigned int off);
+
+#endif /* __PLAT_GPIO_CFG_HELPERS_H */
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
@@ -0,0 +1,107 @@
+/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - GPIO core
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Define the core gpiolib support functions that the s3c platforms may
+ * need to extend or change depending on the hardware and the s3c chip
+ * selected at build or found at run time.
+ *
+ * These definitions are not intended for driver inclusion, there is
+ * nothing here that should not live outside the platform and core
+ * specific code.
+*/
+
+struct s3c_gpio_chip;
+
+/**
+ * struct s3c_gpio_pm - power management (suspend/resume) information
+ * @save: Routine to save the state of the GPIO block
+ * @resume: Routine to resume the GPIO block.
+ */
+struct s3c_gpio_pm {
+ void (*save)(struct s3c_gpio_chip *chip);
+ void (*resume)(struct s3c_gpio_chip *chip);
+};
+
+struct s3c_gpio_cfg;
+
+/**
+ * struct s3c_gpio_chip - wrapper for specific implementation of gpio
+ * @chip: The chip structure to be exported via gpiolib.
+ * @base: The base pointer to the gpio configuration registers.
+ * @config: special function and pull-resistor control information.
+ * @pm_save: Save information for suspend/resume support.
+ *
+ * This wrapper provides the necessary information for the Samsung
+ * specific gpios being registered with gpiolib.
+ */
+struct s3c_gpio_chip {
+ struct gpio_chip chip;
+ struct s3c_gpio_cfg *config;
+ struct s3c_gpio_pm *pm;
+ void __iomem *base;
+#ifdef CONFIG_PM
+ u32 pm_save[4];
+#endif
+};
+
+static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
+{
+ return container_of(gpc, struct s3c_gpio_chip, chip);
+}
+
+/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
+ * @chip: The chip to register
+ *
+ * This is a wrapper to gpiochip_add() that takes our specific gpio chip
+ * information and makes the necessary alterations for the platform and
+ * notes the information for use with the configuration systems and any
+ * other parts of the system.
+ */
+extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
+
+/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
+ * for use with the configuration calls, and other parts of the s3c gpiolib
+ * support code.
+ *
+ * Not all s3c support code will need this, as some configurations of cpu
+ * may only support one or two different configuration options and have an
+ * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
+ * the machine support file should provide its own s3c_gpiolib_getchip()
+ * and any other necessary functions.
+ */
+
+#ifdef CONFIG_S3C_GPIO_TRACK
+extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
+
+static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
+{
+ return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
+}
+#else
+/* machine specific code should provide s3c_gpiolib_getchip */
+
+static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
+#endif
+
+#ifdef CONFIG_PM
+extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
+extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
+#define __gpio_pm(x) x
+#else
+#define s3c_gpio_pm_1bit NULL
+#define s3c_gpio_pm_2bit NULL
+#define s3c_gpio_pm_4bit NULL
+#define __gpio_pm(x) NULL
+
+#endif /* CONFIG_PM */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/iic-core.h
@@ -0,0 +1,35 @@
+/* arch/arm/mach-s3c2410/include/mach/iic-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - I2C Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IIC_CORE_H
+#define __ASM_ARCH_IIC_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_i2c0_setname(char *name)
+{
+ /* currently this device is always compiled in */
+ s3c_device_i2c0.name = name;
+}
+
+static inline void s3c_i2c1_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_I2C1
+ s3c_device_i2c1.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_IIC_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -0,0 +1,57 @@
+/* arch/arm/mach-s3c2410/include/mach/iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - I2C Controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IIC_H
+#define __ASM_ARCH_IIC_H __FILE__
+
+#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
+
+/* Notes:
+ * 1) All frequencies are expressed in Hz
+ * 2) A value of zero is `do not care`
+*/
+
+struct s3c2410_platform_i2c {
+ int bus_num; /* bus number to use */
+ unsigned int flags;
+ unsigned int slave_addr; /* slave address for controller */
+ unsigned long bus_freq; /* standard bus frequency */
+ unsigned long max_freq; /* max frequency for the bus */
+ unsigned long min_freq; /* min frequency for the bus */
+ unsigned int sda_delay; /* pclks (s3c2440 only) */
+
+ void (*cfg_gpio)(struct platform_device *dev);
+};
+
+/**
+ * s3c_i2c0_set_platdata - set platform data for i2c0 device
+ * @i2c: The platform data to set, or NULL for default data.
+ *
+ * Register the given platform data for use with the i2c0 device. This
+ * call copies the platform data, so the caller can use __initdata for
+ * their copy.
+ *
+ * This call will set cfg_gpio if is null to the default platform
+ * implementation.
+ *
+ * Any user of s3c_device_i2c0 should call this, even if it is with
+ * NULL to ensure that the device is given the default platform data
+ * as the driver will no longer carry defaults.
+ */
+extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
+
+/* defined by architecture to configure gpio */
+extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
+
+#endif /* __ASM_ARCH_IIC_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/map-base.h
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/plat-s3c/map.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - Memory map definitions (virtual addresses)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_H
+#define __ASM_PLAT_MAP_H __FILE__
+
+/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+ * little of the VA space as possible so vmalloc and friends have a
+ * better chance of getting memory.
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ */
+
+#define S3C_ADDR_BASE (0xF4000000)
+
+#ifndef __ASSEMBLY__
+#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#else
+#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
+#endif
+
+#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
+#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
+#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
+#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
+#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
+#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
+
+#endif /* __ASM_PLAT_MAP_H */
--- a/arch/arm/plat-s3c/include/plat/map.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/map.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - Memory map definitions (virtual addresses)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_H
-#define __ASM_PLAT_MAP_H __FILE__
-
-/* Fit all our registers in at 0xF4000000 upwards, trying to use as
- * little of the VA space as possible so vmalloc and friends have a
- * better chance of getting memory.
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- */
-
-#define S3C_ADDR_BASE (0xF4000000)
-
-#ifndef __ASSEMBLY__
-#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
-#else
-#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
-#endif
-
-#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
-#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
-#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */
-#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
-#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
-#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
-
-#endif /* __ASM_PLAT_MAP_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -0,0 +1,56 @@
+/* arch/arm/mach-s3c2410/include/mach/nand.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - NAND device controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* struct s3c2410_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name = name of set (optional)
+ * nr_map = map for low-layer logical to physical chip numbers (option)
+ * partitions = mtd partition list
+*/
+
+#define S3C2410_NAND_BBT 0x0001
+
+struct s3c2410_nand_set {
+ unsigned int disable_ecc : 1;
+
+ int nr_chips;
+ int nr_partitions;
+ unsigned int flags;
+ char *name;
+ int *nr_map;
+ struct mtd_partition *partitions;
+ struct nand_ecclayout *ecc_layout;
+};
+
+struct s3c2410_platform_nand {
+ /* timing information for controller, all times in nanoseconds */
+
+ int tacls; /* time for active CLE/ALE to nWE/nOE */
+ int twrph0; /* active time for nWE/nOE */
+ int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
+
+ unsigned int ignore_unset_ecc : 1;
+
+ int nr_sets;
+ struct s3c2410_nand_set *sets;
+
+ /* force software_ecc at runtime */
+ int software_ecc;
+
+ void (*select_chip)(struct s3c2410_nand_set *,
+ int chip);
+};
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/pm.h
@@ -0,0 +1,184 @@
+/* linux/include/asm-arm/plat-s3c24xx/pm.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Written by Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sysdev.h>
+
+/* s3c_pm_init
+ *
+ * called from board at initialisation time to setup the power
+ * management
+*/
+
+#ifdef CONFIG_PM
+
+extern __init int s3c_pm_init(void);
+
+#else
+
+static inline int s3c_pm_init(void)
+{
+ return 0;
+}
+#endif
+
+/* configuration for the IRQ mask over sleep */
+extern unsigned long s3c_irqwake_intmask;
+extern unsigned long s3c_irqwake_eintmask;
+
+/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
+extern unsigned long s3c_irqwake_intallow;
+extern unsigned long s3c_irqwake_eintallow;
+
+/* per-cpu sleep functions */
+
+extern void (*pm_cpu_prep)(void);
+extern void (*pm_cpu_sleep)(void);
+
+/* Flags for PM Control */
+
+extern unsigned long s3c_pm_flags;
+
+extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
+
+/* from sleep.S */
+
+extern int s3c_cpu_save(unsigned long *saveblk);
+extern void s3c_cpu_resume(void);
+
+extern void s3c2410_cpu_suspend(void);
+
+extern unsigned long s3c_sleep_save_phys;
+
+/* sleep save info */
+
+/**
+ * struct sleep_save - save information for shared peripherals.
+ * @reg: Pointer to the register to save.
+ * @val: Holder for the value saved from reg.
+ *
+ * This describes a list of registers which is used by the pm core and
+ * other subsystem to save and restore register values over suspend.
+ */
+struct sleep_save {
+ void __iomem *reg;
+ unsigned long val;
+};
+
+#define SAVE_ITEM(x) \
+ { .reg = (x) }
+
+/**
+ * struct pm_uart_save - save block for core UART
+ * @ulcon: Save value for S3C2410_ULCON
+ * @ucon: Save value for S3C2410_UCON
+ * @ufcon: Save value for S3C2410_UFCON
+ * @umcon: Save value for S3C2410_UMCON
+ * @ubrdiv: Save value for S3C2410_UBRDIV
+ *
+ * Save block for UART registers to be held over sleep and restored if they
+ * are needed (say by debug).
+*/
+struct pm_uart_save {
+ u32 ulcon;
+ u32 ucon;
+ u32 ufcon;
+ u32 umcon;
+ u32 ubrdiv;
+ u32 udivslot;
+};
+
+/* helper functions to save/restore lists of registers. */
+
+extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
+extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
+
+#ifdef CONFIG_PM
+extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
+extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
+extern int s3c24xx_irq_resume(struct sys_device *dev);
+#else
+#define s3c_irqext_wake NULL
+#define s3c24xx_irq_suspend NULL
+#define s3c24xx_irq_resume NULL
+#endif
+
+/* PM debug functions */
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+/**
+ * s3c_pm_dbg() - low level debug function for use in suspend/resume.
+ * @msg: The message to print.
+ *
+ * This function is used mainly to debug the resume process before the system
+ * can rely on printk/console output. It uses the low-level debugging output
+ * routine printascii() to do its work.
+ */
+extern void s3c_pm_dbg(const char *msg, ...);
+
+#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
+#else
+#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
+#endif
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+/**
+ * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
+ * @set: set bits for the state of the LEDs
+ * @clear: clear bits for the state of the LEDs.
+ */
+extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
+
+#else
+static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
+#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
+
+/* suspend memory checking */
+
+#ifdef CONFIG_S3C2410_PM_CHECK
+extern void s3c_pm_check_prepare(void);
+extern void s3c_pm_check_restore(void);
+extern void s3c_pm_check_cleanup(void);
+extern void s3c_pm_check_store(void);
+#else
+#define s3c_pm_check_prepare() do { } while(0)
+#define s3c_pm_check_restore() do { } while(0)
+#define s3c_pm_check_cleanup() do { } while(0)
+#define s3c_pm_check_store() do { } while(0)
+#endif
+
+/**
+ * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
+ *
+ * Setup all the necessary GPIO pins for waking the system on external
+ * interrupt.
+ */
+extern void s3c_pm_configure_extint(void);
+
+/**
+ * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
+ *
+ * Restore the state of the GPIO pins after sleep, which may involve ensuring
+ * that we do not glitch the state of the pins from that the bootloader's
+ * resume code has done.
+*/
+extern void s3c_pm_restore_gpios(void);
+
+/**
+ * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
+ *
+ * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
+ */
+extern void s3c_pm_save_gpios(void);
+
+extern void s3c_pm_save_core(void);
+extern void s3c_pm_restore_core(void);
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-ac97.h
@@ -0,0 +1,67 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
+ *
+ * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 AC97 Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_AC97_H
+#define __ASM_ARCH_REGS_AC97_H __FILE__
+
+#define S3C_AC97_GLBCTRL (0x00)
+
+#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
+#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
+#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
+#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
+#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
+#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
+#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
+#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
+#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
+#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
+#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
+#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
+#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
+
+#define S3C_AC97_GLBSTAT (0x04)
+
+#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
+#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
+#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
+#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
+#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
+#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
+#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
+#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
+
+#define S3C_AC97_CODEC_CMD (0x08)
+
+#define S3C_AC97_CODEC_CMD_READ (1<<23)
+
+#define S3C_AC97_STAT (0x0c)
+#define S3C_AC97_PCM_ADDR (0x10)
+#define S3C_AC97_PCM_DATA (0x18)
+#define S3C_AC97_MIC_DATA (0x1C)
+
+#endif /* __ASM_ARCH_REGS_AC97_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-fb.h
@@ -0,0 +1,366 @@
+/* arch/arm/plat-s3c/include/plat/regs-fb.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - new-style framebuffer register definitions
+ *
+ * This is the register set for the new style framebuffer interface
+ * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
+ * S3C64XX series such as the S3C6400 and S3C6410.
+ *
+ * The file does not contain the cpu specific items which are based on
+ * whichever architecture is selected, it only contains the core of the
+ * register set. See <mach/regs-fb.h> to get the specifics.
+ *
+ * Note, we changed to using regs-fb.h as it avoids any clashes with
+ * the original regs-lcd.h so out of the way of regs-lcd.h as well as
+ * indicating the newer block is much more than just an LCD interface.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Please do not include this file directly, use <mach/regs-fb.h> to
+ * ensure all the localised SoC support is included as necessary.
+*/
+
+/* VIDCON0 */
+
+#define VIDCON0 (0x00)
+#define VIDCON0_INTERLACE (1 << 29)
+#define VIDCON0_VIDOUT_MASK (0x3 << 26)
+#define VIDCON0_VIDOUT_SHIFT (26)
+#define VIDCON0_VIDOUT_RGB (0x0 << 26)
+#define VIDCON0_VIDOUT_TV (0x1 << 26)
+#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
+#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
+
+#define VIDCON0_L1_DATA_MASK (0x7 << 23)
+#define VIDCON0_L1_DATA_SHIFT (23)
+#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
+#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
+#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
+#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
+#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
+#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
+
+#define VIDCON0_L0_DATA_MASK (0x7 << 20)
+#define VIDCON0_L0_DATA_SHIFT (20)
+#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
+#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
+#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
+#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
+#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
+#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
+
+#define VIDCON0_PNRMODE_MASK (0x3 << 17)
+#define VIDCON0_PNRMODE_SHIFT (17)
+#define VIDCON0_PNRMODE_RGB (0x0 << 17)
+#define VIDCON0_PNRMODE_BGR (0x1 << 17)
+#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
+#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
+
+#define VIDCON0_CLKVALUP (1 << 16)
+#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
+#define VIDCON0_CLKVAL_F_SHIFT (6)
+#define VIDCON0_CLKVAL_F_LIMIT (0xff)
+#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
+#define VIDCON0_VLCKFREE (1 << 5)
+#define VIDCON0_CLKDIR (1 << 4)
+
+#define VIDCON0_CLKSEL_MASK (0x3 << 2)
+#define VIDCON0_CLKSEL_SHIFT (2)
+#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
+#define VIDCON0_CLKSEL_LCD (0x1 << 2)
+#define VIDCON0_CLKSEL_27M (0x3 << 2)
+
+#define VIDCON0_ENVID (1 << 1)
+#define VIDCON0_ENVID_F (1 << 0)
+
+#define VIDCON1 (0x04)
+#define VIDCON1_LINECNT_MASK (0x7ff << 16)
+#define VIDCON1_LINECNT_SHIFT (16)
+#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
+#define VIDCON1_VSTATUS_MASK (0x3 << 13)
+#define VIDCON1_VSTATUS_SHIFT (13)
+#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
+#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
+#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
+#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
+
+#define VIDCON1_INV_VCLK (1 << 7)
+#define VIDCON1_INV_HSYNC (1 << 6)
+#define VIDCON1_INV_VSYNC (1 << 5)
+#define VIDCON1_INV_VDEN (1 << 4)
+
+/* VIDCON2 */
+
+#define VIDCON2 (0x08)
+#define VIDCON2_EN601 (1 << 23)
+#define VIDCON2_TVFMTSEL_SW (1 << 14)
+
+#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
+#define VIDCON2_TVFMTSEL1_SHIFT (12)
+#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
+#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
+#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
+
+#define VIDCON2_ORGYCbCr (1 << 8)
+#define VIDCON2_YUVORDCrCb (1 << 7)
+
+/* VIDTCON0 */
+
+#define VIDTCON0_VBPDE_MASK (0xff << 24)
+#define VIDTCON0_VBPDE_SHIFT (24)
+#define VIDTCON0_VBPDE_LIMIT (0xff)
+#define VIDTCON0_VBPDE(_x) ((_x) << 24)
+
+#define VIDTCON0_VBPD_MASK (0xff << 16)
+#define VIDTCON0_VBPD_SHIFT (16)
+#define VIDTCON0_VBPD_LIMIT (0xff)
+#define VIDTCON0_VBPD(_x) ((_x) << 16)
+
+#define VIDTCON0_VFPD_MASK (0xff << 8)
+#define VIDTCON0_VFPD_SHIFT (8)
+#define VIDTCON0_VFPD_LIMIT (0xff)
+#define VIDTCON0_VFPD(_x) ((_x) << 8)
+
+#define VIDTCON0_VSPW_MASK (0xff << 0)
+#define VIDTCON0_VSPW_SHIFT (0)
+#define VIDTCON0_VSPW_LIMIT (0xff)
+#define VIDTCON0_VSPW(_x) ((_x) << 0)
+
+/* VIDTCON1 */
+
+#define VIDTCON1_VFPDE_MASK (0xff << 24)
+#define VIDTCON1_VFPDE_SHIFT (24)
+#define VIDTCON1_VFPDE_LIMIT (0xff)
+#define VIDTCON1_VFPDE(_x) ((_x) << 24)
+
+#define VIDTCON1_HBPD_MASK (0xff << 16)
+#define VIDTCON1_HBPD_SHIFT (16)
+#define VIDTCON1_HBPD_LIMIT (0xff)
+#define VIDTCON1_HBPD(_x) ((_x) << 16)
+
+#define VIDTCON1_HFPD_MASK (0xff << 8)
+#define VIDTCON1_HFPD_SHIFT (8)
+#define VIDTCON1_HFPD_LIMIT (0xff)
+#define VIDTCON1_HFPD(_x) ((_x) << 8)
+
+#define VIDTCON1_HSPW_MASK (0xff << 0)
+#define VIDTCON1_HSPW_SHIFT (0)
+#define VIDTCON1_HSPW_LIMIT (0xff)
+#define VIDTCON1_HSPW(_x) ((_x) << 0)
+
+#define VIDTCON2 (0x18)
+#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
+#define VIDTCON2_LINEVAL_SHIFT (11)
+#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
+#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
+
+#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
+#define VIDTCON2_HOZVAL_SHIFT (0)
+#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
+#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
+
+/* WINCONx */
+
+
+#define WINCONx_BITSWP (1 << 18)
+#define WINCONx_BYTSWP (1 << 17)
+#define WINCONx_HAWSWP (1 << 16)
+#define WINCONx_BURSTLEN_MASK (0x3 << 9)
+#define WINCONx_BURSTLEN_SHIFT (9)
+#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
+#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
+#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
+
+#define WINCONx_ENWIN (1 << 0)
+#define WINCON0_BPPMODE_MASK (0xf << 2)
+#define WINCON0_BPPMODE_SHIFT (2)
+#define WINCON0_BPPMODE_1BPP (0x0 << 2)
+#define WINCON0_BPPMODE_2BPP (0x1 << 2)
+#define WINCON0_BPPMODE_4BPP (0x2 << 2)
+#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
+#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
+#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
+
+#define WINCON1_BLD_PIX (1 << 6)
+
+#define WINCON1_ALPHA_SEL (1 << 1)
+#define WINCON1_BPPMODE_MASK (0xf << 2)
+#define WINCON1_BPPMODE_SHIFT (2)
+#define WINCON1_BPPMODE_1BPP (0x0 << 2)
+#define WINCON1_BPPMODE_2BPP (0x1 << 2)
+#define WINCON1_BPPMODE_4BPP (0x2 << 2)
+#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
+#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
+#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
+#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
+#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
+#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
+#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
+#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
+#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
+#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
+#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
+#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
+
+
+#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
+#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
+#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
+#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
+
+#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
+#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
+#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
+#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
+
+#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
+#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
+#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
+#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
+
+#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
+#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
+#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
+#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
+
+/* For VIDOSD[1..4]C */
+#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
+#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
+#define VIDISD14C_ALPHA0_G_SHIFT (16)
+#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
+#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
+#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
+#define VIDISD14C_ALPHA0_B_SHIFT (12)
+#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
+#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
+#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
+#define VIDISD14C_ALPHA1_R_SHIFT (8)
+#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
+#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
+#define VIDISD14C_ALPHA1_G_SHIFT (4)
+#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
+#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
+#define VIDISD14C_ALPHA1_B_SHIFT (0)
+#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
+#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
+
+/* Video buffer addresses */
+#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
+#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
+#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
+#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
+#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
+
+#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
+#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
+#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
+#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
+
+#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
+#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
+#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
+
+/* Interrupt controls and status */
+
+#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
+#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
+#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
+#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
+
+#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
+#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
+#define VIDINTCON0_INT_I80IFDONE (1 << 17)
+
+#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
+#define VIDINTCON0_FRAMESEL0_SHIFT (15)
+#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
+#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
+#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
+#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
+
+#define VIDINTCON0_FRAMESEL1 (1 << 14)
+#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
+#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
+#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
+#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
+
+#define VIDINTCON0_INT_FRAME (1 << 12)
+#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
+#define VIDINTCON0_FIFIOSEL_SHIFT (5)
+#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
+
+#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
+#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
+#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
+#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
+#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
+#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
+
+#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
+#define VIDINTCON0_INT_FIFO_SHIFT (0)
+#define VIDINTCON0_INT_ENABLE (1 << 0)
+
+#define VIDINTCON1 (0x134)
+#define VIDINTCON1_INT_I180 (1 << 2)
+#define VIDINTCON1_INT_FRAME (1 << 1)
+#define VIDINTCON1_INT_FIFO (1 << 0)
+
+/* Window colour-key control registers */
+
+#define WxKEYCON0_KEYBL_EN (1 << 26)
+#define WxKEYCON0_KEYEN_F (1 << 25)
+#define WxKEYCON0_DIRCON (1 << 24)
+#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
+#define WxKEYCON0_COMPKEY_SHIFT (0)
+#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
+#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
+#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
+#define WxKEYCON1_COLVAL_SHIFT (0)
+#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
+#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
+
+
+/* Window blanking (MAP) */
+
+#define WINxMAP_MAP (1 << 24)
+#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
+#define WINxMAP_MAP_COLOUR_SHIFT (0)
+#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
+#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
+
+#define WPALCON_PAL_UPDATE (1 << 9)
+#define WPALCON_W1PAL_MASK (0x7 << 3)
+#define WPALCON_W1PAL_SHIFT (3)
+#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
+#define WPALCON_W1PAL_24BPP (0x1 << 3)
+#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
+#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
+#define WPALCON_W1PAL_18BPP (0x4 << 3)
+#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
+#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
+
+#define WPALCON_W0PAL_MASK (0x7 << 0)
+#define WPALCON_W0PAL_SHIFT (0)
+#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
+#define WPALCON_W0PAL_24BPP (0x1 << 0)
+#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
+#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
+#define WPALCON_W0PAL_18BPP (0x4 << 0)
+#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
+#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-iic.h
@@ -0,0 +1,56 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 I2C Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_IIC_H
+#define __ASM_ARCH_REGS_IIC_H __FILE__
+
+/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
+#define S3C2410_IICREG(x) (x)
+
+#define S3C2410_IICCON S3C2410_IICREG(0x00)
+#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
+#define S3C2410_IICADD S3C2410_IICREG(0x08)
+#define S3C2410_IICDS S3C2410_IICREG(0x0C)
+#define S3C2440_IICLC S3C2410_IICREG(0x10)
+
+#define S3C2410_IICCON_ACKEN (1<<7)
+#define S3C2410_IICCON_TXDIV_16 (0<<6)
+#define S3C2410_IICCON_TXDIV_512 (1<<6)
+#define S3C2410_IICCON_IRQEN (1<<5)
+#define S3C2410_IICCON_IRQPEND (1<<4)
+#define S3C2410_IICCON_SCALE(x) ((x)&15)
+#define S3C2410_IICCON_SCALEMASK (0xf)
+
+#define S3C2410_IICSTAT_MASTER_RX (2<<6)
+#define S3C2410_IICSTAT_MASTER_TX (3<<6)
+#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
+#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
+#define S3C2410_IICSTAT_MODEMASK (3<<6)
+
+#define S3C2410_IICSTAT_START (1<<5)
+#define S3C2410_IICSTAT_BUSBUSY (1<<5)
+#define S3C2410_IICSTAT_TXRXEN (1<<4)
+#define S3C2410_IICSTAT_ARBITR (1<<3)
+#define S3C2410_IICSTAT_ASSLAVE (1<<2)
+#define S3C2410_IICSTAT_ADDR0 (1<<1)
+#define S3C2410_IICSTAT_LASTBIT (1<<0)
+
+#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
+#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
+#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
+#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
+#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
+
+#define S3C2410_IICLC_FILTER_ON (1<<2)
+
+#endif /* __ASM_ARCH_REGS_IIC_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-irqtype.h
@@ -0,0 +1,21 @@
+/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C - IRQ detection types.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
+ * the S3C64XX
+*/
+#define S3C2410_EXTINT_LOWLEV (0x00)
+#define S3C2410_EXTINT_HILEV (0x01)
+#define S3C2410_EXTINT_FALLEDGE (0x02)
+#define S3C2410_EXTINT_RISEEDGE (0x04)
+#define S3C2410_EXTINT_BOTHEDGE (0x06)
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-nand.h
@@ -0,0 +1,123 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
+ *
+ * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 NAND register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_NAND
+#define __ASM_ARM_REGS_NAND
+
+
+#define S3C2410_NFREG(x) (x)
+
+#define S3C2410_NFCONF S3C2410_NFREG(0x00)
+#define S3C2410_NFCMD S3C2410_NFREG(0x04)
+#define S3C2410_NFADDR S3C2410_NFREG(0x08)
+#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
+#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
+#define S3C2410_NFECC S3C2410_NFREG(0x14)
+
+#define S3C2440_NFCONT S3C2410_NFREG(0x04)
+#define S3C2440_NFCMD S3C2410_NFREG(0x08)
+#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
+#define S3C2440_NFDATA S3C2410_NFREG(0x10)
+#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
+#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
+#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
+#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
+#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
+#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
+#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
+#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
+#define S3C2440_NFSECC S3C2410_NFREG(0x34)
+#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
+#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
+
+#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
+#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
+#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
+#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
+#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
+#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
+#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
+#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
+
+#define S3C2410_NFCONF_EN (1<<15)
+#define S3C2410_NFCONF_512BYTE (1<<14)
+#define S3C2410_NFCONF_4STEP (1<<13)
+#define S3C2410_NFCONF_INITECC (1<<12)
+#define S3C2410_NFCONF_nFCE (1<<11)
+#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
+
+#define S3C2410_NFSTAT_BUSY (1<<0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
+#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
+#define S3C2440_NFCONF_ADVFLASH (1<<3)
+#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
+#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
+#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
+
+#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
+#define S3C2440_NFCONT_SOFTLOCK (1<<12)
+#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
+#define S3C2440_NFCONT_RNBINT_EN (1<<9)
+#define S3C2440_NFCONT_RN_FALLING (1<<8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
+#define S3C2440_NFCONT_INITECC (1<<4)
+#define S3C2440_NFCONT_nFCE (1<<1)
+#define S3C2440_NFCONT_ENABLE (1<<0)
+
+#define S3C2440_NFSTAT_READY (1<<0)
+#define S3C2440_NFSTAT_nCE (1<<1)
+#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
+
+#define S3C2412_NFCONF_NANDBOOT (1<<31)
+#define S3C2412_NFCONF_ECCCLKCON (1<<30)
+#define S3C2412_NFCONF_ECC_MLC (1<<24)
+#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
+#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
+#define S3C2412_NFCONT_SOFTLOCK (1<<16)
+#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
+#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
+#define S3C2412_NFCONT_nFCE1 (1<<2)
+#define S3C2412_NFCONT_nFCE0 (1<<1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
+#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
+#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
+#define S3C2412_NFSTAT_nFCE1 (1<<3)
+#define S3C2412_NFSTAT_nFCE0 (1<<2)
+#define S3C2412_NFSTAT_Res1 (1<<1)
+#define S3C2412_NFSTAT_READY (1<<0)
+
+#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
+#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
+#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
+#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
+#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_NONE (0)
+#define S3C2412_NFECCERR_1BIT (1)
+#define S3C2412_NFECCERR_MULTIBIT (2)
+#define S3C2412_NFECCERR_ECCAREA (3)
+
+
+
+#endif /* __ASM_ARM_REGS_NAND */
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-rtc.h
@@ -0,0 +1,61 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Internal RTC register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_RTC_H
+#define __ASM_ARCH_REGS_RTC_H __FILE__
+
+#define S3C2410_RTCREG(x) (x)
+
+#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN (1<<0)
+#define S3C2410_RTCCON_CLKSEL (1<<1)
+#define S3C2410_RTCCON_CNTSEL (1<<2)
+#define S3C2410_RTCCON_CLKRST (1<<3)
+
+#define S3C2410_TICNT S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE (1<<7)
+
+#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN (1<<6)
+#define S3C2410_RTCALM_YEAREN (1<<5)
+#define S3C2410_RTCALM_MONEN (1<<4)
+#define S3C2410_RTCALM_DAYEN (1<<3)
+#define S3C2410_RTCALM_HOUREN (1<<2)
+#define S3C2410_RTCALM_MINEN (1<<1)
+#define S3C2410_RTCALM_SECEN (1<<0)
+
+#define S3C2410_RTCALM_ALL \
+ S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
+ S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
+ S3C2410_RTCALM_SECEN
+
+
+#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
+
+#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
+
+#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
+
+#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
+#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
+
+
+#endif /* __ASM_ARCH_REGS_RTC_H */
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-sdhci.h
@@ -0,0 +1,87 @@
+/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - SDHCI (HSMMC) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C_SDHCI_REGS_H
+#define __PLAT_S3C_SDHCI_REGS_H __FILE__
+
+#define S3C_SDHCI_CONTROL2 (0x80)
+#define S3C_SDHCI_CONTROL3 (0x84)
+#define S3C64XX_SDHCI_CONTROL4 (0x8C)
+
+#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
+#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
+#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
+#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
+
+#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
+#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
+#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
+
+#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
+#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
+#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
+
+#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
+#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
+#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
+#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
+#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
+
+#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
+#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
+#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
+
+#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
+#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
+#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
+#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
+#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
+#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
+#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
+#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
+
+#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
+#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
+#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
+#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
+
+#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
+#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
+#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
+
+#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
+#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
+#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
+
+#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
+#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
+#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
+
+#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
+#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
+#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
+
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
+#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
+
+#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
+
+#endif /* __PLAT_S3C_SDHCI_REGS_H */
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -77,6 +77,12 @@
#define S3C2440_UCON_FCLK (3<<10)
#define S3C2443_UCON_EPLL (3<<10)
+#define S3C6400_UCON_CLKMASK (3<<10)
+#define S3C6400_UCON_PCLK (0<<10)
+#define S3C6400_UCON_PCLK2 (2<<10)
+#define S3C6400_UCON_UCLK0 (1<<10)
+#define S3C6400_UCON_UCLK1 (3<<10)
+
#define S3C2440_UCON2_FCLK_EN (1<<15)
#define S3C2440_UCON0_DIVMASK (15 << 12)
#define S3C2440_UCON1_DIVMASK (15 << 12)
@@ -149,6 +155,14 @@
#define S3C2410_UFSTAT_RXMASK (15<<0)
#define S3C2410_UFSTAT_RXSHIFT (0)
+/* UFSTAT S3C24A0 */
+#define S3C24A0_UFSTAT_TXFULL (1 << 14)
+#define S3C24A0_UFSTAT_RXFULL (1 << 6)
+#define S3C24A0_UFSTAT_TXMASK (63 << 8)
+#define S3C24A0_UFSTAT_TXSHIFT (8)
+#define S3C24A0_UFSTAT_RXMASK (63)
+#define S3C24A0_UFSTAT_RXSHIFT (0)
+
/* UFSTAT S3C2443 same as S3C2440 */
#define S3C2440_UFSTAT_TXFULL (1<<14)
#define S3C2440_UFSTAT_RXFULL (1<<6)
@@ -175,6 +189,11 @@
#define S3C2443_DIVSLOT (0x2C)
+/* S3C64XX interrupt registers. */
+#define S3C64XX_UINTP 0x30
+#define S3C64XX_UINTSP 0x34
+#define S3C64XX_UINTM 0x38
+
#ifndef __ASSEMBLY__
/* struct s3c24xx_uart_clksrc
@@ -224,7 +243,7 @@
* or platform_add_device() before the console_initcall()
*/
-extern struct platform_device *s3c24xx_uart_devs[3];
+extern struct platform_device *s3c24xx_uart_devs[4];
#endif /* __ASSEMBLY__ */
--- a/arch/arm/plat-s3c/include/plat/regs-timer.h
+++ b/arch/arm/plat-s3c/include/plat/regs-timer.h
@@ -10,7 +10,6 @@
* S3C2410 Timer configuration
*/
-
#ifndef __ASM_ARCH_REGS_TIMER_H
#define __ASM_ARCH_REGS_TIMER_H
@@ -21,6 +20,8 @@
#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
#define S3C2410_TCON S3C_TIMERREG(0x08)
+#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44)
+
#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
@@ -72,6 +73,14 @@
#define S3C2410_TCFG1_MUX_TCLK (4<<0)
#define S3C2410_TCFG1_MUX_MASK (15<<0)
+#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
+#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
+#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
+#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
+#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
+#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
+#define S3C64XX_TCFG1_MUX_MASK (15<<0)
+
#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
/* for each timer, we have an count buffer, an compare buffer and
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ * http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Watchdog timer control
+*/
+
+
+#ifndef __ASM_ARCH_REGS_WATCHDOG_H
+#define __ASM_ARCH_REGS_WATCHDOG_H
+
+#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
+
+#define S3C2410_WTCON S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT S3C_WDOGREG(0x08)
+
+/* the watchdog can either generate a reset pulse, or an
+ * interrupt.
+ */
+
+#define S3C2410_WTCON_RSTEN (0x01)
+#define S3C2410_WTCON_INTEN (1<<2)
+#define S3C2410_WTCON_ENABLE (1<<5)
+
+#define S3C2410_WTCON_DIV16 (0<<3)
+#define S3C2410_WTCON_DIV32 (1<<3)
+#define S3C2410_WTCON_DIV64 (2<<3)
+#define S3C2410_WTCON_DIV128 (3<<3)
+
+#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
+#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
+
+#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
+
+
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -0,0 +1,112 @@
+/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Platform - SDHCI (HSMMC) platform data definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C_SDHCI_H
+#define __PLAT_S3C_SDHCI_H __FILE__
+
+struct platform_device;
+struct mmc_host;
+struct mmc_card;
+struct mmc_ios;
+
+/**
+ * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
+ * @max_width: The maximum number of data bits supported.
+ * @host_caps: Standard MMC host capabilities bit field.
+ * @cfg_gpio: Configure the GPIO for a specific card bit-width
+ * @cfg_card: Configure the interface for a specific card and speed. This
+ * is necessary the controllers and/or GPIO blocks require the
+ * changing of driver-strength and other controls dependant on
+ * the card and speed of operation.
+ * sdhci_host: Pointer kept during init, allows presence change notification
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio or
+ * card speed information.
+*/
+struct s3c_sdhci_platdata {
+ unsigned int max_width;
+ unsigned int host_caps;
+
+ char **clocks; /* set of clock sources */
+
+ void (*cfg_gpio)(struct platform_device *dev, int width);
+ void (*cfg_card)(struct platform_device *dev,
+ void __iomem *regbase,
+ struct mmc_ios *ios,
+ struct mmc_card *card);
+ struct sdhci_host * sdhci_host;
+};
+
+extern void sdhci_s3c_force_presence_change(struct platform_device *pdev);
+
+/**
+ * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
+ * @pd: Platform data to register to device.
+ *
+ * Register the given platform data for use withe S3C SDHCI device.
+ * The call will copy the platform data, so the board definitions can
+ * make the structure itself __initdata.
+ */
+extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
+extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
+
+/* Default platform data, exported so that per-cpu initialisation can
+ * set the correct one when there are more than one cpu type selected.
+*/
+
+extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
+extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
+
+/* Helper function availablity */
+
+#ifdef CONFIG_S3C6410_SETUP_SDHCI
+extern char *s3c6410_hsmmc_clksrcs[4];
+
+extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+
+extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
+ void __iomem *r,
+ struct mmc_ios *ios,
+ struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s3c6410_default_sdhci0(void)
+{
+ s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
+ s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
+ s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s3c6410_default_sdhci1(void)
+{
+ s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
+ s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
+ s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#else
+static inline void s3c6410_default_sdhci0(void) { }
+static inline void s3c6410_default_sdhci1(void) { }
+#endif /* CONFIG_S3C6410_SETUP_SDHCI */
+
+#endif /* __PLAT_S3C_SDHCI_H */
--- a/arch/arm/plat-s3c/include/plat/uncompress.h
+++ b/arch/arm/plat-s3c/include/plat/uncompress.h
@@ -28,7 +28,7 @@
/* defines for UART registers */
#include <plat/regs-serial.h>
-#include <asm/plat-s3c/regs-watchdog.h>
+#include <plat/regs-watchdog.h>
/* working in physical space... */
#undef S3C2410_WDOGREG
@@ -37,7 +37,7 @@
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
+#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
static __inline__ void
uart_wr(unsigned int reg, unsigned int val)
@@ -139,6 +139,28 @@
static void error(char *err);
+#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
+static inline void arch_enable_uart_fifo(void)
+{
+ u32 fifocon = uart_rd(S3C2410_UFCON);
+
+ if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
+ fifocon |= S3C2410_UFCON_RESETBOTH;
+ uart_wr(S3C2410_UFCON, fifocon);
+
+ /* wait for fifo reset to complete */
+ while (1) {
+ fifocon = uart_rd(S3C2410_UFCON);
+ if (!(fifocon & S3C2410_UFCON_RESETBOTH))
+ break;
+ }
+ }
+}
+#else
+#define arch_enable_uart_fifo() do { } while(0)
+#endif
+
+
static void
arch_decomp_setup(void)
{
@@ -149,6 +171,12 @@
arch_detect_cpu();
arch_decomp_wdog_start();
+
+ /* Enable the UART FIFOs if they where not enabled and our
+ * configuration says we should turn them on.
+ */
+
+ arch_enable_uart_fifo();
}
--- /dev/null
+++ b/arch/arm/plat-s3c/init.c
@@ -0,0 +1,161 @@
+/* linux/arch/arm/plat-s3c/init.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series CPU initialisation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+#include <plat/regs-serial.h>
+
+static struct cpu_table *cpu;
+
+static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
+ struct cpu_table *tab,
+ unsigned int count)
+{
+ for (; count != 0; count--, tab++) {
+ if ((idcode & tab->idmask) == tab->idcode)
+ return tab;
+ }
+
+ return NULL;
+}
+
+void __init s3c_init_cpu(unsigned long idcode,
+ struct cpu_table *cputab, unsigned int cputab_size)
+{
+ cpu = s3c_lookup_cpu(idcode, cputab, cputab_size);
+
+ if (cpu == NULL) {
+ printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
+ panic("Unknown S3C24XX CPU");
+ }
+
+ printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
+
+ if (cpu->map_io == NULL || cpu->init == NULL) {
+ printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
+ panic("Unsupported Samsung CPU");
+ }
+
+ cpu->map_io();
+}
+
+/* s3c24xx_init_clocks
+ *
+ * Initialise the clock subsystem and associated information from the
+ * given master crystal value.
+ *
+ * xtal = 0 -> use default PLL crystal value (normally 12MHz)
+ * != 0 -> PLL crystal value in Hz
+*/
+
+void __init s3c24xx_init_clocks(int xtal)
+{
+ if (xtal == 0)
+ xtal = 12*1000*1000;
+
+ if (cpu == NULL)
+ panic("s3c24xx_init_clocks: no cpu setup?\n");
+
+ if (cpu->init_clocks == NULL)
+ panic("s3c24xx_init_clocks: cpu has no clock init\n");
+ else
+ (cpu->init_clocks)(xtal);
+}
+
+/* uart management */
+
+static int nr_uarts __initdata = 0;
+
+static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+/* s3c24xx_init_uartdevs
+ *
+ * copy the specified platform data and configuration into our central
+ * set of devices, before the data is thrown away after the init process.
+ *
+ * This also fills in the array passed to the serial driver for the
+ * early initialisation of the console.
+*/
+
+void __init s3c24xx_init_uartdevs(char *name,
+ struct s3c24xx_uart_resources *res,
+ struct s3c2410_uartcfg *cfg, int no)
+{
+ struct platform_device *platdev;
+ struct s3c2410_uartcfg *cfgptr = uart_cfgs;
+ struct s3c24xx_uart_resources *resp;
+ int uart;
+
+ memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
+
+ for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
+ platdev = s3c24xx_uart_src[cfgptr->hwport];
+
+ resp = res + cfgptr->hwport;
+
+ s3c24xx_uart_devs[uart] = platdev;
+
+ platdev->name = name;
+ platdev->resource = resp->resources;
+ platdev->num_resources = resp->nr_resources;
+
+ platdev->dev.platform_data = cfgptr;
+ }
+
+ nr_uarts = no;
+}
+
+void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+ if (cpu == NULL)
+ return;
+
+ if (cpu->init_uarts == NULL) {
+ printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
+ } else
+ (cpu->init_uarts)(cfg, no);
+}
+
+static int __init s3c_arch_init(void)
+{
+ int ret;
+
+ // do the correct init for cpu
+
+ if (cpu == NULL)
+ panic("s3c_arch_init: NULL cpu\n");
+
+ ret = (cpu->init)();
+ if (ret != 0)
+ return ret;
+
+ ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
+ return ret;
+}
+
+arch_initcall(s3c_arch_init);
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -6,8 +6,8 @@
config PLAT_S3C
bool
- depends on ARCH_S3C2410
- default y if ARCH_S3C2410
+ depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
+ default y
select NO_IOPORT
help
Base platform code for any Samsung S3C device
@@ -16,24 +16,24 @@
config CPU_LLSERIAL_S3C2410_ONLY
bool
- depends on ARCH_S3C2410
+ depends on PLAT_S3C
default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
config CPU_LLSERIAL_S3C2440_ONLY
bool
- depends on ARCH_S3C2410
+ depends on PLAT_S3C
default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
config CPU_LLSERIAL_S3C2410
bool
- depends on ARCH_S3C2410
+ depends on PLAT_S3C
help
Selected if there is an S3C2410 (or register compatible) serial
low-level implementation needed
config CPU_LLSERIAL_S3C2440
bool
- depends on ARCH_S3C2410
+ depends on PLAT_S3C
help
Selected if there is an S3C2440 (or register compatible) serial
low-level implementation needed
@@ -57,6 +57,14 @@
Say y here to use the watchdog to reset the system if the
kernel decompressor detects an error during decompression.
+config S3C_BOOT_UART_FORCE_FIFO
+ bool "Force UART FIFO on during boot process"
+ depends on PLAT_S3C
+ default y
+ help
+ Say Y here to force the UART FIFOs on during the kernel
+ uncompressor
+
comment "Power management"
config S3C2410_PM_DEBUG
@@ -67,6 +75,15 @@
Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
for more information.
+config S3C_PM_DEBUG_LED_SMDK
+ bool "SMDK LED suspend/resume debugging"
+ depends on PM && (MACH_SMDK6410)
+ help
+ Say Y here to enable the use of the SMDK LEDs on the baseboard
+ for debugging of the state of the suspend and resume process.
+
+ Note, this currently only works for S3C64XX based SMDK boards.
+
config S3C2410_PM_CHECK
bool "S3C2410 PM Suspend Memory CRC"
depends on PLAT_S3C && PM && CRC32
@@ -102,3 +119,73 @@
such as the `Uncompressing...` at start time. The value of
this configuration should be between zero and two. The port
must have been initialised by the boot-loader before use.
+
+# options for gpiolib support
+
+config S3C_GPIO_SPACE
+ int "Space between gpio banks"
+ default 0
+ help
+ Add a number of spare GPIO entries between each bank for debugging
+ purposes. This allows any problems where an counter overflows from
+ one bank to another to be caught, at the expense of using a little
+ more memory.
+
+config S3C_GPIO_TRACK
+ bool
+ help
+ Internal configuration option to enable the s3c specific gpio
+ chip tracking if the platform requires it.
+
+config S3C_GPIO_PULL_UPDOWN
+ bool
+ help
+ Internal configuration to enable the correct GPIO pull helper
+
+config S3C_GPIO_PULL_DOWN
+ bool
+ help
+ Internal configuration to enable the correct GPIO pull helper
+
+config S3C_GPIO_PULL_UP
+ bool
+ help
+ Internal configuration to enable the correct GPIO pull helper
+
+config S3C_GPIO_CFG_S3C24XX
+ bool
+ help
+ Internal configuration to enable S3C24XX style GPIO configuration
+ functions.
+
+config S3C_GPIO_CFG_S3C64XX
+ bool
+ help
+ Internal configuration to enable S3C64XX style GPIO configuration
+ functions.
+
+# device definitions to compile in
+
+config S3C_DEV_HSMMC
+ bool
+ depends on PLAT_S3C
+ help
+ Compile in platform device definitions for HSMMC code
+
+config S3C_DEV_HSMMC1
+ bool
+ depends on PLAT_S3C
+ help
+ Compile in platform device definitions for HSMMC channel 1
+
+config S3C_DEV_I2C1
+ bool
+ depends on PLAT_S3C
+ help
+ Compile in platform device definitions for I2C channel 1
+
+config S3C_DEV_FB
+ bool
+ depends on PLAT_S3C
+ help
+ Compile in platform device definition for framebuffer
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -1,3 +1,33 @@
-# dummy makefile, currently just including asm/arm/plat-s3c/include/plat
+# arch/arm/plat-s3c/Makefile
+#
+# Copyright 2008 Simtec Electronics
+#
+# Licensed under GPLv2
-obj-n := dummy.o
+obj-y :=
+obj-m :=
+obj-n :=
+obj- :=
+
+# Core support for all Samsung SoCs
+
+obj-y += init.o
+obj-y += time.o
+obj-y += clock.o
+obj-y += pwm-clock.o
+obj-y += gpio.o
+obj-y += gpio-config.o
+
+# PM support
+
+obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_PM) += pm-gpio.o
+obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o
+
+# devices
+
+obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
+obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
+obj-y += dev-i2c0.o
+obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
+obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
--- /dev/null
+++ b/arch/arm/plat-s3c/pm.c
@@ -0,0 +1,387 @@
+/* linux/arch/arm/plat-s3c/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2004,2006,2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C common power management (suspend to ram) support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+#include <linux/regulator/machine.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-irq.h>
+#include <asm/irq.h>
+
+#include <plat/pm.h>
+#include <plat/pm-core.h>
+
+/* for external use */
+
+unsigned long s3c_pm_flags;
+
+/* Debug code:
+ *
+ * This code supports debug output to the low level UARTs for use on
+ * resume before the console layer is available.
+*/
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+extern void printascii(const char *);
+
+void s3c_pm_dbg(const char *fmt, ...)
+{
+ va_list va;
+ char buff[256];
+
+ va_start(va, fmt);
+ vsprintf(buff, fmt, va);
+ va_end(va);
+
+ printascii(buff);
+}
+
+static inline void s3c_pm_debug_init(void)
+{
+ /* restart uart clocks so we can use them to output */
+ s3c_pm_debug_init_uart();
+}
+
+#else
+#define s3c_pm_debug_init() do { } while(0)
+
+#endif /* CONFIG_S3C2410_PM_DEBUG */
+
+/* Save the UART configurations if we are configured for debug. */
+
+unsigned char pm_uart_udivslot;
+
+#ifdef CONFIG_S3C2410_PM_DEBUG
+
+struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
+{
+ void __iomem *regs = S3C_VA_UARTx(uart);
+
+ save->ulcon = __raw_readl(regs + S3C2410_ULCON);
+ save->ucon = __raw_readl(regs + S3C2410_UCON);
+ save->ufcon = __raw_readl(regs + S3C2410_UFCON);
+ save->umcon = __raw_readl(regs + S3C2410_UMCON);
+ save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+
+ if (pm_uart_udivslot)
+ save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+
+ S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
+ uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
+}
+
+static void s3c_pm_save_uarts(void)
+{
+ struct pm_uart_save *save = uart_save;
+ unsigned int uart;
+
+ for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+ s3c_pm_save_uart(uart, save);
+}
+
+static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save)
+{
+ void __iomem *regs = S3C_VA_UARTx(uart);
+
+ s3c_pm_arch_update_uart(regs, save);
+
+ __raw_writel(save->ulcon, regs + S3C2410_ULCON);
+ __raw_writel(save->ucon, regs + S3C2410_UCON);
+ __raw_writel(save->ufcon, regs + S3C2410_UFCON);
+ __raw_writel(save->umcon, regs + S3C2410_UMCON);
+ __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+
+ if (pm_uart_udivslot)
+ __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+}
+
+static void s3c_pm_restore_uarts(void)
+{
+ struct pm_uart_save *save = uart_save;
+ unsigned int uart;
+
+ for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++)
+ s3c_pm_restore_uart(uart, save);
+}
+#else
+static void s3c_pm_save_uarts(void) { }
+static void s3c_pm_restore_uarts(void) { }
+#endif
+
+/* The IRQ ext-int code goes here, it is too small to currently bother
+ * with its own file. */
+
+unsigned long s3c_irqwake_intmask = 0xffffffffL;
+unsigned long s3c_irqwake_eintmask = 0xffffffffL;
+
+int s3c_irqext_wake(unsigned int irqno, unsigned int state)
+{
+ unsigned long bit = 1L << IRQ_EINT_BIT(irqno);
+
+ if (!(s3c_irqwake_eintallow & bit))
+ return -ENOENT;
+
+ printk(KERN_INFO "wake %s for irq %d\n",
+ state ? "enabled" : "disabled", irqno);
+
+ if (!state)
+ s3c_irqwake_eintmask |= bit;
+ else
+ s3c_irqwake_eintmask &= ~bit;
+
+ return 0;
+}
+
+/* helper functions to save and restore register state */
+
+/**
+ * s3c_pm_do_save() - save a set of registers for restoration on resume.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Run through the list of registers given, saving their contents in the
+ * array for later restoration when we wakeup.
+ */
+void s3c_pm_do_save(struct sleep_save *ptr, int count)
+{
+ for (; count > 0; count--, ptr++) {
+ ptr->val = __raw_readl(ptr->reg);
+ S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
+ }
+}
+
+/**
+ * s3c_pm_do_restore() - restore register values from the save list.
+ * @ptr: Pointer to an array of registers.
+ * @count: Size of the ptr array.
+ *
+ * Restore the register values saved from s3c_pm_do_save().
+ *
+ * Note, we do not use S3C_PMDBG() in here, as the system may not have
+ * restore the UARTs state yet
+*/
+
+void s3c_pm_do_restore(struct sleep_save *ptr, int count)
+{
+ for (; count > 0; count--, ptr++) {
+ printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
+ ptr->reg, ptr->val, __raw_readl(ptr->reg));
+
+ __raw_writel(ptr->val, ptr->reg);
+ }
+}
+
+/**
+ * s3c_pm_do_restore_core() - early restore register values from save list.
+ *
+ * This is similar to s3c_pm_do_restore() except we try and minimise the
+ * side effects of the function in case registers that hardware might need
+ * to work has been restored.
+ *
+ * WARNING: Do not put any debug in here that may effect memory or use
+ * peripherals, as things may be changing!
+*/
+
+void s3c_pm_do_restore_core(struct sleep_save *ptr, int count)
+{
+ for (; count > 0; count--, ptr++)
+ __raw_writel(ptr->val, ptr->reg);
+}
+
+/* s3c2410_pm_show_resume_irqs
+ *
+ * print any IRQs asserted at resume time (ie, we woke from)
+*/
+static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+ unsigned long mask)
+{
+ int i;
+
+ which &= ~mask;
+
+ for (i = 0; i <= 31; i++) {
+ if (which & (1L<<i)) {
+ S3C_PMDBG("IRQ %d asserted at resume\n", start+i);
+ }
+ }
+}
+
+
+void (*pm_cpu_prep)(void);
+void (*pm_cpu_sleep)(void);
+
+#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
+
+/* s3c_pm_enter
+ *
+ * central control for sleep/resume process
+*/
+
+static int s3c_pm_enter(suspend_state_t state)
+{
+ unsigned long regs_save[16];
+
+ /* ensure the debug is initialised (if enabled) */
+
+ s3c_pm_debug_init();
+
+ S3C_PMDBG("%s(%d)\n", __func__, state);
+
+ if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
+ printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
+ return -EINVAL;
+ }
+
+ /* check if we have anything to wake-up with... bad things seem
+ * to happen if you suspend with no wakeup (system will often
+ * require a full power-cycle)
+ */
+
+ if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+ !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
+ printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
+ printk(KERN_ERR "%s: Aborting sleep\n", __func__);
+ return -EINVAL;
+ }
+
+ /* store the physical address of the register recovery block */
+
+ s3c_sleep_save_phys = virt_to_phys(regs_save);
+
+ S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
+
+ /* save all necessary core registers not covered by the drivers */
+
+ s3c_pm_save_gpios();
+ s3c_pm_save_uarts();
+ s3c_pm_save_core();
+
+ /* set the irq configuration for wake */
+
+ s3c_pm_configure_extint();
+
+ S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
+ s3c_irqwake_intmask, s3c_irqwake_eintmask);
+
+ s3c_pm_arch_prepare_irqs();
+
+ /* call cpu specific preparation */
+
+ pm_cpu_prep();
+
+ /* flush cache back to ram */
+
+ flush_cache_all();
+
+ s3c_pm_check_store();
+
+ /* send the cpu to sleep... */
+
+ s3c_pm_arch_stop_clocks();
+
+ /* s3c2410_cpu_save will also act as our return point from when
+ * we resume as it saves its own register state, so use the return
+ * code to differentiate return from save and return from sleep */
+
+ if (s3c_cpu_save(regs_save) == 0) {
+ flush_cache_all();
+ pm_cpu_sleep();
+ }
+
+ /* restore the cpu state using the kernel's cpu init code. */
+
+ cpu_init();
+
+ /* restore the system state */
+
+ s3c_pm_restore_core();
+ s3c_pm_restore_uarts();
+ s3c_pm_restore_gpios();
+
+ s3c_pm_debug_init();
+
+ /* check what irq (if any) restored the system */
+
+ s3c_pm_arch_show_resume_irqs();
+
+ S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
+
+ s3c_pm_check_restore();
+
+ /* LEDs should now be 1110 */
+ s3c_pm_debug_smdkled(1 << 1, 0);
+
+ /* ok, let's return from sleep */
+
+ S3C_PMDBG("S3C PM Resume (post-restore)\n");
+ return 0;
+}
+
+static int s3c_pm_prepare(void)
+{
+ /* prepare check area if configured */
+
+ s3c_pm_check_prepare();
+ return 0;
+}
+
+static void s3c_pm_finish(void)
+{
+ s3c_pm_check_cleanup();
+}
+
+static int s3c_pm_begin(suspend_state_t state)
+{
+ int ret = 0;
+
+#ifdef CONFIG_REGULATOR
+ ret = regulator_suspend_prepare(state);
+#endif
+ return ret;
+}
+
+static struct platform_suspend_ops s3c_pm_ops = {
+ .enter = s3c_pm_enter,
+ .prepare = s3c_pm_prepare,
+ .finish = s3c_pm_finish,
+ .valid = suspend_valid_only_mem,
+ .begin = s3c_pm_begin,
+};
+
+/* s3c_pm_init
+ *
+ * Attach the power management functions. This should be called
+ * from the board specific initialisation if the board supports
+ * it.
+*/
+
+int __init s3c_pm_init(void)
+{
+ printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");
+
+ suspend_set_ops(&s3c_pm_ops);
+ return 0;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-check.c
@@ -0,0 +1,242 @@
+/* linux/arch/arm/plat-s3c/pm-check.c
+ * originally in linux/arch/arm/plat-s3c24xx/pm.c
+ *
+ * Copyright (c) 2004,2006,2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C Power Mangament - suspend/resume memory corruptiuon check.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/init.h>
+#include <linux/crc32.h>
+#include <linux/ioport.h>
+
+#include <plat/pm.h>
+
+#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1
+#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value
+#endif
+
+/* suspend checking code...
+ *
+ * this next area does a set of crc checks over all the installed
+ * memory, so the system can verify if the resume was ok.
+ *
+ * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
+ * increasing it will mean that the area corrupted will be less easy to spot,
+ * and reducing the size will cause the CRC save area to grow
+*/
+
+#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
+
+static u32 crc_size; /* size needed for the crc block */
+static u32 *crcs; /* allocated over suspend/resume */
+
+typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
+
+/* s3c_pm_run_res
+ *
+ * go through the given resource list, and look for system ram
+*/
+
+static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
+{
+ while (ptr != NULL) {
+ if (ptr->child != NULL)
+ s3c_pm_run_res(ptr->child, fn, arg);
+
+ if ((ptr->flags & IORESOURCE_MEM) &&
+ strcmp(ptr->name, "System RAM") == 0) {
+ S3C_PMDBG("Found system RAM at %08lx..%08lx\n",
+ (unsigned long)ptr->start,
+ (unsigned long)ptr->end);
+ arg = (fn)(ptr, arg);
+ }
+
+ ptr = ptr->sibling;
+ }
+}
+
+static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
+{
+ s3c_pm_run_res(&iomem_resource, fn, arg);
+}
+
+static u32 *s3c_pm_countram(struct resource *res, u32 *val)
+{
+ u32 size = (u32)(res->end - res->start)+1;
+
+ size += CHECK_CHUNKSIZE-1;
+ size /= CHECK_CHUNKSIZE;
+
+ S3C_PMDBG("Area %08lx..%08lx, %d blocks\n",
+ (unsigned long)res->start, (unsigned long)res->end, size);
+
+ *val += size * sizeof(u32);
+ return val;
+}
+
+/* s3c_pm_prepare_check
+ *
+ * prepare the necessary information for creating the CRCs. This
+ * must be done before the final save, as it will require memory
+ * allocating, and thus touching bits of the kernel we do not
+ * know about.
+*/
+
+void s3c_pm_check_prepare(void)
+{
+ crc_size = 0;
+
+ s3c_pm_run_sysram(s3c_pm_countram, &crc_size);
+
+ S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size);
+
+ crcs = kmalloc(crc_size+4, GFP_KERNEL);
+ if (crcs == NULL)
+ printk(KERN_ERR "Cannot allocated CRC save area\n");
+}
+
+static u32 *s3c_pm_makecheck(struct resource *res, u32 *val)
+{
+ unsigned long addr, left;
+
+ for (addr = res->start; addr < res->end;
+ addr += CHECK_CHUNKSIZE) {
+ left = res->end - addr;
+
+ if (left > CHECK_CHUNKSIZE)
+ left = CHECK_CHUNKSIZE;
+
+ *val = crc32_le(~0, phys_to_virt(addr), left);
+ val++;
+ }
+
+ return val;
+}
+
+/* s3c_pm_check_store
+ *
+ * compute the CRC values for the memory blocks before the final
+ * sleep.
+*/
+
+void s3c_pm_check_store(void)
+{
+ if (crcs != NULL)
+ s3c_pm_run_sysram(s3c_pm_makecheck, crcs);
+}
+
+/* in_region
+ *
+ * return TRUE if the area defined by ptr..ptr+size contains the
+ * what..what+whatsz
+*/
+
+static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
+{
+ if ((what+whatsz) < ptr)
+ return 0;
+
+ if (what > (ptr+size))
+ return 0;
+
+ return 1;
+}
+
+/**
+ * s3c_pm_runcheck() - helper to check a resource on restore.
+ * @res: The resource to check
+ * @vak: Pointer to list of CRC32 values to check.
+ *
+ * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this
+ * function runs the given memory resource checking it against the stored
+ * CRC to ensure that memory is restored. The function tries to skip as
+ * many of the areas used during the suspend process.
+ */
+static u32 *s3c_pm_runcheck(struct resource *res, u32 *val)
+{
+ void *save_at = phys_to_virt(s3c_sleep_save_phys);
+ unsigned long addr;
+ unsigned long left;
+ void *stkpage;
+ void *ptr;
+ u32 calc;
+
+ stkpage = (void *)((u32)&calc & ~PAGE_MASK);
+
+ for (addr = res->start; addr < res->end;
+ addr += CHECK_CHUNKSIZE) {
+ left = res->end - addr;
+
+ if (left > CHECK_CHUNKSIZE)
+ left = CHECK_CHUNKSIZE;
+
+ ptr = phys_to_virt(addr);
+
+ if (in_region(ptr, left, stkpage, 4096)) {
+ S3C_PMDBG("skipping %08lx, has stack in\n", addr);
+ goto skip_check;
+ }
+
+ if (in_region(ptr, left, crcs, crc_size)) {
+ S3C_PMDBG("skipping %08lx, has crc block in\n", addr);
+ goto skip_check;
+ }
+
+ if (in_region(ptr, left, save_at, 32*4 )) {
+ S3C_PMDBG("skipping %08lx, has save block in\n", addr);
+ goto skip_check;
+ }
+
+ /* calculate and check the checksum */
+
+ calc = crc32_le(~0, ptr, left);
+ if (calc != *val) {
+ printk(KERN_ERR "Restore CRC error at "
+ "%08lx (%08x vs %08x)\n", addr, calc, *val);
+
+ S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n",
+ addr, calc, *val);
+ }
+
+ skip_check:
+ val++;
+ }
+
+ return val;
+}
+
+/**
+ * s3c_pm_check_restore() - memory check called on resume
+ *
+ * check the CRCs after the restore event and free the memory used
+ * to hold them
+*/
+void s3c_pm_check_restore(void)
+{
+ if (crcs != NULL)
+ s3c_pm_run_sysram(s3c_pm_runcheck, crcs);
+}
+
+/**
+ * s3c_pm_check_cleanup() - free memory resources
+ *
+ * Free the resources that where allocated by the suspend
+ * memory check code. We do this separately from the
+ * s3c_pm_check_restore() function as we cannot call any
+ * functions that might sleep during that resume.
+ */
+void s3c_pm_check_cleanup(void)
+{
+ kfree(crcs);
+ crcs = NULL;
+}
+
--- /dev/null
+++ b/arch/arm/plat-s3c/pm-gpio.c
@@ -0,0 +1,378 @@
+/* linux/arch/arm/plat-s3c/pm-gpio.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C series GPIO PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/gpio-core.h>
+#include <plat/pm.h>
+
+/* PM GPIO helpers */
+
+#define OFFS_CON (0x00)
+#define OFFS_DAT (0X04)
+#define OFFS_UP (0X08)
+
+static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
+{
+ chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+ chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+}
+
+static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
+{
+ void __iomem *base = chip->base;
+ u32 old_gpcon = __raw_readl(base + OFFS_CON);
+ u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 gps_gpcon = chip->pm_save[0];
+ u32 gps_gpdat = chip->pm_save[1];
+ u32 gpcon;
+
+ /* GPACON only has one bit per control / data and no PULLUPs.
+ * GPACON[x] = 0 => Output, 1 => SFN */
+
+ /* first set all SFN bits to SFN */
+
+ gpcon = old_gpcon | gps_gpcon;
+ __raw_writel(gpcon, base + OFFS_CON);
+
+ /* now set all the other bits */
+
+ __raw_writel(gps_gpdat, base + OFFS_DAT);
+ __raw_writel(gps_gpcon, base + OFFS_CON);
+
+ S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+ chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_1bit = {
+ .save = s3c_gpio_pm_1bit_save,
+ .resume = s3c_gpio_pm_1bit_resume,
+};
+
+static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
+{
+ chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+ chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+ chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+}
+
+/* Test whether the given masked+shifted bits of an GPIO configuration
+ * are one of the SFN (special function) modes. */
+
+static inline int is_sfn(unsigned long con)
+{
+ return con >= 2;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an input */
+
+static inline int is_in(unsigned long con)
+{
+ return con == 0;
+}
+
+/* Test if the given masked+shifted GPIO configuration is an output */
+
+static inline int is_out(unsigned long con)
+{
+ return con == 1;
+}
+
+/**
+ * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
+ * @chip: The chip information to resume.
+ *
+ * Restore one of the GPIO banks that was saved during suspend. This is
+ * not as simple as once thought, due to the possibility of glitches
+ * from the order that the CON and DAT registers are set in.
+ *
+ * The three states the pin can be are {IN,OUT,SFN} which gives us 9
+ * combinations of changes to check. Three of these, if the pin stays
+ * in the same configuration can be discounted. This leaves us with
+ * the following:
+ *
+ * { IN => OUT } Change DAT first
+ * { IN => SFN } Change CON first
+ * { OUT => SFN } Change CON first, so new data will not glitch
+ * { OUT => IN } Change CON first, so new data will not glitch
+ * { SFN => IN } Change CON first
+ * { SFN => OUT } Change DAT first, so new data will not glitch [1]
+ *
+ * We do not currently deal with the UP registers as these control
+ * weak resistors, so a small delay in change should not need to bring
+ * these into the calculations.
+ *
+ * [1] this assumes that writing to a pin DAT whilst in SFN will set the
+ * state for when it is next output.
+ */
+static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
+{
+ void __iomem *base = chip->base;
+ u32 old_gpcon = __raw_readl(base + OFFS_CON);
+ u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 gps_gpcon = chip->pm_save[0];
+ u32 gps_gpdat = chip->pm_save[1];
+ u32 gpcon, old, new, mask;
+ u32 change_mask = 0x0;
+ int nr;
+
+ /* restore GPIO pull-up settings */
+ __raw_writel(chip->pm_save[2], base + OFFS_UP);
+
+ /* Create a change_mask of all the items that need to have
+ * their CON value changed before their DAT value, so that
+ * we minimise the work between the two settings.
+ */
+
+ for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
+ old = (old_gpcon & mask) >> nr;
+ new = (gps_gpcon & mask) >> nr;
+
+ /* If there is no change, then skip */
+
+ if (old == new)
+ continue;
+
+ /* If both are special function, then skip */
+
+ if (is_sfn(old) && is_sfn(new))
+ continue;
+
+ /* Change is IN => OUT, do not change now */
+
+ if (is_in(old) && is_out(new))
+ continue;
+
+ /* Change is SFN => OUT, do not change now */
+
+ if (is_sfn(old) && is_out(new))
+ continue;
+
+ /* We should now be at the case of IN=>SFN,
+ * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+ change_mask |= mask;
+ }
+
+
+ /* Write the new CON settings */
+
+ gpcon = old_gpcon & ~change_mask;
+ gpcon |= gps_gpcon & change_mask;
+
+ __raw_writel(gpcon, base + OFFS_CON);
+
+ /* Now change any items that require DAT,CON */
+
+ __raw_writel(gps_gpdat, base + OFFS_DAT);
+ __raw_writel(gps_gpcon, base + OFFS_CON);
+
+ S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
+ chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_2bit = {
+ .save = s3c_gpio_pm_2bit_save,
+ .resume = s3c_gpio_pm_2bit_resume,
+};
+
+#ifdef CONFIG_ARCH_S3C64XX
+static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
+{
+ chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
+ chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
+ chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+
+ if (chip->chip.ngpio > 8)
+ chip->pm_save[0] = __raw_readl(chip->base - 4);
+}
+
+static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
+{
+ u32 old, new, mask;
+ u32 change_mask = 0x0;
+ int nr;
+
+ for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) {
+ old = (old_gpcon & mask) >> nr;
+ new = (gps_gpcon & mask) >> nr;
+
+ /* If there is no change, then skip */
+
+ if (old == new)
+ continue;
+
+ /* If both are special function, then skip */
+
+ if (is_sfn(old) && is_sfn(new))
+ continue;
+
+ /* Change is IN => OUT, do not change now */
+
+ if (is_in(old) && is_out(new))
+ continue;
+
+ /* Change is SFN => OUT, do not change now */
+
+ if (is_sfn(old) && is_out(new))
+ continue;
+
+ /* We should now be at the case of IN=>SFN,
+ * OUT=>SFN, OUT=>IN, SFN=>IN. */
+
+ change_mask |= mask;
+ }
+
+ return change_mask;
+}
+
+static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
+{
+ void __iomem *con = chip->base + (index * 4);
+ u32 old_gpcon = __raw_readl(con);
+ u32 gps_gpcon = chip->pm_save[index + 1];
+ u32 gpcon, mask;
+
+ mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
+
+ gpcon = old_gpcon & ~mask;
+ gpcon |= gps_gpcon & mask;
+
+ __raw_writel(gpcon, con);
+}
+
+static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
+{
+ void __iomem *base = chip->base;
+ u32 old_gpcon[2];
+ u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 gps_gpdat = chip->pm_save[2];
+
+ /* First, modify the CON settings */
+
+ old_gpcon[0] = 0;
+ old_gpcon[1] = __raw_readl(base + OFFS_CON);
+
+ s3c_gpio_pm_4bit_con(chip, 0);
+ if (chip->chip.ngpio > 8) {
+ old_gpcon[0] = __raw_readl(base - 4);
+ s3c_gpio_pm_4bit_con(chip, -1);
+ }
+
+ /* Now change the configurations that require DAT,CON */
+
+ __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+ __raw_writel(chip->pm_save[1], base + OFFS_CON);
+ if (chip->chip.ngpio > 8)
+ __raw_writel(chip->pm_save[0], base - 4);
+
+ __raw_writel(chip->pm_save[2], base + OFFS_DAT);
+ __raw_writel(chip->pm_save[3], base + OFFS_UP);
+
+ if (chip->chip.ngpio > 8) {
+ S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
+ chip->chip.label, old_gpcon[0], old_gpcon[1],
+ __raw_readl(base - 4),
+ __raw_readl(base + OFFS_CON),
+ old_gpdat, gps_gpdat);
+ } else
+ S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
+ chip->chip.label, old_gpcon[1],
+ __raw_readl(base + OFFS_CON),
+ old_gpdat, gps_gpdat);
+}
+
+struct s3c_gpio_pm s3c_gpio_pm_4bit = {
+ .save = s3c_gpio_pm_4bit_save,
+ .resume = s3c_gpio_pm_4bit_resume,
+};
+#endif /* CONFIG_ARCH_S3C64XX */
+
+/**
+ * s3c_pm_save_gpio() - save gpio chip data for suspend
+ * @ourchip: The chip for suspend.
+ */
+static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
+{
+ struct s3c_gpio_pm *pm = ourchip->pm;
+
+ if (pm == NULL || pm->save == NULL)
+ S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+ else
+ pm->save(ourchip);
+}
+
+/**
+ * s3c_pm_save_gpios() - Save the state of the GPIO banks.
+ *
+ * For all the GPIO banks, save the state of each one ready for going
+ * into a suspend mode.
+ */
+void s3c_pm_save_gpios(void)
+{
+ struct s3c_gpio_chip *ourchip;
+ unsigned int gpio_nr;
+
+ for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+ ourchip = s3c_gpiolib_getchip(gpio_nr);
+ if (!ourchip)
+ continue;
+
+ s3c_pm_save_gpio(ourchip);
+
+ S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
+ ourchip->chip.label,
+ ourchip->pm_save[0],
+ ourchip->pm_save[1],
+ ourchip->pm_save[2],
+ ourchip->pm_save[3]);
+
+ gpio_nr += ourchip->chip.ngpio;
+ gpio_nr += CONFIG_S3C_GPIO_SPACE;
+ }
+}
+
+/**
+ * s3c_pm_resume_gpio() - restore gpio chip data after suspend
+ * @ourchip: The suspended chip.
+ */
+static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
+{
+ struct s3c_gpio_pm *pm = ourchip->pm;
+
+ if (pm == NULL || pm->resume == NULL)
+ S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+ else
+ pm->resume(ourchip);
+}
+
+void s3c_pm_restore_gpios(void)
+{
+ struct s3c_gpio_chip *ourchip;
+ unsigned int gpio_nr;
+
+ for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) {
+ ourchip = s3c_gpiolib_getchip(gpio_nr);
+ if (!ourchip)
+ continue;
+
+ s3c_pm_resume_gpio(ourchip);
+
+ gpio_nr += ourchip->chip.ngpio;
+ gpio_nr += CONFIG_S3C_GPIO_SPACE;
+ }
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/pwm-clock.c
@@ -0,0 +1,463 @@
+/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
+ *
+ * Copyright (c) 2007 Simtec Electronics
+ * Copyright (c) 2007, 2008 Ben Dooks
+ * Ben Dooks <ben-linux@fluff.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/log2.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+#include <plat/regs-timer.h>
+#include <mach/pwm-clock.h>
+
+/* Each of the timers 0 through 5 go through the following
+ * clock tree, with the inputs depending on the timers.
+ *
+ * pclk ---- [ prescaler 0 ] -+---> timer 0
+ * +---> timer 1
+ *
+ * pclk ---- [ prescaler 1 ] -+---> timer 2
+ * +---> timer 3
+ * \---> timer 4
+ *
+ * Which are fed into the timers as so:
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ * [mux] -> timer 0
+ * tclk 0 ------------------------------/
+ *
+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
+ * [mux] -> timer 1
+ * tclk 0 ------------------------------/
+ *
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ * [mux] -> timer 2
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
+ * [mux] -> timer 3
+ * tclk 1 ------------------------------/
+ *
+ * prescaled 1 ---- [ div 2,4,8, 16 ] --\
+ * [mux] -> timer 4
+ * tclk 1 ------------------------------/
+ *
+ * Since the mux and the divider are tied together in the
+ * same register space, it is impossible to set the parent
+ * and the rate at the same time. To avoid this, we add an
+ * intermediate 'prescaled-and-divided' clock to select
+ * as the parent for the timer input clock called tdiv.
+ *
+ * prescaled clk --> pwm-tdiv ---\
+ * [ mux ] --> timer X
+ * tclk -------------------------/
+*/
+
+static struct clk clk_timer_scaler[];
+
+static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
+{
+ unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+ if (clk == &clk_timer_scaler[1]) {
+ tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
+ tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
+ } else {
+ tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
+ }
+
+ return clk_get_rate(clk->parent) / (tcfg0 + 1);
+}
+
+static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long divisor = parent_rate / rate;
+
+ if (divisor > 256)
+ divisor = 256;
+ else if (divisor < 2)
+ divisor = 2;
+
+ return parent_rate / divisor;
+}
+
+static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
+ unsigned long tcfg0;
+ unsigned long divisor;
+ unsigned long flags;
+
+ divisor = clk_get_rate(clk->parent) / round;
+ divisor--;
+
+ local_irq_save(flags);
+ tcfg0 = __raw_readl(S3C2410_TCFG0);
+
+ if (clk == &clk_timer_scaler[1]) {
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+ tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
+ } else {
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
+ tcfg0 |= divisor;
+ }
+
+ __raw_writel(tcfg0, S3C2410_TCFG0);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static struct clk clk_timer_scaler[] = {
+ [0] = {
+ .name = "pwm-scaler0",
+ .id = -1,
+ .get_rate = clk_pwm_scaler_get_rate,
+ .set_rate = clk_pwm_scaler_set_rate,
+ .round_rate = clk_pwm_scaler_round_rate,
+ },
+ [1] = {
+ .name = "pwm-scaler1",
+ .id = -1,
+ .get_rate = clk_pwm_scaler_get_rate,
+ .set_rate = clk_pwm_scaler_set_rate,
+ .round_rate = clk_pwm_scaler_round_rate,
+ },
+};
+
+static struct clk clk_timer_tclk[] = {
+ [0] = {
+ .name = "pwm-tclk0",
+ .id = -1,
+ },
+ [1] = {
+ .name = "pwm-tclk1",
+ .id = -1,
+ },
+};
+
+struct pwm_tdiv_clk {
+ struct clk clk;
+ unsigned int divisor;
+};
+
+static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
+{
+ return container_of(clk, struct pwm_tdiv_clk, clk);
+}
+
+static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
+{
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+ unsigned int divisor;
+
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+ if (pwm_cfg_src_is_tclk(tcfg1))
+ divisor = to_tdiv(clk)->divisor;
+ else
+ divisor = tcfg_to_divisor(tcfg1);
+
+ return clk_get_rate(clk->parent) / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ unsigned long parent_rate;
+ unsigned long divisor;
+
+ parent_rate = clk_get_rate(clk->parent);
+ divisor = parent_rate / rate;
+
+ if (divisor <= 1 && pwm_tdiv_has_div1())
+ divisor = 1;
+ else if (divisor <= 2)
+ divisor = 2;
+ else if (divisor <= 4)
+ divisor = 4;
+ else if (divisor <= 8)
+ divisor = 8;
+ else
+ divisor = 16;
+
+ return parent_rate / divisor;
+}
+
+static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
+{
+ return pwm_tdiv_div_bits(divclk->divisor);
+}
+
+static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
+{
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+ unsigned long bits = clk_pwm_tdiv_bits(divclk);
+ unsigned long flags;
+ unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
+
+ local_irq_save(flags);
+
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
+ tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+ tcfg1 |= bits << shift;
+ __raw_writel(tcfg1, S3C2410_TCFG1);
+
+ local_irq_restore(flags);
+}
+
+static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct pwm_tdiv_clk *divclk = to_tdiv(clk);
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ unsigned long divisor;
+
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+ rate = clk_round_rate(clk, rate);
+ divisor = parent_rate / rate;
+
+ if (divisor > 16)
+ return -EINVAL;
+
+ divclk->divisor = divisor;
+
+ /* Update the current MUX settings if we are currently
+ * selected as the clock source for this clock. */
+
+ if (!pwm_cfg_src_is_tclk(tcfg1))
+ clk_pwm_tdiv_update(divclk);
+
+ return 0;
+}
+
+static struct pwm_tdiv_clk clk_timer_tdiv[] = {
+ [0] = {
+ .clk = {
+ .name = "pwm-tdiv",
+ .parent = &clk_timer_scaler[0],
+ .get_rate = clk_pwm_tdiv_get_rate,
+ .set_rate = clk_pwm_tdiv_set_rate,
+ .round_rate = clk_pwm_tdiv_round_rate,
+ },
+ },
+ [1] = {
+ .clk = {
+ .name = "pwm-tdiv",
+ .parent = &clk_timer_scaler[0],
+ .get_rate = clk_pwm_tdiv_get_rate,
+ .set_rate = clk_pwm_tdiv_set_rate,
+ .round_rate = clk_pwm_tdiv_round_rate,
+ }
+ },
+ [2] = {
+ .clk = {
+ .name = "pwm-tdiv",
+ .parent = &clk_timer_scaler[1],
+ .get_rate = clk_pwm_tdiv_get_rate,
+ .set_rate = clk_pwm_tdiv_set_rate,
+ .round_rate = clk_pwm_tdiv_round_rate,
+ },
+ },
+ [3] = {
+ .clk = {
+ .name = "pwm-tdiv",
+ .parent = &clk_timer_scaler[1],
+ .get_rate = clk_pwm_tdiv_get_rate,
+ .set_rate = clk_pwm_tdiv_set_rate,
+ .round_rate = clk_pwm_tdiv_round_rate,
+ },
+ },
+ [4] = {
+ .clk = {
+ .name = "pwm-tdiv",
+ .parent = &clk_timer_scaler[1],
+ .get_rate = clk_pwm_tdiv_get_rate,
+ .set_rate = clk_pwm_tdiv_set_rate,
+ .round_rate = clk_pwm_tdiv_round_rate,
+ },
+ },
+};
+
+static int __init clk_pwm_tdiv_register(unsigned int id)
+{
+ struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+ divclk->clk.id = id;
+ divclk->divisor = tcfg_to_divisor(tcfg1);
+
+ return s3c24xx_register_clock(&divclk->clk);
+}
+
+static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
+{
+ return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
+}
+
+static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
+{
+ return &clk_timer_tdiv[id].clk;
+}
+
+static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
+{
+ unsigned int id = clk->id;
+ unsigned long tcfg1;
+ unsigned long flags;
+ unsigned long bits;
+ unsigned long shift = S3C2410_TCFG1_SHIFT(id);
+
+ if (parent == s3c24xx_pwmclk_tclk(id))
+ bits = S3C_TCFG1_MUX_TCLK << shift;
+ else if (parent == s3c24xx_pwmclk_tdiv(id))
+ bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
+ else
+ return -EINVAL;
+
+ clk->parent = parent;
+
+ local_irq_save(flags);
+
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
+ tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
+ __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static struct clk clk_tin[] = {
+ [0] = {
+ .name = "pwm-tin",
+ .id = 0,
+ .set_parent = clk_pwm_tin_set_parent,
+ },
+ [1] = {
+ .name = "pwm-tin",
+ .id = 1,
+ .set_parent = clk_pwm_tin_set_parent,
+ },
+ [2] = {
+ .name = "pwm-tin",
+ .id = 2,
+ .set_parent = clk_pwm_tin_set_parent,
+ },
+ [3] = {
+ .name = "pwm-tin",
+ .id = 3,
+ .set_parent = clk_pwm_tin_set_parent,
+ },
+ [4] = {
+ .name = "pwm-tin",
+ .id = 4,
+ .set_parent = clk_pwm_tin_set_parent,
+ },
+};
+
+static __init int clk_pwm_tin_register(struct clk *pwm)
+{
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
+ unsigned int id = pwm->id;
+
+ struct clk *parent;
+ int ret;
+
+ ret = s3c24xx_register_clock(pwm);
+ if (ret < 0)
+ return ret;
+
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
+
+ if (pwm_cfg_src_is_tclk(tcfg1))
+ parent = s3c24xx_pwmclk_tclk(id);
+ else
+ parent = s3c24xx_pwmclk_tdiv(id);
+
+ return clk_set_parent(pwm, parent);
+}
+
+/**
+ * s3c_pwmclk_init() - initialise pwm clocks
+ *
+ * Initialise and register the clocks which provide the inputs for the
+ * pwm timer blocks.
+ *
+ * Note, this call is required by the time core, so must be called after
+ * the base clocks are added and before any of the initcalls are run.
+ */
+__init void s3c_pwmclk_init(void)
+{
+ struct clk *clk_timers;
+ unsigned int clk;
+ int ret;
+
+ clk_timers = clk_get(NULL, "timers");
+ if (IS_ERR(clk_timers)) {
+ printk(KERN_ERR "%s: no parent clock\n", __func__);
+ return;
+ }
+
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
+ clk_timer_scaler[clk].parent = clk_timers;
+ ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
+ if (ret < 0) {
+ printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
+ return;
+ }
+ }
+
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
+ ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
+ if (ret < 0) {
+ printk(KERN_ERR "error adding pww tclk%d\n", clk);
+ return;
+ }
+ }
+
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
+ ret = clk_pwm_tdiv_register(clk);
+ if (ret < 0) {
+ printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
+ return;
+ }
+ }
+
+ for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
+ ret = clk_pwm_tin_register(&clk_tin[clk]);
+ if (ret < 0) {
+ printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
+ return;
+ }
+ }
+}
--- /dev/null
+++ b/arch/arm/plat-s3c/time.c
@@ -0,0 +1,285 @@
+/* linux/arch/arm/plat-s3c24xx/time.c
+ *
+ * Copyright (C) 2003-2005 Simtec Electronics
+ * Ben Dooks, <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <asm/system.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+#include <asm/irq.h>
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <mach/regs-irq.h>
+#include <asm/mach/time.h>
+#include <mach/tick.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+static unsigned long timer_startval;
+static unsigned long timer_usec_ticks;
+
+#ifndef TICK_MAX
+#define TICK_MAX (0xffff)
+#endif
+
+#define TIMER_USEC_SHIFT 16
+
+/* we use the shifted arithmetic to work out the ratio of timer ticks
+ * to usecs, as often the peripheral clock is not a nice even multiple
+ * of 1MHz.
+ *
+ * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
+ * for the current HZ value of 200 without producing overflows.
+ *
+ * Original patch by Dimitry Andric, updated by Ben Dooks
+*/
+
+
+/* timer_mask_usec_ticks
+ *
+ * given a clock and divisor, make the value to pass into timer_ticks_to_usec
+ * to scale the ticks into usecs
+*/
+
+static inline unsigned long
+timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
+{
+ unsigned long den = pclk / 1000;
+
+ return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
+}
+
+/* timer_ticks_to_usec
+ *
+ * convert timer ticks to usec.
+*/
+
+static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
+{
+ unsigned long res;
+
+ res = ticks * timer_usec_ticks;
+ res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
+
+ return res >> TIMER_USEC_SHIFT;
+}
+
+/***
+ * Returns microsecond since last clock interrupt. Note that interrupts
+ * will have been disabled by do_gettimeoffset()
+ * IRQs are disabled before entering here from do_gettimeofday()
+ */
+
+static unsigned long s3c2410_gettimeoffset (void)
+{
+ unsigned long tdone;
+ unsigned long tval;
+
+ /* work out how many ticks have gone since last timer interrupt */
+
+ tval = __raw_readl(S3C2410_TCNTO(4));
+ tdone = timer_startval - tval;
+
+ /* check to see if there is an interrupt pending */
+
+ if (s3c24xx_ostimer_pending()) {
+ /* re-read the timer, and try and fix up for the missed
+ * interrupt. Note, the interrupt may go off before the
+ * timer has re-loaded from wrapping.
+ */
+
+ tval = __raw_readl(S3C2410_TCNTO(4));
+ tdone = timer_startval - tval;
+
+ if (tval != 0)
+ tdone += timer_startval;
+ }
+
+ return timer_ticks_to_usec(tdone);
+}
+
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+s3c2410_timer_interrupt(int irq, void *dev_id)
+{
+ timer_tick();
+ return IRQ_HANDLED;
+}
+
+static struct irqaction s3c2410_timer_irq = {
+ .name = "S3C2410 Timer Tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = s3c2410_timer_interrupt,
+};
+
+#define use_tclk1_12() ( \
+ machine_is_bast() || \
+ machine_is_vr1000() || \
+ machine_is_anubis() || \
+ machine_is_osiris())
+
+static struct clk *tin;
+static struct clk *tdiv;
+static struct clk *timerclk;
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ *
+ * Currently we only use timer4, as it is the only timer which has no
+ * other function that can be exploited externally
+ */
+static void s3c2410_timer_setup (void)
+{
+ unsigned long tcon;
+ unsigned long tcnt;
+ unsigned long tcfg1;
+ unsigned long tcfg0;
+
+ tcnt = TICK_MAX; /* default value for tcnt */
+
+ /* configure the system for whichever machine is in use */
+
+ if (use_tclk1_12()) {
+ /* timer is at 12MHz, scaler is 1 */
+ timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
+ tcnt = 12000000 / HZ;
+
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
+ tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
+ tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
+ __raw_writel(tcfg1, S3C2410_TCFG1);
+ } else {
+ unsigned long pclk;
+ struct clk *tscaler;
+
+ /* for the h1940 (and others), we use the pclk from the core
+ * to generate the timer values. since values around 50 to
+ * 70MHz are not values we can directly generate the timer
+ * value from, we need to pre-scale and divide before using it.
+ *
+ * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
+ * (8.45 ticks per usec)
+ */
+
+ pclk = clk_get_rate(timerclk);
+
+ /* configure clock tick */
+
+ timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
+
+ tscaler = clk_get_parent(tdiv);
+
+ clk_set_rate(tscaler, pclk / 3);
+ clk_set_rate(tdiv, pclk / 6);
+ clk_set_parent(tin, tdiv);
+
+ tcnt = clk_get_rate(tin) / HZ;
+ }
+
+ tcon = __raw_readl(S3C2410_TCON);
+ tcfg0 = __raw_readl(S3C2410_TCFG0);
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
+
+ /* timers reload after counting zero, so reduce the count by 1 */
+
+ tcnt--;
+
+ printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
+ tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
+
+ /* check to see if timer is within 16bit range... */
+ if (tcnt > TICK_MAX) {
+ panic("setup_timer: HZ is too small, cannot configure timer!");
+ return;
+ }
+
+ __raw_writel(tcfg1, S3C2410_TCFG1);
+ __raw_writel(tcfg0, S3C2410_TCFG0);
+
+ timer_startval = tcnt;
+ __raw_writel(tcnt, S3C2410_TCNTB(4));
+
+ /* ensure timer is stopped... */
+
+ tcon &= ~(7<<20);
+ tcon |= S3C2410_TCON_T4RELOAD;
+ tcon |= S3C2410_TCON_T4MANUALUPD;
+
+ __raw_writel(tcon, S3C2410_TCON);
+ __raw_writel(tcnt, S3C2410_TCNTB(4));
+ __raw_writel(tcnt, S3C2410_TCMPB(4));
+
+ /* start the timer running */
+ tcon |= S3C2410_TCON_T4START;
+ tcon &= ~S3C2410_TCON_T4MANUALUPD;
+ __raw_writel(tcon, S3C2410_TCON);
+}
+
+static void __init s3c2410_timer_resources(void)
+{
+ struct platform_device tmpdev;
+
+ tmpdev.dev.bus = &platform_bus_type;
+ tmpdev.id = 4;
+
+ timerclk = clk_get(NULL, "timers");
+ if (IS_ERR(timerclk))
+ panic("failed to get clock for system timer");
+
+ clk_enable(timerclk);
+
+ if (!use_tclk1_12()) {
+ tin = clk_get(&tmpdev.dev, "pwm-tin");
+ if (IS_ERR(tin))
+ panic("failed to get pwm-tin clock for system timer");
+
+ tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
+ if (IS_ERR(tdiv))
+ panic("failed to get pwm-tdiv clock for system timer");
+ }
+
+ clk_enable(tin);
+}
+
+static void __init s3c2410_timer_init(void)
+{
+ s3c2410_timer_resources();
+ s3c2410_timer_setup();
+ setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
+}
+
+struct sys_timer s3c24xx_timer = {
+ .init = s3c2410_timer_init,
+ .offset = s3c2410_gettimeoffset,
+ .resume = s3c2410_timer_setup
+};
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -27,18 +27,8 @@
*/
#include <linux/init.h>
-#include <linux/module.h>
#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/sysdev.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
#include <linux/io.h>
#include <mach/hardware.h>
@@ -47,490 +37,23 @@
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
+#include <plat/cpu-freq.h>
+
#include <plat/clock.h>
#include <plat/cpu.h>
-
-/* clock information */
-
-static LIST_HEAD(clocks);
-
-DEFINE_MUTEX(clocks_mutex);
-
-/* enable and disable calls for use with the clk struct */
-
-static int clk_null_enable(struct clk *clk, int enable)
-{
- return 0;
-}
-
-/* Clock API calls */
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- struct clk *p;
- struct clk *clk = ERR_PTR(-ENOENT);
- int idno;
-
- if (dev == NULL || dev->bus != &platform_bus_type)
- idno = -1;
- else
- idno = to_platform_device(dev)->id;
-
- mutex_lock(&clocks_mutex);
-
- list_for_each_entry(p, &clocks, list) {
- if (p->id == idno &&
- strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
-
- /* check for the case where a device was supplied, but the
- * clock that was being searched for is not device specific */
-
- if (IS_ERR(clk)) {
- list_for_each_entry(p, &clocks, list) {
- if (p->id == -1 && strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- }
-
- mutex_unlock(&clocks_mutex);
- return clk;
-}
-
-void clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
-int clk_enable(struct clk *clk)
-{
- if (IS_ERR(clk) || clk == NULL)
- return -EINVAL;
-
- clk_enable(clk->parent);
-
- mutex_lock(&clocks_mutex);
-
- if ((clk->usage++) == 0)
- (clk->enable)(clk, 1);
-
- mutex_unlock(&clocks_mutex);
- return 0;
-}
-
-void clk_disable(struct clk *clk)
-{
- if (IS_ERR(clk) || clk == NULL)
- return;
-
- mutex_lock(&clocks_mutex);
-
- if ((--clk->usage) == 0)
- (clk->enable)(clk, 0);
-
- mutex_unlock(&clocks_mutex);
- clk_disable(clk->parent);
-}
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (IS_ERR(clk))
- return 0;
-
- if (clk->rate != 0)
- return clk->rate;
-
- if (clk->get_rate != NULL)
- return (clk->get_rate)(clk);
-
- if (clk->parent != NULL)
- return clk_get_rate(clk->parent);
-
- return clk->rate;
-}
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- if (!IS_ERR(clk) && clk->round_rate)
- return (clk->round_rate)(clk, rate);
-
- return rate;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret;
-
- if (IS_ERR(clk))
- return -EINVAL;
-
- /* We do not default just do a clk->rate = rate as
- * the clock may have been made this way by choice.
- */
-
- WARN_ON(clk->set_rate == NULL);
-
- if (clk->set_rate == NULL)
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
- ret = (clk->set_rate)(clk, rate);
- mutex_unlock(&clocks_mutex);
-
- return ret;
-}
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return clk->parent;
-}
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret = 0;
-
- if (IS_ERR(clk))
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
-
- if (clk->set_parent)
- ret = (clk->set_parent)(clk, parent);
-
- mutex_unlock(&clocks_mutex);
-
- return ret;
-}
-
-EXPORT_SYMBOL(clk_get);
-EXPORT_SYMBOL(clk_put);
-EXPORT_SYMBOL(clk_enable);
-EXPORT_SYMBOL(clk_disable);
-EXPORT_SYMBOL(clk_get_rate);
-EXPORT_SYMBOL(clk_round_rate);
-EXPORT_SYMBOL(clk_set_rate);
-EXPORT_SYMBOL(clk_get_parent);
-EXPORT_SYMBOL(clk_set_parent);
-
-/* base clocks */
-
-static int clk_default_setrate(struct clk *clk, unsigned long rate)
-{
- clk->rate = rate;
- return 0;
-}
-
-struct clk clk_xtal = {
- .name = "xtal",
- .id = -1,
- .rate = 0,
- .parent = NULL,
- .ctrlbit = 0,
-};
-
-struct clk clk_mpll = {
- .name = "mpll",
- .id = -1,
- .set_rate = clk_default_setrate,
-};
-
-struct clk clk_upll = {
- .name = "upll",
- .id = -1,
- .parent = NULL,
- .ctrlbit = 0,
-};
-
-struct clk clk_f = {
- .name = "fclk",
- .id = -1,
- .rate = 0,
- .parent = &clk_mpll,
- .ctrlbit = 0,
- .set_rate = clk_default_setrate,
-};
-
-struct clk clk_h = {
- .name = "hclk",
- .id = -1,
- .rate = 0,
- .parent = NULL,
- .ctrlbit = 0,
- .set_rate = clk_default_setrate,
-};
-
-struct clk clk_p = {
- .name = "pclk",
- .id = -1,
- .rate = 0,
- .parent = NULL,
- .ctrlbit = 0,
- .set_rate = clk_default_setrate,
-};
-
-struct clk clk_usb_bus = {
- .name = "usb-bus",
- .id = -1,
- .rate = 0,
- .parent = &clk_upll,
-};
-
-/* clocks that could be registered by external code */
-
-static int s3c24xx_dclk_enable(struct clk *clk, int enable)
-{
- unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
- if (enable)
- dclkcon |= clk->ctrlbit;
- else
- dclkcon &= ~clk->ctrlbit;
-
- __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
- return 0;
-}
-
-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
-{
- unsigned long dclkcon;
- unsigned int uclk;
-
- if (parent == &clk_upll)
- uclk = 1;
- else if (parent == &clk_p)
- uclk = 0;
- else
- return -EINVAL;
-
- clk->parent = parent;
-
- dclkcon = __raw_readl(S3C24XX_DCLKCON);
-
- if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
- if (uclk)
- dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
- else
- dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
- } else {
- if (uclk)
- dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
- else
- dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
- }
-
- __raw_writel(dclkcon, S3C24XX_DCLKCON);
-
- return 0;
-}
-
-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
-{
- unsigned long div;
-
- if ((rate == 0) || !clk->parent)
- return 0;
-
- div = clk_get_rate(clk->parent) / rate;
- if (div < 2)
- div = 2;
- else if (div > 16)
- div = 16;
-
- return div;
-}
-
-static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
- unsigned long rate)
-{
- unsigned long div = s3c24xx_calc_div(clk, rate);
-
- if (div == 0)
- return 0;
-
- return clk_get_rate(clk->parent) / div;
-}
-
-static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
-
- if (div == 0)
- return -EINVAL;
-
- if (clk == &s3c24xx_dclk0) {
- mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
- S3C2410_DCLKCON_DCLK0_CMP_MASK;
- data = S3C2410_DCLKCON_DCLK0_DIV(div) |
- S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
- } else if (clk == &s3c24xx_dclk1) {
- mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
- S3C2410_DCLKCON_DCLK1_CMP_MASK;
- data = S3C2410_DCLKCON_DCLK1_DIV(div) |
- S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
- } else
- return -EINVAL;
-
- clk->rate = clk_get_rate(clk->parent) / div;
- __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
- S3C24XX_DCLKCON);
- return clk->rate;
-}
-
-static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
-{
- unsigned long mask;
- unsigned long source;
-
- /* calculate the MISCCR setting for the clock */
-
- if (parent == &clk_xtal)
- source = S3C2410_MISCCR_CLK0_MPLL;
- else if (parent == &clk_upll)
- source = S3C2410_MISCCR_CLK0_UPLL;
- else if (parent == &clk_f)
- source = S3C2410_MISCCR_CLK0_FCLK;
- else if (parent == &clk_h)
- source = S3C2410_MISCCR_CLK0_HCLK;
- else if (parent == &clk_p)
- source = S3C2410_MISCCR_CLK0_PCLK;
- else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
- source = S3C2410_MISCCR_CLK0_DCLK0;
- else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
- source = S3C2410_MISCCR_CLK0_DCLK0;
- else
- return -EINVAL;
-
- clk->parent = parent;
-
- if (clk == &s3c24xx_clkout0)
- mask = S3C2410_MISCCR_CLK0_MASK;
- else {
- source <<= 4;
- mask = S3C2410_MISCCR_CLK1_MASK;
- }
-
- s3c2410_modify_misccr(mask, source);
- return 0;
-}
-
-/* external clock definitions */
-
-struct clk s3c24xx_dclk0 = {
- .name = "dclk0",
- .id = -1,
- .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
- .enable = s3c24xx_dclk_enable,
- .set_parent = s3c24xx_dclk_setparent,
- .set_rate = s3c24xx_set_dclk_rate,
- .round_rate = s3c24xx_round_dclk_rate,
-};
-
-struct clk s3c24xx_dclk1 = {
- .name = "dclk1",
- .id = -1,
- .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
- .enable = s3c24xx_dclk_enable,
- .set_parent = s3c24xx_dclk_setparent,
- .set_rate = s3c24xx_set_dclk_rate,
- .round_rate = s3c24xx_round_dclk_rate,
-};
-
-struct clk s3c24xx_clkout0 = {
- .name = "clkout0",
- .id = -1,
- .set_parent = s3c24xx_clkout_setparent,
-};
-
-struct clk s3c24xx_clkout1 = {
- .name = "clkout1",
- .id = -1,
- .set_parent = s3c24xx_clkout_setparent,
-};
-
-struct clk s3c24xx_uclk = {
- .name = "uclk",
- .id = -1,
-};
-
-/* initialise the clock system */
-
-int s3c24xx_register_clock(struct clk *clk)
-{
- clk->owner = THIS_MODULE;
-
- if (clk->enable == NULL)
- clk->enable = clk_null_enable;
-
- /* add to the list of available clocks */
-
- mutex_lock(&clocks_mutex);
- list_add(&clk->list, &clocks);
- mutex_unlock(&clocks_mutex);
-
- return 0;
-}
-
-int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
-{
- int fails = 0;
-
- for (; nr_clks > 0; nr_clks--, clks++) {
- if (s3c24xx_register_clock(*clks) < 0)
- fails++;
- }
-
- return fails;
-}
+#include <plat/pll.h>
/* initalise all the clocks */
-int __init s3c24xx_setup_clocks(unsigned long xtal,
- unsigned long fclk,
- unsigned long hclk,
- unsigned long pclk)
+void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
+ unsigned long hclk,
+ unsigned long pclk)
{
- printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
-
- /* initialise the main system clocks */
-
- clk_xtal.rate = xtal;
- clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
+ clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
+ clk_xtal.rate);
clk_mpll.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_f.rate = fclk;
-
- /* assume uart clocks are correctly setup */
-
- /* register our clocks */
-
- if (s3c24xx_register_clock(&clk_xtal) < 0)
- printk(KERN_ERR "failed to register master xtal\n");
-
- if (s3c24xx_register_clock(&clk_mpll) < 0)
- printk(KERN_ERR "failed to register mpll clock\n");
-
- if (s3c24xx_register_clock(&clk_upll) < 0)
- printk(KERN_ERR "failed to register upll clock\n");
-
- if (s3c24xx_register_clock(&clk_f) < 0)
- printk(KERN_ERR "failed to register cpu fclk\n");
-
- if (s3c24xx_register_clock(&clk_h) < 0)
- printk(KERN_ERR "failed to register cpu hclk\n");
-
- if (s3c24xx_register_clock(&clk_p) < 0)
- printk(KERN_ERR "failed to register cpu pclk\n");
-
- return 0;
}
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -0,0 +1,194 @@
+/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
+ *
+ * Copyright (c) 2004,2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C24XX - definitions for DCLK and CLKOUT registers
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+/* clocks that could be registered by external code */
+
+static int s3c24xx_dclk_enable(struct clk *clk, int enable)
+{
+ unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
+
+ if (enable)
+ dclkcon |= clk->ctrlbit;
+ else
+ dclkcon &= ~clk->ctrlbit;
+
+ __raw_writel(dclkcon, S3C24XX_DCLKCON);
+
+ return 0;
+}
+
+static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
+{
+ unsigned long dclkcon;
+ unsigned int uclk;
+
+ if (parent == &clk_upll)
+ uclk = 1;
+ else if (parent == &clk_p)
+ uclk = 0;
+ else
+ return -EINVAL;
+
+ clk->parent = parent;
+
+ dclkcon = __raw_readl(S3C24XX_DCLKCON);
+
+ if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
+ if (uclk)
+ dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
+ else
+ dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
+ } else {
+ if (uclk)
+ dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
+ else
+ dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
+ }
+
+ __raw_writel(dclkcon, S3C24XX_DCLKCON);
+
+ return 0;
+}
+static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
+{
+ unsigned long div;
+
+ if ((rate == 0) || !clk->parent)
+ return 0;
+
+ div = clk_get_rate(clk->parent) / rate;
+ if (div < 2)
+ div = 2;
+ else if (div > 16)
+ div = 16;
+
+ return div;
+}
+
+static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
+ unsigned long rate)
+{
+ unsigned long div = s3c24xx_calc_div(clk, rate);
+
+ if (div == 0)
+ return 0;
+
+ return clk_get_rate(clk->parent) / div;
+}
+
+static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
+
+ if (div == 0)
+ return -EINVAL;
+
+ if (clk == &s3c24xx_dclk0) {
+ mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
+ S3C2410_DCLKCON_DCLK0_CMP_MASK;
+ data = S3C2410_DCLKCON_DCLK0_DIV(div) |
+ S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
+ } else if (clk == &s3c24xx_dclk1) {
+ mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
+ S3C2410_DCLKCON_DCLK1_CMP_MASK;
+ data = S3C2410_DCLKCON_DCLK1_DIV(div) |
+ S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
+ } else
+ return -EINVAL;
+
+ clk->rate = clk_get_rate(clk->parent) / div;
+ __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
+ S3C24XX_DCLKCON);
+ return clk->rate;
+}
+static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
+{
+ unsigned long mask;
+ unsigned long source;
+
+ /* calculate the MISCCR setting for the clock */
+
+ if (parent == &clk_xtal)
+ source = S3C2410_MISCCR_CLK0_MPLL;
+ else if (parent == &clk_upll)
+ source = S3C2410_MISCCR_CLK0_UPLL;
+ else if (parent == &clk_f)
+ source = S3C2410_MISCCR_CLK0_FCLK;
+ else if (parent == &clk_h)
+ source = S3C2410_MISCCR_CLK0_HCLK;
+ else if (parent == &clk_p)
+ source = S3C2410_MISCCR_CLK0_PCLK;
+ else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
+ source = S3C2410_MISCCR_CLK0_DCLK0;
+ else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
+ source = S3C2410_MISCCR_CLK0_DCLK0;
+ else
+ return -EINVAL;
+
+ clk->parent = parent;
+
+ if (clk == &s3c24xx_clkout0)
+ mask = S3C2410_MISCCR_CLK0_MASK;
+ else {
+ source <<= 4;
+ mask = S3C2410_MISCCR_CLK1_MASK;
+ }
+
+ s3c2410_modify_misccr(mask, source);
+ return 0;
+}
+
+/* external clock definitions */
+
+struct clk s3c24xx_dclk0 = {
+ .name = "dclk0",
+ .id = -1,
+ .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
+ .enable = s3c24xx_dclk_enable,
+ .set_parent = s3c24xx_dclk_setparent,
+ .set_rate = s3c24xx_set_dclk_rate,
+ .round_rate = s3c24xx_round_dclk_rate,
+};
+
+struct clk s3c24xx_dclk1 = {
+ .name = "dclk1",
+ .id = -1,
+ .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
+ .enable = s3c24xx_dclk_enable,
+ .set_parent = s3c24xx_dclk_setparent,
+ .set_rate = s3c24xx_set_dclk_rate,
+ .round_rate = s3c24xx_round_dclk_rate,
+};
+
+struct clk s3c24xx_clkout0 = {
+ .name = "clkout0",
+ .id = -1,
+ .set_parent = s3c24xx_clkout_setparent,
+};
+
+struct clk s3c24xx_clkout1 = {
+ .name = "clkout1",
+ .id = -1,
+ .set_parent = s3c24xx_clkout_setparent,
+};
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -38,7 +38,7 @@
#include <mach/regs-gpio.h>
#include <mach/leds-gpio.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/nand.h>
#include <plat/common-smdk.h>
#include <plat/devs.h>
@@ -201,5 +201,5 @@
platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
- s3c2410_pm_init();
+ s3c_pm_init();
}
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -55,16 +55,6 @@
#include <plat/s3c2442.h>
#include <plat/s3c2443.h>
-struct cpu_table {
- unsigned long idcode;
- unsigned long idmask;
- void (*map_io)(struct map_desc *mach_desc, int size);
- void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
- void (*init_clocks)(int xtal);
- int (*init)(void);
- const char *name;
-};
-
/* table of supported CPUs */
static const char name_s3c2400[] = "S3C2400";
@@ -72,6 +62,7 @@
static const char name_s3c2412[] = "S3C2412";
static const char name_s3c2440[] = "S3C2440";
static const char name_s3c2442[] = "S3C2442";
+static const char name_s3c2442b[] = "S3C2442B";
static const char name_s3c2443[] = "S3C2443";
static const char name_s3c2410a[] = "S3C2410A";
static const char name_s3c2440a[] = "S3C2440A";
@@ -123,6 +114,15 @@
.name = name_s3c2442
},
{
+ .idcode = 0x32440aab,
+ .idmask = 0xffffffff,
+ .map_io = s3c244x_map_io,
+ .init_clocks = s3c244x_init_clocks,
+ .init_uarts = s3c244x_init_uarts,
+ .init = s3c2442_init,
+ .name = name_s3c2442b
+ },
+ {
.idcode = 0x32412001,
.idmask = 0xffffffff,
.map_io = s3c2412_map_io,
@@ -169,23 +169,7 @@
IODESC_ENT(UART)
};
-static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
-{
- struct cpu_table *tab;
- int count;
-
- tab = cpu_ids;
- for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
- if ((idcode & tab->idmask) == tab->idcode)
- return tab;
- }
-
- return NULL;
-}
-
-/* cpu information */
-
-static struct cpu_table *cpu;
+/* read cpu identificaiton code */
static unsigned long s3c24xx_read_idcode_v5(void)
{
@@ -231,6 +215,7 @@
unsigned long idcode = 0x0;
/* initialise the io descriptors we need for initialisation */
+ iotable_init(mach_desc, size);
iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
if (cpu_architecture() >= CPU_ARCH_ARMv5) {
@@ -239,117 +224,7 @@
idcode = s3c24xx_read_idcode_v4();
}
- cpu = s3c_lookup_cpu(idcode);
-
- if (cpu == NULL) {
- printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
- panic("Unknown S3C24XX CPU");
- }
-
- printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
-
- if (cpu->map_io == NULL || cpu->init == NULL) {
- printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
- panic("Unsupported S3C24XX CPU");
- }
-
arm_pm_restart = s3c24xx_pm_restart;
- (cpu->map_io)(mach_desc, size);
-}
-
-/* s3c24xx_init_clocks
- *
- * Initialise the clock subsystem and associated information from the
- * given master crystal value.
- *
- * xtal = 0 -> use default PLL crystal value (normally 12MHz)
- * != 0 -> PLL crystal value in Hz
-*/
-
-void __init s3c24xx_init_clocks(int xtal)
-{
- if (xtal == 0)
- xtal = 12*1000*1000;
-
- if (cpu == NULL)
- panic("s3c24xx_init_clocks: no cpu setup?\n");
-
- if (cpu->init_clocks == NULL)
- panic("s3c24xx_init_clocks: cpu has no clock init\n");
- else
- (cpu->init_clocks)(xtal);
+ s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
}
-
-/* uart management */
-
-static int nr_uarts __initdata = 0;
-
-static struct s3c2410_uartcfg uart_cfgs[3];
-
-/* s3c24xx_init_uartdevs
- *
- * copy the specified platform data and configuration into our central
- * set of devices, before the data is thrown away after the init process.
- *
- * This also fills in the array passed to the serial driver for the
- * early initialisation of the console.
-*/
-
-void __init s3c24xx_init_uartdevs(char *name,
- struct s3c24xx_uart_resources *res,
- struct s3c2410_uartcfg *cfg, int no)
-{
- struct platform_device *platdev;
- struct s3c2410_uartcfg *cfgptr = uart_cfgs;
- struct s3c24xx_uart_resources *resp;
- int uart;
-
- memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
-
- for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
- platdev = s3c24xx_uart_src[cfgptr->hwport];
-
- resp = res + cfgptr->hwport;
-
- s3c24xx_uart_devs[uart] = platdev;
-
- platdev->name = name;
- platdev->resource = resp->resources;
- platdev->num_resources = resp->nr_resources;
-
- platdev->dev.platform_data = cfgptr;
- }
-
- nr_uarts = no;
-}
-
-void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
- if (cpu == NULL)
- return;
-
- if (cpu->init_uarts == NULL) {
- printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
- } else
- (cpu->init_uarts)(cfg, no);
-}
-
-static int __init s3c_arch_init(void)
-{
- int ret;
-
- // do the correct init for cpu
-
- if (cpu == NULL)
- panic("s3c_arch_init: NULL cpu\n");
-
- ret = (cpu->init)();
- if (ret != 0)
- return ret;
-
- ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
- return ret;
-}
-
-arch_initcall(s3c_arch_init);
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -26,14 +26,16 @@
#include <asm/mach/irq.h>
#include <mach/fb.h>
#include <mach/hardware.h>
+#include <mach/ts.h>
+#include <asm/io.h>
#include <asm/irq.h>
#include <plat/regs-serial.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/udc.h>
#include <plat/devs.h>
#include <plat/cpu.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
/* Serial port registrations */
@@ -76,6 +78,19 @@
}
};
+static struct resource s3c2410_uart3_resource[] = {
+ [0] = {
+ .start = S3C2443_PA_UART3,
+ .end = S3C2443_PA_UART3 + 0x3fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX3,
+ .end = IRQ_S3CUART_ERR3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
[0] = {
.resources = s3c2410_uart0_resource,
@@ -89,6 +104,10 @@
.resources = s3c2410_uart2_resource,
.nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
},
+ [3] = {
+ .resources = s3c2410_uart3_resource,
+ .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
+ },
};
/* yart devices */
@@ -105,13 +124,18 @@
.id = 2,
};
-struct platform_device *s3c24xx_uart_src[3] = {
+static struct platform_device s3c24xx_uart_device3 = {
+ .id = 3,
+};
+
+struct platform_device *s3c24xx_uart_src[4] = {
&s3c24xx_uart_device0,
&s3c24xx_uart_device1,
&s3c24xx_uart_device2,
+ &s3c24xx_uart_device3,
};
-struct platform_device *s3c24xx_uart_devs[3] = {
+struct platform_device *s3c24xx_uart_devs[4] = {
};
/* USB Host Controller */
@@ -192,8 +216,8 @@
static struct resource s3c_nand_resource[] = {
[0] = {
- .start = S3C2410_PA_NAND,
- .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
+ .start = S3C24XX_PA_NAND,
+ .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -207,6 +231,23 @@
EXPORT_SYMBOL(s3c_device_nand);
+/* Touchscreen */
+struct platform_device s3c_device_ts = {
+ .name = "s3c2410-ts",
+ .id = -1,
+};
+
+EXPORT_SYMBOL(s3c_device_ts);
+
+static struct s3c2410_ts_mach_info s3c2410ts_info;
+
+void set_s3c2410ts_info(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
+{
+ memcpy(&s3c2410ts_info,hard_s3c2410ts_info,sizeof(struct s3c2410_ts_mach_info));
+ s3c_device_ts.dev.platform_data = &s3c2410ts_info;
+}
+EXPORT_SYMBOL(set_s3c2410ts_info);
+
/* USB Device (Gadget)*/
static struct resource s3c_usbgadget_resource[] = {
@@ -271,31 +312,6 @@
EXPORT_SYMBOL(s3c_device_wdt);
-/* I2C */
-
-static struct resource s3c_i2c_resource[] = {
- [0] = {
- .start = S3C24XX_PA_IIC,
- .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_IIC,
- .end = IRQ_IIC,
- .flags = IORESOURCE_IRQ,
- }
-
-};
-
-struct platform_device s3c_device_i2c = {
- .name = "s3c2410-i2c",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_i2c_resource),
- .resource = s3c_i2c_resource,
-};
-
-EXPORT_SYMBOL(s3c_device_i2c);
-
/* IIS */
static struct resource s3c_iis_resource[] = {
@@ -382,8 +398,8 @@
static struct resource s3c_sdi_resource[] = {
[0] = {
- .start = S3C2410_PA_SDI,
- .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
+ .start = S3C24XX_PA_SDI,
+ .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -403,36 +419,6 @@
EXPORT_SYMBOL(s3c_device_sdi);
-/* High-speed MMC/SD */
-
-static struct resource s3c_hsmmc_resource[] = {
- [0] = {
- .start = S3C2443_PA_HSMMC,
- .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_S3C2443_HSMMC,
- .end = IRQ_S3C2443_HSMMC,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
-
-struct platform_device s3c_device_hsmmc = {
- .name = "s3c-sdhci",
- .id = -1,
- .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
- .resource = s3c_hsmmc_resource,
- .dev = {
- .dma_mask = &s3c_device_hsmmc_dmamask,
- .coherent_dma_mask = 0xffffffffUL
- }
-};
-
-
-
/* SPI (0) */
static struct resource s3c_spi0_resource[] = {
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -32,6 +32,7 @@
#include <asm/irq.h>
#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
{
@@ -215,3 +216,423 @@
}
EXPORT_SYMBOL(s3c2410_gpio_irq2pin);
+
+static void pretty_dump(u32 cfg, u32 state, u32 pull,
+ const char ** function_names_2,
+ const char ** function_names_3,
+ const char * prefix,
+ int count)
+{
+ int n;
+ const char *tag_type = NULL,
+ *tag_state = NULL,
+ *tag_pulldown = NULL,
+ * level0 = "0",
+ * level1 = "1";
+
+ for (n = 0; n < count; n++) {
+ switch ((cfg >> (2 * n)) & 3) {
+ case 0:
+ tag_type = "input ";
+ break;
+ case 1:
+ tag_type = "OUTPUT ";
+ break;
+ case 2:
+ if (function_names_2) {
+ if (function_names_2[n])
+ tag_type = function_names_2[n];
+ else
+ tag_type = "*** ILLEGAL CFG (2) *** ";
+ } else
+ tag_type = "(function) ";
+ break;
+ default:
+ if (function_names_3) {
+ if (function_names_3[n])
+ tag_type = function_names_3[n];
+ else
+ tag_type = "*** ILLEGAL CFG (3) *** ";
+ } else
+ tag_type = "(function) ";
+ break;
+ }
+ if ((state >> n) & 1)
+ tag_state = level1;
+ else
+ tag_state = level0;
+
+ if (((pull >> n) & 1))
+ tag_pulldown = "";
+ else
+ tag_pulldown = "(pulldown)";
+
+ printk(KERN_INFO"%s%02d: %s %s %s\n", prefix, n, tag_type,
+ tag_state, tag_pulldown);
+ }
+ printk(KERN_INFO"\n");
+}
+
+static void pretty_dump_a(u32 cfg, u32 state,
+ const char ** function_names,
+ const char * prefix,
+ int count)
+{
+ int n;
+ const char *tag_type = NULL,
+ *tag_state = NULL,
+ * level0 = "0",
+ * level1 = "1";
+
+ for (n = 0; n < count; n++) {
+ switch ((cfg >> n) & 1) {
+ case 0:
+ tag_type = "OUTPUT ";
+ break;
+ default:
+ if (function_names) {
+ if (function_names[n])
+ tag_type = function_names[n];
+ else
+ tag_type = "*** ILLEGAL CFG *** ";
+ } else
+ tag_type = "(function) ";
+ break;
+ }
+ if ((state >> n) & 1)
+ tag_state = level1;
+ else
+ tag_state = level0;
+
+ printk(KERN_INFO"%s%02d: %s %s\n", prefix, n, tag_type,
+ tag_state);
+ }
+ printk(KERN_INFO"\n");
+}
+
+static const char * funcs_a[] = {
+ "ADDR0 ",
+ "ADDR16 ",
+ "ADDR17 ",
+ "ADDR18 ",
+ "ADDR19 ",
+ "ADDR20 ",
+ "ADDR21 ",
+ "ADDR22 ",
+ "ADDR23 ",
+ "ADDR24 ",
+ "ADDR25 ",
+ "ADDR26 ",
+ "nGCS[1] ",
+ "nGCS[2] ",
+ "nGCS[3] ",
+ "nGCS[4] ",
+ "nGCS[5] ",
+ "CLE ",
+ "ALE ",
+ "nFWE ",
+ "nFRE ",
+ "nRSTOUT ",
+ "nFCE ",
+ NULL,
+ NULL
+};
+
+
+static const char * funcs_b2[] = {
+ "TOUT0 ",
+ "TOUT1 ",
+ "TOUT2 ",
+ "TOUT3 ",
+ "TCLK[0] ",
+ "nXBACK ",
+ "nXBREQ ",
+ "nXDACK1 ",
+ "nXDREQ1 ",
+ "nXDACK0 ",
+ "nXDREQ0 ",
+};
+static const char * funcs_b3[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * funcs_c2[] = {
+ "LEND ",
+ "VCLK ",
+ "VLINE ",
+ "VFRAME ",
+ "VM ",
+ "LCD_LPCOE ",
+ "LCD_LPCREV ",
+ "LCD_LPCREVB",
+ "VD[0] ",
+ "VD[1] ",
+ "VD[2] ",
+ "VD[3] ",
+ "VD[4] ",
+ "VD[5] ",
+ "VD[6] ",
+ "VD[7] ",
+};
+static const char * funcs_c3[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "I2SSDI ",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * funcs_d2[] = {
+ "VD[8] ",
+ "VD[9] ",
+ "VD[10] ",
+ "VD[11] ",
+ "VD[12] ",
+ "VD[13] ",
+ "VD[14] ",
+ "VD[15] ",
+ "VD[16] ",
+ "VD[17] ",
+ "VD[18] ",
+ "VD[19] ",
+ "VD[20] ",
+ "VD[21] ",
+ "VD[22] ",
+ "VD[23] ",
+};
+static const char * funcs_d3[] = {
+ "nSPICS1 ",
+ "SPICLK1 ",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "SPIMISO1 ",
+ "SPIMOSI1 ",
+ "SPICLK1 ",
+ NULL,
+ NULL,
+ NULL,
+ "nSS1 ",
+ "nSS0 ",
+};
+
+static const char * funcs_e2[] = {
+ "I2SLRCK ",
+ "I2SSCLK ",
+ "CDCLK ",
+ "I2SDI ",
+ "I2SDO ",
+ "SDCLK ",
+ "SDCMD ",
+ "SDDAT0 ",
+ "SDDAT1 ",
+ "SDDAT2 ",
+ "SDDAT3 ",
+ "SPIMISO0 ",
+ "SPIMOSI0 ",
+ "SPICLK0 ",
+ "IICSCL ",
+ "IICSDA ",
+};
+static const char * funcs_e3[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * funcs_f2[] = {
+ "EINT[0] ",
+ "EINT[1] ",
+ "EINT[2] ",
+ "EINT[3] ",
+ "EINT[4] ",
+ "EINT[5] ",
+ "EINT[6] ",
+ "EINT[7] ",
+};
+static const char * funcs_f3[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+
+static const char * funcs_g2[] = {
+ "EINT[8] ",
+ "EINT[9] ",
+ "EINT[10] ",
+ "EINT[11] ",
+ "EINT[12] ",
+ "EINT[13] ",
+ "EINT[14] ",
+ "EINT[15] ",
+ "EINT[16] ",
+ "EINT[17] ",
+ "EINT[18] ",
+ "EINT[19] ",
+ "EINT[20] ",
+ "EINT[21] ",
+ "EINT[22] ",
+ "EINT[23] ",
+};
+static const char * funcs_g3[] = {
+ NULL,
+ NULL,
+ "nSS0 ",
+ "nSS1 ",
+ "LCD_PWRDN ",
+ "SPIMISO1 ",
+ "SPIMOSI1 ",
+ "SPICLK1 ",
+ NULL,
+ "nRTS1 ",
+ "nCTS1 ",
+ "TCLK[1] ",
+ "nSPICS0 ",
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * funcs_h2[] = {
+ "nCTS0 ",
+ "nRTS0 ",
+ "TXD[0] ",
+ "RXD[0] ",
+ "TXD[1] ",
+ "RXD[1] ",
+ "TXD[2] ",
+ "RXD[2] ",
+ "UEXTCLK ",
+ "CLKOUT0 ",
+ "CLKOUT1 ",
+};
+static const char * funcs_h3[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "nRTS1 ",
+ "nCTS1 ",
+ NULL,
+ "nSPICS0 ",
+ NULL,
+};
+
+static const char * funcs_j2[] = {
+ "CAMDATA[0] ",
+ "CAMDATA[1] ",
+ "CAMDATA[2] ",
+ "CAMDATA[3] ",
+ "CAMDATA[4] ",
+ "CAMDATA[5] ",
+ "CAMDATA[6] ",
+ "CAMDATA[7] ",
+ "CAMPCLK ",
+ "CAMVSYNC ",
+ "CAMHREF ",
+ "CAMCLKOUT ",
+ "CAMRESET ",
+};
+static const char * funcs_j3[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+/* used to dump GPIO states at suspend */
+void s3c24xx_dump_gpio_states(void)
+{
+ pretty_dump_a(__raw_readl(S3C2410_GPACON),
+ __raw_readl(S3C2410_GPADAT),
+ funcs_a, "GPA", 25);
+ pretty_dump(__raw_readl(S3C2410_GPBCON),
+ __raw_readl(S3C2410_GPBDAT),
+ __raw_readl(S3C2410_GPBUP),
+ funcs_b2, funcs_b3, "GPB", 11);
+ pretty_dump(__raw_readl(S3C2410_GPCCON),
+ __raw_readl(S3C2410_GPCDAT),
+ __raw_readl(S3C2410_GPCUP),
+ funcs_c2, funcs_c3, "GPC", 16);
+ pretty_dump(__raw_readl(S3C2410_GPDCON),
+ __raw_readl(S3C2410_GPDDAT),
+ __raw_readl(S3C2410_GPDUP),
+ funcs_d2, funcs_d3, "GPD", 16);
+ pretty_dump(__raw_readl(S3C2410_GPECON),
+ __raw_readl(S3C2410_GPEDAT),
+ __raw_readl(S3C2410_GPEUP),
+ funcs_e2, funcs_e3, "GPE", 16);
+ pretty_dump(__raw_readl(S3C2410_GPFCON),
+ __raw_readl(S3C2410_GPFDAT),
+ __raw_readl(S3C2410_GPFUP),
+ funcs_f2, funcs_f3, "GPF", 8);
+ pretty_dump(__raw_readl(S3C2410_GPGCON),
+ __raw_readl(S3C2410_GPGDAT),
+ __raw_readl(S3C2410_GPGUP),
+ funcs_g2, funcs_g3, "GPG", 16);
+ pretty_dump(__raw_readl(S3C2410_GPHCON),
+ __raw_readl(S3C2410_GPHDAT),
+ __raw_readl(S3C2410_GPHUP),
+ funcs_h2, funcs_h3, "GPH", 11);
+ pretty_dump(__raw_readl(S3C2440_GPJCON),
+ __raw_readl(S3C2440_GPJDAT),
+ __raw_readl(S3C2440_GPJUP),
+ funcs_j2, funcs_j3, "GPJ", 13);
+
+}
+EXPORT_SYMBOL(s3c24xx_dump_gpio_states);
+
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -19,104 +19,13 @@
#include <linux/io.h>
#include <linux/gpio.h>
+#include <plat/gpio-core.h>
#include <mach/hardware.h>
#include <asm/irq.h>
+#include <plat/pm.h>
#include <mach/regs-gpio.h>
-struct s3c24xx_gpio_chip {
- struct gpio_chip chip;
- void __iomem *base;
-};
-
-static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
-{
- return container_of(gpc, struct s3c24xx_gpio_chip, chip);
-}
-
-/* these routines are exported for use by other parts of the platform
- * and system support, but are not intended to be used directly by the
- * drivers themsevles.
- */
-
-static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
-{
- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
- void __iomem *base = ourchip->base;
- unsigned long flags;
- unsigned long con;
-
- local_irq_save(flags);
-
- con = __raw_readl(base + 0x00);
- con &= ~(3 << (offset * 2));
- con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
-
- __raw_writel(con, base + 0x00);
-
- local_irq_restore(flags);
- return 0;
-}
-
-static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
- void __iomem *base = ourchip->base;
- unsigned long flags;
- unsigned long dat;
- unsigned long con;
-
- local_irq_save(flags);
-
- dat = __raw_readl(base + 0x04);
- dat &= ~(1 << offset);
- if (value)
- dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
-
- con = __raw_readl(base + 0x00);
- con &= ~(3 << (offset * 2));
- con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
-
- __raw_writel(con, base + 0x00);
- __raw_writel(dat, base + 0x04);
-
- local_irq_restore(flags);
- return 0;
-}
-
-static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
- unsigned offset, int value)
-{
- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
- void __iomem *base = ourchip->base;
- unsigned long flags;
- unsigned long dat;
-
- local_irq_save(flags);
-
- dat = __raw_readl(base + 0x04);
- dat &= ~(1 << offset);
- if (value)
- dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
-
- local_irq_restore(flags);
-}
-
-static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
-{
- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
- unsigned long val;
-
- val = __raw_readl(ourchip->base + 0x04);
- val >>= offset;
- val &= 1;
-
- return val;
-}
-
static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
return -EINVAL;
@@ -125,7 +34,7 @@
static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
unsigned offset, int value)
{
- struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
@@ -151,9 +60,10 @@
return 0;
}
-static struct s3c24xx_gpio_chip gpios[] = {
+struct s3c_gpio_chip s3c24xx_gpios[] = {
[0] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
+ .pm = __gpio_pm(&s3c_gpio_pm_1bit),
.chip = {
.base = S3C2410_GPA0,
.owner = THIS_MODULE,
@@ -161,97 +71,87 @@
.ngpio = 24,
.direction_input = s3c24xx_gpiolib_banka_input,
.direction_output = s3c24xx_gpiolib_banka_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
},
},
[1] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPB0,
.owner = THIS_MODULE,
.label = "GPIOB",
.ngpio = 16,
- .direction_input = s3c24xx_gpiolib_input,
- .direction_output = s3c24xx_gpiolib_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
},
},
[2] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPC0,
.owner = THIS_MODULE,
.label = "GPIOC",
.ngpio = 16,
- .direction_input = s3c24xx_gpiolib_input,
- .direction_output = s3c24xx_gpiolib_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
},
},
[3] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPD0,
.owner = THIS_MODULE,
.label = "GPIOD",
.ngpio = 16,
- .direction_input = s3c24xx_gpiolib_input,
- .direction_output = s3c24xx_gpiolib_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
},
},
[4] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPE0,
.label = "GPIOE",
.owner = THIS_MODULE,
.ngpio = 16,
- .direction_input = s3c24xx_gpiolib_input,
- .direction_output = s3c24xx_gpiolib_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
},
},
[5] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPF0,
.owner = THIS_MODULE,
.label = "GPIOF",
.ngpio = 8,
- .direction_input = s3c24xx_gpiolib_input,
- .direction_output = s3c24xx_gpiolib_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
},
},
[6] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
.chip = {
.base = S3C2410_GPG0,
.owner = THIS_MODULE,
.label = "GPIOG",
- .ngpio = 10,
- .direction_input = s3c24xx_gpiolib_input,
- .direction_output = s3c24xx_gpiolib_output,
- .set = s3c24xx_gpiolib_set,
- .get = s3c24xx_gpiolib_get,
+ .ngpio = 16,
+ },
+ },
+ [7] = {
+ .base = S3C24XX_GPIO_BASE(S3C2410_GPH0),
+ .pm = __gpio_pm(&s3c_gpio_pm_2bit),
+ .chip = {
+ .base = S3C2410_GPH0,
+ .owner = THIS_MODULE,
+ .label = "GPIOH",
+ .ngpio = 11,
},
},
};
static __init int s3c24xx_gpiolib_init(void)
{
- struct s3c24xx_gpio_chip *chip = gpios;
+ struct s3c_gpio_chip *chip = s3c24xx_gpios;
int gpn;
- for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
- gpiochip_add(&chip->chip);
+ for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
+ s3c_gpiolib_add(chip);
return 0;
}
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/gta02_pm_wlan.c
@@ -0,0 +1,161 @@
+/*
+ * GTA02 WLAN power management
+ *
+ * (C) 2008 by Openmoko Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+
+#include <mach/gta02.h>
+#include <mach/gta02-pm-wlan.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+
+#include <linux/delay.h>
+
+
+static void __gta02_wlan_power(int on)
+{
+ if (!on) {
+ s3c2410_gpio_setpin(GTA02_CHIP_PWD, 1);
+ s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 0);
+ return;
+ }
+
+ /* power up sequencing */
+
+ s3c2410_gpio_setpin(GTA02_CHIP_PWD, 1);
+ s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 0);
+ msleep(100);
+ s3c2410_gpio_setpin(GTA02_CHIP_PWD, 0);
+ msleep(100);
+ s3c2410_gpio_setpin(GTA02_GPIO_nWLAN_RESET, 1);
+}
+
+void gta02_wlan_power(int on)
+{
+ static DEFINE_MUTEX(lock);
+ static int is_on = -1; /* initial state is unknown */
+
+ on = !!on; /* normalize */
+ mutex_lock(&lock);
+ if (on != is_on)
+ __gta02_wlan_power(on);
+ is_on = on;
+ mutex_unlock(&lock);
+}
+
+static ssize_t gta02_wlan_read(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ if (s3c2410_gpio_getpin(GTA02_CHIP_PWD))
+ return strlcpy(buf, "0\n", 3);
+
+ return strlcpy(buf, "1\n", 3);
+}
+
+static ssize_t gta02_wlan_write(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ unsigned long on = simple_strtoul(buf, NULL, 10) & 1;
+
+ gta02_wlan_power(on);
+ return count;
+}
+
+static DEVICE_ATTR(power_on, 0644, gta02_wlan_read, gta02_wlan_write);
+
+#ifdef CONFIG_PM
+static int gta02_wlan_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ dev_dbg(&pdev->dev, "suspending\n");
+
+ return 0;
+}
+
+static int gta02_wlan_resume(struct platform_device *pdev)
+{
+ dev_dbg(&pdev->dev, "resuming\n");
+
+ return 0;
+}
+#else
+#define gta02_wlan_suspend NULL
+#define gta02_wlan_resume NULL
+#endif
+
+static struct attribute *gta02_wlan_sysfs_entries[] = {
+ &dev_attr_power_on.attr,
+ NULL
+};
+
+static struct attribute_group gta02_wlan_attr_group = {
+ .name = NULL,
+ .attrs = gta02_wlan_sysfs_entries,
+};
+
+static int __init gta02_wlan_probe(struct platform_device *pdev)
+{
+ /* default-on for now */
+ const int default_state = 1;
+
+ if (!machine_is_neo1973_gta02())
+ return -EINVAL;
+
+ dev_info(&pdev->dev, "starting\n");
+
+ s3c2410_gpio_cfgpin(GTA02_CHIP_PWD, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(GTA02_GPIO_nWLAN_RESET, S3C2410_GPIO_OUTPUT);
+ gta02_wlan_power(default_state);
+
+ return sysfs_create_group(&pdev->dev.kobj, &gta02_wlan_attr_group);
+}
+
+static int gta02_wlan_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &gta02_wlan_attr_group);
+
+ return 0;
+}
+
+static struct platform_driver gta02_wlan_driver = {
+ .probe = gta02_wlan_probe,
+ .remove = gta02_wlan_remove,
+ .suspend = gta02_wlan_suspend,
+ .resume = gta02_wlan_resume,
+ .driver = {
+ .name = "gta02-pm-wlan",
+ },
+};
+
+static int __devinit gta02_wlan_init(void)
+{
+ return platform_driver_register(&gta02_wlan_driver);
+}
+
+static void gta02_wlan_exit(void)
+{
+ platform_driver_unregister(&gta02_wlan_driver);
+}
+
+module_init(gta02_wlan_init);
+module_exit(gta02_wlan_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Openmoko GTA02 WLAN power management");
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
@@ -0,0 +1,55 @@
+/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C24xx - pwm clock and timer support
+ */
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @cfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+ return tcfg == S3C2410_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+ return 1 << (1 + tcfg1);
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+ return 0;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+ return ilog2(div) - 1;
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
--- a/arch/arm/plat-s3c24xx/include/plat/clock.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/clock.h
- * linux/arch/arm/mach-s3c2410/clock.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * http://www.simtec.co.uk/products/SWLINUX/
- * Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct clk {
- struct list_head list;
- struct module *owner;
- struct clk *parent;
- const char *name;
- int id;
- int usage;
- unsigned long rate;
- unsigned long ctrlbit;
-
- int (*enable)(struct clk *, int enable);
- int (*set_rate)(struct clk *c, unsigned long rate);
- unsigned long (*get_rate)(struct clk *c);
- unsigned long (*round_rate)(struct clk *c, unsigned long rate);
- int (*set_parent)(struct clk *c, struct clk *parent);
-};
-
-/* other clocks which may be registered by board support */
-
-extern struct clk s3c24xx_dclk0;
-extern struct clk s3c24xx_dclk1;
-extern struct clk s3c24xx_clkout0;
-extern struct clk s3c24xx_clkout1;
-extern struct clk s3c24xx_uclk;
-
-extern struct clk clk_usb_bus;
-
-/* core clock support */
-
-extern struct clk clk_f;
-extern struct clk clk_h;
-extern struct clk clk_p;
-extern struct clk clk_mpll;
-extern struct clk clk_upll;
-extern struct clk clk_xtal;
-
-/* exports for arch/arm/mach-s3c2410
- *
- * Please DO NOT use these outside of arch/arm/mach-s3c2410
-*/
-
-extern struct mutex clocks_mutex;
-
-extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
-
-extern int s3c24xx_register_clock(struct clk *clk);
-extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
-
-extern int s3c24xx_setup_clocks(unsigned long xtal,
- unsigned long fclk,
- unsigned long hclk,
- unsigned long pclk);
--- a/arch/arm/plat-s3c24xx/include/plat/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/cpu.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* todo - fix when rmk changes iodescs to use `void __iomem *` */
-
-#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
-
-#ifndef MHZ
-#define MHZ (1000*1000)
-#endif
-
-#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
-
-/* forward declaration */
-struct s3c24xx_uart_resources;
-struct platform_device;
-struct s3c2410_uartcfg;
-struct map_desc;
-
-/* core initialisation functions */
-
-extern void s3c24xx_init_irq(void);
-
-extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-
-extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c24xx_init_clocks(int xtal);
-
-extern void s3c24xx_init_uartdevs(char *name,
- struct s3c24xx_uart_resources *res,
- struct s3c2410_uartcfg *cfg, int no);
-
-/* timer for 2410/2440 */
-
-struct sys_timer;
-extern struct sys_timer s3c24xx_timer;
-
-/* system device classes */
-
-extern struct sysdev_class s3c2410_sysclass;
-extern struct sysdev_class s3c2412_sysclass;
-extern struct sysdev_class s3c2440_sysclass;
-extern struct sysdev_class s3c2442_sysclass;
-extern struct sysdev_class s3c2443_sysclass;
--- a/arch/arm/plat-s3c24xx/include/plat/devs.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/devs.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 standard platform devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/platform_device.h>
-
-struct s3c24xx_uart_resources {
- struct resource *resources;
- unsigned long nr_resources;
-};
-
-extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
-
-extern struct platform_device *s3c24xx_uart_devs[];
-extern struct platform_device *s3c24xx_uart_src[];
-
-extern struct platform_device s3c_device_timer[];
-
-extern struct platform_device s3c_device_usb;
-extern struct platform_device s3c_device_lcd;
-extern struct platform_device s3c_device_wdt;
-extern struct platform_device s3c_device_i2c;
-extern struct platform_device s3c_device_iis;
-extern struct platform_device s3c_device_rtc;
-extern struct platform_device s3c_device_adc;
-extern struct platform_device s3c_device_sdi;
-extern struct platform_device s3c_device_hsmmc;
-
-extern struct platform_device s3c_device_spi0;
-extern struct platform_device s3c_device_spi1;
-
-extern struct platform_device s3c_device_nand;
-
-extern struct platform_device s3c_device_usbgadget;
-
-/* s3c2440 specific devices */
-
-#ifdef CONFIG_CPU_S3C2440
-
-extern struct platform_device s3c_device_camif;
-
-#endif
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
@@ -10,6 +10,12 @@
* published by the Free Software Foundation.
*/
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
+
#define irqdbf(x...)
#define irqdbf2(x...)
@@ -25,8 +31,15 @@
{
unsigned long mask;
unsigned long submask;
+#ifdef CONFIG_S3C2440_C_FIQ
+ unsigned long flags;
+#endif
submask = __raw_readl(S3C2410_INTSUBMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_save_flags(flags);
+ local_fiq_disable();
+#endif
mask = __raw_readl(S3C2410_INTMSK);
submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
@@ -39,6 +52,9 @@
/* write back masks */
__raw_writel(submask, S3C2410_INTSUBMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_irq_restore(flags);
+#endif
}
@@ -47,8 +63,15 @@
{
unsigned long mask;
unsigned long submask;
+#ifdef CONFIG_S3C2440_C_FIQ
+ unsigned long flags;
+#endif
submask = __raw_readl(S3C2410_INTSUBMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_save_flags(flags);
+ local_fiq_disable();
+#endif
mask = __raw_readl(S3C2410_INTMSK);
submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
@@ -57,6 +80,9 @@
/* write back masks */
__raw_writel(submask, S3C2410_INTSUBMSK);
__raw_writel(mask, S3C2410_INTMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_irq_restore(flags);
+#endif
}
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -0,0 +1,101 @@
+/* linux/include/asm-arm/plat-s3c24xx/map.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_S3C24XX_MAP_H
+#define __ASM_PLAT_S3C24XX_MAP_H
+
+/* interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C24XX_VA_IRQ S3C_VA_IRQ
+#define S3C2410_PA_IRQ (0x4A000000)
+#define S3C24XX_SZ_IRQ SZ_1M
+
+/* memory controller registers */
+#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
+#define S3C2410_PA_MEMCTRL (0x48000000)
+#define S3C24XX_SZ_MEMCTRL SZ_1M
+
+/* UARTs */
+#define S3C24XX_VA_UART S3C_VA_UART
+#define S3C2410_PA_UART (0x50000000)
+#define S3C24XX_SZ_UART SZ_1M
+#define S3C_UART_OFFSET (0x4000)
+
+#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
+
+/* Timers */
+#define S3C24XX_VA_TIMER S3C_VA_TIMER
+#define S3C2410_PA_TIMER (0x51000000)
+#define S3C24XX_SZ_TIMER SZ_1M
+
+/* Clock and Power management */
+#define S3C24XX_VA_CLKPWR S3C_VA_SYS
+#define S3C24XX_SZ_CLKPWR SZ_1M
+
+/* USB Device port */
+#define S3C2410_PA_USBDEV (0x52000000)
+#define S3C24XX_SZ_USBDEV SZ_1M
+
+/* Watchdog */
+#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
+#define S3C2410_PA_WATCHDOG (0x53000000)
+#define S3C24XX_SZ_WATCHDOG SZ_1M
+
+/* Standard size definitions for peripheral blocks. */
+
+#define S3C24XX_SZ_IIS SZ_1M
+#define S3C24XX_SZ_ADC SZ_1M
+#define S3C24XX_SZ_SPI SZ_1M
+#define S3C24XX_SZ_SDI SZ_1M
+#define S3C24XX_SZ_NAND SZ_1M
+#define S3C24XX_SZ_USBHOST SZ_1M
+
+/* GPIO ports */
+
+/* the calculation for the VA of this must ensure that
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 maping. This puts it (currently) at
+ * 0xFA800000, which is not in the way of any current mapping
+ * by the base system.
+*/
+
+#define S3C2410_PA_GPIO (0x56000000)
+#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+#define S3C24XX_SZ_GPIO SZ_1M
+
+
+/* ISA style IO, for each machine to sort out mappings for, if it
+ * implements it. We reserve two 16M regions for ISA.
+ */
+
+#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000)
+#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000)
+
+/* deal with the registers that move under the 2412/2413 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+
+#endif /* __ASM_PLAT_S3C24XX_MAP_H */
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -0,0 +1,15 @@
+#ifndef _ARCH_MCI_H
+#define _ARCH_MCI_H
+
+struct s3c24xx_mci_pdata {
+ unsigned int wprotect_invert : 1;
+ unsigned int detect_invert : 1; /* set => detect active high. */
+
+ unsigned int gpio_detect;
+ unsigned int gpio_wprotect;
+ unsigned long ocr_avail;
+ void (*set_power)(unsigned char power_mode,
+ unsigned short vdd);
+};
+
+#endif /* _ARCH_NCI_H */
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/pll.h
@@ -0,0 +1,37 @@
+/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C24xx - common pll registers and code
+ */
+
+#define S3C24XX_PLLCON_MDIVSHIFT 12
+#define S3C24XX_PLLCON_PDIVSHIFT 4
+#define S3C24XX_PLLCON_SDIVSHIFT 0
+#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
+#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
+#define S3C24XX_PLLCON_SDIVMASK 3
+
+#include <asm/div64.h>
+
+static inline unsigned int
+s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
+{
+ unsigned int mdiv, pdiv, sdiv;
+ uint64_t fvco;
+
+ mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
+ pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
+ sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
+
+ mdiv &= S3C24XX_PLLCON_MDIVMASK;
+ pdiv &= S3C24XX_PLLCON_PDIVMASK;
+ sdiv &= S3C24XX_PLLCON_SDIVMASK;
+
+ fvco = (uint64_t)baseclk * (mdiv + 8);
+ do_div(fvco, (pdiv + 2) << sdiv);
+
+ return (unsigned int)fvco;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h
@@ -0,0 +1,64 @@
+/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+ unsigned long tmp = __raw_readl(S3C2410_CLKCON);
+
+ /* re-start uart clocks */
+ tmp |= S3C2410_CLKCON_UART0;
+ tmp |= S3C2410_CLKCON_UART1;
+ tmp |= S3C2410_CLKCON_UART2;
+
+ __raw_writel(tmp, S3C2410_CLKCON);
+ udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+ __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
+ __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
+
+ /* ack any outstanding external interrupts before we go to sleep */
+
+ __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
+ __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
+ __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
+
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+ __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
+}
+
+static void s3c_pm_show_resume_irqs(int start, unsigned long which,
+ unsigned long mask);
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+ S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n",
+ __raw_readl(S3C2410_SRCPND),
+ __raw_readl(S3C2410_EINTPEND));
+
+ s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
+ s3c_irqwake_intmask);
+
+ s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
+ s3c_irqwake_eintmask);
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+ struct pm_uart_save *save)
+{
+}
--- a/arch/arm/plat-s3c24xx/include/plat/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/pm.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* s3c2410_pm_init
- *
- * called from board at initialisation time to setup the power
- * management
-*/
-
-#ifdef CONFIG_PM
-
-extern __init int s3c2410_pm_init(void);
-
-#else
-
-static inline int s3c2410_pm_init(void)
-{
- return 0;
-}
-#endif
-
-/* configuration for the IRQ mask over sleep */
-extern unsigned long s3c_irqwake_intmask;
-extern unsigned long s3c_irqwake_eintmask;
-
-/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
-extern unsigned long s3c_irqwake_intallow;
-extern unsigned long s3c_irqwake_eintallow;
-
-/* per-cpu sleep functions */
-
-extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
-
-/* Flags for PM Control */
-
-extern unsigned long s3c_pm_flags;
-
-/* from sleep.S */
-
-extern int s3c2410_cpu_save(unsigned long *saveblk);
-extern void s3c2410_cpu_suspend(void);
-extern void s3c2410_cpu_resume(void);
-
-extern unsigned long s3c2410_sleep_save_phys;
-
-/* sleep save info */
-
-struct sleep_save {
- void __iomem *reg;
- unsigned long val;
-};
-
-#define SAVE_ITEM(x) \
- { .reg = (x) }
-
-extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
-
-#ifdef CONFIG_PM
-extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
-extern int s3c24xx_irq_resume(struct sys_device *dev);
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume NULL
-#endif
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -0,0 +1,82 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
+ *
+ * Copyright (c) 2004 Fetron GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 SPI register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_SPI_H
+#define __ASM_ARCH_REGS_SPI_H
+
+#define S3C2410_SPI1 (0x20)
+#define S3C2412_SPI1 (0x100)
+
+#define S3C2410_SPCON (0x00)
+
+#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
+#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
+#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
+#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
+#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
+#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
+#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
+#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
+#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
+#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
+#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
+#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
+
+#define S3C2412_SPCON_DIRC_RX (1<<7)
+
+#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
+#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
+#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
+#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
+#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
+ 0: slave, 1: master */
+#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
+#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
+
+#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
+#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
+
+#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
+
+
+#define S3C2410_SPSTA (0x04)
+
+#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
+#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
+#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
+#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
+#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
+#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
+#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
+#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
+
+#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
+#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
+#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
+#define S3C2412_SPSTA_READY_ORG (1<<3)
+
+#define S3C2410_SPPIN (0x08)
+
+#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
+#define S3C2410_SPPIN_RESERVED (1<<1)
+#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
+#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
+
+#define S3C2410_SPPRE (0x0C)
+#define S3C2410_SPTDAT (0x10)
+#define S3C2410_SPRDAT (0x14)
+
+#define S3C2412_TXFIFO (0x18)
+#define S3C2412_RXFIFO (0x18)
+#define S3C2412_SPFIC (0x24)
+
+
+#endif /* __ASM_ARCH_REGS_SPI_H */
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
@@ -0,0 +1,153 @@
+/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
+ *
+ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+*/
+
+#ifndef __ASM_ARCH_REGS_UDC_H
+#define __ASM_ARCH_REGS_UDC_H
+
+#define S3C2410_USBDREG(x) (x)
+
+#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
+#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
+#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
+
+#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
+#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
+
+#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
+
+#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
+#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
+
+#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
+#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
+#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
+#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
+#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
+
+#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
+#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
+#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
+#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
+#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
+#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
+
+#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
+#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
+#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
+#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
+#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
+#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
+
+#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
+#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
+#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
+#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
+#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
+#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
+
+#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
+#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
+#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
+#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
+#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
+#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
+
+#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
+
+/* indexed registers */
+
+#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
+
+#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
+
+#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
+#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
+
+#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
+#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
+#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
+#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
+
+#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
+
+#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
+#define S3C2410_UDC_PWR_RESET (1<<3) // R
+#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
+#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
+#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
+
+#define S3C2410_UDC_PWR_DEFAULT 0x00
+
+#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
+#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
+#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
+#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
+#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
+#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
+#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
+#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
+#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
+#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
+#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
+
+#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
+#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
+
+
+#define S3C2410_UDC_INDEX_EP0 (0x00)
+#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
+#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
+#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
+#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
+
+#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
+#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
+#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
+#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
+
+#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
+#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
+#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
+#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
+
+#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
+#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
+#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
+#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
+#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
+#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
+#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
+
+#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
+#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
+#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
+#define S3C2410_UDC_EP0_CSR_DE (1<<3)
+#define S3C2410_UDC_EP0_CSR_SE (1<<4)
+#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
+#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
+#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
+
+#define S3C2410_UDC_MAXP_8 (1<<0)
+#define S3C2410_UDC_MAXP_16 (1<<1)
+#define S3C2410_UDC_MAXP_32 (1<<2)
+#define S3C2410_UDC_MAXP_64 (1<<3)
+
+
+#endif
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
@@ -17,7 +17,7 @@
extern int s3c2400_init(void);
-extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
+extern void s3c2400_map_io(void);
extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
@@ -15,7 +15,7 @@
extern int s3c2410_init(void);
-extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
+extern void s3c2410_map_io(void);
extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
@@ -14,7 +14,7 @@
extern int s3c2412_init(void);
-extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
+extern void s3c2412_map_io(void);
extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
@@ -16,7 +16,7 @@
extern int s3c2443_init(void);
-extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
+extern void s3c2443_map_io(void);
extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/udc.h
@@ -0,0 +1,36 @@
+/* arch/arm/mach-s3c2410/include/mach/udc.h
+ *
+ * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * Changelog:
+ * 14-Mar-2005 RTP Created file
+ * 02-Aug-2005 RTP File rename
+ * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
+ * 18-Jan-2007 HMW Add per-platform vbus_draw function
+*/
+
+#ifndef __ASM_ARM_ARCH_UDC_H
+#define __ASM_ARM_ARCH_UDC_H
+
+enum s3c2410_udc_cmd_e {
+ S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
+ S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
+ S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
+};
+
+struct s3c2410_udc_mach_info {
+ void (*udc_command)(enum s3c2410_udc_cmd_e);
+ void (*vbus_draw)(unsigned int ma);
+ unsigned int vbus_pin;
+ unsigned char vbus_pin_inverted;
+};
+
+extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
+
+#endif /* __ASM_ARM_ARCH_UDC_H */
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -1,6 +1,6 @@
/* linux/arch/arm/plat-s3c24xx/irq.c
*
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003,2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
@@ -16,38 +16,6 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Changelog:
- *
- * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
- * Fixed compile warnings
- *
- * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
- * Fixed s3c_extirq_type
- *
- * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
- * Addition of ADC/TC demux
- *
- * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
- * Fix for set_irq_type() on low EINT numbers
- *
- * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
- * Tidy up KF's patch and sort out new release
- *
- * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
- * Add support for power management controls
- *
- * 04-Nov-2004 Ben Dooks
- * Fix standard IRQ wake for EINT0..4 and RTC
- *
- * 22-Feb-2005 Ben Dooks
- * Fixed edge-triggering on ADC IRQ
- *
- * 28-Jun-2005 Ben Dooks
- * Mark IRQ_LCD valid
- *
- * 25-Jul-2005 Ben Dooks
- * Split the S3C2440 IRQ code to separate file
*/
#include <linux/init.h>
@@ -55,90 +23,34 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
-
#include <asm/mach/irq.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
+#include <plat/regs-irqtype.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>
-/* wakeup irq control */
-
-#ifdef CONFIG_PM
-
-/* state for IRQs over sleep */
-
-/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
- *
- * set bit to 1 in allow bitfield to enable the wakeup settings on it
-*/
-
-unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
-unsigned long s3c_irqwake_intmask = 0xffffffffL;
-unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
-unsigned long s3c_irqwake_eintmask = 0xffffffffL;
-
-int
-s3c_irq_wake(unsigned int irqno, unsigned int state)
-{
- unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
-
- if (!(s3c_irqwake_intallow & irqbit))
- return -ENOENT;
-
- printk(KERN_INFO "wake %s for irq %d\n",
- state ? "enabled" : "disabled", irqno);
-
- if (!state)
- s3c_irqwake_intmask |= irqbit;
- else
- s3c_irqwake_intmask &= ~irqbit;
-
- return 0;
-}
-
-static int
-s3c_irqext_wake(unsigned int irqno, unsigned int state)
-{
- unsigned long bit = 1L << (irqno - EXTINT_OFF);
-
- if (!(s3c_irqwake_eintallow & bit))
- return -ENOENT;
-
- printk(KERN_INFO "wake %s for irq %d\n",
- state ? "enabled" : "disabled", irqno);
-
- if (!state)
- s3c_irqwake_eintmask |= bit;
- else
- s3c_irqwake_eintmask &= ~bit;
-
- return 0;
-}
-
-#else
-#define s3c_irqext_wake NULL
-#define s3c_irq_wake NULL
-#endif
-
-
static void
s3c_irq_mask(unsigned int irqno)
{
unsigned long mask;
-
+#ifdef CONFIG_S3C2440_C_FIQ
+ unsigned long flags;
+#endif
irqno -= IRQ_EINT0;
-
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_save_flags(flags);
+ local_fiq_disable();
+#endif
mask = __raw_readl(S3C2410_INTMSK);
mask |= 1UL << irqno;
__raw_writel(mask, S3C2410_INTMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_irq_restore(flags);
+#endif
}
static inline void
@@ -155,9 +67,19 @@
{
unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
unsigned long mask;
+#ifdef CONFIG_S3C2440_C_FIQ
+ unsigned long flags;
+#endif
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_save_flags(flags);
+ local_fiq_disable();
+#endif
mask = __raw_readl(S3C2410_INTMSK);
__raw_writel(mask|bitval, S3C2410_INTMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_irq_restore(flags);
+#endif
__raw_writel(bitval, S3C2410_SRCPND);
__raw_writel(bitval, S3C2410_INTPND);
@@ -168,15 +90,25 @@
s3c_irq_unmask(unsigned int irqno)
{
unsigned long mask;
+#ifdef CONFIG_S3C2440_C_FIQ
+ unsigned long flags;
+#endif
if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
irqdbf2("s3c_irq_unmask %d\n", irqno);
irqno -= IRQ_EINT0;
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_save_flags(flags);
+ local_fiq_disable();
+#endif
mask = __raw_readl(S3C2410_INTMSK);
mask &= ~(1UL << irqno);
__raw_writel(mask, S3C2410_INTMSK);
+#ifdef CONFIG_S3C2440_C_FIQ
+ local_irq_restore(flags);
+#endif
}
struct irq_chip s3c_irq_level_chip = {
@@ -589,59 +521,6 @@
}
}
-#ifdef CONFIG_PM
-
-static struct sleep_save irq_save[] = {
- SAVE_ITEM(S3C2410_INTMSK),
- SAVE_ITEM(S3C2410_INTSUBMSK),
-};
-
-/* the extint values move between the s3c2410/s3c2440 and the s3c2412
- * so we use an array to hold them, and to calculate the address of
- * the register at run-time
-*/
-
-static unsigned long save_extint[3];
-static unsigned long save_eintflt[4];
-static unsigned long save_eintmask;
-
-int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(save_extint); i++)
- save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
-
- for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
- save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
-
- s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
- save_eintmask = __raw_readl(S3C24XX_EINTMASK);
-
- return 0;
-}
-
-int s3c24xx_irq_resume(struct sys_device *dev)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(save_extint); i++)
- __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
-
- for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
- __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
-
- s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
- __raw_writel(save_eintmask, S3C24XX_EINTMASK);
-
- return 0;
-}
-
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume NULL
-#endif
-
/* s3c24xx_init_irq
*
* Initialise S3C2410 IRQ system
@@ -672,26 +551,26 @@
last = 0;
for (i = 0; i < 4; i++) {
- pend = __raw_readl(S3C2410_INTPND);
+ pend = __raw_readl(S3C2410_SUBSRCPND);
if (pend == 0 || pend == last)
break;
- __raw_writel(pend, S3C2410_SRCPND);
- __raw_writel(pend, S3C2410_INTPND);
- printk("irq: clearing pending status %08x\n", (int)pend);
+ printk("irq: clearing subpending status %08x\n", (int)pend);
+ __raw_writel(pend, S3C2410_SUBSRCPND);
last = pend;
}
last = 0;
for (i = 0; i < 4; i++) {
- pend = __raw_readl(S3C2410_SUBSRCPND);
+ pend = __raw_readl(S3C2410_INTPND);
if (pend == 0 || pend == last)
break;
- printk("irq: clearing subpending status %08x\n", (int)pend);
- __raw_writel(pend, S3C2410_SUBSRCPND);
+ __raw_writel(pend, S3C2410_SRCPND);
+ __raw_writel(pend, S3C2410_INTPND);
+ printk("irq: clearing pending status %08x\n", (int)pend);
last = pend;
}
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -0,0 +1,118 @@
+/* linux/arch/arm/plat-s3c24xx/irq-om.c
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C24XX - IRQ PM code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+#include <linux/irq.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/irq.h>
+
+/* state for IRQs over sleep */
+
+/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
+ *
+ * set bit to 1 in allow bitfield to enable the wakeup settings on it
+*/
+
+unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
+unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
+
+int s3c_irq_wake(unsigned int irqno, unsigned int state)
+{
+ unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
+
+ if (!(s3c_irqwake_intallow & irqbit))
+ return -ENOENT;
+
+ printk(KERN_INFO "wake %s for irq %d\n",
+ state ? "enabled" : "disabled", irqno);
+
+ if (!state)
+ s3c_irqwake_intmask |= irqbit;
+ else
+ s3c_irqwake_intmask &= ~irqbit;
+
+ return 0;
+}
+
+static struct sleep_save irq_save[] = {
+ SAVE_ITEM(S3C2410_INTMSK),
+ SAVE_ITEM(S3C2410_INTSUBMSK),
+};
+
+/* the extint values move between the s3c2410/s3c2440 and the s3c2412
+ * so we use an array to hold them, and to calculate the address of
+ * the register at run-time
+*/
+
+static unsigned long save_extint[3];
+static unsigned long save_eintflt[4];
+static unsigned long save_eintmask;
+
+int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(save_extint); i++)
+ save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
+
+ for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
+ save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
+
+ s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+ save_eintmask = __raw_readl(S3C24XX_EINTMASK);
+
+ return 0;
+}
+
+int s3c24xx_irq_resume(struct sys_device *dev)
+{
+ unsigned int i, irq;
+ unsigned long eintpnd;
+ struct irq_desc *desc;
+
+ for (i = 0; i < ARRAY_SIZE(save_extint); i++)
+ __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
+
+ for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
+ __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
+
+ s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+ __raw_writel(save_eintmask, S3C24XX_EINTMASK);
+
+ /*
+ * ACK those interrupts which are now masked and pending.
+ * Level interrupts if not ACKed here, create an interrupt storm
+ * because they are not handled at all.
+ */
+
+ eintpnd = __raw_readl(S3C24XX_EINTPEND);
+
+ eintpnd &= save_eintmask;
+ eintpnd &= ~0xff; /* ignore lower irqs */
+
+ while (eintpnd) {
+ irq = __ffs(eintpnd);
+ eintpnd &= ~(1 << irq);
+
+ irq += (IRQ_EINT4 - 4);
+ desc = irq_to_desc(irq);
+ desc->chip->ack(irq);
+ }
+
+ return 0;
+}
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -6,18 +6,32 @@
config PLAT_S3C24XX
bool
- depends on ARCH_S3C2410
- default y if ARCH_S3C2410
+ depends on ARCH_S3C2410 || ARCH_S3C24A0
+ default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
+ select S3C_GPIO_TRACK
help
Base platform code for any Samsung S3C24XX device
if PLAT_S3C24XX
+# code that is shared between a number of the s3c24xx implementations
+
+config S3C2410_CLOCK
+ bool
+ help
+ Clock code for the S3C2410, and similar processors which
+ is currently includes the S3C2410, S3C2440, S3C2442.
+
+config S3C24XX_DCLK
+ bool
+ help
+ Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
+
config CPU_S3C244X
bool
- depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
+ default y if CPU_S3C2440 || CPU_S3C2442
help
Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
@@ -49,9 +63,31 @@
Enable debugging output for the DMA code. This option sends info
to the kernel log, at priority KERN_DEBUG.
+# SPI default pin configuration code
+
+config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
+ bool
+ help
+ SPI GPIO configuration code for BUS0 when connected to
+ GPE11, GPE12 and GPE13.
+
+config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
+ bool
+ help
+ SPI GPIO configuration code for BUS 1 when connected to
+ GPG5, GPG6 and GPG7.
+
+# common code for s3c24xx based machines, such as the SMDKs.
+
config MACH_SMDK
bool
help
Common machine code for SMDK2410 and SMDK2440
+config MACH_NEO1973
+ bool
+ select RFKILL
+ help
+ Common machine code for Neo1973 hardware
+
endif
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -17,9 +17,8 @@
obj-y += devs.o
obj-y += gpio.o
obj-y += gpiolib.o
-obj-y += time.o
obj-y += clock.o
-obj-y += pwm-clock.o
+obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
# Architecture dependant builds
@@ -28,7 +27,26 @@
obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_PM) += sleep.o
obj-$(CONFIG_HAVE_PWM) += pwm.o
+obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C2410_DMA) += dma.o
+
+# device specific setup and/or initialisation
+obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
+
+# SPI gpio central GPIO functions
+
+obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
+obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o
+
+# machine common support
+
obj-$(CONFIG_MACH_SMDK) += common-smdk.o
+obj-$(CONFIG_MACH_NEO1973) += \
+ neo1973_pm_gsm.o \
+ neo1973_pm_gps.o \
+ neo1973_pm_bt.o \
+ gta02_pm_wlan.o \
+ neo1973_shadow.o
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/neo1973_pm_bt.c
@@ -0,0 +1,323 @@
+/*
+ * Bluetooth PM code for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2007 by Openmoko Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/rfkill.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+
+/* For GTA01 */
+#include <mach/gta01.h>
+#include <linux/pcf50606.h>
+
+/* For GTA02 */
+#include <mach/gta02.h>
+#include <linux/mfd/pcf50633/gpio.h>
+
+#include <linux/regulator/consumer.h>
+
+#define DRVMSG "FIC Neo1973 Bluetooth Power Management"
+
+struct gta01_pm_bt_data {
+ struct regulator *regulator;
+ struct rfkill *rfkill;
+ int pre_resume_state;
+};
+
+static ssize_t bt_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int ret = 0;
+
+ if (!strcmp(attr->attr.name, "power_on")) {
+
+ if (machine_is_neo1973_gta01()) {
+ if (pcf50606_onoff_get(pcf50606_global,
+ PCF50606_REGULATOR_D1REG) &&
+ pcf50606_voltage_get(pcf50606_global,
+ PCF50606_REGULATOR_D1REG) == 3100)
+ ret = 1;
+ } else if (machine_is_neo1973_gta02()) {
+ if (s3c2410_gpio_getpin(GTA02_GPIO_BT_EN))
+ ret = 1;
+ }
+ } else if (!strcmp(attr->attr.name, "reset")) {
+ if (machine_is_neo1973_gta01()) {
+ if (s3c2410_gpio_getpin(GTA01_GPIO_BT_EN) == 0)
+ ret = 1;
+ } else if (machine_is_neo1973_gta02()) {
+ if (s3c2410_gpio_getpin(GTA02_GPIO_BT_EN) == 0)
+ ret = 1;
+ }
+ }
+
+ if (!ret) {
+ return strlcpy(buf, "0\n", 3);
+ } else {
+ return strlcpy(buf, "1\n", 3);
+ }
+}
+
+static void __gta02_pm_bt_toggle_radio(struct device *dev, unsigned int on)
+{
+ struct gta01_pm_bt_data *bt_data = dev_get_drvdata(dev);
+
+ dev_info(dev, "__gta02_pm_bt_toggle_radio %d\n", on);
+
+ if (machine_is_neo1973_gta02()) {
+
+ bt_data = dev_get_drvdata(dev);
+
+ neo1973_gpb_setpin(GTA02_GPIO_BT_EN, !on);
+
+ if (on) {
+ if (!regulator_is_enabled(bt_data->regulator))
+ regulator_enable(bt_data->regulator);
+ } else {
+ if (regulator_is_enabled(bt_data->regulator))
+ regulator_disable(bt_data->regulator);
+ }
+
+ neo1973_gpb_setpin(GTA02_GPIO_BT_EN, on);
+ }
+}
+
+
+static int bt_rfkill_toggle_radio(void *data, enum rfkill_state state)
+{
+ struct device *dev = data;
+ unsigned long on = (state == RFKILL_STATE_ON);
+
+ if (machine_is_neo1973_gta01()) {
+ /* if we are powering up, assert reset, then power,
+ * then release reset */
+ if (on) {
+ neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG,
+ 3100);
+ }
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG, on);
+ neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on);
+ } else if (machine_is_neo1973_gta02())
+ __gta02_pm_bt_toggle_radio(dev, on);
+
+ return 0;
+}
+
+static ssize_t bt_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long on = simple_strtoul(buf, NULL, 10);
+ struct gta01_pm_bt_data *bt_data = dev_get_drvdata(dev);
+
+ if (!strcmp(attr->attr.name, "power_on")) {
+ enum rfkill_state state = on ? RFKILL_STATE_ON : RFKILL_STATE_OFF;
+ bt_rfkill_toggle_radio(dev, state);
+ bt_data->rfkill->state = state;
+
+ if (machine_is_neo1973_gta01()) {
+ /* if we are powering up, assert reset, then power,
+ * then release reset */
+ if (on) {
+ neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG,
+ 3100);
+ }
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG, on);
+ neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on);
+ } else if (machine_is_neo1973_gta02())
+ __gta02_pm_bt_toggle_radio(dev, on);
+
+ } else if (!strcmp(attr->attr.name, "reset")) {
+ /* reset is low-active, so we need to invert */
+ if (machine_is_neo1973_gta01()) {
+ neo1973_gpb_setpin(GTA01_GPIO_BT_EN, on ? 0 : 1);
+ } else if (machine_is_neo1973_gta02()) {
+ neo1973_gpb_setpin(GTA02_GPIO_BT_EN, on ? 0 : 1);
+ }
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR(power_on, 0644, bt_read, bt_write);
+static DEVICE_ATTR(reset, 0644, bt_read, bt_write);
+
+#ifdef CONFIG_PM
+static int gta01_bt_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
+
+ dev_dbg(&pdev->dev, DRVMSG ": suspending\n");
+
+ if (machine_is_neo1973_gta02()) {
+ bt_data->pre_resume_state =
+ s3c2410_gpio_getpin(GTA02_GPIO_BT_EN);
+ __gta02_pm_bt_toggle_radio(&pdev->dev, 0);
+ }
+
+ return 0;
+}
+
+static int gta01_bt_resume(struct platform_device *pdev)
+{
+ struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
+ dev_dbg(&pdev->dev, DRVMSG ": resuming\n");
+
+ if (machine_is_neo1973_gta02()) {
+ __gta02_pm_bt_toggle_radio(&pdev->dev,
+ bt_data->pre_resume_state);
+ }
+
+ return 0;
+}
+#else
+#define gta01_bt_suspend NULL
+#define gta01_bt_resume NULL
+#endif
+
+static struct attribute *gta01_bt_sysfs_entries[] = {
+ &dev_attr_power_on.attr,
+ &dev_attr_reset.attr,
+ NULL
+};
+
+static struct attribute_group gta01_bt_attr_group = {
+ .name = NULL,
+ .attrs = gta01_bt_sysfs_entries,
+};
+
+static int __init gta01_bt_probe(struct platform_device *pdev)
+{
+ struct rfkill *rfkill;
+ struct regulator *regulator;
+ struct gta01_pm_bt_data *bt_data;
+ int ret;
+
+ dev_info(&pdev->dev, DRVMSG ": starting\n");
+
+ bt_data = kzalloc(sizeof(*bt_data), GFP_KERNEL);
+ dev_set_drvdata(&pdev->dev, bt_data);
+
+ if (machine_is_neo1973_gta01()) {
+ /* we make sure that the voltage is off */
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG, 0);
+ /* we pull reset to low to make sure that the chip doesn't
+ * drain power through the reset line */
+ neo1973_gpb_setpin(GTA01_GPIO_BT_EN, 0);
+ } else if (machine_is_neo1973_gta02()) {
+ regulator = regulator_get(&pdev->dev, "BT_3V2");
+ if (IS_ERR(regulator))
+ return -ENODEV;
+
+ bt_data->regulator = regulator;
+
+ /* this tests the true physical state of the regulator... */
+ if (regulator_is_enabled(regulator)) {
+ /*
+ * but these only operate on the logical state of the
+ * regulator... so we need to logicaly "adopt" it on
+ * to turn it off
+ */
+ regulator_enable(regulator);
+ regulator_disable(regulator);
+ }
+
+ /* we pull reset to low to make sure that the chip doesn't
+ * drain power through the reset line */
+ neo1973_gpb_setpin(GTA02_GPIO_BT_EN, 0);
+ }
+
+ rfkill = rfkill_allocate(&pdev->dev, RFKILL_TYPE_BLUETOOTH);
+
+ rfkill->name = pdev->name;
+ rfkill->data = &pdev->dev;
+ rfkill->state = RFKILL_STATE_OFF;
+ rfkill->toggle_radio = bt_rfkill_toggle_radio;
+
+ ret = rfkill_register(rfkill);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register rfkill\n");
+ return ret;
+ }
+
+ bt_data->rfkill = rfkill;
+
+ return sysfs_create_group(&pdev->dev.kobj, &gta01_bt_attr_group);
+}
+
+static int gta01_bt_remove(struct platform_device *pdev)
+{
+ struct gta01_pm_bt_data *bt_data = dev_get_drvdata(&pdev->dev);
+ struct regulator *regulator;
+
+ sysfs_remove_group(&pdev->dev.kobj, &gta01_bt_attr_group);
+
+ if (bt_data->rfkill) {
+ rfkill_unregister(bt_data->rfkill);
+ rfkill_free(bt_data->rfkill);
+ }
+
+ if (!bt_data || !bt_data->regulator)
+ return 0;
+
+ regulator = bt_data->regulator;
+
+ /* Make sure regulator is disabled before calling regulator_put */
+ if (regulator_is_enabled(regulator))
+ regulator_disable(regulator);
+
+ regulator_put(regulator);
+
+ kfree(bt_data);
+
+ return 0;
+}
+
+static struct platform_driver gta01_bt_driver = {
+ .probe = gta01_bt_probe,
+ .remove = gta01_bt_remove,
+ .suspend = gta01_bt_suspend,
+ .resume = gta01_bt_resume,
+ .driver = {
+ .name = "neo1973-pm-bt",
+ },
+};
+
+static int __devinit gta01_bt_init(void)
+{
+ return platform_driver_register(&gta01_bt_driver);
+}
+
+static void gta01_bt_exit(void)
+{
+ platform_driver_unregister(&gta01_bt_driver);
+}
+
+module_init(gta01_bt_init);
+module_exit(gta01_bt_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION(DRVMSG);
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/neo1973_pm_gps.c
@@ -0,0 +1,699 @@
+/*
+ * GPS Power Management code for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2007 by Openmoko Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+
+#include <asm/mach-types.h>
+
+#include <asm/plat-s3c24xx/neo1973.h>
+
+/* For GTA01 */
+#include <mach/gta01.h>
+#include <linux/pcf50606.h>
+
+/* For GTA02 */
+#include <mach/gta02.h>
+
+#include <linux/regulator/consumer.h>
+
+struct neo1973_pm_gps_data {
+ int power_was_on;
+ struct regulator *regulator;
+};
+
+static struct neo1973_pm_gps_data neo1973_gps;
+
+int neo1973_pm_gps_is_on(void)
+{
+ return neo1973_gps.power_was_on;
+}
+EXPORT_SYMBOL_GPL(neo1973_pm_gps_is_on);
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+
+/* This is the 2.8V supply for the RTC crystal, the mail clock crystal and
+ * the input to VDD_RF */
+static void gps_power_2v8_set(int on)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ if (on)
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_IOREG, 2800);
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_IOREG, on);
+ break;
+ case GTA01Bv2_SYSTEM_REV:
+ s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_2V8, on);
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ break;
+ }
+}
+
+static int gps_power_2v8_get(void)
+{
+ int ret = 0;
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ if (pcf50606_onoff_get(pcf50606_global,
+ PCF50606_REGULATOR_IOREG) &&
+ pcf50606_voltage_get(pcf50606_global,
+ PCF50606_REGULATOR_IOREG) == 2800)
+ ret = 1;
+ break;
+ case GTA01Bv2_SYSTEM_REV:
+ if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_2V8))
+ ret = 1;
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ break;
+ }
+
+ return ret;
+}
+
+/* This is the 3V supply (AVDD) for the external RF frontend (LNA bias) */
+static void gps_power_3v_set(int on)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ if (on)
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG, 3000);
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D1REG, on);
+ break;
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_3V, on);
+ break;
+ }
+}
+
+static int gps_power_3v_get(void)
+{
+ int ret = 0;
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ if (pcf50606_onoff_get(pcf50606_global,
+ PCF50606_REGULATOR_D1REG) &&
+ pcf50606_voltage_get(pcf50606_global,
+ PCF50606_REGULATOR_D1REG) == 3000)
+ ret = 1;
+ break;
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_3V))
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+/* This is the 3.3V supply for VDD_IO and VDD_LPREG input */
+static void gps_power_3v3_set(int on)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ if (on)
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_DCD, 3300);
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_DCD, on);
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ s3c2410_gpio_setpin(GTA01_GPIO_GPS_EN_3V3, on);
+ break;
+ }
+}
+
+static int gps_power_3v3_get(void)
+{
+ int ret = 0;
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ if (pcf50606_onoff_get(pcf50606_global,
+ PCF50606_REGULATOR_DCD) &&
+ pcf50606_voltage_get(pcf50606_global,
+ PCF50606_REGULATOR_DCD) == 3300)
+ ret = 1;
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_EN_3V3))
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+/* This is the 2.5V supply for VDD_PLLREG and VDD_COREREG input */
+static void gps_power_2v5_set(int on)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ /* This is CORE_1V8 and cannot be disabled */
+ break;
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (on)
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_D2REG, 2500);
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_D2REG, on);
+ break;
+ }
+}
+
+static int gps_power_2v5_get(void)
+{
+ int ret = 0;
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ /* This is CORE_1V8 and cannot be disabled */
+ ret = 1;
+ break;
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (pcf50606_onoff_get(pcf50606_global,
+ PCF50606_REGULATOR_D2REG) &&
+ pcf50606_voltage_get(pcf50606_global,
+ PCF50606_REGULATOR_D2REG) == 2500)
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+
+/* This is the 1.5V supply for VDD_CORE */
+static void gps_power_1v5_set(int on)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ /* This is switched via 2v5 */
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (on)
+ pcf50606_voltage_set(pcf50606_global,
+ PCF50606_REGULATOR_DCD, 1500);
+ pcf50606_onoff_set(pcf50606_global,
+ PCF50606_REGULATOR_DCD, on);
+ break;
+ }
+}
+
+static int gps_power_1v5_get(void)
+{
+ int ret = 0;
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ /* This is switched via 2v5 */
+ ret = 1;
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (pcf50606_onoff_get(pcf50606_global,
+ PCF50606_REGULATOR_DCD) &&
+ pcf50606_voltage_get(pcf50606_global,
+ PCF50606_REGULATOR_DCD) == 1500)
+ ret = 1;
+ break;
+ }
+
+ return ret;
+}
+#endif
+
+/* This is the POWERON pin */
+static void gps_pwron_set(int on)
+{
+
+ if (machine_is_neo1973_gta01())
+ neo1973_gpb_setpin(GTA01_GPIO_GPS_PWRON, on);
+
+ if (machine_is_neo1973_gta02()) {
+ if (on) {
+ /* return UART pins to being UART pins */
+ s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_TXD1);
+ /* remove pulldown now it won't be floating any more */
+ s3c2410_gpio_pullup(S3C2410_GPH5, 0);
+ } else {
+ /*
+ * take care not to power unpowered GPS from UART TX
+ * return them to GPIO and force low
+ */
+ s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_OUTP);
+ s3c2410_gpio_setpin(S3C2410_GPH4, 0);
+ /* don't let RX from unpowered GPS float */
+ s3c2410_gpio_pullup(S3C2410_GPH5, 1);
+ }
+ if ((on) && (!neo1973_gps.power_was_on))
+ regulator_enable(neo1973_gps.regulator);
+
+ if ((!on) && (neo1973_gps.power_was_on))
+ regulator_disable(neo1973_gps.regulator);
+ }
+
+ neo1973_gps.power_was_on = !!on;
+}
+
+static int gps_pwron_get(void)
+{
+ if (machine_is_neo1973_gta01())
+ return !!s3c2410_gpio_getpin(GTA01_GPIO_GPS_PWRON);
+
+ if (machine_is_neo1973_gta02())
+ return regulator_is_enabled(neo1973_gps.regulator);
+ return -1;
+}
+
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+static void gps_rst_set(int on);
+static int gps_rst_get(void);
+#endif
+
+static ssize_t power_gps_read(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int ret = 0;
+
+ if (!strcmp(attr->attr.name, "pwron"))
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ {
+#endif
+ ret = gps_pwron_get();
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ } else if (!strcmp(attr->attr.name, "power_avdd_3v")) {
+ ret = gps_power_3v_get();
+ } else if (!strcmp(attr->attr.name, "power_tcxo_2v8")) {
+ ret = gps_power_2v8_get();
+ } else if (!strcmp(attr->attr.name, "reset")) {
+ ret = gps_rst_get();
+ } else if (!strcmp(attr->attr.name, "power_lp_io_3v3")) {
+ ret = gps_power_3v3_get();
+ } else if (!strcmp(attr->attr.name, "power_pll_core_2v5")) {
+ ret = gps_power_2v5_get();
+ } else if (!strcmp(attr->attr.name, "power_core_1v5") ||
+ !strcmp(attr->attr.name, "power_vdd_core_1v5")) {
+ ret = gps_power_1v5_get();
+ }
+#endif
+ if (ret)
+ return strlcpy(buf, "1\n", 3);
+ else
+ return strlcpy(buf, "0\n", 3);
+}
+
+static ssize_t power_gps_write(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t count)
+{
+ unsigned long on = simple_strtoul(buf, NULL, 10);
+
+ if (!strcmp(attr->attr.name, "pwron"))
+#ifdef CONFIG_MACH_NEO1973_GTA01
+{
+#endif
+ gps_pwron_set(on);
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ } else if (!strcmp(attr->attr.name, "power_avdd_3v")) {
+ gps_power_3v_set(on);
+ } else if (!strcmp(attr->attr.name, "power_tcxo_2v8")) {
+ gps_power_2v8_set(on);
+ } else if (!strcmp(attr->attr.name, "reset")) {
+ gps_rst_set(on);
+ } else if (!strcmp(attr->attr.name, "power_lp_io_3v3")) {
+ gps_power_3v3_set(on);
+ } else if (!strcmp(attr->attr.name, "power_pll_core_2v5")) {
+ gps_power_2v5_set(on);
+ } else if (!strcmp(attr->attr.name, "power_core_1v5") ||
+ !strcmp(attr->attr.name, "power_vdd_core_1v5")) {
+ gps_power_1v5_set(on);
+ }
+#endif
+ return count;
+}
+
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+
+/* This is the nRESET pin */
+static void gps_rst_set(int on)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ pcf50606_gpo0_set(pcf50606_global, on);
+ break;
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ s3c2410_gpio_setpin(GTA01_GPIO_GPS_RESET, on);
+ break;
+ }
+}
+
+static int gps_rst_get(void)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ if (pcf50606_gpo0_get(pcf50606_global))
+ return 1;
+ break;
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ if (s3c2410_gpio_getpin(GTA01_GPIO_GPS_RESET))
+ return 1;
+ break;
+ }
+
+ return 0;
+}
+
+
+static void gps_power_sequence_up(void)
+{
+ /* According to PMB2520 Data Sheet, Rev. 2006-06-05,
+ * Chapter 4.2.2 */
+
+ /* nRESET must be asserted low */
+ gps_rst_set(0);
+
+ /* POWERON must be de-asserted (low) */
+ gps_pwron_set(0);
+
+ /* Apply VDD_IO and VDD_LPREG_IN */
+ gps_power_3v3_set(1);
+
+ /* VDD_COREREG_IN, VDD_PLLREG_IN */
+ gps_power_1v5_set(1);
+ gps_power_2v5_set(1);
+
+ /* and VDD_RF may be applied */
+ gps_power_2v8_set(1);
+
+ /* We need to enable AVDD, since in GTA01Bv3 it is
+ * shared with RFREG_IN */
+ gps_power_3v_set(1);
+
+ msleep(3); /* Is 3ms enough? */
+
+ /* De-asert nRESET */
+ gps_rst_set(1);
+
+ /* Switch power on */
+ gps_pwron_set(1);
+
+}
+
+static void gps_power_sequence_down(void)
+{
+ /* According to PMB2520 Data Sheet, Rev. 2006-06-05,
+ * Chapter 4.2.3.1 */
+ gps_pwron_set(0);
+
+ /* Don't disable AVDD before PWRON is cleared, since
+ * in GTA01Bv3, AVDD and RFREG_IN are shared */
+ gps_power_3v_set(0);
+
+ /* Remove VDD_COREREG_IN, VDD_PLLREG_IN and VDD_REFREG_IN */
+ gps_power_1v5_set(0);
+ gps_power_2v5_set(0);
+ gps_power_2v8_set(0);
+
+ /* Remove VDD_LPREG_IN and VDD_IO */
+ gps_power_3v3_set(0);
+}
+
+
+static ssize_t power_sequence_read(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return strlcpy(buf, "power_up power_down\n", PAGE_SIZE);
+}
+
+static ssize_t power_sequence_write(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ dev_dbg(dev, "wrote: '%s'\n", buf);
+
+ if (!strncmp(buf, "power_up", 8))
+ gps_power_sequence_up();
+ else if (!strncmp(buf, "power_down", 10))
+ gps_power_sequence_down();
+ else
+ return -EINVAL;
+
+ return count;
+}
+
+static DEVICE_ATTR(power_tcxo_2v8, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(power_avdd_3v, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(reset, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(power_lp_io_3v3, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(power_pll_core_2v5, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(power_core_1v5, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(power_vdd_core_1v5, 0644, power_gps_read, power_gps_write);
+static DEVICE_ATTR(power_sequence, 0644, power_sequence_read,
+ power_sequence_write);
+#endif
+
+#ifdef CONFIG_PM
+static int gta01_pm_gps_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ if (machine_is_neo1973_gta01())
+ /* FIXME */
+ gps_power_sequence_down();
+#endif
+ if (machine_is_neo1973_gta02())
+ gps_pwron_set(0);
+
+ return 0;
+}
+
+static int gta01_pm_gps_resume(struct platform_device *pdev)
+{
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ if (machine_is_neo1973_gta01())
+ if (neo1973_gps.power_was_on)
+ gps_power_sequence_up();
+#endif
+ if (machine_is_neo1973_gta02())
+ if (neo1973_gps.power_was_on)
+ gps_pwron_set(1);
+
+ return 0;
+}
+#else
+#define gta01_pm_gps_suspend NULL
+#define gta01_pm_gps_resume NULL
+#endif
+
+static DEVICE_ATTR(pwron, 0644, power_gps_read, power_gps_write);
+
+
+static struct attribute *gta01_gps_sysfs_entries[] = {
+ &dev_attr_pwron.attr,
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ &dev_attr_power_avdd_3v.attr,
+ &dev_attr_reset.attr,
+ &dev_attr_power_lp_io_3v3.attr,
+ &dev_attr_power_pll_core_2v5.attr,
+ &dev_attr_power_sequence.attr,
+ NULL, /* power_core_1v5 */
+ NULL, /* power_vdd_core_1v5 */
+#endif
+ NULL /* terminating entry */
+};
+
+static struct attribute_group gta01_gps_attr_group = {
+ .name = NULL,
+ .attrs = gta01_gps_sysfs_entries,
+};
+
+static struct attribute *gta02_gps_sysfs_entries[] = {
+ &dev_attr_pwron.attr,
+ NULL
+};
+
+static struct attribute_group gta02_gps_attr_group = {
+ .name = NULL,
+ .attrs = gta02_gps_sysfs_entries,
+};
+
+static int __init gta01_pm_gps_probe(struct platform_device *pdev)
+{
+ if (machine_is_neo1973_gta01()) {
+ s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_PWRON, S3C2410_GPIO_OUTPUT);
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ break;
+ case GTA01v4_SYSTEM_REV:
+ s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_RESET, S3C2410_GPIO_OUTPUT);
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_3V3, S3C2410_GPIO_OUTPUT);
+ /* fallthrough */
+ case GTA01Bv2_SYSTEM_REV:
+ s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_2V8, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_EN_3V, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(GTA01_GPIO_GPS_RESET, S3C2410_GPIO_OUTPUT);
+ break;
+ default:
+ dev_warn(&pdev->dev, "Unknown GTA01 Revision 0x%x, "
+ "AGPS PM features not available!!!\n",
+ system_rev);
+ return -1;
+ break;
+ }
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ gps_power_sequence_down();
+
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-3] =
+ &dev_attr_power_tcxo_2v8.attr;
+ break;
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-3] =
+ &dev_attr_power_core_1v5.attr;
+ gta01_gps_sysfs_entries[ARRAY_SIZE(gta01_gps_sysfs_entries)-2] =
+ &dev_attr_power_vdd_core_1v5.attr;
+ break;
+ }
+#endif
+ return sysfs_create_group(&pdev->dev.kobj, &gta01_gps_attr_group);
+ }
+
+ if (machine_is_neo1973_gta02()) {
+ switch (system_rev) {
+ case GTA02v2_SYSTEM_REV:
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ neo1973_gps.regulator = regulator_get(
+ &pdev->dev, "RF_3V");
+ if (IS_ERR(neo1973_gps.regulator)) {
+ dev_err(&pdev->dev, "probe failed %d\n",
+ (int)neo1973_gps.regulator);
+ return (int)neo1973_gps.regulator;
+ }
+
+ dev_info(&pdev->dev, "FIC Neo1973 GPS Power Management:"
+ "starting\n");
+ break;
+ default:
+ dev_warn(&pdev->dev, "Unknown GTA02 Revision 0x%x, "
+ "AGPS PM features not available!!!\n",
+ system_rev);
+ return -1;
+ break;
+ }
+ return sysfs_create_group(&pdev->dev.kobj, &gta02_gps_attr_group);
+ }
+ return -1;
+}
+
+static int gta01_pm_gps_remove(struct platform_device *pdev)
+{
+ if (machine_is_neo1973_gta01()) {
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ gps_power_sequence_down();
+#endif
+ sysfs_remove_group(&pdev->dev.kobj, &gta01_gps_attr_group);
+ }
+
+ if (machine_is_neo1973_gta02()) {
+ regulator_put(neo1973_gps.regulator);
+ sysfs_remove_group(&pdev->dev.kobj, &gta02_gps_attr_group);
+ }
+ return 0;
+}
+
+static struct platform_driver gta01_pm_gps_driver = {
+ .probe = gta01_pm_gps_probe,
+ .remove = gta01_pm_gps_remove,
+ .suspend = gta01_pm_gps_suspend,
+ .resume = gta01_pm_gps_resume,
+ .driver = {
+ .name = "neo1973-pm-gps",
+ },
+};
+
+static int __devinit gta01_pm_gps_init(void)
+{
+ return platform_driver_register(&gta01_pm_gps_driver);
+}
+
+static void gta01_pm_gps_exit(void)
+{
+ platform_driver_unregister(&gta01_pm_gps_driver);
+}
+
+module_init(gta01_pm_gps_init);
+module_exit(gta01_pm_gps_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("FIC Neo1973 GPS Power Management");
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/neo1973_pm_gps.h
@@ -0,0 +1 @@
+extern int neo1973_pm_gps_is_on(void);
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/neo1973_pm_gsm.c
@@ -0,0 +1,360 @@
+/*
+ * GSM Management code for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2007 by Openmoko Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/console.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+
+#include <mach/gpio.h>
+#include <asm/mach-types.h>
+#include <mach/gta01.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+#include <mach/s3c24xx-serial.h>
+
+#include <mach/hardware.h>
+
+/* For GTA02 */
+#include <mach/gta02.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-gpioj.h>
+
+int gta_gsm_interrupts;
+EXPORT_SYMBOL(gta_gsm_interrupts);
+
+extern void s3c24xx_serial_console_set_silence(int);
+
+struct gta01pm_priv {
+ int gpio_ngsm_en;
+ int gpio_ndl_gsm;
+
+ struct console *con;
+};
+
+static struct gta01pm_priv gta01_gsm;
+
+static struct console *find_s3c24xx_console(void)
+{
+ struct console *con;
+
+ acquire_console_sem();
+
+ for (con = console_drivers; con; con = con->next) {
+ if (!strcmp(con->name, "ttySAC"))
+ break;
+ }
+
+ release_console_sem();
+
+ return con;
+}
+
+static ssize_t gsm_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ if (!strcmp(attr->attr.name, "power_on")) {
+ if (s3c2410_gpio_getpin(GTA01_GPIO_MODEM_ON))
+ goto out_1;
+ } else if (!strcmp(attr->attr.name, "reset")) {
+ if (machine_is_neo1973_gta01() && s3c2410_gpio_getpin(GTA01_GPIO_MODEM_RST))
+ goto out_1;
+ else if (machine_is_neo1973_gta02() && s3c2410_gpio_getpin(GTA02_GPIO_MODEM_RST))
+ goto out_1;
+ } else if (!strcmp(attr->attr.name, "download")) {
+ if (machine_is_neo1973_gta01()) {
+ if (s3c2410_gpio_getpin(GTA01_GPIO_MODEM_DNLOAD))
+ goto out_1;
+ } else if (machine_is_neo1973_gta02()) {
+ if (!s3c2410_gpio_getpin(GTA02_GPIO_nDL_GSM))
+ goto out_1;
+ }
+ } else if (!strcmp(attr->attr.name, "flowcontrolled")) {
+ if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT)
+ goto out_1;
+ }
+
+ return strlcpy(buf, "0\n", 3);
+out_1:
+ return strlcpy(buf, "1\n", 3);
+}
+
+static ssize_t gsm_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long on = simple_strtoul(buf, NULL, 10);
+
+ if (!strcmp(attr->attr.name, "power_on")) {
+ if (on) {
+ if (gta01_gsm.con) {
+ dev_dbg(dev, "powering up GSM, thus "
+ "disconnecting serial console\n");
+
+ console_stop(gta01_gsm.con);
+ s3c24xx_serial_console_set_silence(1);
+ }
+
+ if (gta01_gsm.gpio_ngsm_en)
+ s3c2410_gpio_setpin(gta01_gsm.gpio_ngsm_en, 0);
+
+ if (machine_is_neo1973_gta02()) {
+ switch (system_rev) {
+ case GTA02v2_SYSTEM_REV:
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ pcf50633_gpio_set(gta02_pcf_pdata.pcf,
+ PCF50633_GPIO2, 1);
+ break;
+ }
+ }
+
+ neo1973_gpb_setpin(GTA01_GPIO_MODEM_ON, 1);
+ } else {
+ neo1973_gpb_setpin(GTA01_GPIO_MODEM_ON, 0);
+
+ if (machine_is_neo1973_gta02()) {
+ switch (system_rev) {
+ case GTA02v2_SYSTEM_REV:
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ pcf50633_gpio_set(gta02_pcf_pdata.pcf,
+ PCF50633_GPIO2, 0);
+ break;
+ }
+ }
+
+ if (gta01_gsm.gpio_ngsm_en)
+ s3c2410_gpio_setpin(gta01_gsm.gpio_ngsm_en, 1);
+
+ if (gta01_gsm.con) {
+ s3c24xx_serial_console_set_silence(0);
+ console_start(gta01_gsm.con);
+
+ dev_dbg(dev, "powered down GSM, thus enabling "
+ "serial console\n");
+ }
+ }
+ } else if (!strcmp(attr->attr.name, "reset")) {
+ if (machine_is_neo1973_gta01())
+ neo1973_gpb_setpin(GTA01_GPIO_MODEM_RST, on);
+ else if (machine_is_neo1973_gta02())
+ neo1973_gpb_setpin(GTA02_GPIO_MODEM_RST, on);
+ } else if (!strcmp(attr->attr.name, "download")) {
+ if (machine_is_neo1973_gta01())
+ s3c2410_gpio_setpin(GTA01_GPIO_MODEM_DNLOAD, on);
+
+ if (machine_is_neo1973_gta02()) {
+ /*
+ * the keyboard / buttons driver requests and enables
+ * the JACK_INSERT IRQ. We have to take care about
+ * not enabling and disabling the IRQ when it was
+ * already in that state or we get "unblanaced IRQ"
+ * kernel warnings and stack dumps. So we use the
+ * copy of the ndl_gsm state to figure out if we should
+ * enable or disable the jack interrupt
+ */
+ if (on) {
+ if (gta01_gsm.gpio_ndl_gsm)
+ disable_irq(gpio_to_irq(
+ GTA02_GPIO_JACK_INSERT));
+ } else {
+ if (!gta01_gsm.gpio_ndl_gsm)
+ enable_irq(gpio_to_irq(
+ GTA02_GPIO_JACK_INSERT));
+ }
+
+ gta01_gsm.gpio_ndl_gsm = !on;
+ s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, !on);
+ }
+ } else if (!strcmp(attr->attr.name, "flowcontrolled")) {
+ if (on) {
+ gta_gsm_interrupts = 0;
+ s3c2410_gpio_setpin(S3C2410_GPH1, 1);
+ s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP);
+ } else
+ s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_nRTS0);
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR(power_on, 0644, gsm_read, gsm_write);
+static DEVICE_ATTR(reset, 0644, gsm_read, gsm_write);
+static DEVICE_ATTR(download, 0644, gsm_read, gsm_write);
+static DEVICE_ATTR(flowcontrolled, 0644, gsm_read, gsm_write);
+
+#ifdef CONFIG_PM
+
+static int gta01_gsm_resume(struct platform_device *pdev);
+static int gta01_gsm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ /* GPIO state is saved/restored by S3C2410 core GPIO driver, so we
+ * don't need to do much here. */
+
+ /* If flowcontrol asserted, abort if GSM already interrupted */
+ if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT) {
+ if (gta_gsm_interrupts)
+ goto busy;
+ }
+
+ /* disable DL GSM to prevent jack_insert becoming 'floating' */
+ if (machine_is_neo1973_gta02())
+ s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, 1);
+ return 0;
+
+busy:
+ return -EBUSY;
+}
+
+static int
+gta01_gsm_suspend_late(struct platform_device *pdev, pm_message_t state)
+{
+ /* Last chance: abort if GSM already interrupted */
+ if (s3c2410_gpio_getcfg(S3C2410_GPH1) == S3C2410_GPIO_OUTPUT) {
+ if (gta_gsm_interrupts)
+ return -EBUSY;
+ }
+ return 0;
+}
+
+static int gta01_gsm_resume(struct platform_device *pdev)
+{
+ /* GPIO state is saved/restored by S3C2410 core GPIO driver, so we
+ * don't need to do much here. */
+
+ /* Make sure that the kernel console on the serial port is still
+ * disabled. FIXME: resume ordering race with serial driver! */
+ if (gta01_gsm.con && s3c2410_gpio_getpin(GTA01_GPIO_MODEM_ON))
+ console_stop(gta01_gsm.con);
+
+ if (machine_is_neo1973_gta02())
+ s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, gta01_gsm.gpio_ndl_gsm);
+
+ return 0;
+}
+#else
+#define gta01_gsm_suspend NULL
+#define gta01_gsm_suspend_late NULL
+#define gta01_gsm_resume NULL
+#endif /* CONFIG_PM */
+
+static struct attribute *gta01_gsm_sysfs_entries[] = {
+ &dev_attr_power_on.attr,
+ &dev_attr_reset.attr,
+ &dev_attr_download.attr,
+ &dev_attr_flowcontrolled.attr,
+ NULL
+};
+
+static struct attribute_group gta01_gsm_attr_group = {
+ .name = NULL,
+ .attrs = gta01_gsm_sysfs_entries,
+};
+
+static int __init gta01_gsm_probe(struct platform_device *pdev)
+{
+ switch (system_rev) {
+ case GTA01v3_SYSTEM_REV:
+ gta01_gsm.gpio_ngsm_en = GTA01v3_GPIO_nGSM_EN;
+ break;
+ case GTA01v4_SYSTEM_REV:
+ gta01_gsm.gpio_ngsm_en = 0;
+ break;
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ gta01_gsm.gpio_ngsm_en = GTA01Bv2_GPIO_nGSM_EN;
+ s3c2410_gpio_setpin(GTA01v3_GPIO_nGSM_EN, 0);
+ break;
+ case GTA02v1_SYSTEM_REV:
+ case GTA02v2_SYSTEM_REV:
+ case GTA02v3_SYSTEM_REV:
+ case GTA02v4_SYSTEM_REV:
+ case GTA02v5_SYSTEM_REV:
+ case GTA02v6_SYSTEM_REV:
+ gta01_gsm.gpio_ngsm_en = 0;
+ break;
+ default:
+ dev_warn(&pdev->dev, "Unknown Neo1973 Revision 0x%x, "
+ "some PM features not available!!!\n",
+ system_rev);
+ break;
+ }
+
+ switch (system_rev) {
+ case GTA01v4_SYSTEM_REV:
+ case GTA01Bv2_SYSTEM_REV:
+ gta01_gsm_sysfs_entries[ARRAY_SIZE(gta01_gsm_sysfs_entries)-2] =
+ &dev_attr_download.attr;
+ break;
+ default:
+ break;
+ }
+
+ if (machine_is_neo1973_gta01()) {
+ gta01_gsm.con = find_s3c24xx_console();
+ if (!gta01_gsm.con)
+ dev_warn(&pdev->dev,
+ "cannot find S3C24xx console driver\n");
+ } else
+ gta01_gsm.con = NULL;
+
+ /* note that download initially disabled, and enforce that */
+ gta01_gsm.gpio_ndl_gsm = 1;
+ if (machine_is_neo1973_gta02())
+ s3c2410_gpio_setpin(GTA02_GPIO_nDL_GSM, 1);
+
+ return sysfs_create_group(&pdev->dev.kobj, &gta01_gsm_attr_group);
+}
+
+static int gta01_gsm_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &gta01_gsm_attr_group);
+
+ return 0;
+}
+
+static struct platform_driver gta01_gsm_driver = {
+ .probe = gta01_gsm_probe,
+ .remove = gta01_gsm_remove,
+ .suspend = gta01_gsm_suspend,
+ .suspend_late = gta01_gsm_suspend_late,
+ .resume = gta01_gsm_resume,
+ .driver = {
+ .name = "neo1973-pm-gsm",
+ },
+};
+
+static int __devinit gta01_gsm_init(void)
+{
+ return platform_driver_register(&gta01_gsm_driver);
+}
+
+static void gta01_gsm_exit(void)
+{
+ platform_driver_unregister(&gta01_gsm_driver);
+}
+
+module_init(gta01_gsm_init);
+module_exit(gta01_gsm_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("FIC Neo1973 GSM Power Management");
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/neo1973_shadow.c
@@ -0,0 +1,88 @@
+/*
+ * include/asm-arm/plat-s3c24xx/neo1973.h
+ *
+ * Common utility code for GTA01 and GTA02
+ *
+ * Copyright (C) 2008 by Openmoko, Inc.
+ * Author: Holger Hans Peter Freyther <freyther@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/gpio.h>
+#include <mach/regs-gpio.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+
+/**
+ * Shadow GPIO bank B handling. For the LEDs we need to keep track of the state
+ * in software. The s3c2410_gpio_setpin must not be used for GPIOs on bank B
+ */
+static unsigned long gpb_mask;
+static unsigned long gpb_state;
+
+void neo1973_gpb_add_shadow_gpio(unsigned int gpio)
+{
+ unsigned long offset = S3C2410_GPIO_OFFSET(gpio);
+ unsigned long flags;
+
+ local_irq_save(flags);
+ gpb_mask |= 1L << offset;
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(neo1973_gpb_add_shadow_gpio);
+
+static void set_shadow_gpio(unsigned long offset, unsigned int value)
+{
+ unsigned long state = value != 0;
+
+ gpb_state &= ~(1L << offset);
+ gpb_state |= state << offset;
+}
+
+void neo1973_gpb_setpin(unsigned int pin, unsigned to)
+{
+ void __iomem *base = S3C24XX_GPIO_BASE(S3C2410_GPB0);
+ unsigned long offset = S3C2410_GPIO_OFFSET(pin);
+ unsigned long flags;
+ unsigned long dat;
+
+ BUG_ON(base != S3C24XX_GPIO_BASE(pin));
+
+ local_irq_save(flags);
+ dat = __raw_readl(base + 0x04);
+
+ /* Add the shadow values */
+ dat &= ~gpb_mask;
+ dat |= gpb_state;
+
+ /* Do the operation like s3c2410_gpio_setpin */
+ dat &= ~(1L << offset);
+ dat |= to << offset;
+
+ /* Update the shadow state */
+ if ((1L << offset) & gpb_mask)
+ set_shadow_gpio(offset, to);
+
+ __raw_writel(dat, base + 0x04);
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(neo1973_gpb_setpin);
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -31,14 +31,9 @@
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/interrupt.h>
-#include <linux/crc32.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/io.h>
-
-#include <asm/cacheflush.h>
-#include <mach/hardware.h>
+#include <linux/regulator/machine.h>
#include <plat/regs-serial.h>
#include <mach/regs-clock.h>
@@ -50,10 +45,6 @@
#include <plat/pm.h>
-/* for external use */
-
-unsigned long s3c_pm_flags;
-
#define PFX "s3c24xx-pm: "
static struct sleep_save core_save[] = {
@@ -76,371 +67,26 @@
SAVE_ITEM(S3C2410_BANKCON4),
SAVE_ITEM(S3C2410_BANKCON5),
+#ifndef CONFIG_CPU_FREQ
SAVE_ITEM(S3C2410_CLKDIVN),
SAVE_ITEM(S3C2410_MPLLCON),
+ SAVE_ITEM(S3C2410_REFRESH),
+#endif
SAVE_ITEM(S3C2410_UPLLCON),
SAVE_ITEM(S3C2410_CLKSLOW),
- SAVE_ITEM(S3C2410_REFRESH),
-};
-
-static struct gpio_sleep {
- void __iomem *base;
- unsigned int gpcon;
- unsigned int gpdat;
- unsigned int gpup;
-} gpio_save[] = {
- [0] = {
- .base = S3C2410_GPACON,
- },
- [1] = {
- .base = S3C2410_GPBCON,
- },
- [2] = {
- .base = S3C2410_GPCCON,
- },
- [3] = {
- .base = S3C2410_GPDCON,
- },
- [4] = {
- .base = S3C2410_GPECON,
- },
- [5] = {
- .base = S3C2410_GPFCON,
- },
- [6] = {
- .base = S3C2410_GPGCON,
- },
- [7] = {
- .base = S3C2410_GPHCON,
- },
};
static struct sleep_save misc_save[] = {
SAVE_ITEM(S3C2410_DCLKCON),
};
-#ifdef CONFIG_S3C2410_PM_DEBUG
-
-#define SAVE_UART(va) \
- SAVE_ITEM((va) + S3C2410_ULCON), \
- SAVE_ITEM((va) + S3C2410_UCON), \
- SAVE_ITEM((va) + S3C2410_UFCON), \
- SAVE_ITEM((va) + S3C2410_UMCON), \
- SAVE_ITEM((va) + S3C2410_UBRDIV)
-
-static struct sleep_save uart_save[] = {
- SAVE_UART(S3C24XX_VA_UART0),
- SAVE_UART(S3C24XX_VA_UART1),
-#ifndef CONFIG_CPU_S3C2400
- SAVE_UART(S3C24XX_VA_UART2),
-#endif
-};
-
-/* debug
- *
- * we send the debug to printascii() to allow it to be seen if the
- * system never wakes up from the sleep
-*/
-
-extern void printascii(const char *);
-
-void pm_dbg(const char *fmt, ...)
-{
- va_list va;
- char buff[256];
-
- va_start(va, fmt);
- vsprintf(buff, fmt, va);
- va_end(va);
-
- printascii(buff);
-}
-
-static void s3c2410_pm_debug_init(void)
-{
- unsigned long tmp = __raw_readl(S3C2410_CLKCON);
-
- /* re-start uart clocks */
- tmp |= S3C2410_CLKCON_UART0;
- tmp |= S3C2410_CLKCON_UART1;
- tmp |= S3C2410_CLKCON_UART2;
-
- __raw_writel(tmp, S3C2410_CLKCON);
- udelay(10);
-}
-
-#define DBG(fmt...) pm_dbg(fmt)
-#else
-#define DBG(fmt...) printk(KERN_DEBUG fmt)
-
-#define s3c2410_pm_debug_init() do { } while(0)
-
-static struct sleep_save uart_save[] = {};
-#endif
-
-#if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
-
-/* suspend checking code...
- *
- * this next area does a set of crc checks over all the installed
- * memory, so the system can verify if the resume was ok.
- *
- * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
- * increasing it will mean that the area corrupted will be less easy to spot,
- * and reducing the size will cause the CRC save area to grow
-*/
-
-#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
-
-static u32 crc_size; /* size needed for the crc block */
-static u32 *crcs; /* allocated over suspend/resume */
-
-typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
-
-/* s3c2410_pm_run_res
- *
- * go thorugh the given resource list, and look for system ram
-*/
-
-static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
-{
- while (ptr != NULL) {
- if (ptr->child != NULL)
- s3c2410_pm_run_res(ptr->child, fn, arg);
-
- if ((ptr->flags & IORESOURCE_MEM) &&
- strcmp(ptr->name, "System RAM") == 0) {
- DBG("Found system RAM at %08lx..%08lx\n",
- ptr->start, ptr->end);
- arg = (fn)(ptr, arg);
- }
-
- ptr = ptr->sibling;
- }
-}
-
-static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
-{
- s3c2410_pm_run_res(&iomem_resource, fn, arg);
-}
-
-static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
-{
- u32 size = (u32)(res->end - res->start)+1;
-
- size += CHECK_CHUNKSIZE-1;
- size /= CHECK_CHUNKSIZE;
-
- DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
-
- *val += size * sizeof(u32);
- return val;
-}
-
-/* s3c2410_pm_prepare_check
- *
- * prepare the necessary information for creating the CRCs. This
- * must be done before the final save, as it will require memory
- * allocating, and thus touching bits of the kernel we do not
- * know about.
-*/
-
-static void s3c2410_pm_check_prepare(void)
-{
- crc_size = 0;
-
- s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
-
- DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
-
- crcs = kmalloc(crc_size+4, GFP_KERNEL);
- if (crcs == NULL)
- printk(KERN_ERR "Cannot allocated CRC save area\n");
-}
-
-static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
-{
- unsigned long addr, left;
-
- for (addr = res->start; addr < res->end;
- addr += CHECK_CHUNKSIZE) {
- left = res->end - addr;
-
- if (left > CHECK_CHUNKSIZE)
- left = CHECK_CHUNKSIZE;
-
- *val = crc32_le(~0, phys_to_virt(addr), left);
- val++;
- }
-
- return val;
-}
-
-/* s3c2410_pm_check_store
- *
- * compute the CRC values for the memory blocks before the final
- * sleep.
-*/
-
-static void s3c2410_pm_check_store(void)
-{
- if (crcs != NULL)
- s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
-}
-
-/* in_region
- *
- * return TRUE if the area defined by ptr..ptr+size contatins the
- * what..what+whatsz
-*/
-
-static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
-{
- if ((what+whatsz) < ptr)
- return 0;
-
- if (what > (ptr+size))
- return 0;
-
- return 1;
-}
-
-static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
-{
- void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
- unsigned long addr;
- unsigned long left;
- void *ptr;
- u32 calc;
-
- for (addr = res->start; addr < res->end;
- addr += CHECK_CHUNKSIZE) {
- left = res->end - addr;
-
- if (left > CHECK_CHUNKSIZE)
- left = CHECK_CHUNKSIZE;
-
- ptr = phys_to_virt(addr);
-
- if (in_region(ptr, left, crcs, crc_size)) {
- DBG("skipping %08lx, has crc block in\n", addr);
- goto skip_check;
- }
-
- if (in_region(ptr, left, save_at, 32*4 )) {
- DBG("skipping %08lx, has save block in\n", addr);
- goto skip_check;
- }
-
- /* calculate and check the checksum */
-
- calc = crc32_le(~0, ptr, left);
- if (calc != *val) {
- printk(KERN_ERR PFX "Restore CRC error at "
- "%08lx (%08x vs %08x)\n", addr, calc, *val);
-
- DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
- addr, calc, *val);
- }
-
- skip_check:
- val++;
- }
-
- return val;
-}
-
-/* s3c2410_pm_check_restore
- *
- * check the CRCs after the restore event and free the memory used
- * to hold them
-*/
-
-static void s3c2410_pm_check_restore(void)
-{
- if (crcs != NULL) {
- s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
- kfree(crcs);
- crcs = NULL;
- }
-}
-
-#else
-
-#define s3c2410_pm_check_prepare() do { } while(0)
-#define s3c2410_pm_check_restore() do { } while(0)
-#define s3c2410_pm_check_store() do { } while(0)
-#endif
-
-/* helper functions to save and restore register state */
-
-void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
-{
- for (; count > 0; count--, ptr++) {
- ptr->val = __raw_readl(ptr->reg);
- DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
- }
-}
-
-/* s3c2410_pm_do_restore
- *
- * restore the system from the given list of saved registers
- *
- * Note, we do not use DBG() in here, as the system may not have
- * restore the UARTs state yet
-*/
-
-void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
-{
- for (; count > 0; count--, ptr++) {
- printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
- ptr->reg, ptr->val, __raw_readl(ptr->reg));
-
- __raw_writel(ptr->val, ptr->reg);
- }
-}
-
-/* s3c2410_pm_do_restore_core
- *
- * similar to s3c2410_pm_do_restore_core
- *
- * WARNING: Do not put any debug in here that may effect memory or use
- * peripherals, as things may be changing!
-*/
-
-static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
-{
- for (; count > 0; count--, ptr++) {
- __raw_writel(ptr->val, ptr->reg);
- }
-}
-
-/* s3c2410_pm_show_resume_irqs
- *
- * print any IRQs asserted at resume time (ie, we woke from)
-*/
-
-static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
- unsigned long mask)
-{
- int i;
-
- which &= ~mask;
-
- for (i = 0; i <= 31; i++) {
- if ((which) & (1L<<i)) {
- DBG("IRQ %d asserted at resume\n", start+i);
- }
- }
-}
-
-/* s3c2410_pm_check_resume_pin
+/* s3c_pm_check_resume_pin
*
* check to see if the pin is configured correctly for sleep mode, and
* make any necessary adjustments if it is not
*/
-static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
+static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
{
unsigned long irqstate;
unsigned long pinstate;
@@ -455,21 +101,21 @@
if (!irqstate) {
if (pinstate == S3C2410_GPIO_IRQ)
- DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
+ S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
} else {
if (pinstate == S3C2410_GPIO_IRQ) {
- DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
+ S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
}
}
}
-/* s3c2410_pm_configure_extint
+/* s3c_pm_configure_extint
*
* configure all external interrupt pins
*/
-static void s3c2410_pm_configure_extint(void)
+void s3c_pm_configure_extint(void)
{
int pin;
@@ -479,336 +125,24 @@
*/
for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
- s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
+ s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
}
for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
- s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
+ s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
}
}
-/* offsets for CON/DAT/UP registers */
-
-#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
-#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
-#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
-
-/* s3c2410_pm_save_gpios()
- *
- * Save the state of the GPIOs
- */
-static void s3c2410_pm_save_gpios(void)
+void s3c_pm_restore_core(void)
{
- struct gpio_sleep *gps = gpio_save;
- unsigned int gpio;
-
- for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
- void __iomem *base = gps->base;
-
- gps->gpcon = __raw_readl(base + OFFS_CON);
- gps->gpdat = __raw_readl(base + OFFS_DAT);
-
- if (gpio > 0)
- gps->gpup = __raw_readl(base + OFFS_UP);
-
- }
-}
-
-/* Test whether the given masked+shifted bits of an GPIO configuration
- * are one of the SFN (special function) modes. */
-
-static inline int is_sfn(unsigned long con)
-{
- return (con == 2 || con == 3);
-}
-
-/* Test if the given masked+shifted GPIO configuration is an input */
-
-static inline int is_in(unsigned long con)
-{
- return con == 0;
-}
-
-/* Test if the given masked+shifted GPIO configuration is an output */
-
-static inline int is_out(unsigned long con)
-{
- return con == 1;
+ s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
+ s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
}
-/* s3c2410_pm_restore_gpio()
- *
- * Restore one of the GPIO banks that was saved during suspend. This is
- * not as simple as once thought, due to the possibility of glitches
- * from the order that the CON and DAT registers are set in.
- *
- * The three states the pin can be are {IN,OUT,SFN} which gives us 9
- * combinations of changes to check. Three of these, if the pin stays
- * in the same configuration can be discounted. This leaves us with
- * the following:
- *
- * { IN => OUT } Change DAT first
- * { IN => SFN } Change CON first
- * { OUT => SFN } Change CON first, so new data will not glitch
- * { OUT => IN } Change CON first, so new data will not glitch
- * { SFN => IN } Change CON first
- * { SFN => OUT } Change DAT first, so new data will not glitch [1]
- *
- * We do not currently deal with the UP registers as these control
- * weak resistors, so a small delay in change should not need to bring
- * these into the calculations.
- *
- * [1] this assumes that writing to a pin DAT whilst in SFN will set the
- * state for when it is next output.
- */
-
-static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
+void s3c_pm_save_core(void)
{
- void __iomem *base = gps->base;
- unsigned long gps_gpcon = gps->gpcon;
- unsigned long gps_gpdat = gps->gpdat;
- unsigned long old_gpcon;
- unsigned long old_gpdat;
- unsigned long old_gpup = 0x0;
- unsigned long gpcon;
- int nr;
-
- old_gpcon = __raw_readl(base + OFFS_CON);
- old_gpdat = __raw_readl(base + OFFS_DAT);
-
- if (base == S3C2410_GPACON) {
- /* GPACON only has one bit per control / data and no PULLUPs.
- * GPACON[x] = 0 => Output, 1 => SFN */
-
- /* first set all SFN bits to SFN */
-
- gpcon = old_gpcon | gps->gpcon;
- __raw_writel(gpcon, base + OFFS_CON);
-
- /* now set all the other bits */
-
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
- } else {
- unsigned long old, new, mask;
- unsigned long change_mask = 0x0;
-
- old_gpup = __raw_readl(base + OFFS_UP);
-
- /* Create a change_mask of all the items that need to have
- * their CON value changed before their DAT value, so that
- * we minimise the work between the two settings.
- */
-
- for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
- old = (old_gpcon & mask) >> nr;
- new = (gps_gpcon & mask) >> nr;
-
- /* If there is no change, then skip */
-
- if (old == new)
- continue;
-
- /* If both are special function, then skip */
-
- if (is_sfn(old) && is_sfn(new))
- continue;
-
- /* Change is IN => OUT, do not change now */
-
- if (is_in(old) && is_out(new))
- continue;
-
- /* Change is SFN => OUT, do not change now */
-
- if (is_sfn(old) && is_out(new))
- continue;
-
- /* We should now be at the case of IN=>SFN,
- * OUT=>SFN, OUT=>IN, SFN=>IN. */
-
- change_mask |= mask;
- }
-
- /* Write the new CON settings */
-
- gpcon = old_gpcon & ~change_mask;
- gpcon |= gps_gpcon & change_mask;
-
- __raw_writel(gpcon, base + OFFS_CON);
-
- /* Now change any items that require DAT,CON */
-
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
- __raw_writel(gps->gpup, base + OFFS_UP);
- }
-
- DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
- index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+ s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
+ s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
}
-
-/** s3c2410_pm_restore_gpios()
- *
- * Restore the state of the GPIOs
- */
-
-static void s3c2410_pm_restore_gpios(void)
-{
- struct gpio_sleep *gps = gpio_save;
- int gpio;
-
- for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
- s3c2410_pm_restore_gpio(gpio, gps);
- }
-}
-
-void (*pm_cpu_prep)(void);
-void (*pm_cpu_sleep)(void);
-
-#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
-
-/* s3c2410_pm_enter
- *
- * central control for sleep/resume process
-*/
-
-static int s3c2410_pm_enter(suspend_state_t state)
-{
- unsigned long regs_save[16];
-
- /* ensure the debug is initialised (if enabled) */
-
- s3c2410_pm_debug_init();
-
- DBG("s3c2410_pm_enter(%d)\n", state);
-
- if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
- printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
- return -EINVAL;
- }
-
- /* check if we have anything to wake-up with... bad things seem
- * to happen if you suspend with no wakeup (system will often
- * require a full power-cycle)
- */
-
- if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
- !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
- printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
- printk(KERN_ERR PFX "Aborting sleep\n");
- return -EINVAL;
- }
-
- /* prepare check area if configured */
-
- s3c2410_pm_check_prepare();
-
- /* store the physical address of the register recovery block */
-
- s3c2410_sleep_save_phys = virt_to_phys(regs_save);
-
- DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
-
- /* save all necessary core registers not covered by the drivers */
-
- s3c2410_pm_save_gpios();
- s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
- s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
- s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
-
- /* set the irq configuration for wake */
-
- s3c2410_pm_configure_extint();
-
- DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
- s3c_irqwake_intmask, s3c_irqwake_eintmask);
-
- __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
- __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
-
- /* ack any outstanding external interrupts before we go to sleep */
-
- __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
- __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
- __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
-
- /* call cpu specific preparation */
-
- pm_cpu_prep();
-
- /* flush cache back to ram */
-
- flush_cache_all();
-
- s3c2410_pm_check_store();
-
- /* send the cpu to sleep... */
-
- __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */
-
- /* s3c2410_cpu_save will also act as our return point from when
- * we resume as it saves its own register state, so use the return
- * code to differentiate return from save and return from sleep */
-
- if (s3c2410_cpu_save(regs_save) == 0) {
- flush_cache_all();
- pm_cpu_sleep();
- }
-
- /* restore the cpu state */
-
- cpu_init();
-
- /* restore the system state */
-
- s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
- s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
- s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
- s3c2410_pm_restore_gpios();
-
- s3c2410_pm_debug_init();
-
- /* check what irq (if any) restored the system */
-
- DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
- __raw_readl(S3C2410_SRCPND),
- __raw_readl(S3C2410_EINTPEND));
-
- s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
- s3c_irqwake_intmask);
-
- s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
- s3c_irqwake_eintmask);
-
- DBG("post sleep, preparing to return\n");
-
- s3c2410_pm_check_restore();
-
- /* ok, let's return from sleep */
-
- DBG("S3C2410 PM Resume (post-restore)\n");
- return 0;
-}
-
-static struct platform_suspend_ops s3c2410_pm_ops = {
- .enter = s3c2410_pm_enter,
- .valid = suspend_valid_only_mem,
-};
-
-/* s3c2410_pm_init
- *
- * Attach the power management functions. This should be called
- * from the board specific initialisation if the board supports
- * it.
-*/
-
-int __init s3c2410_pm_init(void)
-{
- printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
-
- suspend_set_ops(&s3c2410_pm_ops);
- return 0;
-}
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -61,7 +61,7 @@
__raw_writel(gstatus4, S3C2410_GSTATUS4);
- return s3c2410_pm_init();
+ return s3c_pm_init();
}
arch_initcall(pm_simtec_init);
--- a/arch/arm/plat-s3c24xx/pwm-clock.c
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -24,10 +24,10 @@
#include <mach/regs-clock.h>
#include <mach/regs-gpio.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/cpu.h>
-#include <plat/regs-timer.h>
+#include <asm/plat-s3c/regs-timer.h>
/* Each of the timers 0 through 5 go through the following
* clock tree, with the inputs depending on the timers.
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -0,0 +1,277 @@
+/* linux/arch/arm/mach-s3c2410/clock.c
+ *
+ * Copyright (c) 2006 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410,S3C2440,S3C2442 Clock control support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+#include <plat/s3c2410.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+
+int s3c2410_clkcon_enable(struct clk *clk, int enable)
+{
+ unsigned int clocks = clk->ctrlbit;
+ unsigned long clkcon;
+
+ clkcon = __raw_readl(S3C2410_CLKCON);
+
+ if (enable)
+ clkcon |= clocks;
+ else
+ clkcon &= ~clocks;
+
+ /* ensure none of the special function bits set */
+ clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
+
+ __raw_writel(clkcon, S3C2410_CLKCON);
+
+ return 0;
+}
+
+static int s3c2410_upll_enable(struct clk *clk, int enable)
+{
+ unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
+ unsigned long orig = clkslow;
+
+ if (enable)
+ clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
+ else
+ clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
+
+ __raw_writel(clkslow, S3C2410_CLKSLOW);
+
+ /* if we started the UPLL, then allow to settle */
+
+ if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
+ udelay(200);
+
+ return 0;
+}
+
+/* standard clock definitions */
+
+static struct clk init_clocks_disable[] = {
+ {
+ .name = "nand",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_NAND,
+ }, {
+ .name = "sdi",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_SDI,
+ }, {
+ .name = "adc",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_ADC,
+ }, {
+ .name = "i2c",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_IIC,
+ }, {
+ .name = "iis",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_IIS,
+ }, {
+ .name = "spi",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_SPI,
+ }
+};
+
+static struct clk init_clocks[] = {
+ {
+ .name = "lcd",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_LCDC,
+ }, {
+ .name = "gpio",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_GPIO,
+ }, {
+ .name = "usb-host",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_USBH,
+ }, {
+ .name = "usb-device",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_USBD,
+ }, {
+ .name = "timers",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_PWMT,
+ }, {
+ .name = "uart",
+ .id = 0,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_UART0,
+ }, {
+ .name = "uart",
+ .id = 1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_UART1,
+ }, {
+ .name = "uart",
+ .id = 2,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_UART2,
+ }, {
+ .name = "rtc",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c2410_clkcon_enable,
+ .ctrlbit = S3C2410_CLKCON_RTC,
+ }, {
+ .name = "watchdog",
+ .id = -1,
+ .parent = &clk_p,
+ .ctrlbit = 0,
+ }, {
+ .name = "usb-bus-host",
+ .id = -1,
+ .parent = &clk_usb_bus,
+ }, {
+ .name = "usb-bus-gadget",
+ .id = -1,
+ .parent = &clk_usb_bus,
+ },
+};
+
+/* s3c2410_baseclk_add()
+ *
+ * Add all the clocks used by the s3c2410 or compatible CPUs
+ * such as the S3C2440 and S3C2442.
+ *
+ * We cannot use a system device as we are needed before any
+ * of the init-calls that initialise the devices are actually
+ * done.
+*/
+
+int __init s3c2410_baseclk_add(void)
+{
+ unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
+ unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
+ struct clk *clkp;
+ struct clk *xtal;
+ int ret;
+ int ptr;
+
+ clk_upll.enable = s3c2410_upll_enable;
+
+ if (s3c24xx_register_clock(&clk_usb_bus) < 0)
+ printk(KERN_ERR "failed to register usb bus clock\n");
+
+ /* register clocks from clock array */
+
+ clkp = init_clocks;
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+ /* ensure that we note the clock state */
+
+ clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
+
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+
+ /* We must be careful disabling the clocks we are not intending to
+ * be using at boot time, as subsystems such as the LCD which do
+ * their own DMA requests to the bus can cause the system to lockup
+ * if they where in the middle of requesting bus access.
+ *
+ * Disabling the LCD clock if the LCD is active is very dangerous,
+ * and therefore the bootloader should be careful to not enable
+ * the LCD clock if it is not needed.
+ */
+
+ /* install (and disable) the clocks we do not need immediately */
+
+ clkp = init_clocks_disable;
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+
+ s3c2410_clkcon_enable(clkp, 0);
+ }
+
+ /* show the clock-slow value */
+
+ xtal = clk_get(NULL, "xtal");
+
+ printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
+ print_mhz(clk_get_rate(xtal) /
+ ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
+ (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
+ (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
+ (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
+
+ s3c_pwmclk_init();
+ return 0;
+}
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -29,6 +29,8 @@
#include <mach/hardware.h>
#include <asm/irq.h>
+#include <plat/cpu-freq.h>
+
#include <mach/regs-clock.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
@@ -42,6 +44,7 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
+#include <plat/pll.h>
static struct map_desc s3c244x_iodesc[] __initdata = {
IODESC_ENT(CLKPWR),
@@ -56,32 +59,37 @@
s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
}
-void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
+extern struct platform_device s3c_device_ts;
+
+void __init s3c244x_map_io(void)
{
/* register our io-tables */
iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
- iotable_init(mach_desc, size);
/* rename any peripherals used differing from the s3c2410 */
s3c_device_sdi.name = "s3c2440-sdi";
- s3c_device_i2c.name = "s3c2440-i2c";
+ s3c_device_i2c0.name = "s3c2440-i2c";
s3c_device_nand.name = "s3c2440-nand";
+ s3c_device_ts.name = "s3c2440-ts";
s3c_device_usbgadget.name = "s3c2440-usbgadget";
}
-void __init s3c244x_init_clocks(int xtal)
+void __init_or_cpufreq s3c244x_setup_clocks(void)
{
+ struct clk *xtal_clk;
unsigned long clkdiv;
unsigned long camdiv;
+ unsigned long xtal;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
- /* now we've got our machine bits initialised, work out what
- * clocks we've got */
+ xtal_clk = clk_get(NULL, "xtal");
+ xtal = clk_get_rate(xtal_clk);
+ clk_put(xtal_clk);
- fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
+ fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
@@ -107,18 +115,24 @@
}
hclk = fclk / hdiv;
- pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
+ pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
/* print brief summary of clocks, etc */
printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
+ s3c24xx_setup_clocks(fclk, hclk, pclk);
+}
+
+void __init s3c244x_init_clocks(int xtal)
+{
/* initialise the clocks here, to allow other things like the
* console to use them, and to add new ones after the initialisation
*/
- s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
+ s3c24xx_register_baseclocks(xtal);
+ s3c244x_setup_clocks();
s3c2410_baseclk_add();
}
@@ -134,13 +148,13 @@
static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
{
- s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
+ s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
return 0;
}
static int s3c244x_resume(struct sys_device *dev)
{
- s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
+ s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
return 0;
}
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -31,7 +31,6 @@
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
-#include <linux/mutex.h>
#include <linux/clk.h>
#include <linux/io.h>
@@ -102,13 +101,13 @@
if (clk_get_rate(clock_upll) > (94 * MHZ)) {
clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
- mutex_lock(&clocks_mutex);
+ spin_lock(&clocks_lock);
clkdivn = __raw_readl(S3C2410_CLKDIVN);
clkdivn |= S3C2440_CLKDIVN_UCLK;
__raw_writel(clkdivn, S3C2410_CLKDIVN);
- mutex_unlock(&clocks_mutex);
+ spin_unlock(&clocks_lock);
}
return 0;
--- a/arch/arm/plat-s3c24xx/s3c244x.h
+++ b/arch/arm/plat-s3c24xx/s3c244x.h
@@ -12,7 +12,7 @@
#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
+extern void s3c244x_map_io(void);
extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c24xx/setup-i2c.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX Base setup for i2c device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+
+struct platform_device;
+
+#include <plat/iic.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+ s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
+ s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
+}
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -41,7 +41,7 @@
.text
- /* s3c2410_cpu_save
+ /* s3c_cpu_save
*
* save enough of the CPU state to allow us to re-start
* pm.c code. as we store items like the sp/lr, we will
@@ -59,7 +59,7 @@
* 1 => resumed from sleep
*/
-ENTRY(s3c2410_cpu_save)
+ENTRY(s3c_cpu_save)
stmfd sp!, { r4 - r12, lr }
@@ store co-processor registers
@@ -84,7 +84,7 @@
.ltorg
@@ the next bits sit in the .data segment, even though they
- @@ happen to be code... the s3c2410_sleep_save_phys needs to be
+ @@ happen to be code... the s3c_sleep_save_phys needs to be
@@ accessed by the resume code before it can restore the MMU.
@@ This means that the variable has to be close enough for the
@@ code to read it... since the .text segment needs to be RO,
@@ -92,19 +92,19 @@
.data
- .global s3c2410_sleep_save_phys
-s3c2410_sleep_save_phys:
+ .global s3c_sleep_save_phys
+s3c_sleep_save_phys:
.word 0
/* sleep magic, to allow the bootloader to check for an valid
* image to resume to. Must be the first word before the
- * s3c2410_cpu_resume entry.
+ * s3c_cpu_resume entry.
*/
.word 0x2bedf00d
- /* s3c2410_cpu_resume
+ /* s3c_cpu_resume
*
* resume code entry for bootloader to call
*
@@ -113,7 +113,7 @@
* must not write to the code segment (code is read-only)
*/
-ENTRY(s3c2410_cpu_resume)
+ENTRY(s3c_cpu_resume)
mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
msr cpsr_c, r0
@@ -145,7 +145,7 @@
mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
- ldr r0, s3c2410_sleep_save_phys @ address of restore block
+ ldr r0, s3c_sleep_save_phys @ address of restore block
ldmia r0, { r4 - r13 }
mcr p15, 0, r4, c13, c0, 0 @ PID
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
@@ -0,0 +1,37 @@
+/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+
+#include <mach/hardware.h>
+
+#include <mach/spi.h>
+#include <mach/regs-gpio.h>
+
+void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
+ int enable)
+{
+ if (enable) {
+ s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
+ s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
+ s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
+ s3c2410_gpio_pullup(S3C2410_GPE11, 0);
+ s3c2410_gpio_pullup(S3C2410_GPE13, 0);
+ } else {
+ s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT);
+ s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT);
+ s3c2410_gpio_pullup(S3C2410_GPE11, 1);
+ s3c2410_gpio_pullup(S3C2410_GPE12, 1);
+ s3c2410_gpio_pullup(S3C2410_GPE13, 1);
+ }
+}
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
@@ -0,0 +1,37 @@
+/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+
+#include <linux/kernel.h>
+
+#include <mach/hardware.h>
+
+#include <mach/spi.h>
+#include <mach/regs-gpio.h>
+
+void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
+ int enable)
+{
+ if (enable) {
+ s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1);
+ s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1);
+ s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1);
+ s3c2410_gpio_pullup(S3C2410_GPG5, 0);
+ s3c2410_gpio_pullup(S3C2410_GPG6, 0);
+ } else {
+ s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT);
+ s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT);
+ s3c2410_gpio_pullup(S3C2410_GPG5, 1);
+ s3c2410_gpio_pullup(S3C2410_GPG6, 1);
+ s3c2410_gpio_pullup(S3C2410_GPG7, 1);
+ }
+}
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -3,6 +3,8 @@
* Copyright (C) 2003-2005 Simtec Electronics
* Ben Dooks, <ben@simtec.co.uk>
*
+ * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -25,23 +27,27 @@
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
-#include <linux/io.h>
#include <asm/system.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
+#include <asm/io.h>
#include <asm/irq.h>
#include <mach/map.h>
-#include <plat/regs-timer.h>
+#include <asm/plat-s3c/regs-timer.h>
#include <mach/regs-irq.h>
#include <asm/mach/time.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
+#include <asm/plat-s3c24xx/clock.h>
+#include <asm/plat-s3c24xx/cpu.h>
static unsigned long timer_startval;
static unsigned long timer_usec_ticks;
+static struct work_struct resume_work;
+
+unsigned long pclk;
+struct clk *clk;
#define TIMER_USEC_SHIFT 16
@@ -177,11 +183,7 @@
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
} else {
- unsigned long pclk;
- struct clk *clk;
-
- /* for the h1940 (and others), we use the pclk from the core
- * to generate the timer values. since values around 50 to
+ /* since values around 50 to
* 70MHz are not values we can directly generate the timer
* value from, we need to pre-scale and divide before using it.
*
@@ -189,19 +191,9 @@
* (8.45 ticks per usec)
*/
- /* this is used as default if no other timer can be found */
-
- clk = clk_get(NULL, "timers");
- if (IS_ERR(clk))
- panic("failed to get clock for system timer");
-
- clk_enable(clk);
-
- pclk = clk_get_rate(clk);
-
/* configure clock tick */
-
timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
+ printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
tcfg1 |= S3C2410_TCFG1_MUX4_DIV2;
@@ -245,16 +237,244 @@
tcon |= S3C2410_TCON_T4START;
tcon &= ~S3C2410_TCON_T4MANUALUPD;
__raw_writel(tcon, S3C2410_TCON);
+
+ __raw_writel(__raw_readl(S3C2410_INTMSK) & (~(1UL << 14)),
+ S3C2410_INTMSK);
+
+}
+
+struct sys_timer s3c24xx_timer;
+static void timer_resume_work(struct work_struct *work)
+{
+ clk_enable(clk);
+
+#ifdef CONFIG_NO_IDLE_HZ
+ if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
+ s3c24xx_timer.dyn_tick->enable();
+ else
+#endif
+ s3c2410_timer_setup();
}
static void __init s3c2410_timer_init (void)
{
+ if (!use_tclk1_12()) {
+ /* for the h1940 (and others), we use the pclk from the core
+ * to generate the timer values.
+ */
+
+ /* this is used as default if no other timer can be found */
+ clk = clk_get(NULL, "timers");
+ if (IS_ERR(clk))
+ panic("failed to get clock for system timer");
+
+ clk_enable(clk);
+
+ pclk = clk_get_rate(clk);
+ printk("pclk = %lu\n", pclk);
+ }
+
+ INIT_WORK(&resume_work, timer_resume_work);
s3c2410_timer_setup();
setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
}
+static void s3c2410_timer_resume_work(struct work_struct *work)
+{
+ s3c2410_timer_setup();
+}
+
+static void s3c2410_timer_resume(void)
+{
+ static DECLARE_WORK(work, s3c2410_timer_resume_work);
+ int res;
+
+ res = schedule_work(&work);
+ if (!res)
+ printk(KERN_ERR
+ "s3c2410_timer_resume_work already queued ???\n");
+}
+
+#ifdef CONFIG_NO_IDLE_HZ
+/*
+ * We'll set a constant prescaler so we don't have to bother setting it
+ * when reprogramming and so that we avoid costly divisions.
+ *
+ * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
+ * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
+ */
+#define INPUT_FREQ_SHIFT 9
+
+static int ticks_last;
+static int ticks_left;
+static uint32_t tcnto_last;
+
+static inline int s3c24xx_timer_read(void)
+{
+ uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
+
+ /*
+ * WARNING: sometimes we get called before TCNTB has been
+ * loaded into the counter and TCNTO then returns its previous
+ * value and kill us, so don't do anything before counter is
+ * reloaded.
+ */
+ if (unlikely(tcnto == tcnto_last))
+ return ticks_last;
+
+ tcnto_last = -1;
+ return tcnto <<
+ ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
+}
+
+static inline void s3c24xx_timer_program(int ticks)
+{
+ uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
+ uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
+
+ /* Just make sure the timer is stopped. */
+ __raw_writel(tcon, S3C2410_TCON);
+
+ /* TODO: add likely()ies / unlikely()ies */
+ if (ticks >> 18) {
+ ticks_last = min(ticks, 0xffff << 3);
+ ticks_left = ticks - ticks_last;
+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
+ __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
+ } else if (ticks >> 17) {
+ ticks_last = ticks;
+ ticks_left = 0;
+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
+ __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
+ } else if (ticks >> 16) {
+ ticks_last = ticks;
+ ticks_left = 0;
+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
+ __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
+ } else {
+ ticks_last = ticks;
+ ticks_left = 0;
+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
+ __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
+ }
+
+ tcnto_last = __raw_readl(S3C2410_TCNTO(4));
+ __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
+ S3C2410_TCON);
+ __raw_writel(tcon | S3C2410_TCON_T4START,
+ S3C2410_TCON);
+}
+
+/*
+ * If we have already waited all the time we were supposed to wait,
+ * kick the timer, setting the longest allowed timeout value just
+ * for time-keeping.
+ */
+static inline void s3c24xx_timer_program_idle(void)
+{
+ s3c24xx_timer_program(0xffff << 3);
+}
+
+static inline void s3c24xx_timer_update(int restart)
+{
+ int ticks_cur = s3c24xx_timer_read();
+ int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
+ int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
+
+ if (restart) {
+ if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
+ s3c24xx_timer_program(ticks_left);
+ else
+ s3c24xx_timer_program_idle();
+ ticks_last += subjiffy;
+ } else
+ ticks_last = subjiffy;
+
+ while (jiffies_elapsed --)
+ timer_tick();
+}
+
+/* Called when the timer expires. */
+static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
+{
+ tcnto_last = -1;
+ s3c24xx_timer_update(1);
+
+ return IRQ_HANDLED;
+}
+
+/* Called to update jiffies with time elapsed. */
+static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
+{
+ s3c24xx_timer_update(0);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Programs the next timer interrupt needed. Called when dynamic tick is
+ * enabled, and to reprogram the ticks to skip from pm_idle. The CPU goes
+ * to sleep directly after this.
+ */
+static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
+{
+ int subjiffy_left = ticks_last - s3c24xx_timer_read();
+
+ s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
+ ticks_last += subjiffy_left;
+}
+
+static unsigned long s3c24xx_timer_offset_dyn_tick(void)
+{
+ /* TODO */
+ return 0;
+}
+
+static int s3c24xx_timer_enable_dyn_tick(void)
+{
+ /* Set our constant prescaler. */
+ uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
+ int prescaler =
+ max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
+
+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
+ tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
+ __raw_writel(tcfg0, S3C2410_TCFG0);
+
+ /* Override handlers. */
+ s3c2410_timer_irq.handler = s3c24xx_timer_handler;
+ s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
+
+ printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
+ "%li Hz pclk with prescaler %i\n", pclk, prescaler);
+
+ s3c24xx_timer_program_idle();
+
+ return 0;
+}
+
+static int s3c24xx_timer_disable_dyn_tick(void)
+{
+ s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
+ s3c24xx_timer.offset = s3c2410_gettimeoffset;
+ s3c2410_timer_setup();
+
+ return 0;
+}
+
+static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
+ .enable = s3c24xx_timer_enable_dyn_tick,
+ .disable = s3c24xx_timer_disable_dyn_tick,
+ .reprogram = s3c24xx_timer_reprogram_dyn_tick,
+ .handler = s3c24xx_timer_handler_dyn_tick,
+};
+#endif /* CONFIG_NO_IDLE_HZ */
+
struct sys_timer s3c24xx_timer = {
.init = s3c2410_timer_init,
.offset = s3c2410_gettimeoffset,
- .resume = s3c2410_timer_setup
+ .resume = s3c2410_timer_resume,
+#ifdef CONFIG_NO_IDLE_HZ
+ .dyn_tick = &s3c24xx_dyn_tick_timer,
+#endif
};
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -0,0 +1,282 @@
+/* linux/arch/arm/plat-s3c64xx/clock.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX Base clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/regs-sys.h>
+#include <plat/regs-clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+struct clk clk_27m = {
+ .name = "clk_27m",
+ .id = -1,
+ .rate = 27000000,
+};
+
+static int clk_48m_ctrl(struct clk *clk, int enable)
+{
+ unsigned long flags;
+ u32 val;
+
+ /* can't rely on clock lock, this register has other usages */
+ local_irq_save(flags);
+
+ val = __raw_readl(S3C64XX_OTHERS);
+ if (enable)
+ val |= S3C64XX_OTHERS_USBMASK;
+ else
+ val &= ~S3C64XX_OTHERS_USBMASK;
+
+ __raw_writel(val, S3C64XX_OTHERS);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+struct clk clk_48m = {
+ .name = "clk_48m",
+ .id = -1,
+ .rate = 48000000,
+ .enable = clk_48m_ctrl,
+};
+
+static int inline s3c64xx_gate(void __iomem *reg,
+ struct clk *clk,
+ int enable)
+{
+ unsigned int ctrlbit = clk->ctrlbit;
+ u32 con;
+
+ con = __raw_readl(reg);
+
+ if (enable)
+ con |= ctrlbit;
+ else
+ con &= ~ctrlbit;
+
+ __raw_writel(con, reg);
+ return 0;
+}
+
+static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
+{
+ return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
+}
+
+static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
+{
+ return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
+}
+
+int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
+{
+ return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
+}
+
+static struct clk init_clocks_disable[] = {
+ {
+ .name = "nand",
+ .id = -1,
+ .parent = &clk_h,
+ }, {
+ .name = "adc",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_TSADC,
+ }, {
+ .name = "i2c",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_IIC,
+ }, {
+ .name = "iis",
+ .id = 0,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_IIS0,
+ }, {
+ .name = "iis",
+ .id = 1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_IIS1,
+ }, {
+ .name = "spi",
+ .id = 0,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_SPI0,
+ }, {
+ .name = "spi",
+ .id = 1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_SPI1,
+ }, {
+ .name = "48m",
+ .id = 0,
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
+ }, {
+ .name = "48m",
+ .id = 1,
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
+ }, {
+ .name = "48m",
+ .id = 2,
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
+ },
+};
+
+static struct clk init_clocks[] = {
+ {
+ .name = "lcd",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_LCD,
+ }, {
+ .name = "gpio",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_GPIO,
+ }, {
+ .name = "usb-host",
+ .id = -1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_UHOST,
+ }, {
+ .name = "hsmmc",
+ .id = 0,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
+ }, {
+ .name = "hsmmc",
+ .id = 1,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
+ }, {
+ .name = "hsmmc",
+ .id = 2,
+ .parent = &clk_h,
+ .enable = s3c64xx_hclk_ctrl,
+ .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
+ }, {
+ .name = "timers",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_PWM,
+ }, {
+ .name = "uart",
+ .id = 0,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_UART0,
+ }, {
+ .name = "uart",
+ .id = 1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_UART1,
+ }, {
+ .name = "uart",
+ .id = 2,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_UART2,
+ }, {
+ .name = "uart",
+ .id = 3,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_UART3,
+ }, {
+ .name = "rtc",
+ .id = -1,
+ .parent = &clk_p,
+ .enable = s3c64xx_pclk_ctrl,
+ .ctrlbit = S3C_CLKCON_PCLK_RTC,
+ }, {
+ .name = "watchdog",
+ .id = -1,
+ .parent = &clk_p,
+ .ctrlbit = S3C_CLKCON_PCLK_WDT,
+ }, {
+ .name = "ac97",
+ .id = -1,
+ .parent = &clk_p,
+ .ctrlbit = S3C_CLKCON_PCLK_AC97,
+ }
+};
+
+static struct clk *clks[] __initdata = {
+ &clk_ext,
+ &clk_epll,
+ &clk_27m,
+ &clk_48m,
+};
+
+void s3c64xx_register_clocks(void)
+{
+ struct clk *clkp;
+ int ret;
+ int ptr;
+
+ s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
+ clkp = init_clocks;
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+
+ clkp = init_clocks_disable;
+ for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+
+ (clkp->enable)(clkp, 0);
+ }
+
+ s3c_pwmclk_init();
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -0,0 +1,139 @@
+/* linux/arch/arm/plat-s3c64xx/cpu.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/regs-serial.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+
+#include <plat/s3c6400.h>
+#include <plat/s3c6410.h>
+
+/* table of supported CPUs */
+
+static const char name_s3c6400[] = "S3C6400";
+static const char name_s3c6410[] = "S3C6410";
+
+static struct cpu_table cpu_ids[] __initdata = {
+ {
+ .idcode = 0x36400000,
+ .idmask = 0xfffff000,
+ .map_io = s3c6400_map_io,
+ .init_clocks = s3c6400_init_clocks,
+ .init_uarts = s3c6400_init_uarts,
+ .init = s3c6400_init,
+ .name = name_s3c6400,
+ }, {
+ .idcode = 0x36410100,
+ .idmask = 0xffffff00,
+ .map_io = s3c6410_map_io,
+ .init_clocks = s3c6410_init_clocks,
+ .init_uarts = s3c6410_init_uarts,
+ .init = s3c6410_init,
+ .name = name_s3c6410,
+ },
+};
+
+/* minimal IO mapping */
+
+/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
+#define UART_OFFS (S3C_PA_UART & 0xfffff)
+
+static struct map_desc s3c_iodesc[] __initdata = {
+ {
+ .virtual = (unsigned long)S3C_VA_SYS,
+ .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
+ .pfn = __phys_to_pfn(S3C_PA_UART),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_VIC0,
+ .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
+ .length = SZ_16K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_VIC1,
+ .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
+ .length = SZ_16K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C_VA_TIMER,
+ .pfn = __phys_to_pfn(S3C_PA_TIMER),
+ .length = SZ_16K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C64XX_VA_GPIO,
+ .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S3C64XX_VA_MODEM,
+ .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
+
+struct sysdev_class s3c64xx_sysclass = {
+ .name = "s3c64xx-core",
+};
+
+static struct sys_device s3c64xx_sysdev = {
+ .cls = &s3c64xx_sysclass,
+};
+
+
+/* read cpu identification code */
+
+void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
+{
+ unsigned long idcode;
+
+ /* initialise the io descriptors we need for initialisation */
+ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
+ iotable_init(mach_desc, size);
+
+ idcode = __raw_readl(S3C_VA_SYS + 0x118);
+ s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
+
+static __init int s3c64xx_sysdev_init(void)
+{
+ sysdev_class_register(&s3c64xx_sysclass);
+ return sysdev_register(&s3c64xx_sysdev);
+}
+
+core_initcall(s3c64xx_sysdev_init);
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dev-uart.c
@@ -0,0 +1,176 @@
+/* linux/arch/arm/plat-s3c64xx/dev-uart.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Base S3C64XX UART resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+/* Serial port registrations */
+
+/* 64xx uarts are closer together */
+
+static struct resource s3c64xx_uart0_resource[] = {
+ [0] = {
+ .start = S3C_PA_UART0,
+ .end = S3C_PA_UART0 + 0x100,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX0,
+ .end = IRQ_S3CUART_RX0,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_S3CUART_TX0,
+ .end = IRQ_S3CUART_TX0,
+ .flags = IORESOURCE_IRQ,
+
+ },
+ [3] = {
+ .start = IRQ_S3CUART_ERR0,
+ .end = IRQ_S3CUART_ERR0,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct resource s3c64xx_uart1_resource[] = {
+ [0] = {
+ .start = S3C_PA_UART1,
+ .end = S3C_PA_UART1 + 0x100,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX1,
+ .end = IRQ_S3CUART_RX1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_S3CUART_TX1,
+ .end = IRQ_S3CUART_TX1,
+ .flags = IORESOURCE_IRQ,
+
+ },
+ [3] = {
+ .start = IRQ_S3CUART_ERR1,
+ .end = IRQ_S3CUART_ERR1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource s3c6xx_uart2_resource[] = {
+ [0] = {
+ .start = S3C_PA_UART2,
+ .end = S3C_PA_UART2 + 0x100,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX2,
+ .end = IRQ_S3CUART_RX2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_S3CUART_TX2,
+ .end = IRQ_S3CUART_TX2,
+ .flags = IORESOURCE_IRQ,
+
+ },
+ [3] = {
+ .start = IRQ_S3CUART_ERR2,
+ .end = IRQ_S3CUART_ERR2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource s3c64xx_uart3_resource[] = {
+ [0] = {
+ .start = S3C_PA_UART3,
+ .end = S3C_PA_UART3 + 0x100,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_S3CUART_RX3,
+ .end = IRQ_S3CUART_RX3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_S3CUART_TX3,
+ .end = IRQ_S3CUART_TX3,
+ .flags = IORESOURCE_IRQ,
+
+ },
+ [3] = {
+ .start = IRQ_S3CUART_ERR3,
+ .end = IRQ_S3CUART_ERR3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
+ [0] = {
+ .resources = s3c64xx_uart0_resource,
+ .nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource),
+ },
+ [1] = {
+ .resources = s3c64xx_uart1_resource,
+ .nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource),
+ },
+ [2] = {
+ .resources = s3c6xx_uart2_resource,
+ .nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource),
+ },
+ [3] = {
+ .resources = s3c64xx_uart3_resource,
+ .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource),
+ },
+};
+
+/* uart devices */
+
+static struct platform_device s3c24xx_uart_device0 = {
+ .id = 0,
+};
+
+static struct platform_device s3c24xx_uart_device1 = {
+ .id = 1,
+};
+
+static struct platform_device s3c24xx_uart_device2 = {
+ .id = 2,
+};
+
+static struct platform_device s3c24xx_uart_device3 = {
+ .id = 3,
+};
+
+struct platform_device *s3c24xx_uart_src[4] = {
+ &s3c24xx_uart_device0,
+ &s3c24xx_uart_device1,
+ &s3c24xx_uart_device2,
+ &s3c24xx_uart_device3,
+};
+
+struct platform_device *s3c24xx_uart_devs[4] = {
+};
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -0,0 +1,428 @@
+/* arch/arm/plat-s3c64xx/gpiolib.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/gpio.h>
+#include <mach/gpio-core.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/regs-gpio.h>
+
+/* GPIO bank summary:
+ *
+ * Bank GPIOs Style SlpCon ExtInt Group
+ * A 8 4Bit Yes 1
+ * B 7 4Bit Yes 1
+ * C 8 4Bit Yes 2
+ * D 5 4Bit Yes 3
+ * E 5 4Bit Yes None
+ * F 16 2Bit Yes 4 [1]
+ * G 7 4Bit Yes 5
+ * H 10 4Bit[2] Yes 6
+ * I 16 2Bit Yes None
+ * J 12 2Bit Yes None
+ * K 16 4Bit[2] No None
+ * L 15 4Bit[2] No None
+ * M 6 4Bit No IRQ_EINT
+ * N 16 2Bit No IRQ_EINT
+ * O 16 2Bit Yes 7
+ * P 15 2Bit Yes 8
+ * Q 9 2Bit Yes 9
+ *
+ * [1] BANKF pins 14,15 do not form part of the external interrupt sources
+ * [2] BANK has two control registers, GPxCON0 and GPxCON1
+ */
+
+#define OFF_GPCON (0x00)
+#define OFF_GPDAT (0x04)
+
+#define con_4bit_shift(__off) ((__off) * 4)
+
+#if 1
+#define gpio_dbg(x...) do { } while(0)
+#else
+#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
+#endif
+
+/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
+ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
+ * following example:
+ *
+ * base + 0x00: Control register, 4 bits per gpio
+ * gpio n: 4 bits starting at (4*n)
+ * 0000 = input, 0001 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ * bit n: data bit n
+ *
+ * Note, since the data register is one bit per gpio and is at base + 0x4
+ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
+ * the output.
+*/
+
+static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ unsigned long con;
+
+ con = __raw_readl(base + OFF_GPCON);
+ con &= ~(0xf << con_4bit_shift(offset));
+ __raw_writel(con, base + OFF_GPCON);
+
+ gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
+
+ return 0;
+}
+
+static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ unsigned long con;
+ unsigned long dat;
+
+ con = __raw_readl(base + OFF_GPCON);
+ con &= ~(0xf << con_4bit_shift(offset));
+ con |= 0x1 << con_4bit_shift(offset);
+
+ dat = __raw_readl(base + OFF_GPDAT);
+ if (value)
+ dat |= 1 << offset;
+ else
+ dat &= ~(1 << offset);
+
+ __raw_writel(dat, base + OFF_GPDAT);
+ __raw_writel(con, base + OFF_GPCON);
+ __raw_writel(dat, base + OFF_GPDAT);
+
+ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
+
+ return 0;
+}
+
+/* The next set of routines are for the case where the GPIO configuration
+ * registers are 4 bits per GPIO but there is more than one register (the
+ * bank has more than 8 GPIOs.
+ *
+ * This case is the similar to the 4 bit case, but the registers are as
+ * follows:
+ *
+ * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
+ * gpio n: 4 bits starting at (4*n)
+ * 0000 = input, 0001 = output, others mean special-function
+ * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
+ * gpio n: 4 bits starting at (4*n)
+ * 0000 = input, 0001 = output, others mean special-function
+ * base + 0x08: Data register, 1 bit per gpio
+ * bit n: data bit n
+ *
+ * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
+ * store the 'base + 0x4' address so that these routines see the data
+ * register at ourchip->base + 0x04.
+*/
+
+static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ void __iomem *regcon = base;
+ unsigned long con;
+
+ if (offset > 7)
+ offset -= 8;
+ else
+ regcon -= 4;
+
+ con = __raw_readl(regcon);
+ con &= ~(0xf << con_4bit_shift(offset));
+ __raw_writel(con, regcon);
+
+ gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
+
+ return 0;
+
+}
+
+static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+ void __iomem *base = ourchip->base;
+ void __iomem *regcon = base;
+ unsigned long con;
+ unsigned long dat;
+
+ if (offset > 7)
+ offset -= 8;
+ else
+ regcon -= 4;
+
+ con = __raw_readl(regcon);
+ con &= ~(0xf << con_4bit_shift(offset));
+ con |= 0x1 << con_4bit_shift(offset);
+
+ dat = __raw_readl(base + OFF_GPDAT);
+ if (value)
+ dat |= 1 << offset;
+ else
+ dat &= ~(1 << offset);
+
+ __raw_writel(dat, base + OFF_GPDAT);
+ __raw_writel(con, regcon);
+ __raw_writel(dat, base + OFF_GPDAT);
+
+ gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
+
+ return 0;
+}
+
+static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
+ .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
+ .cfg_eint = 7,
+ .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
+ .cfg_eint = 3,
+ .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_chip gpio_4bit[] = {
+ {
+ .base = S3C64XX_GPA_BASE,
+ .config = &gpio_4bit_cfg_eint0111,
+ .chip = {
+ .base = S3C64XX_GPA(0),
+ .ngpio = S3C64XX_GPIO_A_NR,
+ .label = "GPA",
+ },
+ }, {
+ .base = S3C64XX_GPB_BASE,
+ .config = &gpio_4bit_cfg_eint0111,
+ .chip = {
+ .base = S3C64XX_GPB(0),
+ .ngpio = S3C64XX_GPIO_B_NR,
+ .label = "GPB",
+ },
+ }, {
+ .base = S3C64XX_GPC_BASE,
+ .config = &gpio_4bit_cfg_eint0111,
+ .chip = {
+ .base = S3C64XX_GPC(0),
+ .ngpio = S3C64XX_GPIO_C_NR,
+ .label = "GPC",
+ },
+ }, {
+ .base = S3C64XX_GPD_BASE,
+ .config = &gpio_4bit_cfg_eint0111,
+ .chip = {
+ .base = S3C64XX_GPD(0),
+ .ngpio = S3C64XX_GPIO_D_NR,
+ .label = "GPD",
+ },
+ }, {
+ .base = S3C64XX_GPE_BASE,
+ .config = &gpio_4bit_cfg_noint,
+ .chip = {
+ .base = S3C64XX_GPE(0),
+ .ngpio = S3C64XX_GPIO_E_NR,
+ .label = "GPE",
+ },
+ }, {
+ .base = S3C64XX_GPG_BASE,
+ .config = &gpio_4bit_cfg_eint0111,
+ .chip = {
+ .base = S3C64XX_GPG(0),
+ .ngpio = S3C64XX_GPIO_G_NR,
+ .label = "GPG",
+ },
+ }, {
+ .base = S3C64XX_GPM_BASE,
+ .config = &gpio_4bit_cfg_eint0011,
+ .chip = {
+ .base = S3C64XX_GPM(0),
+ .ngpio = S3C64XX_GPIO_M_NR,
+ .label = "GPM",
+ },
+ },
+};
+
+static struct s3c_gpio_chip gpio_4bit2[] = {
+ {
+ .base = S3C64XX_GPH_BASE + 0x4,
+ .config = &gpio_4bit_cfg_eint0111,
+ .chip = {
+ .base = S3C64XX_GPH(0),
+ .ngpio = S3C64XX_GPIO_H_NR,
+ .label = "GPH",
+ },
+ }, {
+ .base = S3C64XX_GPK_BASE + 0x4,
+ .config = &gpio_4bit_cfg_noint,
+ .chip = {
+ .base = S3C64XX_GPK(0),
+ .ngpio = S3C64XX_GPIO_K_NR,
+ .label = "GPK",
+ },
+ }, {
+ .base = S3C64XX_GPL_BASE + 0x4,
+ .config = &gpio_4bit_cfg_eint0011,
+ .chip = {
+ .base = S3C64XX_GPL(0),
+ .ngpio = S3C64XX_GPIO_L_NR,
+ .label = "GPL",
+ },
+ },
+};
+
+static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
+ .set_config = s3c_gpio_setcfg_s3c24xx,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
+ .cfg_eint = 2,
+ .set_config = s3c_gpio_setcfg_s3c24xx,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
+ .cfg_eint = 3,
+ .set_config = s3c_gpio_setcfg_s3c24xx,
+ .set_pull = s3c_gpio_setpull_updown,
+ .get_pull = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_chip gpio_2bit[] = {
+ {
+ .base = S3C64XX_GPF_BASE,
+ .config = &gpio_2bit_cfg_eint11,
+ .chip = {
+ .base = S3C64XX_GPF(0),
+ .ngpio = S3C64XX_GPIO_F_NR,
+ .label = "GPF",
+ },
+ }, {
+ .base = S3C64XX_GPI_BASE,
+ .config = &gpio_2bit_cfg_noint,
+ .chip = {
+ .base = S3C64XX_GPI(0),
+ .ngpio = S3C64XX_GPIO_I_NR,
+ .label = "GPI",
+ },
+ }, {
+ .base = S3C64XX_GPJ_BASE,
+ .config = &gpio_2bit_cfg_noint,
+ .chip = {
+ .base = S3C64XX_GPJ(0),
+ .ngpio = S3C64XX_GPIO_J_NR,
+ .label = "GPJ",
+ },
+ }, {
+ .base = S3C64XX_GPN_BASE,
+ .config = &gpio_2bit_cfg_eint10,
+ .chip = {
+ .base = S3C64XX_GPN(0),
+ .ngpio = S3C64XX_GPIO_N_NR,
+ .label = "GPN",
+ },
+ }, {
+ .base = S3C64XX_GPO_BASE,
+ .config = &gpio_2bit_cfg_eint11,
+ .chip = {
+ .base = S3C64XX_GPO(0),
+ .ngpio = S3C64XX_GPIO_O_NR,
+ .label = "GPO",
+ },
+ }, {
+ .base = S3C64XX_GPP_BASE,
+ .config = &gpio_2bit_cfg_eint11,
+ .chip = {
+ .base = S3C64XX_GPP(0),
+ .ngpio = S3C64XX_GPIO_P_NR,
+ .label = "GPP",
+ },
+ }, {
+ .base = S3C64XX_GPQ_BASE,
+ .config = &gpio_2bit_cfg_eint11,
+ .chip = {
+ .base = S3C64XX_GPQ(0),
+ .ngpio = S3C64XX_GPIO_Q_NR,
+ .label = "GPQ",
+ },
+ },
+};
+
+static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
+{
+ chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
+ chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
+ chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
+{
+ chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
+ chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
+ chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+}
+
+static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
+{
+ chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
+}
+
+static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
+ int nr_chips,
+ void (*fn)(struct s3c_gpio_chip *))
+{
+ for (; nr_chips > 0; nr_chips--, chips++) {
+ if (fn)
+ (fn)(chips);
+ s3c_gpiolib_add(chips);
+ }
+}
+
+static __init int s3c64xx_gpiolib_init(void)
+{
+ s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
+ s3c64xx_gpiolib_add_4bit);
+
+ s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
+ s3c64xx_gpiolib_add_4bit2);
+
+ s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
+ s3c64xx_gpiolib_add_2bit);
+
+ return 0;
+}
+
+arch_initcall(s3c64xx_gpiolib_init);
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
@@ -0,0 +1,48 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank A register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
+#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
+#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
+#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
+#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
+
+#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
+#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
+
+#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
+#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
+
+#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
+#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
+
+#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
+#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
+
+#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
+#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
+
+#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
+#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
+
+#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
+#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
+
+#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
+#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
@@ -0,0 +1,60 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank B register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
+#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
+#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
+#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
+#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
+
+#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
+#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
+#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
+#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
+#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
+
+#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
+#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
+#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
+#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
+#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
+
+#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
+#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
+#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
+#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
+#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
+#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
+
+#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
+#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
+#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
+#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
+#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
+
+#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
+#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
+#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
+#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
+
+#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
+#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
+
+#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
+#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank C register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
+#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
+#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
+#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
+#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
+
+#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
+#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
+
+#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
+#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
+
+#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
+#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
+
+#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
+#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
+
+#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
+#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
+#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16)
+#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
+
+#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
+#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
+#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20)
+#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
+
+#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
+#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
+
+#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
+#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28)
+#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
@@ -0,0 +1,49 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank D register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
+#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
+#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
+#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
+#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
+
+#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
+#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
+#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
+#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
+
+#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
+#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
+#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
+#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
+
+#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
+#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
+#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
+#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
+
+#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
+#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
+#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
+#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
+
+#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
+#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
+#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
+#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank E register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
+#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
+#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
+#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
+#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
+
+#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
+#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
+#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
+
+#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
+#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
+#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
+
+#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
+#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
+#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
+
+#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
+#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
+#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
+
+#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
+#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
+#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
@@ -0,0 +1,71 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank F register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
+#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
+#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
+#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
+#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
+
+#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
+#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
+
+#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
+#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
+
+#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
+#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
+
+#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
+#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
+
+#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
+#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
+
+#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
+#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
+
+#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
+#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
+
+#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
+#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
+
+#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
+#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
+
+#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
+#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
+
+#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
+#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
+
+#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
+#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
+
+#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
+#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
+
+#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
+#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
+
+#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
+#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
+
+#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank G register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
+#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
+#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
+#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
+#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
+
+#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
+#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
+
+#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
+#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
+
+#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
+#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
+
+#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
+#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
+
+#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
+#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
+
+#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
+#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
@@ -0,0 +1,74 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank H register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
+#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
+#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
+#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
+#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
+#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
+
+#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
+#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
+#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
+
+#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
+#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
+#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
+
+#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
+#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
+#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
+
+#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
+#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
+#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
+
+#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
+#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
+#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
+
+#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
+#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
+#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
+
+#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
+#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
+#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
+
+#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
+#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
+#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
+#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
+#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
+#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
+
+#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
+#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
+#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
+#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
+#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
+#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
+
+#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
+#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
+#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
+#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
+#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
+
+#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
+#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
+#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
+#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
@@ -0,0 +1,40 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank I register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
+#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
+#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
+#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
+#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
+
+#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPI0_VD0 (0x02 << 0)
+#define S3C64XX_GPI1_VD1 (0x02 << 2)
+#define S3C64XX_GPI2_VD2 (0x02 << 4)
+#define S3C64XX_GPI3_VD3 (0x02 << 6)
+#define S3C64XX_GPI4_VD4 (0x02 << 8)
+#define S3C64XX_GPI5_VD5 (0x02 << 10)
+#define S3C64XX_GPI6_VD6 (0x02 << 12)
+#define S3C64XX_GPI7_VD7 (0x02 << 14)
+#define S3C64XX_GPI8_VD8 (0x02 << 16)
+#define S3C64XX_GPI9_VD9 (0x02 << 18)
+#define S3C64XX_GPI10_VD10 (0x02 << 20)
+#define S3C64XX_GPI11_VD11 (0x02 << 22)
+#define S3C64XX_GPI12_VD12 (0x02 << 24)
+#define S3C64XX_GPI13_VD13 (0x02 << 26)
+#define S3C64XX_GPI14_VD14 (0x02 << 28)
+#define S3C64XX_GPI15_VD15 (0x02 << 30)
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
@@ -0,0 +1,36 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank J register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
+#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
+#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
+#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
+#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
+
+#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPJ0_VD16 (0x02 << 0)
+#define S3C64XX_GPJ1_VD17 (0x02 << 2)
+#define S3C64XX_GPJ2_VD18 (0x02 << 4)
+#define S3C64XX_GPJ3_VD19 (0x02 << 6)
+#define S3C64XX_GPJ4_VD20 (0x02 << 8)
+#define S3C64XX_GPJ5_VD21 (0x02 << 10)
+#define S3C64XX_GPJ6_VD22 (0x02 << 12)
+#define S3C64XX_GPJ7_VD23 (0x02 << 14)
+#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
+#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
+#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
+#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
@@ -0,0 +1,54 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank N register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
+#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
+#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
+
+#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPN0_EINT0 (0x02 << 0)
+#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
+
+#define S3C64XX_GPN1_EINT1 (0x02 << 2)
+#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
+
+#define S3C64XX_GPN2_EINT2 (0x02 << 4)
+#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
+
+#define S3C64XX_GPN3_EINT3 (0x02 << 6)
+#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
+
+#define S3C64XX_GPN4_EINT4 (0x02 << 8)
+#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
+
+#define S3C64XX_GPN5_EINT5 (0x02 << 10)
+#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
+
+#define S3C64XX_GPN6_EINT6 (0x02 << 12)
+#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
+
+#define S3C64XX_GPN7_EINT7 (0x02 << 14)
+#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
+
+#define S3C64XX_GPN8_EINT8 (0x02 << 16)
+#define S3C64XX_GPN9_EINT9 (0x02 << 18)
+#define S3C64XX_GPN10_EINT10 (0x02 << 20)
+#define S3C64XX_GPN11_EINT11 (0x02 << 22)
+#define S3C64XX_GPN12_EINT12 (0x02 << 24)
+#define S3C64XX_GPN13_EINT13 (0x02 << 26)
+#define S3C64XX_GPN14_EINT14 (0x02 << 28)
+#define S3C64XX_GPN15_EINT15 (0x02 << 30)
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank O register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
+#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
+#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
+#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
+#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
+
+#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
+#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
+
+#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
+#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
+
+#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
+#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
+
+#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
+#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
+
+#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
+
+#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
+
+#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
+#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
+
+#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
+#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
+
+#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
+#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
+
+#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
+#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
+
+#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
+#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
+
+#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
+#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
+
+#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
+#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
+
+#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
+#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
+
+#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
+#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
+
+#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
+#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
@@ -0,0 +1,69 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank P register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
+#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
+#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
+#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
+#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
+
+#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
+#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
+
+#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
+#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
+
+#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
+#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
+
+#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
+#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
+
+#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
+#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
+
+#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
+#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
+
+#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
+#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
+
+#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
+#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
+
+#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
+#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
+
+#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
+#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
+
+#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
+#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
+
+#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
+#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
+
+#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
+#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
+
+#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
+#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
+
+#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
+#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
@@ -0,0 +1,46 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * GPIO Bank Q register and configuration definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
+#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
+#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
+#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
+#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
+
+#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
+#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
+
+#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
+#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
+
+#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
+#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
+
+#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
+
+#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
+
+#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
+
+#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
+
+#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
+
+#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
+#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
+
+#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
+#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -0,0 +1,202 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Common IRQ support
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_IRQS_H
+#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+
+#define S3C_IRQ_OFFSET (32)
+
+#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
+
+#define S3C_VIC0_BASE S3C_IRQ(0)
+#define S3C_VIC1_BASE S3C_IRQ(32)
+
+/* UART interrupts, each UART has 4 intterupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+
+#define IRQ_S3CUART_BASE0 (16)
+#define IRQ_S3CUART_BASE1 (20)
+#define IRQ_S3CUART_BASE2 (24)
+#define IRQ_S3CUART_BASE3 (28)
+
+#define UART_IRQ_RXD (0)
+#define UART_IRQ_ERR (1)
+#define UART_IRQ_TXD (2)
+#define UART_IRQ_MODEM (3)
+
+#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
+
+#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
+
+/* VIC based IRQs */
+
+#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
+#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
+
+/* VIC0 */
+
+#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
+#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
+#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
+#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
+#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
+#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
+#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
+#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
+#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
+#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
+#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
+#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
+#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
+#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
+#define IRQ_2D S3C64XX_IRQ_VIC0(11)
+#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
+#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
+#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
+#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
+#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
+#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
+#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
+#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
+#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
+#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
+#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
+#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
+#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
+#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
+#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
+#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
+#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
+#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
+#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
+#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
+
+/* VIC1 */
+
+#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
+#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
+#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
+#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
+#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
+#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
+#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
+#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
+#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
+#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
+#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
+#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
+#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
+#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
+#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
+#define IRQ_UHOST S3C64XX_IRQ_VIC1(15)
+#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
+#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
+#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
+#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
+#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
+#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
+#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
+#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
+#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
+#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
+#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
+#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
+#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
+#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
+#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
+#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
+#define IRQ_TC IRQ_PENDN
+#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
+
+#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
+
+#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
+#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
+#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
+#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
+#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
+
+/* compatibility for device defines */
+
+#define IRQ_IIC1 IRQ_S3C6410_IIC1
+
+/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
+ * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
+ * which we place after the pair of VICs. */
+
+#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
+
+#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
+#define IRQ_EINT(x) S3C_EINT(x)
+#define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0))
+
+/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
+ * that they are sourced from the GPIO pins but with a different scheme for
+ * priority and source indication.
+ *
+ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
+ * interrupts, but for historical reasons they are kept apart from these
+ * next interrupts.
+ *
+ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
+ * machine specific support files.
+ */
+
+#define IRQ_EINT_GROUP1_NR (15)
+#define IRQ_EINT_GROUP2_NR (8)
+#define IRQ_EINT_GROUP3_NR (5)
+#define IRQ_EINT_GROUP4_NR (14)
+#define IRQ_EINT_GROUP5_NR (7)
+#define IRQ_EINT_GROUP6_NR (10)
+#define IRQ_EINT_GROUP7_NR (16)
+#define IRQ_EINT_GROUP8_NR (15)
+#define IRQ_EINT_GROUP9_NR (9)
+
+#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
+#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
+#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
+#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
+#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
+#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
+#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
+#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
+#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
+#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
+
+#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x))
+
+/* Set the default NR_IRQS */
+
+#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
+
+#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/pll.h
@@ -0,0 +1,74 @@
+/* arch/arm/plat-s3c64xx/include/plat/pll.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX PLL code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
+#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
+#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
+#define S3C6400_PLL_MDIV_SHIFT (16)
+#define S3C6400_PLL_PDIV_SHIFT (8)
+#define S3C6400_PLL_SDIV_SHIFT (0)
+
+#include <asm/div64.h>
+
+static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
+ u32 pllcon)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
+ pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
+ sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+
+ return (unsigned long)fvco;
+}
+
+#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
+#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
+#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
+#define S3C6400_EPLL_MDIV_SHIFT (16)
+#define S3C6400_EPLL_PDIV_SHIFT (8)
+#define S3C6400_EPLL_SDIV_SHIFT (0)
+#define S3C6400_EPLL_KDIV_MASK (0xffff)
+
+static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
+{
+ unsigned long result;
+ u32 epll0 = __raw_readl(S3C_EPLL_CON0);
+ u32 epll1 = __raw_readl(S3C_EPLL_CON1);
+ u32 mdiv, pdiv, sdiv, kdiv;
+ u64 tmp;
+
+ mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
+ pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
+ sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
+ kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
+
+ /* We need to multiple baseclk by mdiv (the integer part) and kdiv
+ * which is in 2^16ths, so shift mdiv up (does not overflow) and
+ * add kdiv before multiplying. The use of tmp is to avoid any
+ * overflows before shifting bac down into result when multipling
+ * by the mdiv and kdiv pair.
+ */
+
+ tmp = baseclk;
+ tmp *= (mdiv << 16) + kdiv;
+ do_div(tmp, (pdiv << sdiv));
+ result = tmp >> 16;
+
+ return result;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/pm-core.h
@@ -0,0 +1,106 @@
+/* linux/arch/arm/plat-s3c64xx/include/plat/pm-core.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+ u32 tmp = __raw_readl(S3C_PCLK_GATE);
+
+ /* As a note, since the S3C64XX UARTs generally have multiple
+ * clock sources, we simply enable PCLK at the moment and hope
+ * that the resume settings for the UART are suitable for the
+ * use with PCLK.
+ */
+
+ tmp |= S3C_CLKCON_PCLK_UART0;
+ tmp |= S3C_CLKCON_PCLK_UART1;
+ tmp |= S3C_CLKCON_PCLK_UART2;
+ tmp |= S3C_CLKCON_PCLK_UART3;
+
+ __raw_writel(tmp, S3C_PCLK_GATE);
+ udelay(10);
+}
+
+static inline void s3c_pm_arch_clear_vic(void __iomem *base)
+{
+ __raw_writel(~0, base + VIC_INT_ENABLE_CLEAR);
+ __raw_writel(~0, base + VIC_INT_SOFT_CLEAR);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+ /* shutdown the VICs */
+ s3c_pm_arch_clear_vic(S3C_VA_VIC0);
+ s3c_pm_arch_clear_vic(S3C_VA_VIC1);
+
+ /* clear any pending EINT0 interrupts */
+ __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+}
+
+/* make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on */
+
+#define s3c_irqwake_eintallow ((1 << 28) - 1)
+#define s3c_irqwake_intallow (0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+ struct pm_uart_save *save)
+{
+ u32 ucon = __raw_readl(regs + S3C2410_UCON);
+ u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+ u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+ u32 new_ucon;
+ u32 delta;
+
+ /* S3C64XX UART blocks only support level interrupts, so ensure that
+ * when we restore unused UART blocks we force the level interrupt
+ * settigs. */
+ save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+ /* We have a constraint on changing the clock type of the UART
+ * between UCLKx and PCLK, so ensure that when we restore UCON
+ * that the CLK field is correctly modified if the bootloader
+ * has changed anything.
+ */
+ if (ucon_clk != save_clk) {
+ new_ucon = save->ucon;
+ delta = ucon_clk ^ save_clk;
+
+ /* change from UCLKx => wrong PCLK,
+ * either UCLK can be tested for by a bit-test
+ * with UCLK0 */
+ if (ucon_clk & S3C6400_UCON_UCLK0 &&
+ !(save_clk & S3C6400_UCON_UCLK0) &&
+ delta & S3C6400_UCON_PCLK2) {
+ new_ucon &= ~S3C6400_UCON_UCLK0;
+ } else if (delta == S3C6400_UCON_PCLK2) {
+ /* as an precaution, don't change from
+ * PCLK2 => PCLK or vice-versa */
+ new_ucon ^= S3C6400_UCON_PCLK2;
+ }
+
+ S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+ ucon, new_ucon, save->ucon);
+ save->ucon = new_ucon;
+ }
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -0,0 +1,225 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_CLOCK_H
+#define __PLAT_REGS_CLOCK_H __FILE__
+
+#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
+
+#define S3C_APLL_LOCK S3C_CLKREG(0x00)
+#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
+#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
+#define S3C_APLL_CON S3C_CLKREG(0x0C)
+#define S3C_MPLL_CON S3C_CLKREG(0x10)
+#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
+#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
+#define S3C_CLK_SRC S3C_CLKREG(0x1C)
+#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
+#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
+#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
+#define S3C_CLK_OUT S3C_CLKREG(0x2C)
+#define S3C_HCLK_GATE S3C_CLKREG(0x30)
+#define S3C_PCLK_GATE S3C_CLKREG(0x34)
+#define S3C_SCLK_GATE S3C_CLKREG(0x38)
+#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
+
+/* CLKDIV0 */
+#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28)
+#define S3C6400_CLKDIV0_MFC_SHIFT (28)
+#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24)
+#define S3C6400_CLKDIV0_JPEG_SHIFT (24)
+#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20)
+#define S3C6400_CLKDIV0_CAM_SHIFT (20)
+#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18)
+#define S3C6400_CLKDIV0_SECURITY_SHIFT (18)
+#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
+#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
+#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
+#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
+#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
+#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
+#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
+#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
+#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0)
+#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0)
+#define S3C6400_CLKDIV0_ARM_SHIFT (0)
+
+/* CLKDIV1 */
+#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24)
+#define S3C6410_CLKDIV1_FIMC_SHIFT (24)
+#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20)
+#define S3C6400_CLKDIV1_UHOST_SHIFT (20)
+#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16)
+#define S3C6400_CLKDIV1_SCALER_SHIFT (16)
+#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12)
+#define S3C6400_CLKDIV1_LCD_SHIFT (12)
+#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8)
+#define S3C6400_CLKDIV1_MMC2_SHIFT (8)
+#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4)
+#define S3C6400_CLKDIV1_MMC1_SHIFT (4)
+#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0)
+#define S3C6400_CLKDIV1_MMC0_SHIFT (0)
+
+/* CLKDIV2 */
+#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24)
+#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24)
+#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20)
+#define S3C6400_CLKDIV2_IRDA_SHIFT (20)
+#define S3C6400_CLKDIV2_UART_MASK (0xf << 16)
+#define S3C6400_CLKDIV2_UART_SHIFT (16)
+#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12)
+#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12)
+#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8)
+#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8)
+#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4)
+#define S3C6400_CLKDIV2_SPI1_SHIFT (4)
+#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0)
+#define S3C6400_CLKDIV2_SPI0_SHIFT (0)
+
+/* HCLK GATE Registers */
+#define S3C_CLKCON_HCLK_BUS (1<<30)
+#define S3C_CLKCON_HCLK_SECUR (1<<29)
+#define S3C_CLKCON_HCLK_SDMA1 (1<<28)
+#define S3C_CLKCON_HCLK_SDMA2 (1<<27)
+#define S3C_CLKCON_HCLK_UHOST (1<<26)
+#define S3C_CLKCON_HCLK_IROM (1<<25)
+#define S3C_CLKCON_HCLK_DDR1 (1<<24)
+#define S3C_CLKCON_HCLK_DDR0 (1<<23)
+#define S3C_CLKCON_HCLK_MEM1 (1<<22)
+#define S3C_CLKCON_HCLK_MEM0 (1<<21)
+#define S3C_CLKCON_HCLK_USB (1<<20)
+#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
+#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
+#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
+#define S3C_CLKCON_HCLK_MDP (1<<16)
+#define S3C_CLKCON_HCLK_DHOST (1<<15)
+#define S3C_CLKCON_HCLK_IHOST (1<<14)
+#define S3C_CLKCON_HCLK_DMA1 (1<<13)
+#define S3C_CLKCON_HCLK_DMA0 (1<<12)
+#define S3C_CLKCON_HCLK_JPEG (1<<11)
+#define S3C_CLKCON_HCLK_CAMIF (1<<10)
+#define S3C_CLKCON_HCLK_SCALER (1<<9)
+#define S3C_CLKCON_HCLK_2D (1<<8)
+#define S3C_CLKCON_HCLK_TV (1<<7)
+#define S3C_CLKCON_HCLK_POST0 (1<<5)
+#define S3C_CLKCON_HCLK_ROT (1<<4)
+#define S3C_CLKCON_HCLK_LCD (1<<3)
+#define S3C_CLKCON_HCLK_TZIC (1<<2)
+#define S3C_CLKCON_HCLK_INTC (1<<1)
+#define S3C_CLKCON_HCLK_MFC (1<<0)
+
+/* PCLK GATE Registers */
+#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
+#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
+#define S3C_CLKCON_PCLK_SKEY (1<<24)
+#define S3C_CLKCON_PCLK_CHIPID (1<<23)
+#define S3C_CLKCON_PCLK_SPI1 (1<<22)
+#define S3C_CLKCON_PCLK_SPI0 (1<<21)
+#define S3C_CLKCON_PCLK_HSIRX (1<<20)
+#define S3C_CLKCON_PCLK_HSITX (1<<19)
+#define S3C_CLKCON_PCLK_GPIO (1<<18)
+#define S3C_CLKCON_PCLK_IIC (1<<17)
+#define S3C_CLKCON_PCLK_IIS1 (1<<16)
+#define S3C_CLKCON_PCLK_IIS0 (1<<15)
+#define S3C_CLKCON_PCLK_AC97 (1<<14)
+#define S3C_CLKCON_PCLK_TZPC (1<<13)
+#define S3C_CLKCON_PCLK_TSADC (1<<12)
+#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
+#define S3C_CLKCON_PCLK_IRDA (1<<10)
+#define S3C_CLKCON_PCLK_PCM1 (1<<9)
+#define S3C_CLKCON_PCLK_PCM0 (1<<8)
+#define S3C_CLKCON_PCLK_PWM (1<<7)
+#define S3C_CLKCON_PCLK_RTC (1<<6)
+#define S3C_CLKCON_PCLK_WDT (1<<5)
+#define S3C_CLKCON_PCLK_UART3 (1<<4)
+#define S3C_CLKCON_PCLK_UART2 (1<<3)
+#define S3C_CLKCON_PCLK_UART1 (1<<2)
+#define S3C_CLKCON_PCLK_UART0 (1<<1)
+#define S3C_CLKCON_PCLK_MFC (1<<0)
+
+/* SCLK GATE Registers */
+#define S3C_CLKCON_SCLK_UHOST (1<<30)
+#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
+#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
+#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
+#define S3C_CLKCON_SCLK_MMC2 (1<<26)
+#define S3C_CLKCON_SCLK_MMC1 (1<<25)
+#define S3C_CLKCON_SCLK_MMC0 (1<<24)
+#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
+#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
+#define S3C_CLKCON_SCLK_SPI1 (1<<21)
+#define S3C_CLKCON_SCLK_SPI0 (1<<20)
+#define S3C_CLKCON_SCLK_DAC27 (1<<19)
+#define S3C_CLKCON_SCLK_TV27 (1<<18)
+#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
+#define S3C_CLKCON_SCLK_SCALER (1<<16)
+#define S3C_CLKCON_SCLK_LCD27 (1<<15)
+#define S3C_CLKCON_SCLK_LCD (1<<14)
+#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
+#define S3C6410_CLKCON_FIMC (1<<13)
+#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
+#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
+#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
+#define S3C_CLKCON_SCLK_POST0 (1<<10)
+#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
+#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
+#define S3C_CLKCON_SCLK_SECUR (1<<7)
+#define S3C_CLKCON_SCLK_IRDA (1<<6)
+#define S3C_CLKCON_SCLK_UART (1<<5)
+#define S3C_CLKCON_SCLK_ONENAND (1<<4)
+#define S3C_CLKCON_SCLK_MFC (1<<3)
+#define S3C_CLKCON_SCLK_CAM (1<<2)
+#define S3C_CLKCON_SCLK_JPEG (1<<1)
+
+/* CLKSRC */
+
+#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
+#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
+#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
+#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
+#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
+#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
+#define S3C6400_CLKSRC_MFC (1 << 4)
+
+#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31)
+#define S3C6410_CLKSRC_TV27_SHIFT (31)
+#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30)
+#define S3C6410_CLKSRC_DAC27_SHIFT (30)
+#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28)
+#define S3C6400_CLKSRC_SCALER_SHIFT (28)
+#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26)
+#define S3C6400_CLKSRC_LCD_SHIFT (26)
+#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24)
+#define S3C6400_CLKSRC_IRDA_SHIFT (24)
+#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22)
+#define S3C6400_CLKSRC_MMC2_SHIFT (22)
+#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
+#define S3C6400_CLKSRC_MMC1_SHIFT (20)
+#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
+#define S3C6400_CLKSRC_MMC0_SHIFT (18)
+#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
+#define S3C6400_CLKSRC_SPI1_SHIFT (16)
+#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
+#define S3C6400_CLKSRC_SPI0_SHIFT (14)
+#define S3C6400_CLKSRC_UART_MASK (0x1 << 13)
+#define S3C6400_CLKSRC_UART_SHIFT (13)
+#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10)
+#define S3C6400_CLKSRC_AUDIO1_SHIFT (10)
+#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7)
+#define S3C6400_CLKSRC_AUDIO0_SHIFT (7)
+#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5)
+#define S3C6400_CLKSRC_UHOST_SHIFT (5)
+
+
+#endif /* _PLAT_REGS_CLOCK_H */
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
@@ -0,0 +1,187 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO register definitions
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
+#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
+
+/* Base addresses for each of the banks */
+
+#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg))
+
+#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)
+#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)
+#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)
+#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)
+#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)
+#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)
+#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)
+#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)
+#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)
+#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)
+#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800)
+#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810)
+#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820)
+#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830)
+#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140)
+#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160)
+#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180)
+
+/* SPCON */
+
+#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0)
+
+#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30)
+#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30)
+#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30)
+
+#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28)
+#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28)
+
+#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26)
+#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26)
+
+#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24)
+#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24)
+#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24)
+
+#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22)
+#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22)
+#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22)
+
+#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21)
+
+#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18)
+#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18)
+
+#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16)
+#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16)
+
+#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14)
+#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14)
+
+#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12)
+#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12)
+
+#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8)
+#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8)
+
+#define S3C64XX_SPCON_USBH_DMPD (1 << 7)
+#define S3C64XX_SPCON_USBH_DPPD (1 << 6)
+#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5)
+#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4)
+#define S3C64XX_SPCON_USBH_SUSPND (1 << 3)
+
+#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0)
+#define S3C64XX_SPCON_LCD_SEL_SHIFT (0)
+#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0)
+#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0)
+#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0)
+
+
+/* External interrupt registers */
+
+#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200)
+#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204)
+#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208)
+#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C)
+#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210)
+
+#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220)
+#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224)
+#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228)
+#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C)
+#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230)
+
+#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240)
+#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244)
+#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248)
+#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C)
+#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250)
+
+#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260)
+#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264)
+#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268)
+#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C)
+#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270)
+
+#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280)
+#define S3C64XX_PRIORITY_ARB(x) (1 << (x))
+
+#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284)
+#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288)
+
+#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
+#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
+#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
+#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
+#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
+#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
+
+#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
+#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
+
+/* GPIO sleep configuration */
+
+#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880)
+
+#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14)
+#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5)
+
+#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12)
+#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12)
+
+#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0)
+#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0)
+
+
+#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930)
+
+#define S3C64XX_SLPEN_USE_xSLP (1 << 0)
+#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1)
+
+#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio-memport.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio-memport.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - GPIO memory port register definitions
+ */
+
+#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H
+#define __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__
+
+#define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
+#define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
+
+#define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
+#define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
+#define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
+
+#define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
+#define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
+
+#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_MEMPORT_H */
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-modem.h
@@ -0,0 +1,31 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-modem.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - modem block registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_MODEM_H
+#define __PLAT_S3C64XX_REGS_MODEM_H __FILE__
+
+#define S3C64XX_MODEMREG(x) (S3C64XX_VA_MODEM + (x))
+
+#define S3C64XX_MODEM_INT2AP S3C64XX_MODEMREG(0x0)
+#define S3C64XX_MODEM_INT2MODEM S3C64XX_MODEMREG(0x4)
+#define S3C64XX_MODEM_MIFCON S3C64XX_MODEMREG(0x8)
+#define S3C64XX_MODEM_MIFPCON S3C64XX_MODEMREG(0xC)
+#define S3C64XX_MODEM_INTCLR S3C64XX_MODEMREG(0x10)
+#define S3C64XX_MODEM_DMA_TXADDR S3C64XX_MODEMREG(0x14)
+#define S3C64XX_MODEM_DMA_RXADDR S3C64XX_MODEMREG(0x18)
+
+#define MIFPCON_INT2M_LEVEL (1 << 4)
+#define MIFPCON_LCD_BYPASS (1 << 3)
+
+#endif /* __PLAT_S3C64XX_REGS_MODEM_H */
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
@@ -0,0 +1,116 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - syscon power and sleep control registers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
+#define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
+
+#define S3C64XX_PWR_CFG S3C_SYSREG(0x804)
+
+#define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17)
+#define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16)
+#define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15)
+#define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14)
+#define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13)
+#define S3C64XX_PWRCFG_TS_DISABLE (1 << 12)
+#define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11)
+#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10)
+#define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9)
+#define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8)
+#define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7)
+
+#define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5)
+#define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5)
+#define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5)
+
+#define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3)
+#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3)
+
+#define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2)
+#define S3C64XX_PWRCFG_OSC27_EN (1 << 0)
+
+#define S3C64XX_EINT_MASK S3C_SYSREG(0x808)
+
+#define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810)
+
+#define S3C64XX_NORMALCFG_IROM_ON (1 << 30)
+#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16)
+#define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15)
+#define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14)
+#define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13)
+#define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12)
+#define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10)
+#define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9)
+
+#define S3C64XX_STOP_CFG S3C_SYSREG(0x814)
+
+#define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29)
+#define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20)
+#define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17)
+#define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8)
+#define S3C64XX_STOPCFG_OSC_EN (1 << 0)
+
+#define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818)
+
+#define S3C64XX_SLEEPCFG_OSC_EN (1 << 0)
+
+#define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c)
+
+#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6)
+#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5)
+#define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4)
+#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3)
+#define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2)
+#define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1)
+#define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0)
+
+#define S3C64XX_OSC_STABLE S3C_SYSREG(0x824)
+#define S3C64XX_PWR_STABLE S3C_SYSREG(0x828)
+
+#define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908)
+
+#define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11)
+#define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10)
+#define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9)
+#define S3C64XX_WAKEUPSTAT_HSI (1 << 8)
+#define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6)
+#define S3C64XX_WAKEUPSTAT_MSM (1 << 5)
+#define S3C64XX_WAKEUPSTAT_KEY (1 << 4)
+#define S3C64XX_WAKEUPSTAT_TS (1 << 3)
+#define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2)
+#define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1)
+#define S3C64XX_WAKEUPSTAT_EINT (1 << 0)
+
+#define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c)
+
+#define S3C64XX_BLKPWRSTAT_G (1 << 7)
+#define S3C64XX_BLKPWRSTAT_ETM (1 << 6)
+#define S3C64XX_BLKPWRSTAT_S (1 << 5)
+#define S3C64XX_BLKPWRSTAT_F (1 << 4)
+#define S3C64XX_BLKPWRSTAT_P (1 << 3)
+#define S3C64XX_BLKPWRSTAT_I (1 << 2)
+#define S3C64XX_BLKPWRSTAT_V (1 << 1)
+#define S3C64XX_BLKPWRSTAT_TOP (1 << 0)
+
+#define S3C64XX_INFORM0 S3C_SYSREG(0xA00)
+#define S3C64XX_INFORM1 S3C_SYSREG(0xA04)
+#define S3C64XX_INFORM2 S3C_SYSREG(0xA08)
+#define S3C64XX_INFORM3 S3C_SYSREG(0xA0C)
+
+#endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
@@ -0,0 +1,28 @@
+/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX system register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_SYS_H
+#define __PLAT_REGS_SYS_H __FILE__
+
+#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
+
+#define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
+#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
+#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
+
+#define S3C64XX_OTHERS S3C_SYSREG(0x900)
+
+#define S3C64XX_OTHERS_USBMASK (1 << 16)
+
+#endif /* _PLAT_REGS_SYS_H */
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
@@ -0,0 +1,35 @@
+/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Header file for s3c6400 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S3C6400 related SoCs */
+
+extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c6400_register_clocks(void);
+extern void s3c6400_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S3C6400
+
+extern int s3c6400_init(void);
+extern void s3c6400_map_io(void);
+extern void s3c6400_init_clocks(int xtal);
+
+#define s3c6400_init_uarts s3c6400_common_init_uarts
+
+#else
+#define s3c6400_init_clocks NULL
+#define s3c6400_init_uarts NULL
+#define s3c6400_map_io NULL
+#define s3c6400_init NULL
+#endif
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h
@@ -0,0 +1,29 @@
+/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Header file for s3c6410 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifdef CONFIG_CPU_S3C6410
+
+extern int s3c6410_init(void);
+extern void s3c6410_init_irq(void);
+extern void s3c6410_map_io(void);
+extern void s3c6410_init_clocks(int xtal);
+
+#define s3c6410_init_uarts s3c6400_common_init_uarts
+
+#else
+#define s3c6410_init_clocks NULL
+#define s3c6410_init_uarts NULL
+#define s3c6410_map_io NULL
+#define s3c6410_init NULL
+#endif
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -0,0 +1,256 @@
+/* arch/arm/plat-s3c64xx/irq.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Interrupt handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/serial_core.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/vic.h>
+
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+#include <plat/regs-timer.h>
+#include <plat/cpu.h>
+
+/* Timer interrupt handling */
+
+static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
+{
+ generic_handle_irq(sub_irq);
+}
+
+static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_timer(irq, IRQ_TIMER0);
+}
+
+static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_timer(irq, IRQ_TIMER1);
+}
+
+static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_timer(irq, IRQ_TIMER2);
+}
+
+static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_timer(irq, IRQ_TIMER3);
+}
+
+static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_timer(irq, IRQ_TIMER4);
+}
+
+/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
+
+static void s3c_irq_timer_mask(unsigned int irq)
+{
+ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+ reg &= 0x1f; /* mask out pending interrupts */
+ reg &= ~(1 << (irq - IRQ_TIMER0));
+ __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static void s3c_irq_timer_unmask(unsigned int irq)
+{
+ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+ reg &= 0x1f; /* mask out pending interrupts */
+ reg |= 1 << (irq - IRQ_TIMER0);
+ __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static void s3c_irq_timer_ack(unsigned int irq)
+{
+ u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+
+ reg &= 0x1f;
+ reg |= (1 << 5) << (irq - IRQ_TIMER0);
+ __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+
+static struct irq_chip s3c_irq_timer = {
+ .name = "s3c-timer",
+ .mask = s3c_irq_timer_mask,
+ .unmask = s3c_irq_timer_unmask,
+ .ack = s3c_irq_timer_ack,
+};
+
+struct uart_irq {
+ void __iomem *regs;
+ unsigned int base_irq;
+ unsigned int parent_irq;
+};
+
+/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
+ * are consecutive when looking up the interrupt in the demux routines.
+ */
+static struct uart_irq uart_irqs[] = {
+ [0] = {
+ .regs = S3C_VA_UART0,
+ .base_irq = IRQ_S3CUART_BASE0,
+ .parent_irq = IRQ_UART0,
+ },
+ [1] = {
+ .regs = S3C_VA_UART1,
+ .base_irq = IRQ_S3CUART_BASE1,
+ .parent_irq = IRQ_UART1,
+ },
+ [2] = {
+ .regs = S3C_VA_UART2,
+ .base_irq = IRQ_S3CUART_BASE2,
+ .parent_irq = IRQ_UART2,
+ },
+ [3] = {
+ .regs = S3C_VA_UART3,
+ .base_irq = IRQ_S3CUART_BASE3,
+ .parent_irq = IRQ_UART3,
+ },
+};
+
+static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
+{
+ struct uart_irq *uirq = get_irq_chip_data(irq);
+ return uirq->regs;
+}
+
+static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
+{
+ return irq & 3;
+}
+
+/* UART interrupt registers, not worth adding to seperate include header */
+
+static void s3c_irq_uart_mask(unsigned int irq)
+{
+ void __iomem *regs = s3c_irq_uart_base(irq);
+ unsigned int bit = s3c_irq_uart_bit(irq);
+ u32 reg;
+
+ reg = __raw_readl(regs + S3C64XX_UINTM);
+ reg |= (1 << bit);
+ __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+
+static void s3c_irq_uart_maskack(unsigned int irq)
+{
+ void __iomem *regs = s3c_irq_uart_base(irq);
+ unsigned int bit = s3c_irq_uart_bit(irq);
+ u32 reg;
+
+ reg = __raw_readl(regs + S3C64XX_UINTM);
+ reg |= (1 << bit);
+ __raw_writel(reg, regs + S3C64XX_UINTM);
+ __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+
+static void s3c_irq_uart_unmask(unsigned int irq)
+{
+ void __iomem *regs = s3c_irq_uart_base(irq);
+ unsigned int bit = s3c_irq_uart_bit(irq);
+ u32 reg;
+
+ reg = __raw_readl(regs + S3C64XX_UINTM);
+ reg &= ~(1 << bit);
+ __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+
+static void s3c_irq_uart_ack(unsigned int irq)
+{
+ void __iomem *regs = s3c_irq_uart_base(irq);
+ unsigned int bit = s3c_irq_uart_bit(irq);
+
+ __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+
+static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
+{
+ struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
+ u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
+ int base = uirq->base_irq;
+
+ if (pend & (1 << 0))
+ generic_handle_irq(base);
+ if (pend & (1 << 1))
+ generic_handle_irq(base + 1);
+ if (pend & (1 << 2))
+ generic_handle_irq(base + 2);
+ if (pend & (1 << 3))
+ generic_handle_irq(base + 3);
+}
+
+static struct irq_chip s3c_irq_uart = {
+ .name = "s3c-uart",
+ .mask = s3c_irq_uart_mask,
+ .unmask = s3c_irq_uart_unmask,
+ .mask_ack = s3c_irq_uart_maskack,
+ .ack = s3c_irq_uart_ack,
+};
+
+static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
+{
+ void *reg_base = uirq->regs;
+ unsigned int irq;
+ int offs;
+
+ /* mask all interrupts at the start. */
+ __raw_writel(0xf, reg_base + S3C64XX_UINTM);
+
+ for (offs = 0; offs < 3; offs++) {
+ irq = uirq->base_irq + offs;
+
+ set_irq_chip(irq, &s3c_irq_uart);
+ set_irq_chip_data(irq, uirq);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
+}
+
+void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
+{
+ int uart, irq;
+
+ printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
+
+ /* initialise the pair of VICs */
+ vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
+ vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
+
+ /* add the timer sub-irqs */
+
+ set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
+ set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
+ set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
+ set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
+ set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
+
+ for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
+ set_irq_chip(irq, &s3c_irq_timer);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
+ s3c64xx_uart_irq(&uart_irqs[uart]);
+}
+
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -0,0 +1,204 @@
+/* arch/arm/plat-s3c64xx/irq-eint.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Interrupt handling for IRQ_EINT(x)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware/vic.h>
+
+#include <plat/regs-irqtype.h>
+#include <plat/regs-gpio.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+#define eint_offset(irq) ((irq) - IRQ_EINT(0))
+#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
+
+static inline void s3c_irq_eint_mask(unsigned int irq)
+{
+ u32 mask;
+
+ mask = __raw_readl(S3C64XX_EINT0MASK);
+ mask |= eint_irq_to_bit(irq);
+ __raw_writel(mask, S3C64XX_EINT0MASK);
+}
+
+static void s3c_irq_eint_unmask(unsigned int irq)
+{
+ u32 mask;
+
+ mask = __raw_readl(S3C64XX_EINT0MASK);
+ mask &= ~eint_irq_to_bit(irq);
+ __raw_writel(mask, S3C64XX_EINT0MASK);
+}
+
+static inline void s3c_irq_eint_ack(unsigned int irq)
+{
+ __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
+}
+
+static void s3c_irq_eint_maskack(unsigned int irq)
+{
+ /* compiler should in-line these */
+ s3c_irq_eint_mask(irq);
+ s3c_irq_eint_ack(irq);
+}
+
+static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+ int offs = eint_offset(irq);
+ int pin;
+ int shift;
+ u32 ctrl, mask;
+ u32 newvalue = 0;
+ void __iomem *reg;
+
+ if (offs > 27)
+ return -EINVAL;
+
+ if (offs <= 15)
+ reg = S3C64XX_EINT0CON0;
+ else
+ reg = S3C64XX_EINT0CON1;
+
+ switch (type) {
+ case IRQ_TYPE_NONE:
+ printk(KERN_WARNING "No edge setting!\n");
+ break;
+
+ case IRQ_TYPE_EDGE_RISING:
+ newvalue = S3C2410_EXTINT_RISEEDGE;
+ break;
+
+ case IRQ_TYPE_EDGE_FALLING:
+ newvalue = S3C2410_EXTINT_FALLEDGE;
+ break;
+
+ case IRQ_TYPE_EDGE_BOTH:
+ newvalue = S3C2410_EXTINT_BOTHEDGE;
+ break;
+
+ case IRQ_TYPE_LEVEL_LOW:
+ newvalue = S3C2410_EXTINT_LOWLEV;
+ break;
+
+ case IRQ_TYPE_LEVEL_HIGH:
+ newvalue = S3C2410_EXTINT_HILEV;
+ break;
+
+ default:
+ printk(KERN_ERR "No such irq type %d", type);
+ return -1;
+ }
+
+ shift = (offs / 2) * 4;
+ mask = 0x7 << shift;
+
+ ctrl = __raw_readl(reg);
+ ctrl &= ~mask;
+ ctrl |= newvalue << shift;
+ __raw_writel(ctrl, reg);
+
+ /* set the GPIO pin appropriately */
+
+ if (offs < 23)
+ pin = S3C64XX_GPN(offs);
+ else
+ pin = S3C64XX_GPM(offs - 23);
+
+ s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
+
+ return 0;
+}
+
+static struct irq_chip s3c_irq_eint = {
+ .name = "s3c-eint",
+ .mask = s3c_irq_eint_mask,
+ .unmask = s3c_irq_eint_unmask,
+ .mask_ack = s3c_irq_eint_maskack,
+ .ack = s3c_irq_eint_ack,
+ .set_type = s3c_irq_eint_set_type,
+ .set_wake = s3c_irqext_wake,
+};
+
+/* s3c_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
+ * the specific handlers s3c_irq_demux_eintX_Y.
+ */
+static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
+{
+ u32 status = __raw_readl(S3C64XX_EINT0PEND);
+ u32 mask = __raw_readl(S3C64XX_EINT0MASK);
+ unsigned int irq;
+
+ status &= ~mask;
+ status >>= start;
+ status &= (1 << (end - start + 1)) - 1;
+
+ for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+ if (status & 1)
+ generic_handle_irq(irq);
+
+ status >>= 1;
+ }
+}
+
+static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_eint(0, 3);
+}
+
+static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_eint(4, 11);
+}
+
+static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_eint(12, 19);
+}
+
+static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
+{
+ s3c_irq_demux_eint(20, 27);
+}
+
+int __init s3c64xx_init_irq_eint(void)
+{
+ int irq;
+
+ for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
+ set_irq_chip(irq, &s3c_irq_eint);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
+ set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
+ set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
+ set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
+
+ return 0;
+}
+
+arch_initcall(s3c64xx_init_irq_eint);
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq-pm.c
@@ -0,0 +1,173 @@
+/* arch/arm/plat-s3c64xx/irq-pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX - Interrupt handling Power Management
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/serial_core.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/vic.h>
+
+#include <mach/map.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-timer.h>
+#include <plat/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+/* We handled all the IRQ types in this code, to save having to make several
+ * small files to handle each different type separately. Having the EINT_GRP
+ * code here shouldn't be as much bloat as the IRQ table space needed when
+ * they are enabled. The added benefit is we ensure that these registers are
+ * in the same state as we suspended.
+ */
+
+static struct sleep_save irq_save[] = {
+ SAVE_ITEM(S3C64XX_PRIORITY),
+ SAVE_ITEM(S3C64XX_EINT0CON0),
+ SAVE_ITEM(S3C64XX_EINT0CON1),
+ SAVE_ITEM(S3C64XX_EINT0FLTCON0),
+ SAVE_ITEM(S3C64XX_EINT0FLTCON1),
+ SAVE_ITEM(S3C64XX_EINT0FLTCON2),
+ SAVE_ITEM(S3C64XX_EINT0FLTCON3),
+ SAVE_ITEM(S3C64XX_EINT0MASK),
+ SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+
+static struct irq_grp_save {
+ u32 fltcon;
+ u32 con;
+ u32 mask;
+} eint_grp_save[5];
+
+struct irq_vic_save {
+ u32 int_select;
+ u32 int_enable;
+ u32 soft_int;
+ u32 protect;
+ u32 vect_addr[32];
+ u32 vect_cntl[32];
+};
+
+static struct irq_vic_save irq_pm_vic0_save;
+static struct irq_vic_save irq_pm_vic1_save;
+
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static void s3c64xx_vic_save(void __iomem *base, struct irq_vic_save *save)
+{
+ int v;
+
+ save->int_select = readl(base + VIC_INT_SELECT);
+ save->int_enable = readl(base + VIC_INT_ENABLE);
+ save->soft_int = readl(base + VIC_INT_SOFT);
+ save->protect = readl(base + VIC_PROTECT);
+
+ S3C_PMDBG("%s: select=%08x, enable=%08x, protect=%08x\n", __func__,
+ save->int_select, save->int_enable, save->protect);
+
+ for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
+ save->vect_addr[v] = readl(base + VIC_VECT_ADDR0 + (v * 4));
+ save->vect_cntl[v] = readl(base + VIC_VECT_CNTL0 + (v * 4));
+ }
+}
+
+static void s3c64xx_vic_restore(void __iomem *base, struct irq_vic_save *save)
+{
+ int v;
+
+ writel(save->int_select, base + VIC_INT_SELECT);
+ writel(save->protect, base + VIC_PROTECT);
+
+ /* set the enabled ints and then clear the non-enabled */
+ writel(save->int_enable, base + VIC_INT_ENABLE);
+ writel(~save->int_enable, base + VIC_INT_ENABLE_CLEAR);
+
+ /* and the same for the soft-int register */
+
+ writel(save->soft_int, base + VIC_INT_SOFT);
+ writel(~save->soft_int, base + VIC_INT_SOFT_CLEAR);
+
+ S3C_PMDBG("%s: vic int_enable=%08x\n", __func__, readl(base + VIC_INT_ENABLE));
+
+ for (v = 0; v < ARRAY_SIZE(save->vect_addr); v++) {
+ writel(save->vect_addr[v], base + VIC_VECT_ADDR0 + (v * 4));
+ writel(save->vect_cntl[v], base + VIC_VECT_CNTL0 + (v * 4));
+ }
+}
+
+static int s3c64xx_irq_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+ struct irq_grp_save *grp = eint_grp_save;
+ int i;
+
+ S3C_PMDBG("%s: suspending IRQs\n", __func__);
+
+ s3c64xx_vic_save(S3C_VA_VIC0, &irq_pm_vic0_save);
+ s3c64xx_vic_save(S3C_VA_VIC1, &irq_pm_vic1_save);
+
+ s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+ irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+ for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+ grp->con = __raw_readl(S3C64XX_EINT12CON + (i * 4));
+ grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4));
+ grp->fltcon = __raw_readl(S3C64XX_EINT12FLTCON + (i * 4));
+ }
+
+ return 0;
+}
+
+static int s3c64xx_irq_pm_resume(struct sys_device *dev)
+{
+ struct irq_grp_save *grp = eint_grp_save;
+ int i;
+
+ S3C_PMDBG("%s: resuming IRQs\n", __func__);
+
+ s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+
+ s3c64xx_vic_restore(S3C_VA_VIC0, &irq_pm_vic0_save);
+ s3c64xx_vic_restore(S3C_VA_VIC1, &irq_pm_vic1_save);
+
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+ __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+ for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+ __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4));
+ __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4));
+ __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4));
+ }
+
+ S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+ return 0;
+}
+
+static struct sysdev_driver s3c64xx_irq_driver = {
+ .suspend = s3c64xx_irq_pm_suspend,
+ .resume = s3c64xx_irq_pm_resume,
+};
+
+static int __init s3c64xx_irq_pm_init(void)
+{
+ return sysdev_driver_register(&s3c64xx_sysclass, &s3c64xx_irq_driver);
+}
+
+arch_initcall(s3c64xx_irq_pm_init);
+
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -0,0 +1,61 @@
+# arch/arm/plat-s3c64xx/Kconfig
+#
+# Copyright 2008 Openmoko, Inc.
+# Copyright 2008 Simtec Electronics
+# Ben Dooks <ben@simtec.co.uk>
+#
+# Licensed under GPLv2
+
+config PLAT_S3C64XX
+ bool
+ depends on ARCH_S3C64XX
+ select PLAT_S3C
+ select ARM_VIC
+ default y
+ select NO_IOPORT
+ select ARCH_REQUIRE_GPIOLIB
+ select S3C_GPIO_TRACK
+ select S3C_GPIO_PULL_UPDOWN
+ select S3C_GPIO_CFG_S3C24XX
+ select S3C_GPIO_CFG_S3C64XX
+ help
+ Base platform code for any Samsung S3C64XX device
+
+if PLAT_S3C64XX
+
+# Configuration options shared by all S3C64XX implementations
+
+config CPU_S3C6400_INIT
+ bool
+ help
+ Common initialisation code for the S3C6400 that is shared
+ by other CPUs in the series, such as the S3C6410.
+
+config CPU_S3C6400_CLOCK
+ bool
+ help
+ Common clock support code for the S3C6400 that is shared
+ by other CPUs in the series, such as the S3C6410.
+
+# platform specific device setup
+
+config S3C64XX_SETUP_I2C0
+ bool
+ default y
+ help
+ Common setup code for i2c bus 0.
+
+ Note, currently since i2c0 is always compiled, this setup helper
+ is always compiled with it.
+
+config S3C64XX_SETUP_I2C1
+ bool
+ help
+ Common setup code for i2c bus 1.
+
+config S3C64XX_SETUP_FB_24BPP
+ bool
+ help
+ Common setup code for S3C64XX with an 24bpp RGB display helper.
+
+endif
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -0,0 +1,37 @@
+# arch/arm/plat-s3c64xx/Makefile
+#
+# Copyright 2008 Openmoko, Inc.
+# Copyright 2008 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y :=
+obj-m :=
+obj-n := dummy.o
+obj- :=
+
+# Core files
+
+obj-y += dev-uart.o
+obj-y += cpu.o
+obj-y += irq.o
+obj-y += irq-eint.o
+obj-y += clock.o
+obj-y += gpiolib.o
+
+# CPU support
+
+obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
+obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
+
+# PM support
+
+obj-$(CONFIG_PM) += pm.o
+obj-$(CONFIG_PM) += sleep.o
+obj-$(CONFIG_PM) += irq-pm.o
+
+# Device setup
+
+obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/pm.c
@@ -0,0 +1,177 @@
+/* linux/arch/arm/plat-s3c64xx/pm.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU PM support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+
+#include <plat/pm.h>
+#include <plat/regs-sys.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-clock.h>
+#include <plat/regs-modem.h>
+#include <plat/regs-syscon-power.h>
+#include <plat/regs-gpio-memport.h>
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+#include <plat/gpio-bank-n.h>
+
+void s3c_pm_debug_smdkled(u32 set, u32 clear)
+{
+ unsigned long flags;
+ u32 reg;
+
+ local_irq_save(flags);
+ reg = __raw_readl(S3C64XX_GPNCON);
+ reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
+ S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
+ reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
+ S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
+ __raw_writel(reg, S3C64XX_GPNCON);
+
+ reg = __raw_readl(S3C64XX_GPNDAT);
+ reg &= ~(clear << 12);
+ reg |= set << 12;
+ __raw_writel(reg, S3C64XX_GPNDAT);
+
+ local_irq_restore(flags);
+}
+#endif
+
+static struct sleep_save core_save[] = {
+ SAVE_ITEM(S3C_APLL_LOCK),
+ SAVE_ITEM(S3C_MPLL_LOCK),
+ SAVE_ITEM(S3C_EPLL_LOCK),
+ SAVE_ITEM(S3C_CLK_SRC),
+ SAVE_ITEM(S3C_CLK_DIV0),
+ SAVE_ITEM(S3C_CLK_DIV1),
+ SAVE_ITEM(S3C_CLK_DIV2),
+ SAVE_ITEM(S3C_CLK_OUT),
+ SAVE_ITEM(S3C_HCLK_GATE),
+ SAVE_ITEM(S3C_PCLK_GATE),
+ SAVE_ITEM(S3C_SCLK_GATE),
+ SAVE_ITEM(S3C_MEM0_GATE),
+
+ SAVE_ITEM(S3C_EPLL_CON1),
+ SAVE_ITEM(S3C_EPLL_CON0),
+
+ SAVE_ITEM(S3C64XX_MEM0DRVCON),
+ SAVE_ITEM(S3C64XX_MEM1DRVCON),
+
+#ifndef CONFIG_CPU_FREQ
+ SAVE_ITEM(S3C_APLL_CON),
+ SAVE_ITEM(S3C_MPLL_CON),
+#endif
+};
+
+static struct sleep_save misc_save[] = {
+ SAVE_ITEM(S3C64XX_AHB_CON0),
+ SAVE_ITEM(S3C64XX_AHB_CON1),
+ SAVE_ITEM(S3C64XX_AHB_CON2),
+
+ SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
+ SAVE_ITEM(S3C64XX_SPCON),
+
+ SAVE_ITEM(S3C64XX_MEM0CONSTOP),
+ SAVE_ITEM(S3C64XX_MEM1CONSTOP),
+ SAVE_ITEM(S3C64XX_MEM0CONSLP0),
+ SAVE_ITEM(S3C64XX_MEM0CONSLP1),
+ SAVE_ITEM(S3C64XX_MEM1CONSLP),
+};
+
+void s3c_pm_configure_extint(void)
+{
+ __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
+}
+
+void s3c_pm_restore_core(void)
+{
+ __raw_writel(0, S3C64XX_EINT_MASK);
+
+ s3c_pm_debug_smdkled(1 << 2, 0);
+
+ s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
+ s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
+}
+
+void s3c_pm_save_core(void)
+{
+ s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
+ s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
+}
+
+/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
+ * put the per-cpu code in here until any new cpu comes along and changes
+ * this.
+ */
+
+#include <plat/regs-gpio.h>
+
+static void s3c64xx_cpu_suspend(void)
+{
+ unsigned long tmp;
+
+ /* set our standby method to sleep */
+
+ tmp = __raw_readl(S3C64XX_PWR_CFG);
+ tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+ tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
+ __raw_writel(tmp, S3C64XX_PWR_CFG);
+
+ /* clear any old wakeup */
+
+ __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
+ S3C64XX_WAKEUP_STAT);
+
+ /* set the LED state to 0110 over sleep */
+ s3c_pm_debug_smdkled(3 << 1, 0xf);
+
+ /* issue the standby signal into the pm unit. Note, we
+ * issue a write-buffer drain just in case */
+
+ tmp = 0;
+
+ asm("b 1f\n\t"
+ ".align 5\n\t"
+ "1:\n\t"
+ "mcr p15, 0, %0, c7, c10, 5\n\t"
+ "mcr p15, 0, %0, c7, c10, 4\n\t"
+ "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
+
+ /* we should never get past here */
+
+ panic("sleep resumed to originator?");
+}
+
+static void s3c64xx_pm_prepare(void)
+{
+ /* store address of resume. */
+ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
+
+ /* ensure previous wakeup state is cleared before sleeping */
+ __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
+}
+
+static int s3c64xx_pm_init(void)
+{
+ pm_cpu_prep = s3c64xx_pm_prepare;
+ pm_cpu_sleep = s3c64xx_cpu_suspend;
+ pm_uart_udivslot = 1;
+ return 0;
+}
+
+arch_initcall(s3c64xx_pm_init);
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -0,0 +1,654 @@
+/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 based common clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <plat/cpu-freq.h>
+
+#include <plat/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+
+/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
+ * ext_xtal_mux for want of an actual name from the manual.
+*/
+
+struct clk clk_ext_xtal_mux = {
+ .name = "ext_xtal",
+ .id = -1,
+};
+
+#define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_mpll clk_ext_xtal_mux
+#define clk_fin_epll clk_ext_xtal_mux
+
+#define clk_fout_mpll clk_mpll
+
+struct clk_sources {
+ unsigned int nr_sources;
+ struct clk **sources;
+};
+
+struct clksrc_clk {
+ struct clk clk;
+ unsigned int mask;
+ unsigned int shift;
+
+ struct clk_sources *sources;
+
+ unsigned int divider_shift;
+ void __iomem *reg_divider;
+};
+
+struct clk clk_fout_apll = {
+ .name = "fout_apll",
+ .id = -1,
+};
+
+static struct clk *clk_src_apll_list[] = {
+ [0] = &clk_fin_apll,
+ [1] = &clk_fout_apll,
+};
+
+static struct clk_sources clk_src_apll = {
+ .sources = clk_src_apll_list,
+ .nr_sources = ARRAY_SIZE(clk_src_apll_list),
+};
+
+struct clksrc_clk clk_mout_apll = {
+ .clk = {
+ .name = "mout_apll",
+ .id = -1,
+ },
+ .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
+ .mask = S3C6400_CLKSRC_APLL_MOUT,
+ .sources = &clk_src_apll,
+};
+
+struct clk clk_fout_epll = {
+ .name = "fout_epll",
+ .id = -1,
+};
+
+static struct clk *clk_src_epll_list[] = {
+ [0] = &clk_fin_epll,
+ [1] = &clk_fout_epll,
+};
+
+static struct clk_sources clk_src_epll = {
+ .sources = clk_src_epll_list,
+ .nr_sources = ARRAY_SIZE(clk_src_epll_list),
+};
+
+struct clksrc_clk clk_mout_epll = {
+ .clk = {
+ .name = "mout_epll",
+ .id = -1,
+ },
+ .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
+ .mask = S3C6400_CLKSRC_EPLL_MOUT,
+ .sources = &clk_src_epll,
+};
+
+static struct clk *clk_src_mpll_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &clk_fout_mpll,
+};
+
+static struct clk_sources clk_src_mpll = {
+ .sources = clk_src_mpll_list,
+ .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
+};
+
+struct clksrc_clk clk_mout_mpll = {
+ .clk = {
+ .name = "mout_mpll",
+ .id = -1,
+ },
+ .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
+ .mask = S3C6400_CLKSRC_MPLL_MOUT,
+ .sources = &clk_src_mpll,
+};
+
+static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
+{
+ unsigned long rate = clk_get_rate(clk->parent);
+
+ printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+
+ if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
+ rate /= 2;
+
+ return rate;
+}
+
+struct clk clk_dout_mpll = {
+ .name = "dout_mpll",
+ .id = -1,
+ .parent = &clk_mout_mpll.clk,
+ .get_rate = s3c64xx_clk_doutmpll_get_rate,
+};
+
+static struct clk *clkset_spi_mmc_list[] = {
+ &clk_mout_epll.clk,
+ &clk_dout_mpll,
+ &clk_fin_epll,
+ &clk_27m,
+};
+
+static struct clk_sources clkset_spi_mmc = {
+ .sources = clkset_spi_mmc_list,
+ .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
+};
+
+static struct clk *clkset_irda_list[] = {
+ &clk_mout_epll.clk,
+ &clk_dout_mpll,
+ NULL,
+ &clk_27m,
+};
+
+static struct clk_sources clkset_irda = {
+ .sources = clkset_irda_list,
+ .nr_sources = ARRAY_SIZE(clkset_irda_list),
+};
+
+static struct clk *clkset_uart_list[] = {
+ &clk_mout_epll.clk,
+ &clk_dout_mpll,
+ NULL,
+ NULL
+};
+
+static struct clk_sources clkset_uart = {
+ .sources = clkset_uart_list,
+ .nr_sources = ARRAY_SIZE(clkset_uart_list),
+};
+
+static struct clk *clkset_uhost_list[] = {
+ &clk_mout_epll.clk,
+ &clk_dout_mpll,
+ &clk_fin_epll,
+ &clk_48m,
+};
+
+static struct clk_sources clkset_uhost = {
+ .sources = clkset_uhost_list,
+ .nr_sources = ARRAY_SIZE(clkset_uhost_list),
+};
+
+
+/* The peripheral clocks are all controlled via clocksource followed
+ * by an optional divider and gate stage. We currently roll this into
+ * one clock which hides the intermediate clock from the mux.
+ *
+ * Note, the JPEG clock can only be an even divider...
+ *
+ * The scaler and LCD clocks depend on the S3C64XX version, and also
+ * have a common parent divisor so are not included here.
+ */
+
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+ return container_of(clk, struct clksrc_clk, clk);
+}
+
+static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
+{
+ struct clksrc_clk *sclk = to_clksrc(clk);
+ unsigned long rate = clk_get_rate(clk->parent);
+ u32 clkdiv = __raw_readl(sclk->reg_divider);
+
+ clkdiv >>= sclk->divider_shift;
+ clkdiv &= 0xf;
+ clkdiv++;
+
+ rate /= clkdiv;
+ return rate;
+}
+
+static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+ struct clksrc_clk *sclk = to_clksrc(clk);
+ void __iomem *reg = sclk->reg_divider;
+ unsigned int div;
+ u32 val;
+
+ rate = clk_round_rate(clk, rate);
+ div = clk_get_rate(clk->parent) / rate;
+
+ val = __raw_readl(reg);
+ val &= ~sclk->mask;
+ val |= (rate - 1) << sclk->shift;
+ __raw_writel(val, reg);
+
+ return 0;
+}
+
+static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+ struct clksrc_clk *sclk = to_clksrc(clk);
+ struct clk_sources *srcs = sclk->sources;
+ u32 clksrc = __raw_readl(S3C_CLK_SRC);
+ int src_nr = -1;
+ int ptr;
+
+ for (ptr = 0; ptr < srcs->nr_sources; ptr++)
+ if (srcs->sources[ptr] == parent) {
+ src_nr = ptr;
+ break;
+ }
+
+ if (src_nr >= 0) {
+ clksrc &= ~sclk->mask;
+ clksrc |= src_nr << sclk->shift;
+
+ __raw_writel(clksrc, S3C_CLK_SRC);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
+ unsigned long rate)
+{
+ unsigned long parent_rate = clk_get_rate(clk->parent);
+ int div;
+
+ if (rate > parent_rate)
+ rate = parent_rate;
+ else {
+ div = rate / parent_rate;
+
+ if (div == 0)
+ div = 1;
+ if (div > 16)
+ div = 16;
+
+ rate = parent_rate / div;
+ }
+
+ return rate;
+}
+
+static struct clksrc_clk clk_mmc0 = {
+ .clk = {
+ .name = "mmc_bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC0,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_MMC0_SHIFT,
+ .mask = S3C6400_CLKSRC_MMC0_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+};
+
+static struct clksrc_clk clk_mmc1 = {
+ .clk = {
+ .name = "mmc_bus",
+ .id = 1,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC1,
+ .enable = s3c64xx_sclk_ctrl,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_MMC1_SHIFT,
+ .mask = S3C6400_CLKSRC_MMC1_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+};
+
+static struct clksrc_clk clk_mmc2 = {
+ .clk = {
+ .name = "mmc_bus",
+ .id = 2,
+ .ctrlbit = S3C_CLKCON_SCLK_MMC2,
+ .enable = s3c64xx_sclk_ctrl,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_MMC2_SHIFT,
+ .mask = S3C6400_CLKSRC_MMC2_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+};
+
+static struct clksrc_clk clk_usbhost = {
+ .clk = {
+ .name = "usb-host-bus",
+ .id = -1,
+ .ctrlbit = S3C_CLKCON_SCLK_UHOST,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_UHOST_SHIFT,
+ .mask = S3C6400_CLKSRC_UHOST_MASK,
+ .sources = &clkset_uhost,
+ .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
+ .reg_divider = S3C_CLK_DIV1,
+};
+
+static struct clksrc_clk clk_uart_uclk1 = {
+ .clk = {
+ .name = "uclk1",
+ .id = -1,
+ .ctrlbit = S3C_CLKCON_SCLK_UART,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_UART_SHIFT,
+ .mask = S3C6400_CLKSRC_UART_MASK,
+ .sources = &clkset_uart,
+ .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+};
+
+/* Where does UCLK0 come from? */
+
+static struct clksrc_clk clk_spi0 = {
+ .clk = {
+ .name = "spi-bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI0,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_SPI0_SHIFT,
+ .mask = S3C6400_CLKSRC_SPI0_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+};
+
+static struct clksrc_clk clk_spi1 = {
+ .clk = {
+ .name = "spi-bus",
+ .id = 1,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI1,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_SPI1_SHIFT,
+ .mask = S3C6400_CLKSRC_SPI1_MASK,
+ .sources = &clkset_spi_mmc,
+ .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+};
+
+static struct clk clk_iis_cd0 = {
+ .name = "iis_cdclk0",
+ .id = -1,
+};
+
+static struct clk clk_iis_cd1 = {
+ .name = "iis_cdclk1",
+ .id = -1,
+};
+
+static struct clk clk_pcm_cd = {
+ .name = "pcm_cdclk",
+ .id = -1,
+};
+
+static struct clk *clkset_audio0_list[] = {
+ [0] = &clk_mout_epll.clk,
+ [1] = &clk_dout_mpll,
+ [2] = &clk_fin_epll,
+ [3] = &clk_iis_cd0,
+ [4] = &clk_pcm_cd,
+};
+
+static struct clk_sources clkset_audio0 = {
+ .sources = clkset_audio0_list,
+ .nr_sources = ARRAY_SIZE(clkset_audio0_list),
+};
+
+static struct clksrc_clk clk_audio0 = {
+ .clk = {
+ .name = "audio-bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
+ .mask = S3C6400_CLKSRC_AUDIO0_MASK,
+ .sources = &clkset_audio0,
+ .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+};
+
+static struct clk *clkset_audio1_list[] = {
+ [0] = &clk_mout_epll.clk,
+ [1] = &clk_dout_mpll,
+ [2] = &clk_fin_epll,
+ [3] = &clk_iis_cd1,
+ [4] = &clk_pcm_cd,
+};
+
+static struct clk_sources clkset_audio1 = {
+ .sources = clkset_audio1_list,
+ .nr_sources = ARRAY_SIZE(clkset_audio1_list),
+};
+
+static struct clksrc_clk clk_audio1 = {
+ .clk = {
+ .name = "audio-bus",
+ .id = 1,
+ .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
+ .mask = S3C6400_CLKSRC_AUDIO1_MASK,
+ .sources = &clkset_audio1,
+ .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+};
+
+static struct clksrc_clk clk_irda = {
+ .clk = {
+ .name = "irda-bus",
+ .id = 0,
+ .ctrlbit = S3C_CLKCON_SCLK_IRDA,
+ .enable = s3c64xx_sclk_ctrl,
+ .set_parent = s3c64xx_setparent_clksrc,
+ .get_rate = s3c64xx_getrate_clksrc,
+ .set_rate = s3c64xx_setrate_clksrc,
+ .round_rate = s3c64xx_roundrate_clksrc,
+ },
+ .shift = S3C6400_CLKSRC_IRDA_SHIFT,
+ .mask = S3C6400_CLKSRC_IRDA_MASK,
+ .sources = &clkset_irda,
+ .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
+ .reg_divider = S3C_CLK_DIV2,
+};
+
+/* Clock initialisation code */
+
+static struct clksrc_clk *init_parents[] = {
+ &clk_mout_apll,
+ &clk_mout_epll,
+ &clk_mout_mpll,
+ &clk_mmc0,
+ &clk_mmc1,
+ &clk_mmc2,
+ &clk_usbhost,
+ &clk_uart_uclk1,
+ &clk_spi0,
+ &clk_spi1,
+ &clk_audio0,
+ &clk_audio1,
+ &clk_irda,
+};
+
+static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
+{
+ struct clk_sources *srcs = clk->sources;
+ u32 clksrc = __raw_readl(S3C_CLK_SRC);
+
+ clksrc &= clk->mask;
+ clksrc >>= clk->shift;
+
+ if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+ printk(KERN_ERR "%s: bad source %d\n",
+ clk->clk.name, clksrc);
+ return;
+ }
+
+ clk->clk.parent = srcs->sources[clksrc];
+
+ printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+ clk->clk.name, clk->clk.parent->name, clksrc,
+ clk_get_rate(&clk->clk));
+}
+
+#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
+
+void __init_or_cpufreq s3c6400_setup_clocks(void)
+{
+ struct clk *xtal_clk;
+ unsigned long xtal;
+ unsigned long fclk;
+ unsigned long hclk;
+ unsigned long hclk2;
+ unsigned long pclk;
+ unsigned long epll;
+ unsigned long apll;
+ unsigned long mpll;
+ unsigned int ptr;
+ u32 clkdiv0;
+
+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+ clkdiv0 = __raw_readl(S3C_CLK_DIV0);
+ printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
+
+ xtal_clk = clk_get(NULL, "xtal");
+ BUG_ON(IS_ERR(xtal_clk));
+
+ xtal = clk_get_rate(xtal_clk);
+ clk_put(xtal_clk);
+
+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+ epll = s3c6400_get_epll(xtal);
+ mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
+ apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
+
+ fclk = mpll;
+
+ printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
+ apll, mpll, epll);
+
+ hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+ hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
+ pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
+
+ printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
+ hclk2, hclk, pclk);
+
+ clk_fout_mpll.rate = mpll;
+ clk_fout_epll.rate = epll;
+ clk_fout_apll.rate = apll;
+
+ clk_h.rate = hclk;
+ clk_p.rate = pclk;
+ clk_f.rate = fclk;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
+ s3c6400_set_clksrc(init_parents[ptr]);
+}
+
+static struct clk *clks[] __initdata = {
+ &clk_ext_xtal_mux,
+ &clk_iis_cd0,
+ &clk_iis_cd1,
+ &clk_pcm_cd,
+ &clk_mout_epll.clk,
+ &clk_fout_epll,
+ &clk_mout_mpll.clk,
+ &clk_dout_mpll,
+ &clk_mmc0.clk,
+ &clk_mmc1.clk,
+ &clk_mmc2.clk,
+ &clk_usbhost.clk,
+ &clk_uart_uclk1.clk,
+ &clk_spi0.clk,
+ &clk_spi1.clk,
+ &clk_audio0.clk,
+ &clk_audio1.clk,
+ &clk_irda.clk,
+};
+
+void __init s3c6400_register_clocks(void)
+{
+ struct clk *clkp;
+ int ret;
+ int ptr;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+ clkp = clks[ptr];
+ ret = s3c24xx_register_clock(clkp);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to register clock %s (%d)\n",
+ clkp->name, ret);
+ }
+ }
+
+ clk_epll.parent = &clk_mout_epll.clk;
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/s3c6400-init.c
@@ -0,0 +1,29 @@
+/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C6400 - CPU initialisation (common with other S3C64XX chips)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s3c6400.h>
+#include <plat/s3c6410.h>
+
+/* uart registration process */
+
+void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+ s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
@@ -0,0 +1,37 @@
+/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Base S3C64XX setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+
+#include <mach/regs-fb.h>
+#include <mach/gpio.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+extern void s3c64xx_fb_gpio_setup_24bpp(void)
+{
+ unsigned int gpio;
+
+ for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ }
+
+ for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ }
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-i2c0.c
@@ -0,0 +1,31 @@
+/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Base S3C64XX I2C bus 0 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-bank-b.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
+ s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
+ s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-i2c1.c
@@ -0,0 +1,31 @@
+/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Base S3C64XX I2C bus 1 gpio configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct platform_device; /* don't need the contents */
+
+#include <mach/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-bank-b.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+ s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
+ s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
+ s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
+}
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/sleep.S
@@ -0,0 +1,143 @@
+/* linux/0arch/arm/plat-s3c64xx/sleep.S
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * S3C64XX CPU sleep code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/map.h>
+
+#undef S3C64XX_VA_GPIO
+#define S3C64XX_VA_GPIO (0x0)
+
+#include <plat/regs-gpio.h>
+#include <plat/gpio-bank-n.h>
+
+#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
+
+ .text
+
+ /* s3c_cpu_save
+ *
+ * Save enough processor state to allow the restart of the pm.c
+ * code after resume.
+ *
+ * entry:
+ * r0 = pointer to the save block
+ * exit:
+ * r0 = exit code: 1 => stored data
+ * 0 => resumed from sleep
+ */
+
+ENTRY(s3c_cpu_save)
+ stmfd sp!, { r4 - r12, lr }
+
+ mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
+ mrc p15, 0, r5, c3, c0, 0 @ Domain ID
+ mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
+ mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
+ mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
+ mrc p15, 0, r9, c1, c0, 0 @ Control register
+ mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
+ mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
+
+ stmia r0, { r4 - r13 } @ Save CP registers and SP
+ mov r0, #0
+ ldmfd sp, { r4 - r12, pc } @ return, not disturbing SP
+
+ @@ return to the caller, after the MMU is turned on.
+ @@ restore the last bits of the stack and return.
+resume_with_mmu:
+ mov r0, #1
+ ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
+
+ .data
+
+ /* the next bit is code, but it requires easy access to the
+ * s3c_sleep_save_phys data before the MMU is switched on, so
+ * we store the code that needs this variable in the .data where
+ * the value can be written to (the .text segment is RO).
+ */
+
+ .global s3c_sleep_save_phys
+s3c_sleep_save_phys:
+ .word 0
+
+ /* Sleep magic, the word before the resume entry point so that the
+ * bootloader can check for a resumeable image. */
+
+ .word 0x2bedf00d
+
+ /* s3c_cpu_reusme
+ *
+ * This is the entry point, stored by whatever method the bootloader
+ * requires to get the kernel runnign again. This code expects to be
+ * entered with no caches live and the MMU disabled. It will then
+ * restore the MMU and other basic CP registers saved and restart
+ * the kernel C code to finish the resume code.
+ */
+
+ENTRY(s3c_cpu_resume)
+ msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+ ldr r2, =LL_UART /* for debug */
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+ /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
+ * as the uboot version supplied resets these to inputs during the
+ * resume checks.
+ */
+
+ ldr r3, =S3C64XX_PA_GPIO
+ ldr r0, [ r3, #S3C64XX_GPNCON ]
+ bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
+ S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
+ orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
+ S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
+ str r0, [ r3, #S3C64XX_GPNCON ]
+
+ ldr r0, [ r3, #S3C64XX_GPNDAT ]
+ bic r0, r0, #0xf << 12 @ GPN12..15
+ orr r0, r0, #1 << 15 @ GPN15
+ str r0, [ r3, #S3C64XX_GPNDAT ]
+#endif
+
+ /* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
+ * are thoroughly cleaned just in case the bootloader didn't do it
+ * for us. */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
+ mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
+ @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
+ @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
+
+ ldr r0, s3c_sleep_save_phys
+ ldmia r0, { r4 - r13 }
+
+ mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
+ mcr p15, 0, r5, c3, c0, 0 @ Domain ID
+ mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
+ mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
+ mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
+ mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
+
+ mov r0, #0 @ restore copro access controls
+ mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
+ mcr p15, 0, r0, c7, c5, 4
+
+ ldr r2, =resume_with_mmu
+ mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
+ nop
+ mov pc, r2 /* jump back */
+
+ .end
--- /dev/null
+++ b/dfu-kern
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+if [ -z "$1" ] ; then
+ echo "Usage: $0 <DEVICE> eg, $0 GTA02"
+ exit 1
+fi
+
+../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5119 -D uImage-$1.bin
+if [ $? -eq 1 ] ; then
+../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5120 -D uImage-$1.bin
+../../dfu-util/src/dfu-util -a 3 -d 0x1d50:0x5119 -D uImage-$1.bin
+fi
+
+
--- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt
+++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt
@@ -40,13 +40,13 @@
Machine Support
---------------
- The machine specific functions must call the s3c2410_pm_init() function
+ The machine specific functions must call the s3c_pm_init() function
to say that its bootloader is capable of resuming. This can be as
simple as adding the following to the machine's definition:
- INITMACHINE(s3c2410_pm_init)
+ INITMACHINE(s3c_pm_init)
- A board can do its own setup before calling s3c2410_pm_init, if it
+ A board can do its own setup before calling s3c_pm_init, if it
needs to setup anything else for power management support.
There is currently no support for over-riding the default method of
@@ -74,7 +74,7 @@
enable_irq_wake(IRQ_EINT0);
- s3c2410_pm_init();
+ s3c_pm_init();
}
--- /dev/null
+++ b/drivers/android/alarm.c
@@ -0,0 +1,542 @@
+/* drivers/android/alarm.c
+ *
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/mach/time.h>
+#include <linux/android_alarm.h>
+#include <linux/android_power.h>
+#include <linux/device.h>
+#include <linux/miscdevice.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+
+#define ANDROID_ALARM_PRINT_ERRORS (1U << 0)
+#define ANDROID_ALARM_PRINT_INIT_STATUS (1U << 1)
+#define ANDROID_ALARM_PRINT_INFO (1U << 2)
+#define ANDROID_ALARM_PRINT_IO (1U << 3)
+#define ANDROID_ALARM_PRINT_INT (1U << 4)
+#define ANDROID_ALARM_PRINT_FLOW (1U << 5)
+
+#if 0
+#define ANDROID_ALARM_DPRINTF_MASK (~0)
+#define ANDROID_ALARM_DPRINTF(debug_level_mask, args...) \
+ do { \
+ if(ANDROID_ALARM_DPRINTF_MASK & debug_level_mask) { \
+ printk(args); \
+ } \
+ } while(0)
+#else
+#define ANDROID_ALARM_DPRINTF(args...)
+#endif
+
+// support old usespace code
+#define ANDROID_ALARM_SET_OLD _IOW('a', 2, time_t) // set alarm
+#define ANDROID_ALARM_SET_AND_WAIT_OLD _IOW('a', 3, time_t)
+
+static struct rtc_device *alarm_rtc_dev;
+static int alarm_opened;
+static DEFINE_SPINLOCK(alarm_slock);
+static DEFINE_MUTEX(alarm_setrtc_mutex);
+static android_suspend_lock_t alarm_suspend_lock = {
+ .name = "android_alarm"
+};
+static android_suspend_lock_t alarm_rtc_suspend_lock = {
+ .name = "android_alarm_rtc"
+};
+static DECLARE_WAIT_QUEUE_HEAD(alarm_wait_queue);
+static uint32_t alarm_pending;
+static uint32_t alarm_enabled;
+static uint32_t wait_pending;
+static struct platform_device *alarm_platform_dev;
+static struct hrtimer alarm_timer[ANDROID_ALARM_TYPE_COUNT];
+static struct timespec alarm_time[ANDROID_ALARM_TYPE_COUNT];
+static struct timespec elapsed_rtc_delta;
+
+static void alarm_start_hrtimer(android_alarm_type_t alarm_type)
+{
+ struct timespec hr_alarm_time;
+ if(!(alarm_enabled & (1U << alarm_type)))
+ return;
+ hr_alarm_time = alarm_time[alarm_type];
+ if(alarm_type == ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP || alarm_type == ANDROID_ALARM_ELAPSED_REALTIME)
+ set_normalized_timespec(&hr_alarm_time, hr_alarm_time.tv_sec + elapsed_rtc_delta.tv_sec,
+ hr_alarm_time.tv_nsec + elapsed_rtc_delta.tv_nsec);
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm start hrtimer %d at %ld.%09ld\n", alarm_type, hr_alarm_time.tv_sec, hr_alarm_time.tv_nsec);
+ hrtimer_start(&alarm_timer[alarm_type], timespec_to_ktime(hr_alarm_time), HRTIMER_MODE_ABS);
+}
+
+static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ int rv = 0;
+ unsigned long flags;
+ int i;
+ struct timespec new_alarm_time;
+ struct timespec new_rtc_time;
+ struct timespec tmp_time;
+ struct rtc_time rtc_new_rtc_time;
+ android_alarm_type_t alarm_type = ANDROID_ALARM_IOCTL_TO_TYPE(cmd);
+ uint32_t alarm_type_mask = 1U << alarm_type;
+
+ if(alarm_type >= ANDROID_ALARM_TYPE_COUNT)
+ return -EINVAL;
+
+ if(ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_GET_TIME(0)) {
+ if ((file->f_flags & O_ACCMODE) == O_RDONLY)
+ return -EPERM;
+ if(file->private_data == NULL && cmd != ANDROID_ALARM_SET_RTC) {
+ spin_lock_irqsave(&alarm_slock, flags);
+ if(alarm_opened) {
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ return -EBUSY;
+ }
+ alarm_opened = 1;
+ file->private_data = (void *)1;
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ }
+ }
+
+ switch(ANDROID_ALARM_BASE_CMD(cmd)) {
+ //case ANDROID_ALARM_CLEAR_OLD: // same as ANDROID_ALARM_CLEAR(0)
+ case ANDROID_ALARM_CLEAR(0):
+ spin_lock_irqsave(&alarm_slock, flags);
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm %d clear\n", alarm_type);
+ hrtimer_try_to_cancel(&alarm_timer[alarm_type]);
+ if(alarm_pending) {
+ alarm_pending &= ~alarm_type_mask;
+ if(!alarm_pending && !wait_pending) {
+ android_unlock_suspend(&alarm_suspend_lock);
+ }
+ }
+ alarm_enabled &= ~alarm_type_mask;
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ break;
+
+ case ANDROID_ALARM_SET_OLD:
+ case ANDROID_ALARM_SET_AND_WAIT_OLD:
+ if(get_user(new_alarm_time.tv_sec, (int __user *)arg)) {
+ rv = -EFAULT;
+ goto err1;
+ }
+ new_alarm_time.tv_nsec = 0;
+ goto from_old_alarm_set;
+
+ case ANDROID_ALARM_SET_AND_WAIT(0):
+ case ANDROID_ALARM_SET(0):
+ if(copy_from_user(&new_alarm_time, (void __user *)arg, sizeof(new_alarm_time))) {
+ rv = -EFAULT;
+ goto err1;
+ }
+from_old_alarm_set:
+ spin_lock_irqsave(&alarm_slock, flags);
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm %d set %ld.%09ld\n", alarm_type, new_alarm_time.tv_sec, new_alarm_time.tv_nsec);
+ alarm_time[alarm_type] = new_alarm_time;
+ alarm_enabled |= alarm_type_mask;
+ alarm_start_hrtimer(alarm_type);
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ if(ANDROID_ALARM_BASE_CMD(cmd) != ANDROID_ALARM_SET_AND_WAIT(0) && cmd != ANDROID_ALARM_SET_AND_WAIT_OLD)
+ break;
+ // fall though
+ case ANDROID_ALARM_WAIT:
+ spin_lock_irqsave(&alarm_slock, flags);
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO, "alarm wait\n");
+ if(!alarm_pending && wait_pending) {
+ android_unlock_suspend(&alarm_suspend_lock);
+ wait_pending = 0;
+ }
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ rv = wait_event_interruptible(alarm_wait_queue, alarm_pending);
+ if(rv)
+ goto err1;
+ spin_lock_irqsave(&alarm_slock, flags);
+ rv = alarm_pending;
+ wait_pending = 1;
+ alarm_pending = 0;
+ if(rv & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
+ android_unlock_suspend(&alarm_rtc_suspend_lock);
+ }
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ break;
+ case ANDROID_ALARM_SET_RTC:
+ if(copy_from_user(&new_rtc_time, (void __user *)arg, sizeof(new_rtc_time))) {
+ rv = -EFAULT;
+ goto err1;
+ }
+ rtc_time_to_tm(new_rtc_time.tv_sec, &rtc_new_rtc_time);
+
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_IO,
+ "set rtc %ld %ld - rtc %02d:%02d:%02d %02d/%02d/%04d\n",
+ new_rtc_time.tv_sec, new_rtc_time.tv_nsec,
+ rtc_new_rtc_time.tm_hour, rtc_new_rtc_time.tm_min,
+ rtc_new_rtc_time.tm_sec, rtc_new_rtc_time.tm_mon + 1,
+ rtc_new_rtc_time.tm_mday, rtc_new_rtc_time.tm_year + 1900);
+
+ mutex_lock(&alarm_setrtc_mutex);
+ spin_lock_irqsave(&alarm_slock, flags);
+ for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++)
+ hrtimer_try_to_cancel(&alarm_timer[i]);
+ getnstimeofday(&tmp_time);
+ elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, timespec_sub(tmp_time, new_rtc_time));
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ rv = do_settimeofday(&new_rtc_time);
+ spin_lock_irqsave(&alarm_slock, flags);
+ for (i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++)
+ alarm_start_hrtimer(i);
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ if(rv < 0) {
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, "Failed to set time\n");
+ mutex_unlock(&alarm_setrtc_mutex);
+ goto err1;
+ }
+ rv = rtc_set_time(alarm_rtc_dev, &rtc_new_rtc_time);
+ spin_lock_irqsave(&alarm_slock, flags);
+ alarm_pending |= ANDROID_ALARM_TIME_CHANGE_MASK;
+ wake_up(&alarm_wait_queue);
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ mutex_unlock(&alarm_setrtc_mutex);
+ if(rv < 0) {
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_ERRORS, "Failed to set RTC, time will be lost on reboot\n");
+ goto err1;
+ }
+ break;
+ case ANDROID_ALARM_GET_TIME(0):
+ mutex_lock(&alarm_setrtc_mutex);
+ spin_lock_irqsave(&alarm_slock, flags);
+ if(alarm_type != ANDROID_ALARM_SYSTEMTIME) {
+ getnstimeofday(&tmp_time);
+ if(alarm_type >= ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP) {
+ tmp_time = timespec_sub(tmp_time, elapsed_rtc_delta);
+ }
+ }
+ else
+ ktime_get_ts(&tmp_time);
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ mutex_unlock(&alarm_setrtc_mutex);
+ if(copy_to_user((void __user *)arg, &tmp_time, sizeof(tmp_time))) {
+ rv = -EFAULT;
+ goto err1;
+ }
+ break;
+
+ default:
+ rv = -EINVAL;
+ goto err1;
+ }
+err1:
+ return rv;
+}
+
+static int alarm_open(struct inode *inode, struct file *file)
+{
+ file->private_data = NULL;
+ return 0;
+}
+
+static int alarm_release(struct inode *inode, struct file *file)
+{
+ int i;
+ unsigned long flags;
+
+ spin_lock_irqsave(&alarm_slock, flags);
+ if(file->private_data != 0) {
+ for(i = 0; i < ANDROID_ALARM_TYPE_COUNT; i++) {
+ uint32_t alarm_type_mask = 1U << i;
+ if(alarm_enabled & alarm_type_mask) {
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm_release: clear alarm, pending %d\n", !!(alarm_pending & alarm_type_mask));
+ alarm_enabled &= ~alarm_type_mask;
+ }
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ hrtimer_cancel(&alarm_timer[i]);
+ spin_lock_irqsave(&alarm_slock, flags);
+ }
+ if(alarm_pending | wait_pending) {
+ if(alarm_pending)
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm_release: clear pending alarms %x\n", alarm_pending);
+ android_unlock_suspend(&alarm_suspend_lock);
+ wait_pending = 0;
+ alarm_pending = 0;
+ }
+ alarm_opened = 0;
+ }
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ return 0;
+}
+
+static enum hrtimer_restart alarm_timer_triggered(struct hrtimer *timer)
+{
+ unsigned long flags;
+ android_alarm_type_t alarm_type = (timer - alarm_timer);
+ uint32_t alarm_type_mask = 1U << alarm_type;
+
+
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "alarm_timer_triggered type %d\n", alarm_type);
+ spin_lock_irqsave(&alarm_slock, flags);
+ if (alarm_enabled & alarm_type_mask) {
+ android_lock_suspend_auto_expire(&alarm_suspend_lock, 5 * HZ);
+ alarm_enabled &= ~alarm_type_mask;
+ alarm_pending |= alarm_type_mask;
+ wake_up(&alarm_wait_queue);
+ }
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ return HRTIMER_NORESTART;
+}
+
+static void alarm_triggered_func(void *p)
+{
+// unsigned long flags;
+
+ struct rtc_device *rtc = alarm_rtc_dev;
+ if(rtc->irq_data & RTC_AF) {
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INT, "alarm_triggered_func:\n");
+ android_lock_suspend_auto_expire(&alarm_rtc_suspend_lock, 1 * HZ);
+ }
+}
+
+int alarm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ int err = 0;
+ unsigned long flags;
+ struct rtc_wkalrm rtc_alarm;
+ struct rtc_time rtc_current_rtc_time;
+ unsigned long rtc_current_time;
+ unsigned long rtc_alarm_time;
+ struct timespec rtc_current_timespec;
+ struct timespec rtc_delta;
+ struct timespec elapsed_realtime_alarm_time;
+
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm_suspend(%p, %d)\n", pdev, state.event);
+ spin_lock_irqsave(&alarm_slock, flags);
+ if(alarm_pending && (alarm_suspend_lock.flags & ANDROID_SUSPEND_LOCK_AUTO_EXPIRE)) {
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm pending\n");
+ err = -EBUSY;
+ goto err1;
+ }
+ if(alarm_enabled & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ if(alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK)
+ hrtimer_cancel(&alarm_timer[ANDROID_ALARM_RTC_WAKEUP]);
+ if(alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
+ hrtimer_cancel(&alarm_timer[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP]);
+
+ rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
+ rtc_current_timespec.tv_nsec = 0;
+ rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_timespec.tv_sec);
+ save_time_delta(&rtc_delta, &rtc_current_timespec);
+ set_normalized_timespec(&elapsed_realtime_alarm_time,
+ alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].tv_sec + elapsed_rtc_delta.tv_sec,
+ alarm_time[ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP].tv_nsec + elapsed_rtc_delta.tv_nsec);
+ if((alarm_enabled & ANDROID_ALARM_RTC_WAKEUP_MASK) &&
+ (!(alarm_enabled & ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)
+ || timespec_compare(&alarm_time[ANDROID_ALARM_RTC_WAKEUP], &elapsed_realtime_alarm_time) < 0))
+ rtc_alarm_time = timespec_sub(alarm_time[ANDROID_ALARM_RTC_WAKEUP], rtc_delta).tv_sec;
+ else {
+ rtc_alarm_time = timespec_sub(elapsed_realtime_alarm_time, rtc_delta).tv_sec;
+ }
+ rtc_time_to_tm(rtc_alarm_time, &rtc_alarm.time);
+ rtc_alarm.enabled = 1;
+ rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
+ rtc_read_time(alarm_rtc_dev, &rtc_current_rtc_time);
+ rtc_tm_to_time(&rtc_current_rtc_time, &rtc_current_time);
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO,
+ "rtc alarm set at %ld, now %ld, rtc delta %ld.%09ld\n",
+ rtc_alarm_time, rtc_current_time,
+ rtc_delta.tv_sec, rtc_delta.tv_nsec);
+ if(rtc_current_time + 1 >= rtc_alarm_time) {
+ //spin_lock_irqsave(&alarm_slock, flags);
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm about to go off\n");
+ memset(&rtc_alarm, 0, sizeof(rtc_alarm));
+ rtc_alarm.enabled = 0;
+ rtc_set_alarm(alarm_rtc_dev, &rtc_alarm);
+
+ spin_lock_irqsave(&alarm_slock, flags);
+ android_lock_suspend_auto_expire(&alarm_rtc_suspend_lock, 2 * HZ); // trigger a wakeup
+ alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP);
+ alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP);
+ err = -EBUSY;
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ }
+ }
+ else {
+err1:
+ spin_unlock_irqrestore(&alarm_slock, flags);
+ }
+ return err;
+}
+
+int alarm_resume(struct platform_device *pdev)
+{
+ struct rtc_wkalrm alarm;
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_FLOW, "alarm_resume(%p)\n", pdev);
+ if(alarm_enabled & (ANDROID_ALARM_RTC_WAKEUP_MASK | ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK)) {
+ memset(&alarm, 0, sizeof(alarm));
+ alarm.enabled = 0;
+ rtc_set_alarm(alarm_rtc_dev, &alarm);
+ alarm_start_hrtimer(ANDROID_ALARM_RTC_WAKEUP);
+ alarm_start_hrtimer(ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP);
+ }
+ return 0;
+}
+
+static struct rtc_task alarm_rtc_task = {
+ .func = alarm_triggered_func
+};
+
+static struct file_operations alarm_fops = {
+ .owner = THIS_MODULE,
+ .unlocked_ioctl = alarm_ioctl,
+ .open = alarm_open,
+ .release = alarm_release,
+};
+
+static struct miscdevice alarm_device = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "alarm",
+ .fops = &alarm_fops,
+};
+
+static int rtc_alarm_add_device(struct device *dev,
+ struct class_interface *class_intf)
+{
+ int err;
+ struct rtc_device *rtc = to_rtc_device(dev);
+
+ mutex_lock(&alarm_setrtc_mutex);
+
+ if(alarm_rtc_dev) {
+ err = -EBUSY;
+ goto err1;
+ }
+
+ err = misc_register(&alarm_device);
+ if(err)
+ goto err1;
+ alarm_platform_dev = platform_device_register_simple("alarm", -1, NULL, 0);
+ if(IS_ERR(alarm_platform_dev)) {
+ err = PTR_ERR(alarm_platform_dev);
+ goto err2;
+ }
+ err = rtc_irq_register(rtc, &alarm_rtc_task);
+ if(err)
+ goto err3;
+ alarm_rtc_dev = rtc;
+ mutex_unlock(&alarm_setrtc_mutex);
+
+ //device_pm_set_parent(&alarm_platform_dev->dev, dev); // currently useless, drivers are suspended in reverse creation order
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO, "alarm: parent %p\n", alarm_platform_dev->dev.power.pm_parent);
+ return 0;
+
+err3:
+ platform_device_unregister(alarm_platform_dev);
+err2:
+ misc_deregister(&alarm_device);
+err1:
+ mutex_unlock(&alarm_setrtc_mutex);
+ return err;
+}
+
+static void rtc_alarm_remove_device(struct device *dev,
+ struct class_interface *class_intf)
+{
+ if(dev == &alarm_rtc_dev->dev) {
+ rtc_irq_unregister(alarm_rtc_dev, &alarm_rtc_task);
+ platform_device_unregister(alarm_platform_dev);
+ misc_deregister(&alarm_device);
+ alarm_rtc_dev = NULL;
+ }
+}
+
+static struct class_interface rtc_alarm_interface = {
+ .add_dev = &rtc_alarm_add_device,
+ .remove_dev = &rtc_alarm_remove_device,
+};
+
+static struct platform_driver alarm_driver = {
+ .suspend = alarm_suspend,
+ .resume = alarm_resume,
+ .driver = {
+ .name = "alarm"
+ }
+};
+
+static int __init alarm_late_init(void)
+{
+ unsigned long flags;
+ struct timespec system_time;
+
+ // this needs to run after the rtc is read at boot
+ spin_lock_irqsave(&alarm_slock, flags);
+ // We read the current rtc and system time so we can later calulate
+ // elasped realtime to be (boot_systemtime + rtc - boot_rtc) ==
+ // (rtc - (boot_rtc - boot_systemtime))
+ getnstimeofday(&elapsed_rtc_delta);
+ ktime_get_ts(&system_time);
+ elapsed_rtc_delta = timespec_sub(elapsed_rtc_delta, system_time);
+ spin_unlock_irqrestore(&alarm_slock, flags);
+
+ ANDROID_ALARM_DPRINTF(ANDROID_ALARM_PRINT_INFO,
+ "alarm_late_init: rtc to elapsed realtime delta %ld.%09ld\n",
+ elapsed_rtc_delta.tv_sec, elapsed_rtc_delta.tv_nsec);
+ return 0;
+}
+
+static int __init alarm_init(void)
+{
+ int err;
+ int i;
+
+ for(i = 0; i < ANDROID_ALARM_SYSTEMTIME; i++) {
+ hrtimer_init(&alarm_timer[i], CLOCK_REALTIME, HRTIMER_MODE_ABS);
+ alarm_timer[i].function = alarm_timer_triggered;
+ }
+ hrtimer_init(&alarm_timer[ANDROID_ALARM_SYSTEMTIME], CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
+ alarm_timer[ANDROID_ALARM_SYSTEMTIME].function = alarm_timer_triggered;
+ err = platform_driver_register(&alarm_driver);
+ if(err < 0)
+ goto err1;
+ err = android_init_suspend_lock(&alarm_suspend_lock);
+ if(err < 0)
+ goto err2;
+ err = android_init_suspend_lock(&alarm_rtc_suspend_lock);
+ if(err < 0)
+ goto err3;
+ rtc_alarm_interface.class = rtc_class;
+ err = class_interface_register(&rtc_alarm_interface);
+ if(err < 0)
+ goto err4;
+
+ return 0;
+
+err4:
+ android_uninit_suspend_lock(&alarm_rtc_suspend_lock);
+err3:
+ android_uninit_suspend_lock(&alarm_suspend_lock);
+err2:
+ platform_driver_unregister(&alarm_driver);
+err1:
+ return err;
+}
+
+static void __exit alarm_exit(void)
+{
+ class_interface_unregister(&rtc_alarm_interface);
+ android_uninit_suspend_lock(&alarm_rtc_suspend_lock);
+ android_uninit_suspend_lock(&alarm_suspend_lock);
+ platform_driver_unregister(&alarm_driver);
+}
+
+late_initcall(alarm_late_init);
+module_init(alarm_init);
+module_exit(alarm_exit);
+
--- /dev/null
+++ b/drivers/android/binder.c
@@ -0,0 +1,3495 @@
+/* drivers/android/binder.c
+ *
+ * Android IPC Subsystem
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <asm/cacheflush.h>
+#include <linux/binder.h>
+#include <linux/fdtable.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/nsproxy.h>
+#include <linux/poll.h>
+#include <linux/proc_fs.h>
+#include <linux/rbtree.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+
+static DEFINE_MUTEX(binder_lock);
+static HLIST_HEAD(binder_procs);
+static struct binder_node *binder_context_mgr_node;
+static uid_t binder_context_mgr_uid = -1;
+static int binder_last_id;
+static struct proc_dir_entry *binder_proc_dir_entry_root;
+static struct proc_dir_entry *binder_proc_dir_entry_proc;
+static struct hlist_head binder_dead_nodes;
+
+static int binder_read_proc_proc(
+ char *page, char **start, off_t off, int count, int *eof, void *data);
+
+/* This is only defined in include/asm-arm/sizes.h */
+#ifndef SZ_1K
+#define SZ_1K 0x400
+#endif
+
+#ifndef SZ_4M
+#define SZ_4M 0x400000
+#endif
+
+#define FORBIDDEN_MMAP_FLAGS (VM_WRITE)
+
+#define BINDER_SMALL_BUF_SIZE (PAGE_SIZE * 64)
+
+enum {
+ BINDER_DEBUG_USER_ERROR = 1U << 0,
+ BINDER_DEBUG_FAILED_TRANSACTION = 1U << 1,
+ BINDER_DEBUG_DEAD_TRANSACTION = 1U << 2,
+ BINDER_DEBUG_OPEN_CLOSE = 1U << 3,
+ BINDER_DEBUG_DEAD_BINDER = 1U << 4,
+ BINDER_DEBUG_DEATH_NOTIFICATION = 1U << 5,
+ BINDER_DEBUG_READ_WRITE = 1U << 6,
+ BINDER_DEBUG_USER_REFS = 1U << 7,
+ BINDER_DEBUG_THREADS = 1U << 8,
+ BINDER_DEBUG_TRANSACTION = 1U << 9,
+ BINDER_DEBUG_TRANSACTION_COMPLETE = 1U << 10,
+ BINDER_DEBUG_FREE_BUFFER = 1U << 11,
+ BINDER_DEBUG_INTERNAL_REFS = 1U << 12,
+ BINDER_DEBUG_BUFFER_ALLOC = 1U << 13,
+ BINDER_DEBUG_PRIORITY_CAP = 1U << 14,
+ BINDER_DEBUG_BUFFER_ALLOC_ASYNC = 1U << 15,
+};
+static uint32_t binder_debug_mask = BINDER_DEBUG_USER_ERROR |
+ BINDER_DEBUG_FAILED_TRANSACTION | BINDER_DEBUG_DEAD_TRANSACTION;
+module_param_named(debug_mask, binder_debug_mask, uint, S_IWUSR | S_IRUGO)
+static int binder_debug_no_lock;
+module_param_named(proc_no_lock, binder_debug_no_lock, bool, S_IWUSR | S_IRUGO)
+static DECLARE_WAIT_QUEUE_HEAD(binder_user_error_wait);
+static int binder_stop_on_user_error;
+static int binder_set_stop_on_user_error(
+ const char *val, struct kernel_param *kp)
+{
+ int ret;
+ ret = param_set_int(val, kp);
+ if (binder_stop_on_user_error < 2)
+ wake_up(&binder_user_error_wait);
+ return ret;
+}
+module_param_call(stop_on_user_error, binder_set_stop_on_user_error,
+ param_get_int, &binder_stop_on_user_error, S_IWUSR | S_IRUGO);
+
+#define binder_user_error(x...) \
+ do { \
+ if (binder_debug_mask & BINDER_DEBUG_USER_ERROR) \
+ printk(KERN_INFO x); \
+ if (binder_stop_on_user_error) \
+ binder_stop_on_user_error = 2; \
+ } while (0)
+
+enum {
+ BINDER_STAT_PROC,
+ BINDER_STAT_THREAD,
+ BINDER_STAT_NODE,
+ BINDER_STAT_REF,
+ BINDER_STAT_DEATH,
+ BINDER_STAT_TRANSACTION,
+ BINDER_STAT_TRANSACTION_COMPLETE,
+ BINDER_STAT_COUNT
+};
+
+struct binder_stats {
+ int br[_IOC_NR(BR_FAILED_REPLY) + 1];
+ int bc[_IOC_NR(BC_DEAD_BINDER_DONE) + 1];
+ int obj_created[BINDER_STAT_COUNT];
+ int obj_deleted[BINDER_STAT_COUNT];
+};
+
+static struct binder_stats binder_stats;
+
+struct binder_transaction_log_entry {
+ int debug_id;
+ int call_type;
+ int from_proc;
+ int from_thread;
+ int target_handle;
+ int to_proc;
+ int to_thread;
+ int to_node;
+ int data_size;
+ int offsets_size;
+};
+struct binder_transaction_log {
+ int next;
+ int full;
+ struct binder_transaction_log_entry entry[32];
+};
+struct binder_transaction_log binder_transaction_log;
+struct binder_transaction_log binder_transaction_log_failed;
+
+static struct binder_transaction_log_entry *binder_transaction_log_add(
+ struct binder_transaction_log *log)
+{
+ struct binder_transaction_log_entry *e;
+ e = &log->entry[log->next];
+ memset(e, 0, sizeof(*e));
+ log->next++;
+ if (log->next == ARRAY_SIZE(log->entry)) {
+ log->next = 0;
+ log->full = 1;
+ }
+ return e;
+}
+
+struct binder_work {
+ struct list_head entry;
+ enum {
+ BINDER_WORK_TRANSACTION = 1,
+ BINDER_WORK_TRANSACTION_COMPLETE,
+ BINDER_WORK_NODE,
+ BINDER_WORK_DEAD_BINDER,
+ BINDER_WORK_DEAD_BINDER_AND_CLEAR,
+ BINDER_WORK_CLEAR_DEATH_NOTIFICATION,
+ } type;
+};
+
+struct binder_node {
+ int debug_id;
+ struct binder_work work;
+ union {
+ struct rb_node rb_node;
+ struct hlist_node dead_node;
+ };
+ struct binder_proc *proc;
+ struct hlist_head refs;
+ int internal_strong_refs;
+ int local_weak_refs;
+ int local_strong_refs;
+ void __user *ptr;
+ void __user *cookie;
+ unsigned has_strong_ref : 1;
+ unsigned pending_strong_ref : 1;
+ unsigned has_weak_ref : 1;
+ unsigned pending_weak_ref : 1;
+ unsigned has_async_transaction : 1;
+ unsigned accept_fds : 1;
+ int min_priority : 8;
+ struct list_head async_todo;
+};
+
+struct binder_ref_death {
+ struct binder_work work;
+ void __user *cookie;
+};
+
+struct binder_ref {
+ /* Lookups needed: */
+ /* node + proc => ref (transaction) */
+ /* desc + proc => ref (transaction, inc/dec ref) */
+ /* node => refs + procs (proc exit) */
+ int debug_id;
+ struct rb_node rb_node_desc;
+ struct rb_node rb_node_node;
+ struct hlist_node node_entry;
+ struct binder_proc *proc;
+ struct binder_node *node;
+ uint32_t desc;
+ int strong;
+ int weak;
+ struct binder_ref_death *death;
+};
+
+struct binder_buffer {
+ struct list_head entry; /* free and allocated entries by addesss */
+ struct rb_node rb_node; /* free entry by size or allocated entry */
+ /* by address */
+ unsigned free : 1;
+ unsigned allow_user_free : 1;
+ unsigned async_transaction : 1;
+ unsigned debug_id : 29;
+
+ struct binder_transaction *transaction;
+
+ struct binder_node *target_node;
+ size_t data_size;
+ size_t offsets_size;
+ uint8_t data[0];
+};
+
+struct binder_proc {
+ struct hlist_node proc_node;
+ struct rb_root threads;
+ struct rb_root nodes;
+ struct rb_root refs_by_desc;
+ struct rb_root refs_by_node;
+ int pid;
+ struct vm_area_struct *vma;
+ struct task_struct *tsk;
+ void *buffer;
+ size_t user_buffer_offset;
+
+ struct list_head buffers;
+ struct rb_root free_buffers;
+ struct rb_root allocated_buffers;
+ size_t free_async_space;
+
+ struct page **pages;
+ size_t buffer_size;
+ uint32_t buffer_free;
+ struct list_head todo;
+ wait_queue_head_t wait;
+ struct binder_stats stats;
+ struct list_head delivered_death;
+ int max_threads;
+ int requested_threads;
+ int requested_threads_started;
+ int ready_threads;
+ long default_priority;
+};
+
+enum {
+ BINDER_LOOPER_STATE_REGISTERED = 0x01,
+ BINDER_LOOPER_STATE_ENTERED = 0x02,
+ BINDER_LOOPER_STATE_EXITED = 0x04,
+ BINDER_LOOPER_STATE_INVALID = 0x08,
+ BINDER_LOOPER_STATE_WAITING = 0x10,
+ BINDER_LOOPER_STATE_NEED_RETURN = 0x20
+};
+
+struct binder_thread {
+ struct binder_proc *proc;
+ struct rb_node rb_node;
+ int pid;
+ int looper;
+ struct binder_transaction *transaction_stack;
+ struct list_head todo;
+ uint32_t return_error; /* Write failed, return error code in read buf */
+ uint32_t return_error2; /* Write failed, return error code in read */
+ /* buffer. Used when sending a reply to a dead process that */
+ /* we are also waiting on */
+ wait_queue_head_t wait;
+ struct binder_stats stats;
+};
+
+struct binder_transaction {
+ int debug_id;
+ struct binder_work work;
+ struct binder_thread *from;
+ struct binder_transaction *from_parent;
+ struct binder_proc *to_proc;
+ struct binder_thread *to_thread;
+ struct binder_transaction *to_parent;
+ unsigned need_reply : 1;
+ /*unsigned is_dead : 1;*/ /* not used at the moment */
+
+ struct binder_buffer *buffer;
+ unsigned int code;
+ unsigned int flags;
+ long priority;
+ long saved_priority;
+ uid_t sender_euid;
+};
+
+/*
+ * copied from get_unused_fd_flags
+ */
+int task_get_unused_fd_flags(struct task_struct *tsk, int flags)
+{
+ struct files_struct *files = get_files_struct(tsk);
+ int fd, error;
+ struct fdtable *fdt;
+ unsigned long rlim_cur;
+
+ if (files == NULL)
+ return -ESRCH;
+
+ error = -EMFILE;
+ spin_lock(&files->file_lock);
+
+repeat:
+ fdt = files_fdtable(files);
+ fd = find_next_zero_bit(fdt->open_fds->fds_bits, fdt->max_fds,
+ files->next_fd);
+
+ /*
+ * N.B. For clone tasks sharing a files structure, this test
+ * will limit the total number of files that can be opened.
+ */
+ rcu_read_lock();
+ if (tsk->signal)
+ rlim_cur = tsk->signal->rlim[RLIMIT_NOFILE].rlim_cur;
+ else
+ rlim_cur = 0;
+ rcu_read_unlock();
+ if (fd >= rlim_cur)
+ goto out;
+
+ /* Do we need to expand the fd array or fd set? */
+ error = expand_files(files, fd);
+ if (error < 0)
+ goto out;
+
+ if (error) {
+ /*
+ * If we needed to expand the fs array we
+ * might have blocked - try again.
+ */
+ error = -EMFILE;
+ goto repeat;
+ }
+
+ FD_SET(fd, fdt->open_fds);
+ if (flags & O_CLOEXEC)
+ FD_SET(fd, fdt->close_on_exec);
+ else
+ FD_CLR(fd, fdt->close_on_exec);
+ files->next_fd = fd + 1;
+#if 1
+ /* Sanity check */
+ if (fdt->fd[fd] != NULL) {
+ printk(KERN_WARNING "get_unused_fd: slot %d not NULL!\n", fd);
+ fdt->fd[fd] = NULL;
+ }
+#endif
+ error = fd;
+
+out:
+ spin_unlock(&files->file_lock);
+ put_files_struct(files);
+ return error;
+}
+
+/*
+ * copied from fd_install
+ */
+static void task_fd_install(
+ struct task_struct *tsk, unsigned int fd, struct file *file)
+{
+ struct files_struct *files = get_files_struct(tsk);
+ struct fdtable *fdt;
+
+ if (files == NULL)
+ return;
+
+ spin_lock(&files->file_lock);
+ fdt = files_fdtable(files);
+ BUG_ON(fdt->fd[fd] != NULL);
+ rcu_assign_pointer(fdt->fd[fd], file);
+ spin_unlock(&files->file_lock);
+ put_files_struct(files);
+}
+
+/*
+ * copied from __put_unused_fd in open.c
+ */
+static void __put_unused_fd(struct files_struct *files, unsigned int fd)
+{
+ struct fdtable *fdt = files_fdtable(files);
+ __FD_CLR(fd, fdt->open_fds);
+ if (fd < files->next_fd)
+ files->next_fd = fd;
+}
+
+/*
+ * copied from sys_close
+ */
+static long task_close_fd(struct task_struct *tsk, unsigned int fd)
+{
+ struct file *filp;
+ struct files_struct *files = get_files_struct(tsk);
+ struct fdtable *fdt;
+ int retval;
+
+ if (files == NULL)
+ return -ESRCH;
+
+ spin_lock(&files->file_lock);
+ fdt = files_fdtable(files);
+ if (fd >= fdt->max_fds)
+ goto out_unlock;
+ filp = fdt->fd[fd];
+ if (!filp)
+ goto out_unlock;
+ rcu_assign_pointer(fdt->fd[fd], NULL);
+ FD_CLR(fd, fdt->close_on_exec);
+ __put_unused_fd(files, fd);
+ spin_unlock(&files->file_lock);
+ retval = filp_close(filp, files);
+
+ /* can't restart close syscall because file table entry was cleared */
+ if (unlikely(retval == -ERESTARTSYS ||
+ retval == -ERESTARTNOINTR ||
+ retval == -ERESTARTNOHAND ||
+ retval == -ERESTART_RESTARTBLOCK))
+ retval = -EINTR;
+
+ put_files_struct(files);
+ return retval;
+
+out_unlock:
+ spin_unlock(&files->file_lock);
+ put_files_struct(files);
+ return -EBADF;
+}
+
+static void binder_set_nice(long nice)
+{
+ long min_nice;
+ if (can_nice(current, nice)) {
+ set_user_nice(current, nice);
+ return;
+ }
+ min_nice = 20 - current->signal->rlim[RLIMIT_NICE].rlim_cur;
+ if (binder_debug_mask & BINDER_DEBUG_PRIORITY_CAP)
+ printk(KERN_INFO "binder: %d: nice value %ld not allowed use "
+ "%ld instead\n", current->pid, nice, min_nice);
+ set_user_nice(current, min_nice);
+ if (min_nice < 20)
+ return;
+ binder_user_error("binder: %d RLIMIT_NICE not set\n", current->pid);
+}
+
+static size_t binder_buffer_size(
+ struct binder_proc *proc, struct binder_buffer *buffer)
+{
+ if (list_is_last(&buffer->entry, &proc->buffers))
+ return proc->buffer + proc->buffer_size - (void *)buffer->data;
+ else
+ return (size_t)list_entry(buffer->entry.next,
+ struct binder_buffer, entry) - (size_t)buffer->data;
+}
+
+static void binder_insert_free_buffer(
+ struct binder_proc *proc, struct binder_buffer *new_buffer)
+{
+ struct rb_node **p = &proc->free_buffers.rb_node;
+ struct rb_node *parent = NULL;
+ struct binder_buffer *buffer;
+ size_t buffer_size;
+ size_t new_buffer_size;
+
+ BUG_ON(!new_buffer->free);
+
+ new_buffer_size = binder_buffer_size(proc, new_buffer);
+
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: add free buffer, size %d, "
+ "at %p\n", proc->pid, new_buffer_size, new_buffer);
+
+ while (*p) {
+ parent = *p;
+ buffer = rb_entry(parent, struct binder_buffer, rb_node);
+ BUG_ON(!buffer->free);
+
+ buffer_size = binder_buffer_size(proc, buffer);
+
+ if (new_buffer_size < buffer_size)
+ p = &parent->rb_left;
+ else
+ p = &parent->rb_right;
+ }
+ rb_link_node(&new_buffer->rb_node, parent, p);
+ rb_insert_color(&new_buffer->rb_node, &proc->free_buffers);
+}
+
+static void binder_insert_allocated_buffer(
+ struct binder_proc *proc, struct binder_buffer *new_buffer)
+{
+ struct rb_node **p = &proc->allocated_buffers.rb_node;
+ struct rb_node *parent = NULL;
+ struct binder_buffer *buffer;
+
+ BUG_ON(new_buffer->free);
+
+ while (*p) {
+ parent = *p;
+ buffer = rb_entry(parent, struct binder_buffer, rb_node);
+ BUG_ON(buffer->free);
+
+ if (new_buffer < buffer)
+ p = &parent->rb_left;
+ else if (new_buffer > buffer)
+ p = &parent->rb_right;
+ else
+ BUG();
+ }
+ rb_link_node(&new_buffer->rb_node, parent, p);
+ rb_insert_color(&new_buffer->rb_node, &proc->allocated_buffers);
+}
+
+static struct binder_buffer *binder_buffer_lookup(
+ struct binder_proc *proc, void __user *user_ptr)
+{
+ struct rb_node *n = proc->allocated_buffers.rb_node;
+ struct binder_buffer *buffer;
+ struct binder_buffer *kern_ptr;
+
+ kern_ptr = user_ptr - proc->user_buffer_offset
+ - offsetof(struct binder_buffer, data);
+
+ while (n) {
+ buffer = rb_entry(n, struct binder_buffer, rb_node);
+ BUG_ON(buffer->free);
+
+ if (kern_ptr < buffer)
+ n = n->rb_left;
+ else if (kern_ptr > buffer)
+ n = n->rb_right;
+ else
+ return buffer;
+ }
+ return NULL;
+}
+
+static int binder_update_page_range(struct binder_proc *proc, int allocate,
+ void *start, void *end, struct vm_area_struct *vma)
+{
+ void *page_addr;
+ unsigned long user_page_addr;
+ struct vm_struct tmp_area;
+ struct page **page;
+ struct mm_struct *mm;
+
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: %s pages %p-%p\n",
+ proc->pid, allocate ? "allocate" : "free", start, end);
+
+ if (end <= start)
+ return 0;
+
+ if (vma)
+ mm = NULL;
+ else
+ mm = get_task_mm(proc->tsk);
+
+ if (mm) {
+ down_write(&mm->mmap_sem);
+ vma = proc->vma;
+ }
+
+ if (allocate == 0)
+ goto free_range;
+
+ if (vma == NULL) {
+ printk(KERN_ERR "binder: %d: binder_alloc_buf failed to "
+ "map pages in userspace, no vma\n", proc->pid);
+ goto err_no_vma;
+ }
+
+ for (page_addr = start; page_addr < end; page_addr += PAGE_SIZE) {
+ int ret;
+ struct page **page_array_ptr;
+ page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
+
+ BUG_ON(*page);
+ *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+ if (*page == NULL) {
+ printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
+ "for page at %p\n", proc->pid, page_addr);
+ goto err_alloc_page_failed;
+ }
+ tmp_area.addr = page_addr;
+ tmp_area.size = PAGE_SIZE + PAGE_SIZE /* guard page? */;
+ page_array_ptr = page;
+ ret = map_vm_area(&tmp_area, PAGE_KERNEL, &page_array_ptr);
+ if (ret) {
+ printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
+ "to map page at %p in kernel\n",
+ proc->pid, page_addr);
+ goto err_map_kernel_failed;
+ }
+ user_page_addr = (size_t)page_addr + proc->user_buffer_offset;
+ ret = vm_insert_page(vma, user_page_addr, page[0]);
+ if (ret) {
+ printk(KERN_ERR "binder: %d: binder_alloc_buf failed "
+ "to map page at %lx in userspace\n",
+ proc->pid, user_page_addr);
+ goto err_vm_insert_page_failed;
+ }
+ /* vm_insert_page does not seem to increment the refcount */
+ }
+ if (mm) {
+ up_write(&mm->mmap_sem);
+ mmput(mm);
+ }
+ return 0;
+
+free_range:
+ for (page_addr = end - PAGE_SIZE; page_addr >= start;
+ page_addr -= PAGE_SIZE) {
+ page = &proc->pages[(page_addr - proc->buffer) / PAGE_SIZE];
+ if (vma)
+ zap_page_range(vma, (size_t)page_addr +
+ proc->user_buffer_offset, PAGE_SIZE, NULL);
+err_vm_insert_page_failed:
+ unmap_kernel_range((unsigned long)page_addr, PAGE_SIZE);
+err_map_kernel_failed:
+ __free_page(*page);
+ *page = NULL;
+err_alloc_page_failed:
+ ;
+ }
+err_no_vma:
+ if (mm) {
+ up_write(&mm->mmap_sem);
+ mmput(mm);
+ }
+ return -ENOMEM;
+}
+
+static struct binder_buffer *binder_alloc_buf(struct binder_proc *proc,
+ size_t data_size, size_t offsets_size, int is_async)
+{
+ struct rb_node *n = proc->free_buffers.rb_node;
+ struct binder_buffer *buffer;
+ size_t buffer_size;
+ struct rb_node *best_fit = NULL;
+ void *has_page_addr;
+ void *end_page_addr;
+ size_t size;
+
+ if (proc->vma == NULL) {
+ printk(KERN_ERR "binder: %d: binder_alloc_buf, no vma\n",
+ proc->pid);
+ return NULL;
+ }
+
+ size = ALIGN(data_size, sizeof(void *)) +
+ ALIGN(offsets_size, sizeof(void *));
+
+ if (size < data_size || size < offsets_size) {
+ binder_user_error("binder: %d: got transaction with invalid "
+ "size %d-%d\n", proc->pid, data_size, offsets_size);
+ return NULL;
+ }
+
+ if (is_async &&
+ proc->free_async_space < size + sizeof(struct binder_buffer)) {
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_ERR "binder: %d: binder_alloc_buf size %d f"
+ "ailed, no async space left\n", proc->pid, size);
+ return NULL;
+ }
+
+ while (n) {
+ buffer = rb_entry(n, struct binder_buffer, rb_node);
+ BUG_ON(!buffer->free);
+ buffer_size = binder_buffer_size(proc, buffer);
+
+ if (size < buffer_size) {
+ best_fit = n;
+ n = n->rb_left;
+ } else if (size > buffer_size)
+ n = n->rb_right;
+ else {
+ best_fit = n;
+ break;
+ }
+ }
+ if (best_fit == NULL) {
+ printk(KERN_ERR "binder: %d: binder_alloc_buf size %d failed, "
+ "no address space\n", proc->pid, size);
+ return NULL;
+ }
+ if (n == NULL) {
+ buffer = rb_entry(best_fit, struct binder_buffer, rb_node);
+ buffer_size = binder_buffer_size(proc, buffer);
+ }
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: binder_alloc_buf size %d got buff"
+ "er %p size %d\n", proc->pid, size, buffer, buffer_size);
+
+ has_page_addr =
+ (void *)(((size_t)buffer->data + buffer_size) & PAGE_MASK);
+ if (n == NULL) {
+ if (size + sizeof(struct binder_buffer) + 4 >= buffer_size)
+ buffer_size = size; /* no room for other buffers */
+ else
+ buffer_size = size + sizeof(struct binder_buffer);
+ }
+ end_page_addr = (void *)PAGE_ALIGN((size_t)buffer->data + buffer_size);
+ if (end_page_addr > has_page_addr)
+ end_page_addr = has_page_addr;
+ if (binder_update_page_range(proc, 1,
+ (void *)PAGE_ALIGN((size_t)buffer->data), end_page_addr, NULL))
+ return NULL;
+
+ rb_erase(best_fit, &proc->free_buffers);
+ buffer->free = 0;
+ binder_insert_allocated_buffer(proc, buffer);
+ if (buffer_size != size) {
+ struct binder_buffer *new_buffer = (void *)buffer->data + size;
+ list_add(&new_buffer->entry, &buffer->entry);
+ new_buffer->free = 1;
+ binder_insert_free_buffer(proc, new_buffer);
+ }
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: binder_alloc_buf size %d got "
+ "%p\n", proc->pid, size, buffer);
+ buffer->data_size = data_size;
+ buffer->offsets_size = offsets_size;
+ buffer->async_transaction = is_async;
+ if (is_async) {
+ proc->free_async_space -= size + sizeof(struct binder_buffer);
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC_ASYNC)
+ printk(KERN_INFO "binder: %d: binder_alloc_buf size %d "
+ "async free %d\n", proc->pid, size,
+ proc->free_async_space);
+ }
+
+ return buffer;
+}
+
+static void *buffer_start_page(struct binder_buffer *buffer)
+{
+ return (void *)((size_t)buffer & PAGE_MASK);
+}
+
+static void *buffer_end_page(struct binder_buffer *buffer)
+{
+ return (void *)(((size_t)(buffer + 1) - 1) & PAGE_MASK);
+}
+
+static void binder_delete_free_buffer(
+ struct binder_proc *proc, struct binder_buffer *buffer)
+{
+ struct binder_buffer *prev, *next = NULL;
+ int free_page_end = 1;
+ int free_page_start = 1;
+
+ BUG_ON(proc->buffers.next == &buffer->entry);
+ prev = list_entry(buffer->entry.prev, struct binder_buffer, entry);
+ BUG_ON(!prev->free);
+ if (buffer_end_page(prev) == buffer_start_page(buffer)) {
+ free_page_start = 0;
+ if (buffer_end_page(prev) == buffer_end_page(buffer))
+ free_page_end = 0;
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: merge free, buffer %p "
+ "share page with %p\n", proc->pid, buffer, prev);
+ }
+
+ if (!list_is_last(&buffer->entry, &proc->buffers)) {
+ next = list_entry(buffer->entry.next,
+ struct binder_buffer, entry);
+ if (buffer_start_page(next) == buffer_end_page(buffer)) {
+ free_page_end = 0;
+ if (buffer_start_page(next) ==
+ buffer_start_page(buffer))
+ free_page_start = 0;
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: merge free, "
+ "buffer %p share page with %p\n",
+ proc->pid, buffer, prev);
+ }
+ }
+ list_del(&buffer->entry);
+ if (free_page_start || free_page_end) {
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: merge free, buffer %p do "
+ "not share page%s%s with with %p or %p\n",
+ proc->pid, buffer, free_page_start ? "" : " end",
+ free_page_end ? "" : " start", prev, next);
+ binder_update_page_range(proc, 0, free_page_start ?
+ buffer_start_page(buffer) : buffer_end_page(buffer),
+ (free_page_end ? buffer_end_page(buffer) :
+ buffer_start_page(buffer)) + PAGE_SIZE, NULL);
+ }
+}
+
+static void binder_free_buf(
+ struct binder_proc *proc, struct binder_buffer *buffer)
+{
+ size_t size, buffer_size;
+
+ buffer_size = binder_buffer_size(proc, buffer);
+
+ size = ALIGN(buffer->data_size, sizeof(void *)) +
+ ALIGN(buffer->offsets_size, sizeof(void *));
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder: %d: binder_free_buf %p size %d buffer"
+ "_size %d\n", proc->pid, buffer, size, buffer_size);
+
+ BUG_ON(buffer->free);
+ BUG_ON(size > buffer_size);
+ BUG_ON(buffer->transaction != NULL);
+ BUG_ON((void *)buffer < proc->buffer);
+ BUG_ON((void *)buffer > proc->buffer + proc->buffer_size);
+
+ if (buffer->async_transaction) {
+ proc->free_async_space += size + sizeof(struct binder_buffer);
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC_ASYNC)
+ printk(KERN_INFO "binder: %d: binder_free_buf size %d "
+ "async free %d\n", proc->pid, size,
+ proc->free_async_space);
+ }
+
+ binder_update_page_range(proc, 0,
+ (void *)PAGE_ALIGN((size_t)buffer->data),
+ (void *)(((size_t)buffer->data + buffer_size) & PAGE_MASK),
+ NULL);
+ rb_erase(&buffer->rb_node, &proc->allocated_buffers);
+ buffer->free = 1;
+ if (!list_is_last(&buffer->entry, &proc->buffers)) {
+ struct binder_buffer *next = list_entry(buffer->entry.next,
+ struct binder_buffer, entry);
+ if (next->free) {
+ rb_erase(&next->rb_node, &proc->free_buffers);
+ binder_delete_free_buffer(proc, next);
+ }
+ }
+ if (proc->buffers.next != &buffer->entry) {
+ struct binder_buffer *prev = list_entry(buffer->entry.prev,
+ struct binder_buffer, entry);
+ if (prev->free) {
+ binder_delete_free_buffer(proc, buffer);
+ rb_erase(&prev->rb_node, &proc->free_buffers);
+ buffer = prev;
+ }
+ }
+ binder_insert_free_buffer(proc, buffer);
+}
+
+static struct binder_node *
+binder_get_node(struct binder_proc *proc, void __user *ptr)
+{
+ struct rb_node *n = proc->nodes.rb_node;
+ struct binder_node *node;
+
+ while (n) {
+ node = rb_entry(n, struct binder_node, rb_node);
+
+ if (ptr < node->ptr)
+ n = n->rb_left;
+ else if (ptr > node->ptr)
+ n = n->rb_right;
+ else
+ return node;
+ }
+ return NULL;
+}
+
+static struct binder_node *
+binder_new_node(struct binder_proc *proc, void __user *ptr, void __user *cookie)
+{
+ struct rb_node **p = &proc->nodes.rb_node;
+ struct rb_node *parent = NULL;
+ struct binder_node *node;
+
+ while (*p) {
+ parent = *p;
+ node = rb_entry(parent, struct binder_node, rb_node);
+
+ if (ptr < node->ptr)
+ p = &(*p)->rb_left;
+ else if (ptr > node->ptr)
+ p = &(*p)->rb_right;
+ else
+ return NULL;
+ }
+
+ node = kzalloc(sizeof(*node), GFP_KERNEL);
+ if (node == NULL)
+ return NULL;
+ binder_stats.obj_created[BINDER_STAT_NODE]++;
+ rb_link_node(&node->rb_node, parent, p);
+ rb_insert_color(&node->rb_node, &proc->nodes);
+ node->debug_id = ++binder_last_id;
+ node->proc = proc;
+ node->ptr = ptr;
+ node->cookie = cookie;
+ node->work.type = BINDER_WORK_NODE;
+ INIT_LIST_HEAD(&node->work.entry);
+ INIT_LIST_HEAD(&node->async_todo);
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: %d:%d node %d u%p c%p created\n",
+ proc->pid, current->pid, node->debug_id,
+ node->ptr, node->cookie);
+ return node;
+}
+
+static int
+binder_inc_node(struct binder_node *node, int strong, int internal,
+ struct list_head *target_list)
+{
+ if (strong) {
+ if (internal) {
+ if (target_list == NULL &&
+ node->internal_strong_refs == 0 &&
+ !(node == binder_context_mgr_node &&
+ node->has_strong_ref)) {
+ printk(KERN_ERR "binder: invalid inc strong "
+ "node for %d\n", node->debug_id);
+ return -EINVAL;
+ }
+ node->internal_strong_refs++;
+ } else
+ node->local_strong_refs++;
+ if (!node->has_strong_ref && target_list) {
+ list_del_init(&node->work.entry);
+ list_add_tail(&node->work.entry, target_list);
+ }
+ } else {
+ if (!internal)
+ node->local_weak_refs++;
+ if (!node->has_weak_ref && list_empty(&node->work.entry)) {
+ if (target_list == NULL) {
+ printk(KERN_ERR "binder: invalid inc weak node "
+ "for %d\n", node->debug_id);
+ return -EINVAL;
+ }
+ list_add_tail(&node->work.entry, target_list);
+ }
+ }
+ return 0;
+}
+
+static int
+binder_dec_node(struct binder_node *node, int strong, int internal)
+{
+ if (strong) {
+ if (internal)
+ node->internal_strong_refs--;
+ else
+ node->local_strong_refs--;
+ if (node->local_strong_refs || node->internal_strong_refs)
+ return 0;
+ } else {
+ if (!internal)
+ node->local_weak_refs--;
+ if (node->local_weak_refs || !hlist_empty(&node->refs))
+ return 0;
+ }
+ if (node->proc && (node->has_strong_ref || node->has_weak_ref)) {
+ if (list_empty(&node->work.entry)) {
+ list_add_tail(&node->work.entry, &node->proc->todo);
+ wake_up_interruptible(&node->proc->wait);
+ }
+ } else {
+ if (hlist_empty(&node->refs) && !node->local_strong_refs &&
+ !node->local_weak_refs) {
+ list_del_init(&node->work.entry);
+ if (node->proc) {
+ rb_erase(&node->rb_node, &node->proc->nodes);
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: refless node %d deleted\n", node->debug_id);
+ } else {
+ hlist_del(&node->dead_node);
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: dead node %d deleted\n", node->debug_id);
+ }
+ kfree(node);
+ binder_stats.obj_deleted[BINDER_STAT_NODE]++;
+ }
+ }
+
+ return 0;
+}
+
+
+static struct binder_ref *
+binder_get_ref(struct binder_proc *proc, uint32_t desc)
+{
+ struct rb_node *n = proc->refs_by_desc.rb_node;
+ struct binder_ref *ref;
+
+ while (n) {
+ ref = rb_entry(n, struct binder_ref, rb_node_desc);
+
+ if (desc < ref->desc)
+ n = n->rb_left;
+ else if (desc > ref->desc)
+ n = n->rb_right;
+ else
+ return ref;
+ }
+ return NULL;
+}
+
+static struct binder_ref *
+binder_get_ref_for_node(struct binder_proc *proc, struct binder_node *node)
+{
+ struct rb_node *n;
+ struct rb_node **p = &proc->refs_by_node.rb_node;
+ struct rb_node *parent = NULL;
+ struct binder_ref *ref, *new_ref;
+
+ while (*p) {
+ parent = *p;
+ ref = rb_entry(parent, struct binder_ref, rb_node_node);
+
+ if (node < ref->node)
+ p = &(*p)->rb_left;
+ else if (node > ref->node)
+ p = &(*p)->rb_right;
+ else
+ return ref;
+ }
+ new_ref = kzalloc(sizeof(*ref), GFP_KERNEL);
+ if (new_ref == NULL)
+ return NULL;
+ binder_stats.obj_created[BINDER_STAT_REF]++;
+ new_ref->debug_id = ++binder_last_id;
+ new_ref->proc = proc;
+ new_ref->node = node;
+ rb_link_node(&new_ref->rb_node_node, parent, p);
+ rb_insert_color(&new_ref->rb_node_node, &proc->refs_by_node);
+
+ new_ref->desc = (node == binder_context_mgr_node) ? 0 : 1;
+ for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
+ ref = rb_entry(n, struct binder_ref, rb_node_desc);
+ if (ref->desc > new_ref->desc)
+ break;
+ new_ref->desc = ref->desc + 1;
+ }
+
+ p = &proc->refs_by_desc.rb_node;
+ while (*p) {
+ parent = *p;
+ ref = rb_entry(parent, struct binder_ref, rb_node_desc);
+
+ if (new_ref->desc < ref->desc)
+ p = &(*p)->rb_left;
+ else if (new_ref->desc > ref->desc)
+ p = &(*p)->rb_right;
+ else
+ BUG();
+ }
+ rb_link_node(&new_ref->rb_node_desc, parent, p);
+ rb_insert_color(&new_ref->rb_node_desc, &proc->refs_by_desc);
+ if (node) {
+ hlist_add_head(&new_ref->node_entry, &node->refs);
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: %d new ref %d desc %d for "
+ "node %d\n", proc->pid, new_ref->debug_id,
+ new_ref->desc, node->debug_id);
+ } else {
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: %d new ref %d desc %d for "
+ "dead node\n", proc->pid, new_ref->debug_id,
+ new_ref->desc);
+ }
+ return new_ref;
+}
+
+static void
+binder_delete_ref(struct binder_ref *ref)
+{
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: %d delete ref %d desc %d for "
+ "node %d\n", ref->proc->pid, ref->debug_id,
+ ref->desc, ref->node->debug_id);
+ rb_erase(&ref->rb_node_desc, &ref->proc->refs_by_desc);
+ rb_erase(&ref->rb_node_node, &ref->proc->refs_by_node);
+ if (ref->strong)
+ binder_dec_node(ref->node, 1, 1);
+ hlist_del(&ref->node_entry);
+ binder_dec_node(ref->node, 0, 1);
+ if (ref->death) {
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
+ printk(KERN_INFO "binder: %d delete ref %d desc %d "
+ "has death notification\n", ref->proc->pid,
+ ref->debug_id, ref->desc);
+ list_del(&ref->death->work.entry);
+ kfree(ref->death);
+ binder_stats.obj_deleted[BINDER_STAT_DEATH]++;
+ }
+ kfree(ref);
+ binder_stats.obj_deleted[BINDER_STAT_REF]++;
+}
+
+static int
+binder_inc_ref(
+ struct binder_ref *ref, int strong, struct list_head *target_list)
+{
+ int ret;
+ if (strong) {
+ if (ref->strong == 0) {
+ ret = binder_inc_node(ref->node, 1, 1, target_list);
+ if (ret)
+ return ret;
+ }
+ ref->strong++;
+ } else {
+ if (ref->weak == 0) {
+ ret = binder_inc_node(ref->node, 0, 1, target_list);
+ if (ret)
+ return ret;
+ }
+ ref->weak++;
+ }
+ return 0;
+}
+
+
+static int
+binder_dec_ref(struct binder_ref *ref, int strong)
+{
+ if (strong) {
+ if (ref->strong == 0) {
+ binder_user_error("binder: %d invalid dec strong, "
+ "ref %d desc %d s %d w %d\n",
+ ref->proc->pid, ref->debug_id,
+ ref->desc, ref->strong, ref->weak);
+ return -EINVAL;
+ }
+ ref->strong--;
+ if (ref->strong == 0) {
+ int ret;
+ ret = binder_dec_node(ref->node, strong, 1);
+ if (ret)
+ return ret;
+ }
+ } else {
+ if (ref->weak == 0) {
+ binder_user_error("binder: %d invalid dec weak, "
+ "ref %d desc %d s %d w %d\n",
+ ref->proc->pid, ref->debug_id,
+ ref->desc, ref->strong, ref->weak);
+ return -EINVAL;
+ }
+ ref->weak--;
+ }
+ if (ref->strong == 0 && ref->weak == 0)
+ binder_delete_ref(ref);
+ return 0;
+}
+
+static void
+binder_pop_transaction(
+ struct binder_thread *target_thread, struct binder_transaction *t)
+{
+ if (target_thread) {
+ BUG_ON(target_thread->transaction_stack != t);
+ BUG_ON(target_thread->transaction_stack->from != target_thread);
+ target_thread->transaction_stack =
+ target_thread->transaction_stack->from_parent;
+ t->from = NULL;
+ }
+ t->need_reply = 0;
+ if (t->buffer)
+ t->buffer->transaction = NULL;
+ kfree(t);
+ binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
+}
+
+static void
+binder_send_failed_reply(struct binder_transaction *t, uint32_t error_code)
+{
+ struct binder_thread *target_thread;
+ BUG_ON(t->flags & TF_ONE_WAY);
+ while (1) {
+ target_thread = t->from;
+ if (target_thread) {
+ if (target_thread->return_error != BR_OK &&
+ target_thread->return_error2 == BR_OK) {
+ target_thread->return_error2 =
+ target_thread->return_error;
+ target_thread->return_error = BR_OK;
+ }
+ if (target_thread->return_error == BR_OK) {
+ if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
+ printk(KERN_INFO "binder: send failed reply for transaction %d to %d:%d\n",
+ t->debug_id, target_thread->proc->pid, target_thread->pid);
+
+ binder_pop_transaction(target_thread, t);
+ target_thread->return_error = error_code;
+ wake_up_interruptible(&target_thread->wait);
+ } else {
+ printk(KERN_ERR "binder: reply failed, target "
+ "thread, %d:%d, has error code %d "
+ "already\n", target_thread->proc->pid,
+ target_thread->pid,
+ target_thread->return_error);
+ }
+ return;
+ } else {
+ struct binder_transaction *next = t->from_parent;
+
+ if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
+ printk(KERN_INFO "binder: send failed reply "
+ "for transaction %d, target dead\n",
+ t->debug_id);
+
+ binder_pop_transaction(target_thread, t);
+ if (next == NULL) {
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
+ printk(KERN_INFO "binder: reply failed,"
+ " no target thread at root\n");
+ return;
+ }
+ t = next;
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
+ printk(KERN_INFO "binder: reply failed, no targ"
+ "et thread -- retry %d\n", t->debug_id);
+ }
+ }
+}
+
+static void
+binder_transaction_buffer_release(struct binder_proc *proc,
+ struct binder_buffer *buffer, size_t *failed_at);
+
+static void
+binder_transaction(struct binder_proc *proc, struct binder_thread *thread,
+ struct binder_transaction_data *tr, int reply)
+{
+ struct binder_transaction *t;
+ struct binder_work *tcomplete;
+ size_t *offp, *off_end;
+ struct binder_proc *target_proc;
+ struct binder_thread *target_thread = NULL;
+ struct binder_node *target_node = NULL;
+ struct list_head *target_list;
+ wait_queue_head_t *target_wait;
+ struct binder_transaction *in_reply_to = NULL;
+ struct binder_transaction_log_entry *e;
+ uint32_t return_error;
+
+ e = binder_transaction_log_add(&binder_transaction_log);
+ e->call_type = reply ? 2 : !!(tr->flags & TF_ONE_WAY);
+ e->from_proc = proc->pid;
+ e->from_thread = thread->pid;
+ e->target_handle = tr->target.handle;
+ e->data_size = tr->data_size;
+ e->offsets_size = tr->offsets_size;
+
+ if (reply) {
+ in_reply_to = thread->transaction_stack;
+ if (in_reply_to == NULL) {
+ binder_user_error("binder: %d:%d got reply transaction "
+ "with no transaction stack\n",
+ proc->pid, thread->pid);
+ return_error = BR_FAILED_REPLY;
+ goto err_empty_call_stack;
+ }
+ binder_set_nice(in_reply_to->saved_priority);
+ if (in_reply_to->to_thread != thread) {
+ binder_user_error("binder: %d:%d got reply transaction "
+ "with bad transaction stack,"
+ " transaction %d has target %d:%d\n",
+ proc->pid, thread->pid, in_reply_to->debug_id,
+ in_reply_to->to_proc ?
+ in_reply_to->to_proc->pid : 0,
+ in_reply_to->to_thread ?
+ in_reply_to->to_thread->pid : 0);
+ return_error = BR_FAILED_REPLY;
+ in_reply_to = NULL;
+ goto err_bad_call_stack;
+ }
+ thread->transaction_stack = in_reply_to->to_parent;
+ target_thread = in_reply_to->from;
+ if (target_thread == NULL) {
+ return_error = BR_DEAD_REPLY;
+ goto err_dead_binder;
+ }
+ if (target_thread->transaction_stack != in_reply_to) {
+ binder_user_error("binder: %d:%d got reply transaction "
+ "with bad target transaction stack %d, "
+ "expected %d\n",
+ proc->pid, thread->pid,
+ target_thread->transaction_stack ?
+ target_thread->transaction_stack->debug_id : 0,
+ in_reply_to->debug_id);
+ return_error = BR_FAILED_REPLY;
+ in_reply_to = NULL;
+ target_thread = NULL;
+ goto err_dead_binder;
+ }
+ target_proc = target_thread->proc;
+ } else {
+ if (tr->target.handle) {
+ struct binder_ref *ref;
+ ref = binder_get_ref(proc, tr->target.handle);
+ if (ref == NULL) {
+ binder_user_error("binder: %d:%d got "
+ "transaction to invalid handle\n",
+ proc->pid, thread->pid);
+ return_error = BR_FAILED_REPLY;
+ goto err_invalid_target_handle;
+ }
+ target_node = ref->node;
+ } else {
+ target_node = binder_context_mgr_node;
+ if (target_node == NULL) {
+ return_error = BR_DEAD_REPLY;
+ goto err_no_context_mgr_node;
+ }
+ }
+ e->to_node = target_node->debug_id;
+ target_proc = target_node->proc;
+ if (target_proc == NULL) {
+ return_error = BR_DEAD_REPLY;
+ goto err_dead_binder;
+ }
+ if (!(tr->flags & TF_ONE_WAY) && thread->transaction_stack) {
+ struct binder_transaction *tmp;
+ tmp = thread->transaction_stack;
+ while (tmp) {
+ if (tmp->from && tmp->from->proc == target_proc)
+ target_thread = tmp->from;
+ tmp = tmp->from_parent;
+ }
+ }
+ }
+ if (target_thread) {
+ e->to_thread = target_thread->pid;
+ target_list = &target_thread->todo;
+ target_wait = &target_thread->wait;
+ } else {
+ target_list = &target_proc->todo;
+ target_wait = &target_proc->wait;
+ }
+ e->to_proc = target_proc->pid;
+
+ /* TODO: reuse incoming transaction for reply */
+ t = kzalloc(sizeof(*t), GFP_KERNEL);
+ if (t == NULL) {
+ return_error = BR_FAILED_REPLY;
+ goto err_alloc_t_failed;
+ }
+ binder_stats.obj_created[BINDER_STAT_TRANSACTION]++;
+
+ tcomplete = kzalloc(sizeof(*tcomplete), GFP_KERNEL);
+ if (tcomplete == NULL) {
+ return_error = BR_FAILED_REPLY;
+ goto err_alloc_tcomplete_failed;
+ }
+ binder_stats.obj_created[BINDER_STAT_TRANSACTION_COMPLETE]++;
+
+ t->debug_id = ++binder_last_id;
+ e->debug_id = t->debug_id;
+
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION) {
+ if (reply)
+ printk(KERN_INFO "binder: %d:%d BC_REPLY %d -> %d:%d, "
+ "data %p-%p size %d-%d\n",
+ proc->pid, thread->pid, t->debug_id,
+ target_proc->pid, target_thread->pid,
+ tr->data.ptr.buffer, tr->data.ptr.offsets,
+ tr->data_size, tr->offsets_size);
+ else
+ printk(KERN_INFO "binder: %d:%d BC_TRANSACTION %d -> "
+ "%d - node %d, data %p-%p size %d-%d\n",
+ proc->pid, thread->pid, t->debug_id,
+ target_proc->pid, target_node->debug_id,
+ tr->data.ptr.buffer, tr->data.ptr.offsets,
+ tr->data_size, tr->offsets_size);
+ }
+
+ if (!reply && !(tr->flags & TF_ONE_WAY))
+ t->from = thread;
+ else
+ t->from = NULL;
+ t->sender_euid = proc->tsk->euid;
+ t->to_proc = target_proc;
+ t->to_thread = target_thread;
+ t->code = tr->code;
+ t->flags = tr->flags;
+ t->priority = task_nice(current);
+ t->buffer = binder_alloc_buf(target_proc, tr->data_size,
+ tr->offsets_size, !reply && (t->flags & TF_ONE_WAY));
+ if (t->buffer == NULL) {
+ return_error = BR_FAILED_REPLY;
+ goto err_binder_alloc_buf_failed;
+ }
+ t->buffer->allow_user_free = 0;
+ t->buffer->debug_id = t->debug_id;
+ t->buffer->transaction = t;
+ t->buffer->target_node = target_node;
+ if (target_node)
+ binder_inc_node(target_node, 1, 0, NULL);
+
+ offp = (size_t *)(t->buffer->data + ALIGN(tr->data_size, sizeof(void *)));
+
+ if (copy_from_user(t->buffer->data, tr->data.ptr.buffer, tr->data_size)) {
+ binder_user_error("binder: %d:%d got transaction with invalid "
+ "data ptr\n", proc->pid, thread->pid);
+ return_error = BR_FAILED_REPLY;
+ goto err_copy_data_failed;
+ }
+ if (copy_from_user(offp, tr->data.ptr.offsets, tr->offsets_size)) {
+ binder_user_error("binder: %d:%d got transaction with invalid "
+ "offsets ptr\n", proc->pid, thread->pid);
+ return_error = BR_FAILED_REPLY;
+ goto err_copy_data_failed;
+ }
+ off_end = (void *)offp + tr->offsets_size;
+ for (; offp < off_end; offp++) {
+ struct flat_binder_object *fp;
+ if (*offp > t->buffer->data_size - sizeof(*fp)) {
+ binder_user_error("binder: %d:%d got transaction with "
+ "invalid offset, %d\n",
+ proc->pid, thread->pid, *offp);
+ return_error = BR_FAILED_REPLY;
+ goto err_bad_offset;
+ }
+ fp = (struct flat_binder_object *)(t->buffer->data + *offp);
+ switch (fp->type) {
+ case BINDER_TYPE_BINDER:
+ case BINDER_TYPE_WEAK_BINDER: {
+ struct binder_ref *ref;
+ struct binder_node *node = binder_get_node(proc, fp->binder);
+ if (node == NULL) {
+ node = binder_new_node(proc, fp->binder, fp->cookie);
+ if (node == NULL) {
+ return_error = BR_FAILED_REPLY;
+ goto err_binder_new_node_failed;
+ }
+ node->min_priority = fp->flags & FLAT_BINDER_FLAG_PRIORITY_MASK;
+ node->accept_fds = !!(fp->flags & FLAT_BINDER_FLAG_ACCEPTS_FDS);
+ }
+ if (fp->cookie != node->cookie) {
+ binder_user_error("binder: %d:%d sending u%p "
+ "node %d, cookie mismatch %p != %p\n",
+ proc->pid, thread->pid,
+ fp->binder, node->debug_id,
+ fp->cookie, node->cookie);
+ goto err_binder_get_ref_for_node_failed;
+ }
+ ref = binder_get_ref_for_node(target_proc, node);
+ if (ref == NULL) {
+ return_error = BR_FAILED_REPLY;
+ goto err_binder_get_ref_for_node_failed;
+ }
+ if (fp->type == BINDER_TYPE_BINDER)
+ fp->type = BINDER_TYPE_HANDLE;
+ else
+ fp->type = BINDER_TYPE_WEAK_HANDLE;
+ fp->handle = ref->desc;
+ binder_inc_ref(ref, fp->type == BINDER_TYPE_HANDLE, &thread->todo);
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " node %d u%p -> ref %d desc %d\n",
+ node->debug_id, node->ptr, ref->debug_id, ref->desc);
+ } break;
+ case BINDER_TYPE_HANDLE:
+ case BINDER_TYPE_WEAK_HANDLE: {
+ struct binder_ref *ref = binder_get_ref(proc, fp->handle);
+ if (ref == NULL) {
+ binder_user_error("binder: %d:%d got "
+ "transaction with invalid "
+ "handle, %ld\n", proc->pid,
+ thread->pid, fp->handle);
+ return_error = BR_FAILED_REPLY;
+ goto err_binder_get_ref_failed;
+ }
+ if (ref->node->proc == target_proc) {
+ if (fp->type == BINDER_TYPE_HANDLE)
+ fp->type = BINDER_TYPE_BINDER;
+ else
+ fp->type = BINDER_TYPE_WEAK_BINDER;
+ fp->binder = ref->node->ptr;
+ fp->cookie = ref->node->cookie;
+ binder_inc_node(ref->node, fp->type == BINDER_TYPE_BINDER, 0, NULL);
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " ref %d desc %d -> node %d u%p\n",
+ ref->debug_id, ref->desc, ref->node->debug_id, ref->node->ptr);
+ } else {
+ struct binder_ref *new_ref;
+ new_ref = binder_get_ref_for_node(target_proc, ref->node);
+ if (new_ref == NULL) {
+ return_error = BR_FAILED_REPLY;
+ goto err_binder_get_ref_for_node_failed;
+ }
+ fp->handle = new_ref->desc;
+ binder_inc_ref(new_ref, fp->type == BINDER_TYPE_HANDLE, NULL);
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " ref %d desc %d -> ref %d desc %d (node %d)\n",
+ ref->debug_id, ref->desc, new_ref->debug_id, new_ref->desc, ref->node->debug_id);
+ }
+ } break;
+
+ case BINDER_TYPE_FD: {
+ int target_fd;
+ struct file *file;
+
+ if (reply) {
+ if (!(in_reply_to->flags & TF_ACCEPT_FDS)) {
+ binder_user_error("binder: %d:%d got reply with fd, %ld, but target does not allow fds\n",
+ proc->pid, thread->pid, fp->handle);
+ return_error = BR_FAILED_REPLY;
+ goto err_fd_not_allowed;
+ }
+ } else if (!target_node->accept_fds) {
+ binder_user_error("binder: %d:%d got transaction with fd, %ld, but target does not allow fds\n",
+ proc->pid, thread->pid, fp->handle);
+ return_error = BR_FAILED_REPLY;
+ goto err_fd_not_allowed;
+ }
+
+ file = fget(fp->handle);
+ if (file == NULL) {
+ binder_user_error("binder: %d:%d got transaction with invalid fd, %ld\n",
+ proc->pid, thread->pid, fp->handle);
+ return_error = BR_FAILED_REPLY;
+ goto err_fget_failed;
+ }
+ target_fd = task_get_unused_fd_flags(target_proc->tsk, O_CLOEXEC);
+ if (target_fd < 0) {
+ fput(file);
+ return_error = BR_FAILED_REPLY;
+ goto err_get_unused_fd_failed;
+ }
+ task_fd_install(target_proc->tsk, target_fd, file);
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " fd %ld -> %d\n", fp->handle, target_fd);
+ /* TODO: fput? */
+ fp->handle = target_fd;
+ } break;
+
+ default:
+ binder_user_error("binder: %d:%d got transactio"
+ "n with invalid object type, %lx\n",
+ proc->pid, thread->pid, fp->type);
+ return_error = BR_FAILED_REPLY;
+ goto err_bad_object_type;
+ }
+ }
+ if (reply) {
+ BUG_ON(t->buffer->async_transaction != 0);
+ binder_pop_transaction(target_thread, in_reply_to);
+ } else if (!(t->flags & TF_ONE_WAY)) {
+ BUG_ON(t->buffer->async_transaction != 0);
+ t->need_reply = 1;
+ t->from_parent = thread->transaction_stack;
+ thread->transaction_stack = t;
+ } else {
+ BUG_ON(target_node == NULL);
+ BUG_ON(t->buffer->async_transaction != 1);
+ if (target_node->has_async_transaction) {
+ target_list = &target_node->async_todo;
+ target_wait = NULL;
+ } else
+ target_node->has_async_transaction = 1;
+ }
+ t->work.type = BINDER_WORK_TRANSACTION;
+ list_add_tail(&t->work.entry, target_list);
+ tcomplete->type = BINDER_WORK_TRANSACTION_COMPLETE;
+ list_add_tail(&tcomplete->entry, &thread->todo);
+ if (target_wait)
+ wake_up_interruptible(target_wait);
+ return;
+
+err_get_unused_fd_failed:
+err_fget_failed:
+err_fd_not_allowed:
+err_binder_get_ref_for_node_failed:
+err_binder_get_ref_failed:
+err_binder_new_node_failed:
+err_bad_object_type:
+err_bad_offset:
+err_copy_data_failed:
+ binder_transaction_buffer_release(target_proc, t->buffer, offp);
+ t->buffer->transaction = NULL;
+ binder_free_buf(target_proc, t->buffer);
+err_binder_alloc_buf_failed:
+ kfree(tcomplete);
+ binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
+err_alloc_tcomplete_failed:
+ kfree(t);
+ binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
+err_alloc_t_failed:
+err_bad_call_stack:
+err_empty_call_stack:
+err_dead_binder:
+err_invalid_target_handle:
+err_no_context_mgr_node:
+ if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
+ printk(KERN_INFO "binder: %d:%d transaction failed %d, size %d-%d\n",
+ proc->pid, thread->pid, return_error,
+ tr->data_size, tr->offsets_size);
+
+ {
+ struct binder_transaction_log_entry *fe;
+ fe = binder_transaction_log_add(&binder_transaction_log_failed);
+ *fe = *e;
+ }
+
+ BUG_ON(thread->return_error != BR_OK);
+ if (in_reply_to) {
+ thread->return_error = BR_TRANSACTION_COMPLETE;
+ binder_send_failed_reply(in_reply_to, return_error);
+ } else
+ thread->return_error = return_error;
+}
+
+static void
+binder_transaction_buffer_release(struct binder_proc *proc, struct binder_buffer *buffer, size_t *failed_at)
+{
+ size_t *offp, *off_end;
+ int debug_id = buffer->debug_id;
+
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO "binder: %d buffer release %d, size %d-%d, failed at %p\n",
+ proc->pid, buffer->debug_id,
+ buffer->data_size, buffer->offsets_size, failed_at);
+
+ if (buffer->target_node)
+ binder_dec_node(buffer->target_node, 1, 0);
+
+ offp = (size_t *)(buffer->data + ALIGN(buffer->data_size, sizeof(void *)));
+ if (failed_at)
+ off_end = failed_at;
+ else
+ off_end = (void *)offp + buffer->offsets_size;
+ for (; offp < off_end; offp++) {
+ struct flat_binder_object *fp;
+ if (*offp > buffer->data_size - sizeof(*fp)) {
+ printk(KERN_ERR "binder: transaction release %d bad offset %d, size %d\n", debug_id, *offp, buffer->data_size);
+ continue;
+ }
+ fp = (struct flat_binder_object *)(buffer->data + *offp);
+ switch (fp->type) {
+ case BINDER_TYPE_BINDER:
+ case BINDER_TYPE_WEAK_BINDER: {
+ struct binder_node *node = binder_get_node(proc, fp->binder);
+ if (node == NULL) {
+ printk(KERN_ERR "binder: transaction release %d bad node %p\n", debug_id, fp->binder);
+ break;
+ }
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " node %d u%p\n",
+ node->debug_id, node->ptr);
+ binder_dec_node(node, fp->type == BINDER_TYPE_BINDER, 0);
+ } break;
+ case BINDER_TYPE_HANDLE:
+ case BINDER_TYPE_WEAK_HANDLE: {
+ struct binder_ref *ref = binder_get_ref(proc, fp->handle);
+ if (ref == NULL) {
+ printk(KERN_ERR "binder: transaction release %d bad handle %ld\n", debug_id, fp->handle);
+ break;
+ }
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " ref %d desc %d (node %d)\n",
+ ref->debug_id, ref->desc, ref->node->debug_id);
+ binder_dec_ref(ref, fp->type == BINDER_TYPE_HANDLE);
+ } break;
+
+ case BINDER_TYPE_FD:
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO " fd %ld\n", fp->handle);
+ if (failed_at)
+ task_close_fd(proc->tsk, fp->handle);
+ break;
+
+ default:
+ printk(KERN_ERR "binder: transaction release %d bad object type %lx\n", debug_id, fp->type);
+ break;
+ }
+ }
+}
+
+int
+binder_thread_write(struct binder_proc *proc, struct binder_thread *thread,
+ void __user *buffer, int size, signed long *consumed)
+{
+ uint32_t cmd;
+ void __user *ptr = buffer + *consumed;
+ void __user *end = buffer + size;
+
+ while (ptr < end && thread->return_error == BR_OK) {
+ if (get_user(cmd, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.bc)) {
+ binder_stats.bc[_IOC_NR(cmd)]++;
+ proc->stats.bc[_IOC_NR(cmd)]++;
+ thread->stats.bc[_IOC_NR(cmd)]++;
+ }
+ switch (cmd) {
+ case BC_INCREFS:
+ case BC_ACQUIRE:
+ case BC_RELEASE:
+ case BC_DECREFS: {
+ uint32_t target;
+ struct binder_ref *ref;
+ const char *debug_string;
+
+ if (get_user(target, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (target == 0 && binder_context_mgr_node &&
+ (cmd == BC_INCREFS || cmd == BC_ACQUIRE)) {
+ ref = binder_get_ref_for_node(proc,
+ binder_context_mgr_node);
+ if (ref->desc != target) {
+ binder_user_error("binder: %d:"
+ "%d tried to acquire "
+ "reference to desc 0, "
+ "got %d instead\n",
+ proc->pid, thread->pid,
+ ref->desc);
+ }
+ } else
+ ref = binder_get_ref(proc, target);
+ if (ref == NULL) {
+ binder_user_error("binder: %d:%d refcou"
+ "nt change on invalid ref %d\n",
+ proc->pid, thread->pid, target);
+ break;
+ }
+ switch (cmd) {
+ case BC_INCREFS:
+ debug_string = "IncRefs";
+ binder_inc_ref(ref, 0, NULL);
+ break;
+ case BC_ACQUIRE:
+ debug_string = "Acquire";
+ binder_inc_ref(ref, 1, NULL);
+ break;
+ case BC_RELEASE:
+ debug_string = "Release";
+ binder_dec_ref(ref, 1);
+ break;
+ case BC_DECREFS:
+ default:
+ debug_string = "DecRefs";
+ binder_dec_ref(ref, 0);
+ break;
+ }
+ if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
+ printk(KERN_INFO "binder: %d:%d %s ref %d desc %d s %d w %d for node %d\n",
+ proc->pid, thread->pid, debug_string, ref->debug_id, ref->desc, ref->strong, ref->weak, ref->node->debug_id);
+ break;
+ }
+ case BC_INCREFS_DONE:
+ case BC_ACQUIRE_DONE: {
+ void __user *node_ptr;
+ void *cookie;
+ struct binder_node *node;
+
+ if (get_user(node_ptr, (void * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+ if (get_user(cookie, (void * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+ node = binder_get_node(proc, node_ptr);
+ if (node == NULL) {
+ binder_user_error("binder: %d:%d "
+ "%s u%p no match\n",
+ proc->pid, thread->pid,
+ cmd == BC_INCREFS_DONE ?
+ "BC_INCREFS_DONE" :
+ "BC_ACQUIRE_DONE",
+ node_ptr);
+ break;
+ }
+ if (cookie != node->cookie) {
+ binder_user_error("binder: %d:%d %s u%p node %d"
+ " cookie mismatch %p != %p\n",
+ proc->pid, thread->pid,
+ cmd == BC_INCREFS_DONE ?
+ "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE",
+ node_ptr, node->debug_id,
+ cookie, node->cookie);
+ break;
+ }
+ if (cmd == BC_ACQUIRE_DONE) {
+ if (node->pending_strong_ref == 0) {
+ binder_user_error("binder: %d:%d "
+ "BC_ACQUIRE_DONE node %d has "
+ "no pending acquire request\n",
+ proc->pid, thread->pid,
+ node->debug_id);
+ break;
+ }
+ node->pending_strong_ref = 0;
+ } else {
+ if (node->pending_weak_ref == 0) {
+ binder_user_error("binder: %d:%d "
+ "BC_INCREFS_DONE node %d has "
+ "no pending increfs request\n",
+ proc->pid, thread->pid,
+ node->debug_id);
+ break;
+ }
+ node->pending_weak_ref = 0;
+ }
+ binder_dec_node(node, cmd == BC_ACQUIRE_DONE, 0);
+ if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
+ printk(KERN_INFO "binder: %d:%d %s node %d ls %d lw %d\n",
+ proc->pid, thread->pid, cmd == BC_INCREFS_DONE ? "BC_INCREFS_DONE" : "BC_ACQUIRE_DONE", node->debug_id, node->local_strong_refs, node->local_weak_refs);
+ break;
+ }
+ case BC_ATTEMPT_ACQUIRE:
+ printk(KERN_ERR "binder: BC_ATTEMPT_ACQUIRE not supported\n");
+ return -EINVAL;
+ case BC_ACQUIRE_RESULT:
+ printk(KERN_ERR "binder: BC_ACQUIRE_RESULT not supported\n");
+ return -EINVAL;
+
+ case BC_FREE_BUFFER: {
+ void __user *data_ptr;
+ struct binder_buffer *buffer;
+
+ if (get_user(data_ptr, (void * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+
+ buffer = binder_buffer_lookup(proc, data_ptr);
+ if (buffer == NULL) {
+ binder_user_error("binder: %d:%d "
+ "BC_FREE_BUFFER u%p no match\n",
+ proc->pid, thread->pid, data_ptr);
+ break;
+ }
+ if (!buffer->allow_user_free) {
+ binder_user_error("binder: %d:%d "
+ "BC_FREE_BUFFER u%p matched "
+ "unreturned buffer\n",
+ proc->pid, thread->pid, data_ptr);
+ break;
+ }
+ if (binder_debug_mask & BINDER_DEBUG_FREE_BUFFER)
+ printk(KERN_INFO "binder: %d:%d BC_FREE_BUFFER u%p found buffer %d for %s transaction\n",
+ proc->pid, thread->pid, data_ptr, buffer->debug_id,
+ buffer->transaction ? "active" : "finished");
+
+ if (buffer->transaction) {
+ buffer->transaction->buffer = NULL;
+ buffer->transaction = NULL;
+ }
+ if (buffer->async_transaction && buffer->target_node) {
+ BUG_ON(!buffer->target_node->has_async_transaction);
+ if (list_empty(&buffer->target_node->async_todo))
+ buffer->target_node->has_async_transaction = 0;
+ else
+ list_move_tail(buffer->target_node->async_todo.next, &thread->todo);
+ }
+ binder_transaction_buffer_release(proc, buffer, NULL);
+ binder_free_buf(proc, buffer);
+ break;
+ }
+
+ case BC_TRANSACTION:
+ case BC_REPLY: {
+ struct binder_transaction_data tr;
+
+ if (copy_from_user(&tr, ptr, sizeof(tr)))
+ return -EFAULT;
+ ptr += sizeof(tr);
+ binder_transaction(proc, thread, &tr, cmd == BC_REPLY);
+ break;
+ }
+
+ case BC_REGISTER_LOOPER:
+ if (binder_debug_mask & BINDER_DEBUG_THREADS)
+ printk(KERN_INFO "binder: %d:%d BC_REGISTER_LOOPER\n",
+ proc->pid, thread->pid);
+ if (thread->looper & BINDER_LOOPER_STATE_ENTERED) {
+ thread->looper |= BINDER_LOOPER_STATE_INVALID;
+ binder_user_error("binder: %d:%d ERROR:"
+ " BC_REGISTER_LOOPER called "
+ "after BC_ENTER_LOOPER\n",
+ proc->pid, thread->pid);
+ } else if (proc->requested_threads == 0) {
+ thread->looper |= BINDER_LOOPER_STATE_INVALID;
+ binder_user_error("binder: %d:%d ERROR:"
+ " BC_REGISTER_LOOPER called "
+ "without request\n",
+ proc->pid, thread->pid);
+ } else {
+ proc->requested_threads--;
+ proc->requested_threads_started++;
+ }
+ thread->looper |= BINDER_LOOPER_STATE_REGISTERED;
+ break;
+ case BC_ENTER_LOOPER:
+ if (binder_debug_mask & BINDER_DEBUG_THREADS)
+ printk(KERN_INFO "binder: %d:%d BC_ENTER_LOOPER\n",
+ proc->pid, thread->pid);
+ if (thread->looper & BINDER_LOOPER_STATE_REGISTERED) {
+ thread->looper |= BINDER_LOOPER_STATE_INVALID;
+ binder_user_error("binder: %d:%d ERROR:"
+ " BC_ENTER_LOOPER called after "
+ "BC_REGISTER_LOOPER\n",
+ proc->pid, thread->pid);
+ }
+ thread->looper |= BINDER_LOOPER_STATE_ENTERED;
+ break;
+ case BC_EXIT_LOOPER:
+ if (binder_debug_mask & BINDER_DEBUG_THREADS)
+ printk(KERN_INFO "binder: %d:%d BC_EXIT_LOOPER\n",
+ proc->pid, thread->pid);
+ thread->looper |= BINDER_LOOPER_STATE_EXITED;
+ break;
+
+ case BC_REQUEST_DEATH_NOTIFICATION:
+ case BC_CLEAR_DEATH_NOTIFICATION: {
+ uint32_t target;
+ void __user *cookie;
+ struct binder_ref *ref;
+ struct binder_ref_death *death;
+
+ if (get_user(target, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (get_user(cookie, (void __user * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+ ref = binder_get_ref(proc, target);
+ if (ref == NULL) {
+ binder_user_error("binder: %d:%d %s "
+ "invalid ref %d\n",
+ proc->pid, thread->pid,
+ cmd == BC_REQUEST_DEATH_NOTIFICATION ?
+ "BC_REQUEST_DEATH_NOTIFICATION" :
+ "BC_CLEAR_DEATH_NOTIFICATION",
+ target);
+ break;
+ }
+
+ if (binder_debug_mask & BINDER_DEBUG_DEATH_NOTIFICATION)
+ printk(KERN_INFO "binder: %d:%d %s %p ref %d desc %d s %d w %d for node %d\n",
+ proc->pid, thread->pid,
+ cmd == BC_REQUEST_DEATH_NOTIFICATION ?
+ "BC_REQUEST_DEATH_NOTIFICATION" :
+ "BC_CLEAR_DEATH_NOTIFICATION",
+ cookie, ref->debug_id, ref->desc,
+ ref->strong, ref->weak, ref->node->debug_id);
+
+ if (cmd == BC_REQUEST_DEATH_NOTIFICATION) {
+ if (ref->death) {
+ binder_user_error("binder: %d:%"
+ "d BC_REQUEST_DEATH_NOTI"
+ "FICATION death notific"
+ "ation already set\n",
+ proc->pid, thread->pid);
+ break;
+ }
+ death = kzalloc(sizeof(*death), GFP_KERNEL);
+ if (death == NULL) {
+ thread->return_error = BR_ERROR;
+ if (binder_debug_mask & BINDER_DEBUG_FAILED_TRANSACTION)
+ printk(KERN_INFO "binder: %d:%d "
+ "BC_REQUEST_DEATH_NOTIFICATION failed\n",
+ proc->pid, thread->pid);
+ break;
+ }
+ binder_stats.obj_created[BINDER_STAT_DEATH]++;
+ INIT_LIST_HEAD(&death->work.entry);
+ death->cookie = cookie;
+ ref->death = death;
+ if (ref->node->proc == NULL) {
+ ref->death->work.type = BINDER_WORK_DEAD_BINDER;
+ if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
+ list_add_tail(&ref->death->work.entry, &thread->todo);
+ } else {
+ list_add_tail(&ref->death->work.entry, &proc->todo);
+ wake_up_interruptible(&proc->wait);
+ }
+ }
+ } else {
+ if (ref->death == NULL) {
+ binder_user_error("binder: %d:%"
+ "d BC_CLEAR_DEATH_NOTIFI"
+ "CATION death notificat"
+ "ion not active\n",
+ proc->pid, thread->pid);
+ break;
+ }
+ death = ref->death;
+ if (death->cookie != cookie) {
+ binder_user_error("binder: %d:%"
+ "d BC_CLEAR_DEATH_NOTIFI"
+ "CATION death notificat"
+ "ion cookie mismatch "
+ "%p != %p\n",
+ proc->pid, thread->pid,
+ death->cookie, cookie);
+ break;
+ }
+ ref->death = NULL;
+ if (list_empty(&death->work.entry)) {
+ death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION;
+ if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
+ list_add_tail(&death->work.entry, &thread->todo);
+ } else {
+ list_add_tail(&death->work.entry, &proc->todo);
+ wake_up_interruptible(&proc->wait);
+ }
+ } else {
+ BUG_ON(death->work.type != BINDER_WORK_DEAD_BINDER);
+ death->work.type = BINDER_WORK_DEAD_BINDER_AND_CLEAR;
+ }
+ }
+ } break;
+ case BC_DEAD_BINDER_DONE: {
+ struct binder_work *w;
+ void __user *cookie;
+ struct binder_ref_death *death = NULL;
+ if (get_user(cookie, (void __user * __user *)ptr))
+ return -EFAULT;
+
+ ptr += sizeof(void *);
+ list_for_each_entry(w, &proc->delivered_death, entry) {
+ struct binder_ref_death *tmp_death = container_of(w, struct binder_ref_death, work);
+ if (tmp_death->cookie == cookie) {
+ death = tmp_death;
+ break;
+ }
+ }
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
+ printk(KERN_INFO "binder: %d:%d BC_DEAD_BINDER_DONE %p found %p\n",
+ proc->pid, thread->pid, cookie, death);
+ if (death == NULL) {
+ binder_user_error("binder: %d:%d BC_DEAD"
+ "_BINDER_DONE %p not found\n",
+ proc->pid, thread->pid, cookie);
+ break;
+ }
+
+ list_del_init(&death->work.entry);
+ if (death->work.type == BINDER_WORK_DEAD_BINDER_AND_CLEAR) {
+ death->work.type = BINDER_WORK_CLEAR_DEATH_NOTIFICATION;
+ if (thread->looper & (BINDER_LOOPER_STATE_REGISTERED | BINDER_LOOPER_STATE_ENTERED)) {
+ list_add_tail(&death->work.entry, &thread->todo);
+ } else {
+ list_add_tail(&death->work.entry, &proc->todo);
+ wake_up_interruptible(&proc->wait);
+ }
+ }
+ } break;
+
+ default:
+ printk(KERN_ERR "binder: %d:%d unknown command %d\n", proc->pid, thread->pid, cmd);
+ return -EINVAL;
+ }
+ *consumed = ptr - buffer;
+ }
+ return 0;
+}
+
+void
+binder_stat_br(struct binder_proc *proc, struct binder_thread *thread, uint32_t cmd)
+{
+ if (_IOC_NR(cmd) < ARRAY_SIZE(binder_stats.br)) {
+ binder_stats.br[_IOC_NR(cmd)]++;
+ proc->stats.br[_IOC_NR(cmd)]++;
+ thread->stats.br[_IOC_NR(cmd)]++;
+ }
+}
+
+static int
+binder_has_proc_work(struct binder_proc *proc, struct binder_thread *thread)
+{
+ return !list_empty(&proc->todo) || (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN);
+}
+
+static int
+binder_has_thread_work(struct binder_thread *thread)
+{
+ return !list_empty(&thread->todo) || thread->return_error != BR_OK ||
+ (thread->looper & BINDER_LOOPER_STATE_NEED_RETURN);
+}
+
+static int
+binder_thread_read(struct binder_proc *proc, struct binder_thread *thread,
+ void __user *buffer, int size, signed long *consumed, int non_block)
+{
+ void __user *ptr = buffer + *consumed;
+ void __user *end = buffer + size;
+
+ int ret = 0;
+ int wait_for_proc_work;
+
+ if (*consumed == 0) {
+ if (put_user(BR_NOOP, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ }
+
+retry:
+ wait_for_proc_work = thread->transaction_stack == NULL && list_empty(&thread->todo);
+
+ if (thread->return_error != BR_OK && ptr < end) {
+ if (thread->return_error2 != BR_OK) {
+ if (put_user(thread->return_error2, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (ptr == end)
+ goto done;
+ thread->return_error2 = BR_OK;
+ }
+ if (put_user(thread->return_error, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ thread->return_error = BR_OK;
+ goto done;
+ }
+
+
+ thread->looper |= BINDER_LOOPER_STATE_WAITING;
+ if (wait_for_proc_work)
+ proc->ready_threads++;
+ mutex_unlock(&binder_lock);
+ if (wait_for_proc_work) {
+ if (!(thread->looper & (BINDER_LOOPER_STATE_REGISTERED |
+ BINDER_LOOPER_STATE_ENTERED))) {
+ binder_user_error("binder: %d:%d ERROR: Thread waiting "
+ "for process work before calling BC_REGISTER_"
+ "LOOPER or BC_ENTER_LOOPER (state %x)\n",
+ proc->pid, thread->pid, thread->looper);
+ wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
+ }
+ binder_set_nice(proc->default_priority);
+ if (non_block) {
+ if (!binder_has_proc_work(proc, thread))
+ ret = -EAGAIN;
+ } else
+ ret = wait_event_interruptible_exclusive(proc->wait, binder_has_proc_work(proc, thread));
+ } else {
+ if (non_block) {
+ if (!binder_has_thread_work(thread))
+ ret = -EAGAIN;
+ } else
+ ret = wait_event_interruptible(thread->wait, binder_has_thread_work(thread));
+ }
+ mutex_lock(&binder_lock);
+ if (wait_for_proc_work)
+ proc->ready_threads--;
+ thread->looper &= ~BINDER_LOOPER_STATE_WAITING;
+
+ if (ret)
+ return ret;
+
+ while (1) {
+ uint32_t cmd;
+ struct binder_transaction_data tr;
+ struct binder_work *w;
+ struct binder_transaction *t = NULL;
+
+ if (!list_empty(&thread->todo))
+ w = list_first_entry(&thread->todo, struct binder_work, entry);
+ else if (!list_empty(&proc->todo) && wait_for_proc_work)
+ w = list_first_entry(&proc->todo, struct binder_work, entry);
+ else {
+ if (ptr - buffer == 4 && !(thread->looper & BINDER_LOOPER_STATE_NEED_RETURN)) /* no data added */
+ goto retry;
+ break;
+ }
+
+ if (end - ptr < sizeof(tr) + 4)
+ break;
+
+ switch (w->type) {
+ case BINDER_WORK_TRANSACTION: {
+ t = container_of(w, struct binder_transaction, work);
+ } break;
+ case BINDER_WORK_TRANSACTION_COMPLETE: {
+ cmd = BR_TRANSACTION_COMPLETE;
+ if (put_user(cmd, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+
+ binder_stat_br(proc, thread, cmd);
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION_COMPLETE)
+ printk(KERN_INFO "binder: %d:%d BR_TRANSACTION_COMPLETE\n",
+ proc->pid, thread->pid);
+
+ list_del(&w->entry);
+ kfree(w);
+ binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
+ } break;
+ case BINDER_WORK_NODE: {
+ struct binder_node *node = container_of(w, struct binder_node, work);
+ uint32_t cmd = BR_NOOP;
+ const char *cmd_name;
+ int strong = node->internal_strong_refs || node->local_strong_refs;
+ int weak = !hlist_empty(&node->refs) || node->local_weak_refs || strong;
+ if (weak && !node->has_weak_ref) {
+ cmd = BR_INCREFS;
+ cmd_name = "BR_INCREFS";
+ node->has_weak_ref = 1;
+ node->pending_weak_ref = 1;
+ node->local_weak_refs++;
+ } else if (strong && !node->has_strong_ref) {
+ cmd = BR_ACQUIRE;
+ cmd_name = "BR_ACQUIRE";
+ node->has_strong_ref = 1;
+ node->pending_strong_ref = 1;
+ node->local_strong_refs++;
+ } else if (!strong && node->has_strong_ref) {
+ cmd = BR_RELEASE;
+ cmd_name = "BR_RELEASE";
+ node->has_strong_ref = 0;
+ } else if (!weak && node->has_weak_ref) {
+ cmd = BR_DECREFS;
+ cmd_name = "BR_DECREFS";
+ node->has_weak_ref = 0;
+ }
+ if (cmd != BR_NOOP) {
+ if (put_user(cmd, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (put_user(node->ptr, (void * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+ if (put_user(node->cookie, (void * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+
+ binder_stat_br(proc, thread, cmd);
+ if (binder_debug_mask & BINDER_DEBUG_USER_REFS)
+ printk(KERN_INFO "binder: %d:%d %s %d u%p c%p\n",
+ proc->pid, thread->pid, cmd_name, node->debug_id, node->ptr, node->cookie);
+ } else {
+ list_del_init(&w->entry);
+ if (!weak && !strong) {
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: %d:%d node %d u%p c%p deleted\n",
+ proc->pid, thread->pid, node->debug_id, node->ptr, node->cookie);
+ rb_erase(&node->rb_node, &proc->nodes);
+ kfree(node);
+ binder_stats.obj_deleted[BINDER_STAT_NODE]++;
+ } else {
+ if (binder_debug_mask & BINDER_DEBUG_INTERNAL_REFS)
+ printk(KERN_INFO "binder: %d:%d node %d u%p c%p state unchanged\n",
+ proc->pid, thread->pid, node->debug_id, node->ptr, node->cookie);
+ }
+ }
+ } break;
+ case BINDER_WORK_DEAD_BINDER:
+ case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
+ case BINDER_WORK_CLEAR_DEATH_NOTIFICATION: {
+ struct binder_ref_death *death = container_of(w, struct binder_ref_death, work);
+ uint32_t cmd;
+ if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION)
+ cmd = BR_CLEAR_DEATH_NOTIFICATION_DONE;
+ else
+ cmd = BR_DEAD_BINDER;
+ if (put_user(cmd, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (put_user(death->cookie, (void * __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(void *);
+ if (binder_debug_mask & BINDER_DEBUG_DEATH_NOTIFICATION)
+ printk(KERN_INFO "binder: %d:%d %s %p\n",
+ proc->pid, thread->pid,
+ cmd == BR_DEAD_BINDER ?
+ "BR_DEAD_BINDER" :
+ "BR_CLEAR_DEATH_NOTIFICATION_DONE",
+ death->cookie);
+
+ if (w->type == BINDER_WORK_CLEAR_DEATH_NOTIFICATION) {
+ list_del(&w->entry);
+ kfree(death);
+ binder_stats.obj_deleted[BINDER_STAT_DEATH]++;
+ } else
+ list_move(&w->entry, &proc->delivered_death);
+ if (cmd == BR_DEAD_BINDER)
+ goto done; /* DEAD_BINDER notifications can cause transactions */
+ } break;
+ }
+
+ if (!t)
+ continue;
+
+ BUG_ON(t->buffer == NULL);
+ if (t->buffer->target_node) {
+ struct binder_node *target_node = t->buffer->target_node;
+ tr.target.ptr = target_node->ptr;
+ tr.cookie = target_node->cookie;
+ t->saved_priority = task_nice(current);
+ if (t->priority < target_node->min_priority &&
+ !(t->flags & TF_ONE_WAY))
+ binder_set_nice(t->priority);
+ else if (!(t->flags & TF_ONE_WAY) ||
+ t->saved_priority > target_node->min_priority)
+ binder_set_nice(target_node->min_priority);
+ cmd = BR_TRANSACTION;
+ } else {
+ tr.target.ptr = NULL;
+ tr.cookie = NULL;
+ cmd = BR_REPLY;
+ }
+ tr.code = t->code;
+ tr.flags = t->flags;
+ tr.sender_euid = t->sender_euid;
+
+ if (t->from) {
+ struct task_struct *sender = t->from->proc->tsk;
+ tr.sender_pid = task_tgid_nr_ns(sender, current->nsproxy->pid_ns);
+ } else {
+ tr.sender_pid = 0;
+ }
+
+ tr.data_size = t->buffer->data_size;
+ tr.offsets_size = t->buffer->offsets_size;
+ tr.data.ptr.buffer = (void *)((void *)t->buffer->data + proc->user_buffer_offset);
+ tr.data.ptr.offsets = tr.data.ptr.buffer + ALIGN(t->buffer->data_size, sizeof(void *));
+
+ if (put_user(cmd, (uint32_t __user *)ptr))
+ return -EFAULT;
+ ptr += sizeof(uint32_t);
+ if (copy_to_user(ptr, &tr, sizeof(tr)))
+ return -EFAULT;
+ ptr += sizeof(tr);
+
+ binder_stat_br(proc, thread, cmd);
+ if (binder_debug_mask & BINDER_DEBUG_TRANSACTION)
+ printk(KERN_INFO "binder: %d:%d %s %d %d:%d, cmd %d size %d-%d ptr %p-%p\n",
+ proc->pid, thread->pid,
+ (cmd == BR_TRANSACTION) ? "BR_TRANSACTION" : "BR_REPLY",
+ t->debug_id, t->from ? t->from->proc->pid : 0,
+ t->from ? t->from->pid : 0, cmd,
+ t->buffer->data_size, t->buffer->offsets_size,
+ tr.data.ptr.buffer, tr.data.ptr.offsets);
+
+ list_del(&t->work.entry);
+ t->buffer->allow_user_free = 1;
+ if (cmd == BR_TRANSACTION && !(t->flags & TF_ONE_WAY)) {
+ t->to_parent = thread->transaction_stack;
+ t->to_thread = thread;
+ thread->transaction_stack = t;
+ } else {
+ t->buffer->transaction = NULL;
+ kfree(t);
+ binder_stats.obj_deleted[BINDER_STAT_TRANSACTION]++;
+ }
+ break;
+ }
+
+done:
+
+ *consumed = ptr - buffer;
+ if (proc->requested_threads + proc->ready_threads == 0 &&
+ proc->requested_threads_started < proc->max_threads &&
+ (thread->looper & (BINDER_LOOPER_STATE_REGISTERED |
+ BINDER_LOOPER_STATE_ENTERED)) /* the user-space code fails to */
+ /*spawn a new thread if we leave this out */) {
+ proc->requested_threads++;
+ if (binder_debug_mask & BINDER_DEBUG_THREADS)
+ printk(KERN_INFO "binder: %d:%d BR_SPAWN_LOOPER\n",
+ proc->pid, thread->pid);
+ if (put_user(BR_SPAWN_LOOPER, (uint32_t __user *)buffer))
+ return -EFAULT;
+ }
+ return 0;
+}
+
+static void binder_release_work(struct list_head *list)
+{
+ struct binder_work *w;
+ while (!list_empty(list)) {
+ w = list_first_entry(list, struct binder_work, entry);
+ list_del_init(&w->entry);
+ switch (w->type) {
+ case BINDER_WORK_TRANSACTION: {
+ struct binder_transaction *t = container_of(w, struct binder_transaction, work);
+ if (t->buffer->target_node && !(t->flags & TF_ONE_WAY))
+ binder_send_failed_reply(t, BR_DEAD_REPLY);
+ } break;
+ case BINDER_WORK_TRANSACTION_COMPLETE: {
+ kfree(w);
+ binder_stats.obj_deleted[BINDER_STAT_TRANSACTION_COMPLETE]++;
+ } break;
+ default:
+ break;
+ }
+ }
+
+}
+
+static struct binder_thread *binder_get_thread(struct binder_proc *proc)
+{
+ struct binder_thread *thread = NULL;
+ struct rb_node *parent = NULL;
+ struct rb_node **p = &proc->threads.rb_node;
+
+ while (*p) {
+ parent = *p;
+ thread = rb_entry(parent, struct binder_thread, rb_node);
+
+ if (current->pid < thread->pid)
+ p = &(*p)->rb_left;
+ else if (current->pid > thread->pid)
+ p = &(*p)->rb_right;
+ else
+ break;
+ }
+ if (*p == NULL) {
+ thread = kzalloc(sizeof(*thread), GFP_KERNEL);
+ if (thread == NULL)
+ return NULL;
+ binder_stats.obj_created[BINDER_STAT_THREAD]++;
+ thread->proc = proc;
+ thread->pid = current->pid;
+ init_waitqueue_head(&thread->wait);
+ INIT_LIST_HEAD(&thread->todo);
+ rb_link_node(&thread->rb_node, parent, p);
+ rb_insert_color(&thread->rb_node, &proc->threads);
+ thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN;
+ thread->return_error = BR_OK;
+ thread->return_error2 = BR_OK;
+ }
+ return thread;
+}
+
+static int binder_free_thread(struct binder_proc *proc, struct binder_thread *thread)
+{
+ struct binder_transaction *t;
+ struct binder_transaction *send_reply = NULL;
+ int active_transactions = 0;
+
+ rb_erase(&thread->rb_node, &proc->threads);
+ t = thread->transaction_stack;
+ if (t && t->to_thread == thread)
+ send_reply = t;
+ while (t) {
+ active_transactions++;
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_TRANSACTION)
+ printk(KERN_INFO "binder: release %d:%d transaction %d %s, still active\n",
+ proc->pid, thread->pid, t->debug_id, (t->to_thread == thread) ? "in" : "out");
+ if (t->to_thread == thread) {
+ t->to_proc = NULL;
+ t->to_thread = NULL;
+ if (t->buffer) {
+ t->buffer->transaction = NULL;
+ t->buffer = NULL;
+ }
+ t = t->to_parent;
+ } else if (t->from == thread) {
+ t->from = NULL;
+ t = t->from_parent;
+ } else
+ BUG();
+ }
+ if (send_reply)
+ binder_send_failed_reply(send_reply, BR_DEAD_REPLY);
+ binder_release_work(&thread->todo);
+ kfree(thread);
+ binder_stats.obj_deleted[BINDER_STAT_THREAD]++;
+ return active_transactions;
+}
+
+static unsigned int binder_poll(struct file *filp, struct poll_table_struct *wait)
+{
+ struct binder_proc *proc = filp->private_data;
+ struct binder_thread *thread = NULL;
+ int wait_for_proc_work;
+
+ mutex_lock(&binder_lock);
+ thread = binder_get_thread(proc);
+
+ wait_for_proc_work = thread->transaction_stack == NULL &&
+ list_empty(&thread->todo) && thread->return_error == BR_OK;
+ mutex_unlock(&binder_lock);
+
+ if (wait_for_proc_work) {
+ if (binder_has_proc_work(proc, thread))
+ return POLLIN;
+ poll_wait(filp, &proc->wait, wait);
+ if (binder_has_proc_work(proc, thread))
+ return POLLIN;
+ } else {
+ if (binder_has_thread_work(thread))
+ return POLLIN;
+ poll_wait(filp, &thread->wait, wait);
+ if (binder_has_thread_work(thread))
+ return POLLIN;
+ }
+ return 0;
+}
+
+static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
+{
+ int ret;
+ struct binder_proc *proc = filp->private_data;
+ struct binder_thread *thread;
+ unsigned int size = _IOC_SIZE(cmd);
+ void __user *ubuf = (void __user *)arg;
+
+ /*printk(KERN_INFO "binder_ioctl: %d:%d %x %lx\n", proc->pid, current->pid, cmd, arg);*/
+
+ ret = wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
+ if (ret)
+ return ret;
+
+ mutex_lock(&binder_lock);
+ thread = binder_get_thread(proc);
+ if (thread == NULL) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ switch (cmd) {
+ case BINDER_WRITE_READ: {
+ struct binder_write_read bwr;
+ if (size != sizeof(struct binder_write_read)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ if (copy_from_user(&bwr, ubuf, sizeof(bwr))) {
+ ret = -EFAULT;
+ goto err;
+ }
+ if (binder_debug_mask & BINDER_DEBUG_READ_WRITE)
+ printk(KERN_INFO "binder: %d:%d write %ld at %08lx, read %ld at %08lx\n",
+ proc->pid, thread->pid, bwr.write_size, bwr.write_buffer, bwr.read_size, bwr.read_buffer);
+ if (bwr.write_size > 0) {
+ ret = binder_thread_write(proc, thread, (void __user *)bwr.write_buffer, bwr.write_size, &bwr.write_consumed);
+ if (ret < 0) {
+ bwr.read_consumed = 0;
+ if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
+ ret = -EFAULT;
+ goto err;
+ }
+ }
+ if (bwr.read_size > 0) {
+ ret = binder_thread_read(proc, thread, (void __user *)bwr.read_buffer, bwr.read_size, &bwr.read_consumed, filp->f_flags & O_NONBLOCK);
+ if (!list_empty(&proc->todo))
+ wake_up_interruptible(&proc->wait);
+ if (ret < 0) {
+ if (copy_to_user(ubuf, &bwr, sizeof(bwr)))
+ ret = -EFAULT;
+ goto err;
+ }
+ }
+ if (binder_debug_mask & BINDER_DEBUG_READ_WRITE)
+ printk(KERN_INFO "binder: %d:%d wrote %ld of %ld, read return %ld of %ld\n",
+ proc->pid, thread->pid, bwr.write_consumed, bwr.write_size, bwr.read_consumed, bwr.read_size);
+ if (copy_to_user(ubuf, &bwr, sizeof(bwr))) {
+ ret = -EFAULT;
+ goto err;
+ }
+ break;
+ }
+ case BINDER_SET_MAX_THREADS:
+ if (copy_from_user(&proc->max_threads, ubuf, sizeof(proc->max_threads))) {
+ ret = -EINVAL;
+ goto err;
+ }
+ break;
+ case BINDER_SET_CONTEXT_MGR:
+ if (binder_context_mgr_node != NULL) {
+ printk(KERN_ERR "binder: BINDER_SET_CONTEXT_MGR already set\n");
+ ret = -EBUSY;
+ goto err;
+ }
+ if (binder_context_mgr_uid != -1) {
+ if (binder_context_mgr_uid != current->euid) {
+ printk(KERN_ERR "binder: BINDER_SET_"
+ "CONTEXT_MGR bad uid %d != %d\n",
+ current->euid,
+ binder_context_mgr_uid);
+ ret = -EPERM;
+ goto err;
+ }
+ } else
+ binder_context_mgr_uid = current->euid;
+ binder_context_mgr_node = binder_new_node(proc, NULL, NULL);
+ if (binder_context_mgr_node == NULL) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ binder_context_mgr_node->local_weak_refs++;
+ binder_context_mgr_node->local_strong_refs++;
+ binder_context_mgr_node->has_strong_ref = 1;
+ binder_context_mgr_node->has_weak_ref = 1;
+ break;
+ case BINDER_THREAD_EXIT:
+ if (binder_debug_mask & BINDER_DEBUG_THREADS)
+ printk(KERN_INFO "binder: %d:%d exit\n",
+ proc->pid, thread->pid);
+ binder_free_thread(proc, thread);
+ thread = NULL;
+ break;
+ case BINDER_VERSION:
+ if (size != sizeof(struct binder_version)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ if (put_user(BINDER_CURRENT_PROTOCOL_VERSION, &((struct binder_version *)ubuf)->protocol_version)) {
+ ret = -EINVAL;
+ goto err;
+ }
+ break;
+ default:
+ ret = -EINVAL;
+ goto err;
+ }
+ ret = 0;
+err:
+ if (thread)
+ thread->looper &= ~BINDER_LOOPER_STATE_NEED_RETURN;
+ mutex_unlock(&binder_lock);
+ wait_event_interruptible(binder_user_error_wait, binder_stop_on_user_error < 2);
+ if (ret && ret != -ERESTARTSYS)
+ printk(KERN_INFO "binder: %d:%d ioctl %x %lx returned %d\n", proc->pid, current->pid, cmd, arg, ret);
+ return ret;
+}
+
+static void binder_vma_open(struct vm_area_struct *vma)
+{
+ struct binder_proc *proc = vma->vm_private_data;
+ if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
+ printk(KERN_INFO "binder: %d open vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
+ dump_stack();
+}
+static void binder_vma_close(struct vm_area_struct *vma)
+{
+ struct binder_proc *proc = vma->vm_private_data;
+ if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
+ printk(KERN_INFO "binder: %d close vm area %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
+ proc->vma = NULL;
+}
+
+static struct vm_operations_struct binder_vm_ops = {
+ .open = binder_vma_open,
+ .close = binder_vma_close,
+};
+
+static int binder_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ int ret;
+ struct vm_struct *area;
+ struct binder_proc *proc = filp->private_data;
+ const char *failure_string;
+ struct binder_buffer *buffer;
+
+ if ((vma->vm_end - vma->vm_start) > SZ_4M)
+ vma->vm_end = vma->vm_start + SZ_4M;
+
+ if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
+ printk(KERN_INFO "binder_mmap: %d %lx-%lx (%ld K) vma %lx pagep %lx\n", proc->pid, vma->vm_start, vma->vm_end, (vma->vm_end - vma->vm_start) / SZ_1K, vma->vm_flags, vma->vm_page_prot);
+
+ if (vma->vm_flags & FORBIDDEN_MMAP_FLAGS) {
+ ret = -EPERM;
+ failure_string = "bad vm_flags";
+ goto err_bad_arg;
+ }
+ vma->vm_flags = (vma->vm_flags | VM_DONTCOPY) & ~VM_MAYWRITE;
+
+ area = get_vm_area(vma->vm_end - vma->vm_start, VM_IOREMAP);
+ if (area == NULL) {
+ ret = -ENOMEM;
+ failure_string = "get_vm_area";
+ goto err_get_vm_area_failed;
+ }
+ proc->buffer = area->addr;
+ proc->user_buffer_offset = vma->vm_start - (size_t)proc->buffer;
+
+#if defined(CONFIG_CPU_CACHE_VIPT) && !defined(CONFIG_CPU_S3C6410)
+ if (cache_is_vipt_aliasing()) {
+ while (CACHE_COLOUR((vma->vm_start ^ (uint32_t)proc->buffer))) {
+ printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p bad alignment\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer);
+ vma->vm_start += PAGE_SIZE;
+ }
+ }
+#endif
+ proc->pages = kzalloc(sizeof(proc->pages[0]) * ((vma->vm_end - vma->vm_start) / PAGE_SIZE), GFP_KERNEL);
+ if (proc->pages == NULL) {
+ ret = -ENOMEM;
+ failure_string = "alloc page array";
+ goto err_alloc_pages_failed;
+ }
+ proc->buffer_size = vma->vm_end - vma->vm_start;
+
+ vma->vm_ops = &binder_vm_ops;
+ vma->vm_private_data = proc;
+
+ if (binder_update_page_range(proc, 1, proc->buffer, proc->buffer + PAGE_SIZE, vma)) {
+ ret = -ENOMEM;
+ failure_string = "alloc small buf";
+ goto err_alloc_small_buf_failed;
+ }
+ buffer = proc->buffer;
+ INIT_LIST_HEAD(&proc->buffers);
+ list_add(&buffer->entry, &proc->buffers);
+ buffer->free = 1;
+ binder_insert_free_buffer(proc, buffer);
+ proc->free_async_space = proc->buffer_size / 2;
+ barrier();
+ proc->vma = vma;
+
+ /*printk(KERN_INFO "binder_mmap: %d %lx-%lx maps %p\n", proc->pid, vma->vm_start, vma->vm_end, proc->buffer);*/
+ return 0;
+
+err_alloc_small_buf_failed:
+ kfree(proc->pages);
+err_alloc_pages_failed:
+ vfree(proc->buffer);
+err_get_vm_area_failed:
+ mutex_unlock(&binder_lock);
+err_bad_arg:
+ printk(KERN_ERR "binder_mmap: %d %lx-%lx %s failed %d\n", proc->pid, vma->vm_start, vma->vm_end, failure_string, ret);
+ return ret;
+}
+
+static int binder_open(struct inode *nodp, struct file *filp)
+{
+ struct binder_proc *proc;
+
+ if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
+ printk(KERN_INFO "binder_open: %d:%d\n", current->group_leader->pid, current->pid);
+
+ proc = kzalloc(sizeof(*proc), GFP_KERNEL);
+ if (proc == NULL)
+ return -ENOMEM;
+ get_task_struct(current);
+ proc->tsk = current;
+ INIT_LIST_HEAD(&proc->todo);
+ init_waitqueue_head(&proc->wait);
+ proc->default_priority = task_nice(current);
+ mutex_lock(&binder_lock);
+ binder_stats.obj_created[BINDER_STAT_PROC]++;
+ hlist_add_head(&proc->proc_node, &binder_procs);
+ proc->pid = current->group_leader->pid;
+ INIT_LIST_HEAD(&proc->delivered_death);
+ filp->private_data = proc;
+ mutex_unlock(&binder_lock);
+
+ if (binder_proc_dir_entry_proc) {
+ char strbuf[11];
+ snprintf(strbuf, sizeof(strbuf), "%u", proc->pid);
+ create_proc_read_entry(strbuf, S_IRUGO, binder_proc_dir_entry_proc, binder_read_proc_proc, proc);
+ }
+
+ return 0;
+}
+
+static int binder_flush(struct file *filp, fl_owner_t id)
+{
+ struct rb_node *n;
+ struct binder_proc *proc = filp->private_data;
+ int wake_count = 0;
+
+ mutex_lock(&binder_lock);
+ for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n)) {
+ struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node);
+ thread->looper |= BINDER_LOOPER_STATE_NEED_RETURN;
+ if (thread->looper & BINDER_LOOPER_STATE_WAITING) {
+ wake_up_interruptible(&thread->wait);
+ wake_count++;
+ }
+ }
+ wake_up_interruptible_all(&proc->wait);
+ mutex_unlock(&binder_lock);
+
+ if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
+ printk(KERN_INFO "binder_flush: %d woke %d threads\n", proc->pid, wake_count);
+
+ return 0;
+}
+
+static int binder_release(struct inode *nodp, struct file *filp)
+{
+ struct hlist_node *pos;
+ struct binder_transaction *t;
+ struct rb_node *n;
+ struct binder_proc *proc = filp->private_data;
+ int threads, nodes, incoming_refs, outgoing_refs, buffers, active_transactions, page_count;
+
+ if (binder_proc_dir_entry_proc) {
+ char strbuf[11];
+ snprintf(strbuf, sizeof(strbuf), "%u", proc->pid);
+ remove_proc_entry(strbuf, binder_proc_dir_entry_proc);
+ }
+ mutex_lock(&binder_lock);
+ hlist_del(&proc->proc_node);
+ if (binder_context_mgr_node && binder_context_mgr_node->proc == proc) {
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
+ printk(KERN_INFO "binder_release: %d context_mgr_node gone\n", proc->pid);
+ binder_context_mgr_node = NULL;
+ }
+
+ threads = 0;
+ active_transactions = 0;
+ while ((n = rb_first(&proc->threads))) {
+ struct binder_thread *thread = rb_entry(n, struct binder_thread, rb_node);
+ threads++;
+ active_transactions += binder_free_thread(proc, thread);
+ }
+ nodes = 0;
+ incoming_refs = 0;
+ while ((n = rb_first(&proc->nodes))) {
+ struct binder_node *node = rb_entry(n, struct binder_node, rb_node);
+
+ nodes++;
+ rb_erase(&node->rb_node, &proc->nodes);
+ list_del_init(&node->work.entry);
+ if (hlist_empty(&node->refs)) {
+ kfree(node);
+ binder_stats.obj_deleted[BINDER_STAT_NODE]++;
+ } else {
+ struct binder_ref *ref;
+ int death = 0;
+
+ node->proc = NULL;
+ node->local_strong_refs = 0;
+ node->local_weak_refs = 0;
+ hlist_add_head(&node->dead_node, &binder_dead_nodes);
+
+ hlist_for_each_entry(ref, pos, &node->refs, node_entry) {
+ incoming_refs++;
+ if (ref->death) {
+ death++;
+ if (list_empty(&ref->death->work.entry)) {
+ ref->death->work.type = BINDER_WORK_DEAD_BINDER;
+ list_add_tail(&ref->death->work.entry, &ref->proc->todo);
+ wake_up_interruptible(&ref->proc->wait);
+ } else
+ BUG();
+ }
+ }
+ if (binder_debug_mask & BINDER_DEBUG_DEAD_BINDER)
+ printk(KERN_INFO "binder: node %d now dead, refs %d, death %d\n", node->debug_id, incoming_refs, death);
+ }
+ }
+ outgoing_refs = 0;
+ while ((n = rb_first(&proc->refs_by_desc))) {
+ struct binder_ref *ref = rb_entry(n, struct binder_ref, rb_node_desc);
+ outgoing_refs++;
+ binder_delete_ref(ref);
+ }
+ binder_release_work(&proc->todo);
+ buffers = 0;
+
+ while ((n = rb_first(&proc->allocated_buffers))) {
+ struct binder_buffer *buffer = rb_entry(n, struct binder_buffer, rb_node);
+ t = buffer->transaction;
+ if (t) {
+ t->buffer = NULL;
+ buffer->transaction = NULL;
+ printk(KERN_ERR "binder: release proc %d, transaction %d, not freed\n", proc->pid, t->debug_id);
+ /*BUG();*/
+ }
+ binder_free_buf(proc, buffer);
+ buffers++;
+ }
+
+ binder_stats.obj_deleted[BINDER_STAT_PROC]++;
+ mutex_unlock(&binder_lock);
+
+ page_count = 0;
+ if (proc->pages) {
+ int i;
+ for (i = 0; i < proc->buffer_size / PAGE_SIZE; i++) {
+ if (proc->pages[i]) {
+ if (binder_debug_mask & BINDER_DEBUG_BUFFER_ALLOC)
+ printk(KERN_INFO "binder_release: %d: page %d at %p not freed\n", proc->pid, i, proc->buffer + i * PAGE_SIZE);
+ __free_page(proc->pages[i]);
+ page_count++;
+ }
+ }
+ kfree(proc->pages);
+ vfree(proc->buffer);
+ }
+
+ put_task_struct(proc->tsk);
+
+ if (binder_debug_mask & BINDER_DEBUG_OPEN_CLOSE)
+ printk(KERN_INFO "binder_release: %d threads %d, nodes %d (ref %d), refs %d, active transactions %d, buffers %d, pages %d\n",
+ proc->pid, threads, nodes, incoming_refs, outgoing_refs, active_transactions, buffers, page_count);
+
+ kfree(proc);
+ return 0;
+}
+
+static char *print_binder_transaction(char *buf, char *end, const char *prefix, struct binder_transaction *t)
+{
+ buf += snprintf(buf, end - buf, "%s %d: %p from %d:%d to %d:%d code %x flags %x pri %ld r%d",
+ prefix, t->debug_id, t, t->from ? t->from->proc->pid : 0,
+ t->from ? t->from->pid : 0,
+ t->to_proc ? t->to_proc->pid : 0,
+ t->to_thread ? t->to_thread->pid : 0,
+ t->code, t->flags, t->priority, t->need_reply);
+ if (buf >= end)
+ return buf;
+ if (t->buffer == NULL) {
+ buf += snprintf(buf, end - buf, " buffer free\n");
+ return buf;
+ }
+ if (t->buffer->target_node) {
+ buf += snprintf(buf, end - buf, " node %d",
+ t->buffer->target_node->debug_id);
+ if (buf >= end)
+ return buf;
+ }
+ buf += snprintf(buf, end - buf, " size %d:%d data %p\n",
+ t->buffer->data_size, t->buffer->offsets_size,
+ t->buffer->data);
+ return buf;
+}
+
+static char *print_binder_buffer(char *buf, char *end, const char *prefix, struct binder_buffer *buffer)
+{
+ buf += snprintf(buf, end - buf, "%s %d: %p size %d:%d %s\n",
+ prefix, buffer->debug_id, buffer->data,
+ buffer->data_size, buffer->offsets_size,
+ buffer->transaction ? "active" : "delivered");
+ return buf;
+}
+
+static char *print_binder_work(char *buf, char *end, const char *prefix,
+ const char *transaction_prefix, struct binder_work *w)
+{
+ struct binder_node *node;
+ struct binder_transaction *t;
+
+ switch (w->type) {
+ case BINDER_WORK_TRANSACTION:
+ t = container_of(w, struct binder_transaction, work);
+ buf = print_binder_transaction(buf, end, transaction_prefix, t);
+ break;
+ case BINDER_WORK_TRANSACTION_COMPLETE:
+ buf += snprintf(buf, end - buf,
+ "%stransaction complete\n", prefix);
+ break;
+ case BINDER_WORK_NODE:
+ node = container_of(w, struct binder_node, work);
+ buf += snprintf(buf, end - buf, "%snode work %d: u%p c%p\n",
+ prefix, node->debug_id, node->ptr, node->cookie);
+ break;
+ case BINDER_WORK_DEAD_BINDER:
+ buf += snprintf(buf, end - buf, "%shas dead binder\n", prefix);
+ break;
+ case BINDER_WORK_DEAD_BINDER_AND_CLEAR:
+ buf += snprintf(buf, end - buf,
+ "%shas cleared dead binder\n", prefix);
+ break;
+ case BINDER_WORK_CLEAR_DEATH_NOTIFICATION:
+ buf += snprintf(buf, end - buf,
+ "%shas cleared death notification\n", prefix);
+ break;
+ default:
+ buf += snprintf(buf, end - buf, "%sunknown work: type %d\n",
+ prefix, w->type);
+ break;
+ }
+ return buf;
+}
+
+static char *print_binder_thread(char *buf, char *end, struct binder_thread *thread, int print_always)
+{
+ struct binder_transaction *t;
+ struct binder_work *w;
+ char *start_buf = buf;
+ char *header_buf;
+
+ buf += snprintf(buf, end - buf, " thread %d: l %02x\n", thread->pid, thread->looper);
+ header_buf = buf;
+ t = thread->transaction_stack;
+ while (t) {
+ if (buf >= end)
+ break;
+ if (t->from == thread) {
+ buf = print_binder_transaction(buf, end, " outgoing transaction", t);
+ t = t->from_parent;
+ } else if (t->to_thread == thread) {
+ buf = print_binder_transaction(buf, end, " incoming transaction", t);
+ t = t->to_parent;
+ } else {
+ buf = print_binder_transaction(buf, end, " bad transaction", t);
+ t = NULL;
+ }
+ }
+ list_for_each_entry(w, &thread->todo, entry) {
+ if (buf >= end)
+ break;
+ buf = print_binder_work(buf, end, " ",
+ " pending transaction", w);
+ }
+ if (!print_always && buf == header_buf)
+ buf = start_buf;
+ return buf;
+}
+
+static char *print_binder_node(char *buf, char *end, struct binder_node *node)
+{
+ struct binder_ref *ref;
+ struct hlist_node *pos;
+ struct binder_work *w;
+ int count;
+ count = 0;
+ hlist_for_each_entry(ref, pos, &node->refs, node_entry)
+ count++;
+
+ buf += snprintf(buf, end - buf, " node %d: u%p c%p hs %d hw %d ls %d lw %d is %d iw %d",
+ node->debug_id, node->ptr, node->cookie,
+ node->has_strong_ref, node->has_weak_ref,
+ node->local_strong_refs, node->local_weak_refs,
+ node->internal_strong_refs, count);
+ if (buf >= end)
+ return buf;
+ if (count) {
+ buf += snprintf(buf, end - buf, " proc");
+ if (buf >= end)
+ return buf;
+ hlist_for_each_entry(ref, pos, &node->refs, node_entry) {
+ buf += snprintf(buf, end - buf, " %d", ref->proc->pid);
+ if (buf >= end)
+ return buf;
+ }
+ }
+ buf += snprintf(buf, end - buf, "\n");
+ list_for_each_entry(w, &node->async_todo, entry) {
+ if (buf >= end)
+ break;
+ buf = print_binder_work(buf, end, " ",
+ " pending async transaction", w);
+ }
+ return buf;
+}
+
+static char *print_binder_ref(char *buf, char *end, struct binder_ref *ref)
+{
+ buf += snprintf(buf, end - buf, " ref %d: desc %d %snode %d s %d w %d d %p\n",
+ ref->debug_id, ref->desc, ref->node->proc ? "" : "dead ",
+ ref->node->debug_id, ref->strong, ref->weak, ref->death);
+ return buf;
+}
+
+static char *print_binder_proc(char *buf, char *end, struct binder_proc *proc, int print_all)
+{
+ struct binder_work *w;
+ struct rb_node *n;
+ char *start_buf = buf;
+ char *header_buf;
+
+ buf += snprintf(buf, end - buf, "proc %d\n", proc->pid);
+ header_buf = buf;
+
+ for (n = rb_first(&proc->threads); n != NULL && buf < end; n = rb_next(n))
+ buf = print_binder_thread(buf, end, rb_entry(n, struct binder_thread, rb_node), print_all);
+ for (n = rb_first(&proc->nodes); n != NULL && buf < end; n = rb_next(n)) {
+ struct binder_node *node = rb_entry(n, struct binder_node, rb_node);
+ if (print_all || node->has_async_transaction)
+ buf = print_binder_node(buf, end, node);
+ }
+ if (print_all) {
+ for (n = rb_first(&proc->refs_by_desc); n != NULL && buf < end; n = rb_next(n))
+ buf = print_binder_ref(buf, end, rb_entry(n, struct binder_ref, rb_node_desc));
+ }
+ for (n = rb_first(&proc->allocated_buffers); n != NULL && buf < end; n = rb_next(n))
+ buf = print_binder_buffer(buf, end, " buffer", rb_entry(n, struct binder_buffer, rb_node));
+ list_for_each_entry(w, &proc->todo, entry) {
+ if (buf >= end)
+ break;
+ buf = print_binder_work(buf, end, " ",
+ " pending transaction", w);
+ }
+ list_for_each_entry(w, &proc->delivered_death, entry) {
+ if (buf >= end)
+ break;
+ buf += snprintf(buf, end - buf, " has delivered dead binder\n");
+ break;
+ }
+ if (!print_all && buf == header_buf)
+ buf = start_buf;
+ return buf;
+}
+
+static const char *binder_return_strings[] = {
+ "BR_ERROR",
+ "BR_OK",
+ "BR_TRANSACTION",
+ "BR_REPLY",
+ "BR_ACQUIRE_RESULT",
+ "BR_DEAD_REPLY",
+ "BR_TRANSACTION_COMPLETE",
+ "BR_INCREFS",
+ "BR_ACQUIRE",
+ "BR_RELEASE",
+ "BR_DECREFS",
+ "BR_ATTEMPT_ACQUIRE",
+ "BR_NOOP",
+ "BR_SPAWN_LOOPER",
+ "BR_FINISHED",
+ "BR_DEAD_BINDER",
+ "BR_CLEAR_DEATH_NOTIFICATION_DONE",
+ "BR_FAILED_REPLY"
+};
+
+static const char *binder_command_strings[] = {
+ "BC_TRANSACTION",
+ "BC_REPLY",
+ "BC_ACQUIRE_RESULT",
+ "BC_FREE_BUFFER",
+ "BC_INCREFS",
+ "BC_ACQUIRE",
+ "BC_RELEASE",
+ "BC_DECREFS",
+ "BC_INCREFS_DONE",
+ "BC_ACQUIRE_DONE",
+ "BC_ATTEMPT_ACQUIRE",
+ "BC_REGISTER_LOOPER",
+ "BC_ENTER_LOOPER",
+ "BC_EXIT_LOOPER",
+ "BC_REQUEST_DEATH_NOTIFICATION",
+ "BC_CLEAR_DEATH_NOTIFICATION",
+ "BC_DEAD_BINDER_DONE"
+};
+
+static const char *binder_objstat_strings[] = {
+ "proc",
+ "thread",
+ "node",
+ "ref",
+ "death",
+ "transaction",
+ "transaction_complete"
+};
+
+static char *print_binder_stats(char *buf, char *end, const char *prefix, struct binder_stats *stats)
+{
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(stats->bc) != ARRAY_SIZE(binder_command_strings));
+ for (i = 0; i < ARRAY_SIZE(stats->bc); i++) {
+ if (stats->bc[i])
+ buf += snprintf(buf, end - buf, "%s%s: %d\n", prefix,
+ binder_command_strings[i], stats->bc[i]);
+ if (buf >= end)
+ return buf;
+ }
+
+ BUILD_BUG_ON(ARRAY_SIZE(stats->br) != ARRAY_SIZE(binder_return_strings));
+ for (i = 0; i < ARRAY_SIZE(stats->br); i++) {
+ if (stats->br[i])
+ buf += snprintf(buf, end - buf, "%s%s: %d\n", prefix,
+ binder_return_strings[i], stats->br[i]);
+ if (buf >= end)
+ return buf;
+ }
+
+ BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != ARRAY_SIZE(binder_objstat_strings));
+ BUILD_BUG_ON(ARRAY_SIZE(stats->obj_created) != ARRAY_SIZE(stats->obj_deleted));
+ for (i = 0; i < ARRAY_SIZE(stats->obj_created); i++) {
+ if (stats->obj_created[i] || stats->obj_deleted[i])
+ buf += snprintf(buf, end - buf, "%s%s: active %d total %d\n", prefix,
+ binder_objstat_strings[i],
+ stats->obj_created[i] - stats->obj_deleted[i],
+ stats->obj_created[i]);
+ if (buf >= end)
+ return buf;
+ }
+ return buf;
+}
+
+static char *print_binder_proc_stats(char *buf, char *end, struct binder_proc *proc)
+{
+ struct binder_work *w;
+ struct rb_node *n;
+ int count, strong, weak;
+
+ buf += snprintf(buf, end - buf, "proc %d\n", proc->pid);
+ if (buf >= end)
+ return buf;
+ count = 0;
+ for (n = rb_first(&proc->threads); n != NULL; n = rb_next(n))
+ count++;
+ buf += snprintf(buf, end - buf, " threads: %d\n", count);
+ if (buf >= end)
+ return buf;
+ buf += snprintf(buf, end - buf, " requested threads: %d+%d/%d\n"
+ " ready threads %d\n"
+ " free async space %d\n", proc->requested_threads,
+ proc->requested_threads_started, proc->max_threads,
+ proc->ready_threads, proc->free_async_space);
+ if (buf >= end)
+ return buf;
+ count = 0;
+ for (n = rb_first(&proc->nodes); n != NULL; n = rb_next(n))
+ count++;
+ buf += snprintf(buf, end - buf, " nodes: %d\n", count);
+ if (buf >= end)
+ return buf;
+ count = 0;
+ strong = 0;
+ weak = 0;
+ for (n = rb_first(&proc->refs_by_desc); n != NULL; n = rb_next(n)) {
+ struct binder_ref *ref = rb_entry(n, struct binder_ref, rb_node_desc);
+ count++;
+ strong += ref->strong;
+ weak += ref->weak;
+ }
+ buf += snprintf(buf, end - buf, " refs: %d s %d w %d\n", count, strong, weak);
+ if (buf >= end)
+ return buf;
+
+ count = 0;
+ for (n = rb_first(&proc->allocated_buffers); n != NULL; n = rb_next(n))
+ count++;
+ buf += snprintf(buf, end - buf, " buffers: %d\n", count);
+ if (buf >= end)
+ return buf;
+
+ count = 0;
+ list_for_each_entry(w, &proc->todo, entry) {
+ switch (w->type) {
+ case BINDER_WORK_TRANSACTION:
+ count++;
+ break;
+ default:
+ break;
+ }
+ }
+ buf += snprintf(buf, end - buf, " pending transactions: %d\n", count);
+ if (buf >= end)
+ return buf;
+
+ buf = print_binder_stats(buf, end, " ", &proc->stats);
+
+ return buf;
+}
+
+
+static int binder_read_proc_state(
+ char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ struct binder_proc *proc;
+ struct hlist_node *pos;
+ struct binder_node *node;
+ int len = 0;
+ char *buf = page;
+ char *end = page + PAGE_SIZE;
+ int do_lock = !binder_debug_no_lock;
+
+ if (off)
+ return 0;
+
+ if (do_lock)
+ mutex_lock(&binder_lock);
+
+ buf += snprintf(buf, end - buf, "binder state:\n");
+
+ if (!hlist_empty(&binder_dead_nodes))
+ buf += snprintf(buf, end - buf, "dead nodes:\n");
+ hlist_for_each_entry(node, pos, &binder_dead_nodes, dead_node) {
+ if (buf >= end)
+ break;
+ buf = print_binder_node(buf, end, node);
+ }
+
+ hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
+ if (buf >= end)
+ break;
+ buf = print_binder_proc(buf, end, proc, 1);
+ }
+ if (do_lock)
+ mutex_unlock(&binder_lock);
+ if (buf > page + PAGE_SIZE)
+ buf = page + PAGE_SIZE;
+
+ *start = page + off;
+
+ len = buf - page;
+ if (len > off)
+ len -= off;
+ else
+ len = 0;
+
+ return len < count ? len : count;
+}
+
+static int binder_read_proc_stats(
+ char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ struct binder_proc *proc;
+ struct hlist_node *pos;
+ int len = 0;
+ char *p = page;
+ int do_lock = !binder_debug_no_lock;
+
+ if (off)
+ return 0;
+
+ if (do_lock)
+ mutex_lock(&binder_lock);
+
+ p += snprintf(p, PAGE_SIZE, "binder stats:\n");
+
+ p = print_binder_stats(p, page + PAGE_SIZE, "", &binder_stats);
+
+ hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
+ if (p >= page + PAGE_SIZE)
+ break;
+ p = print_binder_proc_stats(p, page + PAGE_SIZE, proc);
+ }
+ if (do_lock)
+ mutex_unlock(&binder_lock);
+ if (p > page + PAGE_SIZE)
+ p = page + PAGE_SIZE;
+
+ *start = page + off;
+
+ len = p - page;
+ if (len > off)
+ len -= off;
+ else
+ len = 0;
+
+ return len < count ? len : count;
+}
+
+static int binder_read_proc_transactions(
+ char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ struct binder_proc *proc;
+ struct hlist_node *pos;
+ int len = 0;
+ char *buf = page;
+ char *end = page + PAGE_SIZE;
+ int do_lock = !binder_debug_no_lock;
+
+ if (off)
+ return 0;
+
+ if (do_lock)
+ mutex_lock(&binder_lock);
+
+ buf += snprintf(buf, end - buf, "binder transactions:\n");
+ hlist_for_each_entry(proc, pos, &binder_procs, proc_node) {
+ if (buf >= end)
+ break;
+ buf = print_binder_proc(buf, end, proc, 0);
+ }
+ if (do_lock)
+ mutex_unlock(&binder_lock);
+ if (buf > page + PAGE_SIZE)
+ buf = page + PAGE_SIZE;
+
+ *start = page + off;
+
+ len = buf - page;
+ if (len > off)
+ len -= off;
+ else
+ len = 0;
+
+ return len < count ? len : count;
+}
+
+static int binder_read_proc_proc(
+ char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ struct binder_proc *proc = data;
+ int len = 0;
+ char *p = page;
+ int do_lock = !binder_debug_no_lock;
+
+ if (off)
+ return 0;
+
+ if (do_lock)
+ mutex_lock(&binder_lock);
+ p += snprintf(p, PAGE_SIZE, "binder proc state:\n");
+ p = print_binder_proc(p, page + PAGE_SIZE, proc, 1);
+ if (do_lock)
+ mutex_unlock(&binder_lock);
+
+ if (p > page + PAGE_SIZE)
+ p = page + PAGE_SIZE;
+ *start = page + off;
+
+ len = p - page;
+ if (len > off)
+ len -= off;
+ else
+ len = 0;
+
+ return len < count ? len : count;
+}
+
+static char *print_binder_transaction_log_entry(char *buf, char *end, struct binder_transaction_log_entry *e)
+{
+ buf += snprintf(buf, end - buf, "%d: %s from %d:%d to %d:%d node %d handle %d size %d:%d\n",
+ e->debug_id, (e->call_type == 2) ? "reply" :
+ ((e->call_type == 1) ? "async" : "call "), e->from_proc,
+ e->from_thread, e->to_proc, e->to_thread, e->to_node,
+ e->target_handle, e->data_size, e->offsets_size);
+ return buf;
+}
+
+static int binder_read_proc_transaction_log(
+ char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ struct binder_transaction_log *log = data;
+ int len = 0;
+ int i;
+ char *buf = page;
+ char *end = page + PAGE_SIZE;
+
+ if (off)
+ return 0;
+
+ if (log->full) {
+ for (i = log->next; i < ARRAY_SIZE(log->entry); i++) {
+ if (buf >= end)
+ break;
+ buf = print_binder_transaction_log_entry(buf, end, &log->entry[i]);
+ }
+ }
+ for (i = 0; i < log->next; i++) {
+ if (buf >= end)
+ break;
+ buf = print_binder_transaction_log_entry(buf, end, &log->entry[i]);
+ }
+
+ *start = page + off;
+
+ len = buf - page;
+ if (len > off)
+ len -= off;
+ else
+ len = 0;
+
+ return len < count ? len : count;
+}
+
+static struct file_operations binder_fops = {
+ .owner = THIS_MODULE,
+ .poll = binder_poll,
+ .unlocked_ioctl = binder_ioctl,
+ .mmap = binder_mmap,
+ .open = binder_open,
+ .flush = binder_flush,
+ .release = binder_release,
+};
+
+static struct miscdevice binder_miscdev = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "binder",
+ .fops = &binder_fops
+};
+
+static int __init binder_init(void)
+{
+ int ret;
+
+ binder_proc_dir_entry_root = proc_mkdir("binder", NULL);
+ if (binder_proc_dir_entry_root)
+ binder_proc_dir_entry_proc = proc_mkdir("proc", binder_proc_dir_entry_root);
+ ret = misc_register(&binder_miscdev);
+ if (binder_proc_dir_entry_root) {
+ create_proc_read_entry("state", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_state, NULL);
+ create_proc_read_entry("stats", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_stats, NULL);
+ create_proc_read_entry("transactions", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transactions, NULL);
+ create_proc_read_entry("transaction_log", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transaction_log, &binder_transaction_log);
+ create_proc_read_entry("failed_transaction_log", S_IRUGO, binder_proc_dir_entry_root, binder_read_proc_transaction_log, &binder_transaction_log_failed);
+ }
+ return ret;
+}
+
+device_initcall(binder_init);
+
--- /dev/null
+++ b/drivers/android/Kconfig
@@ -0,0 +1,93 @@
+menu "Android"
+
+config ANDROID_BINDER_IPC
+ tristate "Binder IPC Driver"
+ default y
+
+config ANDROID_POWER
+ bool "Android power driver"
+ depends on PM && RTC_CLASS
+ default n
+
+config ANDROID_POWER_STAT
+ bool "Android power driver lock stats"
+ depends on ANDROID_POWER
+ default y
+
+config ANDROID_POWER_ALARM
+ bool "Android alarm driver"
+ depends on ANDROID_POWER
+ default y
+
+config ANDROID_LOGGER
+ bool "Android log driver"
+ default y
+
+config ANDROID_RAM_CONSOLE
+ bool "RAM buffer console"
+ default n
+
+config ANDROID_RAM_CONSOLE_ENABLE_VERBOSE
+ bool "Enable verbose console messages"
+ default y
+ depends on ANDROID_RAM_CONSOLE
+
+menuconfig ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ bool "Enable error correction"
+ default n
+ depends on ANDROID_RAM_CONSOLE
+ select REED_SOLOMON
+ select REED_SOLOMON_ENC8
+ select REED_SOLOMON_DEC8
+
+if ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+
+config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE
+ int "Data data size"
+ default 128
+ help
+ Must be a power of 2.
+
+config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE
+ int "ECC size"
+ default 16
+
+config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE
+ int "Symbol size"
+ default 8
+
+config ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL
+ hex "Polynomial"
+ default 0x19 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 4)
+ default 0x29 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 5)
+ default 0x61 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 6)
+ default 0x89 if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 7)
+ default 0x11d if (ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE = 8)
+
+endif #ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+
+config ANDROID_RAM_CONSOLE_EARLY_INIT
+ bool "Start ram console early"
+ default n
+ depends on ANDROID_RAM_CONSOLE
+
+config ANDROID_RAM_CONSOLE_EARLY_ADDR
+ hex "RAM console virtual address"
+ default 0
+ depends on ANDROID_RAM_CONSOLE_EARLY_INIT
+
+config ANDROID_RAM_CONSOLE_EARLY_SIZE
+ hex "RAM console buffer size"
+ default 0
+ depends on ANDROID_RAM_CONSOLE_EARLY_INIT
+
+config ANDROID_TIMED_GPIO
+ bool "Android timed gpio driver"
+ depends on GENERIC_GPIO
+ default y
+
+config ANDROID_PARANOID_NETWORK
+ bool "Only allow certain groups to create sockets"
+ default y
+
+endmenu
--- /dev/null
+++ b/drivers/android/logger.c
@@ -0,0 +1,607 @@
+/*
+ * drivers/android/logger.c
+ *
+ * Android Logging Subsystem
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * Robert Love <rlove@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+#include <linux/poll.h>
+#include <linux/time.h>
+#include <linux/logger.h>
+
+#include <asm/ioctls.h>
+
+/*
+ * struct logger_log - represents a specific log, such as 'main' or 'radio'
+ *
+ * This structure lives from module insertion until module removal, so it does
+ * not need additional reference counting. The structure is protected by the
+ * mutex 'mutex'.
+ */
+struct logger_log {
+ unsigned char * buffer; /* the ring buffer itself */
+ struct miscdevice misc; /* misc device representing the log */
+ wait_queue_head_t wq; /* wait queue for readers */
+ struct list_head readers; /* this log's readers */
+ struct mutex mutex; /* mutex protecting buffer */
+ size_t w_off; /* current write head offset */
+ size_t head; /* new readers start here */
+ size_t size; /* size of the log */
+};
+
+/*
+ * struct logger_reader - a logging device open for reading
+ *
+ * This object lives from open to release, so we don't need additional
+ * reference counting. The structure is protected by log->mutex.
+ */
+struct logger_reader {
+ struct logger_log * log; /* associated log */
+ struct list_head list; /* entry in logger_log's list */
+ size_t r_off; /* current read head offset */
+};
+
+/* logger_offset - returns index 'n' into the log via (optimized) modulus */
+#define logger_offset(n) ((n) & (log->size - 1))
+
+/*
+ * file_get_log - Given a file structure, return the associated log
+ *
+ * This isn't aesthetic. We have several goals:
+ *
+ * 1) Need to quickly obtain the associated log during an I/O operation
+ * 2) Readers need to maintain state (logger_reader)
+ * 3) Writers need to be very fast (open() should be a near no-op)
+ *
+ * In the reader case, we can trivially go file->logger_reader->logger_log.
+ * For a writer, we don't want to maintain a logger_reader, so we just go
+ * file->logger_log. Thus what file->private_data points at depends on whether
+ * or not the file was opened for reading. This function hides that dirtiness.
+ */
+static inline struct logger_log * file_get_log(struct file *file)
+{
+ if (file->f_mode & FMODE_READ) {
+ struct logger_reader *reader = file->private_data;
+ return reader->log;
+ } else
+ return file->private_data;
+}
+
+/*
+ * get_entry_len - Grabs the length of the payload of the next entry starting
+ * from 'off'.
+ *
+ * Caller needs to hold log->mutex.
+ */
+static __u32 get_entry_len(struct logger_log *log, size_t off)
+{
+ __u16 val;
+
+ switch (log->size - off) {
+ case 1:
+ memcpy(&val, log->buffer + off, 1);
+ memcpy(((char *) &val) + 1, log->buffer, 1);
+ break;
+ default:
+ memcpy(&val, log->buffer + off, 2);
+ }
+
+ return sizeof(struct logger_entry) + val;
+}
+
+/*
+ * do_read_log_to_user - reads exactly 'count' bytes from 'log' into the
+ * user-space buffer 'buf'. Returns 'count' on success.
+ *
+ * Caller must hold log->mutex.
+ */
+static ssize_t do_read_log_to_user(struct logger_log *log,
+ struct logger_reader *reader,
+ char __user *buf,
+ size_t count)
+{
+ size_t len;
+
+ /*
+ * We read from the log in two disjoint operations. First, we read from
+ * the current read head offset up to 'count' bytes or to the end of
+ * the log, whichever comes first.
+ */
+ len = min(count, log->size - reader->r_off);
+ if (copy_to_user(buf, log->buffer + reader->r_off, len))
+ return -EFAULT;
+
+ /*
+ * Second, we read any remaining bytes, starting back at the head of
+ * the log.
+ */
+ if (count != len)
+ if (copy_to_user(buf + len, log->buffer, count - len))
+ return -EFAULT;
+
+ reader->r_off = logger_offset(reader->r_off + count);
+
+ return count;
+}
+
+/*
+ * logger_read - our log's read() method
+ *
+ * Behavior:
+ *
+ * - O_NONBLOCK works
+ * - If there are no log entries to read, blocks until log is written to
+ * - Atomically reads exactly one log entry
+ *
+ * Optimal read size is LOGGER_ENTRY_MAX_LEN. Will set errno to EINVAL if read
+ * buffer is insufficient to hold next entry.
+ */
+static ssize_t logger_read(struct file *file, char __user *buf,
+ size_t count, loff_t *pos)
+{
+ struct logger_reader *reader = file->private_data;
+ struct logger_log *log = reader->log;
+ ssize_t ret;
+ DEFINE_WAIT(wait);
+
+start:
+ while (1) {
+ prepare_to_wait(&log->wq, &wait, TASK_INTERRUPTIBLE);
+
+ mutex_lock(&log->mutex);
+ ret = (log->w_off == reader->r_off);
+ mutex_unlock(&log->mutex);
+ if (!ret)
+ break;
+
+ if (file->f_flags & O_NONBLOCK) {
+ ret = -EAGAIN;
+ break;
+ }
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ break;
+ }
+
+ schedule();
+ }
+
+ finish_wait(&log->wq, &wait);
+ if (ret)
+ return ret;
+
+ mutex_lock(&log->mutex);
+
+ /* is there still something to read or did we race? */
+ if (unlikely(log->w_off == reader->r_off)) {
+ mutex_unlock(&log->mutex);
+ goto start;
+ }
+
+ /* get the size of the next entry */
+ ret = get_entry_len(log, reader->r_off);
+ if (count < ret) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* get exactly one entry from the log */
+ ret = do_read_log_to_user(log, reader, buf, ret);
+
+out:
+ mutex_unlock(&log->mutex);
+
+ return ret;
+}
+
+/*
+ * get_next_entry - return the offset of the first valid entry at least 'len'
+ * bytes after 'off'.
+ *
+ * Caller must hold log->mutex.
+ */
+static size_t get_next_entry(struct logger_log *log, size_t off, size_t len)
+{
+ size_t count = 0;
+
+ do {
+ size_t nr = get_entry_len(log, off);
+ off = logger_offset(off + nr);
+ count += nr;
+ } while (count < len);
+
+ return off;
+}
+
+/*
+ * clock_interval - is a < c < b in mod-space? Put another way, does the line
+ * from a to b cross c?
+ */
+static inline int clock_interval(size_t a, size_t b, size_t c)
+{
+ if (b < a) {
+ if (a < c || b >= c)
+ return 1;
+ } else {
+ if (a < c && b >= c)
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * fix_up_readers - walk the list of all readers and "fix up" any who were
+ * lapped by the writer; also do the same for the default "start head".
+ * We do this by "pulling forward" the readers and start head to the first
+ * entry after the new write head.
+ *
+ * The caller needs to hold log->mutex.
+ */
+static void fix_up_readers(struct logger_log *log, size_t len)
+{
+ size_t old = log->w_off;
+ size_t new = logger_offset(old + len);
+ struct logger_reader *reader;
+
+ if (clock_interval(old, new, log->head))
+ log->head = get_next_entry(log, log->head, len);
+
+ list_for_each_entry(reader, &log->readers, list)
+ if (clock_interval(old, new, reader->r_off))
+ reader->r_off = get_next_entry(log, reader->r_off, len);
+}
+
+/*
+ * do_write_log - writes 'len' bytes from 'buf' to 'log'
+ *
+ * The caller needs to hold log->mutex.
+ */
+static void do_write_log(struct logger_log *log, const void *buf, size_t count)
+{
+ size_t len;
+
+ len = min(count, log->size - log->w_off);
+ memcpy(log->buffer + log->w_off, buf, len);
+
+ if (count != len)
+ memcpy(log->buffer, buf + len, count - len);
+
+ log->w_off = logger_offset(log->w_off + count);
+
+}
+
+/*
+ * do_write_log_user - writes 'len' bytes from the user-space buffer 'buf' to
+ * the log 'log'
+ *
+ * The caller needs to hold log->mutex.
+ *
+ * Returns 'count' on success, negative error code on failure.
+ */
+static ssize_t do_write_log_from_user(struct logger_log *log,
+ const void __user *buf, size_t count)
+{
+ size_t len;
+
+ len = min(count, log->size - log->w_off);
+ if (len && copy_from_user(log->buffer + log->w_off, buf, len))
+ return -EFAULT;
+
+ if (count != len)
+ if (copy_from_user(log->buffer, buf + len, count - len))
+ return -EFAULT;
+
+ log->w_off = logger_offset(log->w_off + count);
+
+ return count;
+}
+
+/*
+ * logger_aio_write - our write method, implementing support for write(),
+ * writev(), and aio_write(). Writes are our fast path, and we try to optimize
+ * them above all else.
+ */
+ssize_t logger_aio_write(struct kiocb *iocb, const struct iovec *iov,
+ unsigned long nr_segs, loff_t ppos)
+{
+ struct logger_log *log = file_get_log(iocb->ki_filp);
+ size_t orig = log->w_off;
+ struct logger_entry header;
+ struct timespec now;
+ ssize_t ret = 0;
+
+ now = current_kernel_time();
+
+ header.pid = current->tgid;
+ header.tid = current->pid;
+ header.sec = now.tv_sec;
+ header.nsec = now.tv_nsec;
+ header.len = min_t(size_t, iocb->ki_left, LOGGER_ENTRY_MAX_PAYLOAD);
+
+ /* null writes succeed, return zero */
+ if (unlikely(!header.len))
+ return 0;
+
+ mutex_lock(&log->mutex);
+
+ /*
+ * Fix up any readers, pulling them forward to the first readable
+ * entry after (what will be) the new write offset. We do this now
+ * because if we partially fail, we can end up with clobbered log
+ * entries that encroach on readable buffer.
+ */
+ fix_up_readers(log, sizeof(struct logger_entry) + header.len);
+
+ do_write_log(log, &header, sizeof(struct logger_entry));
+
+ while (nr_segs-- > 0) {
+ size_t len;
+ ssize_t nr;
+
+ /* figure out how much of this vector we can keep */
+ len = min_t(size_t, iov->iov_len, header.len - ret);
+
+ /* write out this segment's payload */
+ nr = do_write_log_from_user(log, iov->iov_base, len);
+ if (unlikely(nr < 0)) {
+ log->w_off = orig;
+ mutex_unlock(&log->mutex);
+ return nr;
+ }
+
+ iov++;
+ ret += nr;
+ }
+
+ mutex_unlock(&log->mutex);
+
+ /* wake up any blocked readers */
+ wake_up_interruptible(&log->wq);
+
+ return ret;
+}
+
+static struct logger_log * get_log_from_minor(int);
+
+/*
+ * logger_open - the log's open() file operation
+ *
+ * Note how near a no-op this is in the write-only case. Keep it that way!
+ */
+static int logger_open(struct inode *inode, struct file *file)
+{
+ struct logger_log *log;
+ int ret;
+
+ ret = nonseekable_open(inode, file);
+ if (ret)
+ return ret;
+
+ log = get_log_from_minor(MINOR(inode->i_rdev));
+ if (!log)
+ return -ENODEV;
+
+ if (file->f_mode & FMODE_READ) {
+ struct logger_reader *reader;
+
+ reader = kmalloc(sizeof(struct logger_reader), GFP_KERNEL);
+ if (!reader)
+ return -ENOMEM;
+
+ reader->log = log;
+ INIT_LIST_HEAD(&reader->list);
+
+ mutex_lock(&log->mutex);
+ reader->r_off = log->head;
+ list_add_tail(&reader->list, &log->readers);
+ mutex_unlock(&log->mutex);
+
+ file->private_data = reader;
+ } else
+ file->private_data = log;
+
+ return 0;
+}
+
+/*
+ * logger_release - the log's release file operation
+ *
+ * Note this is a total no-op in the write-only case. Keep it that way!
+ */
+static int logger_release(struct inode *ignored, struct file *file)
+{
+ if (file->f_mode & FMODE_READ) {
+ struct logger_reader *reader = file->private_data;
+ list_del(&reader->list);
+ kfree(reader);
+ }
+
+ return 0;
+}
+
+/*
+ * logger_poll - the log's poll file operation, for poll/select/epoll
+ *
+ * Note we always return POLLOUT, because you can always write() to the log.
+ * Note also that, strictly speaking, a return value of POLLIN does not
+ * guarantee that the log is readable without blocking, as there is a small
+ * chance that the writer can lap the reader in the interim between poll()
+ * returning and the read() request.
+ */
+static unsigned int logger_poll(struct file *file, poll_table *wait)
+{
+ struct logger_reader *reader;
+ struct logger_log *log;
+ unsigned int ret = POLLOUT | POLLWRNORM;
+
+ if (!(file->f_mode & FMODE_READ))
+ return ret;
+
+ reader = file->private_data;
+ log = reader->log;
+
+ poll_wait(file, &log->wq, wait);
+
+ mutex_lock(&log->mutex);
+ if (log->w_off != reader->r_off)
+ ret |= POLLIN | POLLRDNORM;
+ mutex_unlock(&log->mutex);
+
+ return ret;
+}
+
+static long logger_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct logger_log *log = file_get_log(file);
+ struct logger_reader *reader;
+ long ret = -ENOTTY;
+
+ mutex_lock(&log->mutex);
+
+ switch (cmd) {
+ case LOGGER_GET_LOG_BUF_SIZE:
+ ret = log->size;
+ break;
+ case LOGGER_GET_LOG_LEN:
+ if (!(file->f_mode & FMODE_READ)) {
+ ret = -EBADF;
+ break;
+ }
+ reader = file->private_data;
+ if (log->w_off >= reader->r_off)
+ ret = log->w_off - reader->r_off;
+ else
+ ret = (log->size - reader->r_off) + log->w_off;
+ break;
+ case LOGGER_GET_NEXT_ENTRY_LEN:
+ if (!(file->f_mode & FMODE_READ)) {
+ ret = -EBADF;
+ break;
+ }
+ reader = file->private_data;
+ if (log->w_off != reader->r_off)
+ ret = get_entry_len(log, reader->r_off);
+ else
+ ret = 0;
+ break;
+ case LOGGER_FLUSH_LOG:
+ if (!(file->f_mode & FMODE_WRITE)) {
+ ret = -EBADF;
+ break;
+ }
+ list_for_each_entry(reader, &log->readers, list)
+ reader->r_off = log->w_off;
+ log->head = log->w_off;
+ ret = 0;
+ break;
+ }
+
+ mutex_unlock(&log->mutex);
+
+ return ret;
+}
+
+static struct file_operations logger_fops = {
+ .owner = THIS_MODULE,
+ .read = logger_read,
+ .aio_write = logger_aio_write,
+ .poll = logger_poll,
+ .unlocked_ioctl = logger_ioctl,
+ .compat_ioctl = logger_ioctl,
+ .open = logger_open,
+ .release = logger_release,
+};
+
+/*
+ * Defines a log structure with name 'NAME' and a size of 'SIZE' bytes, which
+ * must be a power of two, greater than LOGGER_ENTRY_MAX_LEN, and less than
+ * LONG_MAX minus LOGGER_ENTRY_MAX_LEN.
+ */
+#define DEFINE_LOGGER_DEVICE(VAR, NAME, SIZE) \
+static unsigned char _buf_ ## VAR[SIZE]; \
+static struct logger_log VAR = { \
+ .buffer = _buf_ ## VAR, \
+ .misc = { \
+ .minor = MISC_DYNAMIC_MINOR, \
+ .name = NAME, \
+ .fops = &logger_fops, \
+ .parent = NULL, \
+ }, \
+ .wq = __WAIT_QUEUE_HEAD_INITIALIZER(VAR .wq), \
+ .readers = LIST_HEAD_INIT(VAR .readers), \
+ .mutex = __MUTEX_INITIALIZER(VAR .mutex), \
+ .w_off = 0, \
+ .head = 0, \
+ .size = SIZE, \
+};
+
+DEFINE_LOGGER_DEVICE(log_main, LOGGER_LOG_MAIN, 64*1024)
+DEFINE_LOGGER_DEVICE(log_events, LOGGER_LOG_EVENTS, 256*1024)
+DEFINE_LOGGER_DEVICE(log_radio, LOGGER_LOG_RADIO, 64*1024)
+
+static struct logger_log * get_log_from_minor(int minor)
+{
+ if (log_main.misc.minor == minor)
+ return &log_main;
+ if (log_events.misc.minor == minor)
+ return &log_events;
+ if (log_radio.misc.minor == minor)
+ return &log_radio;
+ return NULL;
+}
+
+static int __init init_log(struct logger_log *log)
+{
+ int ret;
+
+ ret = misc_register(&log->misc);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "logger: failed to register misc "
+ "device for log '%s'!\n", log->misc.name);
+ return ret;
+ }
+
+ printk(KERN_INFO "logger: created %luK log '%s'\n",
+ (unsigned long) log->size >> 10, log->misc.name);
+
+ return 0;
+}
+
+static int __init logger_init(void)
+{
+ int ret;
+
+ ret = init_log(&log_main);
+ if (unlikely(ret))
+ goto out;
+
+ ret = init_log(&log_events);
+ if (unlikely(ret))
+ goto out;
+
+ ret = init_log(&log_radio);
+ if (unlikely(ret))
+ goto out;
+
+out:
+ return ret;
+}
+device_initcall(logger_init);
--- /dev/null
+++ b/drivers/android/Makefile
@@ -0,0 +1,6 @@
+obj-$(CONFIG_ANDROID_BINDER_IPC) += binder.o
+obj-$(CONFIG_ANDROID_POWER) += power.o
+obj-$(CONFIG_ANDROID_POWER_ALARM) += alarm.o
+obj-$(CONFIG_ANDROID_LOGGER) += logger.o
+obj-$(CONFIG_ANDROID_RAM_CONSOLE) += ram_console.o
+obj-$(CONFIG_ANDROID_TIMED_GPIO) += timed_gpio.o
--- /dev/null
+++ b/drivers/android/power.c
@@ -0,0 +1,1336 @@
+/* drivers/android/power.c
+ *
+ * Copyright (C) 2005-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
+//#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/fs.h>
+#include <linux/poll.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/rtc.h>
+#include <linux/wait.h>
+#include <linux/android_power.h>
+#include <linux/suspend.h>
+#include <linux/syscalls.h> // sys_sync
+#include <linux/console.h>
+#include <linux/kbd_kern.h>
+#include <linux/vt_kern.h>
+#include <linux/freezer.h>
+#ifdef CONFIG_ANDROID_POWER_STAT
+#include <linux/proc_fs.h>
+#endif
+
+enum {
+ ANDROID_POWER_DEBUG_USER_STATE = 1U << 0,
+ ANDROID_POWER_DEBUG_EXIT_SUSPEND = 1U << 1,
+ ANDROID_POWER_DEBUG_SUSPEND = 1U << 2,
+ ANDROID_POWER_DEBUG_USER_WAKE_LOCK = 1U << 3,
+ ANDROID_POWER_DEBUG_WAKE_LOCK = 1U << 4,
+};
+static int android_power_debug_mask =
+ ANDROID_POWER_DEBUG_USER_STATE | ANDROID_POWER_DEBUG_EXIT_SUSPEND;
+module_param_named(debug_mask, android_power_debug_mask,
+ int, S_IRUGO | S_IWUSR | S_IWGRP);
+
+#define ANDROID_POWER_TEST_EARLY_SUSPEND 0
+
+MODULE_DESCRIPTION("OMAP CSMI Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+
+#define ANDROID_SUSPEND_CONSOLE (MAX_NR_CONSOLES-2)
+
+static spinlock_t g_list_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_MUTEX(g_early_suspend_lock);
+
+wait_queue_head_t g_wait_queue;
+
+static LIST_HEAD(g_inactive_locks);
+static LIST_HEAD(g_active_idle_wake_locks);
+static LIST_HEAD(g_active_partial_wake_locks);
+static LIST_HEAD(g_active_full_wake_locks);
+static LIST_HEAD(g_early_suspend_handlers);
+static enum {
+ USER_AWAKE,
+ USER_NOTIFICATION,
+ USER_SLEEP
+} g_user_suspend_state;
+static int g_current_event_num;
+static struct workqueue_struct *g_suspend_work_queue;
+static void android_power_suspend(struct work_struct *work);
+static void android_power_wakeup_locked(int notification, ktime_t time);
+static DECLARE_WORK(g_suspend_work, android_power_suspend);
+static int g_max_user_lockouts = 16;
+
+//static const char g_free_user_lockout_name[] = "free_user";
+static struct {
+ enum {
+ USER_WAKE_LOCK_INACTIVE,
+ USER_WAKE_LOCK_PARTIAL,
+ USER_WAKE_LOCK_FULL
+ } state;
+ android_suspend_lock_t suspend_lock;
+ char name_buffer[32];
+} *g_user_wake_locks;
+#ifdef CONFIG_ANDROID_POWER_STAT
+android_suspend_lock_t g_deleted_wake_locks;
+android_suspend_lock_t g_no_wake_locks;
+#endif
+static struct kobject *android_power_kobj;
+#ifndef CONFIG_FRAMEBUFFER_CONSOLE
+static wait_queue_head_t fb_state_wq;
+static spinlock_t fb_state_lock = SPIN_LOCK_UNLOCKED;
+int fb_state;
+#endif
+
+#if 0
+android_suspend_lock_t *android_allocate_suspend_lock(const char *debug_name)
+{
+ unsigned long irqflags;
+ struct android_power *e;
+
+ e = kzalloc(sizeof(*e), GFP_KERNEL);
+ if(e == NULL) {
+ printk("android_power_allocate: kzalloc failed\n");
+ return NULL;
+ }
+ e->name = debug_name;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ list_add(&e->link, &g_allocated);
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return e;
+}
+#endif
+
+static int android_init_suspend_lock_internal(
+ android_suspend_lock_t *lock, int has_spin_lock)
+{
+ unsigned long irqflags;
+
+ if(lock->name == NULL) {
+ printk(KERN_ERR "android_init_suspend_lock: error name=NULL, "
+ "lock=%p\n", lock);
+ dump_stack();
+ return -EINVAL;
+ }
+
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_init_suspend_lock name=%s\n",
+ lock->name);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ lock->stat.count = 0;
+ lock->stat.expire_count = 0;
+ lock->stat.total_time = ktime_set(0, 0);
+ lock->stat.max_time = ktime_set(0, 0);
+ lock->stat.last_time = ktime_set(0, 0);
+#endif
+ lock->flags = 0;
+
+ INIT_LIST_HEAD(&lock->link);
+ if (!has_spin_lock)
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ list_add(&lock->link, &g_inactive_locks);
+ if (!has_spin_lock)
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+// if(lock->flags & ANDROID_SUSPEND_LOCK_FLAG_USER_VISIBLE_MASK) {
+// sysfs_create_file(struct kobject * k, const struct attribute * a)
+// }
+ return 0;
+}
+
+int android_init_suspend_lock(android_suspend_lock_t *lock)
+{
+ return android_init_suspend_lock_internal(lock, 0);
+}
+
+void android_uninit_suspend_lock(android_suspend_lock_t *lock)
+{
+ unsigned long irqflags;
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_uninit_suspend_lock name=%s\n",
+ lock->name);
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(lock->stat.count) {
+ if(g_deleted_wake_locks.stat.count == 0) {
+ g_deleted_wake_locks.name = "deleted_wake_locks";
+ android_init_suspend_lock_internal(
+ &g_deleted_wake_locks, 1);
+ }
+ g_deleted_wake_locks.stat.count += lock->stat.count;
+ g_deleted_wake_locks.stat.expire_count += lock->stat.expire_count;
+ g_deleted_wake_locks.stat.total_time = ktime_add(g_deleted_wake_locks.stat.total_time, lock->stat.total_time);
+ g_deleted_wake_locks.stat.max_time = ktime_add(g_deleted_wake_locks.stat.max_time, lock->stat.max_time);
+ }
+#endif
+ list_del(&lock->link);
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+void android_lock_idle(android_suspend_lock_t *lock)
+{
+ unsigned long irqflags;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
+ lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
+ lock->stat.last_time = ktime_get();
+ }
+#endif
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_power: acquire idle wake lock: %s\n",
+ lock->name);
+ lock->expires = INT_MAX;
+ lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+ list_del(&lock->link);
+ list_add(&lock->link, &g_active_idle_wake_locks);
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+void android_lock_idle_auto_expire(android_suspend_lock_t *lock, int timeout)
+{
+ unsigned long irqflags;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
+ lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
+ lock->stat.last_time = ktime_get();
+ }
+#endif
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_power: acquire idle wake lock: %s, "
+ "timeout %d.%03lu\n", lock->name, timeout / HZ,
+ (timeout % HZ) * MSEC_PER_SEC / HZ);
+ lock->expires = jiffies + timeout;
+ lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+ list_del(&lock->link);
+ list_add(&lock->link, &g_active_idle_wake_locks);
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+void android_lock_suspend(android_suspend_lock_t *lock)
+{
+ unsigned long irqflags;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
+ lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
+ lock->stat.last_time = ktime_get();
+ }
+#endif
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_power: acquire wake lock: %s\n",
+ lock->name);
+ lock->expires = INT_MAX;
+ lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+ list_del(&lock->link);
+ list_add(&lock->link, &g_active_partial_wake_locks);
+ g_current_event_num++;
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+void android_lock_suspend_auto_expire(android_suspend_lock_t *lock, int timeout)
+{
+ unsigned long irqflags;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
+ lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
+ lock->stat.last_time = ktime_get();
+ }
+#endif
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_power: acquire wake lock: %s, "
+ "timeout %d.%03lu\n", lock->name, timeout / HZ,
+ (timeout % HZ) * MSEC_PER_SEC / HZ);
+ lock->expires = jiffies + timeout;
+ lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+ list_del(&lock->link);
+ list_add(&lock->link, &g_active_partial_wake_locks);
+ g_current_event_num++;
+ wake_up(&g_wait_queue);
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+void android_lock_partial_suspend_auto_expire(android_suspend_lock_t *lock, int timeout)
+{
+ unsigned long irqflags;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(!(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)) {
+ lock->flags |= ANDROID_SUSPEND_LOCK_ACTIVE;
+ lock->stat.last_time = ktime_get();
+ }
+#endif
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_power: acquire full wake lock: %s, "
+ "timeout %d.%03lu\n", lock->name, timeout / HZ,
+ (timeout % HZ) * MSEC_PER_SEC / HZ);
+ lock->expires = jiffies + timeout;
+ lock->flags |= ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+ list_del(&lock->link);
+ list_add(&lock->link, &g_active_full_wake_locks);
+ g_current_event_num++;
+ wake_up(&g_wait_queue);
+ android_power_wakeup_locked(1, ktime_get());
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+#ifdef CONFIG_ANDROID_POWER_STAT
+static int print_lock_stat(char *buf, android_suspend_lock_t *lock)
+{
+ ktime_t active_time;
+ if(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE)
+ active_time = ktime_sub(ktime_get(), lock->stat.last_time);
+ else
+ active_time = ktime_set(0, 0);
+ return sprintf(buf, "\"%s\"\t%d\t%d\t%lld\t%lld\t%lld\t%lld\n",
+ lock->name,
+ lock->stat.count, lock->stat.expire_count,
+ ktime_to_ns(active_time),
+ ktime_to_ns(lock->stat.total_time),
+ ktime_to_ns(lock->stat.max_time),
+ ktime_to_ns(lock->stat.last_time));
+}
+
+
+static int wakelocks_read_proc(char *page, char **start, off_t off,
+ int count, int *eof, void *data)
+{
+ unsigned long irqflags;
+ android_suspend_lock_t *lock;
+ int len = 0;
+ char *p = page;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+
+ p += sprintf(p, "name\tcount\texpire_count\tactive_since\ttotal_time\tmax_time\tlast_change\n");
+ list_for_each_entry(lock, &g_inactive_locks, link) {
+ p += print_lock_stat(p, lock);
+ }
+ list_for_each_entry(lock, &g_active_partial_wake_locks, link) {
+ p += print_lock_stat(p, lock);
+ }
+ list_for_each_entry(lock, &g_active_full_wake_locks, link) {
+ p += print_lock_stat(p, lock);
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+
+
+ *start = page + off;
+
+ len = p - page;
+ if (len > off)
+ len -= off;
+ else
+ len = 0;
+
+ return len < count ? len : count;
+}
+
+static void android_unlock_suspend_stat_locked(android_suspend_lock_t *lock)
+{
+ if(lock->flags & ANDROID_SUSPEND_LOCK_ACTIVE) {
+ ktime_t duration;
+ lock->flags &= ~ANDROID_SUSPEND_LOCK_ACTIVE;
+ lock->stat.count++;
+ duration = ktime_sub(ktime_get(), lock->stat.last_time);
+ lock->stat.total_time = ktime_add(lock->stat.total_time, duration);
+ if(ktime_to_ns(duration) > ktime_to_ns(lock->stat.max_time))
+ lock->stat.max_time = duration;
+ lock->stat.last_time = ktime_get();
+ }
+}
+#endif
+
+void android_unlock_suspend(android_suspend_lock_t *lock)
+{
+ int had_full_wake_locks;
+ unsigned long irqflags;
+ spin_lock_irqsave(&g_list_lock, irqflags);
+#ifdef CONFIG_ANDROID_POWER_STAT
+ android_unlock_suspend_stat_locked(lock);
+#endif
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk(KERN_INFO "android_power: release wake lock: %s\n",
+ lock->name);
+ lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+ had_full_wake_locks = !list_empty(&g_active_full_wake_locks);
+ list_del(&lock->link);
+ list_add(&lock->link, &g_inactive_locks);
+ wake_up(&g_wait_queue);
+ if(had_full_wake_locks && list_empty(&g_active_full_wake_locks)) {
+ printk("android_unlock_suspend: released at %lld\n", ktime_to_ns(ktime_get()));
+ if(g_user_suspend_state == USER_NOTIFICATION) {
+ printk("android sleep state %d->%d at %lld\n", g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_get()));
+ g_user_suspend_state = USER_SLEEP;
+ queue_work(g_suspend_work_queue, &g_suspend_work);
+ }
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+static void android_power_wakeup_locked(int notification, ktime_t time)
+{
+ int new_state = (notification == 0) ? USER_AWAKE : USER_NOTIFICATION;
+
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE) {
+ struct timespec ts;
+ struct rtc_time tm;
+ getnstimeofday(&ts);
+ rtc_time_to_tm(ts.tv_sec, &tm);
+ printk(KERN_INFO "android_power: wakeup (%d->%d) at %lld "
+ "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
+ g_user_suspend_state, new_state, ktime_to_ns(time),
+ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
+ }
+
+ if(new_state >= g_user_suspend_state) {
+ return;
+ }
+ g_user_suspend_state = new_state;
+ g_current_event_num++;
+ wake_up(&g_wait_queue);
+}
+
+static void android_power_wakeup(void)
+{
+ unsigned long irqflags;
+
+ ktime_t ktime_now;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ ktime_now = ktime_get();
+ android_power_wakeup_locked(0, ktime_now);
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+}
+
+static void android_power_request_sleep(void)
+{
+ unsigned long irqflags;
+ int already_suspended;
+ android_suspend_lock_t *lock, *next_lock;
+
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE) {
+ ktime_t ktime_now;
+ struct timespec ts;
+ struct rtc_time tm;
+ ktime_now = ktime_get();
+ getnstimeofday(&ts);
+ rtc_time_to_tm(ts.tv_sec, &tm);
+ printk(KERN_INFO "android_power: sleep (%d->%d) at %lld "
+ "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n",
+ g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_now),
+ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
+ }
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ already_suspended = g_user_suspend_state == USER_SLEEP;
+ if(!already_suspended) {
+ g_user_suspend_state = USER_SLEEP;
+ }
+
+ list_for_each_entry_safe(lock, next_lock, &g_active_full_wake_locks, link) {
+#ifdef CONFIG_ANDROID_POWER_STAT
+ android_unlock_suspend_stat_locked(lock);
+#endif
+ list_del(&lock->link);
+ list_add(&lock->link, &g_inactive_locks);
+ printk("android_power_suspend: aborted full wake lock %s\n", lock->name);
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ queue_work(g_suspend_work_queue, &g_suspend_work);
+}
+
+void android_register_early_suspend(android_early_suspend_t *handler)
+{
+ struct list_head *pos;
+
+ mutex_lock(&g_early_suspend_lock);
+ list_for_each(pos, &g_early_suspend_handlers) {
+ android_early_suspend_t *e = list_entry(pos, android_early_suspend_t, link);
+ if(e->level > handler->level)
+ break;
+ }
+ list_add_tail(&handler->link, pos);
+ mutex_unlock(&g_early_suspend_lock);
+}
+
+void android_unregister_early_suspend(android_early_suspend_t *handler)
+{
+ mutex_lock(&g_early_suspend_lock);
+ list_del(&handler->link);
+ mutex_unlock(&g_early_suspend_lock);
+}
+
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+static int orig_fgconsole;
+static void console_early_suspend(android_early_suspend_t *h)
+{
+ acquire_console_sem();
+ orig_fgconsole = fg_console;
+ if (vc_allocate(ANDROID_SUSPEND_CONSOLE))
+ goto err;
+ if (set_console(ANDROID_SUSPEND_CONSOLE))
+ goto err;
+ release_console_sem();
+
+ if (vt_waitactive(ANDROID_SUSPEND_CONSOLE))
+ pr_warning("console_early_suspend: Can't switch VCs.\n");
+ return;
+err:
+ pr_warning("console_early_suspend: Can't set console\n");
+ release_console_sem();
+}
+
+static void console_late_resume(android_early_suspend_t *h)
+{
+ int ret;
+ acquire_console_sem();
+ ret = set_console(orig_fgconsole);
+ release_console_sem();
+ if (ret) {
+ pr_warning("console_late_resume: Can't set console.\n");
+ return;
+ }
+
+ if (vt_waitactive(orig_fgconsole))
+ pr_warning("console_late_resume: Can't switch VCs.\n");
+}
+
+static android_early_suspend_t console_early_suspend_desc = {
+ .level = ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH,
+ .suspend = console_early_suspend,
+ .resume = console_late_resume,
+};
+#else
+/* tell userspace to stop drawing, wait for it to stop */
+static void stop_drawing_early_suspend(android_early_suspend_t *h)
+{
+ int ret;
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(&fb_state_lock, irq_flags);
+ fb_state = ANDROID_REQUEST_STOP_DRAWING;
+ spin_unlock_irqrestore(&fb_state_lock, irq_flags);
+
+ wake_up_all(&fb_state_wq);
+ ret = wait_event_timeout(fb_state_wq,
+ fb_state == ANDROID_STOPPED_DRAWING,
+ HZ);
+ if (unlikely(fb_state != ANDROID_STOPPED_DRAWING))
+ printk(KERN_WARNING "android_power: timeout waiting for "
+ "userspace to stop drawing\n");
+}
+
+/* tell userspace to start drawing */
+static void start_drawing_late_resume(android_early_suspend_t *h)
+{
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(&fb_state_lock, irq_flags);
+ fb_state = ANDROID_DRAWING_OK;
+ spin_unlock_irqrestore(&fb_state_lock, irq_flags);
+ wake_up(&fb_state_wq);
+}
+
+static android_early_suspend_t stop_drawing_early_suspend_desc = {
+ .level = ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH,
+ .suspend = stop_drawing_early_suspend,
+ .resume = start_drawing_late_resume,
+};
+#endif
+
+#if ANDROID_POWER_TEST_EARLY_SUSPEND
+
+typedef struct
+{
+ android_early_suspend_t h;
+ const char *string;
+} early_suspend_test_t;
+
+static void early_suspend_test(android_early_suspend_t *h)
+{
+ early_suspend_test_t *est = container_of(h, early_suspend_test_t, h);
+ printk("early suspend %s (l %d)\n", est->string, h->level);
+}
+
+static void late_resume_test(android_early_suspend_t *h)
+{
+ early_suspend_test_t *est = container_of(h, early_suspend_test_t, h);
+ printk("late resume %s (l %d)\n", est->string, h->level);
+}
+
+#define EARLY_SUSPEND_TEST_ENTRY(ilevel, istring) \
+{ \
+ .h = { \
+ .level = ilevel, \
+ .suspend = early_suspend_test, \
+ .resume = late_resume_test \
+ }, \
+ .string = istring \
+}
+static early_suspend_test_t early_suspend_tests[] = {
+ EARLY_SUSPEND_TEST_ENTRY(10, "1"),
+ EARLY_SUSPEND_TEST_ENTRY(5, "2"),
+ EARLY_SUSPEND_TEST_ENTRY(10, "3"),
+ EARLY_SUSPEND_TEST_ENTRY(15, "4"),
+ EARLY_SUSPEND_TEST_ENTRY(8, "5")
+};
+
+#endif
+
+static int get_wait_timeout(int print_locks, int state, struct list_head *list_head)
+{
+ unsigned long irqflags;
+ android_suspend_lock_t *lock, *next;
+ int max_timeout = 0;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ list_for_each_entry_safe(lock, next, list_head, link) {
+ if(lock->flags & ANDROID_SUSPEND_LOCK_AUTO_EXPIRE) {
+ int timeout = lock->expires - (int)jiffies;
+ if(timeout <= 0) {
+ lock->flags &= ~ANDROID_SUSPEND_LOCK_AUTO_EXPIRE;
+#ifdef CONFIG_ANDROID_POWER_STAT
+ lock->stat.expire_count++;
+ android_unlock_suspend_stat_locked(lock);
+#endif
+ list_del(&lock->link);
+ list_add(&lock->link, &g_inactive_locks);
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_WAKE_LOCK)
+ printk("expired wake lock %s\n", lock->name);
+ }
+ else {
+ if(timeout > max_timeout)
+ max_timeout = timeout;
+ if(print_locks)
+ printk("active wake lock %s, time left %d\n", lock->name, timeout);
+ }
+ }
+ else {
+ if(print_locks)
+ printk("active wake lock %s\n", lock->name);
+ }
+ }
+ if(g_user_suspend_state != state || list_empty(list_head))
+ max_timeout = -1;
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return max_timeout;
+}
+
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+static int android_power_class_suspend(struct sys_device *sdev, pm_message_t state)
+{
+ int rv = 0;
+ unsigned long irqflags;
+
+ printk("android_power_suspend: enter\n");
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ if(!list_empty(&g_active_partial_wake_locks)) {
+ printk("android_power_suspend: abort for partial wakeup\n");
+ rv = -EAGAIN;
+ }
+ if(g_user_suspend_state != USER_SLEEP) {
+ printk("android_power_suspend: abort for full wakeup\n");
+ rv = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return rv;
+}
+
+static int android_power_device_suspend(struct sys_device *sdev, pm_message_t state)
+{
+ int rv = 0;
+ unsigned long irqflags;
+
+ printk("android_power_device_suspend: enter\n");
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ if(!list_empty(&g_active_partial_wake_locks)) {
+ printk("android_power_device_suspend: abort for partial wakeup\n");
+ rv = -EAGAIN;
+ }
+ if(g_user_suspend_state != USER_SLEEP) {
+ printk("android_power_device_suspend: abort for full wakeup\n");
+ rv = -EAGAIN;
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return rv;
+}
+#endif
+
+int android_power_is_driver_suspended(void)
+{
+ return (get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) < 0) && (g_user_suspend_state == USER_SLEEP);
+}
+
+int android_power_is_low_power_idle_ok(void)
+{
+ get_wait_timeout(0, USER_SLEEP, &g_active_idle_wake_locks);
+ return list_empty(&g_active_idle_wake_locks);
+}
+
+static void android_power_suspend(struct work_struct *work)
+{
+ int entry_event_num;
+ int ret;
+ int wait = 0;
+ android_early_suspend_t *pos;
+ int print_locks = 0;
+ unsigned long irqflags;
+
+ while(g_user_suspend_state != USER_AWAKE) {
+ while(g_user_suspend_state == USER_NOTIFICATION) {
+ wait = get_wait_timeout(print_locks, USER_NOTIFICATION, &g_active_full_wake_locks);
+ if(wait < 0)
+ break;
+ if(wait)
+ wait_event_interruptible_timeout(g_wait_queue, get_wait_timeout(0, USER_NOTIFICATION, &g_active_full_wake_locks) != wait, wait);
+ }
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ if(g_user_suspend_state == USER_NOTIFICATION && list_empty(&g_active_full_wake_locks)) {
+ printk("android sleep state %d->%d at %lld\n", g_user_suspend_state, USER_SLEEP, ktime_to_ns(ktime_get()));
+ g_user_suspend_state = USER_SLEEP;
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ wait = 0;
+ if(g_user_suspend_state == USER_AWAKE) {
+ printk("android_power_suspend: suspend aborted\n");
+ return;
+ }
+
+ mutex_lock(&g_early_suspend_lock);
+ //printk("android_power_suspend: call early suspend handlers\n");
+ list_for_each_entry(pos, &g_early_suspend_handlers, link) {
+ if(pos->suspend != NULL)
+ pos->suspend(pos);
+ }
+ //printk("android_power_suspend: call early suspend handlers\n");
+
+ //printk("android_power_suspend: enter\n");
+
+ sys_sync();
+
+ while(g_user_suspend_state == USER_SLEEP) {
+ //printk("android_power_suspend: enter wait (%d)\n", wait);
+ if(wait) {
+ wait_event_interruptible_timeout(g_wait_queue, g_user_suspend_state != USER_SLEEP, wait);
+ wait = 0;
+ }
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
+ print_locks = 1;
+ while(1) {
+ wait = get_wait_timeout(print_locks, USER_SLEEP, &g_active_partial_wake_locks);
+ print_locks = 0;
+ if(wait < 0)
+ break;
+ if(wait)
+ wait_event_interruptible_timeout(g_wait_queue, get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) != wait, wait);
+ else
+ wait_event_interruptible(g_wait_queue, get_wait_timeout(0, USER_SLEEP, &g_active_partial_wake_locks) != wait);
+ }
+ wait = 0;
+ //printk("android_power_suspend: exit wait\n");
+ entry_event_num = g_current_event_num;
+ if(g_user_suspend_state != USER_SLEEP)
+ break;
+ sys_sync();
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
+ printk(KERN_INFO "android_power_suspend: enter suspend\n");
+ ret = pm_suspend(PM_SUSPEND_MEM);
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_EXIT_SUSPEND) {
+ struct timespec ts;
+ struct rtc_time tm;
+ getnstimeofday(&ts);
+ rtc_time_to_tm(ts.tv_sec, &tm);
+ printk("android_power_suspend: exit suspend, ret = %d "
+ "(%d-%02d-%02d %02d:%02d:%02d.%09lu UTC)\n", ret,
+ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec, ts.tv_nsec);
+ }
+ if(g_current_event_num == entry_event_num) {
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_SUSPEND)
+ printk(KERN_INFO "android_power_suspend: pm_suspend returned with no event\n");
+ wait = HZ / 2;
+#ifdef CONFIG_ANDROID_POWER_STAT
+ if(g_no_wake_locks.stat.count == 0) {
+ g_no_wake_locks.name = "unknown_wakeups";
+ android_init_suspend_lock(&g_no_wake_locks);
+ }
+ g_no_wake_locks.stat.count++;
+ g_no_wake_locks.stat.total_time = ktime_add(
+ g_no_wake_locks.stat.total_time,
+ ktime_set(0, 500 * NSEC_PER_MSEC));
+ g_no_wake_locks.stat.max_time =
+ ktime_set(0, 500 * NSEC_PER_MSEC);
+#endif
+ }
+ }
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_STATE)
+ printk("android_power_suspend: done\n");
+ //printk("android_power_suspend: call late resume handlers\n");
+ list_for_each_entry_reverse(pos, &g_early_suspend_handlers, link) {
+ if(pos->resume != NULL)
+ pos->resume(pos);
+ }
+ //printk("android_power_suspend: call late resume handlers\n");
+ mutex_unlock(&g_early_suspend_lock);
+ }
+}
+
+#if 0
+struct sysdev_class android_power_sysclass = {
+ set_kset_name("android_power"),
+ .suspend = android_power_class_suspend
+};
+static struct sysdev_class *g_android_power_sysclass = NULL;
+
+static struct {
+ struct sys_device sysdev;
+// omap_csmi_gsm_image_info_t *pdata;
+} android_power_device = {
+ .sysdev = {
+ .id = 0,
+ .cls = &android_power_sysclass,
+// .suspend = android_power_device_suspend
+ },
+// .pdata = &g_gsm_image_info
+};
+
+struct sysdev_class *android_power_get_sysclass(void)
+{
+ return g_android_power_sysclass;
+}
+#endif
+
+static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
+{
+ char * s = buf;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ s += sprintf(s, "%d-%d-%d\n", g_user_suspend_state, list_empty(&g_active_full_wake_locks), list_empty(&g_active_partial_wake_locks));
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return (s - buf);
+}
+
+static ssize_t state_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
+{
+ if(n >= strlen("standby") &&
+ strncmp(buf, "standby", strlen("standby")) == 0) {
+ android_power_request_sleep();
+ wait_event_interruptible(g_wait_queue, g_user_suspend_state == USER_AWAKE);
+ return n;
+ }
+ if(n >= strlen("wake") &&
+ strncmp(buf, "wake", strlen("wake")) == 0) {
+ android_power_wakeup();
+ return n;
+ }
+ printk("android_power state_store: invalid argument\n");
+ return -EINVAL;
+}
+
+static ssize_t request_state_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
+{
+ char * s = buf;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ if(g_user_suspend_state == USER_AWAKE)
+ s += sprintf(s, "wake\n");
+ else if(g_user_suspend_state == USER_NOTIFICATION)
+ s += sprintf(s, "standby (w/full wake lock)\n");
+ else
+ s += sprintf(s, "standby\n");
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return (s - buf);
+}
+
+static ssize_t request_state_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
+{
+ if(n >= strlen("standby") &&
+ strncmp(buf, "standby", strlen("standby")) == 0) {
+ android_power_request_sleep();
+ return n;
+ }
+ if(n >= strlen("wake") &&
+ strncmp(buf, "wake", strlen("wake")) == 0) {
+ android_power_wakeup();
+ return n;
+ }
+ printk("android_power state_store: invalid argument\n");
+ return -EINVAL;
+}
+
+
+static int lookup_wake_lock_name(const char *buf, size_t n, int allocate, int *timeout)
+{
+ int i;
+ int free_index = -1;
+ int inactive_index = -1;
+ int expires_index = -1;
+ int expires_time = INT_MAX;
+ char *tmp_buf[64];
+ char name[32];
+ u64 nanoseconds;
+ int num_arg;
+
+ if(n <= 0)
+ return -EINVAL;
+ if(n >= sizeof(tmp_buf))
+ return -EOVERFLOW;
+ if(n == sizeof(tmp_buf) - 1 && buf[n - 1] != '\0')
+ return -EOVERFLOW;
+
+ memcpy(tmp_buf, buf, n);
+ if(tmp_buf[n - 1] != '\0')
+ tmp_buf[n] = '\0';
+
+ num_arg = sscanf(buf, "%31s %llu", name, &nanoseconds);
+ if(num_arg < 1)
+ return -EINVAL;
+
+ if(strlen(name) >= sizeof(g_user_wake_locks[i].name_buffer))
+ return -EOVERFLOW;
+
+ if(timeout != NULL) {
+ if(num_arg > 1) {
+ do_div(nanoseconds, (NSEC_PER_SEC / HZ));
+ if(nanoseconds <= 0)
+ nanoseconds = 1;
+ *timeout = nanoseconds;
+ }
+ else
+ *timeout = 0;
+ }
+
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ if(strcmp(g_user_wake_locks[i].name_buffer, name) == 0)
+ return i;
+ if(g_user_wake_locks[i].name_buffer[0] == '\0')
+ free_index = i;
+ else if(g_user_wake_locks[i].state == USER_WAKE_LOCK_INACTIVE)
+ inactive_index = i;
+ else if(g_user_wake_locks[i].suspend_lock.expires < expires_time)
+ expires_index = i;
+ }
+ if(allocate) {
+ if(free_index >= 0)
+ i = free_index;
+ else if(inactive_index >= 0)
+ i = inactive_index;
+ else if(expires_index >= 0) {
+ i = expires_index;
+ printk("lookup_wake_lock_name: overwriting expired lock, %s\n", g_user_wake_locks[i].name_buffer);
+ }
+ else {
+ i = 0;
+ printk("lookup_wake_lock_name: overwriting active lock, %s\n", g_user_wake_locks[i].name_buffer);
+ }
+ strcpy(g_user_wake_locks[i].name_buffer, name);
+ return i;
+ }
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
+ printk(KERN_INFO "lookup_wake_lock_name: %s not found\n", name);
+ return -EINVAL;
+}
+
+static ssize_t acquire_full_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
+{
+ int i;
+ char * s = buf;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_FULL)
+ s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
+ }
+ s += sprintf(s, "\n");
+
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return (s - buf);
+}
+
+static ssize_t acquire_full_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
+{
+ int i;
+ unsigned long irqflags;
+ int timeout;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ i = lookup_wake_lock_name(buf, n, 1, &timeout);
+ if(i >= 0)
+ g_user_wake_locks[i].state = USER_WAKE_LOCK_FULL;
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ if(i < 0)
+ return i;
+
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
+ printk(KERN_INFO "acquire_full_wake_lock_store: %s, size %d\n",
+ g_user_wake_locks[i].name_buffer, n);
+
+ //android_lock_partial_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, ktime_to_timespec(g_auto_off_timeout).tv_sec * HZ);
+ if(timeout == 0)
+ timeout = INT_MAX;
+ android_lock_partial_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, timeout);
+
+ return n;
+}
+
+static ssize_t acquire_partial_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
+{
+ int i;
+ char * s = buf;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_PARTIAL)
+ s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
+ }
+ s += sprintf(s, "\n");
+
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return (s - buf);
+}
+
+static ssize_t acquire_partial_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
+{
+ int i;
+ unsigned long irqflags;
+ int timeout;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ i = lookup_wake_lock_name(buf, n, 1, &timeout);
+ if(i >= 0)
+ g_user_wake_locks[i].state = USER_WAKE_LOCK_PARTIAL;
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ if(i < 0)
+ return 0;
+
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
+ printk(KERN_INFO "acquire_partial_wake_lock_store: %s, "
+ "size %d\n", g_user_wake_locks[i].name_buffer, n);
+
+ if(timeout)
+ android_lock_suspend_auto_expire(&g_user_wake_locks[i].suspend_lock, timeout);
+ else
+ android_lock_suspend(&g_user_wake_locks[i].suspend_lock);
+
+ return n;
+}
+
+
+static ssize_t release_wake_lock_show(struct kobject *kobj, struct kobj_attribute *attr, char * buf)
+{
+ int i;
+ char * s = buf;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ if(g_user_wake_locks[i].name_buffer[0] != '\0' && g_user_wake_locks[i].state == USER_WAKE_LOCK_INACTIVE)
+ s += sprintf(s, "%s ", g_user_wake_locks[i].name_buffer);
+ }
+ s += sprintf(s, "\n");
+
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+ return (s - buf);
+}
+
+static ssize_t release_wake_lock_store(struct kobject *kobj, struct kobj_attribute *attr, const char * buf, size_t n)
+{
+ int i;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&g_list_lock, irqflags);
+ i = lookup_wake_lock_name(buf, n, 1, NULL);
+ if(i >= 0) {
+ g_user_wake_locks[i].state = USER_WAKE_LOCK_INACTIVE;
+ }
+ spin_unlock_irqrestore(&g_list_lock, irqflags);
+
+ if(i < 0)
+ return i;
+
+ if (android_power_debug_mask & ANDROID_POWER_DEBUG_USER_WAKE_LOCK)
+ printk(KERN_INFO "release_wake_lock_store: %s, size %d\n",
+ g_user_wake_locks[i].name_buffer, n);
+
+ android_unlock_suspend(&g_user_wake_locks[i].suspend_lock);
+ return n;
+}
+
+
+#ifndef CONFIG_FRAMEBUFFER_CONSOLE
+static ssize_t wait_for_fb_sleep_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ char * s = buf;
+ int ret;
+
+ ret = wait_event_interruptible(fb_state_wq,
+ fb_state != ANDROID_DRAWING_OK);
+ if (ret && fb_state == ANDROID_DRAWING_OK)
+ return ret;
+ else
+ s += sprintf(buf, "sleeping");
+ return (s - buf);
+}
+
+static ssize_t wait_for_fb_wake_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ char * s = buf;
+ int ret;
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(&fb_state_lock, irq_flags);
+ if (fb_state == ANDROID_REQUEST_STOP_DRAWING) {
+ fb_state = ANDROID_STOPPED_DRAWING;
+ wake_up(&fb_state_wq);
+ }
+ spin_unlock_irqrestore(&fb_state_lock, irq_flags);
+
+ ret = wait_event_interruptible(fb_state_wq,
+ fb_state == ANDROID_DRAWING_OK);
+ if (ret && fb_state != ANDROID_DRAWING_OK)
+ return ret;
+ else
+ s += sprintf(buf, "awake");
+
+ return (s - buf);
+}
+#endif
+
+#define android_power_attr(_name) \
+static struct kobj_attribute _name##_attr = { \
+ .attr = { \
+ .name = __stringify(_name), \
+ .mode = 0664, \
+ }, \
+ .show = _name##_show, \
+ .store = _name##_store, \
+}
+
+#define android_power_ro_attr(_name) \
+static struct kobj_attribute _name##_attr = { \
+ .attr = { \
+ .name = __stringify(_name), \
+ .mode = 0444, \
+ }, \
+ .show = _name##_show, \
+ .store = NULL, \
+}
+
+android_power_attr(state);
+android_power_attr(request_state);
+android_power_attr(acquire_full_wake_lock);
+android_power_attr(acquire_partial_wake_lock);
+android_power_attr(release_wake_lock);
+#ifndef CONFIG_FRAMEBUFFER_CONSOLE
+android_power_ro_attr(wait_for_fb_sleep);
+android_power_ro_attr(wait_for_fb_wake);
+#endif
+
+static struct attribute * g[] = {
+ &state_attr.attr,
+ &request_state_attr.attr,
+ &acquire_full_wake_lock_attr.attr,
+ &acquire_partial_wake_lock_attr.attr,
+ &release_wake_lock_attr.attr,
+#ifndef CONFIG_FRAMEBUFFER_CONSOLE
+ &wait_for_fb_sleep_attr.attr,
+ &wait_for_fb_wake_attr.attr,
+#endif
+ NULL,
+};
+
+static struct attribute_group attr_group = {
+ .attrs = g,
+};
+
+#if 0
+// test code when there is no platform suspend
+
+static android_suspend_lock_t test_pm_ops_suspend_lock = {
+ .name = "test_pm_ops"
+};
+
+int test_pm_op_enter(suspend_state_t state)
+{
+ printk("test_pm_op_enter reached\n");
+ android_lock_suspend(&test_pm_ops_suspend_lock);
+ printk("test_pm_op_enter returned\n");
+ return 0;
+}
+
+void test_pm_ops_late_resume_handler(android_early_suspend_t *h)
+{
+ printk("test_pm_ops_late_resume_handler reached\n");
+ android_unlock_suspend(&test_pm_ops_suspend_lock);
+ printk("test_pm_ops_late_resume_handler returned\n");
+}
+
+static struct pm_ops test_pm_ops = {
+ .enter = test_pm_op_enter
+};
+
+static android_early_suspend_t test_pm_ops_early_suspend_handler = {
+ .resume = test_pm_ops_late_resume_handler
+};
+#endif
+
+static int __init android_power_init(void)
+{
+ int ret;
+ int i;
+
+#if 0
+ if(pm_ops == NULL) {
+ printk("android_power_init no pm_ops, installing test code\n");
+ pm_set_ops(&test_pm_ops);
+ android_init_suspend_lock(&test_pm_ops_suspend_lock);
+ android_register_early_suspend(&test_pm_ops_early_suspend_handler);
+ }
+#endif
+
+#ifdef CONFIG_ANDROID_POWER_STAT
+ g_deleted_wake_locks.stat.count = 0;
+#endif
+ init_waitqueue_head(&g_wait_queue);
+#ifndef CONFIG_FRAMEBUFFER_CONSOLE
+ init_waitqueue_head(&fb_state_wq);
+ fb_state = ANDROID_DRAWING_OK;
+#endif
+
+ g_user_wake_locks = kzalloc(sizeof(*g_user_wake_locks) * g_max_user_lockouts, GFP_KERNEL);
+ if(g_user_wake_locks == NULL) {
+ ret = -ENOMEM;
+ goto err1;
+ }
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ g_user_wake_locks[i].suspend_lock.name = g_user_wake_locks[i].name_buffer;
+ android_init_suspend_lock(&g_user_wake_locks[i].suspend_lock);
+ }
+
+ g_suspend_work_queue = create_workqueue("suspend");
+ if(g_suspend_work_queue == NULL) {
+ ret = -ENOMEM;
+ goto err2;
+ }
+
+ android_power_kobj = kobject_create_and_add("android_power", NULL);
+ if (android_power_kobj == NULL) {
+ printk("android_power_init: subsystem_register failed\n");
+ ret = -ENOMEM;
+ goto err3;
+ }
+ ret = sysfs_create_group(android_power_kobj, &attr_group);
+ if(ret) {
+ printk("android_power_init: sysfs_create_group failed\n");
+ goto err4;
+ }
+#ifdef CONFIG_ANDROID_POWER_STAT
+ create_proc_read_entry("wakelocks", S_IRUGO, NULL, wakelocks_read_proc, NULL);
+#endif
+
+#if ANDROID_POWER_TEST_EARLY_SUSPEND
+ {
+ int i;
+ for(i = 0; i < sizeof(early_suspend_tests) / sizeof(early_suspend_tests[0]); i++)
+ android_register_early_suspend(&early_suspend_tests[i].h);
+ }
+#endif
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+ android_register_early_suspend(&console_early_suspend_desc);
+#else
+ android_register_early_suspend(&stop_drawing_early_suspend_desc);
+#endif
+
+#if 0
+ ret = sysdev_class_register(&android_power_sysclass);
+ if(ret) {
+ printk("android_power_init: sysdev_class_register failed\n");
+ goto err1;
+ }
+ ret = sysdev_register(&android_power_device.sysdev);
+ if(ret < 0)
+ goto err2;
+
+ g_android_power_sysclass = &android_power_sysclass;
+#endif
+ return 0;
+
+//err2:
+// sysdev_class_unregister(&android_power_sysclass);
+err4:
+ kobject_del(android_power_kobj);
+err3:
+ destroy_workqueue(g_suspend_work_queue);
+err2:
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ android_uninit_suspend_lock(&g_user_wake_locks[i].suspend_lock);
+ }
+ kfree(g_user_wake_locks);
+err1:
+ return ret;
+}
+
+static void __exit android_power_exit(void)
+{
+ int i;
+// g_android_power_sysclass = NULL;
+// sysdev_unregister(&android_power_device.sysdev);
+// sysdev_class_unregister(&android_power_sysclass);
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+ android_unregister_early_suspend(&console_early_suspend_desc);
+#else
+ android_unregister_early_suspend(&stop_drawing_early_suspend_desc);
+#endif
+#ifdef CONFIG_ANDROID_POWER_STAT
+ remove_proc_entry("wakelocks", NULL);
+#endif
+ sysfs_remove_group(android_power_kobj, &attr_group);
+ kobject_del(android_power_kobj);
+ destroy_workqueue(g_suspend_work_queue);
+ for(i = 0; i < g_max_user_lockouts; i++) {
+ android_uninit_suspend_lock(&g_user_wake_locks[i].suspend_lock);
+ }
+ kfree(g_user_wake_locks);
+}
+
+core_initcall(android_power_init);
+module_exit(android_power_exit);
+
+//EXPORT_SYMBOL(android_power_get_sysclass);
+EXPORT_SYMBOL(android_init_suspend_lock);
+EXPORT_SYMBOL(android_uninit_suspend_lock);
+EXPORT_SYMBOL(android_lock_suspend);
+EXPORT_SYMBOL(android_lock_suspend_auto_expire);
+EXPORT_SYMBOL(android_unlock_suspend);
+EXPORT_SYMBOL(android_power_wakeup);
+EXPORT_SYMBOL(android_register_early_suspend);
+EXPORT_SYMBOL(android_unregister_early_suspend);
+
+
--- /dev/null
+++ b/drivers/android/ram_console.c
@@ -0,0 +1,395 @@
+/* drivers/android/ram_console.c
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/proc_fs.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+#include <linux/rslib.h>
+#endif
+
+struct ram_console_buffer {
+ uint32_t sig;
+ uint32_t start;
+ uint32_t size;
+ uint8_t data[0];
+};
+
+#define RAM_CONSOLE_SIG (0x43474244) /* DBGC */
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
+static char __initdata
+ ram_console_old_log_init_buffer[CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE];
+#endif
+static char *ram_console_old_log;
+static size_t ram_console_old_log_size;
+
+static struct ram_console_buffer *ram_console_buffer;
+static size_t ram_console_buffer_size;
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+static char *ram_console_par_buffer;
+static struct rs_control *ram_console_rs_decoder;
+static int ram_console_corrected_bytes;
+static int ram_console_bad_blocks;
+#define ECC_BLOCK_SIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE
+#define ECC_SIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE
+#define ECC_SYMSIZE CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE
+#define ECC_POLY CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL
+#endif
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+static void ram_console_encode_rs8(uint8_t *data, size_t len, uint8_t *ecc)
+{
+ int i;
+ uint16_t par[ECC_SIZE];
+ /* Initialize the parity buffer */
+ memset(par, 0, sizeof(par));
+ encode_rs8(ram_console_rs_decoder, data, len, par, 0);
+ for (i = 0; i < ECC_SIZE; i++)
+ ecc[i] = par[i];
+}
+
+static int ram_console_decode_rs8(void *data, size_t len, uint8_t *ecc)
+{
+ int i;
+ uint16_t par[ECC_SIZE];
+ for (i = 0; i < ECC_SIZE; i++)
+ par[i] = ecc[i];
+ return decode_rs8(ram_console_rs_decoder, data, par, len,
+ NULL, 0, NULL, 0, NULL);
+}
+#endif
+
+static void ram_console_update(const char *s, unsigned int count)
+{
+ struct ram_console_buffer *buffer = ram_console_buffer;
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ uint8_t *buffer_end = buffer->data + ram_console_buffer_size;
+ uint8_t *block;
+ uint8_t *par;
+ int size = ECC_BLOCK_SIZE;
+#endif
+ memcpy(buffer->data + buffer->start, s, count);
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ block = buffer->data + (buffer->start & ~(ECC_BLOCK_SIZE - 1));
+ par = ram_console_par_buffer +
+ (buffer->start / ECC_BLOCK_SIZE) * ECC_SIZE;
+ do {
+ if (block + ECC_BLOCK_SIZE > buffer_end)
+ size = buffer_end - block;
+ ram_console_encode_rs8(block, size, par);
+ block += ECC_BLOCK_SIZE;
+ par += ECC_SIZE;
+ } while (block < buffer->data + buffer->start + count);
+#endif
+}
+
+static void ram_console_update_header(void)
+{
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ struct ram_console_buffer *buffer = ram_console_buffer;
+ uint8_t *par;
+ par = ram_console_par_buffer +
+ DIV_ROUND_UP(ram_console_buffer_size, ECC_BLOCK_SIZE) * ECC_SIZE;
+ ram_console_encode_rs8((uint8_t *)buffer, sizeof(*buffer), par);
+#endif
+}
+
+static void
+ram_console_write(struct console *console, const char *s, unsigned int count)
+{
+ int rem;
+ struct ram_console_buffer *buffer = ram_console_buffer;
+
+ if (count > ram_console_buffer_size) {
+ s += count - ram_console_buffer_size;
+ count = ram_console_buffer_size;
+ }
+ rem = ram_console_buffer_size - buffer->start;
+ if (rem < count) {
+ ram_console_update(s, rem);
+ s += rem;
+ count -= rem;
+ buffer->start = 0;
+ buffer->size = ram_console_buffer_size;
+ }
+ ram_console_update(s, count);
+
+ buffer->start += count;
+ if (buffer->size < ram_console_buffer_size)
+ buffer->size += count;
+ ram_console_update_header();
+}
+
+static struct console ram_console = {
+ .name = "ram",
+ .write = ram_console_write,
+ .flags = CON_PRINTBUFFER | CON_ENABLED,
+ .index = -1,
+};
+
+static void __init
+ram_console_save_old(struct ram_console_buffer *buffer, char *dest)
+{
+ size_t old_log_size = buffer->size;
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ uint8_t *block;
+ uint8_t *par;
+ char strbuf[80];
+ int strbuf_len;
+
+ block = buffer->data;
+ par = ram_console_par_buffer;
+ while (block < buffer->data + buffer->size) {
+ int numerr;
+ int size = ECC_BLOCK_SIZE;
+ if (block + size > buffer->data + ram_console_buffer_size)
+ size = buffer->data + ram_console_buffer_size - block;
+ numerr = ram_console_decode_rs8(block, size, par);
+ if (numerr > 0) {
+#if 0
+ printk(KERN_INFO "ram_console: error in block %p, %d\n",
+ block, numerr);
+#endif
+ ram_console_corrected_bytes += numerr;
+ } else if (numerr < 0) {
+#if 0
+ printk(KERN_INFO "ram_console: uncorrectable error in "
+ "block %p\n", block);
+#endif
+ ram_console_bad_blocks++;
+ }
+ block += ECC_BLOCK_SIZE;
+ par += ECC_SIZE;
+ }
+ if (ram_console_corrected_bytes || ram_console_bad_blocks)
+ strbuf_len = snprintf(strbuf, sizeof(strbuf),
+ "\n%d Corrected bytes, %d unrecoverable blocks\n",
+ ram_console_corrected_bytes, ram_console_bad_blocks);
+ else
+ strbuf_len = snprintf(strbuf, sizeof(strbuf),
+ "\nNo errors detected\n");
+ if (strbuf_len >= sizeof(strbuf))
+ strbuf_len = sizeof(strbuf) - 1;
+ old_log_size += strbuf_len;
+#endif
+
+ if (dest == NULL) {
+ dest = kmalloc(old_log_size, GFP_KERNEL);
+ if (dest == NULL) {
+ printk(KERN_ERR
+ "ram_console: failed to allocate buffer\n");
+ return;
+ }
+ }
+
+ ram_console_old_log = dest;
+ ram_console_old_log_size = old_log_size;
+ memcpy(ram_console_old_log,
+ &buffer->data[buffer->start], buffer->size - buffer->start);
+ memcpy(ram_console_old_log + buffer->size - buffer->start,
+ &buffer->data[0], buffer->start);
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ memcpy(ram_console_old_log + old_log_size - strbuf_len,
+ strbuf, strbuf_len);
+#endif
+}
+
+static int __init ram_console_init(struct ram_console_buffer *buffer,
+ size_t buffer_size, char *old_buf)
+{
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ int numerr;
+ uint8_t *par;
+#endif
+ ram_console_buffer = buffer;
+ ram_console_buffer_size =
+ buffer_size - sizeof(struct ram_console_buffer);
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION
+ ram_console_buffer_size -= (DIV_ROUND_UP(ram_console_buffer_size,
+ ECC_BLOCK_SIZE) + 1) * ECC_SIZE;
+ ram_console_par_buffer = buffer->data + ram_console_buffer_size;
+
+
+ /* first consecutive root is 0
+ * primitive element to generate roots = 1
+ */
+ ram_console_rs_decoder = init_rs(ECC_SYMSIZE, ECC_POLY, 0, 1, ECC_SIZE);
+ if (ram_console_rs_decoder == NULL) {
+ printk(KERN_INFO "ram_console: init_rs failed\n");
+ return 0;
+ }
+
+ ram_console_corrected_bytes = 0;
+ ram_console_bad_blocks = 0;
+
+ par = ram_console_par_buffer +
+ DIV_ROUND_UP(ram_console_buffer_size, ECC_BLOCK_SIZE) * ECC_SIZE;
+
+ numerr = ram_console_decode_rs8(buffer, sizeof(*buffer), par);
+ if (numerr > 0) {
+ printk(KERN_INFO "ram_console: error in header, %d\n", numerr);
+ ram_console_corrected_bytes += numerr;
+ } else if (numerr < 0) {
+ printk(KERN_INFO
+ "ram_console: uncorrectable error in header\n");
+ ram_console_bad_blocks++;
+ }
+#endif
+
+ if (buffer->sig == RAM_CONSOLE_SIG) {
+ if (buffer->size > ram_console_buffer_size
+ || buffer->start > buffer->size)
+ printk(KERN_INFO "ram_console: found existing invalid "
+ "buffer, size %d, start %d\n",
+ buffer->size, buffer->start);
+ else {
+ printk(KERN_INFO "ram_console: found existing buffer, "
+ "size %d, start %d\n",
+ buffer->size, buffer->start);
+ ram_console_save_old(buffer, old_buf);
+ }
+ } else {
+ printk(KERN_INFO "ram_console: no valid data in buffer "
+ "(sig = 0x%08x)\n", buffer->sig);
+ }
+
+ buffer->sig = RAM_CONSOLE_SIG;
+ buffer->start = 0;
+ buffer->size = 0;
+
+ register_console(&ram_console);
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE
+ console_verbose();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
+static int __init ram_console_early_init(void)
+{
+ return ram_console_init((struct ram_console_buffer *)
+ CONFIG_ANDROID_RAM_CONSOLE_EARLY_ADDR,
+ CONFIG_ANDROID_RAM_CONSOLE_EARLY_SIZE,
+ ram_console_old_log_init_buffer);
+}
+#else
+static int ram_console_driver_probe(struct platform_device *pdev)
+{
+ struct resource *res = pdev->resource;
+ size_t start;
+ size_t buffer_size;
+ void *buffer;
+
+ if (res == NULL || pdev->num_resources != 1 ||
+ !(res->flags & IORESOURCE_MEM)) {
+ printk(KERN_ERR "ram_console: invalid resource, %p %d flags "
+ "%lx\n", res, pdev->num_resources, res ? res->flags : 0);
+ return -ENXIO;
+ }
+ buffer_size = res->end - res->start + 1;
+ start = res->start;
+ printk(KERN_INFO "ram_console: got buffer at %x, size %x\n",
+ start, buffer_size);
+ buffer = ioremap(res->start, buffer_size);
+ if (buffer == NULL) {
+ printk(KERN_ERR "ram_console: failed to map memory\n");
+ return -ENOMEM;
+ }
+
+ return ram_console_init(buffer, buffer_size, NULL/* allocate */);
+}
+
+static struct platform_driver ram_console_driver = {
+ .probe = ram_console_driver_probe,
+ .driver = {
+ .name = "ram_console",
+ },
+};
+
+static int __init ram_console_module_init(void)
+{
+ int err;
+ err = platform_driver_register(&ram_console_driver);
+ return err;
+}
+#endif
+
+static ssize_t ram_console_read_old(struct file *file, char __user *buf,
+ size_t len, loff_t *offset)
+{
+ loff_t pos = *offset;
+ ssize_t count;
+
+ if (pos >= ram_console_old_log_size)
+ return 0;
+
+ count = min(len, (size_t)(ram_console_old_log_size - pos));
+ if (copy_to_user(buf, ram_console_old_log + pos, count))
+ return -EFAULT;
+
+ *offset += count;
+ return count;
+}
+
+static struct file_operations ram_console_file_ops = {
+ .owner = THIS_MODULE,
+ .read = ram_console_read_old,
+};
+
+static int __init ram_console_late_init(void)
+{
+ struct proc_dir_entry *entry;
+
+ if (ram_console_old_log == NULL)
+ return 0;
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
+ ram_console_old_log = kmalloc(ram_console_old_log_size, GFP_KERNEL);
+ if (ram_console_old_log == NULL) {
+ printk(KERN_ERR
+ "ram_console: failed to allocate buffer for old log\n");
+ ram_console_old_log_size = 0;
+ return 0;
+ }
+ memcpy(ram_console_old_log,
+ ram_console_old_log_init_buffer, ram_console_old_log_size);
+#endif
+ entry = create_proc_entry("last_kmsg", S_IFREG | S_IRUGO, NULL);
+ if (!entry) {
+ printk(KERN_ERR "ram_console: failed to create proc entry\n");
+ kfree(ram_console_old_log);
+ ram_console_old_log = NULL;
+ return 0;
+ }
+
+ entry->proc_fops = &ram_console_file_ops;
+ entry->size = ram_console_old_log_size;
+ return 0;
+}
+
+#ifdef CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT
+console_initcall(ram_console_early_init);
+#else
+module_init(ram_console_module_init);
+#endif
+late_initcall(ram_console_late_init);
+
--- /dev/null
+++ b/drivers/android/timed_gpio.c
@@ -0,0 +1,177 @@
+/* drivers/android/timed_gpio.c
+ *
+ * Copyright (C) 2008 Google, Inc.
+ * Author: Mike Lockwood <lockwood@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/hrtimer.h>
+#include <linux/err.h>
+#include <mach/gpio.h>
+
+#include <linux/android_timed_gpio.h>
+
+
+static struct class *timed_gpio_class;
+
+struct timed_gpio_data {
+ struct device *dev;
+ struct hrtimer timer;
+ spinlock_t lock;
+ unsigned gpio;
+ int max_timeout;
+ u8 active_low;
+};
+
+static enum hrtimer_restart gpio_timer_func(struct hrtimer *timer)
+{
+ struct timed_gpio_data *gpio_data = container_of(timer, struct timed_gpio_data, timer);
+
+ gpio_direction_output(gpio_data->gpio, gpio_data->active_low ? 1 : 0);
+ return HRTIMER_NORESTART;
+}
+
+static ssize_t gpio_enable_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct timed_gpio_data *gpio_data = dev_get_drvdata(dev);
+ int remaining;
+
+ if (hrtimer_active(&gpio_data->timer)) {
+ ktime_t r = hrtimer_get_remaining(&gpio_data->timer);
+ remaining = r.tv.sec * 1000 + r.tv.nsec / 1000000;
+ } else
+ remaining = 0;
+
+ return sprintf(buf, "%d\n", remaining);
+}
+
+static ssize_t gpio_enable_store(
+ struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct timed_gpio_data *gpio_data = dev_get_drvdata(dev);
+ int value;
+ unsigned long flags;
+
+ sscanf(buf, "%d", &value);
+
+ spin_lock_irqsave(&gpio_data->lock, flags);
+
+ /* cancel previous timer and set GPIO according to value */
+ hrtimer_cancel(&gpio_data->timer);
+ gpio_direction_output(gpio_data->gpio, gpio_data->active_low ? !value : !!value);
+
+ if (value > 0) {
+ if (value > gpio_data->max_timeout)
+ value = gpio_data->max_timeout;
+
+ hrtimer_start(&gpio_data->timer,
+ ktime_set(value / 1000, (value % 1000) * 1000000),
+ HRTIMER_MODE_REL);
+ }
+
+ spin_unlock_irqrestore(&gpio_data->lock, flags);
+
+ return size;
+}
+
+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, gpio_enable_show, gpio_enable_store);
+
+static int android_timed_gpio_probe(struct platform_device *pdev)
+{
+ struct timed_gpio_platform_data *pdata = pdev->dev.platform_data;
+ struct timed_gpio *cur_gpio;
+ struct timed_gpio_data *gpio_data, *gpio_dat;
+ int i, ret = 0;
+
+ if (!pdata)
+ return -EBUSY;
+
+ gpio_data = kzalloc(sizeof(struct timed_gpio_data) * pdata->num_gpios, GFP_KERNEL);
+ if (!gpio_data)
+ return -ENOMEM;
+
+ for (i = 0; i < pdata->num_gpios; i++) {
+ cur_gpio = &pdata->gpios[i];
+ gpio_dat = &gpio_data[i];
+
+ hrtimer_init(&gpio_dat->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+ gpio_dat->timer.function = gpio_timer_func;
+ spin_lock_init(&gpio_dat->lock);
+
+ gpio_dat->gpio = cur_gpio->gpio;
+ gpio_dat->max_timeout = cur_gpio->max_timeout;
+ gpio_dat->active_low = cur_gpio->active_low;
+ gpio_direction_output(gpio_dat->gpio, gpio_dat->active_low);
+
+ gpio_dat->dev = device_create(timed_gpio_class, &pdev->dev, 0, "%s", cur_gpio->name);
+ if (unlikely(IS_ERR(gpio_dat->dev)))
+ return PTR_ERR(gpio_dat->dev);
+
+ dev_set_drvdata(gpio_dat->dev, gpio_dat);
+ ret = device_create_file(gpio_dat->dev, &dev_attr_enable);
+ if (ret)
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, gpio_data);
+
+ return 0;
+}
+
+static int android_timed_gpio_remove(struct platform_device *pdev)
+{
+ struct timed_gpio_platform_data *pdata = pdev->dev.platform_data;
+ struct timed_gpio_data *gpio_data = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < pdata->num_gpios; i++) {
+ device_remove_file(gpio_data[i].dev, &dev_attr_enable);
+ device_unregister(gpio_data[i].dev);
+ }
+
+ kfree(gpio_data);
+
+ return 0;
+}
+
+static struct platform_driver android_timed_gpio_driver = {
+ .probe = android_timed_gpio_probe,
+ .remove = android_timed_gpio_remove,
+ .driver = {
+ .name = "android-timed-gpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init android_timed_gpio_init(void)
+{
+ timed_gpio_class = class_create(THIS_MODULE, "timed_output");
+ if (IS_ERR(timed_gpio_class))
+ return PTR_ERR(timed_gpio_class);
+ return platform_driver_register(&android_timed_gpio_driver);
+}
+
+static void __exit android_timed_gpio_exit(void)
+{
+ class_destroy(timed_gpio_class);
+ platform_driver_unregister(&android_timed_gpio_driver);
+}
+
+module_init(android_timed_gpio_init);
+module_exit(android_timed_gpio_exit);
+
+MODULE_AUTHOR("Mike Lockwood <lockwood@android.com>");
+MODULE_DESCRIPTION("Android timed gpio driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/ar6000/ar6000/ar6000_drv.c
@@ -0,0 +1,3124 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+/*
+ * This driver is a pseudo ethernet driver to access the Atheros AR6000
+ * WLAN Device
+ */
+static const char athId[] __attribute__ ((unused)) = "$Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/ar6000_drv.c#2 $";
+
+#include "ar6000_drv.h"
+#include "htc.h"
+
+MODULE_LICENSE("GPL and additional rights");
+
+#ifndef REORG_APTC_HEURISTICS
+#undef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#endif /* REORG_APTC_HEURISTICS */
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+#define APTC_TRAFFIC_SAMPLING_INTERVAL 100 /* msec */
+#define APTC_UPPER_THROUGHPUT_THRESHOLD 3000 /* Kbps */
+#define APTC_LOWER_THROUGHPUT_THRESHOLD 2000 /* Kbps */
+
+typedef struct aptc_traffic_record {
+ A_BOOL timerScheduled;
+ struct timeval samplingTS;
+ unsigned long bytesReceived;
+ unsigned long bytesTransmitted;
+} APTC_TRAFFIC_RECORD;
+
+A_TIMER aptcTimer;
+APTC_TRAFFIC_RECORD aptcTR;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+int bmienable = 0;
+unsigned int bypasswmi = 0;
+unsigned int debuglevel = 0;
+int tspecCompliance = 1;
+unsigned int busspeedlow = 0;
+unsigned int onebitmode = 0;
+unsigned int skipflash = 0;
+unsigned int wmitimeout = 2;
+unsigned int wlanNodeCaching = 1;
+unsigned int enableuartprint = 0;
+unsigned int logWmiRawMsgs = 0;
+unsigned int enabletimerwar = 0;
+unsigned int mbox_yield_limit = 99;
+int reduce_credit_dribble = 1 + HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF;
+int allow_trace_signal = 0;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+unsigned int testmode =0;
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(bmienable, int, 0644);
+module_param(bypasswmi, int, 0644);
+module_param(debuglevel, int, 0644);
+module_param(tspecCompliance, int, 0644);
+module_param(onebitmode, int, 0644);
+module_param(busspeedlow, int, 0644);
+module_param(skipflash, int, 0644);
+module_param(wmitimeout, int, 0644);
+module_param(wlanNodeCaching, int, 0644);
+module_param(logWmiRawMsgs, int, 0644);
+module_param(enableuartprint, int, 0644);
+module_param(enabletimerwar, int, 0644);
+module_param(mbox_yield_limit, int, 0644);
+module_param(reduce_credit_dribble, int, 0644);
+module_param(allow_trace_signal, int, 0644);
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+module_param(testmode, int, 0644);
+#endif
+#else
+
+#define __user
+/* for linux 2.4 and lower */
+MODULE_PARM(bmienable,"i");
+MODULE_PARM(bypasswmi,"i");
+MODULE_PARM(debuglevel, "i");
+MODULE_PARM(onebitmode,"i");
+MODULE_PARM(busspeedlow, "i");
+MODULE_PARM(skipflash, "i");
+MODULE_PARM(wmitimeout, "i");
+MODULE_PARM(wlanNodeCaching, "i");
+MODULE_PARM(enableuartprint,"i");
+MODULE_PARM(logWmiRawMsgs, "i");
+MODULE_PARM(enabletimerwar,"i");
+MODULE_PARM(mbox_yield_limit,"i");
+MODULE_PARM(reduce_credit_dribble,"i");
+MODULE_PARM(allow_trace_signal,"i");
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+MODULE_PARM(testmode, "i");
+#endif
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10)
+/* in 2.6.10 and later this is now a pointer to a uint */
+unsigned int _mboxnum = HTC_MAILBOX_NUM_MAX;
+#define mboxnum &_mboxnum
+#else
+unsigned int mboxnum = HTC_MAILBOX_NUM_MAX;
+#endif
+
+#ifdef DEBUG
+A_UINT32 g_dbg_flags = DBG_DEFAULTS;
+unsigned int debugflags = 0;
+int debugdriver = 1;
+unsigned int debughtc = 128;
+unsigned int debugbmi = 1;
+unsigned int debughif = 2;
+unsigned int resetok = 1;
+unsigned int txcreditsavailable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditsconsumed[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenable[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int txcreditintrenableaggregate[HTC_MAILBOX_NUM_MAX] = {0};
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(debugflags, int, 0644);
+module_param(debugdriver, int, 0644);
+module_param(debughtc, int, 0644);
+module_param(debugbmi, int, 0644);
+module_param(debughif, int, 0644);
+module_param(resetok, int, 0644);
+module_param_array(txcreditsavailable, int, mboxnum, 0644);
+module_param_array(txcreditsconsumed, int, mboxnum, 0644);
+module_param_array(txcreditintrenable, int, mboxnum, 0644);
+module_param_array(txcreditintrenableaggregate, int, mboxnum, 0644);
+#else
+/* linux 2.4 and lower */
+MODULE_PARM(debugflags,"i");
+MODULE_PARM(debugdriver, "i");
+MODULE_PARM(debughtc, "i");
+MODULE_PARM(debugbmi, "i");
+MODULE_PARM(debughif, "i");
+MODULE_PARM(resetok, "i");
+MODULE_PARM(txcreditsavailable, "0-3i");
+MODULE_PARM(txcreditsconsumed, "0-3i");
+MODULE_PARM(txcreditintrenable, "0-3i");
+MODULE_PARM(txcreditintrenableaggregate, "0-3i");
+#endif
+
+#else
+unsigned int resetok = 1;
+
+#endif /* DEBUG */
+
+unsigned int tx_attempt[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_post[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int tx_complete[HTC_MAILBOX_NUM_MAX] = {0};
+unsigned int hifBusRequestNumMax = 40;
+unsigned int war23838_disabled = 0;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+unsigned int enableAPTCHeuristics = 1;
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param_array(tx_attempt, int, mboxnum, 0644);
+module_param_array(tx_post, int, mboxnum, 0644);
+module_param_array(tx_complete, int, mboxnum, 0644);
+module_param(hifBusRequestNumMax, int, 0644);
+module_param(war23838_disabled, int, 0644);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+module_param(enableAPTCHeuristics, int, 0644);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#else
+MODULE_PARM(tx_attempt, "0-3i");
+MODULE_PARM(tx_post, "0-3i");
+MODULE_PARM(tx_complete, "0-3i");
+MODULE_PARM(hifBusRequestNumMax, "i");
+MODULE_PARM(war23838_disabled, "i");
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+MODULE_PARM(enableAPTCHeuristics, "i");
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+#endif
+
+#ifdef BLOCK_TX_PATH_FLAG
+int blocktx = 0;
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+module_param(blocktx, int, 0644);
+#else
+MODULE_PARM(blocktx, "i");
+#endif
+#endif /* BLOCK_TX_PATH_FLAG */
+
+// TODO move to arsoft_c
+USER_RSSI_THOLD rssi_map[12];
+
+int reconnect_flag = 0;
+
+DECLARE_WAIT_QUEUE_HEAD(ar6000_scan_queue);
+
+/* Function declarations */
+static int ar6000_init_module(void);
+static void ar6000_cleanup_module(void);
+
+int ar6000_init(struct net_device *dev);
+static int ar6000_open(struct net_device *dev);
+static int ar6000_close(struct net_device *dev);
+static void ar6000_init_control_info(AR_SOFTC_T *ar);
+static int ar6000_data_tx(struct sk_buff *skb, struct net_device *dev);
+
+static void ar6000_destroy(struct net_device *dev, unsigned int unregister);
+static void ar6000_detect_error(unsigned long ptr);
+static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
+static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
+
+/*
+ * HTC service connection handlers
+ */
+static void ar6000_avail_ev(HTC_HANDLE HTCHandle);
+
+static void ar6000_unavail_ev(void *Instance);
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status);
+
+static void ar6000_rx(void *Context, HTC_PACKET *pPacket);
+
+static void ar6000_rx_refill(void *Context,HTC_ENDPOINT_ID Endpoint);
+
+static void ar6000_tx_complete(void *Context, HTC_PACKET *pPacket);
+
+static void ar6000_tx_queue_full(void *Context, HTC_ENDPOINT_ID Endpoint);
+
+/*
+ * Static variables
+ */
+
+static struct net_device *ar6000_devices[MAX_AR6000];
+extern struct iw_handler_def ath_iw_handler_def;
+DECLARE_WAIT_QUEUE_HEAD(arEvent);
+static void ar6000_cookie_init(AR_SOFTC_T *ar);
+static void ar6000_cookie_cleanup(AR_SOFTC_T *ar);
+static void ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie);
+static struct ar_cookie *ar6000_alloc_cookie(AR_SOFTC_T *ar);
+static void ar6000_TxDataCleanup(AR_SOFTC_T *ar);
+
+#ifdef USER_KEYS
+static A_STATUS ar6000_reinstall_keys(AR_SOFTC_T *ar,A_UINT8 key_op_ctrl);
+#endif
+
+
+static struct ar_cookie s_ar_cookie_mem[MAX_COOKIE_NUM];
+
+#define HOST_INTEREST_ITEM_ADDRESS(ar, item) \
+((ar->arTargetType == TARGET_TYPE_AR6001) ? \
+ AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+
+/* Debug log support */
+
+/*
+ * Flag to govern whether the debug logs should be parsed in the kernel
+ * or reported to the application.
+ */
+#ifdef DEBUG
+#define REPORT_DEBUG_LOGS_TO_APP
+#endif
+
+A_STATUS
+ar6000_set_host_app_area(AR_SOFTC_T *ar)
+{
+ A_UINT32 address, data;
+ struct host_app_area_s host_app_area;
+
+ /* Fetch the address of the host_app_area_s instance in the host interest area */
+ address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_app_host_interest);
+ if (ar6000_ReadRegDiag(ar->arHifDevice, &address, &data) != A_OK) {
+ return A_ERROR;
+ }
+ address = data;
+ host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
+ if (ar6000_WriteDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&host_app_area,
+ sizeof(struct host_app_area_s)) != A_OK)
+ {
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+
+A_UINT32
+dbglog_get_debug_hdr_ptr(AR_SOFTC_T *ar)
+{
+ A_UINT32 param;
+ A_UINT32 address;
+ A_STATUS status;
+
+ address = HOST_INTEREST_ITEM_ADDRESS(ar, hi_dbglog_hdr);
+ if ((status = ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&param, 4)) != A_OK)
+ {
+ param = 0;
+ }
+
+ return param;
+}
+
+/*
+ * The dbglog module has been initialized. Its ok to access the relevant
+ * data stuctures over the diagnostic window.
+ */
+void
+ar6000_dbglog_init_done(AR_SOFTC_T *ar)
+{
+ ar->dbglog_init_done = TRUE;
+}
+
+A_UINT32
+dbglog_get_debug_fragment(A_INT8 *datap, A_UINT32 len, A_UINT32 limit)
+{
+ A_INT32 *buffer;
+ A_UINT32 count;
+ A_UINT32 numargs;
+ A_UINT32 length;
+ A_UINT32 fraglen;
+
+ count = fraglen = 0;
+ buffer = (A_INT32 *)datap;
+ length = (limit >> 2);
+
+ if (len <= limit) {
+ fraglen = len;
+ } else {
+ while (count < length) {
+ numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+ fraglen = (count << 2);
+ count += numargs + 1;
+ }
+ }
+
+ return fraglen;
+}
+
+void
+dbglog_parse_debug_logs(A_INT8 *datap, A_UINT32 len)
+{
+ A_INT32 *buffer;
+ A_UINT32 count;
+ A_UINT32 timestamp;
+ A_UINT32 debugid;
+ A_UINT32 moduleid;
+ A_UINT32 numargs;
+ A_UINT32 length;
+
+ count = 0;
+ buffer = (A_INT32 *)datap;
+ length = (len >> 2);
+ while (count < length) {
+ debugid = DBGLOG_GET_DBGID(buffer[count]);
+ moduleid = DBGLOG_GET_MODULEID(buffer[count]);
+ numargs = DBGLOG_GET_NUMARGS(buffer[count]);
+ timestamp = DBGLOG_GET_TIMESTAMP(buffer[count]);
+ switch (numargs) {
+ case 0:
+ AR_DEBUG_PRINTF("%d %d (%d)\n", moduleid, debugid, timestamp);
+ break;
+
+ case 1:
+ AR_DEBUG_PRINTF("%d %d (%d): 0x%x\n", moduleid, debugid,
+ timestamp, buffer[count+1]);
+ break;
+
+ case 2:
+ AR_DEBUG_PRINTF("%d %d (%d): 0x%x, 0x%x\n", moduleid, debugid,
+ timestamp, buffer[count+1], buffer[count+2]);
+ break;
+
+ default:
+ AR_DEBUG_PRINTF("Invalid args: %d\n", numargs);
+ }
+ count += numargs + 1;
+ }
+}
+
+int
+ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar)
+{
+ struct dbglog_hdr_s debug_hdr;
+ struct dbglog_buf_s debug_buf;
+ A_UINT32 address;
+ A_UINT32 length;
+ A_UINT32 dropped;
+ A_UINT32 firstbuf;
+ A_UINT32 debug_hdr_ptr;
+
+ if (!ar->dbglog_init_done) return A_ERROR;
+
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if (ar->dbgLogFetchInProgress) {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ return A_EBUSY;
+ }
+
+ /* block out others */
+ ar->dbgLogFetchInProgress = TRUE;
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ debug_hdr_ptr = dbglog_get_debug_hdr_ptr(ar);
+ printk("debug_hdr_ptr: 0x%x\n", debug_hdr_ptr);
+
+ /* Get the contents of the ring buffer */
+ if (debug_hdr_ptr) {
+ address = debug_hdr_ptr;
+ length = sizeof(struct dbglog_hdr_s);
+ ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&debug_hdr, length);
+ address = (A_UINT32)debug_hdr.dbuf;
+ firstbuf = address;
+ dropped = debug_hdr.dropped;
+ length = sizeof(struct dbglog_buf_s);
+ ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&debug_buf, length);
+
+ do {
+ address = (A_UINT32)debug_buf.buffer;
+ length = debug_buf.length;
+ if ((length) && (debug_buf.length <= debug_buf.bufsize)) {
+ /* Rewind the index if it is about to overrun the buffer */
+ if (ar->log_cnt > (DBGLOG_HOST_LOG_BUFFER_SIZE - length)) {
+ ar->log_cnt = 0;
+ }
+ if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&ar->log_buffer[ar->log_cnt], length))
+ {
+ break;
+ }
+ ar6000_dbglog_event(ar, dropped, &ar->log_buffer[ar->log_cnt], length);
+ ar->log_cnt += length;
+ } else {
+ AR_DEBUG_PRINTF("Length: %d (Total size: %d)\n",
+ debug_buf.length, debug_buf.bufsize);
+ }
+
+ address = (A_UINT32)debug_buf.next;
+ length = sizeof(struct dbglog_buf_s);
+ if(A_OK != ar6000_ReadDataDiag(ar->arHifDevice, address,
+ (A_UCHAR *)&debug_buf, length))
+ {
+ break;
+ }
+
+ } while (address != firstbuf);
+ }
+
+ ar->dbgLogFetchInProgress = FALSE;
+
+ return A_OK;
+}
+
+void
+ar6000_dbglog_event(AR_SOFTC_T *ar, A_UINT32 dropped,
+ A_INT8 *buffer, A_UINT32 length)
+{
+#ifdef REPORT_DEBUG_LOGS_TO_APP
+ #define MAX_WIRELESS_EVENT_SIZE 252
+ /*
+ * Break it up into chunks of MAX_WIRELESS_EVENT_SIZE bytes of messages.
+ * There seems to be a limitation on the length of message that could be
+ * transmitted to the user app via this mechanism.
+ */
+ A_UINT32 send, sent;
+
+ sent = 0;
+ send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+ MAX_WIRELESS_EVENT_SIZE);
+ while (send) {
+ ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, &buffer[sent], send);
+ sent += send;
+ send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
+ MAX_WIRELESS_EVENT_SIZE);
+ }
+#else
+ AR_DEBUG_PRINTF("Dropped logs: 0x%x\nDebug info length: %d\n",
+ dropped, length);
+
+ /* Interpret the debug logs */
+ dbglog_parse_debug_logs(buffer, length);
+#endif /* REPORT_DEBUG_LOGS_TO_APP */
+}
+
+
+
+static int __init
+ar6000_init_module(void)
+{
+ static int probed = 0;
+ A_STATUS status;
+ HTC_INIT_INFO initInfo;
+
+ A_MEMZERO(&initInfo,sizeof(initInfo));
+ initInfo.AddInstance = ar6000_avail_ev;
+ initInfo.DeleteInstance = ar6000_unavail_ev;
+ initInfo.TargetFailure = ar6000_target_failure;
+
+
+#ifdef DEBUG
+ /* Set the debug flags if specified at load time */
+ if(debugflags != 0)
+ {
+ g_dbg_flags = debugflags;
+ }
+#endif
+
+ if (probed) {
+ return -ENODEV;
+ }
+ probed++;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+ ar6000_gpio_init();
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+ status = HTCInit(&initInfo);
+ if(status != A_OK)
+ return -ENODEV;
+
+ return 0;
+}
+
+static void __exit
+ar6000_cleanup_module(void)
+{
+ int i = 0;
+ struct net_device *ar6000_netdev;
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ /* Delete the Adaptive Power Control timer */
+ if (timer_pending(&aptcTimer)) {
+ del_timer_sync(&aptcTimer);
+ }
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+ for (i=0; i < MAX_AR6000; i++) {
+ if (ar6000_devices[i] != NULL) {
+ ar6000_netdev = ar6000_devices[i];
+ ar6000_devices[i] = NULL;
+ ar6000_destroy(ar6000_netdev, 1);
+ }
+ }
+
+ /* shutting down HTC will cause the HIF layer to detach from the
+ * underlying bus driver which will cause the subsequent deletion of
+ * all HIF and HTC instances */
+ HTCShutDown();
+
+ AR_DEBUG_PRINTF("ar6000_cleanup: success\n");
+}
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+void
+aptcTimerHandler(unsigned long arg)
+{
+ A_UINT32 numbytes;
+ A_UINT32 throughput;
+ AR_SOFTC_T *ar;
+ A_STATUS status;
+
+ ar = (AR_SOFTC_T *)arg;
+ A_ASSERT(ar != NULL);
+ A_ASSERT(!timer_pending(&aptcTimer));
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ /* Get the number of bytes transferred */
+ numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+ aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+
+ /* Calculate and decide based on throughput thresholds */
+ throughput = ((numbytes * 8)/APTC_TRAFFIC_SAMPLING_INTERVAL); /* Kbps */
+ if (throughput < APTC_LOWER_THROUGHPUT_THRESHOLD) {
+ /* Enable Sleep and delete the timer */
+ A_ASSERT(ar->arWmiReady == TRUE);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ status = wmi_powermode_cmd(ar->arWmi, REC_POWER);
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ A_ASSERT(status == A_OK);
+ aptcTR.timerScheduled = FALSE;
+ } else {
+ A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+
+
+/* set HTC block size, assume BMI is already initialized */
+A_STATUS ar6000_SetHTCBlockSize(AR_SOFTC_T *ar)
+{
+ A_STATUS status;
+ A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
+
+ do {
+ /* get the block sizes */
+ status = HIFConfigureDevice(ar->arHifDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ blocksizes, sizeof(blocksizes));
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF("Failed to get block size info from HIF layer...\n");
+ break;
+ }
+ /* note: we actually get the block size for mailbox 1, for SDIO the block
+ * size on mailbox 0 is artificially set to 1 */
+ /* must be a power of 2 */
+ A_ASSERT((blocksizes[1] & (blocksizes[1] - 1)) == 0);
+
+ /* set the host interest area for the block size */
+ status = BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_io_block_sz),
+ (A_UCHAR *)&blocksizes[1],
+ 4);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF("BMIWriteMemory for IO block size failed \n");
+ break;
+ }
+
+ AR_DEBUG_PRINTF("Block Size Set: %d (target address:0x%X)\n",
+ blocksizes[1], HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_io_block_sz));
+
+ /* set the host interest area for the mbox ISR yield limit */
+ status = BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_mbox_isr_yield_limit),
+ (A_UCHAR *)&mbox_yield_limit,
+ 4);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF("BMIWriteMemory for yield limit failed \n");
+ break;
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+static void free_raw_buffers(AR_SOFTC_T *ar)
+{
+ int i, j;
+
+ for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) {
+ for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++)
+ kfree(ar->raw_htc_read_buffer[i][j]);
+ for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++)
+ kfree(ar->raw_htc_write_buffer[i][j]);
+ }
+}
+
+static int alloc_raw_buffers(AR_SOFTC_T *ar)
+{
+ int i, j;
+ raw_htc_buffer *b;
+
+ for (i = 0; i != HTC_RAW_STREAM_NUM_MAX; i++) {
+ for (j = 0; j != RAW_HTC_READ_BUFFERS_NUM; j++) {
+ b = kzalloc(sizeof(*b), GFP_KERNEL);
+ if (!b)
+ return -ENOMEM;
+ ar->raw_htc_read_buffer[i][j] = b;
+ }
+ for (j = 0; j != RAW_HTC_WRITE_BUFFERS_NUM; j++) {
+ b = kzalloc(sizeof(*b), GFP_KERNEL);
+ if (!b)
+ return -ENOMEM;
+ ar->raw_htc_write_buffer[i][j] = b;
+ }
+ }
+ return 0;
+}
+
+/*
+ * HTC Event handlers
+ */
+static void
+ar6000_avail_ev(HTC_HANDLE HTCHandle)
+{
+ int i;
+ struct net_device *dev;
+ AR_SOFTC_T *ar;
+ int device_index = 0;
+
+ AR_DEBUG_PRINTF("ar6000_available\n");
+
+ for (i=0; i < MAX_AR6000; i++) {
+ if (ar6000_devices[i] == NULL) {
+ break;
+ }
+ }
+
+ if (i == MAX_AR6000) {
+ AR_DEBUG_PRINTF("ar6000_available: max devices reached\n");
+ return;
+ }
+
+ /* Save this. It gives a bit better readability especially since */
+ /* we use another local "i" variable below. */
+ device_index = i;
+
+ A_ASSERT(HTCHandle != NULL);
+
+ dev = alloc_etherdev(sizeof(AR_SOFTC_T));
+ if (dev == NULL) {
+ AR_DEBUG_PRINTF("ar6000_available: can't alloc etherdev\n");
+ return;
+ }
+
+ ether_setup(dev);
+
+ if (dev->priv == NULL) {
+ printk(KERN_CRIT "ar6000_available: Could not allocate memory\n");
+ return;
+ }
+
+ A_MEMZERO(dev->priv, sizeof(AR_SOFTC_T));
+
+ ar = (AR_SOFTC_T *)dev->priv;
+ ar->arNetDev = dev;
+ ar->arHtcTarget = HTCHandle;
+ ar->arHifDevice = HTCGetHifDevice(HTCHandle);
+ ar->arWlanState = WLAN_ENABLED;
+ ar->arRadioSwitch = WLAN_ENABLED;
+ ar->arDeviceIndex = device_index;
+
+ A_INIT_TIMER(&ar->arHBChallengeResp.timer, ar6000_detect_error, dev);
+ ar->arHBChallengeResp.seqNum = 0;
+ ar->arHBChallengeResp.outstanding = FALSE;
+ ar->arHBChallengeResp.missCnt = 0;
+ ar->arHBChallengeResp.frequency = AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT;
+ ar->arHBChallengeResp.missThres = AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT;
+
+ ar6000_init_control_info(ar);
+ init_waitqueue_head(&arEvent);
+ sema_init(&ar->arSem, 1);
+
+ if (alloc_raw_buffers(ar)) {
+ free_raw_buffers(ar);
+ /*
+ * @@@ Clean up our own mess, but for anything else, cheerfully mimick
+ * the beautiful error non-handling of the rest of this function.
+ */
+ return;
+ }
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ A_INIT_TIMER(&aptcTimer, aptcTimerHandler, ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+ /*
+ * If requested, perform some magic which requires no cooperation from
+ * the Target. It causes the Target to ignore flash and execute to the
+ * OS from ROM.
+ *
+ * This is intended to support recovery from a corrupted flash on Targets
+ * that support flash.
+ */
+ if (skipflash)
+ {
+ ar6000_reset_device_skipflash(ar->arHifDevice);
+ }
+
+ BMIInit();
+ {
+ struct bmi_target_info targ_info;
+
+ if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != A_OK) {
+ return;
+ }
+
+ ar->arVersion.target_ver = targ_info.target_ver;
+ ar->arTargetType = targ_info.target_type;
+ }
+
+ if (enableuartprint) {
+ A_UINT32 param;
+ param = 1;
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_serial_enable),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF("BMIWriteMemory for enableuartprint failed \n");
+ return ;
+ }
+ AR_DEBUG_PRINTF("Serial console prints enabled\n");
+ }
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ if(testmode) {
+ ar->arTargetMode = AR6000_TCMD_MODE;
+ }else {
+ ar->arTargetMode = AR6000_WLAN_MODE;
+ }
+#endif
+ if (enabletimerwar) {
+ A_UINT32 param;
+
+ if (BMIReadMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4)!= A_OK)
+ {
+ AR_DEBUG_PRINTF("BMIReadMemory for enabletimerwar failed \n");
+ return;
+ }
+
+ param |= HI_OPTION_TIMER_WAR;
+
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
+ (A_UCHAR *)&param,
+ 4) != A_OK)
+ {
+ AR_DEBUG_PRINTF("BMIWriteMemory for enabletimerwar failed \n");
+ return;
+ }
+ AR_DEBUG_PRINTF("Timer WAR enabled\n");
+ }
+
+
+ /* since BMIInit is called in the driver layer, we have to set the block
+ * size here for the target */
+
+ if (A_FAILED(ar6000_SetHTCBlockSize(ar))) {
+ return;
+ }
+
+ spin_lock_init(&ar->arLock);
+
+ /* Don't install the init function if BMI is requested */
+ if(!bmienable)
+ {
+ dev->init = ar6000_init;
+ } else {
+ AR_DEBUG_PRINTF(" BMI enabled \n");
+ }
+
+ dev->open = &ar6000_open;
+ dev->stop = &ar6000_close;
+ dev->hard_start_xmit = &ar6000_data_tx;
+ dev->get_stats = &ar6000_get_stats;
+
+ /* dev->tx_timeout = ar6000_tx_timeout; */
+ dev->do_ioctl = &ar6000_ioctl;
+ dev->watchdog_timeo = AR6000_TX_TIMEOUT;
+ ar6000_ioctl_iwsetup(&ath_iw_handler_def);
+ dev->wireless_handlers = &ath_iw_handler_def;
+ ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
+
+ /*
+ * We need the OS to provide us with more headroom in order to
+ * perform dix to 802.3, WMI header encap, and the HTC header
+ */
+ dev->hard_header_len = ETH_HLEN + sizeof(ATH_LLC_SNAP_HDR) +
+ sizeof(WMI_DATA_HDR) + HTC_HEADER_LEN;
+
+ /* This runs the init function */
+ SET_NETDEV_DEV(dev, HIFGetOSDevice(ar->arHifDevice));
+ if (register_netdev(dev)) {
+ AR_DEBUG_PRINTF("ar6000_avail: register_netdev failed\n");
+ ar6000_destroy(dev, 0);
+ return;
+ }
+
+ HTCSetInstance(ar->arHtcTarget, ar);
+
+ /* We only register the device in the global list if we succeed. */
+ /* If the device is in the global list, it will be destroyed */
+ /* when the module is unloaded. */
+ ar6000_devices[device_index] = dev;
+
+ AR_DEBUG_PRINTF("ar6000_avail: name=%s htcTarget=0x%x, dev=0x%x (%d), ar=0x%x\n",
+ dev->name, (A_UINT32)HTCHandle, (A_UINT32)dev, device_index,
+ (A_UINT32)ar);
+}
+
+static void ar6000_target_failure(void *Instance, A_STATUS Status)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
+ WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+ static A_BOOL sip = FALSE;
+
+ if (Status != A_OK) {
+ if (timer_pending(&ar->arHBChallengeResp.timer)) {
+ A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+ }
+
+ /* try dumping target assertion information (if any) */
+ ar6000_dump_target_assert_info(ar->arHifDevice,ar->arTargetType);
+
+ /*
+ * Fetch the logs from the target via the diagnostic
+ * window.
+ */
+ ar6000_dbglog_get_debug_logs(ar);
+
+ /* Report the error only once */
+ if (!sip) {
+ sip = TRUE;
+ errEvent.errorVal = WMI_TARGET_COM_ERR |
+ WMI_TARGET_FATAL_ERR;
+#ifdef SEND_EVENT_TO_APP
+ ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+ (A_UINT8 *)&errEvent,
+ sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+#endif
+ }
+ }
+}
+
+static void
+ar6000_unavail_ev(void *Instance)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Instance;
+ /* NULL out it's entry in the global list */
+ ar6000_devices[ar->arDeviceIndex] = NULL;
+ ar6000_destroy(ar->arNetDev, 1);
+}
+
+/*
+ * We need to differentiate between the surprise and planned removal of the
+ * device because of the following consideration:
+ * - In case of surprise removal, the hcd already frees up the pending
+ * for the device and hence there is no need to unregister the function
+ * driver inorder to get these requests. For planned removal, the function
+ * driver has to explictly unregister itself to have the hcd return all the
+ * pending requests before the data structures for the devices are freed up.
+ * Note that as per the current implementation, the function driver will
+ * end up releasing all the devices since there is no API to selectively
+ * release a particular device.
+ * - Certain commands issued to the target can be skipped for surprise
+ * removal since they will anyway not go through.
+ */
+static void
+ar6000_destroy(struct net_device *dev, unsigned int unregister)
+{
+ AR_SOFTC_T *ar;
+
+ AR_DEBUG_PRINTF("+ar6000_destroy \n");
+
+ if((dev == NULL) || ((ar = netdev_priv(dev)) == NULL))
+ {
+ AR_DEBUG_PRINTF("%s(): Failed to get device structure.\n", __func__);
+ return;
+ }
+
+ /* Stop the transmit queues */
+ netif_stop_queue(dev);
+
+ /* Disable the target and the interrupts associated with it */
+ if (ar->arWmiReady == TRUE)
+ {
+ if (!bypasswmi)
+ {
+ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE)
+ {
+ AR_DEBUG_PRINTF("%s(): Disconnect\n", __func__);
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar6000_init_profile_info(ar);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ wmi_disconnect_cmd(ar->arWmi);
+ }
+
+ ar6000_dbglog_get_debug_logs(ar);
+ ar->arWmiReady = FALSE;
+ ar->arConnected = FALSE;
+ ar->arConnectPending = FALSE;
+ wmi_shutdown(ar->arWmi);
+ ar->arWmiEnabled = FALSE;
+ ar->arWmi = NULL;
+ ar->arWlanState = WLAN_ENABLED;
+#ifdef USER_KEYS
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+ ar->user_key_ctrl = 0;
+#endif
+ }
+
+ AR_DEBUG_PRINTF("%s(): WMI stopped\n", __func__);
+ }
+ else
+ {
+ AR_DEBUG_PRINTF("%s(): WMI not ready 0x%08x 0x%08x\n",
+ __func__, (unsigned int) ar, (unsigned int) ar->arWmi);
+
+ /* Shut down WMI if we have started it */
+ if(ar->arWmiEnabled == TRUE)
+ {
+ AR_DEBUG_PRINTF("%s(): Shut down WMI\n", __func__);
+ wmi_shutdown(ar->arWmi);
+ ar->arWmiEnabled = FALSE;
+ ar->arWmi = NULL;
+ }
+ }
+
+ /* stop HTC */
+ HTCStop(ar->arHtcTarget);
+
+ /* set the instance to NULL so we do not get called back on remove incase we
+ * we're explicity destroyed by module unload */
+ HTCSetInstance(ar->arHtcTarget, NULL);
+
+ if (resetok) {
+ /* try to reset the device if we can
+ * The driver may have been configure NOT to reset the target during
+ * a debug session */
+ AR_DEBUG_PRINTF(" Attempting to reset target on instance destroy.... \n");
+ ar6000_reset_device(ar->arHifDevice, ar->arTargetType);
+ } else {
+ AR_DEBUG_PRINTF(" Host does not want target reset. \n");
+ }
+
+ /* Done with cookies */
+ ar6000_cookie_cleanup(ar);
+
+ /* Cleanup BMI */
+ BMIInit();
+
+ /* Clear the tx counters */
+ memset(tx_attempt, 0, sizeof(tx_attempt));
+ memset(tx_post, 0, sizeof(tx_post));
+ memset(tx_complete, 0, sizeof(tx_complete));
+
+
+ /* Free up the device data structure */
+ if (unregister)
+ unregister_netdev(dev);
+
+ free_raw_buffers(ar);
+
+#ifndef free_netdev
+ kfree(dev);
+#else
+ free_netdev(dev);
+#endif
+
+ AR_DEBUG_PRINTF("-ar6000_destroy \n");
+}
+
+static void ar6000_detect_error(unsigned long ptr)
+{
+ struct net_device *dev = (struct net_device *)ptr;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_TARGET_ERROR_REPORT_EVENT errEvent;
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if (ar->arHBChallengeResp.outstanding) {
+ ar->arHBChallengeResp.missCnt++;
+ } else {
+ ar->arHBChallengeResp.missCnt = 0;
+ }
+
+ if (ar->arHBChallengeResp.missCnt > ar->arHBChallengeResp.missThres) {
+ /* Send Error Detect event to the application layer and do not reschedule the error detection module timer */
+ ar->arHBChallengeResp.missCnt = 0;
+ ar->arHBChallengeResp.seqNum = 0;
+ errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+#ifdef SEND_EVENT_TO_APP
+ ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
+ (A_UINT8 *)&errEvent,
+ sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
+#endif
+ return;
+ }
+
+ /* Generate the sequence number for the next challenge */
+ ar->arHBChallengeResp.seqNum++;
+ ar->arHBChallengeResp.outstanding = TRUE;
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ /* Send the challenge on the control channel */
+ if (wmi_get_challenge_resp_cmd(ar->arWmi, ar->arHBChallengeResp.seqNum, DRV_HB_CHALLENGE) != A_OK) {
+ AR_DEBUG_PRINTF("Unable to send heart beat challenge\n");
+ }
+
+
+ /* Reschedule the timer for the next challenge */
+ A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+}
+
+void ar6000_init_profile_info(AR_SOFTC_T *ar)
+{
+ ar->arSsidLen = 0;
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arNetworkType = INFRA_NETWORK;
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arAuthMode = NONE_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arPairwiseCryptoLen = 0;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arGroupCryptoLen = 0;
+ A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+ ar->arBssChannel = 0;
+}
+
+static void
+ar6000_init_control_info(AR_SOFTC_T *ar)
+{
+ ar->arWmiEnabled = FALSE;
+ ar6000_init_profile_info(ar);
+ ar->arDefTxKeyIndex = 0;
+ A_MEMZERO(ar->arWepKeyList, sizeof(ar->arWepKeyList));
+ ar->arChannelHint = 0;
+ ar->arListenInterval = MAX_LISTEN_INTERVAL;
+ ar->arVersion.host_ver = AR6K_SW_VERSION;
+ ar->arRssi = 0;
+ ar->arTxPwr = 0;
+ ar->arTxPwrSet = FALSE;
+ ar->arSkipScan = 0;
+ ar->arBeaconInterval = 0;
+ ar->arBitRate = 0;
+ ar->arMaxRetries = 0;
+ ar->arWmmEnabled = TRUE;
+}
+
+static int
+ar6000_open(struct net_device *dev)
+{
+ /* Wake up the queues */
+ netif_wake_queue(dev);
+
+ return 0;
+}
+
+static int
+ar6000_close(struct net_device *dev)
+{
+ netif_stop_queue(dev);
+
+ return 0;
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connectservice(AR_SOFTC_T *ar,
+ HTC_SERVICE_CONNECT_REQ *pConnect,
+ WMI_PRI_STREAM_ID WmiStreamID,
+ char *pDesc)
+{
+ A_STATUS status;
+ HTC_SERVICE_CONNECT_RESP response;
+
+ do {
+
+ A_MEMZERO(&response,sizeof(response));
+
+ status = HTCConnectService(ar->arHtcTarget,
+ pConnect,
+ &response);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(" Failed to connect to %s service status:%d \n", pDesc, status);
+ break;
+ }
+
+ if (WmiStreamID == WMI_NOT_MAPPED) {
+ /* done */
+ break;
+ }
+
+ /* set endpoint mapping for the WMI stream in the driver layer */
+ arSetWMIStream2EndpointIDMap(ar,WmiStreamID,response.Endpoint);
+
+ } while (FALSE);
+
+ return status;
+}
+
+static void ar6000_TxDataCleanup(AR_SOFTC_T *ar)
+{
+ /* flush all the data (non-control) streams
+ * we only flush packets that are tagged as data, we leave any control packets that
+ * were in the TX queues alone */
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI),
+ AR6K_DATA_PKT_TAG);
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arWMIStream2EndpointID(ar,WMI_LOW_PRI),
+ AR6K_DATA_PKT_TAG);
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arWMIStream2EndpointID(ar,WMI_HIGH_PRI),
+ AR6K_DATA_PKT_TAG);
+ HTCFlushEndpoint(ar->arHtcTarget,
+ arWMIStream2EndpointID(ar,WMI_HIGHEST_PRI),
+ AR6K_DATA_PKT_TAG);
+}
+
+/* This function does one time initialization for the lifetime of the device */
+int ar6000_init(struct net_device *dev)
+{
+ AR_SOFTC_T *ar;
+ A_STATUS status;
+ A_INT32 timeleft;
+
+ if((ar = netdev_priv(dev)) == NULL)
+ {
+ return(-EIO);
+ }
+
+ /* Do we need to finish the BMI phase */
+ if(BMIDone(ar->arHifDevice) != A_OK)
+ {
+ return -EIO;
+ }
+
+ if (!bypasswmi)
+ {
+#if 0 /* TBDXXX */
+ if (ar->arVersion.host_ver != ar->arVersion.target_ver) {
+ A_PRINTF("WARNING: Host version 0x%x does not match Target "
+ " version 0x%x!\n",
+ ar->arVersion.host_ver, ar->arVersion.target_ver);
+ }
+#endif
+
+ /* Indicate that WMI is enabled (although not ready yet) */
+ ar->arWmiEnabled = TRUE;
+ if ((ar->arWmi = wmi_init((void *) ar)) == NULL)
+ {
+ AR_DEBUG_PRINTF("%s() Failed to initialize WMI.\n", __func__);
+ return(-EIO);
+ }
+
+ AR_DEBUG_PRINTF("%s() Got WMI @ 0x%08x.\n", __func__,
+ (unsigned int) ar->arWmi);
+ }
+
+ do {
+ HTC_SERVICE_CONNECT_REQ connect;
+
+ /* the reason we have to wait for the target here is that the driver layer
+ * has to init BMI in order to set the host block size,
+ */
+ status = HTCWaitTarget(ar->arHtcTarget);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ A_MEMZERO(&connect,sizeof(connect));
+ /* meta data is unused for now */
+ connect.pMetaData = NULL;
+ connect.MetaDataLength = 0;
+ /* these fields are the same for all service endpoints */
+ connect.EpCallbacks.pContext = ar;
+ connect.EpCallbacks.EpTxComplete = ar6000_tx_complete;
+ connect.EpCallbacks.EpRecv = ar6000_rx;
+ connect.EpCallbacks.EpRecvRefill = ar6000_rx_refill;
+ connect.EpCallbacks.EpSendFull = ar6000_tx_queue_full;
+ /* set the max queue depth so that our ar6000_tx_queue_full handler gets called.
+ * Linux has the peculiarity of not providing flow control between the
+ * NIC and the network stack. There is no API to indicate that a TX packet
+ * was sent which could provide some back pressure to the network stack.
+ * Under linux you would have to wait till the network stack consumed all sk_buffs
+ * before any back-flow kicked in. Which isn't very friendly.
+ * So we have to manage this ourselves */
+ connect.MaxSendQueueDepth = 32;
+
+ /* connect to control service */
+ connect.ServiceID = WMI_CONTROL_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ WMI_CONTROL_PRI,
+ "WMI CONTROL");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* for the remaining data services set the connection flag to reduce dribbling,
+ * if configured to do so */
+ if (reduce_credit_dribble) {
+ connect.ConnectionFlags |= HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE;
+ /* the credit dribble trigger threshold is (reduce_credit_dribble - 1) for a value
+ * of 0-3 */
+ connect.ConnectionFlags &= ~HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+ connect.ConnectionFlags |=
+ ((A_UINT16)reduce_credit_dribble - 1) & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK;
+ }
+ /* connect to best-effort service */
+ connect.ServiceID = WMI_DATA_BE_SVC;
+
+ status = ar6000_connectservice(ar,
+ &connect,
+ WMI_BEST_EFFORT_PRI,
+ "WMI DATA BE");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* connect to back-ground
+ * map this to WMI LOW_PRI */
+ connect.ServiceID = WMI_DATA_BK_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ WMI_LOW_PRI,
+ "WMI DATA BK");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* connect to Video service, map this to
+ * to HI PRI */
+ connect.ServiceID = WMI_DATA_VI_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ WMI_HIGH_PRI,
+ "WMI DATA VI");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* connect to VO service, this is currently not
+ * mapped to a WMI priority stream due to historical reasons.
+ * WMI originally defined 3 priorities over 3 mailboxes
+ * We can change this when WMI is reworked so that priorities are not
+ * dependent on mailboxes */
+ connect.ServiceID = WMI_DATA_VO_SVC;
+ status = ar6000_connectservice(ar,
+ &connect,
+ WMI_HIGHEST_PRI,
+ "WMI DATA VO");
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ A_ASSERT(arWMIStream2EndpointID(ar,WMI_CONTROL_PRI) != 0);
+ A_ASSERT(arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI) != 0);
+ A_ASSERT(arWMIStream2EndpointID(ar,WMI_LOW_PRI) != 0);
+ A_ASSERT(arWMIStream2EndpointID(ar,WMI_HIGH_PRI) != 0);
+ A_ASSERT(arWMIStream2EndpointID(ar,WMI_HIGHEST_PRI) != 0);
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ return (-EIO);
+ }
+
+ /*
+ * give our connected endpoints some buffers
+ */
+ ar6000_rx_refill(ar, arWMIStream2EndpointID(ar,WMI_CONTROL_PRI));
+
+ ar6000_rx_refill(ar, arWMIStream2EndpointID(ar,WMI_BEST_EFFORT_PRI));
+
+ /*
+ * We will post the receive buffers only for SPE testing and so we are
+ * making it conditional on the 'bypasswmi' flag.
+ */
+ if (bypasswmi) {
+ ar6000_rx_refill(ar,arWMIStream2EndpointID(ar,WMI_LOW_PRI));
+ ar6000_rx_refill(ar,arWMIStream2EndpointID(ar,WMI_HIGH_PRI));
+ }
+
+ /* setup credit distribution */
+ ar6000_setup_credit_dist(ar->arHtcTarget, &ar->arCreditStateInfo);
+
+ /* Since cookies are used for HTC transports, they should be */
+ /* initialized prior to enabling HTC. */
+ ar6000_cookie_init(ar);
+
+ /* start HTC */
+ status = HTCStart(ar->arHtcTarget);
+
+ if (status != A_OK) {
+ if (ar->arWmiEnabled == TRUE) {
+ wmi_shutdown(ar->arWmi);
+ ar->arWmiEnabled = FALSE;
+ ar->arWmi = NULL;
+ }
+ ar6000_cookie_cleanup(ar);
+ return -EIO;
+ }
+
+ if (!bypasswmi) {
+ /* Wait for Wmi event to be ready */
+ timeleft = wait_event_interruptible_timeout(arEvent,
+ (ar->arWmiReady == TRUE), wmitimeout * HZ);
+
+ if(!timeleft || signal_pending(current))
+ {
+ AR_DEBUG_PRINTF("WMI is not ready or wait was interrupted\n");
+#if defined(DWSIM) /* TBDXXX */
+ AR_DEBUG_PRINTF(".....but proceed anyway.\n");
+#else
+ return -EIO;
+#endif
+ }
+
+ AR_DEBUG_PRINTF("%s() WMI is ready\n", __func__);
+
+ /* Communicate the wmi protocol verision to the target */
+ if ((ar6000_set_host_app_area(ar)) != A_OK) {
+ AR_DEBUG_PRINTF("Unable to set the host app area\n");
+ }
+ }
+
+ ar->arNumDataEndPts = 1;
+
+ return(0);
+}
+
+
+void
+ar6000_bitrate_rx(void *devt, A_INT32 rateKbps)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arBitRate = rateKbps;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_ratemask_rx(void *devt, A_UINT16 ratemask)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arRateMask = ratemask;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_txPwr_rx(void *devt, A_UINT8 txPwr)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arTxPwr = txPwr;
+ wake_up(&arEvent);
+}
+
+
+void
+ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ A_MEMCPY(ar->arChannelList, chanList, numChan * sizeof (A_UINT16));
+ ar->arNumChannels = numChan;
+
+ wake_up(&arEvent);
+}
+
+A_UINT8
+ar6000_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, A_UINT32 * mapNo)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ A_UINT8 *datap;
+ ATH_MAC_HDR *macHdr;
+ A_UINT32 i, eptMap;
+
+ (*mapNo) = 0;
+ datap = A_NETBUF_DATA(skb);
+ macHdr = (ATH_MAC_HDR *)(datap + sizeof(WMI_DATA_HDR));
+ if (IEEE80211_IS_MULTICAST(macHdr->dstMac)) {
+ return ENDPOINT_2;
+ }
+
+ eptMap = -1;
+ for (i = 0; i < ar->arNodeNum; i ++) {
+ if (IEEE80211_ADDR_EQ(macHdr->dstMac, ar->arNodeMap[i].macAddress)) {
+ (*mapNo) = i + 1;
+ ar->arNodeMap[i].txPending ++;
+ return ar->arNodeMap[i].epId;
+ }
+
+ if ((eptMap == -1) && !ar->arNodeMap[i].txPending) {
+ eptMap = i;
+ }
+ }
+
+ if (eptMap == -1) {
+ eptMap = ar->arNodeNum;
+ ar->arNodeNum ++;
+ A_ASSERT(ar->arNodeNum <= MAX_NODE_NUM);
+ }
+
+ A_MEMCPY(ar->arNodeMap[eptMap].macAddress, macHdr->dstMac, IEEE80211_ADDR_LEN);
+
+ for (i = ENDPOINT_2; i <= ENDPOINT_5; i ++) {
+ if (!ar->arTxPending[i]) {
+ ar->arNodeMap[eptMap].epId = i;
+ break;
+ }
+ // No free endpoint is available, start redistribution on the inuse endpoints.
+ if (i == ENDPOINT_5) {
+ ar->arNodeMap[eptMap].epId = ar->arNexEpId;
+ ar->arNexEpId ++;
+ if (ar->arNexEpId > ENDPOINT_5) {
+ ar->arNexEpId = ENDPOINT_2;
+ }
+ }
+ }
+
+ (*mapNo) = eptMap + 1;
+ ar->arNodeMap[eptMap].txPending ++;
+
+ return ar->arNodeMap[eptMap].epId;
+}
+
+#ifdef DEBUG
+static void ar6000_dump_skb(struct sk_buff *skb)
+{
+ u_char *ch;
+ for (ch = A_NETBUF_DATA(skb);
+ (A_UINT32)ch < ((A_UINT32)A_NETBUF_DATA(skb) +
+ A_NETBUF_LEN(skb)); ch++)
+ {
+ AR_DEBUG_PRINTF("%2.2x ", *ch);
+ }
+ AR_DEBUG_PRINTF("\n");
+}
+#endif
+
+static int
+ar6000_data_tx(struct sk_buff *skb, struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_PRI_STREAM_ID streamID = WMI_NOT_MAPPED;
+ A_UINT32 mapNo = 0;
+ int len;
+ struct ar_cookie *cookie;
+ A_BOOL checkAdHocPsMapping = FALSE;
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,13)
+ skb->list = NULL;
+#endif
+
+ AR_DEBUG2_PRINTF("ar6000_data_tx start - skb=0x%x, data=0x%x, len=0x%x\n",
+ (A_UINT32)skb, (A_UINT32)A_NETBUF_DATA(skb),
+ A_NETBUF_LEN(skb));
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ /* TCMD doesnt support any data, free the buf and return */
+ if(ar->arTargetMode == AR6000_TCMD_MODE) {
+ A_NETBUF_FREE(skb);
+ return 0;
+ }
+#endif
+ do {
+
+ if (ar->arWmiReady == FALSE && bypasswmi == 0) {
+ break;
+ }
+
+#ifdef BLOCK_TX_PATH_FLAG
+ if (blocktx) {
+ break;
+ }
+#endif /* BLOCK_TX_PATH_FLAG */
+
+ if (ar->arWmiEnabled) {
+ if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len) {
+ struct sk_buff *newbuf;
+ /*
+ * We really should have gotten enough headroom but sometimes
+ * we still get packets with not enough headroom. Copy the packet.
+ */
+ len = A_NETBUF_LEN(skb);
+ newbuf = A_NETBUF_ALLOC(len);
+ if (newbuf == NULL) {
+ break;
+ }
+ A_NETBUF_PUT(newbuf, len);
+ A_MEMCPY(A_NETBUF_DATA(newbuf), A_NETBUF_DATA(skb), len);
+ A_NETBUF_FREE(skb);
+ skb = newbuf;
+ /* fall through and assemble header */
+ }
+
+ if (wmi_dix_2_dot3(ar->arWmi, skb) != A_OK) {
+ AR_DEBUG_PRINTF("ar6000_data_tx - wmi_dix_2_dot3 failed\n");
+ break;
+ }
+
+ if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE) != A_OK) {
+ AR_DEBUG_PRINTF("ar6000_data_tx - wmi_data_hdr_add failed\n");
+ break;
+ }
+
+ if ((ar->arNetworkType == ADHOC_NETWORK) &&
+ ar->arIbssPsEnable && ar->arConnected) {
+ /* flag to check adhoc mapping once we take the lock below: */
+ checkAdHocPsMapping = TRUE;
+
+ } else {
+ /* get the stream mapping */
+ if (ar->arWmmEnabled) {
+ streamID = wmi_get_stream_id(ar->arWmi,
+ wmi_implicit_create_pstream(ar->arWmi, skb, UPLINK_TRAFFIC, UNDEFINED_PRI));
+ } else {
+ streamID = WMI_BEST_EFFORT_PRI;
+ }
+ }
+
+ } else {
+ struct iphdr *ipHdr;
+ /*
+ * the endpoint is directly based on the TOS field in the IP
+ * header **** only for testing ******
+ */
+ ipHdr = A_NETBUF_DATA(skb) + sizeof(ATH_MAC_HDR);
+ /* here we map the TOS field to an endpoint number, this is for
+ * the endpointping test application */
+ streamID = IP_TOS_TO_WMI_PRI(ipHdr->tos);
+ }
+
+ } while (FALSE);
+
+ /* did we succeed ? */
+ if ((streamID == WMI_NOT_MAPPED) && !checkAdHocPsMapping) {
+ /* cleanup and exit */
+ A_NETBUF_FREE(skb);
+ AR6000_STAT_INC(ar, tx_dropped);
+ AR6000_STAT_INC(ar, tx_aborted_errors);
+ return 0;
+ }
+
+ cookie = NULL;
+
+ /* take the lock to protect driver data */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ do {
+
+ if (checkAdHocPsMapping) {
+ streamID = ar6000_ibss_map_epid(skb, dev, &mapNo);
+ }
+
+ A_ASSERT(streamID != WMI_NOT_MAPPED);
+
+ /* validate that the endpoint is connected */
+ if (arWMIStream2EndpointID(ar,streamID) == 0) {
+ AR_DEBUG_PRINTF("Stream %d is NOT mapped!\n",streamID);
+ break;
+ }
+ /* allocate resource for this packet */
+ cookie = ar6000_alloc_cookie(ar);
+
+ if (cookie != NULL) {
+ /* update counts while the lock is held */
+ ar->arTxPending[streamID]++;
+ ar->arTotalTxDataPending++;
+ }
+
+ } while (FALSE);
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (cookie != NULL) {
+ cookie->arc_bp[0] = (A_UINT32)skb;
+ cookie->arc_bp[1] = mapNo;
+ SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+ cookie,
+ A_NETBUF_DATA(skb),
+ A_NETBUF_LEN(skb),
+ arWMIStream2EndpointID(ar,streamID),
+ AR6K_DATA_PKT_TAG);
+
+#ifdef DEBUG
+ if (debugdriver >= 3) {
+ ar6000_dump_skb(skb);
+ }
+#endif
+ /* HTC interface is asynchronous, if this fails, cleanup will happen in
+ * the ar6000_tx_complete callback */
+ HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+ } else {
+ /* no packet to send, cleanup */
+ A_NETBUF_FREE(skb);
+ AR6000_STAT_INC(ar, tx_dropped);
+ AR6000_STAT_INC(ar, tx_aborted_errors);
+ }
+
+ return 0;
+}
+
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+static void
+tvsub(register struct timeval *out, register struct timeval *in)
+{
+ if((out->tv_usec -= in->tv_usec) < 0) {
+ out->tv_sec--;
+ out->tv_usec += 1000000;
+ }
+ out->tv_sec -= in->tv_sec;
+}
+
+void
+applyAPTCHeuristics(AR_SOFTC_T *ar)
+{
+ A_UINT32 duration;
+ A_UINT32 numbytes;
+ A_UINT32 throughput;
+ struct timeval ts;
+ A_STATUS status;
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if ((enableAPTCHeuristics) && (!aptcTR.timerScheduled)) {
+ do_gettimeofday(&ts);
+ tvsub(&ts, &aptcTR.samplingTS);
+ duration = ts.tv_sec * 1000 + ts.tv_usec / 1000; /* ms */
+ numbytes = aptcTR.bytesTransmitted + aptcTR.bytesReceived;
+
+ if (duration > APTC_TRAFFIC_SAMPLING_INTERVAL) {
+ /* Initialize the time stamp and byte count */
+ aptcTR.bytesTransmitted = aptcTR.bytesReceived = 0;
+ do_gettimeofday(&aptcTR.samplingTS);
+
+ /* Calculate and decide based on throughput thresholds */
+ throughput = ((numbytes * 8) / duration);
+ if (throughput > APTC_UPPER_THROUGHPUT_THRESHOLD) {
+ /* Disable Sleep and schedule a timer */
+ A_ASSERT(ar->arWmiReady == TRUE);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ status = wmi_powermode_cmd(ar->arWmi, MAX_PERF_POWER);
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ A_TIMEOUT_MS(&aptcTimer, APTC_TRAFFIC_SAMPLING_INTERVAL, 0);
+ aptcTR.timerScheduled = TRUE;
+ }
+ }
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+static void ar6000_tx_queue_full(void *Context, HTC_ENDPOINT_ID Endpoint)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+
+
+ if (Endpoint == arWMIStream2EndpointID(ar,WMI_CONTROL_PRI)) {
+ if (!bypasswmi) {
+ /* under normal WMI if this is getting full, then something is running rampant
+ * the host should not be exhausting the WMI queue with too many commands
+ * the only exception to this is during testing using endpointping */
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ /* set flag to handle subsequent messages */
+ ar->arWMIControlEpFull = TRUE;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ AR_DEBUG_PRINTF("WMI Control Endpoint is FULL!!! \n");
+ }
+ } else {
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arNetQueueStopped = TRUE;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ /* one of the data endpoints queues is getting full..need to stop network stack
+ * the queue will resume in ar6000_tx_complete() */
+ netif_stop_queue(ar->arNetDev);
+ }
+
+
+}
+
+
+static void
+ar6000_tx_complete(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ void *cookie = (void *)pPacket->pPktContext;
+ struct sk_buff *skb = NULL;
+ A_UINT32 mapNo = 0;
+ A_STATUS status;
+ struct ar_cookie * ar_cookie;
+ WMI_PRI_STREAM_ID streamID;
+ A_BOOL wakeEvent = FALSE;
+
+ status = pPacket->Status;
+ ar_cookie = (struct ar_cookie *)cookie;
+ skb = (struct sk_buff *)ar_cookie->arc_bp[0];
+ streamID = arEndpoint2WMIStreamID(ar,pPacket->Endpoint);
+ mapNo = ar_cookie->arc_bp[1];
+
+ A_ASSERT(skb);
+ A_ASSERT(pPacket->pBuffer == A_NETBUF_DATA(skb));
+
+ if (A_SUCCESS(status)) {
+ A_ASSERT(pPacket->ActualLength == A_NETBUF_LEN(skb));
+ }
+
+ AR_DEBUG2_PRINTF("ar6000_tx_complete skb=0x%x data=0x%x len=0x%x sid=%d ",
+ (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
+ pPacket->ActualLength,
+ streamID);
+
+ /* lock the driver as we update internal state */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ ar->arTxPending[streamID]--;
+
+ if ((streamID != WMI_CONTROL_PRI) || bypasswmi) {
+ ar->arTotalTxDataPending--;
+ }
+
+ if (streamID == WMI_CONTROL_PRI)
+ {
+ if (ar->arWMIControlEpFull) {
+ /* since this packet completed, the WMI EP is no longer full */
+ ar->arWMIControlEpFull = FALSE;
+ }
+
+ if (ar->arTxPending[streamID] == 0) {
+ wakeEvent = TRUE;
+ }
+ }
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF("%s() -TX ERROR, status: 0x%x\n", __func__,
+ status);
+ AR6000_STAT_INC(ar, tx_errors);
+ } else {
+ AR_DEBUG2_PRINTF("OK\n");
+ AR6000_STAT_INC(ar, tx_packets);
+ ar->arNetStats.tx_bytes += A_NETBUF_LEN(skb);
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ aptcTR.bytesTransmitted += a_netbuf_to_len(skb);
+ applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+ }
+
+ // TODO this needs to be looked at
+ if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable
+ && (streamID != WMI_CONTROL_PRI) && mapNo)
+ {
+ mapNo --;
+ ar->arNodeMap[mapNo].txPending --;
+
+ if (!ar->arNodeMap[mapNo].txPending && (mapNo == (ar->arNodeNum - 1))) {
+ A_UINT32 i;
+ for (i = ar->arNodeNum; i > 0; i --) {
+ if (!ar->arNodeMap[i - 1].txPending) {
+ A_MEMZERO(&ar->arNodeMap[i - 1], sizeof(struct ar_node_mapping));
+ ar->arNodeNum --;
+ } else {
+ break;
+ }
+ }
+ }
+ }
+
+ /* Freeing a cookie should not be contingent on either of */
+ /* these flags, just if we have a cookie or not. */
+ /* Can we even get here without a cookie? Fix later. */
+ if (ar->arWmiReady == TRUE || (bypasswmi))
+ {
+ ar6000_free_cookie(ar, cookie);
+ }
+
+ if (ar->arNetQueueStopped) {
+ ar->arNetQueueStopped = FALSE;
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ /* lock is released, we can freely call other kernel APIs */
+
+ /* this indirectly frees the HTC_PACKET */
+ A_NETBUF_FREE(skb);
+
+ if ((ar->arConnected == TRUE) || (bypasswmi)) {
+ if (status != A_ECANCELED) {
+ /* don't wake the queue if we are flushing, other wise it will just
+ * keep queueing packets, which will keep failing */
+ netif_wake_queue(ar->arNetDev);
+ }
+ }
+
+ if (wakeEvent) {
+ wake_up(&arEvent);
+ }
+
+}
+
+/*
+ * Receive event handler. This is called by HTC when a packet is received
+ */
+int pktcount;
+static void
+ar6000_rx(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ struct sk_buff *skb = (struct sk_buff *)pPacket->pPktContext;
+ int minHdrLen;
+ A_STATUS status = pPacket->Status;
+ WMI_PRI_STREAM_ID streamID = arEndpoint2WMIStreamID(ar,pPacket->Endpoint);
+ HTC_ENDPOINT_ID ept = pPacket->Endpoint;
+
+ A_ASSERT((status != A_OK) || (pPacket->pBuffer == (A_NETBUF_DATA(skb) + HTC_HEADER_LEN)));
+
+ AR_DEBUG2_PRINTF("ar6000_rx ar=0x%x sid=%d, skb=0x%x, data=0x%x, len=0x%x ",
+ (A_UINT32)ar, streamID, (A_UINT32)skb, (A_UINT32)pPacket->pBuffer,
+ pPacket->ActualLength);
+ if (status != A_OK) {
+ AR_DEBUG2_PRINTF("ERR\n");
+ } else {
+ AR_DEBUG2_PRINTF("OK\n");
+ }
+
+ /* take lock to protect buffer counts
+ * and adaptive power throughput state */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ ar->arRxBuffers[streamID]--;
+
+ if (A_SUCCESS(status)) {
+ AR6000_STAT_INC(ar, rx_packets);
+ ar->arNetStats.rx_bytes += pPacket->ActualLength;
+#ifdef ADAPTIVE_POWER_THROUGHPUT_CONTROL
+ aptcTR.bytesReceived += a_netbuf_to_len(skb);
+ applyAPTCHeuristics(ar);
+#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
+
+ A_NETBUF_PUT(skb, pPacket->ActualLength + HTC_HEADER_LEN);
+ A_NETBUF_PULL(skb, HTC_HEADER_LEN);
+
+#ifdef DEBUG
+ if (debugdriver >= 2) {
+ ar6000_dump_skb(skb);
+ }
+#endif /* DEBUG */
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (status != A_OK) {
+ AR6000_STAT_INC(ar, rx_errors);
+ A_NETBUF_FREE(skb);
+ } else if (ar->arWmiEnabled == TRUE) {
+ if (streamID == WMI_CONTROL_PRI) {
+ /*
+ * this is a wmi control msg
+ */
+ wmi_control_rx(ar->arWmi, skb);
+ } else {
+ WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
+ if (WMI_DATA_HDR_IS_MSG_TYPE(dhdr, CNTL_MSGTYPE)) {
+ /*
+ * this is a wmi control msg
+ */
+ /* strip off WMI hdr */
+ wmi_data_hdr_remove(ar->arWmi, skb);
+ wmi_control_rx(ar->arWmi, skb);
+ } else {
+ /*
+ * this is a wmi data packet
+ */
+ minHdrLen = sizeof (WMI_DATA_HDR) + sizeof(ATH_MAC_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR);
+
+ if ((pPacket->ActualLength < minHdrLen) ||
+ (pPacket->ActualLength > AR6000_BUFFER_SIZE))
+ {
+ /*
+ * packet is too short or too long
+ */
+ AR_DEBUG_PRINTF("TOO SHORT or TOO LONG\n");
+ AR6000_STAT_INC(ar, rx_errors);
+ AR6000_STAT_INC(ar, rx_length_errors);
+ A_NETBUF_FREE(skb);
+ } else {
+ if (ar->arWmmEnabled) {
+ wmi_implicit_create_pstream(ar->arWmi, skb,
+ DNLINK_TRAFFIC, UNDEFINED_PRI);
+ }
+#if 0
+ /* Access RSSI values here */
+ AR_DEBUG_PRINTF("RSSI %d\n",
+ ((WMI_DATA_HDR *) A_NETBUF_DATA(skb))->rssi);
+#endif
+ wmi_data_hdr_remove(ar->arWmi, skb);
+ wmi_dot3_2_dix(ar->arWmi, skb);
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
+ /*
+ * extra push and memcpy, for eth_type_trans() of 2.4 kernel
+ * will pull out hard_header_len bytes of the skb.
+ */
+ A_NETBUF_PUSH(skb, sizeof(WMI_DATA_HDR) + sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN);
+ A_MEMCPY(A_NETBUF_DATA(skb), A_NETBUF_DATA(skb) + sizeof(WMI_DATA_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR) + HTC_HEADER_LEN, sizeof(ATH_MAC_HDR));
+#endif
+ if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
+ {
+ skb->dev = ar->arNetDev;
+ skb->protocol = eth_type_trans(skb, ar->arNetDev);
+ netif_rx(skb);
+ }
+ else
+ {
+ A_NETBUF_FREE(skb);
+ }
+ }
+ }
+ }
+ } else {
+ if ((ar->arNetDev->flags & IFF_UP) == IFF_UP)
+ {
+ skb->dev = ar->arNetDev;
+ skb->protocol = eth_type_trans(skb, ar->arNetDev);
+ netif_rx(skb);
+ }
+ else
+ {
+ A_NETBUF_FREE(skb);
+ }
+ }
+
+ if (status != A_ECANCELED) {
+ /*
+ * HTC provides A_ECANCELED status when it doesn't want to be refilled
+ * (probably due to a shutdown)
+ */
+ ar6000_rx_refill(Context, ept);
+ }
+
+
+}
+
+static void
+ar6000_rx_refill(void *Context, HTC_ENDPOINT_ID Endpoint)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ void *osBuf;
+ int RxBuffers;
+ int buffersToRefill;
+ HTC_PACKET *pPacket;
+ WMI_PRI_STREAM_ID streamId = arEndpoint2WMIStreamID(ar,Endpoint);
+
+ buffersToRefill = (int)AR6000_MAX_RX_BUFFERS -
+ (int)ar->arRxBuffers[streamId];
+
+ if (buffersToRefill <= 0) {
+ /* fast return, nothing to fill */
+ return;
+ }
+
+ AR_DEBUG2_PRINTF("ar6000_rx_refill: providing htc with %d buffers at eid=%d\n",
+ buffersToRefill, Endpoint);
+
+ for (RxBuffers = 0; RxBuffers < buffersToRefill; RxBuffers++) {
+ osBuf = A_NETBUF_ALLOC(AR6000_BUFFER_SIZE);
+ if (NULL == osBuf) {
+ break;
+ }
+ /* the HTC packet wrapper is at the head of the reserved area
+ * in the skb */
+ pPacket = (HTC_PACKET *)(A_NETBUF_HEAD(osBuf));
+ /* set re-fill info */
+ SET_HTC_PACKET_INFO_RX_REFILL(pPacket,osBuf,A_NETBUF_DATA(osBuf),AR6000_BUFFER_SIZE,Endpoint);
+ /* add this packet */
+ HTCAddReceivePkt(ar->arHtcTarget, pPacket);
+ }
+
+ /* update count */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arRxBuffers[streamId] += RxBuffers;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+}
+
+static struct net_device_stats *
+ar6000_get_stats(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ return &ar->arNetStats;
+}
+
+static struct iw_statistics *
+ar6000_get_iwstats(struct net_device * dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ struct iw_statistics * pIwStats = &ar->arIwStats;
+
+ if ((ar->arWmiReady == FALSE)
+ /*
+ * The in_atomic function is used to determine if the scheduling is
+ * allowed in the current context or not. This was introduced in 2.6
+ * From what I have read on the differences between 2.4 and 2.6, the
+ * 2.4 kernel did not support preemption and so this check might not
+ * be required for 2.4 kernels.
+ */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+ || (in_atomic())
+#endif
+ )
+ {
+ pIwStats->status = 0;
+ pIwStats->qual.qual = 0;
+ pIwStats->qual.level =0;
+ pIwStats->qual.noise = 0;
+ pIwStats->discard.code =0;
+ pIwStats->discard.retries=0;
+ pIwStats->miss.beacon =0;
+ return pIwStats;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+
+
+ ar->statsUpdatePending = TRUE;
+
+ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ AR_DEBUG_PRINTF("ar6000 : WMI get stats timeout \n");
+ up(&ar->arSem);
+ pIwStats->status = 0;
+ return pIwStats;
+ }
+ pIwStats->status = 1 ;
+ pIwStats->qual.qual = pStats->cs_aveBeacon_rssi;
+ pIwStats->qual.level =pStats->cs_aveBeacon_rssi + 161; /* noise is -95 dBm */
+ pIwStats->qual.noise = pStats->noise_floor_calibation;
+ pIwStats->discard.code = pStats->rx_decrypt_err;
+ pIwStats->discard.retries = pStats->tx_retry_cnt;
+ pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
+ up(&ar->arSem);
+ return pIwStats;
+}
+
+void
+ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ struct net_device *dev = ar->arNetDev;
+
+ ar->arWmiReady = TRUE;
+ wake_up(&arEvent);
+ A_MEMCPY(dev->dev_addr, datap, AR6000_ETH_ADDR_LEN);
+ AR_DEBUG_PRINTF("mac address = %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+ dev->dev_addr[0], dev->dev_addr[1],
+ dev->dev_addr[2], dev->dev_addr[3],
+ dev->dev_addr[4], dev->dev_addr[5]);
+
+ ar->arPhyCapability = phyCap;
+}
+
+A_UINT8
+ar6000_iptos_to_userPriority(A_UINT8 *pkt)
+{
+ struct iphdr *ipHdr = (struct iphdr *)pkt;
+ A_UINT8 userPriority;
+
+ /*
+ * IP Tos format :
+ * (Refer Pg 57 WMM-test-plan-v1.2)
+ * IP-TOS - 8bits
+ * : DSCP(6-bits) ECN(2-bits)
+ * : DSCP - P2 P1 P0 X X X
+ * where (P2 P1 P0) form 802.1D
+ */
+ userPriority = ipHdr->tos >> 5;
+ return (userPriority & 0x7);
+}
+
+void
+ar6000_connect_event(AR_SOFTC_T *ar, A_UINT16 channel, A_UINT8 *bssid,
+ A_UINT16 listenInterval, A_UINT16 beaconInterval,
+ NETWORK_TYPE networkType, A_UINT8 beaconIeLen,
+ A_UINT8 assocReqLen, A_UINT8 assocRespLen,
+ A_UINT8 *assocInfo)
+{
+ union iwreq_data wrqu;
+ int i, beacon_ie_pos, assoc_resp_ie_pos, assoc_req_ie_pos;
+ static const char *tag1 = "ASSOCINFO(ReqIEs=";
+ static const char *tag2 = "ASSOCRESPIE=";
+ static const char *beaconIetag = "BEACONIE=";
+ char buf[WMI_CONTROL_MSG_MAX_LEN * 2 + sizeof(tag1)];
+ char *pos;
+ A_UINT8 key_op_ctrl;
+
+ A_MEMCPY(ar->arBssid, bssid, sizeof(ar->arBssid));
+ ar->arBssChannel = channel;
+
+ A_PRINTF("AR6000 connected event on freq %d ", channel);
+ A_PRINTF("with bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x "
+ " listenInterval=%d, beaconInterval = %d, beaconIeLen = %d assocReqLen=%d"
+ " assocRespLen =%d\n",
+ bssid[0], bssid[1], bssid[2],
+ bssid[3], bssid[4], bssid[5],
+ listenInterval, beaconInterval,
+ beaconIeLen, assocReqLen, assocRespLen);
+ if (networkType & ADHOC_NETWORK) {
+ if (networkType & ADHOC_CREATOR) {
+ A_PRINTF("Network: Adhoc (Creator)\n");
+ } else {
+ A_PRINTF("Network: Adhoc (Joiner)\n");
+ }
+ } else {
+ A_PRINTF("Network: Infrastructure\n");
+ }
+
+ if (beaconIeLen && (sizeof(buf) > (9 + beaconIeLen * 2))) {
+ AR_DEBUG_PRINTF("\nBeaconIEs= ");
+
+ beacon_ie_pos = 0;
+ A_MEMZERO(buf, sizeof(buf));
+ sprintf(buf, "%s", beaconIetag);
+ pos = buf + 9;
+ for (i = beacon_ie_pos; i < beacon_ie_pos + beaconIeLen; i++) {
+ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
+ sprintf(pos, "%2.2x", assocInfo[i]);
+ pos += 2;
+ }
+ AR_DEBUG_PRINTF("\n");
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+
+ if (assocRespLen && (sizeof(buf) > (12 + (assocRespLen * 2))))
+ {
+ assoc_resp_ie_pos = beaconIeLen + assocReqLen +
+ sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16) + /* status Code */
+ sizeof(A_UINT16) ; /* associd */
+ A_MEMZERO(buf, sizeof(buf));
+ sprintf(buf, "%s", tag2);
+ pos = buf + 12;
+ AR_DEBUG_PRINTF("\nAssocRespIEs= ");
+ /*
+ * The Association Response Frame w.o. the WLAN header is delivered to
+ * the host, so skip over to the IEs
+ */
+ for (i = assoc_resp_ie_pos; i < assoc_resp_ie_pos + assocRespLen - 6; i++)
+ {
+ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
+ sprintf(pos, "%2.2x", assocInfo[i]);
+ pos += 2;
+ }
+ AR_DEBUG_PRINTF("\n");
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+
+ if (assocReqLen && (sizeof(buf) > (17 + (assocReqLen * 2)))) {
+ /*
+ * assoc Request includes capability and listen interval. Skip these.
+ */
+ assoc_req_ie_pos = beaconIeLen +
+ sizeof(A_UINT16) + /* capinfo*/
+ sizeof(A_UINT16); /* listen interval */
+
+ A_MEMZERO(buf, sizeof(buf));
+ sprintf(buf, "%s", tag1);
+ pos = buf + 17;
+ AR_DEBUG_PRINTF("AssocReqIEs= ");
+ for (i = assoc_req_ie_pos; i < assoc_req_ie_pos + assocReqLen - 4; i++) {
+ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
+ sprintf(pos, "%2.2x", assocInfo[i]);
+ pos += 2;;
+ }
+ AR_DEBUG_PRINTF("\n");
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+
+#ifdef USER_KEYS
+ if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
+ ar->user_saved_keys.keyOk == TRUE)
+ {
+
+ key_op_ctrl = KEY_OP_VALID_MASK & ~KEY_OP_INIT_TSC;
+ if (ar->user_key_ctrl & AR6000_USER_SETKEYS_RSC_UNCHANGED) {
+ key_op_ctrl &= ~KEY_OP_INIT_RSC;
+ } else {
+ key_op_ctrl |= KEY_OP_INIT_RSC;
+ }
+ ar6000_reinstall_keys(ar, key_op_ctrl);
+ }
+#endif /* USER_KEYS */
+
+ /* flush data queues */
+ ar6000_TxDataCleanup(ar);
+
+ netif_wake_queue(ar->arNetDev);
+
+ if ((OPEN_AUTH == ar->arDot11AuthMode) &&
+ (NONE_AUTH == ar->arAuthMode) &&
+ (WEP_CRYPT == ar->arPairwiseCrypto))
+ {
+ if (!ar->arConnected) {
+ ar6000_install_static_wep_keys(ar);
+ }
+ }
+
+ ar->arConnected = TRUE;
+ ar->arConnectPending = FALSE;
+
+ reconnect_flag = 0;
+
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ A_MEMCPY(wrqu.addr.sa_data, bssid, IEEE80211_ADDR_LEN);
+ wrqu.addr.sa_family = ARPHRD_ETHER;
+ wireless_send_event(ar->arNetDev, SIOCGIWAP, &wrqu, NULL);
+ if ((ar->arNetworkType == ADHOC_NETWORK) && ar->arIbssPsEnable) {
+ A_MEMZERO(ar->arNodeMap, sizeof(ar->arNodeMap));
+ ar->arNodeNum = 0;
+ ar->arNexEpId = ENDPOINT_2;
+ }
+
+}
+
+void ar6000_set_numdataendpts(AR_SOFTC_T *ar, A_UINT32 num)
+{
+ A_ASSERT(num <= (HTC_MAILBOX_NUM_MAX - 1));
+ ar->arNumDataEndPts = num;
+}
+
+void
+ar6000_disconnect_event(AR_SOFTC_T *ar, A_UINT8 reason, A_UINT8 *bssid,
+ A_UINT8 assocRespLen, A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus)
+{
+ A_UINT8 i;
+
+ A_PRINTF("AR6000 disconnected");
+ if (bssid[0] || bssid[1] || bssid[2] || bssid[3] || bssid[4] || bssid[5]) {
+ A_PRINTF(" from %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+ bssid[0], bssid[1], bssid[2], bssid[3], bssid[4], bssid[5]);
+ }
+ A_PRINTF("\n");
+
+ AR_DEBUG_PRINTF("\nDisconnect Reason is %d", reason);
+ AR_DEBUG_PRINTF("\nProtocol Reason/Status Code is %d", protocolReasonStatus);
+ AR_DEBUG_PRINTF("\nAssocResp Frame = %s",
+ assocRespLen ? " " : "NULL");
+ for (i = 0; i < assocRespLen; i++) {
+ if (!(i % 0x10)) {
+ AR_DEBUG_PRINTF("\n");
+ }
+ AR_DEBUG_PRINTF("%2.2x ", assocInfo[i]);
+ }
+ AR_DEBUG_PRINTF("\n");
+ /*
+ * If the event is due to disconnect cmd from the host, only they the target
+ * would stop trying to connect. Under any other condition, target would
+ * keep trying to connect.
+ *
+ */
+ if( reason == DISCONNECT_CMD)
+ {
+ ar->arConnectPending = FALSE;
+ } else {
+ ar->arConnectPending = TRUE;
+ if (((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x11)) ||
+ ((reason == ASSOC_FAILED) && (protocolReasonStatus == 0x0) && (reconnect_flag == 1))) {
+ ar->arConnected = TRUE;
+ return;
+ }
+ }
+ ar->arConnected = FALSE;
+
+ if( (reason != CSERV_DISCONNECT) || (reconnect_flag != 1) ) {
+ reconnect_flag = 0;
+ }
+
+#ifdef USER_KEYS
+ if (reason != CSERV_DISCONNECT)
+ {
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+ ar->user_key_ctrl = 0;
+ }
+#endif /* USER_KEYS */
+
+ netif_stop_queue(ar->arNetDev);
+ A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
+ ar->arBssChannel = 0;
+ ar->arBeaconInterval = 0;
+
+ ar6000_TxDataCleanup(ar);
+}
+
+void
+ar6000_regDomain_event(AR_SOFTC_T *ar, A_UINT32 regCode)
+{
+ A_PRINTF("AR6000 Reg Code = 0x%x\n", regCode);
+ ar->arRegCode = regCode;
+}
+
+void
+ar6000_neighborReport_event(AR_SOFTC_T *ar, int numAps, WMI_NEIGHBOR_INFO *info)
+{
+ static const char *tag = "PRE-AUTH";
+ char buf[128];
+ union iwreq_data wrqu;
+ int i;
+
+ AR_DEBUG_PRINTF("AR6000 Neighbor Report Event\n");
+ for (i=0; i < numAps; info++, i++) {
+ AR_DEBUG_PRINTF("bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",
+ info->bssid[0], info->bssid[1], info->bssid[2],
+ info->bssid[3], info->bssid[4], info->bssid[5]);
+ if (info->bssFlags & WMI_PREAUTH_CAPABLE_BSS) {
+ AR_DEBUG_PRINTF("preauth-cap");
+ }
+ if (info->bssFlags & WMI_PMKID_VALID_BSS) {
+ AR_DEBUG_PRINTF(" pmkid-valid\n");
+ continue; /* we skip bss if the pmkid is already valid */
+ }
+ AR_DEBUG_PRINTF("\n");
+ snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
+ tag,
+ info->bssid[0], info->bssid[1], info->bssid[2],
+ info->bssid[3], info->bssid[4], info->bssid[5],
+ i, info->bssFlags);
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+ }
+}
+
+void
+ar6000_tkip_micerr_event(AR_SOFTC_T *ar, A_UINT8 keyid, A_BOOL ismcast)
+{
+ static const char *tag = "MLME-MICHAELMICFAILURE.indication";
+ char buf[128];
+ union iwreq_data wrqu;
+
+ A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
+ keyid, ismcast ? "multi": "uni");
+ snprintf(buf, sizeof(buf), "%s(keyid=%d %scat)", tag, keyid,
+ ismcast ? "multi" : "uni");
+ memset(&wrqu, 0, sizeof(wrqu));
+ wrqu.data.length = strlen(buf);
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+}
+
+void
+ar6000_scanComplete_event(AR_SOFTC_T *ar, A_STATUS status)
+{
+ AR_DEBUG_PRINTF("AR6000 scan complete: %d\n", status);
+
+ ar->scan_complete = 1;
+ wake_up_interruptible(&ar6000_scan_queue);
+}
+
+void
+ar6000_targetStats_event(AR_SOFTC_T *ar, WMI_TARGET_STATS *pTarget)
+{
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ A_UINT8 ac;
+
+ /*A_PRINTF("AR6000 updating target stats\n");*/
+ pStats->tx_packets += pTarget->txrxStats.tx_stats.tx_packets;
+ pStats->tx_bytes += pTarget->txrxStats.tx_stats.tx_bytes;
+ pStats->tx_unicast_pkts += pTarget->txrxStats.tx_stats.tx_unicast_pkts;
+ pStats->tx_unicast_bytes += pTarget->txrxStats.tx_stats.tx_unicast_bytes;
+ pStats->tx_multicast_pkts += pTarget->txrxStats.tx_stats.tx_multicast_pkts;
+ pStats->tx_multicast_bytes += pTarget->txrxStats.tx_stats.tx_multicast_bytes;
+ pStats->tx_broadcast_pkts += pTarget->txrxStats.tx_stats.tx_broadcast_pkts;
+ pStats->tx_broadcast_bytes += pTarget->txrxStats.tx_stats.tx_broadcast_bytes;
+ pStats->tx_rts_success_cnt += pTarget->txrxStats.tx_stats.tx_rts_success_cnt;
+ for(ac = 0; ac < WMM_NUM_AC; ac++)
+ pStats->tx_packet_per_ac[ac] += pTarget->txrxStats.tx_stats.tx_packet_per_ac[ac];
+ pStats->tx_errors += pTarget->txrxStats.tx_stats.tx_errors;
+ pStats->tx_failed_cnt += pTarget->txrxStats.tx_stats.tx_failed_cnt;
+ pStats->tx_retry_cnt += pTarget->txrxStats.tx_stats.tx_retry_cnt;
+ pStats->tx_rts_fail_cnt += pTarget->txrxStats.tx_stats.tx_rts_fail_cnt;
+ pStats->tx_unicast_rate = wmi_get_rate(pTarget->txrxStats.tx_stats.tx_unicast_rate);
+
+ pStats->rx_packets += pTarget->txrxStats.rx_stats.rx_packets;
+ pStats->rx_bytes += pTarget->txrxStats.rx_stats.rx_bytes;
+ pStats->rx_unicast_pkts += pTarget->txrxStats.rx_stats.rx_unicast_pkts;
+ pStats->rx_unicast_bytes += pTarget->txrxStats.rx_stats.rx_unicast_bytes;
+ pStats->rx_multicast_pkts += pTarget->txrxStats.rx_stats.rx_multicast_pkts;
+ pStats->rx_multicast_bytes += pTarget->txrxStats.rx_stats.rx_multicast_bytes;
+ pStats->rx_broadcast_pkts += pTarget->txrxStats.rx_stats.rx_broadcast_pkts;
+ pStats->rx_broadcast_bytes += pTarget->txrxStats.rx_stats.rx_broadcast_bytes;
+ pStats->rx_fragment_pkt += pTarget->txrxStats.rx_stats.rx_fragment_pkt;
+ pStats->rx_errors += pTarget->txrxStats.rx_stats.rx_errors;
+ pStats->rx_crcerr += pTarget->txrxStats.rx_stats.rx_crcerr;
+ pStats->rx_key_cache_miss += pTarget->txrxStats.rx_stats.rx_key_cache_miss;
+ pStats->rx_decrypt_err += pTarget->txrxStats.rx_stats.rx_decrypt_err;
+ pStats->rx_duplicate_frames += pTarget->txrxStats.rx_stats.rx_duplicate_frames;
+ pStats->rx_unicast_rate = wmi_get_rate(pTarget->txrxStats.rx_stats.rx_unicast_rate);
+
+
+ pStats->tkip_local_mic_failure
+ += pTarget->txrxStats.tkipCcmpStats.tkip_local_mic_failure;
+ pStats->tkip_counter_measures_invoked
+ += pTarget->txrxStats.tkipCcmpStats.tkip_counter_measures_invoked;
+ pStats->tkip_replays += pTarget->txrxStats.tkipCcmpStats.tkip_replays;
+ pStats->tkip_format_errors += pTarget->txrxStats.tkipCcmpStats.tkip_format_errors;
+ pStats->ccmp_format_errors += pTarget->txrxStats.tkipCcmpStats.ccmp_format_errors;
+ pStats->ccmp_replays += pTarget->txrxStats.tkipCcmpStats.ccmp_replays;
+
+
+ pStats->power_save_failure_cnt += pTarget->pmStats.power_save_failure_cnt;
+ pStats->noise_floor_calibation = pTarget->noise_floor_calibation;
+
+ pStats->cs_bmiss_cnt += pTarget->cservStats.cs_bmiss_cnt;
+ pStats->cs_lowRssi_cnt += pTarget->cservStats.cs_lowRssi_cnt;
+ pStats->cs_connect_cnt += pTarget->cservStats.cs_connect_cnt;
+ pStats->cs_disconnect_cnt += pTarget->cservStats.cs_disconnect_cnt;
+ pStats->cs_aveBeacon_snr = pTarget->cservStats.cs_aveBeacon_snr;
+ pStats->cs_aveBeacon_rssi = pTarget->cservStats.cs_aveBeacon_rssi;
+ pStats->cs_lastRoam_msec = pTarget->cservStats.cs_lastRoam_msec;
+ pStats->cs_snr = pTarget->cservStats.cs_snr;
+ pStats->cs_rssi = pTarget->cservStats.cs_rssi;
+
+ pStats->lq_val = pTarget->lqVal;
+
+ pStats->wow_num_pkts_dropped += pTarget->wowStats.wow_num_pkts_dropped;
+ pStats->wow_num_host_pkt_wakeups += pTarget->wowStats.wow_num_host_pkt_wakeups;
+ pStats->wow_num_host_event_wakeups += pTarget->wowStats.wow_num_host_event_wakeups;
+ pStats->wow_num_events_discarded += pTarget->wowStats.wow_num_events_discarded;
+
+ ar->statsUpdatePending = FALSE;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_rssiThreshold_event(AR_SOFTC_T *ar, WMI_RSSI_THRESHOLD_VAL newThreshold, A_INT16 rssi)
+{
+ USER_RSSI_THOLD userRssiThold;
+
+ userRssiThold.tag = rssi_map[newThreshold].tag;
+ userRssiThold.rssi = rssi;
+ AR_DEBUG2_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold, userRssiThold.tag, rssi);
+#ifdef SEND_EVENT_TO_APP
+ ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(A_UINT8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
+#endif
+}
+
+
+void
+ar6000_hbChallengeResp_event(AR_SOFTC_T *ar, A_UINT32 cookie, A_UINT32 source)
+{
+ if (source == APP_HB_CHALLENGE) {
+ /* Report it to the app in case it wants a positive acknowledgement */
+#ifdef SEND_EVENT_TO_APP
+ ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
+ (A_UINT8 *)&cookie, sizeof(cookie));
+#endif
+ } else {
+ /* This would ignore the replys that come in after their due time */
+ if (cookie == ar->arHBChallengeResp.seqNum) {
+ ar->arHBChallengeResp.outstanding = FALSE;
+ }
+ }
+}
+
+
+void
+ar6000_reportError_event(AR_SOFTC_T *ar, WMI_TARGET_ERROR_VAL errorVal)
+{
+ char *errString[] = {
+ [WMI_TARGET_PM_ERR_FAIL] "WMI_TARGET_PM_ERR_FAIL",
+ [WMI_TARGET_KEY_NOT_FOUND] "WMI_TARGET_KEY_NOT_FOUND",
+ [WMI_TARGET_DECRYPTION_ERR] "WMI_TARGET_DECRYPTION_ERR",
+ [WMI_TARGET_BMISS] "WMI_TARGET_BMISS",
+ [WMI_PSDISABLE_NODE_JOIN] "WMI_PSDISABLE_NODE_JOIN"
+ };
+
+ A_PRINTF("AR6000 Error on Target. Error = 0x%x\n", errorVal);
+
+ /* One error is reported at a time, and errorval is a bitmask */
+ if(errorVal & (errorVal - 1))
+ return;
+
+ A_PRINTF("AR6000 Error type = ");
+ switch(errorVal)
+ {
+ case WMI_TARGET_PM_ERR_FAIL:
+ case WMI_TARGET_KEY_NOT_FOUND:
+ case WMI_TARGET_DECRYPTION_ERR:
+ case WMI_TARGET_BMISS:
+ case WMI_PSDISABLE_NODE_JOIN:
+ A_PRINTF("%s\n", errString[errorVal]);
+ break;
+ default:
+ A_PRINTF("INVALID\n");
+ break;
+ }
+
+}
+
+
+void
+ar6000_cac_event(AR_SOFTC_T *ar, A_UINT8 ac, A_UINT8 cacIndication,
+ A_UINT8 statusCode, A_UINT8 *tspecSuggestion)
+{
+ WMM_TSPEC_IE *tspecIe;
+
+ /*
+ * This is the TSPEC IE suggestion from AP.
+ * Suggestion provided by AP under some error
+ * cases, could be helpful for the host app.
+ * Check documentation.
+ */
+ tspecIe = (WMM_TSPEC_IE *)tspecSuggestion;
+
+ /*
+ * What do we do, if we get TSPEC rejection? One thought
+ * that comes to mind is implictly delete the pstream...
+ */
+ A_PRINTF("AR6000 CAC notification. "
+ "AC = %d, cacIndication = 0x%x, statusCode = 0x%x\n",
+ ac, cacIndication, statusCode);
+}
+
+#define AR6000_PRINT_BSSID(_pBss) do { \
+ A_PRINTF("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ",\
+ (_pBss)[0],(_pBss)[1],(_pBss)[2],(_pBss)[3],\
+ (_pBss)[4],(_pBss)[5]); \
+} while(0)
+
+void
+ar6000_roam_tbl_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_TBL *pTbl)
+{
+ A_UINT8 i;
+
+ A_PRINTF("ROAM TABLE NO OF ENTRIES is %d ROAM MODE is %d\n",
+ pTbl->numEntries, pTbl->roamMode);
+ for (i= 0; i < pTbl->numEntries; i++) {
+ A_PRINTF("[%d]bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x ", i,
+ pTbl->bssRoamInfo[i].bssid[0], pTbl->bssRoamInfo[i].bssid[1],
+ pTbl->bssRoamInfo[i].bssid[2],
+ pTbl->bssRoamInfo[i].bssid[3],
+ pTbl->bssRoamInfo[i].bssid[4],
+ pTbl->bssRoamInfo[i].bssid[5]);
+ A_PRINTF("RSSI %d RSSIDT %d LAST RSSI %d UTIL %d ROAM_UTIL %d"
+ " BIAS %d\n",
+ pTbl->bssRoamInfo[i].rssi,
+ pTbl->bssRoamInfo[i].rssidt,
+ pTbl->bssRoamInfo[i].last_rssi,
+ pTbl->bssRoamInfo[i].util,
+ pTbl->bssRoamInfo[i].roam_util,
+ pTbl->bssRoamInfo[i].bias);
+ }
+}
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters, WMI_GET_WOW_LIST_REPLY *wow_reply)
+{
+ A_UINT8 i,j;
+
+ /*Each event now contains exactly one filter, see bug 26613*/
+ A_PRINTF("WOW pattern %d of %d patterns\n", wow_reply->this_filter_num, wow_reply->num_filters);
+ A_PRINTF("wow mode = %s host mode = %s\n",
+ (wow_reply->wow_mode == 0? "disabled":"enabled"),
+ (wow_reply->host_mode == 1 ? "awake":"asleep"));
+
+
+ /*If there are no patterns, the reply will only contain generic
+ WoW information. Pattern information will exist only if there are
+ patterns present. Bug 26716*/
+
+ /* If this event contains pattern information, display it*/
+ if (wow_reply->this_filter_num) {
+ i=0;
+ A_PRINTF("id=%d size=%d offset=%d\n",
+ wow_reply->wow_filters[i].wow_filter_id,
+ wow_reply->wow_filters[i].wow_filter_size,
+ wow_reply->wow_filters[i].wow_filter_offset);
+ A_PRINTF("wow pattern = ");
+ for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+ A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_pattern[j]);
+ }
+
+ A_PRINTF("\nwow mask = ");
+ for (j=0; j< wow_reply->wow_filters[i].wow_filter_size; j++) {
+ A_PRINTF("%2.2x",wow_reply->wow_filters[i].wow_filter_mask[j]);
+ }
+ A_PRINTF("\n");
+ }
+}
+
+/*
+ * Report the Roaming related data collected on the target
+ */
+void
+ar6000_display_roam_time(WMI_TARGET_ROAM_TIME *p)
+{
+ A_PRINTF("Disconnect Data : BSSID: ");
+ AR6000_PRINT_BSSID(p->disassoc_bssid);
+ A_PRINTF(" RSSI %d DISASSOC Time %d NO_TXRX_TIME %d\n",
+ p->disassoc_bss_rssi,p->disassoc_time,
+ p->no_txrx_time);
+ A_PRINTF("Connect Data: BSSID: ");
+ AR6000_PRINT_BSSID(p->assoc_bssid);
+ A_PRINTF(" RSSI %d ASSOC Time %d TXRX_TIME %d\n",
+ p->assoc_bss_rssi,p->assoc_time,
+ p->allow_txrx_time);
+ A_PRINTF("Last Data Tx Time (b4 Disassoc) %d "\
+ "First Data Tx Time (after Assoc) %d\n",
+ p->last_data_txrx_time, p->first_data_txrx_time);
+}
+
+void
+ar6000_roam_data_event(AR_SOFTC_T *ar, WMI_TARGET_ROAM_DATA *p)
+{
+ switch (p->roamDataType) {
+ case ROAM_DATA_TIME:
+ ar6000_display_roam_time(&p->u.roamTime);
+ break;
+ default:
+ break;
+ }
+}
+
+void
+ar6000_bssInfo_event_rx(AR_SOFTC_T *ar, A_UINT8 *datap, int len)
+{
+ struct sk_buff *skb;
+ WMI_BSS_INFO_HDR *bih = (WMI_BSS_INFO_HDR *)datap;
+
+
+ if (!ar->arMgmtFilter) {
+ return;
+ }
+ if (((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_BEACON) &&
+ (bih->frameType != BEACON_FTYPE)) ||
+ ((ar->arMgmtFilter & IEEE80211_FILTER_TYPE_PROBE_RESP) &&
+ (bih->frameType != PROBERESP_FTYPE)))
+ {
+ return;
+ }
+
+ if ((skb = A_NETBUF_ALLOC_RAW(len)) != NULL) {
+
+ A_NETBUF_PUT(skb, len);
+ A_MEMCPY(A_NETBUF_DATA(skb), datap, len);
+ skb->dev = ar->arNetDev;
+ printk("MAC RAW...\n");
+// skb->mac.raw = A_NETBUF_DATA(skb);
+ skb->ip_summed = CHECKSUM_NONE;
+ skb->pkt_type = PACKET_OTHERHOST;
+ skb->protocol = __constant_htons(0x0019);
+ netif_rx(skb);
+ }
+}
+
+A_UINT32 wmiSendCmdNum;
+
+A_STATUS
+ar6000_control_tx(void *devt, void *osbuf, WMI_PRI_STREAM_ID streamID)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ A_STATUS status = A_OK;
+ struct ar_cookie *cookie = NULL;
+ int i;
+
+ /* take lock to protect ar6000_alloc_cookie() */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ do {
+
+ AR_DEBUG2_PRINTF("ar_contrstatus = ol_tx: skb=0x%x, len=0x%x, sid=%d\n",
+ (A_UINT32)osbuf, A_NETBUF_LEN(osbuf), streamID);
+
+ if ((streamID == WMI_CONTROL_PRI) && (ar->arWMIControlEpFull)) {
+ /* control endpoint is full, don't allocate resources, we
+ * are just going to drop this packet */
+ cookie = NULL;
+ AR_DEBUG_PRINTF(" WMI Control EP full, dropping packet : 0x%X, len:%d \n",
+ (A_UINT32)osbuf, A_NETBUF_LEN(osbuf));
+ } else {
+ cookie = ar6000_alloc_cookie(ar);
+ }
+
+ if (cookie == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ if(logWmiRawMsgs) {
+ A_PRINTF("WMI cmd send, msgNo %d :", wmiSendCmdNum);
+ for(i = 0; i < a_netbuf_to_len(osbuf); i++)
+ A_PRINTF("%x ", ((A_UINT8 *)a_netbuf_to_data(osbuf))[i]);
+ A_PRINTF("\n");
+ }
+
+ wmiSendCmdNum++;
+
+ } while (FALSE);
+
+ if (cookie != NULL) {
+ /* got a structure to send it out on */
+ ar->arTxPending[streamID]++;
+
+ if (streamID != WMI_CONTROL_PRI) {
+ ar->arTotalTxDataPending++;
+ }
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ if (cookie != NULL) {
+ cookie->arc_bp[0] = (A_UINT32)osbuf;
+ cookie->arc_bp[1] = 0;
+ SET_HTC_PACKET_INFO_TX(&cookie->HtcPkt,
+ cookie,
+ A_NETBUF_DATA(osbuf),
+ A_NETBUF_LEN(osbuf),
+ arWMIStream2EndpointID(ar,streamID),
+ AR6K_CONTROL_PKT_TAG);
+ /* this interface is asynchronous, if there is an error, cleanup will happen in the
+ * TX completion callback */
+ HTCSendPkt(ar->arHtcTarget, &cookie->HtcPkt);
+ status = A_OK;
+ }
+
+ return status;
+}
+
+/* indicate tx activity or inactivity on a WMI stream */
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 TrafficClass, A_BOOL Active)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ WMI_PRI_STREAM_ID streamid;
+
+ if (ar->arWmiEnabled) {
+ streamid = wmi_get_stream_id(ar->arWmi, TrafficClass);
+ } else {
+ /* for mbox ping testing, the traffic class is mapped directly as a stream ID,
+ * see handling of AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE in ioctl.c */
+ streamid = (WMI_PRI_STREAM_ID)TrafficClass;
+ }
+
+ /* notify HTC, this may cause credit distribution changes */
+
+ HTCIndicateActivityChange(ar->arHtcTarget,
+ arWMIStream2EndpointID(ar,streamid),
+ Active);
+
+}
+
+module_init(ar6000_init_module);
+module_exit(ar6000_cleanup_module);
+
+/* Init cookie queue */
+static void
+ar6000_cookie_init(AR_SOFTC_T *ar)
+{
+ A_UINT32 i;
+
+ ar->arCookieList = NULL;
+ A_MEMZERO(s_ar_cookie_mem, sizeof(s_ar_cookie_mem));
+
+ for (i = 0; i < MAX_COOKIE_NUM; i++) {
+ ar6000_free_cookie(ar, &s_ar_cookie_mem[i]);
+ }
+}
+
+/* cleanup cookie queue */
+static void
+ar6000_cookie_cleanup(AR_SOFTC_T *ar)
+{
+ /* It is gone .... */
+ ar->arCookieList = NULL;
+}
+
+/* Init cookie queue */
+static void
+ar6000_free_cookie(AR_SOFTC_T *ar, struct ar_cookie * cookie)
+{
+ /* Insert first */
+ A_ASSERT(ar != NULL);
+ A_ASSERT(cookie != NULL);
+ cookie->arc_list_next = ar->arCookieList;
+ ar->arCookieList = cookie;
+}
+
+/* cleanup cookie queue */
+static struct ar_cookie *
+ar6000_alloc_cookie(AR_SOFTC_T *ar)
+{
+ struct ar_cookie *cookie;
+
+ cookie = ar->arCookieList;
+ if(cookie != NULL)
+ {
+ ar->arCookieList = cookie->arc_list_next;
+ }
+
+ return cookie;
+}
+
+#ifdef SEND_EVENT_TO_APP
+/*
+ * This function is used to send event which come from taget to
+ * the application. The buf which send to application is include
+ * the event ID and event content.
+ */
+#define EVENT_ID_LEN 2
+void ar6000_send_event_to_app(AR_SOFTC_T *ar, A_UINT16 eventId,
+ A_UINT8 *datap, int len)
+{
+
+#if (WIRELESS_EXT >= 15)
+
+/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
+
+ char *buf;
+ A_UINT16 size;
+ union iwreq_data wrqu;
+
+ size = len + EVENT_ID_LEN;
+
+ if (size > IW_CUSTOM_MAX) {
+ AR_DEBUG_PRINTF("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
+ eventId, size, IW_CUSTOM_MAX);
+ return;
+ }
+
+ buf = A_MALLOC_NOWAIT(size);
+ A_MEMZERO(buf, size);
+ A_MEMCPY(buf, &eventId, EVENT_ID_LEN);
+ A_MEMCPY(buf+EVENT_ID_LEN, datap, len);
+
+ //AR_DEBUG_PRINTF("event ID = %d,len = %d\n",*(A_UINT16*)buf, size);
+ A_MEMZERO(&wrqu, sizeof(wrqu));
+ wrqu.data.length = size;
+ wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
+
+ A_FREE(buf);
+#endif
+
+
+}
+#endif
+
+
+void
+ar6000_tx_retry_err_event(void *devt)
+{
+ AR_DEBUG2_PRINTF("Tx retries reach maximum!\n");
+}
+
+void
+ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, A_UINT8 snr)
+{
+ AR_DEBUG2_PRINTF("snr threshold range %d, snr %d\n", newThreshold, snr);
+}
+
+void
+ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL newThreshold, A_UINT8 lq)
+{
+ AR_DEBUG2_PRINTF("lq threshold range %d, lq %d\n", newThreshold, lq);
+}
+
+
+
+A_UINT32
+a_copy_to_user(void *to, const void *from, A_UINT32 n)
+{
+ return(copy_to_user(to, from, n));
+}
+
+A_UINT32
+a_copy_from_user(void *to, const void *from, A_UINT32 n)
+{
+ return(copy_from_user(to, from, n));
+}
+
+
+A_STATUS
+ar6000_get_driver_cfg(struct net_device *dev,
+ A_UINT16 cfgParam,
+ void *result)
+{
+
+ A_STATUS ret = 0;
+
+ switch(cfgParam)
+ {
+ case AR6000_DRIVER_CFG_GET_WLANNODECACHING:
+ *((A_UINT32 *)result) = wlanNodeCaching;
+ break;
+ case AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS:
+ *((A_UINT32 *)result) = logWmiRawMsgs;
+ break;
+ default:
+ ret = EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+void
+ar6000_keepalive_rx(void *devt, A_UINT8 configured)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+
+ ar->arKeepaliveConfigured = configured;
+ wake_up(&arEvent);
+}
+
+void
+ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID, WMI_PMKID *pmkidList)
+{
+ A_UINT8 i, j;
+
+ A_PRINTF("Number of Cached PMKIDs is %d\n", numPMKID);
+
+ for (i = 0; i < numPMKID; i++) {
+ A_PRINTF("\nPMKID %d ", i);
+ for (j = 0; j < WMI_PMKID_LEN; j++) {
+ A_PRINTF("%2.2x", pmkidList->pmkid[j]);
+ }
+ pmkidList++;
+ }
+}
+
+#ifdef USER_KEYS
+static A_STATUS
+
+ar6000_reinstall_keys(AR_SOFTC_T *ar, A_UINT8 key_op_ctrl)
+{
+ A_STATUS status = A_OK;
+ struct ieee80211req_key *uik = &ar->user_saved_keys.ucast_ik;
+ struct ieee80211req_key *bik = &ar->user_saved_keys.bcast_ik;
+ CRYPTO_TYPE keyType = ar->user_saved_keys.keyType;
+
+ if (IEEE80211_CIPHER_CCKM_KRK != uik->ik_type) {
+ if (NONE_CRYPT == keyType) {
+ goto _reinstall_keys_out;
+ }
+
+ if (uik->ik_keylen) {
+ status = wmi_addKey_cmd(ar->arWmi, uik->ik_keyix,
+ ar->user_saved_keys.keyType, PAIRWISE_USAGE,
+ uik->ik_keylen, (A_UINT8 *)&uik->ik_keyrsc,
+ uik->ik_keydata, key_op_ctrl, SYNC_BEFORE_WMIFLAG);
+ }
+
+ } else {
+ status = wmi_add_krk_cmd(ar->arWmi, uik->ik_keydata);
+ }
+
+ if (IEEE80211_CIPHER_CCKM_KRK != bik->ik_type) {
+ if (NONE_CRYPT == keyType) {
+ goto _reinstall_keys_out;
+ }
+
+ if (bik->ik_keylen) {
+ status = wmi_addKey_cmd(ar->arWmi, bik->ik_keyix,
+ ar->user_saved_keys.keyType, GROUP_USAGE,
+ bik->ik_keylen, (A_UINT8 *)&bik->ik_keyrsc,
+ bik->ik_keydata, key_op_ctrl, NO_SYNC_WMIFLAG);
+ }
+ } else {
+ status = wmi_add_krk_cmd(ar->arWmi, bik->ik_keydata);
+ }
+
+_reinstall_keys_out:
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
+ ar->user_key_ctrl = 0;
+
+ return status;
+}
+#endif /* USER_KEYS */
+
+
+void
+ar6000_dset_open_req(
+ void *context,
+ A_UINT32 id,
+ A_UINT32 targHandle,
+ A_UINT32 targReplyFn,
+ A_UINT32 targReplyArg)
+{
+}
+
+void
+ar6000_dset_close(
+ void *context,
+ A_UINT32 access_cookie)
+{
+ return;
+}
+
+void
+ar6000_dset_data_req(
+ void *context,
+ A_UINT32 accessCookie,
+ A_UINT32 offset,
+ A_UINT32 length,
+ A_UINT32 targBuf,
+ A_UINT32 targReplyFn,
+ A_UINT32 targReplyArg)
+{
+}
--- /dev/null
+++ b/drivers/ar6000/ar6000/ar6000_drv.h
@@ -0,0 +1,361 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _AR6000_H_
+#define _AR6000_H_
+
+#include <linux/version.h>
+
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/skbuff.h>
+#include <linux/if_ether.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <net/iw_handler.h>
+#include <linux/if_arp.h>
+#include <linux/ip.h>
+#include <linux/semaphore.h>
+#include <linux/wireless.h>
+#include <linux/module.h>
+#include <asm/io.h>
+
+#include <a_config.h>
+#include <athdefs.h>
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include "a_drv.h"
+#include "bmi.h"
+#include <ieee80211.h>
+#include <ieee80211_ioctl.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include "gpio_api.h"
+#include "gpio.h"
+#include <host_version.h>
+#include <linux/rtnetlink.h>
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#include "AR6Khwreg.h"
+#include "ar6000_api.h"
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#include <testcmd.h>
+#endif
+
+#include "targaddrs.h"
+#include "dbglog_api.h"
+#include "ar6000_diag.h"
+#include "common_drv.h"
+
+#ifndef __dev_put
+#define __dev_put(dev) dev_put(dev)
+#endif
+
+#ifdef USER_KEYS
+
+#define USER_SAVEDKEYS_STAT_INIT 0
+#define USER_SAVEDKEYS_STAT_RUN 1
+
+// TODO this needs to move into the AR_SOFTC struct
+struct USER_SAVEDKEYS {
+ struct ieee80211req_key ucast_ik;
+ struct ieee80211req_key bcast_ik;
+ CRYPTO_TYPE keyType;
+ A_BOOL keyOk;
+};
+#endif
+
+#define DBG_INFO 0x00000001
+#define DBG_ERROR 0x00000002
+#define DBG_WARNING 0x00000004
+#define DBG_SDIO 0x00000008
+#define DBG_HIF 0x00000010
+#define DBG_HTC 0x00000020
+#define DBG_WMI 0x00000040
+#define DBG_WMI2 0x00000080
+#define DBG_DRIVER 0x00000100
+
+#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING)
+
+
+#ifdef DEBUG
+#define AR_DEBUG_PRINTF(args...) if (debugdriver) A_PRINTF(args);
+#define AR_DEBUG2_PRINTF(args...) if (debugdriver >= 2) A_PRINTF(args);
+extern int debugdriver;
+#else
+#define AR_DEBUG_PRINTF(args...)
+#define AR_DEBUG2_PRINTF(args...)
+#endif
+
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MAX_AR6000 1
+#define AR6000_MAX_RX_BUFFERS 16
+#define AR6000_BUFFER_SIZE 1664
+#define AR6000_TX_TIMEOUT 10
+#define AR6000_ETH_ADDR_LEN 6
+#define AR6000_MAX_ENDPOINTS 4
+#define MAX_NODE_NUM 15
+#define MAX_COOKIE_NUM 150
+#define AR6000_HB_CHALLENGE_RESP_FREQ_DEFAULT 1
+#define AR6000_HB_CHALLENGE_RESP_MISS_THRES_DEFAULT 1
+
+enum {
+ DRV_HB_CHALLENGE = 0,
+ APP_HB_CHALLENGE
+};
+
+/* HTC RAW streams */
+typedef enum _HTC_RAW_STREAM_ID {
+ HTC_RAW_STREAM_NOT_MAPPED = -1,
+ HTC_RAW_STREAM_0 = 0,
+ HTC_RAW_STREAM_1 = 1,
+ HTC_RAW_STREAM_2 = 2,
+ HTC_RAW_STREAM_3 = 3,
+ HTC_RAW_STREAM_NUM_MAX
+} HTC_RAW_STREAM_ID;
+
+#define RAW_HTC_READ_BUFFERS_NUM 4
+#define RAW_HTC_WRITE_BUFFERS_NUM 4
+
+typedef struct {
+ int currPtr;
+ int length;
+ unsigned char data[AR6000_BUFFER_SIZE];
+ HTC_PACKET HTCPacket;
+} raw_htc_buffer;
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/*
+ * add TCMD_MODE besides wmi and bypasswmi
+ * in TCMD_MODE, only few TCMD releated wmi commands
+ * counld be hanlder
+ */
+enum {
+ AR6000_WMI_MODE = 0,
+ AR6000_BYPASS_MODE,
+ AR6000_TCMD_MODE,
+ AR6000_WLAN_MODE
+};
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+struct ar_wep_key {
+ A_UINT8 arKeyIndex;
+ A_UINT8 arKeyLen;
+ A_UINT8 arKey[64];
+} ;
+
+struct ar_node_mapping {
+ A_UINT8 macAddress[6];
+ A_UINT8 epId;
+ A_UINT8 txPending;
+};
+
+struct ar_cookie {
+ A_UINT32 arc_bp[2]; /* Must be first field */
+ HTC_PACKET HtcPkt; /* HTC packet wrapper */
+ struct ar_cookie *arc_list_next;
+};
+
+struct ar_hb_chlng_resp {
+ A_TIMER timer;
+ A_UINT32 frequency;
+ A_UINT32 seqNum;
+ A_BOOL outstanding;
+ A_UINT8 missCnt;
+ A_UINT8 missThres;
+};
+
+typedef struct ar6_softc {
+ struct net_device *arNetDev; /* net_device pointer */
+ void *arWmi;
+ int arTxPending[WMI_PRI_MAX_COUNT];
+ int arTotalTxDataPending;
+ A_UINT8 arNumDataEndPts;
+ A_BOOL arWmiEnabled;
+ A_BOOL arWmiReady;
+ A_BOOL arConnected;
+ A_BOOL arRadioSwitch;
+ HTC_HANDLE arHtcTarget;
+ void *arHifDevice;
+ spinlock_t arLock;
+ struct semaphore arSem;
+ int arRxBuffers[WMI_PRI_MAX_COUNT];
+ int arSsidLen;
+ u_char arSsid[32];
+ A_UINT8 arNetworkType;
+ A_UINT8 arDot11AuthMode;
+ A_UINT8 arAuthMode;
+ A_UINT8 arPairwiseCrypto;
+ A_UINT8 arPairwiseCryptoLen;
+ A_UINT8 arGroupCrypto;
+ A_UINT8 arGroupCryptoLen;
+ A_UINT8 arDefTxKeyIndex;
+ struct ar_wep_key arWepKeyList[WMI_MAX_KEY_INDEX + 1];
+ A_UINT8 arBssid[6];
+ A_UINT8 arReqBssid[6];
+ A_UINT16 arChannelHint;
+ A_UINT16 arBssChannel;
+ A_UINT16 arListenInterval;
+ struct ar6000_version arVersion;
+ A_UINT32 arTargetType;
+ A_INT8 arRssi;
+ A_UINT8 arTxPwr;
+ A_BOOL arTxPwrSet;
+ A_INT32 arBitRate;
+ struct net_device_stats arNetStats;
+ struct iw_statistics arIwStats;
+ A_INT8 arNumChannels;
+ A_UINT16 arChannelList[32];
+ A_UINT32 arRegCode;
+ A_BOOL statsUpdatePending;
+ TARGET_STATS arTargetStats;
+ A_INT8 arMaxRetries;
+ A_UINT8 arPhyCapability;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ A_UINT8 tcmdRxReport;
+ A_UINT32 tcmdRxTotalPkt;
+ A_INT32 tcmdRxRssi;
+ A_UINT32 tcmdPm;
+ A_UINT32 arTargetMode;
+#endif
+ AR6000_WLAN_STATE arWlanState;
+ struct ar_node_mapping arNodeMap[MAX_NODE_NUM];
+ A_UINT8 arIbssPsEnable;
+ A_UINT8 arNodeNum;
+ A_UINT8 arNexEpId;
+ struct ar_cookie *arCookieList;
+ A_UINT16 arRateMask;
+ A_UINT8 arSkipScan;
+ A_UINT16 arBeaconInterval;
+ A_BOOL arConnectPending;
+ A_BOOL arWmmEnabled;
+ struct ar_hb_chlng_resp arHBChallengeResp;
+ A_UINT8 arKeepaliveConfigured;
+ A_UINT32 arMgmtFilter;
+ HTC_ENDPOINT_ID arWmi2EpMapping[WMI_PRI_MAX_COUNT];
+ WMI_PRI_STREAM_ID arEp2WmiMapping[ENDPOINT_MAX];
+#ifdef HTC_RAW_INTERFACE
+ HTC_ENDPOINT_ID arRaw2EpMapping[HTC_RAW_STREAM_NUM_MAX];
+ HTC_RAW_STREAM_ID arEp2RawMapping[ENDPOINT_MAX];
+ struct semaphore raw_htc_read_sem[HTC_RAW_STREAM_NUM_MAX];
+ struct semaphore raw_htc_write_sem[HTC_RAW_STREAM_NUM_MAX];
+ wait_queue_head_t raw_htc_read_queue[HTC_RAW_STREAM_NUM_MAX];
+ wait_queue_head_t raw_htc_write_queue[HTC_RAW_STREAM_NUM_MAX];
+ raw_htc_buffer *raw_htc_read_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_READ_BUFFERS_NUM];
+ raw_htc_buffer *raw_htc_write_buffer[HTC_RAW_STREAM_NUM_MAX][RAW_HTC_WRITE_BUFFERS_NUM];
+ A_BOOL write_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+ A_BOOL read_buffer_available[HTC_RAW_STREAM_NUM_MAX];
+#endif
+ A_BOOL arNetQueueStopped;
+ A_BOOL arRawIfInit;
+ int arDeviceIndex;
+ COMMON_CREDIT_STATE_INFO arCreditStateInfo;
+ A_BOOL arWMIControlEpFull;
+ A_BOOL dbgLogFetchInProgress;
+ A_UCHAR log_buffer[DBGLOG_HOST_LOG_BUFFER_SIZE];
+ A_UINT32 log_cnt;
+ A_UINT32 dbglog_init_done;
+ A_UINT32 arConnectCtrlFlags;
+ A_UINT32 scan_complete;
+#ifdef USER_KEYS
+ A_INT32 user_savedkeys_stat;
+ A_UINT32 user_key_ctrl;
+ struct USER_SAVEDKEYS user_saved_keys;
+#endif
+} AR_SOFTC_T;
+
+
+#define arWMIStream2EndpointID(ar,wmi) (ar)->arWmi2EpMapping[(wmi)]
+#define arSetWMIStream2EndpointIDMap(ar,wmi,ep) \
+{ (ar)->arWmi2EpMapping[(wmi)] = (ep); \
+ (ar)->arEp2WmiMapping[(ep)] = (wmi); }
+#define arEndpoint2WMIStreamID(ar,ep) (ar)->arEp2WmiMapping[(ep)]
+
+#define arRawIfEnabled(ar) (ar)->arRawIfInit
+#define arRawStream2EndpointID(ar,raw) (ar)->arRaw2EpMapping[(raw)]
+#define arSetRawStream2EndpointIDMap(ar,raw,ep) \
+{ (ar)->arRaw2EpMapping[(raw)] = (ep); \
+ (ar)->arEp2RawMapping[(ep)] = (raw); }
+#define arEndpoint2RawStreamID(ar,ep) (ar)->arEp2RawMapping[(ep)]
+
+struct ar_giwscan_param {
+ char *current_ev;
+ char *end_buf;
+ A_BOOL firstPass;
+};
+
+#define AR6000_STAT_INC(ar, stat) (ar->arNetStats.stat++)
+
+#define AR6000_SPIN_LOCK(lock, param) do { \
+ if (irqs_disabled()) { \
+ AR_DEBUG_PRINTF("IRQs disabled:AR6000_LOCK\n"); \
+ } \
+ spin_lock_bh(lock); \
+} while (0)
+
+#define AR6000_SPIN_UNLOCK(lock, param) do { \
+ if (irqs_disabled()) { \
+ AR_DEBUG_PRINTF("IRQs disabled: AR6000_UNLOCK\n"); \
+ } \
+ spin_unlock_bh(lock); \
+} while (0)
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
+void ar6000_ioctl_iwsetup(struct iw_handler_def *def);
+void ar6000_gpio_init(void);
+void ar6000_init_profile_info(AR_SOFTC_T *ar);
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar);
+int ar6000_init(struct net_device *dev);
+int ar6000_dbglog_get_debug_logs(AR_SOFTC_T *ar);
+A_STATUS ar6000_SetHTCBlockSize(AR_SOFTC_T *ar);
+
+#ifdef HTC_RAW_INTERFACE
+
+#ifndef __user
+#define __user
+#endif
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar);
+int ar6000_htc_raw_close(AR_SOFTC_T *ar);
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar,
+ HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t count);
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar,
+ HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t count);
+
+#endif /* HTC_RAW_INTERFACE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _AR6000_H_ */
--- /dev/null
+++ b/drivers/ar6000/ar6000/ar6000_raw_if.c
@@ -0,0 +1,439 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "ar6000_drv.h"
+
+#ifdef HTC_RAW_INTERFACE
+
+static void
+ar6000_htc_raw_read_cb(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ raw_htc_buffer *busy;
+ HTC_RAW_STREAM_ID streamID;
+
+ busy = (raw_htc_buffer *)pPacket->pPktContext;
+ A_ASSERT(busy != NULL);
+
+ if (pPacket->Status == A_ECANCELED) {
+ /*
+ * HTC provides A_ECANCELED status when it doesn't want to be refilled
+ * (probably due to a shutdown)
+ */
+ return;
+ }
+
+ streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+ A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+
+#ifdef CF
+ if (down_trylock(&ar->raw_htc_read_sem[streamID])) {
+#else
+ if (down_interruptible(&ar->raw_htc_read_sem[streamID])) {
+#endif /* CF */
+ AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
+ }
+
+ A_ASSERT((pPacket->Status != A_OK) ||
+ (pPacket->pBuffer == (busy->data + HTC_HEADER_LEN)));
+
+ busy->length = pPacket->ActualLength + HTC_HEADER_LEN;
+ busy->currPtr = HTC_HEADER_LEN;
+ ar->read_buffer_available[streamID] = TRUE;
+ //AR_DEBUG_PRINTF("raw read cb: 0x%X 0x%X \n", busy->currPtr,busy->length);
+ up(&ar->raw_htc_read_sem[streamID]);
+
+ /* Signal the waiting process */
+ AR_DEBUG2_PRINTF("Waking up the StreamID(%d) read process\n", streamID);
+ wake_up_interruptible(&ar->raw_htc_read_queue[streamID]);
+}
+
+static void
+ar6000_htc_raw_write_cb(void *Context, HTC_PACKET *pPacket)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)Context;
+ raw_htc_buffer *free;
+ HTC_RAW_STREAM_ID streamID;
+
+ free = (raw_htc_buffer *)pPacket->pPktContext;
+ A_ASSERT(free != NULL);
+
+ if (pPacket->Status == A_ECANCELED) {
+ /*
+ * HTC provides A_ECANCELED status when it doesn't want to be refilled
+ * (probably due to a shutdown)
+ */
+ return;
+ }
+
+ streamID = arEndpoint2RawStreamID(ar,pPacket->Endpoint);
+ A_ASSERT(streamID != HTC_RAW_STREAM_NOT_MAPPED);
+
+#ifdef CF
+ if (down_trylock(&ar->raw_htc_write_sem[streamID])) {
+#else
+ if (down_interruptible(&ar->raw_htc_write_sem[streamID])) {
+#endif
+ AR_DEBUG2_PRINTF("Unable to down the semaphore\n");
+ }
+
+ A_ASSERT(pPacket->pBuffer == (free->data + HTC_HEADER_LEN));
+
+ free->length = 0;
+ ar->write_buffer_available[streamID] = TRUE;
+ up(&ar->raw_htc_write_sem[streamID]);
+
+ /* Signal the waiting process */
+ AR_DEBUG2_PRINTF("Waking up the StreamID(%d) write process\n", streamID);
+ wake_up_interruptible(&ar->raw_htc_write_queue[streamID]);
+}
+
+/* connect to a service */
+static A_STATUS ar6000_connect_raw_service(AR_SOFTC_T *ar,
+ HTC_RAW_STREAM_ID StreamID)
+{
+ A_STATUS status;
+ HTC_SERVICE_CONNECT_RESP response;
+ A_UINT8 streamNo;
+ HTC_SERVICE_CONNECT_REQ connect;
+
+ do {
+
+ A_MEMZERO(&connect,sizeof(connect));
+ /* pass the stream ID as meta data to the RAW streams service */
+ streamNo = (A_UINT8)StreamID;
+ connect.pMetaData = &streamNo;
+ connect.MetaDataLength = sizeof(A_UINT8);
+ /* these fields are the same for all endpoints */
+ connect.EpCallbacks.pContext = ar;
+ connect.EpCallbacks.EpTxComplete = ar6000_htc_raw_write_cb;
+ connect.EpCallbacks.EpRecv = ar6000_htc_raw_read_cb;
+ /* simple interface, we don't need these optional callbacks */
+ connect.EpCallbacks.EpRecvRefill = NULL;
+ connect.EpCallbacks.EpSendFull = NULL;
+ connect.MaxSendQueueDepth = RAW_HTC_WRITE_BUFFERS_NUM;
+
+ /* connect to the raw streams service, we may be able to get 1 or more
+ * connections, depending on WHAT is running on the target */
+ connect.ServiceID = HTC_RAW_STREAMS_SVC;
+
+ A_MEMZERO(&response,sizeof(response));
+
+ /* try to connect to the raw stream, it is okay if this fails with
+ * status HTC_SERVICE_NO_MORE_EP */
+ status = HTCConnectService(ar->arHtcTarget,
+ &connect,
+ &response);
+
+ if (A_FAILED(status)) {
+ if (response.ConnectRespCode == HTC_SERVICE_NO_MORE_EP) {
+ AR_DEBUG_PRINTF("HTC RAW , No more streams allowed \n");
+ status = A_OK;
+ }
+ break;
+ }
+
+ /* set endpoint mapping for the RAW HTC streams */
+ arSetRawStream2EndpointIDMap(ar,StreamID,response.Endpoint);
+
+ AR_DEBUG_PRINTF("HTC RAW : stream ID: %d, endpoint: %d\n",
+ StreamID, arRawStream2EndpointID(ar,StreamID));
+
+ } while (FALSE);
+
+ return status;
+}
+
+int ar6000_htc_raw_open(AR_SOFTC_T *ar)
+{
+ A_STATUS status;
+ int streamID, endPt, count2;
+ raw_htc_buffer *buffer;
+ HTC_SERVICE_ID servicepriority;
+
+ A_ASSERT(ar->arHtcTarget != NULL);
+
+ /* wait for target */
+ status = HTCWaitTarget(ar->arHtcTarget);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF("HTCWaitTarget failed (%d)\n", status);
+ return -ENODEV;
+ }
+
+ for (endPt = 0; endPt < ENDPOINT_MAX; endPt++) {
+ ar->arEp2RawMapping[endPt] = HTC_RAW_STREAM_NOT_MAPPED;
+ }
+
+ for (streamID = HTC_RAW_STREAM_0; streamID < HTC_RAW_STREAM_NUM_MAX; streamID++) {
+ /* Initialize the data structures */
+ init_MUTEX(&ar->raw_htc_read_sem[streamID]);
+ init_MUTEX(&ar->raw_htc_write_sem[streamID]);
+ init_waitqueue_head(&ar->raw_htc_read_queue[streamID]);
+ init_waitqueue_head(&ar->raw_htc_write_queue[streamID]);
+
+ /* try to connect to the raw service */
+ status = ar6000_connect_raw_service(ar,streamID);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (arRawStream2EndpointID(ar,streamID) == 0) {
+ break;
+ }
+
+ for (count2 = 0; count2 < RAW_HTC_READ_BUFFERS_NUM; count2 ++) {
+ /* Initialize the receive buffers */
+ buffer = ar->raw_htc_write_buffer[streamID][count2];
+ memset(buffer, 0, sizeof(raw_htc_buffer));
+ buffer = ar->raw_htc_read_buffer[streamID][count2];
+ memset(buffer, 0, sizeof(raw_htc_buffer));
+
+ SET_HTC_PACKET_INFO_RX_REFILL(&buffer->HTCPacket,
+ buffer,
+ buffer->data,
+ AR6000_BUFFER_SIZE,
+ arRawStream2EndpointID(ar,streamID));
+
+ /* Queue buffers to HTC for receive */
+ if ((status = HTCAddReceivePkt(ar->arHtcTarget, &buffer->HTCPacket)) != A_OK)
+ {
+ BMIInit();
+ return -EIO;
+ }
+ }
+
+ for (count2 = 0; count2 < RAW_HTC_WRITE_BUFFERS_NUM; count2 ++) {
+ /* Initialize the receive buffers */
+ buffer = ar->raw_htc_write_buffer[streamID][count2];
+ memset(buffer, 0, sizeof(raw_htc_buffer));
+ }
+
+ ar->read_buffer_available[streamID] = FALSE;
+ ar->write_buffer_available[streamID] = TRUE;
+ }
+
+ if (A_FAILED(status)) {
+ return -EIO;
+ }
+
+ AR_DEBUG_PRINTF("HTC RAW, number of streams the target supports: %d \n", streamID);
+
+ servicepriority = HTC_RAW_STREAMS_SVC; /* only 1 */
+
+ /* set callbacks and priority list */
+ HTCSetCreditDistribution(ar->arHtcTarget,
+ ar,
+ NULL, /* use default */
+ NULL, /* use default */
+ &servicepriority,
+ 1);
+
+ /* Start the HTC component */
+ if ((status = HTCStart(ar->arHtcTarget)) != A_OK) {
+ BMIInit();
+ return -EIO;
+ }
+
+ (ar)->arRawIfInit = TRUE;
+
+ return 0;
+}
+
+int ar6000_htc_raw_close(AR_SOFTC_T *ar)
+{
+ A_PRINTF("ar6000_htc_raw_close called \n");
+ HTCStop(ar->arHtcTarget);
+
+ /* reset the device */
+ ar6000_reset_device(ar->arHifDevice, ar->arTargetType);
+ /* Initialize the BMI component */
+ BMIInit();
+
+ return 0;
+}
+
+raw_htc_buffer *
+get_filled_buffer(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID)
+{
+ int count;
+ raw_htc_buffer *busy;
+
+ /* Check for data */
+ for (count = 0; count < RAW_HTC_READ_BUFFERS_NUM; count ++) {
+ busy = ar->raw_htc_read_buffer[StreamID][count];
+ if (busy->length) {
+ break;
+ }
+ }
+ if (busy->length) {
+ ar->read_buffer_available[StreamID] = TRUE;
+ } else {
+ ar->read_buffer_available[StreamID] = FALSE;
+ }
+
+ return busy;
+}
+
+ssize_t ar6000_htc_raw_read(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t length)
+{
+ int readPtr;
+ raw_htc_buffer *busy;
+
+ if (arRawStream2EndpointID(ar,StreamID) == 0) {
+ AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID);
+ return -EFAULT;
+ }
+
+ if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+
+ busy = get_filled_buffer(ar,StreamID);
+ while (!ar->read_buffer_available[StreamID]) {
+ up(&ar->raw_htc_read_sem[StreamID]);
+
+ /* Wait for the data */
+ AR_DEBUG2_PRINTF("Sleeping StreamID(%d) read process\n", StreamID);
+ if (wait_event_interruptible(ar->raw_htc_read_queue[StreamID],
+ ar->read_buffer_available[StreamID]))
+ {
+ return -EINTR;
+ }
+ if (down_interruptible(&ar->raw_htc_read_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+ busy = get_filled_buffer(ar,StreamID);
+ }
+
+ /* Read the data */
+ readPtr = busy->currPtr;
+ if (length > busy->length - HTC_HEADER_LEN) {
+ length = busy->length - HTC_HEADER_LEN;
+ }
+ if (copy_to_user(buffer, &busy->data[readPtr], length)) {
+ up(&ar->raw_htc_read_sem[StreamID]);
+ return -EFAULT;
+ }
+
+ busy->currPtr += length;
+
+ //AR_DEBUG_PRINTF("raw read ioctl: currPTR : 0x%X 0x%X \n", busy->currPtr,busy->length);
+
+ if (busy->currPtr == busy->length)
+ {
+ busy->currPtr = 0;
+ busy->length = 0;
+ HTC_PACKET_RESET_RX(&busy->HTCPacket);
+ //AR_DEBUG_PRINTF("raw read ioctl: ep for packet:%d \n", busy->HTCPacket.Endpoint);
+ HTCAddReceivePkt(ar->arHtcTarget, &busy->HTCPacket);
+ }
+ ar->read_buffer_available[StreamID] = FALSE;
+ up(&ar->raw_htc_read_sem[StreamID]);
+
+ return length;
+}
+
+static raw_htc_buffer *
+get_free_buffer(AR_SOFTC_T *ar, HTC_ENDPOINT_ID StreamID)
+{
+ int count;
+ raw_htc_buffer *free;
+
+ free = NULL;
+ for (count = 0; count < RAW_HTC_WRITE_BUFFERS_NUM; count ++) {
+ free = ar->raw_htc_write_buffer[StreamID][count];
+ if (free->length == 0) {
+ break;
+ }
+ }
+ if (!free->length) {
+ ar->write_buffer_available[StreamID] = TRUE;
+ } else {
+ ar->write_buffer_available[StreamID] = FALSE;
+ }
+
+ return free;
+}
+
+ssize_t ar6000_htc_raw_write(AR_SOFTC_T *ar, HTC_RAW_STREAM_ID StreamID,
+ char __user *buffer, size_t length)
+{
+ int writePtr;
+ raw_htc_buffer *free;
+
+ if (arRawStream2EndpointID(ar,StreamID) == 0) {
+ AR_DEBUG_PRINTF("StreamID(%d) not connected! \n", StreamID);
+ return -EFAULT;
+ }
+
+ if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+
+ /* Search for a free buffer */
+ free = get_free_buffer(ar,StreamID);
+
+ /* Check if there is space to write else wait */
+ while (!ar->write_buffer_available[StreamID]) {
+ up(&ar->raw_htc_write_sem[StreamID]);
+
+ /* Wait for buffer to become free */
+ AR_DEBUG2_PRINTF("Sleeping StreamID(%d) write process\n", StreamID);
+ if (wait_event_interruptible(ar->raw_htc_write_queue[StreamID],
+ ar->write_buffer_available[StreamID]))
+ {
+ return -EINTR;
+ }
+ if (down_interruptible(&ar->raw_htc_write_sem[StreamID])) {
+ return -ERESTARTSYS;
+ }
+ free = get_free_buffer(ar,StreamID);
+ }
+
+ /* Send the data */
+ writePtr = HTC_HEADER_LEN;
+ if (length > (AR6000_BUFFER_SIZE - HTC_HEADER_LEN)) {
+ length = AR6000_BUFFER_SIZE - HTC_HEADER_LEN;
+ }
+
+ if (copy_from_user(&free->data[writePtr], buffer, length)) {
+ up(&ar->raw_htc_read_sem[StreamID]);
+ return -EFAULT;
+ }
+
+ free->length = length;
+
+ SET_HTC_PACKET_INFO_TX(&free->HTCPacket,
+ free,
+ &free->data[writePtr],
+ length,
+ arRawStream2EndpointID(ar,StreamID),
+ AR6K_DATA_PKT_TAG);
+
+ HTCSendPkt(ar->arHtcTarget,&free->HTCPacket);
+
+ ar->write_buffer_available[StreamID] = FALSE;
+ up(&ar->raw_htc_write_sem[StreamID]);
+
+ return length;
+}
+#endif /* HTC_RAW_INTERFACE */
--- /dev/null
+++ b/drivers/ar6000/ar6000/ar6xapi_linux.h
@@ -0,0 +1,128 @@
+#ifndef _AR6XAPI_LINUX_H
+#define _AR6XAPI_LINUX_H
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ar6_softc;
+
+void ar6000_ready_event(void *devt, A_UINT8 *datap, A_UINT8 phyCap);
+A_UINT8 ar6000_iptos_to_userPriority(A_UINT8 *pkt);
+A_STATUS ar6000_control_tx(void *devt, void *osbuf, WMI_PRI_STREAM_ID streamID);
+void ar6000_connect_event(struct ar6_softc *ar, A_UINT16 channel,
+ A_UINT8 *bssid, A_UINT16 listenInterval,
+ A_UINT16 beaconInterval, NETWORK_TYPE networkType,
+ A_UINT8 beaconIeLen, A_UINT8 assocReqLen,
+ A_UINT8 assocRespLen,A_UINT8 *assocInfo);
+void ar6000_disconnect_event(struct ar6_softc *ar, A_UINT8 reason,
+ A_UINT8 *bssid, A_UINT8 assocRespLen,
+ A_UINT8 *assocInfo, A_UINT16 protocolReasonStatus);
+void ar6000_tkip_micerr_event(struct ar6_softc *ar, A_UINT8 keyid,
+ A_BOOL ismcast);
+void ar6000_bitrate_rx(void *devt, A_INT32 rateKbps);
+void ar6000_channelList_rx(void *devt, A_INT8 numChan, A_UINT16 *chanList);
+void ar6000_regDomain_event(struct ar6_softc *ar, A_UINT32 regCode);
+void ar6000_txPwr_rx(void *devt, A_UINT8 txPwr);
+void ar6000_keepalive_rx(void *devt, A_UINT8 configured);
+void ar6000_neighborReport_event(struct ar6_softc *ar, int numAps,
+ WMI_NEIGHBOR_INFO *info);
+void ar6000_set_numdataendpts(struct ar6_softc *ar, A_UINT32 num);
+void ar6000_scanComplete_event(struct ar6_softc *ar, A_STATUS status);
+void ar6000_targetStats_event(struct ar6_softc *ar, WMI_TARGET_STATS *pStats);
+void ar6000_rssiThreshold_event(struct ar6_softc *ar,
+ WMI_RSSI_THRESHOLD_VAL newThreshold,
+ A_INT16 rssi);
+void ar6000_reportError_event(struct ar6_softc *, WMI_TARGET_ERROR_VAL errorVal);
+void ar6000_cac_event(struct ar6_softc *ar, A_UINT8 ac, A_UINT8 cac_indication,
+ A_UINT8 statusCode, A_UINT8 *tspecSuggestion);
+void ar6000_hbChallengeResp_event(struct ar6_softc *, A_UINT32 cookie, A_UINT32 source);
+void
+ar6000_roam_tbl_event(struct ar6_softc *ar, WMI_TARGET_ROAM_TBL *pTbl);
+
+void
+ar6000_roam_data_event(struct ar6_softc *ar, WMI_TARGET_ROAM_DATA *p);
+
+void
+ar6000_wow_list_event(struct ar6_softc *ar, A_UINT8 num_filters,
+ WMI_GET_WOW_LIST_REPLY *wow_reply);
+
+void ar6000_pmkid_list_event(void *devt, A_UINT8 numPMKID,
+ WMI_PMKID *pmkidList);
+
+void ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values);
+void ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value);
+void ar6000_gpio_ack_rx(void);
+
+void ar6000_dbglog_init_done(struct ar6_softc *ar);
+
+#ifdef SEND_EVENT_TO_APP
+void ar6000_send_event_to_app(struct ar6_softc *ar, A_UINT16 eventId, A_UINT8 *datap, int len);
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+void ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len);
+#endif
+
+void ar6000_tx_retry_err_event(void *devt);
+
+void ar6000_snrThresholdEvent_rx(void *devt,
+ WMI_SNR_THRESHOLD_VAL newThreshold,
+ A_UINT8 snr);
+
+void ar6000_lqThresholdEvent_rx(void *devt, WMI_LQ_THRESHOLD_VAL range, A_UINT8 lqVal);
+
+
+void ar6000_ratemask_rx(void *devt, A_UINT16 ratemask);
+
+A_STATUS ar6000_get_driver_cfg(struct net_device *dev,
+ A_UINT16 cfgParam,
+ void *result);
+void ar6000_bssInfo_event_rx(struct ar6_softc *ar, A_UINT8 *data, int len);
+
+void ar6000_dbglog_event(struct ar6_softc *ar, A_UINT32 dropped,
+ A_INT8 *buffer, A_UINT32 length);
+
+int ar6000_dbglog_get_debug_logs(struct ar6_softc *ar);
+
+void ar6000_indicate_tx_activity(void *devt, A_UINT8 trafficClass, A_BOOL Active);
+
+void ar6000_dset_open_req(void *devt,
+ A_UINT32 id,
+ A_UINT32 targ_handle,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+void ar6000_dset_close(void *devt, A_UINT32 access_cookie);
+void ar6000_dset_data_req(void *devt,
+ A_UINT32 access_cookie,
+ A_UINT32 offset,
+ A_UINT32 length,
+ A_UINT32 targ_buf,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/ar6000/athdrv_linux.h
@@ -0,0 +1,993 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _ATHDRV_LINUX_H
+#define _ATHDRV_LINUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ * There are two types of ioctl's here: Standard ioctls and
+ * eXtended ioctls. All extended ioctls (XIOCTL) are multiplexed
+ * off of the single ioctl command, AR6000_IOCTL_EXTENDED. The
+ * arguments for every XIOCTL starts with a 32-bit command word
+ * that is used to select which extended ioctl is in use. After
+ * the command word are command-specific arguments.
+ */
+
+/* Linux standard Wireless Extensions, private ioctl interfaces */
+#define IEEE80211_IOCTL_SETPARAM (SIOCIWFIRSTPRIV+0)
+#define IEEE80211_IOCTL_GETPARAM (SIOCIWFIRSTPRIV+1)
+#define IEEE80211_IOCTL_SETKEY (SIOCIWFIRSTPRIV+2)
+#define IEEE80211_IOCTL_SETWMMPARAMS (SIOCIWFIRSTPRIV+3)
+#define IEEE80211_IOCTL_DELKEY (SIOCIWFIRSTPRIV+4)
+#define IEEE80211_IOCTL_GETWMMPARAMS (SIOCIWFIRSTPRIV+5)
+#define IEEE80211_IOCTL_SETOPTIE (SIOCIWFIRSTPRIV+6)
+#define IEEE80211_IOCTL_SETMLME (SIOCIWFIRSTPRIV+7)
+//#define IEEE80211_IOCTL_GETOPTIE (SIOCIWFIRSTPRIV+7)
+#define IEEE80211_IOCTL_ADDPMKID (SIOCIWFIRSTPRIV+8)
+//#define IEEE80211_IOCTL_SETAUTHALG (SIOCIWFIRSTPRIV+10)
+#define IEEE80211_IOCTL_LASTONE (SIOCIWFIRSTPRIV+9)
+
+
+
+/* ====WMI Ioctls==== */
+/*
+ *
+ * Many ioctls simply provide WMI services to application code:
+ * an application makes such an ioctl call with a set of arguments
+ * that are packaged into the corresponding WMI message, and sent
+ * to the Target.
+ */
+
+#define AR6000_IOCTL_WMI_GETREV (SIOCIWFIRSTPRIV+10)
+/*
+ * arguments:
+ * ar6000_version *revision
+ */
+
+#define AR6000_IOCTL_WMI_SETPWR (SIOCIWFIRSTPRIV+11)
+/*
+ * arguments:
+ * WMI_POWER_MODE_CMD pwrModeCmd (see include/wmi.h)
+ * uses: WMI_SET_POWER_MODE_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETSCAN (SIOCIWFIRSTPRIV+12)
+/*
+ * arguments:
+ * WMI_SCAN_PARAMS_CMD scanParams (see include/wmi.h)
+ * uses: WMI_SET_SCAN_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETLISTENINT (SIOCIWFIRSTPRIV+13)
+/*
+ * arguments:
+ * UINT32 listenInterval
+ * uses: WMI_SET_LISTEN_INT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SETBSSFILTER (SIOCIWFIRSTPRIV+14)
+/*
+ * arguments:
+ * WMI_BSS_FILTER filter (see include/wmi.h)
+ * uses: WMI_SET_BSS_FILTER_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_CHANNELPARAMS (SIOCIWFIRSTPRIV+16)
+/*
+ * arguments:
+ * WMI_CHANNEL_PARAMS_CMD chParams
+ * uses: WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PROBEDSSID (SIOCIWFIRSTPRIV+17)
+/*
+ * arguments:
+ * WMI_PROBED_SSID_CMD probedSsids (see include/wmi.h)
+ * uses: WMI_SETPROBED_SSID_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_PMPARAMS (SIOCIWFIRSTPRIV+18)
+/*
+ * arguments:
+ * WMI_POWER_PARAMS_CMD powerParams (see include/wmi.h)
+ * uses: WMI_SET_POWER_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BADAP (SIOCIWFIRSTPRIV+19)
+/*
+ * arguments:
+ * WMI_ADD_BAD_AP_CMD badAPs (see include/wmi.h)
+ * uses: WMI_ADD_BAD_AP_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_QOS_QUEUE (SIOCIWFIRSTPRIV+20)
+/*
+ * arguments:
+ * ar6000_queuereq queueRequest (see below)
+ */
+
+#define AR6000_IOCTL_WMI_CREATE_QOS (SIOCIWFIRSTPRIV+21)
+/*
+ * arguments:
+ * WMI_CREATE_PSTREAM createPstreamCmd (see include/wmi.h)
+ * uses: WMI_CREATE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_DELETE_QOS (SIOCIWFIRSTPRIV+22)
+/*
+ * arguments:
+ * WMI_DELETE_PSTREAM_CMD deletePstreamCmd (see include/wmi.h)
+ * uses: WMI_DELETE_PSTREAM_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_SNRTHRESHOLD (SIOCIWFIRSTPRIV+23)
+/*
+ * arguments:
+ * WMI_SNR_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_SNR_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK (SIOCIWFIRSTPRIV+24)
+/*
+ * arguments:
+ * WMI_TARGET_ERROR_REPORT_BITMASK errorReportBitMask (see include/wmi.h)
+ * uses: WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_GET_TARGET_STATS (SIOCIWFIRSTPRIV+25)
+/*
+ * arguments:
+ * TARGET_STATS *targetStats (see below)
+ * uses: WMI_GET_STATISTICS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ASSOC_INFO (SIOCIWFIRSTPRIV+26)
+/*
+ * arguments:
+ * WMI_SET_ASSOC_INFO_CMD setAssocInfoCmd
+ * uses: WMI_SET_ASSOC_INFO_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_ACCESS_PARAMS (SIOCIWFIRSTPRIV+27)
+/*
+ * arguments:
+ * WMI_SET_ACCESS_PARAMS_CMD setAccessParams (see include/wmi.h)
+ * uses: WMI_SET_ACCESS_PARAMS_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_BMISS_TIME (SIOCIWFIRSTPRIV+28)
+/*
+ * arguments:
+ * UINT32 beaconMissTime
+ * uses: WMI_SET_BMISS_TIME_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_DISC_TIMEOUT (SIOCIWFIRSTPRIV+29)
+/*
+ * arguments:
+ * WMI_DISC_TIMEOUT_CMD disconnectTimeoutCmd (see include/wmi.h)
+ * uses: WMI_SET_DISC_TIMEOUT_CMDID
+ */
+
+#define AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS (SIOCIWFIRSTPRIV+30)
+/*
+ * arguments:
+ * WMI_IBSS_PM_CAPS_CMD ibssPowerMgmtCapsCmd
+ * uses: WMI_SET_IBSS_PM_CAPS_CMDID
+ */
+
+/*
+ * There is a very small space available for driver-private
+ * wireless ioctls. In order to circumvent this limitation,
+ * we multiplex a bunch of ioctls (XIOCTLs) on top of a
+ * single AR6000_IOCTL_EXTENDED ioctl.
+ */
+#define AR6000_IOCTL_EXTENDED (SIOCIWFIRSTPRIV+31)
+
+
+/* ====BMI Extended Ioctls==== */
+
+#define AR6000_XIOCTL_BMI_DONE 1
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_DONE)
+ * uses: BMI_DONE
+ */
+
+#define AR6000_XIOCTL_BMI_READ_MEMORY 2
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_READ_MEMORY)
+ * UINT32 address
+ * UINT32 length
+ * }
+ * char results[length]
+ * }
+ * uses: BMI_READ_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_MEMORY 3
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_MEMORY)
+ * UINT32 address
+ * UINT32 length
+ * char data[length]
+ * uses: BMI_WRITE_MEMORY
+ */
+
+#define AR6000_XIOCTL_BMI_EXECUTE 4
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_EXECUTE)
+ * UINT32 TargetAddress
+ * UINT32 parameter
+ * uses: BMI_EXECUTE
+ */
+
+#define AR6000_XIOCTL_BMI_SET_APP_START 5
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_SET_APP_START)
+ * UINT32 TargetAddress
+ * uses: BMI_SET_APP_START
+ */
+
+#define AR6000_XIOCTL_BMI_READ_SOC_REGISTER 6
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_READ_SOC_REGISTER)
+ * UINT32 TargetAddress, 32-bit aligned
+ * }
+ * UINT32 result
+ * }
+ * uses: BMI_READ_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER 7
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER)
+ * UINT32 TargetAddress, 32-bit aligned
+ * UINT32 newValue
+ * }
+ * uses: BMI_WRITE_SOC_REGISTER
+ */
+
+#define AR6000_XIOCTL_BMI_TEST 8
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_BMI_TEST)
+ * UINT32 address
+ * UINT32 length
+ * UINT32 count
+ */
+
+
+
+/* Historical Host-side DataSet support */
+#define AR6000_XIOCTL_UNUSED9 9
+#define AR6000_XIOCTL_UNUSED10 10
+#define AR6000_XIOCTL_UNUSED11 11
+
+/* ====Misc Extended Ioctls==== */
+
+#define AR6000_XIOCTL_FORCE_TARGET_RESET 12
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_FORCE_TARGET_RESET)
+ */
+
+
+#ifdef HTC_RAW_INTERFACE
+/* HTC Raw Interface Ioctls */
+#define AR6000_XIOCTL_HTC_RAW_OPEN 13
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_OPEN)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_CLOSE 14
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_CLOSE)
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_READ 15
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_READ)
+ * UINT32 mailboxID
+ * UINT32 length
+ * }
+ * results[length]
+ * }
+ */
+
+#define AR6000_XIOCTL_HTC_RAW_WRITE 16
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_HTC_RAW_WRITE)
+ * UINT32 mailboxID
+ * UINT32 length
+ * char buffer[length]
+ */
+#endif /* HTC_RAW_INTERFACE */
+
+#define AR6000_XIOCTL_CHECK_TARGET_READY 17
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_CHECK_TARGET_READY)
+ */
+
+
+
+/* ====GPIO (General Purpose I/O) Extended Ioctls==== */
+
+#define AR6000_XIOCTL_GPIO_OUTPUT_SET 18
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_OUTPUT_SET)
+ * ar6000_gpio_output_set_cmd_s (see below)
+ * uses: WMIX_GPIO_OUTPUT_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INPUT_GET 19
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_INPUT_GET)
+ * uses: WMIX_GPIO_INPUT_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_SET 20
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_SET)
+ * ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_SET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_REGISTER_GET 21
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_REGISTER_GET)
+ * ar6000_gpio_register_cmd_s (see below)
+ * uses: WMIX_GPIO_REGISTER_GET_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_ACK 22
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_ACK)
+ * ar6000_cpio_intr_ack_cmd_s (see below)
+ * uses: WMIX_GPIO_INTR_ACK_CMDID
+ */
+
+#define AR6000_XIOCTL_GPIO_INTR_WAIT 23
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_GPIO_INTR_WAIT)
+ */
+
+
+
+/* ====more wireless commands==== */
+
+#define AR6000_XIOCTL_SET_ADHOC_BSSID 24
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BSSID)
+ * WMI_SET_ADHOC_BSSID_CMD setAdHocBssidCmd (see include/wmi.h)
+ */
+
+#define AR6000_XIOCTL_SET_OPT_MODE 25
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_OPT_MODE)
+ * WMI_SET_OPT_MODE_CMD setOptModeCmd (see include/wmi.h)
+ * uses: WMI_SET_OPT_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_OPT_SEND_FRAME 26
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_OPT_SEND_FRAME)
+ * WMI_OPT_TX_FRAME_CMD optTxFrameCmd (see include/wmi.h)
+ * uses: WMI_OPT_TX_FRAME_CMDID
+ */
+
+#define AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL 27
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL)
+ * WMI_BEACON_INT_CMD beaconIntCmd (see include/wmi.h)
+ * uses: WMI_SET_BEACON_INT_CMDID
+ */
+
+
+#define IEEE80211_IOCTL_SETAUTHALG 28
+
+
+#define AR6000_XIOCTL_SET_VOICE_PKT_SIZE 29
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_VOICE_PKT_SIZE)
+ * WMI_SET_VOICE_PKT_SIZE_CMD setVoicePktSizeCmd (see include/wmi.h)
+ * uses: WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+
+
+#define AR6000_XIOCTL_SET_MAX_SP 30
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_SET_MAX_SP)
+ * WMI_SET_MAX_SP_LEN_CMD maxSPLen(see include/wmi.h)
+ * uses: WMI_SET_MAX_SP_LEN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_TBL 31
+
+#define AR6000_XIOCTL_WMI_SET_ROAM_CTRL 32
+
+#define AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS 33
+
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS)
+ * WMI_SET_POWERSAVE_TIMERS_CMD powerSaveTimers(see include/wmi.h)
+ * WMI_SET_POWERSAVE_TIMERS_CMDID
+ */
+
+#define AR6000_XIOCTRL_WMI_GET_POWER_MODE 34
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTRL_WMI_GET_POWER_MODE)
+ */
+
+#define AR6000_XIOCTRL_WMI_SET_WLAN_STATE 35
+typedef enum {
+ WLAN_DISABLED,
+ WLAN_ENABLED
+} AR6000_WLAN_STATE;
+/*
+ * arguments:
+ * enable/disable
+ */
+
+#define AR6000_XIOCTL_WMI_GET_ROAM_DATA 36
+
+#define AR6000_XIOCTL_WMI_SETRETRYLIMITS 37
+/*
+ * arguments:
+ * WMI_SET_RETRY_LIMITS_CMD ibssSetRetryLimitsCmd
+ * uses: WMI_SET_RETRY_LIMITS_CMDID
+ */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/* ====extended commands for radio test ==== */
+
+#define AR6000_XIOCTL_TCMD_CONT_TX 38
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_TX)
+ * WMI_TCMD_CONT_TX_CMD contTxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_TX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_CONT_RX 39
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TCMD_CONT_RX)
+ * WMI_TCMD_CONT_RX_CMD rxCmd (see include/wmi.h)
+ * uses: WMI_TCMD_CONT_RX_CMDID
+ */
+
+#define AR6000_XIOCTL_TCMD_PM 40
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TCMD_PM)
+ * WMI_TCMD_PM_CMD pmCmd (see include/wmi.h)
+ * uses: WMI_TCMD_PM_CMDID
+ */
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+#define AR6000_XIOCTL_WMI_STARTSCAN 41
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_STARTSCAN)
+ * UINT8 scanType
+ * UINT8 scanConnected
+ * A_BOOL forceFgScan
+ * uses: WMI_START_SCAN_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SETFIXRATES 42
+
+#define AR6000_XIOCTL_WMI_GETFIXRATES 43
+
+
+#define AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD 44
+/*
+ * arguments:
+ * WMI_RSSI_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_CLR_RSSISNR 45
+/*
+ * arguments:
+ * WMI_CLR_RSSISNR_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_CLR_RSSISNR_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LQTHRESHOLD 46
+/*
+ * arguments:
+ * WMI_LQ_THRESHOLD_PARAMS_CMD thresholdParams (see include/wmi.h)
+ * uses: WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_RTS 47
+/*
+ * arguments:
+ * WMI_SET_RTS_MODE_CMD (see include/wmi.h)
+ * uses: WMI_SET_RTS_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_LPREAMBLE 48
+
+#define AR6000_XIOCTL_WMI_SET_AUTHMODE 49
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_AUTHMODE)
+ * UINT8 mode
+ * uses: WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_SET_REASSOCMODE 50
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_WMM)
+ * UINT8 mode
+ * uses: WMI_SET_WMM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_WMM 51
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS)
+ * UINT32 frequency
+ * UINT8 threshold
+ */
+#define AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS 52
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP)
+ * UINT32 cookie
+ */
+#define AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP 53
+
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_WMI_GET_RD)
+ * UINT32 regDomain
+ */
+#define AR6000_XIOCTL_WMI_GET_RD 54
+
+#define AR6000_XIOCTL_DIAG_READ 55
+
+#define AR6000_XIOCTL_DIAG_WRITE 56
+
+/*
+ * arguments cmd (AR6000_XIOCTL_SET_TXOP)
+ * WMI_TXOP_CFG txopEnable
+ */
+#define AR6000_XIOCTL_WMI_SET_TXOP 57
+
+#ifdef USER_KEYS
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
+ * UINT32 keyOpCtrl
+ * uses AR6000_USER_SETKEYS_INFO
+ */
+#define AR6000_XIOCTL_USER_SETKEYS 58
+#endif /* USER_KEYS */
+
+#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59
+/*
+ * arguments:
+ * UINT8 cmd (AR6000_XIOCTL_WMI_SET_KEEPALIVE)
+ * UINT8 keepaliveInterval
+ * uses: WMI_SET_KEEPALIVE_CMDID
+ */
+
+#define AR6000_XIOCTL_WMI_GET_KEEPALIVE 60
+/*
+ * arguments:
+ * UINT8 cmd (AR6000_XIOCTL_WMI_GET_KEEPALIVE)
+ * UINT8 keepaliveInterval
+ * A_BOOL configured
+ * uses: WMI_GET_KEEPALIVE_CMDID
+ */
+
+/* ====ROM Patching Extended Ioctls==== */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_INSTALL 61
+/*
+ * arguments:
+ * union {
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_INSTALL)
+ * UINT32 ROM Address
+ * UINT32 RAM Address
+ * UINT32 number of bytes
+ * UINT32 activate? (0 or 1)
+ * }
+ * A_UINT32 resulting rompatch ID
+ * }
+ * uses: BMI_ROMPATCH_INSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL 62
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL)
+ * UINT32 rompatch ID
+ * }
+ * uses: BMI_ROMPATCH_UNINSTALL
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE 63
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE)
+ * UINT32 rompatch count
+ * UINT32 rompatch IDs[rompatch count]
+ * }
+ * uses: BMI_ROMPATCH_ACTIVATE
+ */
+
+#define AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE 64
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE)
+ * UINT32 rompatch count
+ * UINT32 rompatch IDs[rompatch count]
+ * }
+ * uses: BMI_ROMPATCH_DEACTIVATE
+ */
+
+#define AR6000_XIOCTL_WMI_SET_APPIE 65
+/*
+ * arguments:
+ * struct {
+ * UINT32 cmd (AR6000_XIOCTL_WMI_SET_APPIE)
+ * UINT32 app_frmtype;
+ * UINT32 app_buflen;
+ * UINT8 app_buf[];
+ * }
+ */
+#define AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER 66
+/*
+ * arguments:
+ * A_UINT32 filter_type;
+ */
+
+#define AR6000_XIOCTL_DBGLOG_CFG_MODULE 67
+
+#define AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS 68
+
+#define AR6000_XIOCTL_WMI_SET_WSC_STATUS 70
+/*
+ * arguments:
+ * A_UINT32 wsc_status;
+ * (WSC_REG_INACTIVE or WSC_REG_ACTIVE)
+ */
+
+/*
+ * arguments:
+ * struct {
+ * A_UINT8 streamType;
+ * A_UINT8 status;
+ * }
+ * uses: WMI_SET_BT_STATUS_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_STATUS 71
+
+/*
+ * arguments:
+ * struct {
+ * A_UINT8 paramType;
+ * union {
+ * A_UINT8 noSCOPkts;
+ * BT_PARAMS_A2DP a2dpParams;
+ * BT_COEX_REGS regs;
+ * };
+ * }
+ * uses: WMI_SET_BT_PARAM_CMDID
+ */
+#define AR6000_XIOCTL_WMI_SET_BT_PARAMS 72
+
+#define AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE 73
+#define AR6000_XIOCTL_WMI_SET_WOW_MODE 74
+#define AR6000_XIOCTL_WMI_GET_WOW_LIST 75
+#define AR6000_XIOCTL_WMI_ADD_WOW_PATTERN 76
+#define AR6000_XIOCTL_WMI_DEL_WOW_PATTERN 77
+
+
+
+#define AR6000_XIOCTL_TARGET_INFO 78
+/*
+ * arguments:
+ * UINT32 cmd (AR6000_XIOCTL_TARGET_INFO)
+ * A_UINT32 TargetVersion (returned)
+ * A_UINT32 TargetType (returned)
+ * (See also bmi_msg.h target_ver and target_type)
+ */
+
+#define AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE 79
+/*
+ * arguments:
+ * none
+ */
+
+#define AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE 80
+/*
+ * This ioctl is used to emulate traffic activity
+ * timeouts. Activity/inactivity will trigger the driver
+ * to re-balance credits.
+ *
+ * arguments:
+ * ar6000_traffic_activity_change
+ */
+
+#define AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS 81
+/*
+ * This ioctl is used to set the connect control flags
+ *
+ * arguments:
+ * A_UINT32 connectCtrlFlags
+ */
+
+#define AR6000_XIOCTL_WMI_SET_AKMP_PARAMS 82
+/*
+ * This IOCTL sets any Authentication,Key Management and Protection
+ * related parameters. This is used along with the information set in
+ * Connect Command.
+ * Currently this enables Multiple PMKIDs to an AP.
+ *
+ * arguments:
+ * struct {
+ * A_UINT32 akmpInfo;
+ * }
+ * uses: WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define AR6000_XIOCTL_WMI_GET_PMKID_LIST 83
+
+#define AR6000_XIOCTL_WMI_SET_PMKID_LIST 84
+/*
+ * This IOCTL is used to set a list of PMKIDs. This list of
+ * PMKIDs is used in the [Re]AssocReq Frame. This list is used
+ * only if the MultiPMKID option is enabled via the
+ * AR6000_XIOCTL_WMI_SET_AKMP_PARAMS IOCTL.
+ *
+ * arguments:
+ * struct {
+ * A_UINT32 numPMKID;
+ * WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
+ * }
+ * uses: WMI_SET_PMKIDLIST_CMD
+ */
+
+/* Historical DSETPATCH support for INI patches */
+#define AR6000_XIOCTL_UNUSED90 90
+
+
+
+/* used by AR6000_IOCTL_WMI_GETREV */
+struct ar6000_version {
+ A_UINT32 host_ver;
+ A_UINT32 target_ver;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_QOS_QUEUE */
+struct ar6000_queuereq {
+ A_UINT8 trafficClass;
+ A_UINT16 activeTsids;
+};
+
+/* used by AR6000_IOCTL_WMI_GET_TARGET_STATS */
+typedef struct targetStats_t {
+ A_UINT64 tx_packets;
+ A_UINT64 tx_bytes;
+ A_UINT64 tx_unicast_pkts;
+ A_UINT64 tx_unicast_bytes;
+ A_UINT64 tx_multicast_pkts;
+ A_UINT64 tx_multicast_bytes;
+ A_UINT64 tx_broadcast_pkts;
+ A_UINT64 tx_broadcast_bytes;
+ A_UINT64 tx_rts_success_cnt;
+ A_UINT64 tx_packet_per_ac[4];
+
+ A_UINT64 tx_errors;
+ A_UINT64 tx_failed_cnt;
+ A_UINT64 tx_retry_cnt;
+ A_UINT64 tx_rts_fail_cnt;
+ A_INT32 tx_unicast_rate;
+ A_UINT64 rx_packets;
+ A_UINT64 rx_bytes;
+ A_UINT64 rx_unicast_pkts;
+ A_UINT64 rx_unicast_bytes;
+ A_UINT64 rx_multicast_pkts;
+ A_UINT64 rx_multicast_bytes;
+ A_UINT64 rx_broadcast_pkts;
+ A_UINT64 rx_broadcast_bytes;
+ A_UINT64 rx_fragment_pkt;
+
+ A_UINT64 rx_errors;
+ A_UINT64 rx_crcerr;
+ A_UINT64 rx_key_cache_miss;
+ A_UINT64 rx_decrypt_err;
+ A_UINT64 rx_duplicate_frames;
+ A_INT32 rx_unicast_rate;
+
+ A_UINT64 tkip_local_mic_failure;
+ A_UINT64 tkip_counter_measures_invoked;
+ A_UINT64 tkip_replays;
+ A_UINT64 tkip_format_errors;
+ A_UINT64 ccmp_format_errors;
+ A_UINT64 ccmp_replays;
+
+ A_UINT64 power_save_failure_cnt;
+ A_INT16 noise_floor_calibation;
+
+ A_UINT64 cs_bmiss_cnt;
+ A_UINT64 cs_lowRssi_cnt;
+ A_UINT64 cs_connect_cnt;
+ A_UINT64 cs_disconnect_cnt;
+ A_UINT8 cs_aveBeacon_snr;
+ A_INT16 cs_aveBeacon_rssi;
+ A_UINT8 cs_lastRoam_msec;
+ A_UINT8 cs_snr;
+ A_INT16 cs_rssi;
+
+ A_UINT32 lq_val;
+
+ A_UINT32 wow_num_pkts_dropped;
+ A_UINT8 wow_num_host_pkt_wakeups;
+ A_UINT8 wow_num_host_event_wakeups;
+ A_UINT16 wow_num_events_discarded;
+
+}TARGET_STATS;
+
+typedef struct targetStats_cmd_t {
+ TARGET_STATS targetStats;
+ int clearStats;
+} TARGET_STATS_CMD;
+
+/* used by AR6000_XIOCTL_USER_SETKEYS */
+
+/*
+ * Setting this bit to 1 doesnot initialize the RSC on the firmware
+ */
+#define AR6000_XIOCTL_USER_SETKEYS_RSC_CTRL 1
+#define AR6000_USER_SETKEYS_RSC_UNCHANGED 0x00000002
+
+typedef struct {
+ A_UINT32 keyOpCtrl; /* Bit Map of Key Mgmt Ctrl Flags */
+} AR6000_USER_SETKEYS_INFO;
+
+
+/* used by AR6000_XIOCTL_GPIO_OUTPUT_SET */
+struct ar6000_gpio_output_set_cmd_s {
+ A_UINT32 set_mask;
+ A_UINT32 clear_mask;
+ A_UINT32 enable_mask;
+ A_UINT32 disable_mask;
+};
+
+/*
+ * used by AR6000_XIOCTL_GPIO_REGISTER_GET and AR6000_XIOCTL_GPIO_REGISTER_SET
+ */
+struct ar6000_gpio_register_cmd_s {
+ A_UINT32 gpioreg_id;
+ A_UINT32 value;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_ACK */
+struct ar6000_gpio_intr_ack_cmd_s {
+ A_UINT32 ack_mask;
+};
+
+/* used by AR6000_XIOCTL_GPIO_INTR_WAIT */
+struct ar6000_gpio_intr_wait_cmd_s {
+ A_UINT32 intr_mask;
+ A_UINT32 input_values;
+};
+
+/* used by the AR6000_XIOCTL_DBGLOG_CFG_MODULE */
+typedef struct ar6000_dbglog_module_config_s {
+ A_UINT32 valid;
+ A_UINT16 mmask;
+ A_UINT16 tsr;
+ A_BOOL rep;
+ A_UINT16 size;
+} DBGLOG_MODULE_CONFIG;
+
+typedef struct user_rssi_thold_t {
+ A_INT16 tag;
+ A_INT16 rssi;
+} USER_RSSI_THOLD;
+
+typedef struct user_rssi_params_t {
+ A_UINT8 weight;
+ A_UINT32 pollTime;
+ USER_RSSI_THOLD tholds[12];
+} USER_RSSI_PARAMS;
+
+/*
+ * Host driver may have some config parameters. Typically, these
+ * config params are one time config parameters. These could
+ * correspond to any of the underlying modules. Host driver exposes
+ * an api for the underlying modules to get this config.
+ */
+#define AR6000_DRIVER_CFG_BASE 0x8000
+
+/* Should driver perform wlan node caching? */
+#define AR6000_DRIVER_CFG_GET_WLANNODECACHING 0x8001
+/*Should we log raw WMI msgs */
+#define AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS 0x8002
+
+/* used by AR6000_XIOCTL_DIAG_READ & AR6000_XIOCTL_DIAG_WRITE */
+struct ar6000_diag_window_cmd_s {
+ unsigned int addr;
+ unsigned int value;
+};
+
+
+struct ar6000_traffic_activity_change {
+ A_UINT32 StreamID; /* stream ID to indicate activity change */
+ A_UINT32 Active; /* active (1) or inactive (0) */
+};
+
+#ifdef __cplusplus
+}
+#endif
+#endif
--- /dev/null
+++ b/drivers/ar6000/ar6000/athtypes_linux.h
@@ -0,0 +1,47 @@
+/*
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/athtypes_linux.h#1 $
+ *
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _ATHTYPES_LINUX_H_
+#define _ATHTYPES_LINUX_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#endif
+
+typedef int8_t A_INT8;
+typedef int16_t A_INT16;
+typedef int32_t A_INT32;
+typedef int64_t A_INT64;
+
+typedef u_int8_t A_UINT8;
+typedef u_int16_t A_UINT16;
+typedef u_int32_t A_UINT32;
+typedef u_int64_t A_UINT64;
+
+typedef int A_BOOL;
+typedef char A_CHAR;
+typedef unsigned char A_UCHAR;
+typedef unsigned long A_ATH_TIMER;
+
+
+#endif /* _ATHTYPES_LINUX_H_ */
--- /dev/null
+++ b/drivers/ar6000/ar6000/config_linux.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _CONFIG_LINUX_H_
+#define _CONFIG_LINUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Host-side GPIO support is optional.
+ * If run-time access to GPIO pins is not required, then
+ * this should be changed to #undef.
+ */
+#define CONFIG_HOST_GPIO_SUPPORT
+
+/*
+ * Host side Test Command support
+ */
+#define CONFIG_HOST_TCMD_SUPPORT
+
+#define USE_4BYTE_REGISTER_ACCESS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/ar6000/debug_linux.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _DEBUG_LINUX_H_
+#define _DEBUG_LINUX_H_
+
+#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING)
+
+extern A_UINT32 g_dbg_flags;
+
+#define DBGFMT "%s() : "
+#define DBGARG __func__
+#define DBGFN A_PRINTF
+
+/* ------- Debug related stuff ------- */
+enum {
+ ATH_DEBUG_SEND = 0x0001,
+ ATH_DEBUG_RECV = 0x0002,
+ ATH_DEBUG_SYNC = 0x0004,
+ ATH_DEBUG_DUMP = 0x0008,
+ ATH_DEBUG_IRQ = 0x0010,
+ ATH_DEBUG_TRC = 0x0020,
+ ATH_DEBUG_WARN = 0x0040,
+ ATH_DEBUG_ERR = 0x0080,
+ ATH_LOG_INF = 0x0100,
+ ATH_DEBUG_BMI = 0x0110,
+ ATH_DEBUG_WMI = 0x0120,
+ ATH_DEBUG_HIF = 0x0140,
+ ATH_DEBUG_HTC = 0x0180,
+ ATH_DEBUG_WLAN = 0x1000,
+ ATH_LOG_ERR = 0x1010,
+ ATH_DEBUG_ANY = 0xFFFF,
+};
+
+#ifdef DEBUG
+
+#define A_DPRINTF(f, a) \
+ if(g_dbg_flags & (f)) \
+ { \
+ DBGFN a ; \
+ }
+
+
+// TODO FIX usage of A_PRINTF!
+#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl))
+#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \
+ if (debughtc & ATH_DEBUG_DUMP) { \
+ DebugDumpBytes(buffer, length,desc); \
+ } \
+} while(0)
+#define PRINTX_ARG(arg...) arg
+#define AR_DEBUG_PRINTF(flags, args) do { \
+ if (debughtc & (flags)) { \
+ A_PRINTF(KERN_ALERT PRINTX_ARG args); \
+ } \
+} while (0)
+#define AR_DEBUG_ASSERT(test) do { \
+ if (!(test)) { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \
+ } \
+} while(0)
+extern int debughtc;
+#else
+#define AR_DEBUG_PRINTF(flags, args)
+#define AR_DEBUG_PRINTBUF(buffer, length, desc)
+#define AR_DEBUG_ASSERT(test)
+#define AR_DEBUG_LVL_CHECK(lvl) 0
+#define A_DPRINTF(f, a)
+#endif
+
+#endif /* _DEBUG_LINUX_H_ */
--- /dev/null
+++ b/drivers/ar6000/ar6000/ioctl.c
@@ -0,0 +1,2540 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "ar6000_drv.h"
+
+static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+static A_UINT8 null_mac[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+extern USER_RSSI_THOLD rssi_map[12];
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+extern int tspecCompliance;
+extern int bmienable;
+extern int bypasswmi;
+
+static int
+ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if(wmi_get_roam_tbl_cmd(ar->arWmi) != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ /* currently assume only roam times are required */
+ if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != A_OK) {
+ return -EIO;
+ }
+
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_ROAM_CTRL_CMD cmd;
+ A_UINT8 size = sizeof(cmd);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
+ if (cmd.info.bssBiasInfo.numBss > 1) {
+ size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
+ }
+ }
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
+ A_UINT8 size = sizeof(cmd);
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if (copy_from_user(&cmd, userdata, size)) {
+ return -EFAULT;
+ }
+
+ if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_WMM_CMD cmd;
+ A_STATUS ret;
+
+ if ((dev->flags & IFF_UP) != IFF_UP) {
+ return -EIO;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+
+ if (cmd.status == WMI_WMM_ENABLED) {
+ ar->arWmmEnabled = TRUE;
+ } else {
+ ar->arWmmEnabled = FALSE;
+ }
+
+ ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_WMM_TXOP_CMD cmd;
+ A_STATUS ret;
+
+ if ((dev->flags & IFF_UP) != IFF_UP) {
+ return -EIO;
+ }
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
+ sizeof(cmd)))
+ {
+ return -EFAULT;
+ }
+
+ ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ A_STATUS ret = 0;
+
+ if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
+ &ar->arRegCode, sizeof(ar->arRegCode)))
+ ret = -EFAULT;
+
+ return ret;
+}
+
+
+/* Get power mode command */
+static int
+ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_POWER_MODE_CMD power_mode;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
+ if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
+ ret = -EFAULT;
+ }
+
+ return ret;
+}
+
+
+static int
+ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (cmd.numChannels > 1) {
+ cmdp = A_MALLOC(130);
+ if (copy_from_user(cmdp, rq->ifr_data,
+ sizeof (*cmdp) +
+ ((cmd.numChannels - 1) * sizeof(A_UINT16))))
+ {
+ kfree(cmdp);
+ return -EFAULT;
+ }
+ } else {
+ cmdp = &cmd;
+ }
+
+ if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
+ ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
+ {
+ ret = -EINVAL;
+ }
+
+ if (!ret &&
+ (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
+ cmdp->numChannels, cmdp->channelList)
+ != A_OK))
+ {
+ ret = -EIO;
+ }
+
+ if (cmd.numChannels > 1) {
+ kfree(cmdp);
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
+{
+#define SWAP_THOLD(thold1, thold2) do { \
+ USER_RSSI_THOLD tmpThold; \
+ tmpThold.tag = thold1.tag; \
+ tmpThold.rssi = thold1.rssi; \
+ thold1.tag = thold2.tag; \
+ thold1.rssi = thold2.rssi; \
+ thold2.tag = tmpThold.tag; \
+ thold2.rssi = tmpThold.rssi; \
+} while (0)
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
+ USER_RSSI_PARAMS rssiParams;
+ A_INT32 i, j;
+
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
+ return -EFAULT;
+ }
+ cmd.weight = rssiParams.weight;
+ cmd.pollTime = rssiParams.pollTime;
+
+ A_MEMCPY(rssi_map, &rssiParams.tholds, sizeof(rssi_map));
+ /*
+ * only 6 elements, so use bubble sorting, in ascending order
+ */
+ for (i = 5; i > 0; i--) {
+ for (j = 0; j < i; j++) { /* above tholds */
+ if (rssi_map[j+1].rssi < rssi_map[j].rssi) {
+ SWAP_THOLD(rssi_map[j+1], rssi_map[j]);
+ } else if (rssi_map[j+1].rssi == rssi_map[j].rssi) {
+ return EFAULT;
+ }
+ }
+ }
+ for (i = 11; i > 6; i--) {
+ for (j = 6; j < i; j++) { /* below tholds */
+ if (rssi_map[j+1].rssi < rssi_map[j].rssi) {
+ SWAP_THOLD(rssi_map[j+1], rssi_map[j]);
+ } else if (rssi_map[j+1].rssi == rssi_map[j].rssi) {
+ return EFAULT;
+ }
+ }
+ }
+
+#ifdef DEBUG
+ for (i = 0; i < 12; i++) {
+ AR_DEBUG2_PRINTF("thold[%d].tag: %d, thold[%d].rssi: %d \n",
+ i, rssi_map[i].tag, i, rssi_map[i].rssi);
+ }
+#endif
+ cmd.thresholdAbove1_Val = rssi_map[0].rssi;
+ cmd.thresholdAbove2_Val = rssi_map[1].rssi;
+ cmd.thresholdAbove3_Val = rssi_map[2].rssi;
+ cmd.thresholdAbove4_Val = rssi_map[3].rssi;
+ cmd.thresholdAbove5_Val = rssi_map[4].rssi;
+ cmd.thresholdAbove6_Val = rssi_map[5].rssi;
+ cmd.thresholdBelow1_Val = rssi_map[6].rssi;
+ cmd.thresholdBelow2_Val = rssi_map[7].rssi;
+ cmd.thresholdBelow3_Val = rssi_map[8].rssi;
+ cmd.thresholdBelow4_Val = rssi_map[9].rssi;
+ cmd.thresholdBelow5_Val = rssi_map[10].rssi;
+ cmd.thresholdBelow6_Val = rssi_map[11].rssi;
+
+ if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
+{
+
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != A_OK ) {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+
+static int
+ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_PROBED_SSID_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
+ cmd.ssid) != A_OK)
+ {
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_ADD_BAD_AP_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
+ return -EIO;
+ }
+
+ if (A_MEMCMP(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
+ /*
+ * This is a delete badAP.
+ */
+ if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != A_OK) {
+ ret = -EIO;
+ }
+ } else {
+ if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != A_OK) {
+ ret = -EIO;
+ }
+ }
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_CREATE_PSTREAM_CMD cmd;
+ A_STATUS ret;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
+ if (ret == A_OK)
+ ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_DELETE_PSTREAM_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
+
+ switch (ret) {
+ case A_OK:
+ return 0;
+ case A_EBUSY :
+ return -EBUSY;
+ case A_NO_MEMORY:
+ return -ENOMEM;
+ case A_EINVAL:
+ default:
+ return -EFAULT;
+ }
+}
+
+static int
+ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ar6000_queuereq qreq;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if( copy_from_user(&qreq, rq->ifr_data,
+ sizeof(struct ar6000_queuereq)))
+ return -EFAULT;
+
+ qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
+
+ if (copy_to_user(rq->ifr_data, &qreq,
+ sizeof(struct ar6000_queuereq)))
+ {
+ ret = -EFAULT;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
+ struct ifreq *rq, A_UINT8 *data, A_UINT32 len)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ A_UINT32 buf[2];
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ ar->tcmdRxReport = 0;
+ if (wmi_test_cmd(ar->arWmi, data, len) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ buf[0] = ar->tcmdRxTotalPkt;
+ buf[1] = ar->tcmdRxRssi;
+ if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
+ ret = -EFAULT;
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+void
+ar6000_tcmd_rx_report_event(void *devt, A_UINT8 * results, int len)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)devt;
+ TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
+
+ ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
+ ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
+ ar->tcmdRxReport = 1;
+
+ wake_up(&arEvent);
+}
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+static int
+ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_TARGET_ERROR_REPORT_BITMASK cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
+
+ return (ret==0 ? ret : -EINVAL);
+}
+
+static int
+ar6000_clear_target_stats(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ A_MEMZERO(pStats, sizeof(TARGET_STATS));
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ return ret;
+}
+
+static int
+ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ TARGET_STATS_CMD cmd;
+ TARGET_STATS *pStats = &ar->arTargetStats;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ ar->statsUpdatePending = TRUE;
+
+ if(wmi_get_stats_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == FALSE, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
+ ret = -EFAULT;
+ }
+
+ if (cmd.clearStats == 1) {
+ ret = ar6000_clear_target_stats(dev);
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+static int
+ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_ACCESS_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_access_params_cmd(ar->arWmi, cmd.txop, cmd.eCWmin, cmd.eCWmax,
+ cmd.aifsn) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_DISC_TIMEOUT_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_VOICE_PKT_SIZE_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_max_sp_len(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_MAX_SP_LEN_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+
+static int
+ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_BT_STATUS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+static int
+ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char * userdata)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_SET_BT_PARAMS_CMD cmd;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
+ return -EFAULT;
+ }
+
+ if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == A_OK)
+ {
+ ret = 0;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return (ret);
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results;
+/* gpio_reg_results and gpio_data_available are protected by arSem */
+static struct ar6000_gpio_register_cmd_s gpio_reg_results;
+static A_BOOL gpio_data_available; /* Requested GPIO data available */
+static A_BOOL gpio_intr_available; /* GPIO interrupt info available */
+static A_BOOL gpio_ack_received; /* GPIO ack was received */
+
+/* Host-side initialization for General Purpose I/O support */
+void ar6000_gpio_init(void)
+{
+ gpio_intr_available = FALSE;
+ gpio_data_available = FALSE;
+ gpio_ack_received = FALSE;
+}
+
+/*
+ * Called when a GPIO interrupt is received from the Target.
+ * intr_values shows which GPIO pins have interrupted.
+ * input_values shows a recent value of GPIO pins.
+ */
+void
+ar6000_gpio_intr_rx(A_UINT32 intr_mask, A_UINT32 input_values)
+{
+ gpio_intr_results.intr_mask = intr_mask;
+ gpio_intr_results.input_values = input_values;
+ *((volatile A_BOOL *)&gpio_intr_available) = TRUE;
+ wake_up(&arEvent);
+}
+
+/*
+ * This is called when a response is received from the Target
+ * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
+ * call.
+ */
+void
+ar6000_gpio_data_rx(A_UINT32 reg_id, A_UINT32 value)
+{
+ gpio_reg_results.gpioreg_id = reg_id;
+ gpio_reg_results.value = value;
+ *((volatile A_BOOL *)&gpio_data_available) = TRUE;
+ wake_up(&arEvent);
+}
+
+/*
+ * This is called when an acknowledgement is received from the Target
+ * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
+ * call.
+ */
+void
+ar6000_gpio_ack_rx(void)
+{
+ gpio_ack_received = TRUE;
+ wake_up(&arEvent);
+}
+
+A_STATUS
+ar6000_gpio_output_set(struct net_device *dev,
+ A_UINT32 set_mask,
+ A_UINT32 clear_mask,
+ A_UINT32 enable_mask,
+ A_UINT32 disable_mask)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ gpio_ack_received = FALSE;
+ return wmi_gpio_output_set(ar->arWmi,
+ set_mask, clear_mask, enable_mask, disable_mask);
+}
+
+static A_STATUS
+ar6000_gpio_input_get(struct net_device *dev)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+ return wmi_gpio_input_get(ar->arWmi);
+}
+
+static A_STATUS
+ar6000_gpio_register_set(struct net_device *dev,
+ A_UINT32 gpioreg_id,
+ A_UINT32 value)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ gpio_ack_received = FALSE;
+ return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
+}
+
+static A_STATUS
+ar6000_gpio_register_get(struct net_device *dev,
+ A_UINT32 gpioreg_id)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ *((volatile A_BOOL *)&gpio_data_available) = FALSE;
+ return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
+}
+
+static A_STATUS
+ar6000_gpio_intr_ack(struct net_device *dev,
+ A_UINT32 ack_mask)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ gpio_intr_available = FALSE;
+ return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ HIF_DEVICE *hifDevice = ar->arHifDevice;
+ int ret, param, param2;
+ unsigned int address = 0;
+ unsigned int length = 0;
+ unsigned char *buffer;
+ char *userdata;
+ A_UINT32 connectCtrlFlags;
+
+
+ static WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
+ WMI_SHORTSCANRATIO_DEFAULT,
+ DEFAULT_SCAN_CTRL_FLAGS,
+ 0};
+ WMI_SET_AKMP_PARAMS_CMD akmpParams;
+ WMI_SET_PMKID_LIST_CMD pmkidInfo;
+
+ if (cmd == AR6000_IOCTL_EXTENDED)
+ {
+ /*
+ * This allows for many more wireless ioctls than would otherwise
+ * be available. Applications embed the actual ioctl command in
+ * the first word of the parameter block, and use the command
+ * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
+ */
+ get_user(cmd, (int *)rq->ifr_data);
+ userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
+ }
+ else
+ {
+ userdata = (char *)rq->ifr_data;
+ }
+
+ if ((ar->arWlanState == WLAN_DISABLED) &&
+ ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
+ (cmd != AR6000_XIOCTL_DIAG_READ) &&
+ (cmd != AR6000_XIOCTL_DIAG_WRITE)))
+ {
+ return -EIO;
+ }
+
+ ret = 0;
+ switch(cmd)
+ {
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ case AR6000_XIOCTL_TCMD_CONT_TX:
+ {
+ TCMD_CONT_TX txCmd;
+
+ if (ar->tcmdPm == TCMD_PM_SLEEP) {
+ A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
+ return -EFAULT;
+ }
+
+ if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX)))
+ return -EFAULT;
+ wmi_test_cmd(ar->arWmi,(A_UINT8 *)&txCmd, sizeof(TCMD_CONT_TX));
+ }
+ break;
+ case AR6000_XIOCTL_TCMD_CONT_RX:
+ {
+ TCMD_CONT_RX rxCmd;
+
+ if (ar->tcmdPm == TCMD_PM_SLEEP) {
+ A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
+ return -EFAULT;
+ }
+ if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX)))
+ return -EFAULT;
+ switch(rxCmd.act)
+ {
+ case TCMD_CONT_RX_PROMIS:
+ case TCMD_CONT_RX_FILTER:
+ case TCMD_CONT_RX_SETMAC:
+ wmi_test_cmd(ar->arWmi,(A_UINT8 *)&rxCmd,
+ sizeof(TCMD_CONT_RX));
+ break;
+ case TCMD_CONT_RX_REPORT:
+ ar6000_ioctl_tcmd_get_rx_report(dev, rq,
+ (A_UINT8 *)&rxCmd, sizeof(TCMD_CONT_RX));
+ break;
+ default:
+ A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
+ return -EINVAL;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_TCMD_PM:
+ {
+ TCMD_PM pmCmd;
+
+ if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM)))
+ return -EFAULT;
+ ar->tcmdPm = pmCmd.mode;
+ wmi_test_cmd(ar->arWmi, (A_UINT8*)&pmCmd, sizeof(TCMD_PM));
+ }
+ break;
+#endif /* CONFIG_HOST_TCMD_SUPPORT */
+
+ case AR6000_XIOCTL_BMI_DONE:
+ if(bmienable)
+ {
+ ret = ar6000_init(dev);
+ }
+ else
+ {
+ ret = BMIDone(hifDevice);
+ }
+ break;
+
+ case AR6000_XIOCTL_BMI_READ_MEMORY:
+ get_user(address, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ AR_DEBUG_PRINTF("Read Memory (address: 0x%x, length: %d)\n",
+ address, length);
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ ret = BMIReadMemory(hifDevice, address, buffer, length);
+ if (copy_to_user(rq->ifr_data, buffer, length)) {
+ ret = -EFAULT;
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+ break;
+
+ case AR6000_XIOCTL_BMI_WRITE_MEMORY:
+ get_user(address, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ AR_DEBUG_PRINTF("Write Memory (address: 0x%x, length: %d)\n",
+ address, length);
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ if (copy_from_user(buffer, &userdata[sizeof(address) +
+ sizeof(length)], length))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = BMIWriteMemory(hifDevice, address, buffer, length);
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+ break;
+
+ case AR6000_XIOCTL_BMI_TEST:
+ AR_DEBUG_PRINTF("No longer supported\n");
+ ret = -EOPNOTSUPP;
+ break;
+
+ case AR6000_XIOCTL_BMI_EXECUTE:
+ get_user(address, (unsigned int *)userdata);
+ get_user(param, (unsigned int *)userdata + 1);
+ AR_DEBUG_PRINTF("Execute (address: 0x%x, param: %d)\n",
+ address, param);
+ ret = BMIExecute(hifDevice, address, &param);
+ put_user(param, (unsigned int *)rq->ifr_data); /* return value */
+ break;
+
+ case AR6000_XIOCTL_BMI_SET_APP_START:
+ get_user(address, (unsigned int *)userdata);
+ AR_DEBUG_PRINTF("Set App Start (address: 0x%x)\n", address);
+ ret = BMISetAppStart(hifDevice, address);
+ break;
+
+ case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
+ get_user(address, (unsigned int *)userdata);
+ ret = BMIReadSOCRegister(hifDevice, address, &param);
+ put_user(param, (unsigned int *)rq->ifr_data); /* return value */
+ break;
+
+ case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
+ get_user(address, (unsigned int *)userdata);
+ get_user(param, (unsigned int *)userdata + 1);
+ ret = BMIWriteSOCRegister(hifDevice, address, param);
+ break;
+
+#ifdef HTC_RAW_INTERFACE
+ case AR6000_XIOCTL_HTC_RAW_OPEN:
+ ret = A_OK;
+ if (!arRawIfEnabled(ar)) {
+ /* make sure block size is set in case the target was reset since last
+ * BMI phase (i.e. flashup downloads) */
+ ret = ar6000_SetHTCBlockSize(ar);
+ if (A_FAILED(ret)) {
+ break;
+ }
+ /* Terminate the BMI phase */
+ ret = BMIDone(hifDevice);
+ if (ret == A_OK) {
+ ret = ar6000_htc_raw_open(ar);
+ }
+ }
+ break;
+
+ case AR6000_XIOCTL_HTC_RAW_CLOSE:
+ if (arRawIfEnabled(ar)) {
+ ret = ar6000_htc_raw_close(ar);
+ arRawIfEnabled(ar) = FALSE;
+ } else {
+ ret = A_ERROR;
+ }
+ break;
+
+ case AR6000_XIOCTL_HTC_RAW_READ:
+ if (arRawIfEnabled(ar)) {
+ unsigned int streamID;
+ get_user(streamID, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ buffer = rq->ifr_data + sizeof(length);
+ ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
+ buffer, length);
+ put_user(ret, (unsigned int *)rq->ifr_data);
+ } else {
+ ret = A_ERROR;
+ }
+ break;
+
+ case AR6000_XIOCTL_HTC_RAW_WRITE:
+ if (arRawIfEnabled(ar)) {
+ unsigned int streamID;
+ get_user(streamID, (unsigned int *)userdata);
+ get_user(length, (unsigned int *)userdata + 1);
+ buffer = userdata + sizeof(streamID) + sizeof(length);
+ ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
+ buffer, length);
+ put_user(ret, (unsigned int *)rq->ifr_data);
+ } else {
+ ret = A_ERROR;
+ }
+ break;
+#endif /* HTC_RAW_INTERFACE */
+
+ case AR6000_IOCTL_WMI_GETREV:
+ {
+ if (copy_to_user(rq->ifr_data, &ar->arVersion,
+ sizeof(ar->arVersion)))
+ {
+ ret = -EFAULT;
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETPWR:
+ {
+ WMI_POWER_MODE_CMD pwrModeCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&pwrModeCmd, userdata,
+ sizeof(pwrModeCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
+ {
+ WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&ibssPmCaps, userdata,
+ sizeof(ibssPmCaps)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
+ ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != A_OK)
+ {
+ ret = -EIO;
+ }
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arIbssPsEnable = ibssPmCaps.power_saving;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_PMPARAMS:
+ {
+ WMI_POWER_PARAMS_CMD pmParams;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&pmParams, userdata,
+ sizeof(pmParams)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
+ pmParams.pspoll_number,
+ pmParams.dtim_policy) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETSCAN:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&scParams, userdata,
+ sizeof(scParams)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (CAN_SCAN_IN_CONNECT(scParams.scanCtrlFlags)) {
+ ar->arSkipScan = FALSE;
+ } else {
+ ar->arSkipScan = TRUE;
+ }
+
+ if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
+ scParams.fg_end_period,
+ scParams.bg_period,
+ scParams.minact_chdwell_time,
+ scParams.maxact_chdwell_time,
+ scParams.pas_chdwell_time,
+ scParams.shortScanRatio,
+ scParams.scanCtrlFlags,
+ scParams.max_dfsch_act_time) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETLISTENINT:
+ {
+ WMI_LISTEN_INT_CMD listenCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&listenCmd, userdata,
+ sizeof(listenCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != A_OK) {
+ ret = -EIO;
+ } else {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arListenInterval = param;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_BMISS_TIME:
+ {
+ WMI_BMISS_TIME_CMD bmissCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&bmissCmd, userdata,
+ sizeof(bmissCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SETBSSFILTER:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+
+ get_user(param, (unsigned char *)userdata);
+ get_user(param2, (unsigned int *)(userdata + 1));
+ printk("SETBSSFILTER: filter 0x%x, mask: 0x%x\n", param, param2);
+ if (wmi_bssfilter_cmd(ar->arWmi, param, param2) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
+ {
+ ret = ar6000_ioctl_set_snr_threshold(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
+ {
+ ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_CLR_RSSISNR:
+ {
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ }
+ ret = wmi_clr_rssi_snr(ar->arWmi);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
+ {
+ ret = ar6000_ioctl_set_lq_threshold(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
+ {
+ WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setLpreambleCmd, userdata,
+ sizeof(setLpreambleCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_RTS:
+ {
+ WMI_SET_RTS_CMD rtsCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&rtsCmd, userdata,
+ sizeof(rtsCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_WMM:
+ {
+ ret = ar6000_ioctl_set_wmm(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_TXOP:
+ {
+ ret = ar6000_ioctl_set_txop(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_RD:
+ {
+ ret = ar6000_ioctl_get_rd(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
+ {
+ ret = ar6000_ioctl_set_channelParams(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_PROBEDSSID:
+ {
+ ret = ar6000_ioctl_set_probedSsid(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_BADAP:
+ {
+ ret = ar6000_ioctl_set_badAp(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_CREATE_QOS:
+ {
+ ret = ar6000_ioctl_create_qos(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_DELETE_QOS:
+ {
+ ret = ar6000_ioctl_delete_qos(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
+ {
+ ret = ar6000_ioctl_get_qos_queue(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_GET_TARGET_STATS:
+ {
+ ret = ar6000_ioctl_get_target_stats(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
+ {
+ ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
+ {
+ WMI_SET_ASSOC_INFO_CMD cmd;
+ A_UINT8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ get_user(cmd.ieType, userdata);
+ if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
+ ret = -EIO;
+ } else {
+ get_user(cmd.bufferSize, userdata + 1);
+ if (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) {
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(assocInfo, userdata + 2,
+ cmd.bufferSize))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
+ cmd.bufferSize,
+ assocInfo) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ }
+ }
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
+ {
+ ret = ar6000_ioctl_set_access_params(dev, rq);
+ break;
+ }
+ case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
+ {
+ ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
+ break;
+ }
+ case AR6000_XIOCTL_FORCE_TARGET_RESET:
+ {
+ if (ar->arHtcTarget)
+ {
+// HTCForceReset(htcTarget);
+ }
+ else
+ {
+ AR_DEBUG_PRINTF("ar6000_ioctl cannot attempt reset.\n");
+ }
+ break;
+ }
+ case AR6000_XIOCTL_TARGET_INFO:
+ case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
+ {
+ /* If we made it to here, then the Target exists and is ready. */
+
+ if (cmd == AR6000_XIOCTL_TARGET_INFO) {
+ if (copy_to_user((A_UINT32 *)rq->ifr_data, &ar->arVersion.target_ver,
+ sizeof(ar->arVersion.target_ver)))
+ {
+ ret = -EFAULT;
+ }
+ if (copy_to_user(((A_UINT32 *)rq->ifr_data)+1, &ar->arTargetType,
+ sizeof(ar->arTargetType)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
+ {
+ WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
+
+ if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
+ {
+ ret = -EFAULT;
+ } else {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ /* Start a cyclic timer with the parameters provided. */
+ if (hbparam.frequency) {
+ ar->arHBChallengeResp.frequency = hbparam.frequency;
+ }
+ if (hbparam.threshold) {
+ ar->arHBChallengeResp.missThres = hbparam.threshold;
+ }
+
+ /* Delete the pending timer and start a new one */
+ if (timer_pending(&ar->arHBChallengeResp.timer)) {
+ A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
+ }
+ A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
+ {
+ A_UINT32 cookie;
+
+ if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
+ return -EFAULT;
+ }
+
+ /* Send the challenge on the control channel */
+ if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != A_OK) {
+ return -EIO;
+ }
+ break;
+ }
+#ifdef USER_KEYS
+ case AR6000_XIOCTL_USER_SETKEYS:
+ {
+
+ ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
+
+ if (copy_from_user(&ar->user_key_ctrl, userdata,
+ sizeof(ar->user_key_ctrl)))
+ {
+ return -EFAULT;
+ }
+
+ A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
+ break;
+ }
+#endif /* USER_KEYS */
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+ case AR6000_XIOCTL_GPIO_OUTPUT_SET:
+ {
+ struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (copy_from_user(&gpio_output_set_cmd, userdata,
+ sizeof(gpio_output_set_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_output_set(dev,
+ gpio_output_set_cmd.set_mask,
+ gpio_output_set_cmd.clear_mask,
+ gpio_output_set_cmd.enable_mask,
+ gpio_output_set_cmd.disable_mask);
+ if (ret != A_OK) {
+ ret = EIO;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_INPUT_GET:
+ {
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ ret = ar6000_gpio_input_get(dev);
+ if (ret != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ /* Wait for Target to respond. */
+ wait_event_interruptible(arEvent, gpio_data_available);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
+
+ if (copy_to_user(userdata, &gpio_reg_results.value,
+ sizeof(gpio_reg_results.value)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_REGISTER_SET:
+ {
+ struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (copy_from_user(&gpio_register_cmd, userdata,
+ sizeof(gpio_register_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_register_set(dev,
+ gpio_register_cmd.gpioreg_id,
+ gpio_register_cmd.value);
+ if (ret != A_OK) {
+ ret = EIO;
+ }
+
+ /* Wait for acknowledgement from Target */
+ wait_event_interruptible(arEvent, gpio_ack_received);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_REGISTER_GET:
+ {
+ struct ar6000_gpio_register_cmd_s gpio_register_cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (copy_from_user(&gpio_register_cmd, userdata,
+ sizeof(gpio_register_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
+ if (ret != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ /* Wait for Target to respond. */
+ wait_event_interruptible(arEvent, gpio_data_available);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
+ if (copy_to_user(userdata, &gpio_reg_results,
+ sizeof(gpio_reg_results)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_INTR_ACK:
+ {
+ struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (copy_from_user(&gpio_intr_ack_cmd, userdata,
+ sizeof(gpio_intr_ack_cmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
+ if (ret != A_OK) {
+ ret = EIO;
+ }
+ }
+ up(&ar->arSem);
+ break;
+ }
+ case AR6000_XIOCTL_GPIO_INTR_WAIT:
+ {
+ /* Wait for Target to report an interrupt. */
+ dev_hold(dev);
+ rtnl_unlock();
+ wait_event_interruptible(arEvent, gpio_intr_available);
+ rtnl_lock();
+ __dev_put(dev);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ } else {
+ if (copy_to_user(userdata, &gpio_intr_results,
+ sizeof(gpio_intr_results)))
+ {
+ ret = -EFAULT;
+ }
+ }
+ break;
+ }
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+ case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
+ {
+ struct ar6000_dbglog_module_config_s config;
+
+ if (copy_from_user(&config, userdata, sizeof(config))) {
+ return -EFAULT;
+ }
+
+ /* Send the challenge on the control channel */
+ if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
+ config.tsr, config.rep,
+ config.size, config.valid) != A_OK)
+ {
+ return -EIO;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
+ {
+ /* Send the challenge on the control channel */
+ if (ar6000_dbglog_get_debug_logs(ar) != A_OK)
+ {
+ return -EIO;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_ADHOC_BSSID:
+ {
+ WMI_SET_ADHOC_BSSID_CMD adhocBssid;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&adhocBssid, userdata,
+ sizeof(adhocBssid)))
+ {
+ ret = -EFAULT;
+ } else if (A_MEMCMP(adhocBssid.bssid, bcast_mac,
+ AR6000_ETH_ADDR_LEN) == 0)
+ {
+ ret = -EFAULT;
+ } else {
+
+ A_MEMCPY(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_OPT_MODE:
+ {
+ WMI_SET_OPT_MODE_CMD optModeCmd;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&optModeCmd, userdata,
+ sizeof(optModeCmd)))
+ {
+ ret = -EFAULT;
+ } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
+ ret = -EFAULT;
+
+ } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_OPT_SEND_FRAME:
+ {
+ WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
+ A_UINT8 data[MAX_OPT_DATA_LEN];
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&optTxFrmCmd, userdata,
+ sizeof(optTxFrmCmd)))
+ {
+ ret = -EFAULT;
+ } else if (copy_from_user(data,
+ userdata+sizeof(WMI_OPT_TX_FRAME_CMD)-1,
+ optTxFrmCmd.optIEDataLen))
+ {
+ ret = -EFAULT;
+ } else {
+ ret = wmi_opt_tx_frame_cmd(ar->arWmi,
+ optTxFrmCmd.frmType,
+ optTxFrmCmd.dstAddr,
+ optTxFrmCmd.bssid,
+ optTxFrmCmd.optIEDataLen,
+ data);
+ }
+
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
+ {
+ WMI_SET_RETRY_LIMITS_CMD setRetryParams;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setRetryParams, userdata,
+ sizeof(setRetryParams)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
+ setRetryParams.trafficClass,
+ setRetryParams.maxRetries,
+ setRetryParams.enableNotify) != A_OK)
+ {
+ ret = -EIO;
+ }
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arMaxRetries = setRetryParams.maxRetries;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_ADHOC_BEACON_INTVAL:
+ {
+ WMI_BEACON_INT_CMD bIntvlCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&bIntvlCmd, userdata,
+ sizeof(bIntvlCmd)))
+ {
+ ret = -EFAULT;
+ } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
+ != A_OK)
+ {
+ ret = -EIO;
+ }
+ break;
+ }
+ case IEEE80211_IOCTL_SETAUTHALG:
+ {
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ieee80211req_authalg req;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&req, userdata,
+ sizeof(struct ieee80211req_authalg)))
+ {
+ ret = -EFAULT;
+ } else if (req.auth_alg == AUTH_ALG_OPEN_SYSTEM) {
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arGroupCrypto = NONE_CRYPT;
+ } else if (req.auth_alg == AUTH_ALG_LEAP) {
+ ar->arDot11AuthMode = LEAP_AUTH;
+ } else {
+ ret = -EIO;
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
+ ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_SET_MAX_SP:
+ ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
+ break;
+
+ case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
+ ret = ar6000_ioctl_get_roam_tbl(dev, rq);
+ break;
+ case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
+ ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
+ break;
+ case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
+ ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
+ break;
+ case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
+ ret = ar6000_ioctl_get_power_mode(dev, rq);
+ break;
+ case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
+ get_user(ar->arWlanState, (unsigned int *)userdata);
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ break;
+ }
+
+ if (ar->arWlanState == WLAN_ENABLED) {
+ /* Enable foreground scanning */
+ if (wmi_scanparams_cmd(ar->arWmi, scParams.fg_start_period,
+ scParams.fg_end_period,
+ scParams.bg_period,
+ scParams.minact_chdwell_time,
+ scParams.maxact_chdwell_time,
+ scParams.pas_chdwell_time,
+ scParams.shortScanRatio,
+ scParams.scanCtrlFlags,
+ scParams.max_dfsch_act_time) != A_OK)
+ {
+ ret = -EIO;
+ }
+ if (ar->arSsidLen) {
+ ar->arConnectPending = TRUE;
+ if (wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+ ar->arDot11AuthMode, ar->arAuthMode,
+ ar->arPairwiseCrypto,
+ ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto, ar->arGroupCryptoLen,
+ ar->arSsidLen, ar->arSsid,
+ ar->arReqBssid, ar->arChannelHint,
+ ar->arConnectCtrlFlags) != A_OK)
+ {
+ ret = -EIO;
+ ar->arConnectPending = FALSE;
+ }
+ }
+ } else {
+ /* Disconnect from the AP and disable foreground scanning */
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ if (ar->arConnected == TRUE || ar->arConnectPending == TRUE) {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ wmi_disconnect_cmd(ar->arWmi);
+ } else {
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ }
+
+ if (wmi_scanparams_cmd(ar->arWmi, 0xFFFF, 0, 0, 0, 0, 0, 0, 0xFF, 0) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
+ ret = ar6000_ioctl_get_roam_data(dev, rq);
+ break;
+ case AR6000_XIOCTL_WMI_SET_BT_STATUS:
+ ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
+ break;
+ case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
+ ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
+ break;
+ case AR6000_XIOCTL_WMI_STARTSCAN:
+ {
+ WMI_START_SCAN_CMD setStartScanCmd;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setStartScanCmd, userdata,
+ sizeof(setStartScanCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_startscan_cmd(ar->arWmi, setStartScanCmd.scanType,
+ setStartScanCmd.forceFgScan,
+ setStartScanCmd.isLegacy,
+ setStartScanCmd.homeDwellTime,
+ setStartScanCmd.forceScanInterval) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SETFIXRATES:
+ {
+ WMI_FIX_RATES_CMD setFixRatesCmd;
+ A_STATUS returnStatus;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setFixRatesCmd, userdata,
+ sizeof(setFixRatesCmd)))
+ {
+ ret = -EFAULT;
+ } else {
+ returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
+ if (returnStatus == A_EINVAL)
+ {
+ ret = -EINVAL;
+ }
+ else if(returnStatus != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_WMI_GETFIXRATES:
+ {
+ WMI_FIX_RATES_CMD getFixRatesCmd;
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ /* Used copy_from_user/copy_to_user to access user space data */
+ if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
+ ret = -EFAULT;
+ } else {
+ ar->arRateMask = 0xFFFF;
+
+ if (wmi_get_ratemask_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFF, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret) {
+ getFixRatesCmd.fixRateMask = ar->arRateMask;
+ }
+
+ if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
+ ret = -EFAULT;
+ }
+
+ up(&ar->arSem);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_AUTHMODE:
+ {
+ WMI_SET_AUTH_MODE_CMD setAuthMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setAuthMode, userdata,
+ sizeof(setAuthMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
+ {
+ WMI_SET_REASSOC_MODE_CMD setReassocMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setReassocMode, userdata,
+ sizeof(setReassocMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_DIAG_READ:
+ {
+ A_UINT32 addr, data;
+ get_user(addr, (unsigned int *)userdata);
+ if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+ ret = -EIO;
+ }
+ put_user(data, (unsigned int *)userdata + 1);
+ break;
+ }
+ case AR6000_XIOCTL_DIAG_WRITE:
+ {
+ A_UINT32 addr, data;
+ get_user(addr, (unsigned int *)userdata);
+ get_user(data, (unsigned int *)userdata + 1);
+ if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != A_OK) {
+ ret = -EIO;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
+ {
+ WMI_SET_KEEPALIVE_CMD setKeepAlive;
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ } else if (copy_from_user(&setKeepAlive, userdata,
+ sizeof(setKeepAlive))){
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
+ {
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ WMI_GET_KEEPALIVE_CMD getKeepAlive;
+ int ret = 0;
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
+ ret = -EFAULT;
+ } else {
+ getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
+ ar->arKeepaliveConfigured = 0xFF;
+ if (wmi_get_keepalive_configured(ar->arWmi) != A_OK){
+ up(&ar->arSem);
+ return -EIO;
+ }
+ wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+
+ if (!ret) {
+ getKeepAlive.configured = ar->arKeepaliveConfigured;
+ }
+ if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
+ ret = -EFAULT;
+ }
+ up(&ar->arSem);
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_APPIE:
+ {
+ WMI_SET_APPIE_CMD appIEcmd;
+ A_UINT8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
+ A_UINT32 fType,ieLen;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ get_user(fType, (A_UINT32 *)userdata);
+ appIEcmd.mgmtFrmType = fType;
+ if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
+ ret = -EIO;
+ } else {
+ get_user(ieLen, (A_UINT32 *)(userdata + 4));
+ appIEcmd.ieLen = ieLen;
+ if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
+ ret = -EIO;
+ break;
+ }
+ if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
+ appIEcmd.ieLen, appIeInfo) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
+ {
+ WMI_BSS_FILTER_CMD cmd;
+ A_UINT32 filterType;
+
+ if (copy_from_user(&filterType, userdata, sizeof(A_UINT32)))
+ {
+ return -EFAULT;
+ }
+ if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
+ IEEE80211_FILTER_TYPE_PROBE_RESP))
+ {
+ cmd.bssFilter = ALL_BSS_FILTER;
+ } else {
+ cmd.bssFilter = NONE_BSS_FILTER;
+ }
+ if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != A_OK) {
+ ret = -EIO;
+ }
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ ar->arMgmtFilter = filterType;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
+ {
+ A_UINT32 wsc_status;
+
+ if (copy_from_user(&wsc_status, userdata, sizeof(A_UINT32)))
+ {
+ return -EFAULT;
+ }
+ if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != A_OK) {
+ ret = -EIO;
+ }
+ break;
+ }
+ case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
+ {
+ A_UINT32 ROM_addr;
+ A_UINT32 RAM_addr;
+ A_UINT32 nbytes;
+ A_UINT32 do_activate;
+ A_UINT32 rompatch_id;
+
+ get_user(ROM_addr, (A_UINT32 *)userdata);
+ get_user(RAM_addr, (A_UINT32 *)userdata + 1);
+ get_user(nbytes, (A_UINT32 *)userdata + 2);
+ get_user(do_activate, (A_UINT32 *)userdata + 3);
+ AR_DEBUG_PRINTF("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n",
+ ROM_addr, RAM_addr, nbytes);
+ ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
+ nbytes, do_activate, &rompatch_id);
+ if (ret == A_OK) {
+ put_user(rompatch_id, (unsigned int *)rq->ifr_data); /* return value */
+ }
+ break;
+ }
+
+ case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
+ {
+ A_UINT32 rompatch_id;
+
+ get_user(rompatch_id, (A_UINT32 *)userdata);
+ AR_DEBUG_PRINTF("UNinstall rompatch_id %d\n", rompatch_id);
+ ret = BMIrompatchUninstall(hifDevice, rompatch_id);
+ break;
+ }
+
+ case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
+ case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
+ {
+ A_UINT32 rompatch_count;
+
+ get_user(rompatch_count, (A_UINT32 *)userdata);
+ AR_DEBUG_PRINTF("Change rompatch activation count=%d\n", rompatch_count);
+ length = sizeof(A_UINT32) * rompatch_count;
+ if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
+ A_MEMZERO(buffer, length);
+ if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
+ {
+ ret = -EFAULT;
+ } else {
+ if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
+ ret = BMIrompatchActivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+ } else {
+ ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (A_UINT32 *)buffer);
+ }
+ }
+ A_FREE(buffer);
+ } else {
+ ret = -ENOMEM;
+ }
+
+ break;
+ }
+
+ case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
+ {
+ WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setHostSleepMode, userdata,
+ sizeof(setHostSleepMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
+ &setHostSleepMode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_SET_WOW_MODE:
+ {
+ WMI_SET_WOW_MODE_CMD setWowMode;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&setWowMode, userdata,
+ sizeof(setWowMode)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_wow_mode_cmd(ar->arWmi,
+ &setWowMode) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_GET_WOW_LIST:
+ {
+ WMI_GET_WOW_LIST_CMD getWowList;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&getWowList, userdata,
+ sizeof(getWowList)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_get_wow_list_cmd(ar->arWmi,
+ &getWowList) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
+ {
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+ WMI_ADD_WOW_PATTERN_CMD cmd;
+ A_UINT8 mask_data[WOW_PATTERN_SIZE]={0};
+ A_UINT8 pattern_data[WOW_PATTERN_SIZE]={0};
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+
+ if(copy_from_user(&cmd, userdata,
+ sizeof(WMI_ADD_WOW_PATTERN_CMD)))
+ return -EFAULT;
+ if (copy_from_user(pattern_data,
+ userdata + 3,
+ cmd.filter_size)){
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(mask_data,
+ (userdata + 3 + cmd.filter_size),
+ cmd.filter_size)){
+ ret = -EFAULT;
+ break;
+ } else {
+ if (wmi_add_wow_pattern_cmd(ar->arWmi,
+ &cmd, pattern_data, mask_data, cmd.filter_size) != A_OK){
+ ret = -EIO;
+ }
+ }
+ }
+#undef WOW_PATTERN_SIZE
+#undef WOW_MASK_SIZE
+ break;
+ }
+ case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
+ {
+ WMI_DEL_WOW_PATTERN_CMD delWowPattern;
+
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&delWowPattern, userdata,
+ sizeof(delWowPattern)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_del_wow_pattern_cmd(ar->arWmi,
+ &delWowPattern) != A_OK)
+ {
+ ret = -EIO;
+ }
+ }
+ break;
+ }
+ case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
+ if (ar->arHtcTarget != NULL) {
+ HTCDumpCreditStates(ar->arHtcTarget);
+ }
+ break;
+ case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
+ if (ar->arHtcTarget != NULL) {
+ struct ar6000_traffic_activity_change data;
+
+ if (copy_from_user(&data, userdata, sizeof(data)))
+ {
+ return -EFAULT;
+ }
+ /* note, this is used for testing (mbox ping testing), indicate activity
+ * change using the stream ID as the traffic class */
+ ar6000_indicate_tx_activity(ar,
+ (A_UINT8)data.StreamID,
+ data.Active ? TRUE : FALSE);
+ }
+ break;
+ case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&connectCtrlFlags, userdata,
+ sizeof(connectCtrlFlags)))
+ {
+ ret = -EFAULT;
+ } else {
+ ar->arConnectCtrlFlags = connectCtrlFlags;
+ }
+ break;
+ case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else if (copy_from_user(&akmpParams, userdata,
+ sizeof(WMI_SET_AKMP_PARAMS_CMD)))
+ {
+ ret = -EFAULT;
+ } else {
+ if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ if (copy_from_user(&pmkidInfo.numPMKID, userdata,
+ sizeof(pmkidInfo.numPMKID)))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (copy_from_user(&pmkidInfo.pmkidList,
+ userdata + sizeof(pmkidInfo.numPMKID),
+ pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
+ {
+ ret = -EFAULT;
+ break;
+ }
+ if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
+ if (ar->arWmiReady == FALSE) {
+ ret = -EIO;
+ } else {
+ if (wmi_get_pmkid_list_cmd(ar->arWmi) != A_OK) {
+ ret = -EIO;
+ }
+ }
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ }
+ return ret;
+}
+
--- /dev/null
+++ b/drivers/ar6000/ar6000/netbuf.c
@@ -0,0 +1,225 @@
+
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <a_config.h>
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "htc_packet.h"
+
+#define AR6000_DATA_OFFSET 64
+
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+ skb_queue_tail((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt)
+{
+ skb_queue_head((struct sk_buff_head *) q, (struct sk_buff *) pkt);
+}
+
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q)
+{
+ return((void *) skb_dequeue((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q)
+{
+ return(skb_queue_len((struct sk_buff_head *) q));
+}
+
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q)
+{
+ return(skb_queue_empty((struct sk_buff_head *) q));
+}
+
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q)
+{
+ skb_queue_head_init((struct sk_buff_head *) q);
+}
+
+void *
+a_netbuf_alloc(int size)
+{
+ struct sk_buff *skb;
+ skb = dev_alloc_skb(AR6000_DATA_OFFSET + sizeof(HTC_PACKET) + size);
+ skb_reserve(skb, AR6000_DATA_OFFSET + sizeof(HTC_PACKET));
+ return ((void *)skb);
+}
+
+/*
+ * Allocate an SKB w.o. any encapsulation requirement.
+ */
+void *
+a_netbuf_alloc_raw(int size)
+{
+ struct sk_buff *skb;
+
+ skb = dev_alloc_skb(size);
+
+ return ((void *)skb);
+}
+
+void
+a_netbuf_free(void *bufPtr)
+{
+ struct sk_buff *skb = (struct sk_buff *)bufPtr;
+
+ dev_kfree_skb(skb);
+}
+
+A_UINT32
+a_netbuf_to_len(void *bufPtr)
+{
+ return (((struct sk_buff *)bufPtr)->len);
+}
+
+void *
+a_netbuf_to_data(void *bufPtr)
+{
+ return (((struct sk_buff *)bufPtr)->data);
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_push(void *bufPtr, A_INT32 len)
+{
+ skb_push((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Add len # of bytes to the beginning of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+ skb_push((struct sk_buff *) bufPtr, len);
+ A_MEMCPY(((struct sk_buff *)bufPtr)->data, srcPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr
+ */
+A_STATUS
+a_netbuf_put(void *bufPtr, A_INT32 len)
+{
+ skb_put((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Add len # of bytes to the end of the network buffer
+ * pointed to by bufPtr and also fill with data
+ */
+A_STATUS
+a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len)
+{
+ char *start = ((struct sk_buff *)bufPtr)->data +
+ ((struct sk_buff *)bufPtr)->len;
+ skb_put((struct sk_buff *)bufPtr, len);
+ A_MEMCPY(start, srcPtr, len);
+
+ return A_OK;
+}
+
+
+/*
+ * Trim the network buffer pointed to by bufPtr to len # of bytes
+ */
+A_STATUS
+a_netbuf_setlen(void *bufPtr, A_INT32 len)
+{
+ skb_trim((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer.
+ */
+A_STATUS
+a_netbuf_trim(void *bufPtr, A_INT32 len)
+{
+ skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+ return A_OK;
+}
+
+/*
+ * Chop of len # of bytes from the end of the buffer and return the data.
+ */
+A_STATUS
+a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+ char *start = ((struct sk_buff *)bufPtr)->data +
+ (((struct sk_buff *)bufPtr)->len - len);
+
+ A_MEMCPY(dstPtr, start, len);
+ skb_trim((struct sk_buff *)bufPtr, ((struct sk_buff *)bufPtr)->len - len);
+
+ return A_OK;
+}
+
+
+/*
+ * Returns the number of bytes available to a a_netbuf_push()
+ */
+A_INT32
+a_netbuf_headroom(void *bufPtr)
+{
+ return (skb_headroom((struct sk_buff *)bufPtr));
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ */
+A_STATUS
+a_netbuf_pull(void *bufPtr, A_INT32 len)
+{
+ skb_pull((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
+/*
+ * Removes specified number of bytes from the beginning of the buffer
+ * and return the data
+ */
+A_STATUS
+a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len)
+{
+ A_MEMCPY(dstPtr, ((struct sk_buff *)bufPtr)->data, len);
+ skb_pull((struct sk_buff *)bufPtr, len);
+
+ return A_OK;
+}
+
--- /dev/null
+++ b/drivers/ar6000/ar6000/osapi_linux.h
@@ -0,0 +1,319 @@
+/*
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/osapi_linux.h#1 $
+ *
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _OSAPI_LINUX_H_
+#define _OSAPI_LINUX_H_
+
+#ifdef __KERNEL__
+
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+#include <linux/jiffies.h>
+#endif
+#include <linux/timer.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#ifdef KERNEL_2_4
+#include <asm/arch/irq.h>
+#include <asm/irq.h>
+#endif
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK __attribute__ ((packed))
+#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK __ATTRIB_PACK
+
+/*
+ * Endianes macros
+ */
+#define A_BE2CPU8(x) ntohb(x)
+#define A_BE2CPU16(x) ntohs(x)
+#define A_BE2CPU32(x) ntohl(x)
+
+#define A_LE2CPU8(x) (x)
+#define A_LE2CPU16(x) (x)
+#define A_LE2CPU32(x) (x)
+
+#define A_CPU2BE8(x) htonb(x)
+#define A_CPU2BE16(x) htons(x)
+#define A_CPU2BE32(x) htonl(x)
+
+#define A_MEMCPY(dst, src, len) memcpy((A_UINT8 *)(dst), (src), (len))
+#define A_MEMZERO(addr, len) memset(addr, 0, len)
+#define A_MEMCMP(addr1, addr2, len) memcmp((addr1), (addr2), (len))
+#define A_MALLOC(size) kmalloc((size), GFP_KERNEL)
+#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC)
+#define A_FREE(addr) kfree(addr)
+#define A_PRINTF(args...) printk(args)
+
+/* Mutual Exclusion */
+typedef spinlock_t A_MUTEX_T;
+#define A_MUTEX_INIT(mutex) spin_lock_init(mutex)
+#define A_MUTEX_LOCK(mutex) spin_lock_bh(mutex)
+#define A_MUTEX_UNLOCK(mutex) spin_unlock_bh(mutex)
+#define A_IS_MUTEX_VALID(mutex) TRUE /* okay to return true, since A_MUTEX_DELETE does nothing */
+#define A_MUTEX_DELETE(mutex) /* spin locks are not kernel resources so nothing to free.. */
+
+/* Get current time in ms adding a constant offset (in ms) */
+#define A_GET_MS(offset) \
+ (jiffies + ((offset) / 1000) * HZ)
+
+/*
+ * Timer Functions
+ */
+#define A_MDELAY(msecs) mdelay(msecs)
+typedef struct timer_list A_TIMER;
+
+#define A_INIT_TIMER(pTimer, pFunction, pArg) do { \
+ init_timer(pTimer); \
+ (pTimer)->function = (pFunction); \
+ (pTimer)->data = (unsigned long)(pArg); \
+} while (0)
+
+/*
+ * Start a Timer that elapses after 'periodMSec' milli-seconds
+ * Support is provided for a one-shot timer. The 'repeatFlag' is
+ * ignored.
+ */
+#define A_TIMEOUT_MS(pTimer, periodMSec, repeatFlag) do { \
+ if (repeatFlag) { \
+ printk("\n" __FILE__ ":%d: Timer Repeat requested\n",__LINE__); \
+ panic("Timer Repeat"); \
+ } \
+ mod_timer((pTimer), jiffies + HZ * (periodMSec) / 1000); \
+} while (0)
+
+/*
+ * Cancel the Timer.
+ */
+#define A_UNTIMEOUT(pTimer) do { \
+ del_timer((pTimer)); \
+} while (0)
+
+#define A_DELETE_TIMER(pTimer) do { \
+} while (0)
+
+/*
+ * Wait Queue related functions
+ */
+typedef wait_queue_head_t A_WAITQUEUE_HEAD;
+#define A_INIT_WAITQUEUE_HEAD(head) init_waitqueue_head(head)
+#ifndef wait_event_interruptible_timeout
+#define __wait_event_interruptible_timeout(wq, condition, ret) \
+do { \
+ wait_queue_t __wait; \
+ init_waitqueue_entry(&__wait, current); \
+ \
+ add_wait_queue(&wq, &__wait); \
+ for (;;) { \
+ set_current_state(TASK_INTERRUPTIBLE); \
+ if (condition) \
+ break; \
+ if (!signal_pending(current)) { \
+ ret = schedule_timeout(ret); \
+ if (!ret) \
+ break; \
+ continue; \
+ } \
+ ret = -ERESTARTSYS; \
+ break; \
+ } \
+ current->state = TASK_RUNNING; \
+ remove_wait_queue(&wq, &__wait); \
+} while (0)
+
+#define wait_event_interruptible_timeout(wq, condition, timeout) \
+({ \
+ long __ret = timeout; \
+ if (!(condition)) \
+ __wait_event_interruptible_timeout(wq, condition, __ret); \
+ __ret; \
+})
+#endif /* wait_event_interruptible_timeout */
+
+#define A_WAIT_EVENT_INTERRUPTIBLE_TIMEOUT(head, condition, timeout) do { \
+ wait_event_interruptible_timeout(head, condition, timeout); \
+} while (0)
+
+#define A_WAKE_UP(head) wake_up(head)
+
+#ifdef DEBUG
+#define A_ASSERT(expr) \
+ if (!(expr)) { \
+ printk(KERN_ALERT "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
+ panic(#expr); \
+ }
+
+#else
+#define A_ASSERT(expr)
+#endif /* DEBUG */
+
+/*
+ * Initialization of the network buffer subsystem
+ */
+#define A_NETBUF_INIT()
+
+/*
+ * Network buffer queue support
+ */
+typedef struct sk_buff_head A_NETBUF_QUEUE_T;
+
+#define A_NETBUF_QUEUE_INIT(q) \
+ a_netbuf_queue_init(q)
+
+#define A_NETBUF_ENQUEUE(q, pkt) \
+ a_netbuf_enqueue((q), (pkt))
+#define A_NETBUF_PREQUEUE(q, pkt) \
+ a_netbuf_prequeue((q), (pkt))
+#define A_NETBUF_DEQUEUE(q) \
+ (a_netbuf_dequeue(q))
+#define A_NETBUF_QUEUE_SIZE(q) \
+ a_netbuf_queue_size(q)
+#define A_NETBUF_QUEUE_EMPTY(q) \
+ a_netbuf_queue_empty(q)
+
+/*
+ * Network buffer support
+ */
+#define A_NETBUF_ALLOC(size) \
+ a_netbuf_alloc(size)
+#define A_NETBUF_ALLOC_RAW(size) \
+ a_netbuf_alloc_raw(size)
+#define A_NETBUF_FREE(bufPtr) \
+ a_netbuf_free(bufPtr)
+#define A_NETBUF_DATA(bufPtr) \
+ a_netbuf_to_data(bufPtr)
+#define A_NETBUF_LEN(bufPtr) \
+ a_netbuf_to_len(bufPtr)
+#define A_NETBUF_PUSH(bufPtr, len) \
+ a_netbuf_push(bufPtr, len)
+#define A_NETBUF_PUT(bufPtr, len) \
+ a_netbuf_put(bufPtr, len)
+#define A_NETBUF_TRIM(bufPtr,len) \
+ a_netbuf_trim(bufPtr, len)
+#define A_NETBUF_PULL(bufPtr, len) \
+ a_netbuf_pull(bufPtr, len)
+#define A_NETBUF_HEADROOM(bufPtr)\
+ a_netbuf_headroom(bufPtr)
+#define A_NETBUF_SETLEN(bufPtr,len) \
+ a_netbuf_setlen(bufPtr, len)
+
+/* Add data to end of a buffer */
+#define A_NETBUF_PUT_DATA(bufPtr, srcPtr, len) \
+ a_netbuf_put_data(bufPtr, srcPtr, len)
+
+/* Add data to start of the buffer */
+#define A_NETBUF_PUSH_DATA(bufPtr, srcPtr, len) \
+ a_netbuf_push_data(bufPtr, srcPtr, len)
+
+/* Remove data at start of the buffer */
+#define A_NETBUF_PULL_DATA(bufPtr, dstPtr, len) \
+ a_netbuf_pull_data(bufPtr, dstPtr, len)
+
+/* Remove data from the end of the buffer */
+#define A_NETBUF_TRIM_DATA(bufPtr, dstPtr, len) \
+ a_netbuf_trim_data(bufPtr, dstPtr, len)
+
+/* View data as "size" contiguous bytes of type "t" */
+#define A_NETBUF_VIEW_DATA(bufPtr, t, size) \
+ (t )( ((struct skbuf *)(bufPtr))->data)
+
+/* return the beginning of the headroom for the buffer */
+#define A_NETBUF_HEAD(bufPtr) \
+ ((((struct sk_buff *)(bufPtr))->head))
+
+/*
+ * OS specific network buffer access routines
+ */
+void *a_netbuf_alloc(int size);
+void *a_netbuf_alloc_raw(int size);
+void a_netbuf_free(void *bufPtr);
+void *a_netbuf_to_data(void *bufPtr);
+A_UINT32 a_netbuf_to_len(void *bufPtr);
+A_STATUS a_netbuf_push(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_push_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_put(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_put_data(void *bufPtr, char *srcPtr, A_INT32 len);
+A_STATUS a_netbuf_pull(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_pull_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_trim(void *bufPtr, A_INT32 len);
+A_STATUS a_netbuf_trim_data(void *bufPtr, char *dstPtr, A_INT32 len);
+A_STATUS a_netbuf_setlen(void *bufPtr, A_INT32 len);
+A_INT32 a_netbuf_headroom(void *bufPtr);
+void a_netbuf_enqueue(A_NETBUF_QUEUE_T *q, void *pkt);
+void a_netbuf_prequeue(A_NETBUF_QUEUE_T *q, void *pkt);
+void *a_netbuf_dequeue(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_size(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+int a_netbuf_queue_empty(A_NETBUF_QUEUE_T *q);
+void a_netbuf_queue_init(A_NETBUF_QUEUE_T *q);
+
+/*
+ * Kernel v.s User space functions
+ */
+A_UINT32 a_copy_to_user(void *to, const void *from, A_UINT32 n);
+A_UINT32 a_copy_from_user(void *to, const void *from, A_UINT32 n);
+
+#else /* __KERNEL__ */
+
+#ifdef __GNUC__
+#define __ATTRIB_PACK __attribute__ ((packed))
+#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN __attribute__ ((noreturn))
+#ifndef INLINE
+#define INLINE __inline__
+#endif
+#else /* Not GCC */
+#define __ATTRIB_PACK
+#define __ATTRIB_PRINTF
+#define __ATTRIB_NORETURN
+#ifndef INLINE
+#define INLINE __inline
+#endif
+#endif /* End __GNUC__ */
+
+#define PREPACK
+#define POSTPACK __ATTRIB_PACK
+
+#endif /* __KERNEL__ */
+
+#endif /* _OSAPI_LINUX_H_ */
--- /dev/null
+++ b/drivers/ar6000/ar6000/wireless_ext.c
@@ -0,0 +1,1972 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "ar6000_drv.h"
+
+static A_UINT8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+static void ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi);
+extern unsigned int wmitimeout;
+extern A_WAITQUEUE_HEAD arEvent;
+extern wait_queue_head_t ar6000_scan_queue;
+
+/*
+ * Encode a WPA or RSN information element as a custom
+ * element using the hostap format.
+ */
+static u_int
+encode_ie(void *buf, size_t bufsize,
+ const u_int8_t *ie, size_t ielen,
+ const char *leader, size_t leader_len)
+{
+ u_int8_t *p;
+ int i;
+
+ if (bufsize < leader_len)
+ return 0;
+ p = buf;
+ memcpy(p, leader, leader_len);
+ bufsize -= leader_len;
+ p += leader_len;
+ for (i = 0; i < ielen && bufsize > 2; i++)
+ p += sprintf(p, "%02x", ie[i]);
+ return (i == ielen ? p - (u_int8_t *)buf : 0);
+}
+
+void
+ar6000_scan_node(void *arg, bss_t *ni)
+{
+ struct iw_event iwe;
+#if WIRELESS_EXT > 14
+ char buf[64*2 + 30];
+#endif
+ struct ar_giwscan_param *param;
+ A_CHAR *current_ev;
+ A_CHAR *end_buf;
+ struct ieee80211_common_ie *cie;
+ struct iw_request_info info;
+
+ info.cmd = 0;
+ info.flags = 0;
+
+ param = (struct ar_giwscan_param *)arg;
+
+ if (param->current_ev >= param->end_buf) {
+ return;
+ }
+ if ((param->firstPass == TRUE) &&
+ ((ni->ni_cie.ie_wpa == NULL) && (ni->ni_cie.ie_rsn == NULL))) {
+ /*
+ * Only forward wpa bss's in first pass
+ */
+ return;
+ }
+
+ if ((param->firstPass == FALSE) &&
+ ((ni->ni_cie.ie_wpa != NULL) || (ni->ni_cie.ie_rsn != NULL))) {
+ /*
+ * Only forward non-wpa bss's in 2nd pass
+ */
+ return;
+ }
+
+ current_ev = param->current_ev;
+ end_buf = param->end_buf;
+
+ cie = &ni->ni_cie;
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWAP;
+ iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
+ A_MEMCPY(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
+ current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
+ IW_EV_ADDR_LEN);
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWESSID;
+ iwe.u.data.flags = 1;
+ iwe.u.data.length = cie->ie_ssid[1];
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
+ &cie->ie_ssid[2]);
+
+ if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWMODE;
+ iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
+ IW_MODE_MASTER : IW_MODE_ADHOC;
+ current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
+ IW_EV_UINT_LEN);
+ }
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWFREQ;
+ iwe.u.freq.m = cie->ie_chan * 100000;
+ iwe.u.freq.e = 1;
+ current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
+ IW_EV_FREQ_LEN);
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVQUAL;
+ ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
+ current_ev = iwe_stream_add_event(&info, current_ev, end_buf, &iwe,
+ IW_EV_QUAL_LEN);
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = SIOCGIWENCODE;
+ if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
+ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
+ } else {
+ iwe.u.data.flags = IW_ENCODE_DISABLED;
+ }
+ iwe.u.data.length = 0;
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe, "");
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
+ iwe.u.data.length = strlen(buf);
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe, buf);
+
+ if (cie->ie_wpa != NULL) {
+ static const char wpa_leader[] = "wpa_ie=";
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
+ cie->ie_wpa[1]+2,
+ wpa_leader, sizeof(wpa_leader)-1);
+
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
+ buf);
+ }
+ }
+
+ if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
+ static const char rsn_leader[] = "rsn_ie=";
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
+ cie->ie_rsn[1]+2,
+ rsn_leader, sizeof(rsn_leader)-1);
+
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
+ buf);
+ }
+ }
+
+ if (cie->ie_wmm != NULL) {
+ static const char wmm_leader[] = "wmm_ie=";
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
+ cie->ie_wmm[1]+2,
+ wmm_leader, sizeof(wmm_leader)-1);
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
+ buf);
+ }
+ }
+
+ if (cie->ie_ath != NULL) {
+ static const char ath_leader[] = "ath_ie=";
+
+ A_MEMZERO(&iwe, sizeof(iwe));
+ iwe.cmd = IWEVCUSTOM;
+ iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
+ cie->ie_ath[1]+2,
+ ath_leader, sizeof(ath_leader)-1);
+ if (iwe.u.data.length != 0) {
+ current_ev = iwe_stream_add_point(&info, current_ev, end_buf, &iwe,
+ buf);
+ }
+ }
+
+ param->current_ev = current_ev;
+}
+
+int
+ar6000_ioctl_giwscan(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ar_giwscan_param param;
+ int i;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ param.current_ev = extra;
+ param.end_buf = extra + IW_SCAN_MAX_DATA;
+ param.firstPass = TRUE;
+
+ /*
+ * Do two passes to insure WPA scan candidates
+ * are sorted to the front. This is a hack to deal with
+ * the wireless extensions capping scan results at
+ * IW_SCAN_MAX_DATA bytes. In densely populated environments
+ * it's easy to overflow this buffer (especially with WPA/RSN
+ * information elements). Note this sorting hack does not
+ * guarantee we won't overflow anyway.
+ */
+ for (i = 0; i < 2; i++) {
+ /*
+ * Translate data to WE format.
+ */
+ wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, &param);
+ param.firstPass = FALSE;
+ if (param.current_ev >= param.end_buf) {
+ data->length = param.current_ev - extra;
+ return -E2BIG;
+ }
+ }
+
+ if(!(data->length = param.current_ev - extra)) {
+ printk("%s(): data length %d\n", __FUNCTION__, data->length);
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+extern int reconnect_flag;
+/* SIOCSIWESSID */
+static int
+ar6000_ioctl_siwessid(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *ssid)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ A_STATUS status;
+ A_UINT8 arNetworkType;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ /*
+ * iwconfig passes a string with length excluding any trailing NUL.
+ * FIXME: we should be able to set an ESSID of 32 bytes, yet things fall
+ * over badly if we do. So we limit the ESSID to 31 bytes.
+ */
+ if (data->flags && (!data->length || data->length >= sizeof(ar->arSsid))) {
+ /*
+ * ssid is invalid
+ */
+ return -EINVAL;
+ }
+ /* Added for bug 25178, return an IOCTL error instead of target returning
+ Illegal parameter error when either the BSSID or channel is missing
+ and we cannot scan during connect.
+ */
+ if (data->flags) {
+ if (ar->arSkipScan == TRUE &&
+ (ar->arChannelHint == 0 ||
+ (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
+ !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
+ {
+ return -EINVAL;
+ }
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+
+ if (ar->arTxPending[WMI_CONTROL_PRI]) {
+ /*
+ * sleep until the command queue drains
+ */
+ wait_event_interruptible_timeout(arEvent,
+ ar->arTxPending[WMI_CONTROL_PRI] == 0, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ return -EINTR;
+ }
+ }
+
+ if (!data->flags) {
+ arNetworkType = ar->arNetworkType;
+ ar6000_init_profile_info(ar);
+ ar->arNetworkType = arNetworkType;
+ }
+
+ /*
+ * The original logic here prevented a disconnect if issuing an "essid off"
+ * if no ESSID was set, presumably to prevent sending multiple disconnects
+ * to the WMI.
+ *
+ * Unfortunately, this also meant that no disconnect was sent when we were
+ * already connected, but the profile has been changed since (which also
+ * clears the ESSID as a reminder that the WMI needs updating.)
+ *
+ * The "1 ||" makes sure we always disconnect or reconnect. The WMI doesn't
+ * seem to mind being sent multiple disconnects.
+ */
+ if (1 || (ar->arSsidLen) || (!data->flags))
+ {
+ if ((!data->flags) ||
+ (A_MEMCMP(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
+ (ar->arSsidLen != (data->length)))
+ {
+ /*
+ * SSID set previously or essid off has been issued.
+ *
+ * Disconnect Command is issued in two cases after wmi is ready
+ * (1) ssid is different from the previous setting
+ * (2) essid off has been issued
+ *
+ */
+ if (ar->arWmiReady == TRUE) {
+ reconnect_flag = 0;
+ status = wmi_disconnect_cmd(ar->arWmi);
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ if (ar->arSkipScan == FALSE) {
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ }
+ if (!data->flags) {
+ up(&ar->arSem);
+ return 0;
+ }
+ } else {
+ up(&ar->arSem);
+ }
+ }
+ else
+ {
+ /*
+ * SSID is same, so we assume profile hasn't changed.
+ * If the interface is up and wmi is ready, we issue
+ * a reconnect cmd. Issue a reconnect only we are already
+ * connected.
+ */
+ if((ar->arConnected == TRUE) && (ar->arWmiReady == TRUE))
+ {
+ reconnect_flag = TRUE;
+ status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
+ ar->arChannelHint);
+ up(&ar->arSem);
+ if (status != A_OK) {
+ return -EIO;
+ }
+ return 0;
+ }
+ else{
+ /*
+ * Dont return if connect is pending.
+ */
+ if(!(ar->arConnectPending)) {
+ up(&ar->arSem);
+ return 0;
+ }
+ }
+ }
+ }
+
+ ar->arSsidLen = data->length;
+ A_MEMCPY(ar->arSsid, ssid, ar->arSsidLen);
+
+ /* The ssid length check prevents second "essid off" from the user,
+ to be treated as a connect cmd. The second "essid off" is ignored.
+ */
+ if((ar->arWmiReady == TRUE) && (ar->arSsidLen > 0) )
+ {
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+ if (SHARED_AUTH == ar->arDot11AuthMode) {
+ ar6000_install_static_wep_keys(ar);
+ }
+ AR_DEBUG_PRINTF("Connect called with authmode %d dot11 auth %d"\
+ " PW crypto %d PW crypto Len %d GRP crypto %d"\
+ " GRP crypto Len %d\n",
+ ar->arAuthMode, ar->arDot11AuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto, ar->arGroupCryptoLen);
+ reconnect_flag = 0;
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+ status = wmi_connect_cmd(ar->arWmi, ar->arNetworkType,
+ ar->arDot11AuthMode, ar->arAuthMode,
+ ar->arPairwiseCrypto, ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto,ar->arGroupCryptoLen,
+ ar->arSsidLen, ar->arSsid,
+ ar->arReqBssid, ar->arChannelHint,
+ ar->arConnectCtrlFlags);
+
+
+ up(&ar->arSem);
+
+ if (status != A_OK) {
+ return -EIO;
+ }
+ ar->arConnectPending = TRUE;
+ }else{
+ up(&ar->arSem);
+ }
+ return 0;
+}
+
+/* SIOCGIWESSID */
+static int
+ar6000_ioctl_giwessid(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *essid)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ data->flags = 1;
+ data->length = ar->arSsidLen;
+ A_MEMCPY(essid, ar->arSsid, ar->arSsidLen);
+
+ return 0;
+}
+
+
+void ar6000_install_static_wep_keys(AR_SOFTC_T *ar)
+{
+ A_UINT8 index;
+ A_UINT8 keyUsage;
+
+ for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
+ if (ar->arWepKeyList[index].arKeyLen) {
+ keyUsage = GROUP_USAGE;
+ if (index == ar->arDefTxKeyIndex) {
+ keyUsage |= TX_USAGE;
+ }
+ wmi_addKey_cmd(ar->arWmi,
+ index,
+ WEP_CRYPT,
+ keyUsage,
+ ar->arWepKeyList[index].arKeyLen,
+ NULL,
+ ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL,
+ NO_SYNC_WMIFLAG);
+ }
+ }
+}
+
+int
+ar6000_ioctl_delkey(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ return 0;
+}
+
+int
+ar6000_ioctl_setmlme(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ieee80211req_mlme *mlme = (struct ieee80211req_mlme *)extra;
+
+ if ((ar->arWmiReady == FALSE) || (ar->arConnected != TRUE))
+ return -EIO;
+
+ switch (mlme->im_op) {
+ case IEEE80211_MLME_DISASSOC:
+ case IEEE80211_MLME_DEAUTH:
+ /* Not Supported */
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+int
+ar6000_ioctl_setwmmparams(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ return -EIO; /* for now */
+}
+
+int
+ar6000_ioctl_getwmmparams(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ return -EIO; /* for now */
+}
+
+int ar6000_ioctl_setoptie(struct net_device *dev, struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ /* The target generates the WPA/RSN IE */
+ return 0;
+}
+
+int
+ar6000_ioctl_setauthalg(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ieee80211req_authalg *req = (struct ieee80211req_authalg *)extra;
+ int ret = 0;
+
+
+ AR6000_SPIN_LOCK(&ar->arLock, 0);
+
+ if (req->auth_alg == AUTH_ALG_OPEN_SYSTEM) {
+ ar->arDot11AuthMode = OPEN_AUTH;
+ } else if (req->auth_alg == AUTH_ALG_LEAP) {
+ ar->arDot11AuthMode = LEAP_AUTH;
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arGroupCrypto = WEP_CRYPT;
+ } else {
+ ret = -EIO;
+ }
+
+ AR6000_SPIN_UNLOCK(&ar->arLock, 0);
+
+ return ret;
+}
+static int
+ar6000_ioctl_addpmkid(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ieee80211req_addpmkid *req = (struct ieee80211req_addpmkid *)extra;
+ A_STATUS status;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ AR_DEBUG_PRINTF("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
+ req->pi_bssid[0], req->pi_bssid[1], req->pi_bssid[2],
+ req->pi_bssid[3], req->pi_bssid[4], req->pi_bssid[5],
+ req->pi_enable);
+
+ status = wmi_setPmkid_cmd(ar->arWmi, req->pi_bssid, req->pi_pmkid,
+ req->pi_enable);
+
+ if (status != A_OK) {
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCSIWRATE
+ */
+int
+ar6000_ioctl_siwrate(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ A_UINT32 kbps;
+
+ if (rrq->fixed) {
+ kbps = rrq->value / 1000; /* rrq->value is in bps */
+ } else {
+ kbps = -1; /* -1 indicates auto rate */
+ }
+ if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps) == A_EINVAL)
+ {
+ AR_DEBUG_PRINTF("BitRate is not Valid %d\n", kbps);
+ return -EINVAL;
+ }
+ ar->arBitRate = kbps;
+ if(ar->arWmiReady == TRUE)
+ {
+ if (wmi_set_bitrate_cmd(ar->arWmi, kbps) != A_OK) {
+ return -EINVAL;
+ }
+ }
+ return 0;
+}
+
+/*
+ * SIOCGIWRATE
+ */
+int
+ar6000_ioctl_giwrate(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ int ret = 0;
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ if(ar->arWmiReady == TRUE)
+ {
+ ar->arBitRate = 0xFFFF;
+ if (wmi_get_bitrate_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+ wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+ }
+ /* If the interface is down or wmi is not ready or the target is not
+ connected - return the value stored in the device structure */
+ if (!ret) {
+ if (ar->arBitRate == -1) {
+ rrq->fixed = TRUE;
+ rrq->value = 0;
+ } else {
+ rrq->value = ar->arBitRate * 1000;
+ }
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+/*
+ * SIOCSIWTXPOW
+ */
+static int
+ar6000_ioctl_siwtxpow(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ A_UINT8 dbM;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arRadioSwitch == WLAN_ENABLED
+ && rrq->disabled) {
+ if (wmi_switch_radio(ar->arWmi, WLAN_DISABLED) < 0)
+ return -EIO;
+ ar->arRadioSwitch = WLAN_DISABLED;
+ } else if (ar->arRadioSwitch == WLAN_DISABLED
+ && !rrq->disabled) {
+ if (wmi_switch_radio(ar->arWmi, WLAN_ENABLED) < 0)
+ return -EIO;
+ ar->arRadioSwitch = WLAN_ENABLED;
+ }
+
+ if (rrq->fixed) {
+ if (rrq->flags != IW_TXPOW_DBM) {
+ return -EOPNOTSUPP;
+ }
+ ar->arTxPwr= dbM = rrq->value;
+ ar->arTxPwrSet = TRUE;
+ } else {
+ ar->arTxPwr = dbM = 0;
+ ar->arTxPwrSet = FALSE;
+ }
+ if(ar->arWmiReady == TRUE)
+ {
+ AR_DEBUG_PRINTF("Set tx pwr cmd %d dbM\n", dbM);
+ wmi_set_txPwr_cmd(ar->arWmi, dbM);
+ }
+ return 0;
+}
+
+/*
+ * SIOCGIWTXPOW
+ */
+int
+ar6000_ioctl_giwtxpow(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ int ret = 0;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arRadioSwitch == WLAN_DISABLED) {
+ rrq->disabled = 1;
+ return 0;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ if((ar->arWmiReady == TRUE) && (ar->arConnected == TRUE))
+ {
+ ar->arTxPwr = 0;
+
+ if (wmi_get_txPwr_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ ret = -EINTR;
+ }
+ }
+ /* If the interace is down or wmi is not ready or target is not connected
+ then return value stored in the device structure */
+
+ if (!ret) {
+ if (ar->arTxPwrSet == TRUE) {
+ rrq->fixed = TRUE;
+ }
+ rrq->value = ar->arTxPwr;
+ rrq->flags = IW_TXPOW_DBM;
+ }
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+/*
+ * SIOCSIWRETRY
+ * since iwconfig only provides us with one max retry value, we use it
+ * to apply to data frames of the BE traffic class.
+ */
+static int
+ar6000_ioctl_siwretry(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (rrq->disabled) {
+ return -EOPNOTSUPP;
+ }
+
+ if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
+ return -EOPNOTSUPP;
+ }
+
+ if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
+ return - EINVAL;
+ }
+ if(ar->arWmiReady == TRUE)
+ {
+ if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
+ rrq->value, 0) != A_OK){
+ return -EINVAL;
+ }
+ }
+ ar->arMaxRetries = rrq->value;
+ return 0;
+}
+
+/*
+ * SIOCGIWRETRY
+ */
+static int
+ar6000_ioctl_giwretry(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *rrq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ rrq->disabled = 0;
+ switch (rrq->flags & IW_RETRY_TYPE) {
+ case IW_RETRY_LIFETIME:
+ return -EOPNOTSUPP;
+ break;
+ case IW_RETRY_LIMIT:
+ rrq->flags = IW_RETRY_LIMIT;
+ switch (rrq->flags & IW_RETRY_MODIFIER) {
+ case IW_RETRY_MIN:
+ rrq->flags |= IW_RETRY_MIN;
+ rrq->value = WMI_MIN_RETRIES;
+ break;
+ case IW_RETRY_MAX:
+ rrq->flags |= IW_RETRY_MAX;
+ rrq->value = ar->arMaxRetries;
+ break;
+ }
+ break;
+ }
+ return 0;
+}
+
+/*
+ * SIOCSIWENCODE
+ */
+static int
+ar6000_ioctl_siwencode(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *keybuf)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ int index;
+ A_INT32 auth = ar->arDot11AuthMode;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ index = erq->flags & IW_ENCODE_INDEX;
+
+ if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
+ ((index - 1) > WMI_MAX_KEY_INDEX)))
+ {
+ return -EIO;
+ }
+
+ if (erq->flags & IW_ENCODE_DISABLED) {
+ /*
+ * Encryption disabled
+ */
+ if (index) {
+ /*
+ * If key index was specified then clear the specified key
+ */
+ index--;
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ ar->arWepKeyList[index].arKeyLen = 0;
+ }
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ ar->arGroupCrypto = NONE_CRYPT;
+ ar->arAuthMode = NONE_AUTH;
+ } else {
+ /*
+ * Enabling WEP encryption
+ */
+ if (index) {
+ index--; /* keyindex is off base 1 in iwconfig */
+ }
+
+ if (erq->flags & IW_ENCODE_OPEN) {
+ auth = OPEN_AUTH;
+ } else if (erq->flags & IW_ENCODE_RESTRICTED) {
+ auth = SHARED_AUTH;
+ }
+
+ if (erq->length) {
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
+ return -EIO;
+ }
+
+ A_MEMZERO(ar->arWepKeyList[index].arKey,
+ sizeof(ar->arWepKeyList[index].arKey));
+ A_MEMCPY(ar->arWepKeyList[index].arKey, keybuf, erq->length);
+ ar->arWepKeyList[index].arKeyLen = erq->length;
+ } else {
+ if (ar->arWepKeyList[index].arKeyLen == 0) {
+ return -EIO;
+ }
+ ar->arDefTxKeyIndex = index;
+ }
+
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arGroupCrypto = WEP_CRYPT;
+ ar->arDot11AuthMode = auth;
+ ar->arAuthMode = NONE_AUTH;
+ }
+
+ /*
+ * profile has changed. Erase ssid to signal change
+ */
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+
+ return 0;
+}
+
+static int
+ar6000_ioctl_giwencode(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *erq, char *key)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
+ A_UINT8 keyIndex;
+ struct ar_wep_key *wk;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arPairwiseCrypto == NONE_CRYPT) {
+ erq->length = 0;
+ erq->flags = IW_ENCODE_DISABLED;
+ } else {
+ /* get the keyIndex */
+ keyIndex = erq->flags & IW_ENCODE_INDEX;
+ if (0 == keyIndex) {
+ keyIndex = ar->arDefTxKeyIndex;
+ } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
+ (keyIndex - 1 > WMI_MAX_KEY_INDEX))
+ {
+ keyIndex = WMI_MIN_KEY_INDEX;
+ } else {
+ keyIndex--;
+ }
+ erq->flags = keyIndex + 1;
+ erq->flags |= IW_ENCODE_ENABLED;
+ wk = &ar->arWepKeyList[keyIndex];
+ if (erq->length > wk->arKeyLen) {
+ erq->length = wk->arKeyLen;
+ }
+ if (wk->arKeyLen) {
+ A_MEMCPY(key, wk->arKey, erq->length);
+ }
+ if (ar->arDot11AuthMode == OPEN_AUTH) {
+ erq->flags |= IW_ENCODE_OPEN;
+ } else if (ar->arDot11AuthMode == SHARED_AUTH) {
+ erq->flags |= IW_ENCODE_RESTRICTED;
+ }
+ }
+
+ return 0;
+}
+
+static int ar6000_ioctl_siwpower(struct net_device *dev,
+ struct iw_request_info *info,
+ union iwreq_data *wrqu, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
+ WMI_POWER_MODE power_mode;
+
+ if (wrqu->power.disabled)
+ power_mode = MAX_PERF_POWER;
+ else
+ power_mode = REC_POWER;
+
+ if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
+ return -EIO;
+
+ return 0;
+}
+
+static int ar6000_ioctl_giwpower(struct net_device *dev,
+ struct iw_request_info *info,
+ union iwreq_data *wrqu, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
+
+ return wmi_get_power_mode_cmd(ar->arWmi);
+}
+
+static int ar6000_ioctl_siwgenie(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *dwrq,
+ char *extra)
+{
+ /* The target does that for us */
+ return 0;
+}
+
+static int ar6000_ioctl_giwgenie(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *dwrq,
+ char *extra)
+{
+ return 0;
+}
+
+static int ar6000_ioctl_siwauth(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *param,
+ char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
+ int reset = 0;
+
+ switch (param->flags & IW_AUTH_INDEX) {
+ case IW_AUTH_WPA_VERSION:
+ if (param->value & IW_AUTH_WPA_VERSION_DISABLED) {
+ ar->arAuthMode = NONE_AUTH;
+ }
+ if (param->value & IW_AUTH_WPA_VERSION_WPA) {
+ ar->arAuthMode = WPA_AUTH;
+ }
+ if (param->value & IW_AUTH_WPA_VERSION_WPA2) {
+ ar->arAuthMode = WPA2_AUTH;
+ }
+
+ reset = 1;
+ break;
+ case IW_AUTH_CIPHER_PAIRWISE:
+ if (param->value & IW_AUTH_CIPHER_NONE) {
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ }
+ if (param->value & IW_AUTH_CIPHER_WEP40) {
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ }
+ if (param->value & IW_AUTH_CIPHER_TKIP) {
+ ar->arPairwiseCrypto = TKIP_CRYPT;
+ }
+ if (param->value & IW_AUTH_CIPHER_CCMP) {
+ ar->arPairwiseCrypto = AES_CRYPT;
+ }
+
+ reset = 1;
+ break;
+ case IW_AUTH_CIPHER_GROUP:
+ if (param->value & IW_AUTH_CIPHER_NONE) {
+ ar->arGroupCrypto = NONE_CRYPT;
+ }
+ if (param->value & IW_AUTH_CIPHER_WEP40) {
+ ar->arGroupCrypto = WEP_CRYPT;
+ }
+ if (param->value & IW_AUTH_CIPHER_TKIP) {
+ ar->arGroupCrypto = TKIP_CRYPT;
+ }
+ if (param->value & IW_AUTH_CIPHER_CCMP) {
+ ar->arGroupCrypto = AES_CRYPT;
+ }
+
+ reset = 1;
+ break;
+ case IW_AUTH_KEY_MGMT:
+ if (param->value & IW_AUTH_KEY_MGMT_PSK) {
+ if (ar->arAuthMode == WPA_AUTH) {
+ ar->arAuthMode = WPA_PSK_AUTH;
+ } else if (ar->arAuthMode == WPA2_AUTH) {
+ ar->arAuthMode = WPA2_PSK_AUTH;
+ }
+
+ reset = 1;
+ }
+ break;
+
+ case IW_AUTH_TKIP_COUNTERMEASURES:
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ wmi_set_tkip_countermeasures_cmd(ar->arWmi, param->value);
+ break;
+
+ case IW_AUTH_DROP_UNENCRYPTED:
+ break;
+
+ case IW_AUTH_80211_AUTH_ALG:
+ if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) {
+ ar->arDot11AuthMode = OPEN_AUTH;
+ }
+ if (param->value & IW_AUTH_ALG_SHARED_KEY) {
+ ar->arDot11AuthMode = SHARED_AUTH;
+ }
+ if (param->value & IW_AUTH_ALG_LEAP) {
+ ar->arDot11AuthMode = LEAP_AUTH;
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ ar->arGroupCrypto = WEP_CRYPT;
+ }
+
+ reset = 1;
+ break;
+
+ case IW_AUTH_WPA_ENABLED:
+ reset = 1;
+ break;
+
+ case IW_AUTH_RX_UNENCRYPTED_EAPOL:
+ break;
+
+ case IW_AUTH_PRIVACY_INVOKED:
+ break;
+
+ default:
+ printk("%s(): Unknown flag 0x%x\n", __FUNCTION__, param->flags);
+ return -EOPNOTSUPP;
+ }
+
+ if (reset) {
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+
+ return 0;
+}
+
+static int ar6000_ioctl_giwauth(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *dwrq,
+ char *extra)
+{
+ return 0;
+}
+
+static int ar6000_ioctl_siwencodeext(struct net_device *dev,
+ struct iw_request_info *info,
+ union iwreq_data *wrqu,
+ char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)netdev_priv(dev);
+ struct iw_point *encoding = &wrqu->encoding;
+ struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
+ int alg = ext->alg, idx;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ /* Determine and validate the key index */
+ idx = (encoding->flags & IW_ENCODE_INDEX) - 1;
+ if (idx) {
+ if (idx < 0 || idx > 3)
+ return -EINVAL;
+ }
+
+ if ((alg == IW_ENCODE_ALG_TKIP) || (alg == IW_ENCODE_ALG_CCMP)) {
+ struct ieee80211req_key ik;
+ KEY_USAGE key_usage;
+ CRYPTO_TYPE key_type = NONE_CRYPT;
+ int status;
+
+ ar->user_saved_keys.keyOk = FALSE;
+
+ if (alg == IW_ENCODE_ALG_TKIP) {
+ key_type = TKIP_CRYPT;
+ ik.ik_type = IEEE80211_CIPHER_TKIP;
+ } else {
+ key_type = AES_CRYPT;
+ ik.ik_type = IEEE80211_CIPHER_AES_CCM;
+ }
+
+ ik.ik_keyix = idx;
+ ik.ik_keylen = ext->key_len;
+ ik.ik_flags = IEEE80211_KEY_RECV;
+ if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
+ ik.ik_flags |= IEEE80211_KEY_XMIT
+ | IEEE80211_KEY_DEFAULT;
+ }
+
+ if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
+ memcpy(&ik.ik_keyrsc, ext->rx_seq, 8);
+ }
+
+ memcpy(ik.ik_keydata, ext->key, ext->key_len);
+
+ ar->user_saved_keys.keyType = key_type;
+ if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
+ key_usage = GROUP_USAGE;
+ memset(ik.ik_macaddr, 0, ETH_ALEN);
+ memcpy(&ar->user_saved_keys.bcast_ik, &ik,
+ sizeof(struct ieee80211req_key));
+ } else {
+ key_usage = PAIRWISE_USAGE;
+ memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
+ memcpy(&ar->user_saved_keys.ucast_ik, &ik,
+ sizeof(struct ieee80211req_key));
+ }
+
+ status = wmi_addKey_cmd(ar->arWmi, ik.ik_keyix, key_type,
+ key_usage, ik.ik_keylen,
+ (A_UINT8 *)&ik.ik_keyrsc,
+ ik.ik_keydata,
+ KEY_OP_INIT_VAL, SYNC_BEFORE_WMIFLAG);
+
+ if (status < 0)
+ return -EIO;
+
+ ar->user_saved_keys.keyOk = TRUE;
+
+ return 0;
+
+ } else {
+ /* WEP falls back to SIWENCODE */
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+
+static int ar6000_ioctl_giwencodeext(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *dwrq,
+ char *extra)
+{
+ return 0;
+}
+
+
+static int
+ar6000_ioctl_setparam(struct net_device *dev,
+ struct iw_request_info *info,
+ void *erq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ int *i = (int *)extra;
+ int param = i[0];
+ int value = i[1];
+ int ret = 0;
+ A_BOOL profChanged = FALSE;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ switch (param) {
+ case IEEE80211_PARAM_WPA:
+ switch (value) {
+ case WPA_MODE_WPA1:
+ ar->arAuthMode = WPA_AUTH;
+ profChanged = TRUE;
+ break;
+ case WPA_MODE_WPA2:
+ ar->arAuthMode = WPA2_AUTH;
+ profChanged = TRUE;
+ break;
+ case WPA_MODE_NONE:
+ ar->arAuthMode = NONE_AUTH;
+ profChanged = TRUE;
+ break;
+ default:
+ printk("IEEE80211_PARAM_WPA: Unknown value %d\n", value);
+ }
+ break;
+ case IEEE80211_PARAM_AUTHMODE:
+ switch(value) {
+ case IEEE80211_AUTH_WPA_PSK:
+ if (WPA_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA_PSK_AUTH;
+ profChanged = TRUE;
+ } else if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_PSK_AUTH;
+ profChanged = TRUE;
+ } else {
+ AR_DEBUG_PRINTF("Error - Setting PSK mode when WPA "\
+ "param was set to %d\n",
+ ar->arAuthMode);
+ ret = -1;
+ }
+ break;
+ case IEEE80211_AUTH_WPA_CCKM:
+ if (WPA2_AUTH == ar->arAuthMode) {
+ ar->arAuthMode = WPA2_AUTH_CCKM;
+ } else {
+ ar->arAuthMode = WPA_AUTH_CCKM;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_UCASTCIPHER:
+ switch (value) {
+ case IEEE80211_CIPHER_AES_CCM:
+ ar->arPairwiseCrypto = AES_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ ar->arPairwiseCrypto = TKIP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_WEP:
+ ar->arPairwiseCrypto = WEP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_NONE:
+ ar->arPairwiseCrypto = NONE_CRYPT;
+ profChanged = TRUE;
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_UCASTKEYLEN:
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+ ret = -EIO;
+ } else {
+ ar->arPairwiseCryptoLen = value;
+ }
+ break;
+ case IEEE80211_PARAM_MCASTCIPHER:
+ switch (value) {
+ case IEEE80211_CIPHER_AES_CCM:
+ ar->arGroupCrypto = AES_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ ar->arGroupCrypto = TKIP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_WEP:
+ ar->arGroupCrypto = WEP_CRYPT;
+ profChanged = TRUE;
+ break;
+ case IEEE80211_CIPHER_NONE:
+ ar->arGroupCrypto = NONE_CRYPT;
+ profChanged = TRUE;
+ break;
+ }
+ break;
+ case IEEE80211_PARAM_MCASTKEYLEN:
+ if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
+ ret = -EIO;
+ } else {
+ ar->arGroupCryptoLen = value;
+ }
+ break;
+ case IEEE80211_PARAM_COUNTERMEASURES:
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+ wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
+ break;
+ default:
+ break;
+ }
+
+ if (profChanged == TRUE) {
+ /*
+ * profile has changed. Erase ssid to signal change
+ */
+ A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
+ ar->arSsidLen = 0;
+ }
+
+ return ret;
+}
+
+int
+ar6000_ioctl_getparam(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ return -EIO; /* for now */
+}
+
+int
+ar6000_ioctl_setkey(struct net_device *dev, struct iw_request_info *info,
+ void *w, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct ieee80211req_key *ik = (struct ieee80211req_key *)extra;
+ KEY_USAGE keyUsage;
+ A_STATUS status;
+ CRYPTO_TYPE keyType = NONE_CRYPT;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ ar->user_saved_keys.keyOk = FALSE;
+
+ if ( 0 == memcmp(ik->ik_macaddr, "\x00\x00\x00\x00\x00\x00",
+ IEEE80211_ADDR_LEN)) {
+ keyUsage = GROUP_USAGE;
+ A_MEMCPY(&ar->user_saved_keys.bcast_ik, ik,
+ sizeof(struct ieee80211req_key));
+ } else {
+ keyUsage = PAIRWISE_USAGE;
+ A_MEMCPY(&ar->user_saved_keys.ucast_ik, ik,
+ sizeof(struct ieee80211req_key));
+ }
+
+ switch (ik->ik_type) {
+ case IEEE80211_CIPHER_WEP:
+ keyType = WEP_CRYPT;
+ break;
+ case IEEE80211_CIPHER_TKIP:
+ keyType = TKIP_CRYPT;
+ break;
+ case IEEE80211_CIPHER_AES_CCM:
+ keyType = AES_CRYPT;
+ break;
+ default:
+ break;
+ }
+ ar->user_saved_keys.keyType = keyType;
+
+ if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
+ if (NONE_CRYPT == keyType) {
+ return -EIO;
+ }
+
+ status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
+ ik->ik_keylen, (A_UINT8 *)&ik->ik_keyrsc,
+ ik->ik_keydata, KEY_OP_INIT_VAL,
+ SYNC_BEFORE_WMIFLAG);
+
+ if (status != A_OK) {
+ return -EIO;
+ }
+ } else {
+ status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
+ }
+
+ ar->user_saved_keys.keyOk = TRUE;
+
+ return 0;
+}
+
+
+/*
+ * SIOCGIWNAME
+ */
+int
+ar6000_ioctl_giwname(struct net_device *dev,
+ struct iw_request_info *info,
+ char *name, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ switch (ar->arPhyCapability) {
+ case (WMI_11A_CAPABILITY):
+ strncpy(name, "AR6000 802.11a", IFNAMSIZ);
+ break;
+ case (WMI_11G_CAPABILITY):
+ strncpy(name, "AR6000 802.11g", IFNAMSIZ);
+ break;
+ case (WMI_11AG_CAPABILITY):
+ strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
+ break;
+ default:
+ strncpy(name, "AR6000 802.11", IFNAMSIZ);
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCSIWFREQ
+ */
+int
+ar6000_ioctl_siwfreq(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_freq *freq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ /*
+ * We support limiting the channels via wmiconfig.
+ *
+ * We use this command to configure the channel hint for the connect cmd
+ * so it is possible the target will end up connecting to a different
+ * channel.
+ */
+ if (freq->e > 1) {
+ return -EINVAL;
+ } else if (freq->e == 1) {
+ ar->arChannelHint = freq->m / 100000;
+ } else {
+ ar->arChannelHint = wlan_ieee2freq(freq->m);
+ }
+
+ A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
+ return 0;
+}
+
+/*
+ * SIOCGIWFREQ
+ */
+int
+ar6000_ioctl_giwfreq(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_freq *freq, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arConnected != TRUE) {
+ return -EINVAL;
+ }
+
+ freq->m = ar->arBssChannel * 100000;
+ freq->e = 1;
+
+ return 0;
+}
+
+/*
+ * SIOCSIWMODE
+ */
+int
+ar6000_ioctl_siwmode(struct net_device *dev,
+ struct iw_request_info *info,
+ __u32 *mode, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ switch (*mode) {
+ case IW_MODE_INFRA:
+ ar->arNetworkType = INFRA_NETWORK;
+ break;
+ case IW_MODE_ADHOC:
+ ar->arNetworkType = ADHOC_NETWORK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCGIWMODE
+ */
+int
+ar6000_ioctl_giwmode(struct net_device *dev,
+ struct iw_request_info *info,
+ __u32 *mode, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ switch (ar->arNetworkType) {
+ case INFRA_NETWORK:
+ *mode = IW_MODE_INFRA;
+ break;
+ case ADHOC_NETWORK:
+ *mode = IW_MODE_ADHOC;
+ break;
+ default:
+ return -EIO;
+ }
+ return 0;
+}
+
+/*
+ * SIOCSIWSENS
+ */
+int
+ar6000_ioctl_siwsens(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *sens, char *extra)
+{
+ return 0;
+}
+
+/*
+ * SIOCGIWSENS
+ */
+int
+ar6000_ioctl_giwsens(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_param *sens, char *extra)
+{
+ sens->value = 0;
+ sens->fixed = 1;
+
+ return 0;
+}
+
+/*
+ * SIOCGIWRANGE
+ */
+int
+ar6000_ioctl_giwrange(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ struct iw_range *range = (struct iw_range *) extra;
+ int i, ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (down_interruptible(&ar->arSem)) {
+ return -ERESTARTSYS;
+ }
+ ar->arNumChannels = -1;
+ A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
+
+ if (wmi_get_channelList_cmd(ar->arWmi) != A_OK) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
+
+ if (signal_pending(current)) {
+ up(&ar->arSem);
+ return -EINTR;
+ }
+
+ data->length = sizeof(struct iw_range);
+ A_MEMZERO(range, sizeof(struct iw_range));
+
+ range->txpower_capa = IW_TXPOW_DBM;
+
+ range->min_pmp = 1 * 1024;
+ range->max_pmp = 65535 * 1024;
+ range->min_pmt = 1 * 1024;
+ range->max_pmt = 1000 * 1024;
+ range->pmp_flags = IW_POWER_PERIOD;
+ range->pmt_flags = IW_POWER_TIMEOUT;
+ range->pm_capa = 0;
+
+ range->we_version_compiled = WIRELESS_EXT;
+ range->we_version_source = 13;
+
+ range->retry_capa = IW_RETRY_LIMIT;
+ range->retry_flags = IW_RETRY_LIMIT;
+ range->min_retry = 0;
+ range->max_retry = 255;
+
+ range->num_frequency = range->num_channels = ar->arNumChannels;
+ for (i = 0; i < ar->arNumChannels; i++) {
+ range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
+ range->freq[i].m = ar->arChannelList[i] * 100000;
+ range->freq[i].e = 1;
+ /*
+ * Linux supports max of 32 channels, bail out once you
+ * reach the max.
+ */
+ if (i == IW_MAX_FREQUENCIES) {
+ break;
+ }
+ }
+
+ /* Max quality is max field value minus noise floor */
+ range->max_qual.qual = 0xff - 161;
+
+ /*
+ * In order to use dBm measurements, 'level' must be lower
+ * than any possible measurement (see iw_print_stats() in
+ * wireless tools). It's unclear how this is meant to be
+ * done, but setting zero in these values forces dBm and
+ * the actual numbers are not used.
+ */
+ range->max_qual.level = 0;
+ range->max_qual.noise = 0;
+
+ range->sensitivity = 3;
+
+ range->max_encoding_tokens = 4;
+ /* XXX query driver to find out supported key sizes */
+ range->num_encoding_sizes = 3;
+ range->encoding_size[0] = 5; /* 40-bit */
+ range->encoding_size[1] = 13; /* 104-bit */
+ range->encoding_size[2] = 16; /* 128-bit */
+
+ range->num_bitrates = 0;
+
+ /* estimated maximum TCP throughput values (bps) */
+ range->throughput = 22000000;
+
+ range->min_rts = 0;
+ range->max_rts = 2347;
+ range->min_frag = 256;
+ range->max_frag = 2346;
+
+ up(&ar->arSem);
+
+ return ret;
+}
+
+
+/*
+ * SIOCSIWAP
+ * This ioctl is used to set the desired bssid for the connect command.
+ */
+int
+ar6000_ioctl_siwap(struct net_device *dev,
+ struct iw_request_info *info,
+ struct sockaddr *ap_addr, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ap_addr->sa_family != ARPHRD_ETHER) {
+ return -EIO;
+ }
+
+ if (A_MEMCMP(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
+ A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
+ } else {
+ A_MEMCPY(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid));
+ }
+
+ return 0;
+}
+
+/*
+ * SIOCGIWAP
+ */
+int
+ar6000_ioctl_giwap(struct net_device *dev,
+ struct iw_request_info *info,
+ struct sockaddr *ap_addr, char *extra)
+{
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ if (ar->arConnected != TRUE) {
+ return -EINVAL;
+ }
+
+ A_MEMCPY(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
+ ap_addr->sa_family = ARPHRD_ETHER;
+
+ return 0;
+}
+
+/*
+ * SIOCGIWAPLIST
+ */
+int
+ar6000_ioctl_iwaplist(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+ return -EIO; /* for now */
+}
+
+/*
+ * SIOCSIWSCAN
+ */
+int
+ar6000_ioctl_siwscan(struct net_device *dev,
+ struct iw_request_info *info,
+ struct iw_point *data, char *extra)
+{
+#define ACT_DWELLTIME_DEFAULT 105
+#define HOME_TXDRAIN_TIME 100
+#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
+ AR_SOFTC_T *ar = (AR_SOFTC_T *)dev->priv;
+ int ret = 0;
+
+ if (ar->arWmiReady == FALSE) {
+ return -EIO;
+ }
+
+ if (ar->arWlanState == WLAN_DISABLED) {
+ return -EIO;
+ }
+
+ /* We ask for everything from the target */
+ if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != A_OK) {
+ printk("Couldn't set filtering\n");
+ ret = -EIO;
+ }
+
+ if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, FALSE, FALSE, \
+ HOME_TXDRAIN_TIME, SCAN_INT) != A_OK) {
+ ret = -EIO;
+ }
+
+ ar->scan_complete = 0;
+ wait_event_interruptible_timeout(ar6000_scan_queue, ar->scan_complete,
+ 5 * HZ);
+
+ if (wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0) != A_OK) {
+ printk("Couldn't set filtering\n");
+ ret = -EIO;
+ }
+
+ return ret;
+#undef ACT_DWELLTIME_DEFAULT
+#undef HOME_TXDRAIN_TIME
+#undef SCAN_INT
+}
+
+
+/*
+ * Units are in db above the noise floor. That means the
+ * rssi values reported in the tx/rx descriptors in the
+ * driver are the SNR expressed in db.
+ *
+ * If you assume that the noise floor is -95, which is an
+ * excellent assumption 99.5 % of the time, then you can
+ * derive the absolute signal level (i.e. -95 + rssi).
+ * There are some other slight factors to take into account
+ * depending on whether the rssi measurement is from 11b,
+ * 11g, or 11a. These differences are at most 2db and
+ * can be documented.
+ *
+ * NB: various calculations are based on the orinoco/wavelan
+ * drivers for compatibility
+ */
+static void
+ar6000_set_quality(struct iw_quality *iq, A_INT8 rssi)
+{
+ if (rssi < 0) {
+ iq->qual = 0;
+ } else {
+ iq->qual = rssi;
+ }
+
+ /* NB: max is 94 because noise is hardcoded to 161 */
+ if (iq->qual > 94)
+ iq->qual = 94;
+
+ iq->noise = 161; /* -95dBm */
+ iq->level = iq->noise + iq->qual;
+ iq->updated = 7;
+}
+
+
+/* Structures to export the Wireless Handlers */
+static const iw_handler ath_handlers[] = {
+ (iw_handler) NULL, /* SIOCSIWCOMMIT */
+ (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */
+ (iw_handler) NULL, /* SIOCSIWNWID */
+ (iw_handler) NULL, /* SIOCGIWNWID */
+ (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */
+ (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */
+ (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */
+ (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */
+ (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */
+ (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */
+ (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */
+ (iw_handler) ar6000_ioctl_giwrange, /* SIOCGIWRANGE */
+ (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */
+ (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */
+ (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */
+ (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */
+ (iw_handler) NULL, /* SIOCSIWSPY */
+ (iw_handler) NULL, /* SIOCGIWSPY */
+ (iw_handler) NULL, /* SIOCSIWTHRSPY */
+ (iw_handler) NULL, /* SIOCGIWTHRSPY */
+ (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */
+ (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */
+ (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */
+ (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */
+ (iw_handler) ar6000_ioctl_siwessid, /* SIOCSIWESSID */
+ (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */
+ (iw_handler) NULL, /* SIOCSIWNICKN */
+ (iw_handler) NULL, /* SIOCGIWNICKN */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */
+ (iw_handler) ar6000_ioctl_giwrate, /* SIOCGIWRATE */
+ (iw_handler) NULL, /* SIOCSIWRTS */
+ (iw_handler) NULL, /* SIOCGIWRTS */
+ (iw_handler) NULL, /* SIOCSIWFRAG */
+ (iw_handler) NULL, /* SIOCGIWFRAG */
+ (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */
+ (iw_handler) ar6000_ioctl_giwtxpow, /* SIOCGIWTXPOW */
+ (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */
+ (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */
+ (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */
+ (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */
+ (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */
+ (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) NULL, /* -- hole -- */
+ (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */
+ (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */
+ (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */
+ (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */
+ (iw_handler) ar6000_ioctl_siwencodeext,/* SIOCSIWENCODEEXT */
+ (iw_handler) ar6000_ioctl_giwencodeext,/* SIOCGIWENCODEEXT */
+ (iw_handler) NULL, /* SIOCSIWPMKSA */
+};
+
+static const iw_handler ath_priv_handlers[] = {
+ (iw_handler) ar6000_ioctl_setparam, /* SIOCWFIRSTPRIV+0 */
+ (iw_handler) ar6000_ioctl_getparam, /* SIOCWFIRSTPRIV+1 */
+ (iw_handler) ar6000_ioctl_setkey, /* SIOCWFIRSTPRIV+2 */
+ (iw_handler) ar6000_ioctl_setwmmparams, /* SIOCWFIRSTPRIV+3 */
+ (iw_handler) ar6000_ioctl_delkey, /* SIOCWFIRSTPRIV+4 */
+ (iw_handler) ar6000_ioctl_getwmmparams, /* SIOCWFIRSTPRIV+5 */
+ (iw_handler) ar6000_ioctl_setoptie, /* SIOCWFIRSTPRIV+6 */
+ (iw_handler) ar6000_ioctl_setmlme, /* SIOCWFIRSTPRIV+7 */
+ (iw_handler) ar6000_ioctl_addpmkid, /* SIOCWFIRSTPRIV+8 */
+};
+
+#define IW_PRIV_TYPE_KEY \
+ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_key))
+#define IW_PRIV_TYPE_DELKEY \
+ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_del_key))
+#define IW_PRIV_TYPE_MLME \
+ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_mlme))
+#define IW_PRIV_TYPE_ADDPMKID \
+ (IW_PRIV_TYPE_BYTE | sizeof(struct ieee80211req_addpmkid))
+
+static const struct iw_priv_args ar6000_priv_args[] = {
+ { IEEE80211_IOCTL_SETKEY,
+ IW_PRIV_TYPE_KEY | IW_PRIV_SIZE_FIXED, 0, "setkey"},
+ { IEEE80211_IOCTL_DELKEY,
+ IW_PRIV_TYPE_DELKEY | IW_PRIV_SIZE_FIXED, 0, "delkey"},
+ { IEEE80211_IOCTL_SETPARAM,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setparam"},
+ { IEEE80211_IOCTL_GETPARAM,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getparam"},
+ { IEEE80211_IOCTL_SETWMMPARAMS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 4, 0, "setwmmparams"},
+ { IEEE80211_IOCTL_GETWMMPARAMS,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3,
+ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, "getwmmparams"},
+ { IEEE80211_IOCTL_SETOPTIE,
+ IW_PRIV_TYPE_BYTE, 0, "setie"},
+ { IEEE80211_IOCTL_SETMLME,
+ IW_PRIV_TYPE_MLME, 0, "setmlme"},
+ { IEEE80211_IOCTL_ADDPMKID,
+ IW_PRIV_TYPE_ADDPMKID | IW_PRIV_SIZE_FIXED, 0, "addpmkid"},
+};
+
+void ar6000_ioctl_iwsetup(struct iw_handler_def *def)
+{
+ def->private_args = (struct iw_priv_args *)ar6000_priv_args;
+ def->num_private_args = ARRAY_SIZE(ar6000_priv_args);
+}
+
+struct iw_handler_def ath_iw_handler_def = {
+ .standard = (iw_handler *)ath_handlers,
+ .num_standard = ARRAY_SIZE(ath_handlers),
+ .private = (iw_handler *)ath_priv_handlers,
+ .num_private = ARRAY_SIZE(ath_priv_handlers),
+};
+
+
--- /dev/null
+++ b/drivers/ar6000/bmi/bmi.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "hif.h"
+#include "bmi.h"
+#include "htc_api.h"
+#include "bmi_internal.h"
+
+/*
+Although we had envisioned BMI to run on top of HTC, this is not what the
+final implementation boiled down to on dragon. Its a part of BSP and does
+not use the HTC protocol either. On the host side, however, we were still
+living with the original idea. I think the time has come to accept the truth
+and separate it from HTC which has been carrying BMI's burden all this while.
+It shall make HTC state machine relatively simpler
+*/
+
+/* APIs visible to the driver */
+void
+BMIInit(void)
+{
+ bmiDone = FALSE;
+}
+
+A_STATUS
+BMIDone(HIF_DEVICE *device)
+{
+ A_STATUS status;
+ A_UINT32 cid;
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF (ATH_DEBUG_BMI, ("BMIDone skipped\n"));
+ return A_OK;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Enter (device: 0x%p)\n", device));
+ bmiDone = TRUE;
+ cid = BMI_DONE;
+
+ status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Done: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info)
+{
+ A_STATUS status;
+ A_UINT32 cid;
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Enter (device: 0x%p)\n", device));
+ cid = BMI_GET_TARGET_INFO;
+
+ status = bmiBufferSend(device, (A_UCHAR *)&cid, sizeof(cid));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_ver,
+ sizeof(targ_info->target_ver));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Version from the device\n"));
+ return A_ERROR;
+ }
+
+ if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
+ /* Determine how many bytes are in the Target's targ_info */
+ status = bmiBufferReceive(device, (A_UCHAR *)&targ_info->target_info_byte_count,
+ sizeof(targ_info->target_info_byte_count));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info Byte Count from the device\n"));
+ return A_ERROR;
+ }
+
+ /*
+ * The Target's targ_info doesn't match the Host's targ_info.
+ * We need to do some backwards compatibility work to make this OK.
+ */
+ A_ASSERT(targ_info->target_info_byte_count == sizeof(*targ_info));
+
+ /* Read the remainder of the targ_info */
+ status = bmiBufferReceive(device,
+ ((A_UCHAR *)targ_info)+sizeof(targ_info->target_info_byte_count),
+ sizeof(*targ_info)-sizeof(targ_info->target_info_byte_count));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read Target Info (%d bytes) from the device\n",
+ targ_info->target_info_byte_count));
+ return A_ERROR;
+ }
+ } else {
+ /*
+ * Target must be an AR6001 whose firmware does not
+ * support BMI_GET_TARGET_INFO. Construct the data
+ * that it would have sent.
+ */
+ targ_info->target_info_byte_count = sizeof(targ_info);
+ targ_info->target_type = TARGET_TYPE_AR6001;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
+ targ_info->target_ver, targ_info->target_type));
+ printk("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
+ targ_info->target_ver, targ_info->target_type);
+
+ return A_OK;
+}
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ A_UINT32 remaining, rxlen;
+ static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)];
+ memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Read Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+ device, address, length));
+
+ cid = BMI_READ_MEMORY;
+
+ remaining = length;
+
+ while (remaining)
+ {
+ rxlen = (remaining < BMI_DATASZ_MAX) ? remaining : BMI_DATASZ_MAX;
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&data[offset], &rxlen, sizeof(rxlen));
+ offset += sizeof(length);
+
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+ status = bmiBufferReceive(device, data, rxlen);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+ A_MEMCPY(&buffer[length - remaining], data, rxlen);
+ remaining -= rxlen; address += rxlen;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read Memory: Exit\n"));
+ return A_OK;
+}
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ A_UINT32 remaining, txlen;
+ const A_UINT32 header = sizeof(cid) + sizeof(address) + sizeof(length);
+ static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(address) + sizeof(length)];
+ memset (&data, 0, header);
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Write Memory: Enter (device: 0x%p, address: 0x%x, length: %d)\n",
+ device, address, length));
+
+ cid = BMI_WRITE_MEMORY;
+
+ remaining = length;
+ while (remaining)
+ {
+ txlen = (remaining < (BMI_DATASZ_MAX - header)) ?
+ remaining : (BMI_DATASZ_MAX - header);
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&data[offset], &txlen, sizeof(txlen));
+ offset += sizeof(txlen);
+ A_MEMCPY(&data[offset], &buffer[length - remaining], txlen);
+ offset += txlen;
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+ remaining -= txlen; address += txlen;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Write Memory: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(*param)];
+ memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(*param));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Execute: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+ device, address, *param));
+
+ cid = BMI_EXECUTE;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&data[offset], param, sizeof(*param));
+ offset += sizeof(*param);
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, data, sizeof(*param));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+
+ A_MEMCPY(param, data, sizeof(*param));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Execute: Exit (param: %d)\n", *param));
+ return A_OK;
+}
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+ A_UINT32 address)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[sizeof(cid) + sizeof(address)];
+ memset (&data, 0, sizeof(cid) + sizeof(address));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Set App Start: Enter (device: 0x%p, address: 0x%x)\n",
+ device, address));
+
+ cid = BMI_SET_APP_START;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &address, sizeof(address));
+ offset += sizeof(address);
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Set App Start: Exit\n"));
+ return A_OK;
+}
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[sizeof(cid) + sizeof(address)];
+ memset (&data, 0, sizeof(cid) + sizeof(address));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Read SOC Register: Enter (device: 0x%p, address: 0x%x)\n",
+ device, address));
+
+ cid = BMI_READ_SOC_REGISTER;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &address, sizeof(address));
+ offset += sizeof(address);
+
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, data, sizeof(*param));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+ A_MEMCPY(param, data, sizeof(*param));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit (value: %d)\n", *param));
+ return A_OK;
+}
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 param)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[sizeof(cid) + sizeof(address) + sizeof(param)];
+
+ memset (&data, 0, sizeof(cid) + sizeof(address) + sizeof(param));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Write SOC Register: Enter (device: 0x%p, address: 0x%x, param: %d)\n",
+ device, address, param));
+
+ cid = BMI_WRITE_SOC_REGISTER;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &address, sizeof(address));
+ offset += sizeof(address);
+ A_MEMCPY(&data[offset], &param, sizeof(param));
+ offset += sizeof(param);
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Read SOC Register: Exit\n"));
+ return A_OK;
+}
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+ A_UINT32 ROM_addr,
+ A_UINT32 RAM_addr,
+ A_UINT32 nbytes,
+ A_UINT32 do_activate,
+ A_UINT32 *rompatch_id)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+ sizeof(nbytes) + sizeof(do_activate)];
+
+ memset (&data, 0, sizeof(cid) + sizeof(ROM_addr) + sizeof(RAM_addr) +
+ sizeof(nbytes) + sizeof(do_activate));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI rompatch Install: Enter (device: 0x%p, ROMaddr: 0x%x, RAMaddr: 0x%x length: %d activate: %d)\n",
+ device, ROM_addr, RAM_addr, nbytes, do_activate));
+
+ cid = BMI_ROMPATCH_INSTALL;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &ROM_addr, sizeof(ROM_addr));
+ offset += sizeof(ROM_addr);
+ A_MEMCPY(&data[offset], &RAM_addr, sizeof(RAM_addr));
+ offset += sizeof(RAM_addr);
+ A_MEMCPY(&data[offset], &nbytes, sizeof(nbytes));
+ offset += sizeof(nbytes);
+ A_MEMCPY(&data[offset], &do_activate, sizeof(do_activate));
+ offset += sizeof(do_activate);
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ status = bmiBufferReceive(device, (A_UCHAR *)rompatch_id, sizeof(*rompatch_id));
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read from the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch Install: (rompatch_id=%d)\n", *rompatch_id));
+ return A_OK;
+}
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+ A_UINT32 rompatch_id)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[sizeof(cid) + sizeof(rompatch_id)];
+ memset (&data, 0, sizeof(cid) + sizeof(rompatch_id));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI rompatch Uninstall: Enter (device: 0x%p, rompatch_id: %d)\n",
+ device, rompatch_id));
+
+ cid = BMI_ROMPATCH_UNINSTALL;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &rompatch_id, sizeof(rompatch_id));
+ offset += sizeof(rompatch_id);
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI rompatch UNinstall: (rompatch_id=0x%x)\n", rompatch_id));
+ return A_OK;
+}
+
+static A_STATUS
+_BMIrompatchChangeActivation(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list,
+ A_UINT32 do_activate)
+{
+ A_UINT32 cid;
+ A_STATUS status;
+ A_UINT32 offset;
+ static A_UCHAR data[BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count)];
+ A_UINT32 length;
+
+ memset (&data, 0, BMI_DATASZ_MAX + sizeof(cid) + sizeof(rompatch_count));
+
+ if (bmiDone) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Command disallowed\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
+ ("BMI Change rompatch Activation: Enter (device: 0x%p, count: %d)\n",
+ device, rompatch_count));
+
+ cid = do_activate ? BMI_ROMPATCH_ACTIVATE : BMI_ROMPATCH_DEACTIVATE;
+
+ offset = 0;
+ A_MEMCPY(&data[offset], &cid, sizeof(cid));
+ offset += sizeof(cid);
+ A_MEMCPY(&data[offset], &rompatch_count, sizeof(rompatch_count));
+ offset += sizeof(rompatch_count);
+ length = rompatch_count * sizeof(*rompatch_list);
+ A_MEMCPY(&data[offset], rompatch_list, length);
+ offset += length;
+ status = bmiBufferSend(device, data, offset);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to write to the device\n"));
+ return A_ERROR;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Change rompatch Activation: Exit\n"));
+
+ return A_OK;
+}
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list)
+{
+ return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 1);
+}
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list)
+{
+ return _BMIrompatchChangeActivation(device, rompatch_count, rompatch_list, 0);
+}
+
+/* BMI Access routines */
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_STATUS status;
+ A_UINT32 timeout;
+ A_UINT32 address;
+ static A_UINT32 cmdCredits;
+ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+
+ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+ &mboxAddress, sizeof(mboxAddress));
+
+ cmdCredits = 0;
+ timeout = BMI_COMMUNICATION_TIMEOUT;
+
+ while(timeout-- && !cmdCredits) {
+ /* Read the counter register to get the command credits */
+ address = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
+ /* hit the credit counter with a 4-byte access, the first byte read will hit the counter and cause
+ * a decrement, while the remaining 3 bytes has no effect. The rationale behind this is to
+ * make all HIF accesses 4-byte aligned */
+ status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, 4,
+ HIF_RD_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to decrement the command credit count register\n"));
+ return A_ERROR;
+ }
+ /* the counter is only 8=bits, ignore anything in the upper 3 bytes */
+ cmdCredits &= 0xFF;
+ }
+
+ if (cmdCredits) {
+ address = mboxAddress[ENDPOINT1];
+ status = HIFReadWrite(device, address, buffer, length,
+ HIF_WR_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to send the BMI data to the device\n"));
+ return A_ERROR;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("BMI Communication timeout\n"));
+ return A_ERROR;
+ }
+
+ return status;
+}
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length)
+{
+ A_STATUS status;
+ A_UINT32 address;
+ A_UINT32 timeout;
+ static A_UINT32 cmdCredits;
+ A_UINT32 mboxAddress[HTC_MAILBOX_NUM_MAX];
+
+ HIFConfigureDevice(device, HIF_DEVICE_GET_MBOX_ADDR,
+ &mboxAddress, sizeof(mboxAddress));
+
+ cmdCredits = 0;
+ timeout = BMI_COMMUNICATION_TIMEOUT;
+ while(timeout-- && !cmdCredits) {
+ /* Read the counter register to get the command credits */
+ address = COUNT_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 1;
+ /* read the counter using a 4-byte read. Since the counter is NOT auto-decrementing,
+ * we can read this counter multiple times using a non-incrementing address mode.
+ * The rationale here is to make all HIF accesses a multiple of 4 bytes */
+ status = HIFReadWrite(device, address, (A_UINT8 *)&cmdCredits, sizeof(cmdCredits),
+ HIF_RD_SYNC_BYTE_FIX, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the command credit count register\n"));
+ return A_ERROR;
+ }
+ /* we did a 4-byte read to the same count register so mask off upper bytes */
+ cmdCredits &= 0xFF;
+ status = A_ERROR;
+ }
+
+ if (cmdCredits) {
+ address = mboxAddress[ENDPOINT1];
+ status = HIFReadWrite(device, address, buffer, length,
+ HIF_RD_SYNC_BYTE_INC, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to read the BMI data from the device\n"));
+ return A_ERROR;
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_BMI, ("BMI Communication timeout\n"));
+ return A_ERROR;
+ }
+
+ return status;
+}
--- /dev/null
+++ b/drivers/ar6000/bmi/bmi_internal.h
@@ -0,0 +1,45 @@
+#ifndef BMI_INTERNAL_H
+#define BMI_INTERNAL_H
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "a_debug.h"
+#include "AR6Khwreg.h"
+#include "bmi_msg.h"
+
+#define BMI_COMMUNICATION_TIMEOUT 100000
+
+/* ------ Global Variable Declarations ------- */
+A_BOOL bmiDone;
+
+A_STATUS
+bmiBufferSend(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+bmiBufferReceive(HIF_DEVICE *device,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/hif/hif2.c
@@ -0,0 +1,646 @@
+/*
+ * hif2.c - HIF layer re-implementation for the Linux SDIO stack
+ *
+ * Copyright (C) 2008 by OpenMoko, Inc.
+ * Written by Werner Almesberger <werner@openmoko.org>
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Based on:
+ *
+ * @abstract: HIF layer reference implementation for Atheros SDIO stack
+ * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/list.h>
+#include <linux/wait.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/sdio_ids.h>
+#include <asm/gpio.h>
+
+#include "athdefs.h"
+#include "a_types.h"
+#include "hif.h"
+
+
+/*
+ * KNOWN BUGS:
+ *
+ * - HIF_DEVICE_IRQ_ASYNC_SYNC doesn't work yet (gets MMC errors)
+ * - latency can reach hundreds of ms, probably because of scheduling delays
+ * - packets go through about three queues before finally hitting the network
+ */
+
+/*
+ * Differences from Atheros' HIFs:
+ *
+ * - synchronous and asynchronous requests may get reordered with respect to
+ * each other, e.g., if HIFReadWrite returns for an asynchronous request and
+ * then HIFReadWrite is called for a synchronous request, the synchronous
+ * request may be executed before the asynchronous request.
+ *
+ * - request queue locking seems unnecessarily complex in the Atheros HIFs.
+ *
+ * - Atheros mask interrupts by calling sdio_claim_irq/sdio_release_irq, which
+ * can cause quite a bit of overhead. This HIF has its own light-weight
+ * interrupt masking.
+ *
+ * - Atheros call deviceInsertedHandler from a thread spawned off the probe or
+ * device insertion function. The original explanation for the Atheros SDIO
+ * stack said that this is done because a delay is needed to let the chip
+ * complete initialization. There is indeed a one second delay in the thread.
+ *
+ * The Atheros Linux SDIO HIF removes the delay and only retains the thread.
+ * Experimentally removing the thread didn't show any conflicts, so let's get
+ * rid of it for good.
+ *
+ * - The Atheros SDIO stack with Samuel's driver sets SDIO_CCCR_POWER in
+ * SDIO_POWER_EMPC. Atheros' Linux SDIO code apparently doesn't. We don't
+ * either, and this seems to work fine.
+ * @@@ Need to check this with Atheros.
+ */
+
+
+#define MBOXES 4
+
+#define HIF_MBOX_BLOCK_SIZE 128
+#define HIF_MBOX_BASE_ADDR 0x800
+#define HIF_MBOX_WIDTH 0x800
+#define HIF_MBOX_START_ADDR(mbox) \
+ (HIF_MBOX_BASE_ADDR+(mbox)*HIF_MBOX_WIDTH)
+
+
+struct hif_device {
+ void *htc_handle;
+ struct sdio_func *func;
+
+ /*
+ * @@@ our sweet little bit of bogosity - the mechanism that lets us
+ * use the SDIO stack from softirqs. This really wants to use skbs.
+ */
+ struct list_head queue;
+ spinlock_t queue_lock;
+ struct task_struct *io_task;
+ wait_queue_head_t wait;
+};
+
+struct hif_request {
+ struct list_head list;
+ struct sdio_func *func;
+ int (*read)(struct sdio_func *func,
+ void *dst, unsigned int addr, int count);
+ int (*write)(struct sdio_func *func,
+ unsigned int addr, void *src, int count);
+ void *buf;
+ unsigned long addr;
+ int len;
+ A_STATUS (*completion)(void *context, A_STATUS status);
+ void *context;
+};
+
+
+static HTC_CALLBACKS htcCallbacks;
+
+/*
+ * shutdown_lock prevents recursion through HIFShutDownDevice
+ */
+static DEFINE_MUTEX(shutdown_lock);
+
+
+/* ----- Request processing ------------------------------------------------ */
+
+
+static A_STATUS process_request(struct hif_request *req)
+{
+ int ret;
+ A_STATUS status;
+
+ dev_dbg(&req->func->dev, "process_request(req %p)\n", req);
+ sdio_claim_host(req->func);
+ if (req->read)
+ ret = req->read(req->func, req->buf, req->addr, req->len);
+ else
+ ret = req->write(req->func, req->addr, req->buf, req->len);
+ sdio_release_host(req->func);
+ status = ret ? A_ERROR : A_OK;
+ if (req->completion)
+ req->completion(req->context, status);
+ kfree(req);
+ return status;
+}
+
+
+static void enqueue_request(struct hif_device *hif, struct hif_request *req)
+{
+ unsigned long flags;
+
+ dev_dbg(&req->func->dev, "enqueue_request(req %p)\n", req);
+ spin_lock_irqsave(&hif->queue_lock, flags);
+ list_add_tail(&req->list, &hif->queue);
+ spin_unlock_irqrestore(&hif->queue_lock, flags);
+ wake_up(&hif->wait);
+}
+
+
+static struct hif_request *dequeue_request(struct hif_device *hif)
+{
+ struct hif_request *req;
+ unsigned long flags;
+
+ spin_lock_irqsave(&hif->queue_lock, flags);
+ if (list_empty(&hif->queue))
+ req = NULL;
+ else {
+ req = list_first_entry(&hif->queue,
+ struct hif_request, list);
+ list_del(&req->list);
+ }
+ spin_unlock_irqrestore(&hif->queue_lock, flags);
+ return req;
+}
+
+
+static void wait_queue_empty(struct hif_device *hif)
+{
+ unsigned long flags;
+ int empty;
+
+ while (1) {
+ spin_lock_irqsave(&hif->queue_lock, flags);
+ empty = list_empty(&hif->queue);
+ spin_unlock_irqrestore(&hif->queue_lock, flags);
+ if (empty)
+ break;
+ else
+ yield();
+ }
+}
+
+
+static int io(void *data)
+{
+ struct hif_device *hif = data;
+ struct sched_param param = { .sched_priority = 2 };
+ /* one priority level slower than ksdioirqd (which is at 1) */
+ DEFINE_WAIT(wait);
+ struct hif_request *req;
+
+ sched_setscheduler(current, SCHED_FIFO, &param);
+
+ while (1) {
+ while (1) {
+ /*
+ * Since we never use signals here, one might think
+ * that this ought to be TASK_UNINTERRUPTIBLE. However,
+ * such a task would increase the load average and,
+ * worse, it would trigger the softlockup check.
+ */
+ prepare_to_wait(&hif->wait, &wait, TASK_INTERRUPTIBLE);
+ if (kthread_should_stop()) {
+ finish_wait(&hif->wait, &wait);
+ return 0;
+ }
+ req = dequeue_request(hif);
+ if (req)
+ break;
+ schedule();
+ }
+ finish_wait(&hif->wait, &wait);
+
+ (void) process_request(req);
+ }
+ return 0;
+}
+
+
+A_STATUS HIFReadWrite(HIF_DEVICE *hif, A_UINT32 address, A_UCHAR *buffer,
+ A_UINT32 length, A_UINT32 request, void *context)
+{
+ struct device *dev = HIFGetOSDevice(hif);
+ struct hif_request *req;
+
+ dev_dbg(dev, "HIFReadWrite(device %p, address 0x%x, buffer %p, "
+ "length %d, request 0x%x, context %p)\n",
+ hif, address, buffer, length, request, context);
+
+ BUG_ON(!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)));
+ BUG_ON(!(request & (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)));
+ BUG_ON(!(request & (HIF_READ | HIF_WRITE)));
+ BUG_ON(!(request & HIF_EXTENDED_IO));
+
+ if (address >= HIF_MBOX_START_ADDR(0) &&
+ address < HIF_MBOX_START_ADDR(MBOXES+1)) {
+ BUG_ON(length > HIF_MBOX_WIDTH);
+ /* Adjust the address so that the last byte falls on the EOM
+ address. */
+ address += HIF_MBOX_WIDTH-length;
+ }
+
+ req = kzalloc(sizeof(*req), GFP_ATOMIC);
+ if (!req) {
+ if (request & HIF_ASYNCHRONOUS)
+ htcCallbacks.rwCompletionHandler(context, A_ERROR);
+ return A_ERROR;
+ }
+
+ req->func = hif->func;
+ req->addr = address;
+ req->buf = buffer;
+ req->len = length;
+
+ if (request & HIF_READ) {
+ if (request & HIF_FIXED_ADDRESS)
+ req->read = sdio_readsb;
+ else
+ req->read = sdio_memcpy_fromio;
+ } else {
+ if (request & HIF_FIXED_ADDRESS)
+ req->write = sdio_writesb;
+ else
+ req->write = sdio_memcpy_toio;
+ }
+
+ if (!(request & HIF_ASYNCHRONOUS))
+ return process_request(req);
+
+ req->completion = htcCallbacks.rwCompletionHandler;
+ req->context = context;
+ enqueue_request(hif, req);
+
+ return A_OK;
+}
+
+
+/* ----- Interrupt handling ------------------------------------------------ */
+
+/*
+ * Volatile ought to be good enough to make gcc do the right thing on S3C24xx.
+ * No need to use atomic or put barriers, keeping the code more readable.
+ *
+ * Warning: this story changes if going SMP/SMT.
+ */
+
+static volatile int masked = 1;
+static volatile int pending;
+static volatile int in_interrupt;
+
+
+static void ar6000_do_irq(struct sdio_func *func)
+{
+ HIF_DEVICE *hif = sdio_get_drvdata(func);
+ struct device *dev = HIFGetOSDevice(hif);
+ A_STATUS status;
+
+ dev_dbg(dev, "ar6000_do_irq -> %p\n", htcCallbacks.dsrHandler);
+
+ status = htcCallbacks.dsrHandler(hif->htc_handle);
+ BUG_ON(status != A_OK);
+}
+
+
+static void sdio_ar6000_irq(struct sdio_func *func)
+{
+ HIF_DEVICE *hif = sdio_get_drvdata(func);
+ struct device *dev = HIFGetOSDevice(hif);
+
+ dev_dbg(dev, "sdio_ar6000_irq\n");
+
+ in_interrupt = 1;
+ if (masked) {
+ in_interrupt = 0;
+ pending++;
+ return;
+ }
+ /*
+ * @@@ This is ugly. If we don't drop the lock, we'll deadlock when
+ * the handler tries to do SDIO. So there are four choices:
+ *
+ * 1) Break the call chain by calling the callback from a workqueue.
+ * Ugh.
+ * 2) Make process_request aware that we already have the lock.
+ * 3) Drop the lock. Which is ugly but should be safe as long as we're
+ * making sure the device doesn't go away.
+ * 4) Change the AR6k driver such that it only issues asynchronous
+ * quests when called from an interrupt.
+ *
+ * Solution 2) is probably the best for now. Will try it later.
+ */
+ sdio_release_host(func);
+ ar6000_do_irq(func);
+ sdio_claim_host(func);
+ in_interrupt = 0;
+}
+
+
+void HIFAckInterrupt(HIF_DEVICE *hif)
+{
+ struct device *dev = HIFGetOSDevice(hif);
+
+ dev_dbg(dev, "HIFAckInterrupt\n");
+ /* do nothing */
+}
+
+
+void HIFUnMaskInterrupt(HIF_DEVICE *hif)
+{
+ struct device *dev = HIFGetOSDevice(hif);
+
+ dev_dbg(dev, "HIFUnMaskInterrupt\n");
+ do {
+ masked = 1;
+ if (pending) {
+ pending = 0;
+ ar6000_do_irq(hif->func);
+ /* We may take an interrupt before unmasking and thus
+ get it pending. In this case, we just loop back. */
+ }
+ masked = 0;
+ }
+ while (pending);
+}
+
+
+void HIFMaskInterrupt(HIF_DEVICE *hif)
+{
+ struct device *dev = HIFGetOSDevice(hif);
+
+ dev_dbg(dev, "HIFMaskInterrupt\n");
+ /*
+ * Since sdio_ar6000_irq can also be called from a process context, we
+ * may conceivably end up racing with it. Thus, we need to wait until
+ * we can be sure that no concurrent interrupt processing is going on
+ * before we return.
+ *
+ * Note: this may be a bit on the paranoid side - the callers may
+ * actually be nice enough to disable scheduling. Check later.
+ */
+ masked = 1;
+ while (in_interrupt)
+ yield();
+}
+
+
+/* ----- HIF API glue functions -------------------------------------------- */
+
+
+struct device *HIFGetOSDevice(HIF_DEVICE *hif)
+{
+ return &hif->func->dev;
+}
+
+
+void HIFSetHandle(void *hif_handle, void *handle)
+{
+ HIF_DEVICE *hif = (HIF_DEVICE *) hif_handle;
+
+ hif->htc_handle = handle;
+}
+
+
+/* ----- Device configuration (HIF side) ----------------------------------- */
+
+
+A_STATUS HIFConfigureDevice(HIF_DEVICE *hif,
+ HIF_DEVICE_CONFIG_OPCODE opcode, void *config, A_UINT32 configLen)
+{
+ struct device *dev = HIFGetOSDevice(hif);
+ HIF_DEVICE_IRQ_PROCESSING_MODE *ipm_cfg = config;
+ A_UINT32 *mbs_cfg = config;
+ int i;
+
+ dev_dbg(dev, "HIFConfigureDevice\n");
+
+ switch (opcode) {
+ case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
+ for (i = 0; i != MBOXES; i++)
+ mbs_cfg[i] = HIF_MBOX_BLOCK_SIZE;
+ break;
+ case HIF_DEVICE_GET_MBOX_ADDR:
+ for (i = 0; i != MBOXES; i++)
+ mbs_cfg[i] = HIF_MBOX_START_ADDR(i);
+ break;
+ case HIF_DEVICE_GET_IRQ_PROC_MODE:
+ *ipm_cfg = HIF_DEVICE_IRQ_SYNC_ONLY;
+// *ipm_cfg = HIF_DEVICE_IRQ_ASYNC_SYNC;
+ break;
+ default:
+ return A_ERROR;
+ }
+ return A_OK;
+}
+
+
+/* ----- Device probe and removal (Linux side) ----------------------------- */
+
+
+static int sdio_ar6000_probe(struct sdio_func *func,
+ const struct sdio_device_id *id)
+{
+ struct device *dev = &func->dev;
+ struct hif_device *hif;
+ int ret;
+
+ dev_dbg(dev, "sdio_ar6000_probe\n");
+ BUG_ON(!htcCallbacks.deviceInsertedHandler);
+
+ hif = kzalloc(sizeof(*hif), GFP_KERNEL);
+ if (!hif)
+ return -ENOMEM;
+
+ sdio_set_drvdata(func, hif);
+ sdio_claim_host(func);
+ sdio_enable_func(func);
+
+ hif->func = func;
+ INIT_LIST_HEAD(&hif->queue);
+ init_waitqueue_head(&hif->wait);
+ spin_lock_init(&hif->queue_lock);
+
+ ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
+ if (ret < 0) {
+ dev_err(dev, "sdio_set_block_size returns %d\n", ret);
+ goto out_enabled;
+ }
+ ret = sdio_claim_irq(func, sdio_ar6000_irq);
+ if (ret) {
+ dev_err(dev, "sdio_claim_irq returns %d\n", ret);
+ goto out_enabled;
+ }
+ /* Set SDIO_BUS_CD_DISABLE in SDIO_CCCR_IF ? */
+#if 0
+ sdio_f0_writeb(func, SDIO_CCCR_CAP_E4MI, SDIO_CCCR_CAPS, &ret);
+ if (ret) {
+ dev_err(dev, "sdio_f0_writeb(SDIO_CCCR_CAPS) returns %d\n",
+ ret);
+ goto out_got_irq;
+ }
+#else
+ if (0) /* avoid warning */
+ goto out_got_irq;
+#endif
+
+ sdio_release_host(func);
+
+ hif->io_task = kthread_run(io, hif, "ar6000_io");
+ if (IS_ERR(hif->io_task)) {
+ dev_err(dev, "kthread_run(ar6000_io): %d\n", ret);
+ goto out_func_ready;
+ }
+
+ ret = htcCallbacks.deviceInsertedHandler(hif);
+ if (ret == A_OK)
+ return 0;
+
+ dev_err(dev, "deviceInsertedHandler: %d\n", ret);
+
+ ret = kthread_stop(hif->io_task);
+ if (ret)
+ dev_err(dev, "kthread_stop (ar6000_io): %d\n", ret);
+
+out_func_ready:
+ sdio_claim_host(func);
+
+out_got_irq:
+ sdio_release_irq(func);
+
+out_enabled:
+ sdio_set_drvdata(func, NULL);
+ sdio_disable_func(func);
+ sdio_release_host(func);
+
+ return ret;
+}
+
+
+static void sdio_ar6000_remove(struct sdio_func *func)
+{
+ struct device *dev = &func->dev;
+ HIF_DEVICE *hif = sdio_get_drvdata(func);
+ int ret;
+
+ dev_dbg(dev, "sdio_ar6000_remove\n");
+ if (mutex_trylock(&shutdown_lock)) {
+ /*
+ * Funny, Atheros' HIF does this call, but this just puts us in
+ * a recursion through HTCShutDown/HIFShutDown if unloading the
+ * module.
+ *
+ * However, we need it for suspend/resume. See the comment at
+ * HIFShutDown, below.
+ */
+ ret = htcCallbacks.deviceRemovedHandler(hif->htc_handle, A_OK);
+ if (ret != A_OK)
+ dev_err(dev, "deviceRemovedHandler: %d\n", ret);
+ mutex_unlock(&shutdown_lock);
+ }
+ wait_queue_empty(hif);
+ ret = kthread_stop(hif->io_task);
+ if (ret)
+ dev_err(dev, "kthread_stop (ar6000_io): %d\n", ret);
+ sdio_claim_host(func);
+ sdio_release_irq(func);
+ sdio_set_drvdata(func, NULL);
+ sdio_disable_func(func);
+ sdio_release_host(func);
+ kfree(hif);
+}
+
+
+/* ----- Device registration/unregistration (called by HIF) ---------------- */
+
+
+#define ATHEROS_SDIO_DEVICE(id, offset) \
+ SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_##id | (offset))
+
+static const struct sdio_device_id sdio_ar6000_ids[] = {
+ { ATHEROS_SDIO_DEVICE(AR6000, 0) },
+ { ATHEROS_SDIO_DEVICE(AR6000, 0x1) },
+ { ATHEROS_SDIO_DEVICE(AR6000, 0x8) },
+ { ATHEROS_SDIO_DEVICE(AR6000, 0x9) },
+ { ATHEROS_SDIO_DEVICE(AR6000, 0xa) },
+ { ATHEROS_SDIO_DEVICE(AR6000, 0xb) },
+ { /* end: all zeroes */ },
+};
+
+MODULE_DEVICE_TABLE(sdio, sdio_ar6000_ids);
+
+
+static struct sdio_driver sdio_ar6000_driver = {
+ .probe = sdio_ar6000_probe,
+ .remove = sdio_ar6000_remove,
+ .name = "sdio_ar6000",
+ .id_table = sdio_ar6000_ids,
+};
+
+
+int HIFInit(HTC_CALLBACKS *callbacks)
+{
+ int ret;
+
+ BUG_ON(!callbacks);
+
+ printk(KERN_DEBUG "HIFInit\n");
+ htcCallbacks = *callbacks;
+
+ ret = sdio_register_driver(&sdio_ar6000_driver);
+ if (ret) {
+ printk(KERN_ERR
+ "sdio_register_driver(sdio_ar6000_driver): %d\n", ret);
+ return A_ERROR;
+ }
+
+ return 0;
+}
+
+
+/*
+ * We have three possible call chains here:
+ *
+ * System shutdown/reboot:
+ *
+ * kernel_restart_prepare ...> device_shutdown ... > s3cmci_shutdown ->
+ * mmc_remove_host ..> sdio_bus_remove -> sdio_ar6000_remove ->
+ * deviceRemovedHandler (HTCTargetRemovedHandler) -> HIFShutDownDevice
+ *
+ * This is roughly the same sequence as suspend, described below.
+ *
+ * Module removal:
+ *
+ * sys_delete_module -> ar6000_cleanup_module -> HTCShutDown ->
+ * HIFShutDownDevice -> sdio_unregister_driver ...> sdio_bus_remove ->
+ * sdio_ar6000_remove
+ *
+ * In this case, HIFShutDownDevice must call sdio_unregister_driver to
+ * notify the driver about its removal. sdio_ar6000_remove must not call
+ * deviceRemovedHandler, because that would loop back into HIFShutDownDevice.
+ *
+ * Suspend:
+ *
+ * device_suspend ...> s3cmci_suspend ...> sdio_bus_remove ->
+ * sdio_ar6000_remove -> deviceRemovedHandler (HTCTargetRemovedHandler) ->
+ * HIFShutDownDevice
+ *
+ * We must call deviceRemovedHandler to inform the ar6k stack that the device
+ * has been removed. Since HTCTargetRemovedHandler calls back into
+ * HIFShutDownDevice, we must also prevent the call to
+ * sdio_unregister_driver, or we'd end up recursing into the SDIO stack,
+ * eventually deadlocking somewhere.
+ */
+
+void HIFShutDownDevice(HIF_DEVICE *hif)
+{
+ /* Beware, HTCShutDown calls us with hif == NULL ! */
+ if (mutex_trylock(&shutdown_lock)) {
+ sdio_unregister_driver(&sdio_ar6000_driver);
+ mutex_unlock(&shutdown_lock);
+ }
+}
--- /dev/null
+++ b/drivers/ar6000/hif/hif.c
@@ -0,0 +1,824 @@
+/*
+ * @file: hif.c
+ *
+ * @abstract: HIF layer reference implementation for Atheros SDIO stack
+ *
+ * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "hif_internal.h"
+
+/* ------ Static Variables ------ */
+
+/* ------ Global Variable Declarations ------- */
+SD_PNP_INFO Ids[] = {
+ {
+ .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0xB,
+ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
+ .SDIO_FunctionClass = FUNCTION_CLASS,
+ .SDIO_FunctionNo = 1
+ },
+ {
+ .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0xA,
+ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
+ .SDIO_FunctionClass = FUNCTION_CLASS,
+ .SDIO_FunctionNo = 1
+ },
+ {
+ .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0x9,
+ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
+ .SDIO_FunctionClass = FUNCTION_CLASS,
+ .SDIO_FunctionNo = 1
+ },
+ {
+ .SDIO_ManufacturerID = MANUFACTURER_ID_AR6001_BASE | 0x8,
+ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
+ .SDIO_FunctionClass = FUNCTION_CLASS,
+ .SDIO_FunctionNo = 1
+ },
+ {
+ .SDIO_ManufacturerID = MANUFACTURER_ID_AR6002_BASE | 0x0,
+ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
+ .SDIO_FunctionClass = FUNCTION_CLASS,
+ .SDIO_FunctionNo = 1
+ },
+ {
+ .SDIO_ManufacturerID = MANUFACTURER_ID_AR6002_BASE | 0x1,
+ .SDIO_ManufacturerCode = MANUFACTURER_CODE,
+ .SDIO_FunctionClass = FUNCTION_CLASS,
+ .SDIO_FunctionNo = 1
+ },
+ {
+ } //list is null termintaed
+};
+
+TARGET_FUNCTION_CONTEXT FunctionContext = {
+ .function.Version = CT_SDIO_STACK_VERSION_CODE,
+ .function.pName = "sdio_wlan",
+ .function.MaxDevices = 1,
+ .function.NumDevices = 0,
+ .function.pIds = Ids,
+ .function.pProbe = hifDeviceInserted,
+ .function.pRemove = hifDeviceRemoved,
+ .function.pSuspend = NULL,
+ .function.pResume = NULL,
+ .function.pWake = NULL,
+ .function.pContext = &FunctionContext,
+};
+
+HIF_DEVICE hifDevice[HIF_MAX_DEVICES];
+HTC_CALLBACKS htcCallbacks;
+BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM];
+static BUS_REQUEST *s_busRequestFreeQueue = NULL;
+OS_CRITICALSECTION lock;
+extern A_UINT32 onebitmode;
+extern A_UINT32 busspeedlow;
+
+#ifdef DEBUG
+extern A_UINT32 debughif;
+#define ATH_DEBUG_ERROR 1
+#define ATH_DEBUG_WARN 2
+#define ATH_DEBUG_TRACE 3
+#define _AR_DEBUG_PRINTX_ARG(arg...) arg
+#define AR_DEBUG_PRINTF(lvl, args)\
+ {if (lvl <= debughif)\
+ A_PRINTF(KERN_ALERT _AR_DEBUG_PRINTX_ARG args);\
+ }
+#else
+#define AR_DEBUG_PRINTF(lvl, args)
+#endif
+
+static BUS_REQUEST *hifAllocateBusRequest(void);
+static void hifFreeBusRequest(BUS_REQUEST *busrequest);
+static THREAD_RETURN insert_helper_func(POSKERNEL_HELPER pHelper);
+static void ResetAllCards(void);
+
+/* ------ Functions ------ */
+int HIFInit(HTC_CALLBACKS *callbacks)
+{
+ SDIO_STATUS status;
+ DBG_ASSERT(callbacks != NULL);
+
+ /* Store the callback and event handlers */
+ htcCallbacks.deviceInsertedHandler = callbacks->deviceInsertedHandler;
+ htcCallbacks.deviceRemovedHandler = callbacks->deviceRemovedHandler;
+ htcCallbacks.deviceSuspendHandler = callbacks->deviceSuspendHandler;
+ htcCallbacks.deviceResumeHandler = callbacks->deviceResumeHandler;
+ htcCallbacks.deviceWakeupHandler = callbacks->deviceWakeupHandler;
+ htcCallbacks.rwCompletionHandler = callbacks->rwCompletionHandler;
+ htcCallbacks.dsrHandler = callbacks->dsrHandler;
+
+ CriticalSectionInit(&lock);
+
+ /* Register with bus driver core */
+ status = SDIO_RegisterFunction(&FunctionContext.function);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+
+ return(0);
+}
+
+A_STATUS
+HIFReadWrite(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_UINT32 request,
+ void *context)
+{
+ A_UINT8 rw;
+ A_UINT8 mode;
+ A_UINT8 funcNo;
+ A_UINT8 opcode;
+ A_UINT16 count;
+ SDREQUEST *sdrequest;
+ SDIO_STATUS sdiostatus;
+ BUS_REQUEST *busrequest;
+ A_STATUS status = A_OK;
+
+ DBG_ASSERT(device != NULL);
+ DBG_ASSERT(device->handle != NULL);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
+
+ do {
+ busrequest = hifAllocateBusRequest();
+ if (busrequest == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF Unable to allocate bus request\n"));
+ status = A_NO_RESOURCE;
+ break;
+ }
+
+ sdrequest = busrequest->request;
+ busrequest->context = context;
+
+ sdrequest->pDataBuffer = buffer;
+ if (request & HIF_SYNCHRONOUS) {
+ sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS;
+ sdrequest->pCompleteContext = NULL;
+ sdrequest->pCompletion = NULL;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Synchronous\n"));
+ } else if (request & HIF_ASYNCHRONOUS) {
+ sdrequest->Flags = SDREQ_FLAGS_RESP_SDIO_R5 | SDREQ_FLAGS_DATA_TRANS |
+ SDREQ_FLAGS_TRANS_ASYNC;
+ sdrequest->pCompleteContext = busrequest;
+ sdrequest->pCompletion = hifRWCompletionHandler;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Execution mode: Asynchronous\n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Invalid execution mode: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ if (request & HIF_EXTENDED_IO) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Command type: CMD53\n"));
+ sdrequest->Command = CMD53;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Invalid command type: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ if (request & HIF_BLOCK_BASIS) {
+ mode = CMD53_BLOCK_BASIS;
+ sdrequest->BlockLen = HIF_MBOX_BLOCK_SIZE;
+ sdrequest->BlockCount = length / HIF_MBOX_BLOCK_SIZE;
+ count = sdrequest->BlockCount;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Block mode (BlockLen: %d, BlockCount: %d)\n",
+ sdrequest->BlockLen, sdrequest->BlockCount));
+ } else if (request & HIF_BYTE_BASIS) {
+ mode = CMD53_BYTE_BASIS;
+ sdrequest->BlockLen = length;
+ sdrequest->BlockCount = 1;
+ count = sdrequest->BlockLen;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Byte mode (BlockLen: %d, BlockCount: %d)\n",
+ sdrequest->BlockLen, sdrequest->BlockCount));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Invalid data mode: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+#if 0
+ /* useful for checking register accesses */
+ if (length & 0x3) {
+ A_PRINTF(KERN_ALERT"HIF (%s) is not a multiple of 4 bytes, addr:0x%X, len:%d\n",
+ request & HIF_WRITE ? "write":"read", address, length);
+ }
+#endif
+
+ if ((address >= HIF_MBOX_START_ADDR(0)) &&
+ (address <= HIF_MBOX_END_ADDR(3)))
+ {
+
+ DBG_ASSERT(length <= HIF_MBOX_WIDTH);
+
+ /*
+ * Mailbox write. Adjust the address so that the last byte
+ * falls on the EOM address.
+ */
+ address += (HIF_MBOX_WIDTH - length);
+ }
+
+
+
+ if (request & HIF_WRITE) {
+ rw = CMD53_WRITE;
+ sdrequest->Flags |= SDREQ_FLAGS_DATA_WRITE;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Write\n"));
+ } else if (request & HIF_READ) {
+ rw = CMD53_READ;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Direction: Read\n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Invalid direction: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ if (request & HIF_FIXED_ADDRESS) {
+ opcode = CMD53_FIXED_ADDRESS;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Fixed\n"));
+ } else if (request & HIF_INCREMENTAL_ADDRESS) {
+ opcode = CMD53_INCR_ADDRESS;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Address mode: Incremental\n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Invalid address mode: 0x%08x\n", request));
+ status = A_EINVAL;
+ break;
+ }
+
+ funcNo = SDDEVICE_GET_SDIO_FUNCNO(device->handle);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Function number: %d\n", funcNo));
+ SDIO_SET_CMD53_ARG(sdrequest->Argument, rw, funcNo,
+ mode, opcode, address, count);
+
+ /* Send the command out */
+ sdiostatus = SDDEVICE_CALL_REQUEST_FUNC(device->handle, sdrequest);
+
+ if (!SDIO_SUCCESS(sdiostatus)) {
+ status = A_ERROR;
+ }
+
+ } while (FALSE);
+
+ if (A_FAILED(status) || (request & HIF_SYNCHRONOUS)) {
+ if (busrequest != NULL) {
+ hifFreeBusRequest(busrequest);
+ }
+ }
+
+ if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
+ /* call back async handler on failure */
+ htcCallbacks.rwCompletionHandler(context, status);
+ }
+
+ return status;
+}
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+ void *config, A_UINT32 configLen)
+{
+ A_UINT32 count;
+
+ switch(opcode) {
+ case HIF_DEVICE_GET_MBOX_BLOCK_SIZE:
+ ((A_UINT32 *)config)[0] = HIF_MBOX0_BLOCK_SIZE;
+ ((A_UINT32 *)config)[1] = HIF_MBOX1_BLOCK_SIZE;
+ ((A_UINT32 *)config)[2] = HIF_MBOX2_BLOCK_SIZE;
+ ((A_UINT32 *)config)[3] = HIF_MBOX3_BLOCK_SIZE;
+ break;
+
+ case HIF_DEVICE_GET_MBOX_ADDR:
+ for (count = 0; count < 4; count ++) {
+ ((A_UINT32 *)config)[count] = HIF_MBOX_START_ADDR(count);
+ }
+ break;
+ case HIF_DEVICE_GET_IRQ_PROC_MODE:
+ /* the SDIO stack allows the interrupts to be processed either way, ASYNC or SYNC */
+ *((HIF_DEVICE_IRQ_PROCESSING_MODE *)config) = HIF_DEVICE_IRQ_ASYNC_SYNC;
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ ("Unsupported configuration opcode: %d\n", opcode));
+ return A_ERROR;
+ }
+
+ return A_OK;
+}
+
+void
+HIFShutDownDevice(HIF_DEVICE *device)
+{
+ A_UINT8 data;
+ A_UINT32 count;
+ SDIO_STATUS status;
+ SDCONFIG_BUS_MODE_DATA busSettings;
+ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
+
+ if (device != NULL) {
+ DBG_ASSERT(device->handle != NULL);
+
+ /* Remove the allocated current if any */
+ status = SDLIB_IssueConfig(device->handle,
+ SDCONFIG_FUNC_FREE_SLOT_CURRENT, NULL, 0);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+
+ /* Disable the card */
+ fData.EnableFlags = SDCONFIG_DISABLE_FUNC;
+ fData.TimeOut = 1;
+ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ENABLE_DISABLE,
+ &fData, sizeof(fData));
+ DBG_ASSERT(SDIO_SUCCESS(status));
+
+ /* Perform a soft I/O reset */
+ data = SDIO_IO_RESET;
+ status = SDLIB_IssueCMD52(device->handle, 0, SDIO_IO_ABORT_REG,
+ &data, 1, 1);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+
+ /*
+ * WAR - Codetelligence driver does not seem to shutdown correctly in 1
+ * bit mode. By default it configures the HC in the 4 bit. Its later in
+ * our driver that we switch to 1 bit mode. If we try to shutdown, the
+ * driver hangs so we revert to 4 bit mode, to be transparent to the
+ * underlying bus driver.
+ */
+ if (onebitmode) {
+ ZERO_OBJECT(busSettings);
+ busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(device->handle);
+ SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
+ SDCONFIG_BUS_WIDTH_4_BIT);
+
+ /* Issue config request to change the bus width to 4 bit */
+ status = SDLIB_IssueConfig(device->handle, SDCONFIG_BUS_MODE_CTRL,
+ &busSettings,
+ sizeof(SDCONFIG_BUS_MODE_DATA));
+ DBG_ASSERT(SDIO_SUCCESS(status));
+ }
+
+ /* Free the bus requests */
+ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
+ SDDeviceFreeRequest(device->handle, busRequest[count].request);
+ }
+ /* Clean up the queue */
+ s_busRequestFreeQueue = NULL;
+ } else {
+ /* since we are unloading the driver anyways, reset all cards in case the SDIO card
+ * is externally powered and we are unloading the SDIO stack. This avoids the problem when
+ * the SDIO stack is reloaded and attempts are made to re-enumerate a card that is already
+ * enumerated */
+ ResetAllCards();
+ /* Unregister with bus driver core */
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Unregistering with the bus driver\n"));
+ status = SDIO_UnregisterFunction(&FunctionContext.function);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+ }
+}
+
+void
+hifRWCompletionHandler(SDREQUEST *request)
+{
+ A_STATUS status;
+ void *context;
+ BUS_REQUEST *busrequest;
+
+ if (SDIO_SUCCESS(request->Status)) {
+ status = A_OK;
+ } else {
+ status = A_ERROR;
+ }
+
+ DBG_ASSERT(status == A_OK);
+ busrequest = (BUS_REQUEST *) request->pCompleteContext;
+ context = (void *) busrequest->context;
+ /* free the request before calling the callback, in case the
+ * callback submits another request, this guarantees that
+ * there is at least 1 free request available everytime the callback
+ * is invoked */
+ hifFreeBusRequest(busrequest);
+ htcCallbacks.rwCompletionHandler(context, status);
+}
+
+void
+hifIRQHandler(void *context)
+{
+ A_STATUS status;
+ HIF_DEVICE *device;
+
+ device = (HIF_DEVICE *)context;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
+ status = htcCallbacks.dsrHandler(device->htc_handle);
+ DBG_ASSERT(status == A_OK);
+}
+
+BOOL
+hifDeviceInserted(SDFUNCTION *function, SDDEVICE *handle)
+{
+ BOOL enabled;
+ A_UINT8 data;
+ A_UINT32 count;
+ HIF_DEVICE *device;
+ SDIO_STATUS status;
+ A_UINT16 maxBlocks;
+ A_UINT16 maxBlockSize;
+ SDCONFIG_BUS_MODE_DATA busSettings;
+ SDCONFIG_FUNC_ENABLE_DISABLE_DATA fData;
+ TARGET_FUNCTION_CONTEXT *functionContext;
+ SDCONFIG_FUNC_SLOT_CURRENT_DATA slotCurrent;
+ SD_BUSCLOCK_RATE currentBusClock;
+
+ DBG_ASSERT(function != NULL);
+ DBG_ASSERT(handle != NULL);
+
+ device = addHifDevice(handle);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device: %p\n", device));
+ functionContext = (TARGET_FUNCTION_CONTEXT *)function->pContext;
+
+ /*
+ * Issue commands to get the manufacturer ID and stuff and compare it
+ * against the rev Id derived from the ID registered during the
+ * initialization process. Report the device only in the case there
+ * is a match. In the case od SDIO, the bus driver has already queried
+ * these details so we just need to use their data structures to get the
+ * relevant values. Infact, the driver has already matched it against
+ * the Ids that we registered with it so we dont need to the step here.
+ */
+
+ /* Configure the SDIO Bus Width */
+ if (onebitmode) {
+ data = SDIO_BUS_WIDTH_1_BIT;
+ status = SDLIB_IssueCMD52(handle, 0, SDIO_BUS_IF_REG, &data, 1, 1);
+ if (!SDIO_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Unable to set the bus width to 1 bit\n"));
+ return FALSE;
+ }
+ }
+
+ /* Get current bus flags */
+ ZERO_OBJECT(busSettings);
+
+ busSettings.BusModeFlags = SDDEVICE_GET_BUSMODE_FLAGS(handle);
+ if (onebitmode) {
+ SDCONFIG_SET_BUS_WIDTH(busSettings.BusModeFlags,
+ SDCONFIG_BUS_WIDTH_1_BIT);
+ }
+
+ /* get the current operating clock, the bus driver sets us up based
+ * on what our CIS reports and what the host controller can handle
+ * we can use this to determine whether we want to drop our clock rate
+ * down */
+ currentBusClock = SDDEVICE_GET_OPER_CLOCK(handle);
+ busSettings.ClockRate = currentBusClock;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("HIF currently running at: %d \n",currentBusClock));
+
+ /* see if HIF wants to run at a lower clock speed, we may already be
+ * at that lower clock speed */
+ if (currentBusClock > (SDIO_CLOCK_FREQUENCY_DEFAULT >> busspeedlow)) {
+ busSettings.ClockRate = SDIO_CLOCK_FREQUENCY_DEFAULT >> busspeedlow;
+ AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
+ ("HIF overriding clock to %d \n",busSettings.ClockRate));
+ }
+
+ /* Issue config request to override clock rate */
+ status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_CHANGE_BUS_MODE, &busSettings,
+ sizeof(SDCONFIG_BUS_MODE_DATA));
+ if (!SDIO_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Unable to configure the host clock\n"));
+ return FALSE;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Configured clock: %d, Maximum clock: %d\n",
+ busSettings.ActualClockRate,
+ SDDEVICE_GET_MAX_CLOCK(handle)));
+ }
+
+ /*
+ * Check if the target supports block mode. This result of this check
+ * can be used to implement the HIFReadWrite API.
+ */
+ if (SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle)) {
+ /* Limit block size to operational block limit or card function
+ capability */
+ maxBlockSize = min(SDDEVICE_GET_OPER_BLOCK_LEN(handle),
+ SDDEVICE_GET_SDIO_FUNC_MAXBLKSIZE(handle));
+
+ /* check if the card support multi-block transfers */
+ if (!(SDDEVICE_GET_SDIOCARD_CAPS(handle) & SDIO_CAPS_MULTI_BLOCK)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Byte basis only\n"));
+
+ /* Limit block size to max byte basis */
+ maxBlockSize = min(maxBlockSize,
+ (A_UINT16)SDIO_MAX_LENGTH_BYTE_BASIS);
+ maxBlocks = 1;
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Multi-block capable\n"));
+ maxBlocks = SDDEVICE_GET_OPER_BLOCKS(handle);
+ status = SDLIB_SetFunctionBlockSize(handle, HIF_MBOX_BLOCK_SIZE);
+ if (!SDIO_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Failed to set block size. Err:%d\n", status));
+ return FALSE;
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Bytes Per Block: %d bytes, Block Count:%d \n",
+ maxBlockSize, maxBlocks));
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Function does not support Block Mode!\n"));
+ return FALSE;
+ }
+
+ /* Allocate the slot current */
+ status = SDLIB_GetDefaultOpCurrent(handle, &slotCurrent.SlotCurrent);
+ if (SDIO_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Allocating Slot current: %d mA\n",
+ slotCurrent.SlotCurrent));
+ status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ALLOC_SLOT_CURRENT,
+ &slotCurrent, sizeof(slotCurrent));
+ if (!SDIO_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Failed to allocate slot current %d\n", status));
+ return FALSE;
+ }
+ }
+
+ /* Enable the dragon function */
+ count = 0;
+ enabled = FALSE;
+ fData.TimeOut = 1;
+ fData.EnableFlags = SDCONFIG_ENABLE_FUNC;
+ while ((count++ < SDWLAN_ENABLE_DISABLE_TIMEOUT) && !enabled)
+ {
+ /* Enable dragon */
+ status = SDLIB_IssueConfig(handle, SDCONFIG_FUNC_ENABLE_DISABLE,
+ &fData, sizeof(fData));
+ if (!SDIO_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Attempting to enable the card again\n"));
+ continue;
+ }
+
+ /* Mark the status as enabled */
+ enabled = TRUE;
+ }
+
+ /* Check if we were succesful in enabling the target */
+ if (!enabled) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
+ ("Failed to communicate with the target\n"));
+ return FALSE;
+ }
+
+ /* Allocate the bus requests to be used later */
+ A_MEMZERO(busRequest, sizeof(busRequest));
+ for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
+ if ((busRequest[count].request = SDDeviceAllocRequest(handle)) == NULL){
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("Unable to allocate memory\n"));
+ /* TODO: Free the memory that has already been allocated */
+ return FALSE;
+ }
+ hifFreeBusRequest(&busRequest[count]);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("0x%08x = busRequest[%d].request = 0x%08x\n",
+ (unsigned int) &busRequest[count], count,
+ (unsigned int) busRequest[count].request));
+ }
+
+ /* Schedule a worker to handle device inserted, this is a temporary workaround
+ * to fix a deadlock if the device fails to intialize in the insertion handler
+ * The failure causes the instance to shutdown the HIF layer and unregister the
+ * function driver within the busdriver probe context which can deadlock
+ *
+ * NOTE: we cannot use the default work queue because that would block
+ * SD bus request processing for all synchronous I/O. We must use a kernel
+ * thread that is creating using the helper library.
+ * */
+
+ if (SDIO_SUCCESS(SDLIB_OSCreateHelper(&device->insert_helper,
+ insert_helper_func,
+ device))) {
+ device->helper_started = TRUE;
+ }
+
+ return TRUE;
+}
+
+static THREAD_RETURN insert_helper_func(POSKERNEL_HELPER pHelper)
+{
+
+ /*
+ * Adding a wait of around a second before we issue the very first
+ * command to dragon. During the process of loading/unloading the
+ * driver repeatedly it was observed that we get a data timeout
+ * while accessing function 1 registers in the chip. The theory at
+ * this point is that some initialization delay in dragon is
+ * causing the SDIO state in dragon core to be not ready even after
+ * the ready bit indicates that function 1 is ready. Accomodating
+ * for this behavior by adding some delay in the driver before it
+ * issues the first command after switching on dragon. Need to
+ * investigate this a bit more - TODO
+ */
+
+ A_MDELAY(1000);
+ /* Inform HTC */
+ if ((htcCallbacks.deviceInsertedHandler(SD_GET_OS_HELPER_CONTEXT(pHelper))) != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("Device rejected\n"));
+ }
+
+ return 0;
+}
+
+void
+HIFAckInterrupt(HIF_DEVICE *device)
+{
+ SDIO_STATUS status;
+ DBG_ASSERT(device != NULL);
+ DBG_ASSERT(device->handle != NULL);
+
+ /* Acknowledge our function IRQ */
+ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_ACK_IRQ,
+ NULL, 0);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+}
+
+void
+HIFUnMaskInterrupt(HIF_DEVICE *device)
+{
+ SDIO_STATUS status;
+
+ DBG_ASSERT(device != NULL);
+ DBG_ASSERT(device->handle != NULL);
+
+ /* Register the IRQ Handler */
+ SDDEVICE_SET_IRQ_HANDLER(device->handle, hifIRQHandler, device);
+
+ /* Unmask our function IRQ */
+ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_UNMASK_IRQ,
+ NULL, 0);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+}
+
+void HIFMaskInterrupt(HIF_DEVICE *device)
+{
+ SDIO_STATUS status;
+ DBG_ASSERT(device != NULL);
+ DBG_ASSERT(device->handle != NULL);
+
+ /* Mask our function IRQ */
+ status = SDLIB_IssueConfig(device->handle, SDCONFIG_FUNC_MASK_IRQ,
+ NULL, 0);
+ DBG_ASSERT(SDIO_SUCCESS(status));
+
+ /* Unregister the IRQ Handler */
+ SDDEVICE_SET_IRQ_HANDLER(device->handle, NULL, NULL);
+}
+
+static BUS_REQUEST *hifAllocateBusRequest(void)
+{
+ BUS_REQUEST *busrequest;
+
+ /* Acquire lock */
+ CriticalSectionAcquire(&lock);
+
+ /* Remove first in list */
+ if((busrequest = s_busRequestFreeQueue) != NULL)
+ {
+ s_busRequestFreeQueue = busrequest->next;
+ }
+
+ /* Release lock */
+ CriticalSectionRelease(&lock);
+
+ return busrequest;
+}
+
+static void
+hifFreeBusRequest(BUS_REQUEST *busrequest)
+{
+ DBG_ASSERT(busrequest != NULL);
+
+ /* Acquire lock */
+ CriticalSectionAcquire(&lock);
+
+ /* Insert first in list */
+ busrequest->next = s_busRequestFreeQueue;
+ s_busRequestFreeQueue = busrequest;
+
+ /* Release lock */
+ CriticalSectionRelease(&lock);
+}
+
+void
+hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *handle)
+{
+ A_STATUS status;
+ HIF_DEVICE *device;
+ DBG_ASSERT(function != NULL);
+ DBG_ASSERT(handle != NULL);
+
+ device = getHifDevice(handle);
+ status = htcCallbacks.deviceRemovedHandler(device->htc_handle, A_OK);
+
+ /* cleanup the helper thread */
+ if (device->helper_started) {
+ SDLIB_OSDeleteHelper(&device->insert_helper);
+ device->helper_started = FALSE;
+ }
+
+ delHifDevice(handle);
+ DBG_ASSERT(status == A_OK);
+}
+
+HIF_DEVICE *
+addHifDevice(SDDEVICE *handle)
+{
+ DBG_ASSERT(handle != NULL);
+ hifDevice[0].handle = handle;
+ return &hifDevice[0];
+}
+
+HIF_DEVICE *
+getHifDevice(SDDEVICE *handle)
+{
+ DBG_ASSERT(handle != NULL);
+ return &hifDevice[0];
+}
+
+void
+delHifDevice(SDDEVICE *handle)
+{
+ DBG_ASSERT(handle != NULL);
+ hifDevice[0].handle = NULL;
+}
+
+struct device*
+HIFGetOSDevice(HIF_DEVICE *device)
+{
+ return &device->handle->Device->dev;
+}
+
+static void ResetAllCards(void)
+{
+ UINT8 data;
+ SDIO_STATUS status;
+ int i;
+
+ data = SDIO_IO_RESET;
+
+ /* set the I/O CARD reset bit:
+ * NOTE: we are exploiting a "feature" of the SDIO core that resets the core when you
+ * set the RES bit in the SDIO_IO_ABORT register. This bit however "normally" resets the
+ * I/O functions leaving the SDIO core in the same state (as per SDIO spec).
+ * In this design, this reset can be used to reset the SDIO core itself */
+ for (i = 0; i < HIF_MAX_DEVICES; i++) {
+ if (hifDevice[i].handle != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("Issuing I/O Card reset for instance: %d \n",i));
+ /* set the I/O Card reset bit */
+ status = SDLIB_IssueCMD52(hifDevice[i].handle,
+ 0, /* function 0 space */
+ SDIO_IO_ABORT_REG,
+ &data,
+ 1, /* 1 byte */
+ TRUE); /* write */
+ }
+ }
+
+}
+
+void HIFSetHandle(void *hif_handle, void *handle)
+{
+ HIF_DEVICE *device = (HIF_DEVICE *) hif_handle;
+
+ device->htc_handle = handle;
+
+ return;
+}
--- /dev/null
+++ b/drivers/ar6000/hif/hif_internal.h
@@ -0,0 +1,102 @@
+/*
+ * @file: hif_internal.h
+ *
+ * @abstract: internal header file for hif layer
+ *
+ * @notice: Copyright (c) 2004-2006 Atheros Communications Inc.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include <linux/sdio/ctsystem.h>
+#include <linux/sdio/sdio_busdriver.h>
+#include <linux/sdio/_sdio_defs.h>
+#include <linux/sdio/sdio_lib.h>
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "hif.h"
+
+#define MANUFACTURER_ID_AR6001_BASE 0x100
+#define MANUFACTURER_ID_AR6002_BASE 0x200
+#define FUNCTION_CLASS 0x0
+#define MANUFACTURER_CODE 0x271
+
+#define BUS_REQUEST_MAX_NUM 64
+
+#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000
+#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
+#define FLAGS_CARD_ENAB 0x02
+#define FLAGS_CARD_IRQ_UNMSK 0x04
+
+#define HIF_MBOX_BLOCK_SIZE 128
+#define HIF_MBOX_BASE_ADDR 0x800
+#define HIF_MBOX_WIDTH 0x800
+#define HIF_MBOX0_BLOCK_SIZE 1
+#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
+#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
+
+#define HIF_MBOX_START_ADDR(mbox) \
+ HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH
+
+#define HIF_MBOX_END_ADDR(mbox) \
+ HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1
+
+struct hif_device {
+ SDDEVICE *handle;
+ void *htc_handle;
+ OSKERNEL_HELPER insert_helper;
+ BOOL helper_started;
+};
+
+typedef struct target_function_context {
+ SDFUNCTION function; /* function description of the bus driver */
+ OS_SEMAPHORE instanceSem; /* instance lock. Unused */
+ SDLIST instanceList; /* list of instances. Unused */
+} TARGET_FUNCTION_CONTEXT;
+
+typedef struct bus_request {
+ struct bus_request *next;
+ SDREQUEST *request;
+ void *context;
+} BUS_REQUEST;
+
+BOOL
+hifDeviceInserted(SDFUNCTION *function, SDDEVICE *device);
+
+void
+hifDeviceRemoved(SDFUNCTION *function, SDDEVICE *device);
+
+SDREQUEST *
+hifAllocateDeviceRequest(SDDEVICE *device);
+
+void
+hifFreeDeviceRequest(SDREQUEST *request);
+
+void
+hifRWCompletionHandler(SDREQUEST *request);
+
+void
+hifIRQHandler(void *context);
+
+HIF_DEVICE *
+addHifDevice(SDDEVICE *handle);
+
+HIF_DEVICE *
+getHifDevice(SDDEVICE *handle);
+
+void
+delHifDevice(SDDEVICE *handle);
--- /dev/null
+++ b/drivers/ar6000/htc/ar6k.c
@@ -0,0 +1,991 @@
+/*
+ * AR6K device layer that handles register level I/O
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6Khwreg.h"
+#include "a_osapi.h"
+#include "a_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+#define MAILBOX_FOR_BLOCK_SIZE 1
+
+extern A_UINT32 resetok;
+
+static A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
+static A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
+
+#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
+#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
+
+void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket)
+{
+ LOCK_AR6K(pDev);
+ HTC_PACKET_ENQUEUE(&pDev->RegisterIOList,pPacket);
+ UNLOCK_AR6K(pDev);
+}
+
+HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev)
+{
+ HTC_PACKET *pPacket;
+
+ LOCK_AR6K(pDev);
+ pPacket = HTC_PACKET_DEQUEUE(&pDev->RegisterIOList);
+ UNLOCK_AR6K(pDev);
+
+ return pPacket;
+}
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev)
+{
+ A_UINT32 mailboxaddrs[AR6K_MAILBOXES];
+ A_UINT32 blocksizes[AR6K_MAILBOXES];
+ A_STATUS status = A_OK;
+ int i;
+
+ AR_DEBUG_ASSERT(AR6K_IRQ_PROC_REGS_SIZE == 16);
+ AR_DEBUG_ASSERT(AR6K_IRQ_ENABLE_REGS_SIZE == 4);
+
+ do {
+ /* give a handle to HIF for this target */
+ HIFSetHandle(pDev->HIFDevice, (void *)pDev);
+ /* initialize our free list of IO packets */
+ INIT_HTC_PACKET_QUEUE(&pDev->RegisterIOList);
+ A_MUTEX_INIT(&pDev->Lock);
+
+ /* get the addresses for all 4 mailboxes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+ mailboxaddrs, sizeof(mailboxaddrs));
+
+ if (status != A_OK) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* carve up register I/O packets (these are for ASYNC register I/O ) */
+ for (i = 0; i < AR6K_MAX_REG_IO_BUFFERS; i++) {
+ HTC_PACKET *pIOPacket;
+ pIOPacket = &pDev->RegIOBuffers[i].HtcPacket;
+ SET_HTC_PACKET_INFO_RX_REFILL(pIOPacket,
+ pDev,
+ pDev->RegIOBuffers[i].Buffer,
+ AR6K_REG_IO_BUFFER_SIZE,
+ 0); /* don't care */
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ /* get the address of the mailbox we are using */
+ pDev->MailboxAddress = mailboxaddrs[HTC_MAILBOX];
+
+ /* get the block sizes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ blocksizes, sizeof(blocksizes));
+
+ if (status != A_OK) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* note: we actually get the block size of a mailbox other than 0, for SDIO the block
+ * size on mailbox 0 is artificially set to 1. So we use the block size that is set
+ * for the other 3 mailboxes */
+ pDev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
+ /* must be a power of 2 */
+ AR_DEBUG_ASSERT((pDev->BlockSize & (pDev->BlockSize - 1)) == 0);
+
+ /* assemble mask, used for padding to a block */
+ pDev->BlockMask = pDev->BlockSize - 1;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("BlockSize: %d, MailboxAddress:0x%X \n",
+ pDev->BlockSize, pDev->MailboxAddress));
+
+ pDev->GetPendingEventsFunc = NULL;
+ /* see if the HIF layer implements the get pending events function */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+ &pDev->GetPendingEventsFunc,
+ sizeof(pDev->GetPendingEventsFunc));
+
+ /* assume we can process HIF interrupt events asynchronously */
+ pDev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
+
+ /* see if the HIF layer overrides this assumption */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_IRQ_PROC_MODE,
+ &pDev->HifIRQProcessingMode,
+ sizeof(pDev->HifIRQProcessingMode));
+
+ switch (pDev->HifIRQProcessingMode) {
+ case HIF_DEVICE_IRQ_SYNC_ONLY:
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is SYNC ONLY\n"));
+ break;
+ case HIF_DEVICE_IRQ_ASYNC_SYNC:
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF Interrupt processing is ASYNC and SYNC\n"));
+ break;
+ default:
+ AR_DEBUG_ASSERT(FALSE);
+ }
+
+ pDev->HifMaskUmaskRecvEvent = NULL;
+
+ /* see if the HIF layer implements the mask/unmask recv events function */
+ HIFConfigureDevice(pDev->HIFDevice,
+ HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+ &pDev->HifMaskUmaskRecvEvent,
+ sizeof(pDev->HifMaskUmaskRecvEvent));
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("HIF special overrides : 0x%X , 0x%X\n",
+ (A_UINT32)pDev->GetPendingEventsFunc, (A_UINT32)pDev->HifMaskUmaskRecvEvent));
+
+ status = DevDisableInterrupts(pDev);
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ /* make sure handle is cleared */
+ HIFSetHandle(pDev->HIFDevice, NULL);
+ }
+
+ return status;
+
+}
+
+static A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+
+ LOCK_AR6K(pDev);
+
+ /* Enable all the interrupts except for the dragon interrupt */
+ pDev->IrqEnableRegisters.int_status_enable = INT_STATUS_ENABLE_ERROR_SET(0x01) |
+ INT_STATUS_ENABLE_CPU_SET(0x01) |
+ INT_STATUS_ENABLE_COUNTER_SET(0x01);
+
+ if (NULL == pDev->GetPendingEventsFunc) {
+ pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ } else {
+ /* The HIF layer provided us with a pending events function which means that
+ * the detection of pending mbox messages is handled in the HIF layer.
+ * This is the case for the SPI2 interface.
+ * In the normal case we enable MBOX interrupts, for the case
+ * with HIFs that offer this mechanism, we keep these interrupts
+ * masked */
+ pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ }
+
+
+ /* Set up the CPU Interrupt Status Register */
+ pDev->IrqEnableRegisters.cpu_int_status_enable = CPU_INT_STATUS_ENABLE_BIT_SET(0x00);
+
+ /* Set up the Error Interrupt Status Register */
+ pDev->IrqEnableRegisters.error_status_enable =
+ ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01) |
+ ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01);
+
+ /* Set up the Counter Interrupt Status Register (only for debug interrupt to catch fatal errors) */
+ pDev->IrqEnableRegisters.counter_int_status_enable =
+ COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK);
+
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ UNLOCK_AR6K(pDev);
+
+ /* always synchronous */
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ /* Can't write it for some reason */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Failed to update interrupt control registers err: %d\n", status));
+
+ }
+
+ return status;
+}
+
+static A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev)
+{
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+
+ LOCK_AR6K(pDev);
+ /* Disable all interrupts */
+ pDev->IrqEnableRegisters.int_status_enable = 0;
+ pDev->IrqEnableRegisters.cpu_int_status_enable = 0;
+ pDev->IrqEnableRegisters.error_status_enable = 0;
+ pDev->IrqEnableRegisters.counter_int_status_enable = 0;
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ UNLOCK_AR6K(pDev);
+
+ /* always synchronous */
+ return HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+}
+
+/* enable device interrupts */
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev)
+{
+ /* Unmask the host controller interrupts */
+ HIFUnMaskInterrupt(pDev->HIFDevice);
+
+ return DevEnableInterrupts(pDev);
+}
+
+/* disable all device interrupts */
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+
+ status = DevDisableInterrupts(pDev);
+
+ if (A_SUCCESS(status)) {
+ /* Disable the interrupt at the HIF layer */
+ HIFMaskInterrupt(pDev->HIFDevice);
+ }
+
+ return status;
+}
+
+/* callback when our fetch to enable/disable completes */
+static void DevDoEnableDisableRecvAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDoEnableDisableRecvAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Failed to disable receiver, status:%d \n", pPacket->Status));
+ }
+ /* free this IO packet */
+ AR6KFreeIOPacket(pDev,pPacket);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDoEnableDisableRecvAsyncHandler \n"));
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "override" method when the HIF reports another methods to
+ * disable recv events */
+static A_STATUS DevDoEnableDisableRecvOverride(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC,("DevDoEnableDisableRecvOverride: Enable:%d Mode:%d\n",
+ EnableRecv,AsyncMode));
+
+ do {
+
+ if (AsyncMode) {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+ pIOPacket->pContext = pDev;
+
+ /* call the HIF layer override and do this asynchronously */
+ status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+ EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+ pIOPacket);
+ break;
+ }
+
+ /* if we get here we are doing it synchronously */
+ status = pDev->HifMaskUmaskRecvEvent(pDev->HIFDevice,
+ EnableRecv ? HIF_UNMASK_RECV : HIF_MASK_RECV,
+ NULL);
+
+ } while (FALSE);
+
+ if (A_FAILED(status) && (pIOPacket != NULL)) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ return status;
+}
+
+/* disable packet reception (used in case the host runs out of buffers)
+ * this is the "normal" method using the interrupt enable registers through
+ * the host I/F */
+static A_STATUS DevDoEnableDisableRecvNormal(AR6K_DEVICE *pDev, A_BOOL EnableRecv, A_BOOL AsyncMode)
+{
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket = NULL;
+ AR6K_IRQ_ENABLE_REGISTERS regs;
+
+ /* take the lock to protect interrupt enable shadows */
+ LOCK_AR6K(pDev);
+
+ if (EnableRecv) {
+ pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ } else {
+ pDev->IrqEnableRegisters.int_status_enable &= ~INT_STATUS_ENABLE_MBOX_DATA_SET(0x01);
+ }
+
+ /* copy into our temp area */
+ A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
+ UNLOCK_AR6K(pDev);
+
+ do {
+
+ if (AsyncMode) {
+
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ status = A_NO_MEMORY;
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* copy values to write to our async I/O buffer */
+ A_MEMCPY(pIOPacket->pBuffer,&regs,AR6K_IRQ_ENABLE_REGS_SIZE);
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevDoEnableDisableRecvAsyncHandler;
+ pIOPacket->pContext = pDev;
+
+ /* write it out asynchronously */
+ HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_ASYNC_BYTE_INC,
+ pIOPacket);
+ break;
+ }
+
+ /* if we get here we are doing it synchronously */
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ INT_STATUS_ENABLE_ADDRESS,
+ &regs.int_status_enable,
+ AR6K_IRQ_ENABLE_REGS_SIZE,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ } while (FALSE);
+
+ if (A_FAILED(status) && (pIOPacket != NULL)) {
+ AR6KFreeIOPacket(pDev,pIOPacket);
+ }
+
+ return status;
+}
+
+
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+ if (NULL == pDev->HifMaskUmaskRecvEvent) {
+ return DevDoEnableDisableRecvNormal(pDev,FALSE,AsyncMode);
+ } else {
+ return DevDoEnableDisableRecvOverride(pDev,FALSE,AsyncMode);
+ }
+}
+
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL AsyncMode)
+{
+ if (NULL == pDev->HifMaskUmaskRecvEvent) {
+ return DevDoEnableDisableRecvNormal(pDev,TRUE,AsyncMode);
+ } else {
+ return DevDoEnableDisableRecvOverride(pDev,TRUE,AsyncMode);
+ }
+}
+
+void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
+ AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs)
+{
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("\n<------- Register Table -------->\n"));
+
+ if (pIrqProcRegs != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Int Status: 0x%x\n",pIrqProcRegs->host_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("CPU Int Status: 0x%x\n",pIrqProcRegs->cpu_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Error Int Status: 0x%x\n",pIrqProcRegs->error_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Counter Int Status: 0x%x\n",pIrqProcRegs->counter_int_status));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Mbox Frame: 0x%x\n",pIrqProcRegs->mbox_frame));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Rx Lookahead Valid: 0x%x\n",pIrqProcRegs->rx_lookahead_valid));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Rx Lookahead 0: 0x%x\n",pIrqProcRegs->rx_lookahead[0]));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Rx Lookahead 1: 0x%x\n",pIrqProcRegs->rx_lookahead[1]));
+ }
+
+ if (pIrqEnableRegs != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Int Status Enable: 0x%x\n",pIrqEnableRegs->int_status_enable));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP,
+ ("Counter Int Status Enable: 0x%x\n",pIrqEnableRegs->counter_int_status_enable));
+ AR_DEBUG_PRINTF(ATH_DEBUG_DUMP, ("<------------------------------->\n"));
+ }
+}
+
+
+#ifdef MBOXHW_UNIT_TEST
+
+
+/* This is a mailbox hardware unit test that must be called in a schedulable context
+ * This test is very simple, it will send a list of buffers with a counting pattern
+ * and the target will invert the data and send the message back
+ *
+ * the unit test has the following constraints:
+ *
+ * The target has at least 8 buffers of 256 bytes each. The host will send
+ * the following pattern of buffers in rapid succession :
+ *
+ * 1 buffer - 128 bytes
+ * 1 buffer - 256 bytes
+ * 1 buffer - 512 bytes
+ * 1 buffer - 1024 bytes
+ *
+ * The host will send the buffers to one mailbox and wait for buffers to be reflected
+ * back from the same mailbox. The target sends the buffers FIFO order.
+ * Once the final buffer has been received for a mailbox, the next mailbox is tested.
+ *
+ *
+ * Note: To simplifythe test , we assume that the chosen buffer sizes
+ * will fall on a nice block pad
+ *
+ * It is expected that higher-order tests will be written to stress the mailboxes using
+ * a message-based protocol (with some performance timming) that can create more
+ * randomness in the packets sent over mailboxes.
+ *
+ * */
+
+#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1))
+
+#define BUFFER_BLOCK_PAD 128
+
+#if 0
+#define BUFFER1 128
+#define BUFFER2 256
+#define BUFFER3 512
+#define BUFFER4 1024
+#endif
+
+#if 1
+#define BUFFER1 80
+#define BUFFER2 200
+#define BUFFER3 444
+#define BUFFER4 800
+#endif
+
+#define TOTAL_BYTES (A_ROUND_UP_PWR2(BUFFER1,BUFFER_BLOCK_PAD) + \
+ A_ROUND_UP_PWR2(BUFFER2,BUFFER_BLOCK_PAD) + \
+ A_ROUND_UP_PWR2(BUFFER3,BUFFER_BLOCK_PAD) + \
+ A_ROUND_UP_PWR2(BUFFER4,BUFFER_BLOCK_PAD) )
+
+#define TEST_BYTES (BUFFER1 + BUFFER2 + BUFFER3 + BUFFER4)
+
+#define TEST_CREDITS_RECV_TIMEOUT 100
+
+static A_UINT8 g_Buffer[TOTAL_BYTES];
+static A_UINT32 g_MailboxAddrs[AR6K_MAILBOXES];
+static A_UINT32 g_BlockSizes[AR6K_MAILBOXES];
+
+#define BUFFER_PROC_LIST_DEPTH 4
+
+typedef struct _BUFFER_PROC_LIST{
+ A_UINT8 *pBuffer;
+ A_UINT32 length;
+}BUFFER_PROC_LIST;
+
+
+#define PUSH_BUFF_PROC_ENTRY(pList,len,pCurrpos) \
+{ \
+ (pList)->pBuffer = (pCurrpos); \
+ (pList)->length = (len); \
+ (pCurrpos) += (len); \
+ (pList)++; \
+}
+
+/* a simple and crude way to send different "message" sizes */
+static void AssembleBufferList(BUFFER_PROC_LIST *pList)
+{
+ A_UINT8 *pBuffer = g_Buffer;
+
+#if BUFFER_PROC_LIST_DEPTH < 4
+#error "Buffer processing list depth is not deep enough!!"
+#endif
+
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER1,pBuffer);
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER2,pBuffer);
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER3,pBuffer);
+ PUSH_BUFF_PROC_ENTRY(pList,BUFFER4,pBuffer);
+
+}
+
+#define FILL_ZERO TRUE
+#define FILL_COUNTING FALSE
+static void InitBuffers(A_BOOL Zero)
+{
+ A_UINT16 *pBuffer16 = (A_UINT16 *)g_Buffer;
+ int i;
+
+ /* fill buffer with 16 bit counting pattern or zeros */
+ for (i = 0; i < (TOTAL_BYTES / 2) ; i++) {
+ if (!Zero) {
+ pBuffer16[i] = (A_UINT16)i;
+ } else {
+ pBuffer16[i] = 0;
+ }
+ }
+}
+
+
+static A_BOOL CheckOneBuffer(A_UINT16 *pBuffer16, int Length)
+{
+ int i;
+ A_UINT16 startCount;
+ A_BOOL success = TRUE;
+
+ /* get the starting count */
+ startCount = pBuffer16[0];
+ /* invert it, this is the expected value */
+ startCount = ~startCount;
+ /* scan the buffer and verify */
+ for (i = 0; i < (Length / 2) ; i++,startCount++) {
+ /* target will invert all the data */
+ if ((A_UINT16)pBuffer16[i] != (A_UINT16)~startCount) {
+ success = FALSE;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Invalid Data Got:0x%X, Expecting:0x%X (offset:%d, total:%d) \n",
+ pBuffer16[i], ((A_UINT16)~startCount), i, Length));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("0x%X 0x%X 0x%X 0x%X \n",
+ pBuffer16[i], pBuffer16[i + 1], pBuffer16[i + 2],pBuffer16[i+3]));
+ break;
+ }
+ }
+
+ return success;
+}
+
+static A_BOOL CheckBuffers(void)
+{
+ int i;
+ A_BOOL success = TRUE;
+ BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+ /* assemble the list */
+ AssembleBufferList(checkList);
+
+ /* scan the buffers and verify */
+ for (i = 0; i < BUFFER_PROC_LIST_DEPTH ; i++) {
+ success = CheckOneBuffer((A_UINT16 *)checkList[i].pBuffer, checkList[i].length);
+ if (!success) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer : 0x%X, Length:%d failed verify \n",
+ (A_UINT32)checkList[i].pBuffer, checkList[i].length));
+ break;
+ }
+ }
+
+ return success;
+}
+
+ /* find the end marker for the last buffer we will be sending */
+static A_UINT16 GetEndMarker(void)
+{
+ A_UINT8 *pBuffer;
+ BUFFER_PROC_LIST checkList[BUFFER_PROC_LIST_DEPTH];
+
+ /* fill up buffers with the normal counting pattern */
+ InitBuffers(FILL_COUNTING);
+
+ /* assemble the list we will be sending down */
+ AssembleBufferList(checkList);
+ /* point to the last 2 bytes of the last buffer */
+ pBuffer = &(checkList[BUFFER_PROC_LIST_DEPTH - 1].pBuffer[(checkList[BUFFER_PROC_LIST_DEPTH - 1].length) - 2]);
+
+ /* the last count in the last buffer is the marker */
+ return (A_UINT16)pBuffer[0] | ((A_UINT16)pBuffer[1] << 8);
+}
+
+#define ATH_PRINT_OUT_ZONE ATH_DEBUG_ERR
+
+/* send the ordered buffers to the target */
+static A_STATUS SendBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+ A_STATUS status = A_OK;
+ A_UINT32 request = HIF_WR_SYNC_BLOCK_INC;
+ BUFFER_PROC_LIST sendList[BUFFER_PROC_LIST_DEPTH];
+ int i;
+ int totalBytes = 0;
+ int paddedLength;
+ int totalwPadding = 0;
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sending buffers on mailbox : %d \n",mbox));
+
+ /* fill buffer with counting pattern */
+ InitBuffers(FILL_COUNTING);
+
+ /* assemble the order in which we send */
+ AssembleBufferList(sendList);
+
+ for (i = 0; i < BUFFER_PROC_LIST_DEPTH; i++) {
+
+ /* we are doing block transfers, so we need to pad everything to a block size */
+ paddedLength = (sendList[i].length + (g_BlockSizes[mbox] - 1)) &
+ (~(g_BlockSizes[mbox] - 1));
+
+ /* send each buffer synchronously */
+ status = HIFReadWrite(pDev->HIFDevice,
+ g_MailboxAddrs[mbox],
+ sendList[i].pBuffer,
+ paddedLength,
+ request,
+ NULL);
+ if (status != A_OK) {
+ break;
+ }
+ totalBytes += sendList[i].length;
+ totalwPadding += paddedLength;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Sent %d bytes (%d padded bytes) to mailbox : %d \n",totalBytes,totalwPadding,mbox));
+
+ return status;
+}
+
+/* poll the mailbox credit counter until we get a credit or timeout */
+static A_STATUS GetCredits(AR6K_DEVICE *pDev, int mbox, int *pCredits)
+{
+ A_STATUS status = A_OK;
+ int timeout = TEST_CREDITS_RECV_TIMEOUT;
+ A_UINT8 credits = 0;
+ A_UINT32 address;
+
+ while (TRUE) {
+
+ /* Read the counter register to get credits, this auto-decrements */
+ address = COUNT_DEC_ADDRESS + (AR6K_MAILBOXES + mbox) * 4;
+ status = HIFReadWrite(pDev->HIFDevice, address, &credits, sizeof(credits),
+ HIF_RD_SYNC_BYTE_FIX, NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Unable to decrement the command credit count register (mbox=%d)\n",mbox));
+ status = A_ERROR;
+ break;
+ }
+
+ if (credits) {
+ break;
+ }
+
+ timeout--;
+
+ if (timeout <= 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Timeout reading credit registers (mbox=%d, address:0x%X) \n",mbox,address));
+ status = A_ERROR;
+ break;
+ }
+
+ /* delay a little, target may not be ready */
+ A_MDELAY(1000);
+
+ }
+
+ if (status == A_OK) {
+ *pCredits = credits;
+ }
+
+ return status;
+}
+
+
+/* wait for the buffers to come back */
+static A_STATUS RecvBuffers(AR6K_DEVICE *pDev, int mbox)
+{
+ A_STATUS status = A_OK;
+ A_UINT32 request = HIF_RD_SYNC_BLOCK_INC;
+ BUFFER_PROC_LIST recvList[BUFFER_PROC_LIST_DEPTH];
+ int curBuffer;
+ int credits;
+ int i;
+ int totalBytes = 0;
+ int paddedLength;
+ int totalwPadding = 0;
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for buffers on mailbox : %d \n",mbox));
+
+ /* zero the buffers */
+ InitBuffers(FILL_ZERO);
+
+ /* assemble the order in which we should receive */
+ AssembleBufferList(recvList);
+
+ curBuffer = 0;
+
+ while (curBuffer < BUFFER_PROC_LIST_DEPTH) {
+
+ /* get number of buffers that have been completed, this blocks
+ * until we get at least 1 credit or it times out */
+ status = GetCredits(pDev, mbox, &credits);
+
+ if (status != A_OK) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got %d messages on mailbox : %d \n",credits, mbox));
+
+ /* get all the buffers that are sitting on the queue */
+ for (i = 0; i < credits; i++) {
+ AR_DEBUG_ASSERT(curBuffer < BUFFER_PROC_LIST_DEPTH);
+ /* recv the current buffer synchronously, the buffers should come back in
+ * order... with padding applied by the target */
+ paddedLength = (recvList[curBuffer].length + (g_BlockSizes[mbox] - 1)) &
+ (~(g_BlockSizes[mbox] - 1));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ g_MailboxAddrs[mbox],
+ recvList[curBuffer].pBuffer,
+ paddedLength,
+ request,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to read %d bytes on mailbox:%d : address:0x%X \n",
+ recvList[curBuffer].length, mbox, g_MailboxAddrs[mbox]));
+ break;
+ }
+
+ totalwPadding += paddedLength;
+ totalBytes += recvList[curBuffer].length;
+ curBuffer++;
+ }
+
+ if (status != A_OK) {
+ break;
+ }
+ /* go back and get some more */
+ credits = 0;
+ }
+
+ if (totalBytes != TEST_BYTES) {
+ AR_DEBUG_ASSERT(FALSE);
+ } else {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Got all buffers on mbox:%d total recv :%d (w/Padding : %d) \n",
+ mbox, totalBytes, totalwPadding));
+ }
+
+ return status;
+
+
+}
+
+static A_STATUS DoOneMboxHWTest(AR6K_DEVICE *pDev, int mbox)
+{
+ A_STATUS status;
+
+ do {
+ /* send out buffers */
+ status = SendBuffers(pDev,mbox);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Sending buffers Failed : %d mbox:%d\n",status,mbox));
+ break;
+ }
+
+ /* go get them, this will block */
+ status = RecvBuffers(pDev, mbox);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Recv buffers Failed : %d mbox:%d\n",status,mbox));
+ break;
+ }
+
+ /* check the returned data patterns */
+ if (!CheckBuffers()) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Buffer Verify Failed : mbox:%d\n",mbox));
+ status = A_ERROR;
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" Send/Recv success! mailbox : %d \n",mbox));
+
+ } while (FALSE);
+
+ return status;
+}
+
+/* here is where the test starts */
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev)
+{
+ int i;
+ A_STATUS status;
+ int credits = 0;
+ A_UINT8 params[4];
+ int numBufs;
+ int bufferSize;
+ A_UINT16 temp;
+
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest START - \n"));
+
+ do {
+ /* get the addresses for all 4 mailboxes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_ADDR,
+ g_MailboxAddrs, sizeof(g_MailboxAddrs));
+
+ if (status != A_OK) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* get the block sizes */
+ status = HIFConfigureDevice(pDev->HIFDevice, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ g_BlockSizes, sizeof(g_BlockSizes));
+
+ if (status != A_OK) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* note, the HIF layer usually reports mbox 0 to have a block size of
+ * 1, but our test wants to run in block-mode for all mailboxes, so we treat all mailboxes
+ * the same. */
+ g_BlockSizes[0] = g_BlockSizes[1];
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Block Size to use: %d \n",g_BlockSizes[0]));
+
+ if (g_BlockSizes[1] > BUFFER_BLOCK_PAD) {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("%d Block size is too large for buffer pad %d\n",
+ g_BlockSizes[1], BUFFER_BLOCK_PAD));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Waiting for target.... \n"));
+
+ /* the target lets us know it is ready by giving us 1 credit on
+ * mailbox 0 */
+ status = GetCredits(pDev, 0, &credits);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait for target ready \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Target is ready ...\n"));
+
+ /* read the first 4 scratch registers */
+ status = HIFReadWrite(pDev->HIFDevice,
+ SCRATCH_ADDRESS,
+ params,
+ 4,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to wait get parameters \n"));
+ break;
+ }
+
+ numBufs = params[0];
+ bufferSize = (int)(((A_UINT16)params[2] << 8) | (A_UINT16)params[1]);
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE,
+ ("Target parameters: bufs per mailbox:%d, buffer size:%d bytes (total space: %d, minimum required space (w/padding): %d) \n",
+ numBufs, bufferSize, (numBufs * bufferSize), TOTAL_BYTES));
+
+ if ((numBufs * bufferSize) < TOTAL_BYTES) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Not Enough buffer space to run test! need:%d, got:%d \n",
+ TOTAL_BYTES, (numBufs*bufferSize)));
+ status = A_ERROR;
+ break;
+ }
+
+ temp = GetEndMarker();
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ SCRATCH_ADDRESS + 4,
+ (A_UINT8 *)&temp,
+ 2,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write end marker \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("End Marker: 0x%X \n",temp));
+
+ temp = (A_UINT16)g_BlockSizes[1];
+ /* convert to a mask */
+ temp = temp - 1;
+ status = HIFReadWrite(pDev->HIFDevice,
+ SCRATCH_ADDRESS + 6,
+ (A_UINT8 *)&temp,
+ 2,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to write block mask \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, ("Set Block Mask: 0x%X \n",temp));
+
+ /* execute the test on each mailbox */
+ for (i = 0; i < AR6K_MAILBOXES; i++) {
+ status = DoOneMboxHWTest(pDev, i);
+ if (status != A_OK) {
+ break;
+ }
+ }
+
+ } while (FALSE);
+
+ if (status == A_OK) {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - SUCCESS! - \n"));
+ } else {
+ AR_DEBUG_PRINTF(ATH_PRINT_OUT_ZONE, (" DoMboxHWTest DONE - FAILED! - \n"));
+ }
+ /* don't let HTC_Start continue, the target is actually not running any HTC code */
+ return A_ERROR;
+}
+#endif
+
+
+
--- /dev/null
+++ b/drivers/ar6000/htc/ar6k_events.c
@@ -0,0 +1,638 @@
+/*
+ * AR6K Driver layer event handling (i.e. interrupts, message polling)
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6Khwreg.h"
+#include "a_osapi.h"
+#include "a_debug.h"
+#include "hif.h"
+#include "htc_packet.h"
+#include "ar6k.h"
+
+extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
+extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
+
+#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
+
+/* completion routine for ALL HIF layer async I/O */
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
+{
+ HTC_PACKET *pPacket = (HTC_PACKET *)context;
+
+ COMPLETE_HTC_PACKET(pPacket,status);
+
+ return A_OK;
+}
+
+/* mailbox recv message polling */
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+ A_UINT32 *pLookAhead,
+ int TimeoutMS)
+{
+ A_STATUS status = A_OK;
+ int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
+
+ AR_DEBUG_ASSERT(timeout > 0);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
+
+ while (TRUE) {
+
+ if (pDev->GetPendingEventsFunc != NULL)
+ {
+
+ HIF_PENDING_EVENTS_INFO events;
+
+ /* the HIF layer uses a special mechanism to get events, do this
+ * synchronously */
+ status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+ &events,
+ NULL);
+ if (A_FAILED(status))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
+ break;
+ }
+
+ if (events.Events & HIF_RECV_MSG_AVAIL)
+ {
+ /* there is a message available, the lookahead should be valid now */
+ *pLookAhead = events.LookAhead;
+
+ break;
+ }
+ }
+ else
+ {
+
+ /* this is the standard HIF way.... */
+ /* load the register table */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ (A_UINT8 *)&pDev->IrqProcRegisters,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (A_FAILED(status))
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
+ break;
+ }
+
+ /* check for MBOX data and valid lookahead */
+ if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX))
+ {
+ if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
+ {
+ /* mailbox has a message and the look ahead is valid */
+ *pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+ break;
+ }
+ }
+
+ }
+
+ timeout--;
+
+ if (timeout <= 0)
+ {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
+ status = A_ERROR;
+
+ /* check if the target asserted */
+ if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+ /* target signaled an assert, process this pending interrupt
+ * this will call the target failure handler */
+ DevServiceDebugInterrupt(pDev);
+ }
+
+ break;
+ }
+
+ /* delay a little */
+ A_MDELAY(DELAY_PER_INTERVAL_MS);
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout));
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
+
+ return status;
+}
+
+static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ A_UINT8 cpu_int_status;
+ A_UINT8 regBuffer[4];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
+ cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
+ pDev->IrqEnableRegisters.cpu_int_status_enable;
+ AR_DEBUG_ASSERT(cpu_int_status);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ ("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
+ cpu_int_status));
+
+ /* Clear the interrupt */
+ pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
+
+ /* set up the register transfer buffer to hit the register 4 times , this is done
+ * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+ * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+ /* set W1C value to clear the interrupt, this hits the register first */
+ regBuffer[0] = cpu_int_status;
+ /* the remaining 4 values are set to zero which have no-effect */
+ regBuffer[1] = 0;
+ regBuffer[2] = 0;
+ regBuffer[3] = 0;
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ CPU_INT_STATUS_ADDRESS,
+ regBuffer,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+
+ AR_DEBUG_ASSERT(status == A_OK);
+ return status;
+}
+
+
+static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
+{
+ A_STATUS status;
+ A_UINT8 error_int_status;
+ A_UINT8 regBuffer[4];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
+ error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
+ AR_DEBUG_ASSERT(error_int_status);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ ("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
+ error_int_status));
+
+ if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
+ /* Wakeup */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
+ }
+
+ if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
+ /* Rx Underflow */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
+ }
+
+ if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
+ /* Tx Overflow */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
+ }
+
+ /* Clear the interrupt */
+ pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
+
+ /* set up the register transfer buffer to hit the register 4 times , this is done
+ * to make the access 4-byte aligned to mitigate issues with host bus interconnects that
+ * restrict bus transfer lengths to be a multiple of 4-bytes */
+
+ /* set W1C value to clear the interrupt, this hits the register first */
+ regBuffer[0] = error_int_status;
+ /* the remaining 4 values are set to zero which have no-effect */
+ regBuffer[1] = 0;
+ regBuffer[2] = 0;
+ regBuffer[3] = 0;
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ ERROR_INT_STATUS_ADDRESS,
+ regBuffer,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+
+ AR_DEBUG_ASSERT(status == A_OK);
+ return status;
+}
+
+static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
+{
+ A_UINT32 dummy;
+ A_STATUS status;
+
+ /* Send a target failure event to the application */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
+
+ if (pDev->TargetFailureCallback != NULL) {
+ pDev->TargetFailureCallback(pDev->HTCContext);
+ }
+
+ /* clear the interrupt , the debug error interrupt is
+ * counter 0 */
+ /* read counter to clear interrupt */
+ status = HIFReadWrite(pDev->HIFDevice,
+ COUNT_DEC_ADDRESS,
+ (A_UINT8 *)&dummy,
+ 4,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ AR_DEBUG_ASSERT(status == A_OK);
+ return status;
+}
+
+static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
+{
+ A_UINT8 counter_int_status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
+
+ counter_int_status = pDev->IrqProcRegisters.counter_int_status &
+ pDev->IrqEnableRegisters.counter_int_status_enable;
+
+ AR_DEBUG_ASSERT(counter_int_status);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ ("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
+ counter_int_status));
+
+ /* Check if the debug interrupt is pending */
+ if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
+ return DevServiceDebugInterrupt(pDev);
+ }
+
+ return A_OK;
+}
+
+/* callback when our fetch to get interrupt status registers completes */
+static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
+ A_UINT32 lookAhead = 0;
+ A_BOOL otherInts = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ do {
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" GetEvents I/O request failed, status:%d \n", pPacket->Status));
+ /* bail out, don't unmask HIF interrupt */
+ break;
+ }
+
+ if (pDev->GetPendingEventsFunc != NULL) {
+ /* the HIF layer collected the information for us */
+ HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
+ if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
+ lookAhead = pEvents->LookAhead;
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
+ }
+ }
+ if (pEvents->Events & HIF_OTHER_EVENTS) {
+ otherInts = TRUE;
+ }
+ } else {
+ /* standard interrupt table handling.... */
+ AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
+ A_UINT8 host_int_status;
+
+ host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
+
+ if (host_int_status & (1 << HTC_MAILBOX)) {
+ host_int_status &= ~(1 << HTC_MAILBOX);
+ if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+ /* mailbox has a message and the look ahead is valid */
+ lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
+ }
+ }
+ }
+
+ if (host_int_status) {
+ /* there are other interrupts to handle */
+ otherInts = TRUE;
+ }
+ }
+
+ if (otherInts || (lookAhead == 0)) {
+ /* if there are other interrupts to process, we cannot do this in the async handler so
+ * ack the interrupt which will cause our sync handler to run again
+ * if however there are no more messages, we can now ack the interrupt */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
+ otherInts, lookAhead));
+ HIFAckInterrupt(pDev->HIFDevice);
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
+ lookAhead));
+ /* lookahead is non-zero and there are no other interrupts to service,
+ * go get the next message */
+ pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, NULL);
+ }
+
+ } while (FALSE);
+
+ /* free this IO packet */
+ AR6KFreeIOPacket(pDev,pPacket);
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
+}
+
+/* called by the HTC layer when it wants us to check if the device has any more pending
+ * recv messages, this starts off a series of async requests to read interrupt registers */
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
+ A_STATUS status = A_OK;
+ HTC_PACKET *pIOPacket;
+
+ /* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
+ * cause us to switch contexts */
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ do {
+
+ if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+ /* break the async processing chain right here, no need to continue.
+ * The DevDsrHandler() will handle things in a loop when things are driven
+ * synchronously */
+ break;
+ }
+ /* first allocate one of our HTC packets we created for async I/O
+ * we reuse HTC packet definitions so that we can use the completion mechanism
+ * in DevRWCompletionHandler() */
+ pIOPacket = AR6KAllocIOPacket(pDev);
+
+ if (NULL == pIOPacket) {
+ /* there should be only 1 asynchronous request out at a time to read these registers
+ * so this should actually never happen */
+ status = A_NO_MEMORY;
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* stick in our completion routine when the I/O operation completes */
+ pIOPacket->Completion = DevGetEventAsyncHandler;
+ pIOPacket->pContext = pDev;
+
+ if (pDev->GetPendingEventsFunc) {
+ /* HIF layer has it's own mechanism, pass the IO to it.. */
+ status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+ (HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
+ pIOPacket);
+
+ } else {
+ /* standard way, read the interrupt register table asynchronously again */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ pIOPacket->pBuffer,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_ASYNC_BYTE_INC,
+ pIOPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
+
+ return status;
+}
+
+/* process pending interrupts synchronously */
+static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
+{
+ A_STATUS status = A_OK;
+ A_UINT8 host_int_status = 0;
+ A_UINT32 lookAhead = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+ /*** NOTE: the HIF implementation guarantees that the context of this call allows
+ * us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
+ * can block or switch thread/task ontexts.
+ * This is a fully schedulable context.
+ * */
+ do {
+
+ if (pDev->GetPendingEventsFunc != NULL) {
+ HIF_PENDING_EVENTS_INFO events;
+
+ /* the HIF layer uses a special mechanism to get events
+ * get this synchronously */
+ status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
+ &events,
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (events.Events & HIF_RECV_MSG_AVAIL) {
+ lookAhead = events.LookAhead;
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
+ }
+ }
+
+ if (!(events.Events & HIF_OTHER_EVENTS) ||
+ !(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
+ /* no need to read the register table, no other interesting interrupts.
+ * Some interfaces (like SPI) can shadow interrupt sources without
+ * requiring the host to do a full table read */
+ break;
+ }
+
+ /* otherwise fall through and read the register table */
+ }
+
+ /*
+ * Read the first 28 bytes of the HTC register table. This will yield us
+ * the value of different int status registers and the lookahead
+ * registers.
+ * length = sizeof(int_status) + sizeof(cpu_int_status) +
+ * sizeof(error_int_status) + sizeof(counter_int_status) +
+ * sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
+ * sizeof(hole) + sizeof(rx_lookahead) +
+ * sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
+ * sizeof(error_status_enable) +
+ * sizeof(counter_int_status_enable);
+ *
+ */
+ status = HIFReadWrite(pDev->HIFDevice,
+ HOST_INT_STATUS_ADDRESS,
+ (A_UINT8 *)&pDev->IrqProcRegisters,
+ AR6K_IRQ_PROC_REGS_SIZE,
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
+ DevDumpRegisters(&pDev->IrqProcRegisters,
+ &pDev->IrqEnableRegisters);
+ }
+
+ /* Update only those registers that are enabled */
+ host_int_status = pDev->IrqProcRegisters.host_int_status &
+ pDev->IrqEnableRegisters.int_status_enable;
+
+ if (NULL == pDev->GetPendingEventsFunc) {
+ /* only look at mailbox status if the HIF layer did not provide this function,
+ * on some HIF interfaces reading the RX lookahead is not valid to do */
+ if (host_int_status & (1 << HTC_MAILBOX)) {
+ /* mask out pending mailbox value, we use "lookAhead" as the real flag for
+ * mailbox processing below */
+ host_int_status &= ~(1 << HTC_MAILBOX);
+ if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
+ /* mailbox has a message and the look ahead is valid */
+ lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
+ if (0 == lookAhead) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
+ }
+ }
+ }
+ } else {
+ /* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
+ host_int_status &= ~(1 << HTC_MAILBOX);
+ }
+
+ } while (FALSE);
+
+
+ do {
+
+ /* did the interrupt status fetches succeed? */
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if ((0 == host_int_status) && (0 == lookAhead)) {
+ /* nothing to process, the caller can use this to break out of a loop */
+ *pDone = TRUE;
+ break;
+ }
+
+ if (lookAhead != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
+ /* Mailbox Interrupt, the HTC layer may issue async requests to empty the
+ * mailbox...
+ * When emptying the recv mailbox we use the async handler above called from the
+ * completion routine of the callers read request. This can improve performance
+ * by reducing context switching when we rapidly pull packets */
+ status = pDev->MessagePendingCallback(pDev->HTCContext, lookAhead, pASyncProcessing);
+ if (A_FAILED(status)) {
+ break;
+ }
+ }
+
+ /* now handle the rest of them */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
+ (" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
+ host_int_status));
+
+ if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
+ /* CPU Interrupt */
+ status = DevServiceCPUInterrupt(pDev);
+ if (A_FAILED(status)){
+ break;
+ }
+ }
+
+ if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
+ /* Error Interrupt */
+ status = DevServiceErrorInterrupt(pDev);
+ if (A_FAILED(status)){
+ break;
+ }
+ }
+
+ if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
+ /* Counter Interrupt */
+ status = DevServiceCounterInterrupt(pDev);
+ if (A_FAILED(status)){
+ break;
+ }
+ }
+
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
+ *pDone, *pASyncProcessing, status));
+
+ return status;
+}
+
+
+/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
+A_STATUS DevDsrHandler(void *context)
+{
+ AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
+ A_STATUS status = A_OK;
+ A_BOOL done = FALSE;
+ A_BOOL asyncProc = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%X)\n", (A_UINT32)pDev));
+
+
+ while (!done) {
+ status = ProcessPendingIRQs(pDev, &done, &asyncProc);
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
+ /* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
+ asyncProc = FALSE;
+ /* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
+ * this has a nice side effect of blocking us until all async read requests are completed.
+ * This behavior is required on some HIF implementations that do not allow ASYNC
+ * processing in interrupt handlers (like Windows CE) */
+ }
+
+ if (asyncProc) {
+ /* the function performed some async I/O for performance, we
+ need to exit the ISR immediately, the check below will prevent the interrupt from being
+ Ack'd while we handle it asynchronously */
+ break;
+ }
+
+ }
+
+ if (A_SUCCESS(status) && !asyncProc) {
+ /* Ack the interrupt only if :
+ * 1. we did not get any errors in processing interrupts
+ * 2. there are no outstanding async processing requests */
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
+ HIFAckInterrupt(pDev->HIFDevice);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
+ return A_OK;
+}
+
+
--- /dev/null
+++ b/drivers/ar6000/htc/ar6k.h
@@ -0,0 +1,191 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef AR6K_H_
+#define AR6K_H_
+
+#define AR6K_MAILBOXES 4
+
+/* HTC runs over mailbox 0 */
+#define HTC_MAILBOX 0
+
+#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
+
+#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
+ INT_STATUS_ENABLE_CPU_MASK | \
+ INT_STATUS_ENABLE_COUNTER_MASK)
+
+//#define MBOXHW_UNIT_TEST 1
+
+#include "athstartpack.h"
+typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
+ A_UINT8 host_int_status;
+ A_UINT8 cpu_int_status;
+ A_UINT8 error_int_status;
+ A_UINT8 counter_int_status;
+ A_UINT8 mbox_frame;
+ A_UINT8 rx_lookahead_valid;
+ A_UINT8 hole[2];
+ A_UINT32 rx_lookahead[2];
+} POSTPACK AR6K_IRQ_PROC_REGISTERS;
+
+#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
+
+
+
+typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
+ A_UINT8 int_status_enable;
+ A_UINT8 cpu_int_status_enable;
+ A_UINT8 error_status_enable;
+ A_UINT8 counter_int_status_enable;
+} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
+
+#include "athendpack.h"
+
+#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
+
+#define AR6K_REG_IO_BUFFER_SIZE 32
+#define AR6K_MAX_REG_IO_BUFFERS 8
+
+/* buffers for ASYNC I/O */
+typedef struct AR6K_ASYNC_REG_IO_BUFFER {
+ HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */
+ A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE];
+} AR6K_ASYNC_REG_IO_BUFFER;
+
+typedef struct _AR6K_DEVICE {
+ A_MUTEX_T Lock;
+ AR6K_IRQ_PROC_REGISTERS IrqProcRegisters;
+ AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters;
+ void *HIFDevice;
+ A_UINT32 BlockSize;
+ A_UINT32 BlockMask;
+ A_UINT32 MailboxAddress;
+ HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
+ void *HTCContext;
+ HTC_PACKET_QUEUE RegisterIOList;
+ AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
+ void (*TargetFailureCallback)(void *Context);
+ A_STATUS (*MessagePendingCallback)(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc);
+ HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode;
+ HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
+} AR6K_DEVICE;
+
+#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
+
+A_STATUS DevSetup(AR6K_DEVICE *pDev);
+A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
+A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
+ A_UINT32 *pLookAhead,
+ int TimeoutMS);
+A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
+A_STATUS DevDsrHandler(void *context);
+A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
+void DevDumpRegisters(AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
+ AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
+
+#define DEV_STOP_RECV_ASYNC TRUE
+#define DEV_STOP_RECV_SYNC FALSE
+#define DEV_ENABLE_RECV_ASYNC TRUE
+#define DEV_ENABLE_RECV_SYNC FALSE
+A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
+
+static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
+ A_UINT32 paddedLength;
+ A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+ A_STATUS status;
+
+ /* adjust the length to be a multiple of block size if appropriate */
+ paddedLength = (SendLength + (pDev->BlockMask)) &
+ (~(pDev->BlockMask));
+#if 0 // BufferLength may not be set in , fix this...
+ if (paddedLength > pPacket->BufferLength) {
+ AR_DEBUG_ASSERT(FALSE);
+ if (pPacket->Completion != NULL) {
+ COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+ }
+ return A_EINVAL;
+ }
+#endif
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+ paddedLength,
+ pDev->MailboxAddress,
+ sync ? "SYNC" : "ASYNC"));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ pDev->MailboxAddress,
+ pPacket->pBuffer,
+ paddedLength, /* the padded length */
+ sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
+ sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
+
+ if (sync) {
+ pPacket->Status = status;
+ }
+
+ return status;
+}
+
+static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
+ A_UINT32 paddedLength;
+ A_STATUS status;
+ A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
+
+ /* adjust the length to be a multiple of block size if appropriate */
+ paddedLength = (RecvLength + (pDev->BlockMask)) &
+ (~(pDev->BlockMask));
+ if (paddedLength > pPacket->BufferLength) {
+ AR_DEBUG_ASSERT(FALSE);
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
+ paddedLength,RecvLength,pPacket->BufferLength));
+ if (pPacket->Completion != NULL) {
+ COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
+ }
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("DevRecvPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
+ paddedLength,
+ pDev->MailboxAddress,
+ sync ? "SYNC" : "ASYNC"));
+
+ status = HIFReadWrite(pDev->HIFDevice,
+ pDev->MailboxAddress,
+ pPacket->pBuffer,
+ paddedLength,
+ sync ? HIF_RD_SYNC_BLOCK_INC : HIF_RD_ASYNC_BLOCK_INC,
+ sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
+
+ if (sync) {
+ pPacket->Status = status;
+ }
+
+ return status;
+}
+
+#ifdef MBOXHW_UNIT_TEST
+A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
+#endif
+
+#endif /*AR6K_H_*/
--- /dev/null
+++ b/drivers/ar6000/htc/htc.c
@@ -0,0 +1,507 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "htc_internal.h"
+
+
+static HTC_INIT_INFO HTCInitInfo = {NULL,NULL,NULL};
+static A_BOOL HTCInitialized = FALSE;
+
+static A_STATUS HTCTargetInsertedHandler(void *hif_handle);
+static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status);
+static void HTCReportFailure(void *Context);
+
+/* Initializes the HTC layer */
+A_STATUS HTCInit(HTC_INIT_INFO *pInitInfo)
+{
+ HTC_CALLBACKS htcCallbacks;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Enter\n"));
+ if (HTCInitialized) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
+ return A_OK;
+ }
+
+ A_MEMCPY(&HTCInitInfo,pInitInfo,sizeof(HTC_INIT_INFO));
+
+ A_MEMZERO(&htcCallbacks, sizeof(HTC_CALLBACKS));
+
+ /* setup HIF layer callbacks */
+ htcCallbacks.deviceInsertedHandler = HTCTargetInsertedHandler;
+ htcCallbacks.deviceRemovedHandler = HTCTargetRemovedHandler;
+ /* the device layer handles these */
+ htcCallbacks.rwCompletionHandler = DevRWCompletionHandler;
+ htcCallbacks.dsrHandler = DevDsrHandler;
+ HIFInit(&htcCallbacks);
+ HTCInitialized = TRUE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCInit: Exit\n"));
+ return A_OK;
+}
+
+void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
+{
+ LOCK_HTC(target);
+ HTC_PACKET_ENQUEUE(pList,pPacket);
+ UNLOCK_HTC(target);
+}
+
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList)
+{
+ HTC_PACKET *pPacket;
+
+ LOCK_HTC(target);
+ pPacket = HTC_PACKET_DEQUEUE(pList);
+ UNLOCK_HTC(target);
+
+ return pPacket;
+}
+
+/* cleanup the HTC instance */
+static void HTCCleanup(HTC_TARGET *target)
+{
+ if (A_IS_MUTEX_VALID(&target->HTCLock)) {
+ A_MUTEX_DELETE(&target->HTCLock);
+ }
+
+ if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
+ A_MUTEX_DELETE(&target->HTCRxLock);
+ }
+
+ if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
+ A_MUTEX_DELETE(&target->HTCTxLock);
+ }
+ /* free our instance */
+ A_FREE(target);
+}
+
+/* registered target arrival callback from the HIF layer */
+static A_STATUS HTCTargetInsertedHandler(void *hif_handle)
+{
+ HTC_TARGET *target = NULL;
+ A_STATUS status;
+ int i;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Enter\n"));
+
+ do {
+
+ /* allocate target memory */
+ if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
+ status = A_ERROR;
+ break;
+ }
+
+ A_MEMZERO(target, sizeof(HTC_TARGET));
+ A_MUTEX_INIT(&target->HTCLock);
+ A_MUTEX_INIT(&target->HTCRxLock);
+ A_MUTEX_INIT(&target->HTCTxLock);
+ INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
+ INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
+
+ /* give device layer the hif device handle */
+ target->Device.HIFDevice = hif_handle;
+ /* give the device layer our context (for event processing)
+ * the device layer will register it's own context with HIF
+ * so we need to set this so we can fetch it in the target remove handler */
+ target->Device.HTCContext = target;
+ /* set device layer target failure callback */
+ target->Device.TargetFailureCallback = HTCReportFailure;
+ /* set device layer recv message pending callback */
+ target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
+ target->EpWaitingForBuffers = ENDPOINT_MAX;
+
+ /* setup device layer */
+ status = DevSetup(&target->Device);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* carve up buffers/packets for control messages */
+ for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
+ HTC_PACKET *pControlPacket;
+ pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+ SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
+ target,
+ target->HTCControlBuffers[i].Buffer,
+ HTC_CONTROL_BUFFER_SIZE,
+ ENDPOINT_0);
+ HTC_FREE_CONTROL_RX(target,pControlPacket);
+ }
+
+ for (;i < NUM_CONTROL_BUFFERS;i++) {
+ HTC_PACKET *pControlPacket;
+ pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
+ INIT_HTC_PACKET_INFO(pControlPacket,
+ target->HTCControlBuffers[i].Buffer,
+ HTC_CONTROL_BUFFER_SIZE);
+ HTC_FREE_CONTROL_TX(target,pControlPacket);
+ }
+
+ } while (FALSE);
+
+ if (A_SUCCESS(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" calling AddInstance callback \n"));
+ /* announce ourselves */
+ HTCInitInfo.AddInstance((HTC_HANDLE)target);
+ } else {
+ if (target != NULL) {
+ HTCCleanup(target);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htcTargetInserted - Exit\n"));
+
+ return status;
+}
+
+/* registered removal callback from the HIF layer */
+static A_STATUS HTCTargetRemovedHandler(void *handle, A_STATUS status)
+{
+ HTC_TARGET *target;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCTargetRemovedHandler handle:0x%X \n",(A_UINT32)handle));
+
+ if (NULL == handle) {
+ /* this could be NULL in the event that target initialization failed */
+ return A_OK;
+ }
+
+ target = ((AR6K_DEVICE *)handle)->HTCContext;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" removing target:0x%X instance:0x%X ... \n",
+ (A_UINT32)target, (A_UINT32)target->pInstanceContext));
+
+ if (target->pInstanceContext != NULL) {
+ /* let upper layer know, it needs to call HTCStop() */
+ HTCInitInfo.DeleteInstance(target->pInstanceContext);
+ }
+
+ HIFShutDownDevice(target->Device.HIFDevice);
+
+ HTCCleanup(target);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCTargetRemovedHandler \n"));
+ return A_OK;
+}
+
+/* get the low level HIF device for the caller , the caller may wish to do low level
+ * HIF requests */
+void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ return target->Device.HIFDevice;
+}
+
+/* set the instance block for this HTC handle, so that on removal, the blob can be
+ * returned to the caller */
+void HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+ target->pInstanceContext = Instance;
+}
+
+/* wait for the target to arrive (sends HTC Ready message)
+ * this operation is fully synchronous and the message is polled for */
+A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_STATUS status;
+ HTC_PACKET *pPacket = NULL;
+ HTC_READY_MSG *pRdyMsg;
+ HTC_SERVICE_CONNECT_REQ connect;
+ HTC_SERVICE_CONNECT_RESP resp;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%X) \n", (A_UINT32)target));
+
+ do {
+
+#ifdef MBOXHW_UNIT_TEST
+
+ status = DoMboxHWTest(&target->Device);
+
+ if (status != A_OK) {
+ break;
+ }
+
+#endif
+
+ /* we should be getting 1 control message that the target is ready */
+ status = HTCWaitforControlMessage(target, &pPacket);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
+ break;
+ }
+
+ /* we controlled the buffer creation so it has to be properly aligned */
+ pRdyMsg = (HTC_READY_MSG *)pPacket->pBuffer;
+
+ if ((pRdyMsg->MessageID != HTC_MSG_READY_ID) ||
+ (pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
+ /* this message is not valid */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pRdyMsg->CreditCount == 0 || pRdyMsg->CreditSize == 0) {
+ /* this message is not valid */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ target->TargetCredits = pRdyMsg->CreditCount;
+ target->TargetCreditSize = pRdyMsg->CreditSize;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Target Ready: credits: %d credit size: %d\n",
+ target->TargetCredits, target->TargetCreditSize));
+
+ /* setup our pseudo HTC control endpoint connection */
+ A_MEMZERO(&connect,sizeof(connect));
+ A_MEMZERO(&resp,sizeof(resp));
+ connect.EpCallbacks.pContext = target;
+ connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
+ connect.EpCallbacks.EpRecv = HTCControlRecv;
+ connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */
+ connect.EpCallbacks.EpSendFull = NULL; /* not nedded */
+ connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
+ connect.ServiceID = HTC_CTRL_RSVD_SVC;
+
+ /* connect fake service */
+ status = HTCConnectService((HTC_HANDLE)target,
+ &connect,
+ &resp);
+
+ if (!A_FAILED(status)) {
+ break;
+ }
+
+ } while (FALSE);
+
+ if (pPacket != NULL) {
+ HTC_FREE_CONTROL_RX(target,pPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
+
+ return status;
+}
+
+
+
+/* Start HTC, enable interrupts and let the target know host has finished setup */
+A_STATUS HTCStart(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_PACKET *pPacket;
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
+
+ /* now that we are starting, push control receive buffers into the
+ * HTC control endpoint */
+
+ while (1) {
+ pPacket = HTC_ALLOC_CONTROL_RX(target);
+ if (NULL == pPacket) {
+ break;
+ }
+ HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
+ }
+
+ do {
+
+ AR_DEBUG_ASSERT(target->InitCredits != NULL);
+ AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
+ AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
+
+ /* call init credits callback to do the distribution ,
+ * NOTE: the first entry in the distribution list is ENDPOINT_0, so
+ * we pass the start of the list after this one. */
+ target->InitCredits(target->pCredDistContext,
+ target->EpCreditDistributionListHead->pNext,
+ target->TargetCredits);
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
+ DumpCreditDistStates(target);
+ }
+
+ /* the caller is done connecting to services, so we can indicate to the
+ * target that the setup phase is complete */
+ status = HTCSendSetupComplete(target);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* unmask interrupts */
+ status = DevUnmaskInterrupts(&target->Device);
+
+ if (A_FAILED(status)) {
+ HTCStop(target);
+ }
+
+ } while (FALSE);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
+ return status;
+}
+
+
+/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
+void HTCStop(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
+
+ /* mark that we are shutting down .. */
+ target->HTCStateFlags |= HTC_STATE_STOPPING;
+
+ /* Masking interrupts is a synchronous operation, when this function returns
+ * all pending HIF I/O has completed, we can safely flush the queues */
+ DevMaskInterrupts(&target->Device);
+
+ /* flush all send packets */
+ HTCFlushSendPkts(target);
+ /* flush all recv buffers */
+ HTCFlushRecvBuffers(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
+}
+
+/* undo what was done in HTCInit() */
+void HTCShutDown(void)
+{
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCShutDown: \n"));
+ HTCInitialized = FALSE;
+ /* undo HTCInit */
+ HIFShutDownDevice(NULL);
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCShutDown: \n"));
+}
+
+void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+
+ LOCK_HTC_TX(target);
+
+ DumpCreditDistStates(target);
+
+ UNLOCK_HTC_TX(target);
+}
+
+/* report a target failure from the device, this is a callback from the device layer
+ * which uses a mechanism to report errors from the target (i.e. special interrupts) */
+static void HTCReportFailure(void *Context)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+
+ target->TargetFailure = TRUE;
+
+ if ((target->pInstanceContext != NULL) && (HTCInitInfo.TargetFailure != NULL)) {
+ /* let upper layer know, it needs to call HTCStop() */
+ HTCInitInfo.TargetFailure(target->pInstanceContext, A_ERROR);
+ }
+}
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
+{
+ A_CHAR stream[60];
+ A_UINT32 i;
+ A_UINT16 offset, count;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<---------Dumping %d Bytes : %s ------>\n", length, pDescription));
+
+ count = 0;
+ offset = 0;
+ for(i = 0; i < length; i++) {
+ sprintf(stream + offset, "%2.2X ", buffer[i]);
+ count ++;
+ offset += 3;
+
+ if(count == 16) {
+ count = 0;
+ offset = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream));
+ A_MEMZERO(stream, 60);
+ }
+ }
+
+ if(offset != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("[H]: %s\n", stream));
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("<------------------------------------------------->\n"));
+}
+
+A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ HTC_ENDPOINT_STAT_ACTION Action,
+ HTC_ENDPOINT_STATS *pStats)
+{
+
+#ifdef HTC_EP_STAT_PROFILING
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_BOOL clearStats = FALSE;
+ A_BOOL sample = FALSE;
+
+ switch (Action) {
+ case HTC_EP_STAT_SAMPLE :
+ sample = TRUE;
+ break;
+ case HTC_EP_STAT_SAMPLE_AND_CLEAR :
+ sample = TRUE;
+ clearStats = TRUE;
+ break;
+ case HTC_EP_STAT_CLEAR :
+ clearStats = TRUE;
+ break;
+ default:
+ break;
+ }
+
+ A_ASSERT(Endpoint < ENDPOINT_MAX);
+
+ /* lock out TX and RX while we sample and/or clear */
+ LOCK_HTC_TX(target);
+ LOCK_HTC_RX(target);
+
+ if (sample) {
+ A_ASSERT(pStats != NULL);
+ /* return the stats to the caller */
+ A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+ }
+
+ if (clearStats) {
+ /* reset stats */
+ A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
+ }
+
+ UNLOCK_HTC_RX(target);
+ UNLOCK_HTC_TX(target);
+
+ return TRUE;
+#else
+ return FALSE;
+#endif
+}
--- /dev/null
+++ b/drivers/ar6000/htc/htc_debug.h
@@ -0,0 +1,65 @@
+#ifndef HTC_DEBUG_H_
+#define HTC_DEBUG_H_
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+/* ------- Debug related stuff ------- */
+enum {
+ ATH_DEBUG_SEND = 0x0001,
+ ATH_DEBUG_RECV = 0x0002,
+ ATH_DEBUG_SYNC = 0x0004,
+ ATH_DEBUG_DUMP = 0x0008,
+ ATH_DEBUG_IRQ = 0x0010,
+ ATH_DEBUG_TRC = 0x0020,
+ ATH_DEBUG_WARN = 0x0040,
+ ATH_DEBUG_ERR = 0x0080,
+ ATH_DEBUG_ANY = 0xFFFF,
+};
+
+#ifdef DEBUG
+
+// TODO FIX usage of A_PRINTF!
+#define AR_DEBUG_LVL_CHECK(lvl) (debughtc & (lvl))
+#define AR_DEBUG_PRINTBUF(buffer, length, desc) do { \
+ if (debughtc & ATH_DEBUG_DUMP) { \
+ DebugDumpBytes(buffer, length,desc); \
+ } \
+} while(0)
+#define PRINTX_ARG(arg...) arg
+#define AR_DEBUG_PRINTF(flags, args) do { \
+ if (debughtc & (flags)) { \
+ A_PRINTF(KERN_ALERT PRINTX_ARG args); \
+ } \
+} while (0)
+#define AR_DEBUG_ASSERT(test) do { \
+ if (!(test)) { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Debug Assert Caught, File %s, Line: %d, Test:%s \n",__FILE__, __LINE__,#test)); \
+ } \
+} while(0)
+extern int debughtc;
+#else
+#define AR_DEBUG_PRINTF(flags, args)
+#define AR_DEBUG_PRINTBUF(buffer, length, desc)
+#define AR_DEBUG_ASSERT(test)
+#define AR_DEBUG_LVL_CHECK(lvl) 0
+#endif
+
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+#endif /*HTC_DEBUG_H_*/
--- /dev/null
+++ b/drivers/ar6000/htc/htc_internal.h
@@ -0,0 +1,168 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _HTC_INTERNAL_H_
+#define _HTC_INTERNAL_H_
+
+/* for debugging, uncomment this to capture the last frame header, on frame header
+ * processing errors, the last frame header is dump for comparison */
+//#define HTC_CAPTURE_LAST_FRAME
+
+//#define HTC_EP_STAT_PROFILING
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "a_debug.h"
+#include "htc.h"
+#include "htc_api.h"
+#include "bmi_msg.h"
+#include "hif.h"
+#include "ar6k.h"
+
+/* HTC operational parameters */
+#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */
+#define HTC_TARGET_DEBUG_INTR_MASK 0x01
+#define HTC_TARGET_CREDIT_INTR_MASK 0xF0
+
+typedef struct _HTC_ENDPOINT {
+ HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to
+ non-zero value means this endpoint is in use */
+ HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */
+ HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */
+ HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */
+ HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */
+ int MaxTxQueueDepth; /* max depth of the TX queue before we need to
+ call driver's full handler */
+ int CurrentTxQueueDepth; /* current TX queue depth */
+ int MaxMsgLength; /* max length of endpoint message */
+#ifdef HTC_EP_STAT_PROFILING
+ HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */
+#endif
+} HTC_ENDPOINT;
+
+#ifdef HTC_EP_STAT_PROFILING
+#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
+#else
+#define INC_HTC_EP_STAT(p,stat,count)
+#endif
+
+#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL
+
+#define NUM_CONTROL_BUFFERS 8
+#define NUM_CONTROL_TX_BUFFERS 2
+#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
+
+#define HTC_CONTROL_BUFFER_SIZE (HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH)
+
+typedef struct HTC_CONTROL_BUFFER {
+ HTC_PACKET HtcPacket;
+ A_UINT8 Buffer[HTC_CONTROL_BUFFER_SIZE];
+} HTC_CONTROL_BUFFER;
+
+/* our HTC target state */
+typedef struct _HTC_TARGET {
+ HTC_ENDPOINT EndPoint[ENDPOINT_MAX];
+ HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS];
+ HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead;
+ HTC_PACKET_QUEUE ControlBufferTXFreeList;
+ HTC_PACKET_QUEUE ControlBufferRXFreeList;
+ HTC_CREDIT_DIST_CALLBACK DistributeCredits;
+ HTC_CREDIT_INIT_CALLBACK InitCredits;
+ void *pCredDistContext;
+ int TargetCredits;
+ int TargetCreditSize;
+ A_MUTEX_T HTCLock;
+ A_MUTEX_T HTCRxLock;
+ A_MUTEX_T HTCTxLock;
+ AR6K_DEVICE Device; /* AR6K - specific state */
+ A_UINT32 HTCStateFlags;
+ HTC_ENDPOINT_ID EpWaitingForBuffers;
+ A_BOOL TargetFailure;
+ void *pInstanceContext;
+#define HTC_STATE_WAIT_BUFFERS (1 << 0)
+#define HTC_STATE_STOPPING (1 << 1)
+#ifdef HTC_CAPTURE_LAST_FRAME
+ HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */
+ A_UINT8 LastTrailer[256];
+ A_UINT8 LastTrailerLength;
+#endif
+} HTC_TARGET;
+
+#define HTC_STOPPING(t) ((t)->HTCStateFlags & HTC_STATE_STOPPING)
+#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock);
+#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock);
+#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock);
+#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
+#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock);
+#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
+
+#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
+#define HTC_RECYCLE_RX_PKT(target,p) \
+{ \
+ HTC_PACKET_RESET_RX(pPacket); \
+ HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \
+}
+
+/* internal HTC functions */
+void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
+void HTCControlRecv(void *Context, HTC_PACKET *pPacket);
+A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
+HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
+void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
+A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 Flags);
+A_STATUS HTCIssueRecv(HTC_TARGET *target, HTC_PACKET *pPacket);
+void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
+A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc);
+void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
+A_STATUS HTCSendSetupComplete(HTC_TARGET *target);
+void HTCFlushRecvBuffers(HTC_TARGET *target);
+void HTCFlushSendPkts(HTC_TARGET *target);
+void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
+void DumpCreditDistStates(HTC_TARGET *target);
+void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
+
+static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
+ HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
+ if (pPacket != NULL) {
+ /* set payload pointer area with some headroom */
+ pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
+ }
+ return pPacket;
+}
+
+#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
+#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
+#define HTC_FREE_CONTROL_RX(t,p) \
+{ \
+ HTC_PACKET_RESET_RX(p); \
+ HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_INTERNAL_H_ */
--- /dev/null
+++ b/drivers/ar6000/htc/htc_recv.c
@@ -0,0 +1,703 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "htc_internal.h"
+
+#define HTCIssueRecv(t, p) \
+ DevRecvPacket(&(t)->Device, \
+ (p), \
+ (p)->ActualLength)
+
+#define DO_RCV_COMPLETION(t,p,e) \
+{ \
+ if ((p)->ActualLength > 0) { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" completing packet 0x%X (%d bytes) on ep : %d \n", \
+ (A_UINT32)(p), (p)->ActualLength, (p)->Endpoint)); \
+ (e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \
+ (p)); \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" recycling empty packet \n")); \
+ HTC_RECYCLE_RX_PKT((t), (p)); \
+ } \
+}
+
+#ifdef HTC_EP_STAT_PROFILING
+#define HTC_RX_STAT_PROFILE(t,ep,lookAhead) \
+{ \
+ LOCK_HTC_RX((t)); \
+ INC_HTC_EP_STAT((ep), RxReceived, 1); \
+ if ((lookAhead) != 0) { \
+ INC_HTC_EP_STAT((ep), RxLookAheads, 1); \
+ } \
+ UNLOCK_HTC_RX((t)); \
+}
+#else
+#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
+#endif
+
+static INLINE A_STATUS HTCProcessTrailer(HTC_TARGET *target,
+ A_UINT8 *pBuffer,
+ int Length,
+ A_UINT32 *pNextLookAhead,
+ HTC_ENDPOINT_ID FromEndpoint)
+{
+ HTC_RECORD_HDR *pRecord;
+ A_UINT8 *pRecordBuf;
+ HTC_LOOKAHEAD_REPORT *pLookAhead;
+ A_UINT8 *pOrigBuffer;
+ int origLength;
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessTrailer (length:%d) \n", Length));
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ AR_DEBUG_PRINTBUF(pBuffer,Length,"Recv Trailer");
+ }
+
+ pOrigBuffer = pBuffer;
+ origLength = Length;
+ status = A_OK;
+
+ while (Length > 0) {
+
+ if (Length < sizeof(HTC_RECORD_HDR)) {
+ status = A_EPROTO;
+ break;
+ }
+ /* these are byte aligned structs */
+ pRecord = (HTC_RECORD_HDR *)pBuffer;
+ Length -= sizeof(HTC_RECORD_HDR);
+ pBuffer += sizeof(HTC_RECORD_HDR);
+
+ if (pRecord->Length > Length) {
+ /* no room left in buffer for record */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
+ pRecord->Length, pRecord->RecordID, Length));
+ status = A_EPROTO;
+ break;
+ }
+ /* start of record follows the header */
+ pRecordBuf = pBuffer;
+
+ switch (pRecord->RecordID) {
+ case HTC_RECORD_CREDITS:
+ AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_CREDIT_REPORT));
+ HTCProcessCreditRpt(target,
+ (HTC_CREDIT_REPORT *)pRecordBuf,
+ pRecord->Length / (sizeof(HTC_CREDIT_REPORT)),
+ FromEndpoint);
+ break;
+ case HTC_RECORD_LOOKAHEAD:
+ AR_DEBUG_ASSERT(pRecord->Length >= sizeof(HTC_LOOKAHEAD_REPORT));
+ pLookAhead = (HTC_LOOKAHEAD_REPORT *)pRecordBuf;
+ if ((pLookAhead->PreValid == ((~pLookAhead->PostValid) & 0xFF)) &&
+ (pNextLookAhead != NULL)) {
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ (" LookAhead Report Found (pre valid:0x%X, post valid:0x%X) \n",
+ pLookAhead->PreValid,
+ pLookAhead->PostValid));
+
+ /* look ahead bytes are valid, copy them over */
+ ((A_UINT8 *)pNextLookAhead)[0] = pLookAhead->LookAhead[0];
+ ((A_UINT8 *)pNextLookAhead)[1] = pLookAhead->LookAhead[1];
+ ((A_UINT8 *)pNextLookAhead)[2] = pLookAhead->LookAhead[2];
+ ((A_UINT8 *)pNextLookAhead)[3] = pLookAhead->LookAhead[3];
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ DebugDumpBytes((A_UINT8 *)pNextLookAhead,4,"Next Look Ahead");
+ }
+ }
+ break;
+ default:
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" unhandled record: id:%d length:%d \n",
+ pRecord->RecordID, pRecord->Length));
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* advance buffer past this record for next time around */
+ pBuffer += pRecord->Length;
+ Length -= pRecord->Length;
+ }
+
+ if (A_FAILED(status)) {
+ DebugDumpBytes(pOrigBuffer,origLength,"BAD Recv Trailer");
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessTrailer \n"));
+ return status;
+
+}
+
+/* process a received message (i.e. strip off header, process any trailer data)
+ * note : locks must be released when this function is called */
+static A_STATUS HTCProcessRecvHeader(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT32 *pNextLookAhead)
+{
+ A_UINT8 temp;
+ A_UINT8 *pBuf;
+ A_STATUS status = A_OK;
+ A_UINT16 payloadLen;
+ A_UINT32 lookAhead;
+
+ pBuf = pPacket->pBuffer;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCProcessRecvHeader \n"));
+
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ AR_DEBUG_PRINTBUF(pBuf,pPacket->ActualLength,"HTC Recv PKT");
+ }
+
+ do {
+ /* note, we cannot assume the alignment of pBuffer, so we use the safe macros to
+ * retrieve 16 bit fields */
+ payloadLen = A_GET_UINT16_FIELD(pBuf, HTC_FRAME_HDR, PayloadLen);
+
+ ((A_UINT8 *)&lookAhead)[0] = pBuf[0];
+ ((A_UINT8 *)&lookAhead)[1] = pBuf[1];
+ ((A_UINT8 *)&lookAhead)[2] = pBuf[2];
+ ((A_UINT8 *)&lookAhead)[3] = pBuf[3];
+
+ if (lookAhead != pPacket->HTCReserved) {
+ /* somehow the lookahead that gave us the full read length did not
+ * reflect the actual header in the pending message */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCProcessRecvHeader, lookahead mismatch! \n"));
+ DebugDumpBytes((A_UINT8 *)&pPacket->HTCReserved,4,"Expected Message LookAhead");
+ DebugDumpBytes(pBuf,sizeof(HTC_FRAME_HDR),"Current Frame Header");
+#ifdef HTC_CAPTURE_LAST_FRAME
+ DebugDumpBytes((A_UINT8 *)&target->LastFrameHdr,sizeof(HTC_FRAME_HDR),"Last Frame Header");
+ if (target->LastTrailerLength != 0) {
+ DebugDumpBytes(target->LastTrailer,
+ target->LastTrailerLength,
+ "Last trailer");
+ }
+#endif
+ status = A_EPROTO;
+ break;
+ }
+
+ /* get flags */
+ temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, Flags);
+
+ if (temp & HTC_FLAGS_RECV_TRAILER) {
+ /* this packet has a trailer */
+
+ /* extract the trailer length in control byte 0 */
+ temp = A_GET_UINT8_FIELD(pBuf, HTC_FRAME_HDR, ControlBytes[0]);
+
+ if ((temp < sizeof(HTC_RECORD_HDR)) || (temp > payloadLen)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCProcessRecvHeader, invalid header (payloadlength should be :%d, CB[0] is:%d) \n",
+ payloadLen, temp));
+ status = A_EPROTO;
+ break;
+ }
+
+ /* process trailer data that follows HDR + application payload */
+ status = HTCProcessTrailer(target,
+ (pBuf + HTC_HDR_LENGTH + payloadLen - temp),
+ temp,
+ pNextLookAhead,
+ pPacket->Endpoint);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+#ifdef HTC_CAPTURE_LAST_FRAME
+ A_MEMCPY(target->LastTrailer, (pBuf + HTC_HDR_LENGTH + payloadLen - temp), temp);
+ target->LastTrailerLength = temp;
+#endif
+ /* trim length by trailer bytes */
+ pPacket->ActualLength -= temp;
+ }
+#ifdef HTC_CAPTURE_LAST_FRAME
+ else {
+ target->LastTrailerLength = 0;
+ }
+#endif
+
+ /* if we get to this point, the packet is good */
+ /* remove header and adjust length */
+ pPacket->pBuffer += HTC_HDR_LENGTH;
+ pPacket->ActualLength -= HTC_HDR_LENGTH;
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ /* dump the whole packet */
+ DebugDumpBytes(pBuf,pPacket->ActualLength,"BAD HTC Recv PKT");
+ } else {
+#ifdef HTC_CAPTURE_LAST_FRAME
+ A_MEMCPY(&target->LastFrameHdr,pBuf,sizeof(HTC_FRAME_HDR));
+#endif
+ if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
+ if (pPacket->ActualLength > 0) {
+ AR_DEBUG_PRINTBUF(pPacket->pBuffer,pPacket->ActualLength,"HTC - Application Msg");
+ }
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCProcessRecvHeader \n"));
+ return status;
+}
+
+/* asynchronous completion handler for recv packet fetching, when the device layer
+ * completes a read request, it will call this completion handler */
+void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+ HTC_ENDPOINT *pEndpoint;
+ A_UINT32 nextLookAhead = 0;
+ A_STATUS status;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("+HTCRecvCompleteHandler (status:%d, ep:%d) \n",
+ pPacket->Status, pPacket->Endpoint));
+
+ AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+ pEndpoint = &target->EndPoint[pPacket->Endpoint];
+ pPacket->Completion = NULL;
+
+ /* get completion status */
+ status = pPacket->Status;
+
+ do {
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("HTCRecvCompleteHandler: request failed (status:%d, ep:%d) \n",
+ pPacket->Status, pPacket->Endpoint));
+ break;
+ }
+ /* process the header for any trailer data */
+ status = HTCProcessRecvHeader(target,pPacket,&nextLookAhead);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* was there a lookahead for the next packet? */
+ if (nextLookAhead != 0) {
+ A_STATUS nextStatus;
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTCRecvCompleteHandler - next look ahead was non-zero : 0x%X \n",
+ nextLookAhead));
+ /* we have another packet, get the next packet fetch started (pipelined) before
+ * we call into the endpoint's callback, this will start another async request */
+ nextStatus = HTCRecvMessagePendingHandler(target,nextLookAhead,NULL);
+ if (A_EPROTO == nextStatus) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Next look ahead from recv header was INVALID\n"));
+ DebugDumpBytes((A_UINT8 *)&nextLookAhead,
+ 4,
+ "BAD lookahead from lookahead report");
+ }
+ } else {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTCRecvCompleteHandler - rechecking for more messages...\n"));
+ /* if we did not get anything on the look-ahead,
+ * call device layer to asynchronously re-check for messages. If we can keep the async
+ * processing going we get better performance. If there is a pending message we will keep processing
+ * messages asynchronously which should pipeline things nicely */
+ DevCheckPendingRecvMsgsAsync(&target->Device);
+ }
+
+ HTC_RX_STAT_PROFILE(target,pEndpoint,nextLookAhead);
+ DO_RCV_COMPLETION(target,pPacket,pEndpoint);
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCRecvCompleteHandler , message fetch failed (status = %d) \n",
+ status));
+ /* recyle this packet */
+ HTC_RECYCLE_RX_PKT(target, pPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-HTCRecvCompleteHandler\n"));
+}
+
+/* synchronously wait for a control message from the target,
+ * This function is used at initialization time ONLY. At init messages
+ * on ENDPOINT 0 are expected. */
+A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket)
+{
+ A_STATUS status;
+ A_UINT32 lookAhead;
+ HTC_PACKET *pPacket = NULL;
+ HTC_FRAME_HDR *pHdr;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCWaitforControlMessage \n"));
+
+ do {
+
+ *ppControlPacket = NULL;
+
+ /* call the polling function to see if we have a message */
+ status = DevPollMboxMsgRecv(&target->Device,
+ &lookAhead,
+ HTC_TARGET_RESPONSE_TIMEOUT);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
+ ("HTCWaitforControlMessage : lookAhead : 0x%X \n", lookAhead));
+
+ /* check the lookahead */
+ pHdr = (HTC_FRAME_HDR *)&lookAhead;
+
+ if (pHdr->EndpointID != ENDPOINT_0) {
+ /* unexpected endpoint number, should be zero */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ if (A_FAILED(status)) {
+ /* bad message */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ pPacket = HTC_ALLOC_CONTROL_RX(target);
+
+ if (pPacket == NULL) {
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ pPacket->HTCReserved = lookAhead;
+ pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+
+ if (pPacket->ActualLength > pPacket->BufferLength) {
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ /* we want synchronous operation */
+ pPacket->Completion = NULL;
+
+ /* get the message from the device, this will block */
+ status = HTCIssueRecv(target, pPacket);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* process receive header */
+ status = HTCProcessRecvHeader(target,pPacket,NULL);
+
+ pPacket->Status = status;
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCWaitforControlMessage, HTCProcessRecvHeader failed (status = %d) \n",
+ status));
+ break;
+ }
+
+ /* give the caller this control message packet, they are responsible to free */
+ *ppControlPacket = pPacket;
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ if (pPacket != NULL) {
+ /* cleanup buffer on error */
+ HTC_FREE_CONTROL_RX(target,pPacket);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCWaitforControlMessage \n"));
+
+ return status;
+}
+
+/* callback when device layer or lookahead report parsing detects a pending message */
+A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 LookAhead, A_BOOL *pAsyncProc)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+ A_STATUS status = A_OK;
+ HTC_PACKET *pPacket = NULL;
+ HTC_FRAME_HDR *pHdr;
+ HTC_ENDPOINT *pEndpoint;
+ A_BOOL asyncProc = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+HTCRecvMessagePendingHandler LookAhead:0x%X \n",LookAhead));
+
+ if (IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(&target->Device)) {
+ /* We use async mode to get the packets if the device layer supports it.
+ * The device layer interfaces with HIF in which HIF may have restrictions on
+ * how interrupts are processed */
+ asyncProc = TRUE;
+ }
+
+ if (pAsyncProc != NULL) {
+ /* indicate to caller how we decided to process this */
+ *pAsyncProc = asyncProc;
+ }
+
+ while (TRUE) {
+
+ pHdr = (HTC_FRAME_HDR *)&LookAhead;
+
+ if (pHdr->EndpointID >= ENDPOINT_MAX) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Invalid Endpoint in look-ahead: %d \n",pHdr->EndpointID));
+ /* invalid endpoint */
+ status = A_EPROTO;
+ break;
+ }
+
+ if (pHdr->PayloadLen > HTC_MAX_PAYLOAD_LENGTH) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Payload length %d exceeds max HTC : %d !\n",
+ pHdr->PayloadLen, HTC_MAX_PAYLOAD_LENGTH));
+ status = A_EPROTO;
+ break;
+ }
+
+ pEndpoint = &target->EndPoint[pHdr->EndpointID];
+
+ if (0 == pEndpoint->ServiceID) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Endpoint %d is not connected !\n",pHdr->EndpointID));
+ /* endpoint isn't even connected */
+ status = A_EPROTO;
+ break;
+ }
+
+ /* lock RX to get a buffer */
+ LOCK_HTC_RX(target);
+
+ /* get a packet from the endpoint recv queue */
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+
+ if (NULL == pPacket) {
+ /* check for refill handler */
+ if (pEndpoint->EpCallBacks.EpRecvRefill != NULL) {
+ UNLOCK_HTC_RX(target);
+ /* call the re-fill handler */
+ pEndpoint->EpCallBacks.EpRecvRefill(pEndpoint->EpCallBacks.pContext,
+ pHdr->EndpointID);
+ LOCK_HTC_RX(target);
+ /* check if we have more buffers */
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+ /* fall through */
+ }
+ }
+
+ if (NULL == pPacket) {
+ /* this is not an error, we simply need to mark that we are waiting for buffers.*/
+ target->HTCStateFlags |= HTC_STATE_WAIT_BUFFERS;
+ target->EpWaitingForBuffers = pHdr->EndpointID;
+ status = A_NO_MEMORY;
+ }
+
+ UNLOCK_HTC_RX(target);
+
+ if (A_FAILED(status)) {
+ /* no buffers */
+ break;
+ }
+
+ AR_DEBUG_ASSERT(pPacket->Endpoint == pHdr->EndpointID);
+
+ /* make sure this message can fit in the endpoint buffer */
+ if ((pHdr->PayloadLen + HTC_HDR_LENGTH) > pPacket->BufferLength) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Payload Length Error : header reports payload of: %d, endpoint buffer size: %d \n",
+ pHdr->PayloadLen, pPacket->BufferLength));
+ status = A_EPROTO;
+ break;
+ }
+
+ pPacket->HTCReserved = LookAhead; /* set expected look ahead */
+ /* set the amount of data to fetch */
+ pPacket->ActualLength = pHdr->PayloadLen + HTC_HDR_LENGTH;
+
+ if (asyncProc) {
+ /* we use async mode to get the packet if the device layer supports it
+ * set our callback and context */
+ pPacket->Completion = HTCRecvCompleteHandler;
+ pPacket->pContext = target;
+ } else {
+ /* fully synchronous */
+ pPacket->Completion = NULL;
+ }
+
+ /* go fetch the packet */
+ status = HTCIssueRecv(target, pPacket);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ if (asyncProc) {
+ /* we did this asynchronously so we can get out of the loop, the asynch processing
+ * creates a chain of requests to continue processing pending messages in the
+ * context of callbacks */
+ break;
+ }
+
+ /* in the sync case, we process the packet, check lookaheads and then repeat */
+
+ LookAhead = 0;
+ status = HTCProcessRecvHeader(target,pPacket,&LookAhead);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ HTC_RX_STAT_PROFILE(target,pEndpoint,LookAhead);
+ DO_RCV_COMPLETION(target,pPacket,pEndpoint);
+
+ pPacket = NULL;
+
+ if (0 == LookAhead) {
+ break;
+ }
+
+ }
+
+ if (A_NO_MEMORY == status) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Endpoint :%d has no buffers, blocking receiver to prevent overrun.. \n",
+ pHdr->EndpointID));
+ /* try to stop receive at the device layer */
+ DevStopRecv(&target->Device, asyncProc ? DEV_STOP_RECV_ASYNC : DEV_STOP_RECV_SYNC);
+ status = A_OK;
+ } else if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Failed to get pending message : LookAhead Value: 0x%X (status = %d) \n",
+ LookAhead, status));
+ if (pPacket != NULL) {
+ /* clean up packet on error */
+ HTC_RECYCLE_RX_PKT(target, pPacket);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-HTCRecvMessagePendingHandler \n"));
+
+ return status;
+}
+
+/* Makes a buffer available to the HTC module */
+A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint;
+ A_BOOL unblockRecv = FALSE;
+ A_STATUS status = A_OK;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("+- HTCAddReceivePkt: endPointId: %d, buffer: 0x%X, length: %d\n",
+ pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->BufferLength));
+
+ do {
+
+ if (HTC_STOPPING(target)) {
+ status = A_ECANCELED;
+ break;
+ }
+
+ AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
+
+ pEndpoint = &target->EndPoint[pPacket->Endpoint];
+
+ LOCK_HTC_RX(target);
+
+ /* store receive packet */
+ HTC_PACKET_ENQUEUE(&pEndpoint->RxBuffers, pPacket);
+
+ /* check if we are blocked waiting for a new buffer */
+ if (target->HTCStateFlags & HTC_STATE_WAIT_BUFFERS) {
+ if (target->EpWaitingForBuffers == pPacket->Endpoint) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" receiver was blocked on ep:%d, unblocking.. \n",
+ target->EpWaitingForBuffers));
+ target->HTCStateFlags &= ~HTC_STATE_WAIT_BUFFERS;
+ target->EpWaitingForBuffers = ENDPOINT_MAX;
+ unblockRecv = TRUE;
+ }
+ }
+
+ UNLOCK_HTC_RX(target);
+
+ if (unblockRecv && !HTC_STOPPING(target)) {
+ /* TODO : implement a buffer threshold count? */
+ DevEnableRecv(&target->Device,DEV_ENABLE_RECV_SYNC);
+ }
+
+ } while (FALSE);
+
+ return status;
+}
+
+static void HTCFlushEndpointRX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
+{
+ HTC_PACKET *pPacket;
+
+ LOCK_HTC_RX(target);
+
+ while (1) {
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->RxBuffers);
+ if (NULL == pPacket) {
+ break;
+ }
+ UNLOCK_HTC_RX(target);
+ pPacket->Status = A_ECANCELED;
+ pPacket->ActualLength = 0;
+ AR_DEBUG_PRINTF(ATH_DEBUG_RECV, (" Flushing RX packet:0x%X, length:%d, ep:%d \n",
+ (A_UINT32)pPacket, pPacket->BufferLength, pPacket->Endpoint));
+ /* give the packet back */
+ pEndpoint->EpCallBacks.EpRecv(pEndpoint->EpCallBacks.pContext,
+ pPacket);
+ LOCK_HTC_RX(target);
+ }
+
+ UNLOCK_HTC_RX(target);
+
+
+}
+
+void HTCFlushRecvBuffers(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ int i;
+
+ /* NOTE: no need to flush endpoint 0, these buffers were
+ * allocated as part of the HTC struct */
+ for (i = ENDPOINT_1; i < ENDPOINT_MAX; i++) {
+ pEndpoint = &target->EndPoint[i];
+ if (pEndpoint->ServiceID == 0) {
+ /* not in use.. */
+ continue;
+ }
+ HTCFlushEndpointRX(target,pEndpoint);
+ }
+
+
+}
+
+
--- /dev/null
+++ b/drivers/ar6000/htc/htc_send.c
@@ -0,0 +1,543 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "htc_internal.h"
+
+#define DO_EP_TX_COMPLETION(ep,p) \
+{ \
+ (p)->Completion = NULL; \
+ (ep)->EpCallBacks.EpTxComplete((ep)->EpCallBacks.pContext,(p)); \
+}
+
+
+/* call the distribute credits callback with the distribution */
+#define DO_DISTRIBUTION(t,reason,description,pList) \
+{ \
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, \
+ (" calling distribute function (%s) (dfn:0x%X, ctxt:0x%X, dist:0x%X) \n", \
+ (description), \
+ (A_UINT32)(t)->DistributeCredits, \
+ (A_UINT32)(t)->pCredDistContext, \
+ (A_UINT32)pList)); \
+ (t)->DistributeCredits((t)->pCredDistContext, \
+ (pList), \
+ (reason)); \
+}
+
+/* our internal send packet completion handler when packets are submited to the AR6K device
+ * layer */
+static void HTCSendPktCompletionHandler(void *Context, HTC_PACKET *pPacket)
+{
+ HTC_TARGET *target = (HTC_TARGET *)Context;
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[pPacket->Endpoint];
+
+
+ if (A_FAILED(pPacket->Status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCSendPktCompletionHandler: request failed (status:%d, ep:%d) \n",
+ pPacket->Status, pPacket->Endpoint));
+ }
+ /* first, fixup the head room we allocated */
+ pPacket->pBuffer += HTC_HDR_LENGTH;
+ /* do completion */
+ DO_EP_TX_COMPLETION(pEndpoint,pPacket);
+}
+
+A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket, A_UINT8 SendFlags)
+{
+ A_STATUS status;
+ A_UINT8 *pHdrBuf;
+ A_BOOL sync = FALSE;
+
+ /* caller always provides headrooom */
+ pPacket->pBuffer -= HTC_HDR_LENGTH;
+ pHdrBuf = pPacket->pBuffer;
+ /* setup frame header */
+ A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)pPacket->ActualLength);
+ A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,SendFlags);
+ A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)pPacket->Endpoint);
+
+ if (pPacket->Completion == NULL) {
+ /* mark that this request was synchronously issued */
+ sync = TRUE;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("+-HTCIssueSend: transmit length : %d (%s) \n",
+ pPacket->ActualLength + HTC_HDR_LENGTH,
+ sync ? "SYNC" : "ASYNC" ));
+
+ /* send message to device */
+ status = DevSendPacket(&target->Device,
+ pPacket,
+ pPacket->ActualLength + HTC_HDR_LENGTH);
+
+ if (sync) {
+ /* use local sync variable. If this was issued asynchronously, pPacket is no longer
+ * safe to access. */
+ pPacket->pBuffer += HTC_HDR_LENGTH;
+ }
+
+ /* if this request was asynchronous, the packet completion routine will be invoked by
+ * the device layer when the HIF layer completes the request */
+
+ return status;
+}
+
+/* try to send the current packet or a packet at the head of the TX queue,
+ * if there are no credits, the packet remains in the queue.
+ * this function always succeeds and returns a flag if the TX queue for
+ * the endpoint has hit the set limit */
+static A_BOOL HTCTrySend(HTC_TARGET *target,
+ HTC_ENDPOINT *pEndpoint,
+ HTC_PACKET *pPacketToSend)
+{
+ HTC_PACKET *pPacket;
+ int creditsRequired;
+ int remainder;
+ A_UINT8 sendFlags;
+ A_BOOL epFull = FALSE;
+
+ LOCK_HTC_TX(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+HTCTrySend (pPkt:0x%X)\n",(A_UINT32)pPacketToSend));
+
+ if (pPacketToSend != NULL) {
+ /* caller supplied us a packet to queue to the tail of the HTC TX queue before
+ * we check the tx queue */
+ HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue,pPacketToSend);
+ pEndpoint->CurrentTxQueueDepth++;
+ }
+
+ /* now drain the TX queue for transmission as long as we have enough
+ * credits */
+
+ while (1) {
+
+ if (HTC_QUEUE_EMPTY(&pEndpoint->TxQueue)) {
+ /* nothing in the queue */
+ break;
+ }
+
+ sendFlags = 0;
+
+ /* get packet at head, but don't remove it */
+ pPacket = HTC_GET_PKT_AT_HEAD(&pEndpoint->TxQueue);
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Got head packet:0x%X , Queue Depth: %d\n",
+ (A_UINT32)pPacket, pEndpoint->CurrentTxQueueDepth));
+
+ /* figure out how many credits this message requires */
+ creditsRequired = (pPacket->ActualLength + HTC_HDR_LENGTH) / target->TargetCreditSize;
+ remainder = (pPacket->ActualLength + HTC_HDR_LENGTH) % target->TargetCreditSize;
+
+ if (remainder) {
+ creditsRequired++;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Creds Required:%d Got:%d\n",
+ creditsRequired, pEndpoint->CreditDist.TxCredits));
+
+ if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+
+ /* not enough credits */
+
+ if (pPacket->Endpoint == ENDPOINT_0) {
+ /* leave it in the queue */
+ break;
+ }
+ /* invoke the registered distribution function only if this is not
+ * endpoint 0, we let the driver layer provide more credits if it can.
+ * We pass the credit distribution list starting at the endpoint in question
+ * */
+
+ /* set how many credits we need */
+ pEndpoint->CreditDist.TxCreditsSeek =
+ creditsRequired - pEndpoint->CreditDist.TxCredits;
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_SEEK_CREDITS,
+ "Seek Credits",
+ &pEndpoint->CreditDist);
+
+ pEndpoint->CreditDist.TxCreditsSeek = 0;
+
+ if (pEndpoint->CreditDist.TxCredits < creditsRequired) {
+ /* still not enough credits to send, leave packet in the queue */
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ (" Not enough credits for ep %d leaving packet in queue..\n",
+ pPacket->Endpoint));
+ break;
+ }
+
+ }
+
+ pEndpoint->CreditDist.TxCredits -= creditsRequired;
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed, creditsRequired);
+
+ /* check if we need credits */
+ if (pEndpoint->CreditDist.TxCredits < pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+ sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
+ INC_HTC_EP_STAT(pEndpoint, TxCreditLowIndications, 1);
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,(" Host Needs Credits \n"));
+ }
+
+ /* now we can fully dequeue */
+ pPacket = HTC_PACKET_DEQUEUE(&pEndpoint->TxQueue);
+ pEndpoint->CurrentTxQueueDepth--;
+
+ INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
+
+ UNLOCK_HTC_TX(target);
+
+ HTCIssueSend(target, pPacket, sendFlags);
+
+ LOCK_HTC_TX(target);
+
+ /* go back and check for more messages */
+ }
+
+ if (pEndpoint->CurrentTxQueueDepth >= pEndpoint->MaxTxQueueDepth) {
+ /* let caller know that this endpoint has reached the maximum depth */
+ epFull = TRUE;
+ }
+
+ UNLOCK_HTC_TX(target);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-HTCTrySend: \n"));
+ return epFull;
+}
+
+/* HTC API - HTCSendPkt */
+A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint;
+ HTC_ENDPOINT_ID ep;
+ A_STATUS status = A_OK;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
+ ("+HTCSendPkt: Enter endPointId: %d, buffer: 0x%X, length: %d \n",
+ pPacket->Endpoint, (A_UINT32)pPacket->pBuffer, pPacket->ActualLength));
+
+ ep = pPacket->Endpoint;
+ AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
+ pEndpoint = &target->EndPoint[ep];
+
+ do {
+
+ if (HTC_STOPPING(target)) {
+ status = A_ECANCELED;
+ pPacket->Status = status;
+ DO_EP_TX_COMPLETION(pEndpoint,pPacket);
+ break;
+ }
+ /* everything sent through this interface is asynchronous */
+ /* fill in HTC completion routines */
+ pPacket->Completion = HTCSendPktCompletionHandler;
+ pPacket->pContext = target;
+
+ if (HTCTrySend(target, pEndpoint, pPacket)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d, TX queue is full, Depth:%d, Max:%d \n",
+ ep, pEndpoint->CurrentTxQueueDepth, pEndpoint->MaxTxQueueDepth));
+ /* queue is now full, let caller know */
+ if (pEndpoint->EpCallBacks.EpSendFull != NULL) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Calling driver's send full callback.... \n"));
+ pEndpoint->EpCallBacks.EpSendFull(pEndpoint->EpCallBacks.pContext,
+ ep);
+ }
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCSendPkt \n"));
+ } while (FALSE);
+
+ return status;
+}
+
+
+/* check TX queues to drain because of credit distribution update */
+static INLINE void HTCCheckEndpointTxQueues(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ HTC_ENDPOINT_CREDIT_DIST *pDistItem;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCCheckEndpointTxQueues \n"));
+ pDistItem = target->EpCreditDistributionListHead;
+
+ /* run through the credit distribution list to see
+ * if there are packets queued
+ * NOTE: no locks need to be taken since the distribution list
+ * is not dynamic (cannot be re-ordered) and we are not modifying any state */
+ while (pDistItem != NULL) {
+ pEndpoint = (HTC_ENDPOINT *)pDistItem->pHTCReserved;
+
+ if (pEndpoint->CurrentTxQueueDepth > 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Ep %d has %d credits and %d Packets in TX Queue \n",
+ pDistItem->Endpoint, pEndpoint->CreditDist.TxCredits, pEndpoint->CurrentTxQueueDepth));
+ /* try to start the stalled queue, this list is ordered by priority.
+ * Highest priority queue get's processed first, if there are credits available the
+ * highest priority queue will get a chance to reclaim credits from lower priority
+ * ones */
+ HTCTrySend(target, pEndpoint, NULL);
+ }
+
+ pDistItem = pDistItem->pNext;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCCheckEndpointTxQueues \n"));
+}
+
+/* process credit reports and call distribution function */
+void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
+{
+ int i;
+ HTC_ENDPOINT *pEndpoint;
+ int totalCredits = 0;
+ A_BOOL doDist = FALSE;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+HTCProcessCreditRpt, Credit Report Entries:%d \n", NumEntries));
+
+ /* lock out TX while we update credits */
+ LOCK_HTC_TX(target);
+
+ for (i = 0; i < NumEntries; i++, pRpt++) {
+ if (pRpt->EndpointID >= ENDPOINT_MAX) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ pEndpoint = &target->EndPoint[pRpt->EndpointID];
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n",
+ pRpt->EndpointID, pRpt->Credits));
+
+
+#ifdef HTC_EP_STAT_PROFILING
+
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
+
+ if (FromEndpoint == pRpt->EndpointID) {
+ /* this credit report arrived on the same endpoint indicating it arrived in an RX
+ * packet */
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx, pRpt->Credits);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
+ } else if (FromEndpoint == ENDPOINT_0) {
+ /* this credit arrived on endpoint 0 as a NULL message */
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0, pRpt->Credits);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
+ } else {
+ /* arrived on another endpoint */
+ INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther, pRpt->Credits);
+ INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
+ }
+
+#endif
+
+ if (ENDPOINT_0 == pRpt->EndpointID) {
+ /* always give endpoint 0 credits back */
+ pEndpoint->CreditDist.TxCredits += pRpt->Credits;
+ } else {
+ /* for all other endpoints, update credits to distribute, the distribution function
+ * will handle giving out credits back to the endpoints */
+ pEndpoint->CreditDist.TxCreditsToDist += pRpt->Credits;
+ /* flag that we have to do the distribution */
+ doDist = TRUE;
+ }
+
+ totalCredits += pRpt->Credits;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Report indicated %d credits to distribute \n", totalCredits));
+
+ if (doDist) {
+ /* this was a credit return based on a completed send operations
+ * note, this is done with the lock held */
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_SEND_COMPLETE,
+ "Send Complete",
+ target->EpCreditDistributionListHead->pNext);
+ }
+
+ UNLOCK_HTC_TX(target);
+
+ if (totalCredits) {
+ HTCCheckEndpointTxQueues(target);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-HTCProcessCreditRpt \n"));
+}
+
+/* flush endpoint TX queue */
+static void HTCFlushEndpointTX(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint, HTC_TX_TAG Tag)
+{
+ HTC_PACKET *pPacket;
+ HTC_PACKET_QUEUE discardQueue;
+
+ /* initialize the discard queue */
+ INIT_HTC_PACKET_QUEUE(&discardQueue);
+
+ LOCK_HTC_TX(target);
+
+ /* interate from the front of the TX queue and flush out packets */
+ ITERATE_OVER_LIST_ALLOW_REMOVE(&pEndpoint->TxQueue, pPacket, HTC_PACKET, ListLink) {
+
+ /* check for removal */
+ if ((HTC_TX_PACKET_TAG_ALL == Tag) || (Tag == pPacket->PktInfo.AsTx.Tag)) {
+ /* remove from queue */
+ HTC_PACKET_REMOVE(pPacket);
+ /* add it to the discard pile */
+ HTC_PACKET_ENQUEUE(&discardQueue, pPacket);
+ pEndpoint->CurrentTxQueueDepth--;
+ }
+
+ } ITERATE_END;
+
+ UNLOCK_HTC_TX(target);
+
+ /* empty the discard queue */
+ while (1) {
+ pPacket = HTC_PACKET_DEQUEUE(&discardQueue);
+ if (NULL == pPacket) {
+ break;
+ }
+ pPacket->Status = A_ECANCELED;
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, (" Flushing TX packet:0x%X, length:%d, ep:%d tag:0x%X \n",
+ (A_UINT32)pPacket, pPacket->ActualLength, pPacket->Endpoint, pPacket->PktInfo.AsTx.Tag));
+ DO_EP_TX_COMPLETION(pEndpoint,pPacket);
+ }
+
+}
+
+void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+#ifdef DEBUG
+ HTC_ENDPOINT *pEndpoint = (HTC_ENDPOINT *)pEPDist->pHTCReserved;
+#endif
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("--- EP : %d ServiceID: 0x%X --------------\n",
+ pEPDist->Endpoint, pEPDist->ServiceID));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" this:0x%X next:0x%X prev:0x%X\n",
+ (A_UINT32)pEPDist, (A_UINT32)pEPDist->pNext, (A_UINT32)pEPDist->pPrev));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" DistFlags : 0x%X \n", pEPDist->DistFlags));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsNorm : %d \n", pEPDist->TxCreditsNorm));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsMin : %d \n", pEPDist->TxCreditsMin));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCredits : %d \n", pEPDist->TxCredits));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsAssigned : %d \n", pEPDist->TxCreditsAssigned));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsSeek : %d \n", pEPDist->TxCreditsSeek));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditSize : %d \n", pEPDist->TxCreditSize));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsPerMaxMsg : %d \n", pEPDist->TxCreditsPerMaxMsg));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxCreditsToDist : %d \n", pEPDist->TxCreditsToDist));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, (" TxQueueDepth : %d \n", pEndpoint->CurrentTxQueueDepth));
+ AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("----------------------------------------------------\n"));
+}
+
+void DumpCreditDistStates(HTC_TARGET *target)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pEPList = target->EpCreditDistributionListHead;
+
+ while (pEPList != NULL) {
+ DumpCreditDist(pEPList);
+ pEPList = pEPList->pNext;
+ }
+
+ if (target->DistributeCredits != NULL) {
+ DO_DISTRIBUTION(target,
+ HTC_DUMP_CREDIT_STATE,
+ "Dump State",
+ NULL);
+ }
+}
+
+/* flush all send packets from all endpoint queues */
+void HTCFlushSendPkts(HTC_TARGET *target)
+{
+ HTC_ENDPOINT *pEndpoint;
+ int i;
+
+ DumpCreditDistStates(target);
+
+ for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
+ pEndpoint = &target->EndPoint[i];
+ if (pEndpoint->ServiceID == 0) {
+ /* not in use.. */
+ continue;
+ }
+ HTCFlushEndpointTX(target,pEndpoint,HTC_TX_PACKET_TAG_ALL);
+ }
+
+
+}
+
+/* HTC API to flush an endpoint's TX queue*/
+void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint];
+
+ if (pEndpoint->ServiceID == 0) {
+ AR_DEBUG_ASSERT(FALSE);
+ /* not in use.. */
+ return;
+ }
+
+ HTCFlushEndpointTX(target, pEndpoint, Tag);
+}
+
+/* HTC API to indicate activity to the credit distribution function */
+void HTCIndicateActivityChange(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ A_BOOL Active)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ HTC_ENDPOINT *pEndpoint = &target->EndPoint[Endpoint];
+ A_BOOL doDist = FALSE;
+
+ if (pEndpoint->ServiceID == 0) {
+ AR_DEBUG_ASSERT(FALSE);
+ /* not in use.. */
+ return;
+ }
+
+ LOCK_HTC_TX(target);
+
+ if (Active) {
+ if (!(pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE)) {
+ /* mark active now */
+ pEndpoint->CreditDist.DistFlags |= HTC_EP_ACTIVE;
+ doDist = TRUE;
+ }
+ } else {
+ if (pEndpoint->CreditDist.DistFlags & HTC_EP_ACTIVE) {
+ /* mark inactive now */
+ pEndpoint->CreditDist.DistFlags &= ~HTC_EP_ACTIVE;
+ doDist = TRUE;
+ }
+ }
+
+ if (doDist) {
+ /* do distribution again based on activity change
+ * note, this is done with the lock held */
+ DO_DISTRIBUTION(target,
+ HTC_CREDIT_DIST_ACTIVITY_CHANGE,
+ "Activity Change",
+ target->EpCreditDistributionListHead->pNext);
+ }
+
+ UNLOCK_HTC_TX(target);
+
+}
--- /dev/null
+++ b/drivers/ar6000/htc/htc_services.c
@@ -0,0 +1,403 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "htc_internal.h"
+
+void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
+{
+ /* not implemented
+ * we do not send control TX frames during normal runtime, only during setup */
+ AR_DEBUG_ASSERT(FALSE);
+}
+
+ /* callback when a control message arrives on this endpoint */
+void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
+{
+ AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
+
+ /* the only control messages we are expecting are NULL messages (credit resports), which should
+ * never get here */
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("HTCControlRecv, got message with length:%d \n",
+ pPacket->ActualLength + HTC_HDR_LENGTH));
+
+ /* dump header and message */
+ DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
+ pPacket->ActualLength + HTC_HDR_LENGTH,
+ "Unexpected ENDPOINT 0 Message");
+
+ HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket);
+}
+
+A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
+{
+ HTC_PACKET *pSendPacket = NULL;
+ A_STATUS status;
+ HTC_SETUP_COMPLETE_MSG *pSetupComplete;
+
+ do {
+ /* allocate a packet to send to the target */
+ pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+ if (NULL == pSendPacket) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ /* assemble setup complete message */
+ pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
+ A_MEMZERO(pSetupComplete,sizeof(HTC_SETUP_COMPLETE_MSG));
+ pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;
+
+ SET_HTC_PACKET_INFO_TX(pSendPacket,
+ NULL,
+ (A_UINT8 *)pSetupComplete,
+ sizeof(HTC_SETUP_COMPLETE_MSG),
+ ENDPOINT_0,
+ HTC_SERVICE_TX_PACKET_TAG);
+
+ /* we want synchronous operation */
+ pSendPacket->Completion = NULL;
+ /* send the message */
+ status = HTCIssueSend(target,pSendPacket,0);
+
+ } while (FALSE);
+
+ if (pSendPacket != NULL) {
+ HTC_FREE_CONTROL_TX(target,pSendPacket);
+ }
+
+ return status;
+}
+
+
+A_STATUS HTCConnectService(HTC_HANDLE HTCHandle,
+ HTC_SERVICE_CONNECT_REQ *pConnectReq,
+ HTC_SERVICE_CONNECT_RESP *pConnectResp)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ A_STATUS status = A_OK;
+ HTC_PACKET *pRecvPacket = NULL;
+ HTC_PACKET *pSendPacket = NULL;
+ HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg;
+ HTC_CONNECT_SERVICE_MSG *pConnectMsg;
+ HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX;
+ HTC_ENDPOINT *pEndpoint;
+ int maxMsgSize = 0;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%X SvcID:0x%X \n",
+ (A_UINT32)target, pConnectReq->ServiceID));
+
+ do {
+
+ AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
+
+ if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
+ /* special case for pseudo control service */
+ assignedEndpoint = ENDPOINT_0;
+ maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
+ } else {
+ /* allocate a packet to send to the target */
+ pSendPacket = HTC_ALLOC_CONTROL_TX(target);
+
+ if (NULL == pSendPacket) {
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_NO_MEMORY;
+ break;
+ }
+ /* assemble connect service message */
+ pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
+ AR_DEBUG_ASSERT(pConnectMsg != NULL);
+ A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
+ pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
+ pConnectMsg->ServiceID = pConnectReq->ServiceID;
+ pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
+ /* check caller if it wants to transfer meta data */
+ if ((pConnectReq->pMetaData != NULL) &&
+ (pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+ /* copy meta data into message buffer (after header ) */
+ A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
+ pConnectReq->pMetaData,
+ pConnectReq->MetaDataLength);
+ pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
+ }
+
+ SET_HTC_PACKET_INFO_TX(pSendPacket,
+ NULL,
+ (A_UINT8 *)pConnectMsg,
+ sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
+ ENDPOINT_0,
+ HTC_SERVICE_TX_PACKET_TAG);
+
+ /* we want synchronous operation */
+ pSendPacket->Completion = NULL;
+
+ status = HTCIssueSend(target,pSendPacket,0);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /* wait for response */
+ status = HTCWaitforControlMessage(target, &pRecvPacket);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* we controlled the buffer creation so it has to be properly aligned */
+ pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
+
+ if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
+ (pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
+ /* this message is not valid */
+ AR_DEBUG_ASSERT(FALSE);
+ status = A_EPROTO;
+ break;
+ }
+
+ pConnectResp->ConnectRespCode = pResponseMsg->Status;
+ /* check response status */
+ if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ (" Target failed service 0x%X connect request (status:%d)\n",
+ pResponseMsg->ServiceID, pResponseMsg->Status));
+ status = A_EPROTO;
+ break;
+ }
+
+ assignedEndpoint = pResponseMsg->EndpointID;
+ maxMsgSize = pResponseMsg->MaxMsgSize;
+
+ if ((pConnectResp->pMetaData != NULL) &&
+ (pResponseMsg->ServiceMetaLength > 0) &&
+ (pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
+ /* caller supplied a buffer and the target responded with data */
+ int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
+ /* copy the meta data */
+ A_MEMCPY(pConnectResp->pMetaData,
+ ((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
+ copyLength);
+ pConnectResp->ActualLength = copyLength;
+ }
+
+ }
+
+ /* the rest of these are parameter checks so set the error status */
+ status = A_EPROTO;
+
+ if (assignedEndpoint >= ENDPOINT_MAX) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ if (0 == maxMsgSize) {
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ pEndpoint = &target->EndPoint[assignedEndpoint];
+
+ if (pEndpoint->ServiceID != 0) {
+ /* endpoint already in use! */
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+
+ /* return assigned endpoint to caller */
+ pConnectResp->Endpoint = assignedEndpoint;
+ pConnectResp->MaxMsgLength = maxMsgSize;
+
+ /* setup the endpoint */
+ pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
+ pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
+ pEndpoint->MaxMsgLength = maxMsgSize;
+ /* copy all the callbacks */
+ pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
+ INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
+ INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
+ /* set the credit distribution info for this endpoint, this information is
+ * passed back to the credit distribution callback function */
+ pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
+ pEndpoint->CreditDist.pHTCReserved = pEndpoint;
+ pEndpoint->CreditDist.Endpoint = assignedEndpoint;
+ pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
+ pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
+
+ if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
+ pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
+ }
+
+ status = A_OK;
+
+ } while (FALSE);
+
+ if (pSendPacket != NULL) {
+ HTC_FREE_CONTROL_TX(target,pSendPacket);
+ }
+
+ if (pRecvPacket != NULL) {
+ HTC_FREE_CONTROL_RX(target,pRecvPacket);
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
+
+ return status;
+}
+
+static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
+
+ if (NULL == target->EpCreditDistributionListHead) {
+ target->EpCreditDistributionListHead = pEpDist;
+ pEpDist->pNext = NULL;
+ pEpDist->pPrev = NULL;
+ return;
+ }
+
+ /* queue to the end of the list, this does not have to be very
+ * fast since this list is built at startup time */
+ pCurEntry = target->EpCreditDistributionListHead;
+
+ while (pCurEntry) {
+ pLastEntry = pCurEntry;
+ pCurEntry = pCurEntry->pNext;
+ }
+
+ pLastEntry->pNext = pEpDist;
+ pEpDist->pPrev = pLastEntry;
+ pEpDist->pNext = NULL;
+}
+
+
+
+/* default credit init callback */
+static void HTCDefaultCreditInit(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ int TotalCredits)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ int totalEps = 0;
+ int creditsPerEndpoint;
+
+ pCurEpDist = pEPList;
+ /* first run through the list and figure out how many endpoints we are dealing with */
+ while (pCurEpDist != NULL) {
+ pCurEpDist = pCurEpDist->pNext;
+ totalEps++;
+ }
+
+ /* even distribution */
+ creditsPerEndpoint = TotalCredits/totalEps;
+
+ pCurEpDist = pEPList;
+ /* run through the list and set minimum and normal credits and
+ * provide the endpoint with some credits to start */
+ while (pCurEpDist != NULL) {
+
+ if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
+ /* too many endpoints and not enough credits */
+ AR_DEBUG_ASSERT(FALSE);
+ break;
+ }
+ /* our minimum is set for at least 1 max message */
+ pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+ /* this value is ignored by our credit alg, since we do
+ * not dynamically adjust credits, this is the policy of
+ * the "default" credit distribution, something simple and easy */
+ pCurEpDist->TxCreditsNorm = 0xFFFF;
+ /* give the endpoint minimum credits */
+ pCurEpDist->TxCredits = creditsPerEndpoint;
+ pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+}
+
+/* default credit distribution callback, NOTE, this callback holds the TX lock */
+void HTCDefaultCreditDist(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+ HTC_CREDIT_DIST_REASON Reason)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+
+ if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
+ pCurEpDist = pEPDistList;
+ /* simple distribution */
+ while (pCurEpDist != NULL) {
+ if (pCurEpDist->TxCreditsToDist > 0) {
+ /* just give the endpoint back the credits */
+ pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+ pCurEpDist->TxCreditsToDist = 0;
+ }
+ pCurEpDist = pCurEpDist->pNext;
+ }
+ }
+
+ /* note we do not need to handle the other reason codes as this is a very
+ * simple distribution scheme, no need to seek for more credits or handle inactivity */
+}
+
+void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
+ void *pCreditDistContext,
+ HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+ HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+ HTC_SERVICE_ID ServicePriorityOrder[],
+ int ListLength)
+{
+ HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
+ int i;
+ int ep;
+
+ if (CreditInitFunc != NULL) {
+ /* caller has supplied their own distribution functions */
+ target->InitCredits = CreditInitFunc;
+ AR_DEBUG_ASSERT(CreditDistFunc != NULL);
+ target->DistributeCredits = CreditDistFunc;
+ target->pCredDistContext = pCreditDistContext;
+ } else {
+ /* caller wants HTC to do distribution */
+ /* if caller wants service to handle distributions then
+ * it must set both of these to NULL! */
+ AR_DEBUG_ASSERT(CreditDistFunc == NULL);
+ target->InitCredits = HTCDefaultCreditInit;
+ target->DistributeCredits = HTCDefaultCreditDist;
+ target->pCredDistContext = target;
+ }
+
+ /* always add HTC control endpoint first, we only expose the list after the
+ * first one, this is added for TX queue checking */
+ AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
+
+ /* build the list of credit distribution structures in priority order
+ * supplied by the caller, these will follow endpoint 0 */
+ for (i = 0; i < ListLength; i++) {
+ /* match services with endpoints and add the endpoints to the distribution list
+ * in FIFO order */
+ for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
+ if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
+ /* queue this one to the list */
+ AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
+ break;
+ }
+ }
+ AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
+ }
+
+}
--- /dev/null
+++ b/drivers/ar6000/include/a_config.h
@@ -0,0 +1,27 @@
+#ifndef _A_CONFIG_H_
+#define _A_CONFIG_H_
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+/*
+ * This file contains software configuration options that enables
+ * specific software "features"
+ */
+#include "../ar6000/config_linux.h"
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/include/a_debug.h
@@ -0,0 +1,41 @@
+#ifndef _A_DEBUG_H_
+#define _A_DEBUG_H_
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include <a_types.h>
+#include <a_osapi.h>
+
+#define DBG_INFO 0x00000001
+#define DBG_ERROR 0x00000002
+#define DBG_WARNING 0x00000004
+#define DBG_SDIO 0x00000008
+#define DBG_HIF 0x00000010
+#define DBG_HTC 0x00000020
+#define DBG_WMI 0x00000040
+#define DBG_WMI2 0x00000080
+#define DBG_DRIVER 0x00000100
+
+#define DBG_DEFAULTS (DBG_ERROR|DBG_WARNING)
+
+#include "../ar6000/debug_linux.h"
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/include/a_drv_api.h
@@ -0,0 +1,185 @@
+#ifndef _A_DRV_API_H_
+#define _A_DRV_API_H_
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/****************************************************************************/
+/** **/
+/** WMI related hooks **/
+/** **/
+/****************************************************************************/
+/****************************************************************************/
+
+#include <ar6000_api.h>
+
+#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \
+ ar6000_channelList_rx((devt), (numChan), (chanList))
+
+#define A_WMI_SET_NUMDATAENDPTS(devt, num) \
+ ar6000_set_numdataendpts((devt), (num))
+
+#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \
+ ar6000_control_tx((devt), (osbuf), (streamID))
+
+#define A_WMI_TARGETSTATS_EVENT(devt, pStats) \
+ ar6000_targetStats_event((devt), (pStats))
+
+#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \
+ ar6000_scanComplete_event((devt), (status))
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+
+#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \
+ ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_DSET_CLOSE(devt, access_cookie) \
+ ar6000_dset_close((devt), (access_cookie))
+
+#endif
+
+#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
+ ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
+
+#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
+ ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
+
+#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \
+ ar6000_regDomain_event((devt), (regCode))
+
+#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \
+ ar6000_neighborReport_event((devt), (numAps), (info))
+
+#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \
+ ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
+
+#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \
+ ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
+
+#define A_WMI_BITRATE_RX(devt, rateKbps) \
+ ar6000_bitrate_rx((devt), (rateKbps))
+
+#define A_WMI_TXPWR_RX(devt, txPwr) \
+ ar6000_txPwr_rx((devt), (txPwr))
+
+#define A_WMI_READY_EVENT(devt, datap, phyCap) \
+ ar6000_ready_event((devt), (datap), (phyCap))
+
+#define A_WMI_DBGLOG_INIT_DONE(ar) \
+ ar6000_dbglog_init_done(ar);
+
+#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \
+ ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
+
+#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \
+ ar6000_reportError_event((devt), (errorVal))
+
+#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
+ ar6000_roam_tbl_event((devt), (pTbl))
+
+#define A_WMI_ROAM_DATA_EVENT(devt, p) \
+ ar6000_roam_data_event((devt), (p))
+
+#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \
+ ar6000_wow_list_event((devt), (num_filters), (wow_filters))
+
+#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \
+ ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
+
+#define A_WMI_IPTOS_TO_USERPRIORITY(pkt) \
+ ar6000_iptos_to_userPriority((pkt))
+
+#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list) \
+ ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list))
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+
+#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
+ ar6000_gpio_intr_rx((intr_mask), (input_values))
+
+#define A_WMI_GPIO_DATA_RX(reg_id, value) \
+ ar6000_gpio_data_rx((reg_id), (value))
+
+#define A_WMI_GPIO_ACK_RX() \
+ ar6000_gpio_ack_rx()
+
+#endif
+
+#ifdef SEND_EVENT_TO_APP
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
+ ar6000_send_event_to_app((ar), (eventId), (datap), (len))
+
+#else
+
+#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
+
+#endif
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
+ ar6000_tcmd_rx_report_event((devt), (results), (len))
+#endif
+
+#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \
+ ar6000_hbChallengeResp_event((devt), (cookie), (source))
+
+#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
+ ar6000_tx_retry_err_event((devt))
+
+#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
+ ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
+
+#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
+ ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
+
+#define A_WMI_RATEMASK_RX(devt, ratemask) \
+ ar6000_ratemask_rx((devt), (ratemask))
+
+#define A_WMI_KEEPALIVE_RX(devt, configured) \
+ ar6000_keepalive_rx((devt), (configured))
+
+#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \
+ ar6000_bssInfo_event_rx((ar), (datap), (len))
+
+#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
+ ar6000_dbglog_event((ar), (dropped), (buffer), (length));
+
+#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
+ ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
+
+#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
+ ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
+
+/****************************************************************************/
+/****************************************************************************/
+/** **/
+/** HTC related hooks **/
+/** **/
+/****************************************************************************/
+/****************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/include/a_drv.h
@@ -0,0 +1,28 @@
+#ifndef _A_DRV_H_
+#define _A_DRV_H_
+/*
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_drv.h#1 $
+ *
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "../ar6000/athdrv_linux.h"
+
+#endif /* _ADRV_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/a_osapi.h
@@ -0,0 +1,28 @@
+#ifndef _A_OSAPI_H_
+#define _A_OSAPI_H_
+/*
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_osapi.h#1 $
+ *
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "../ar6000/osapi_linux.h"
+
+#endif /* _OSAPI_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/ar6000_api.h
@@ -0,0 +1,29 @@
+#ifndef _AR6000_API_H_
+#define _AR6000_API_H_
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file contains the API to access the OS dependent atheros host driver
+ * by the WMI or WLAN generic modules.
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/ar6000_api.h#1 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "../ar6000/ar6xapi_linux.h"
+
+#endif /* _AR6000_API_H */
+
--- /dev/null
+++ b/drivers/ar6000/include/ar6000_diag.h
@@ -0,0 +1,38 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef AR6000_DIAG_H_
+#define AR6000_DIAG_H_
+
+
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length);
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length);
+
+#endif /*AR6000_DIAG_H_*/
--- /dev/null
+++ b/drivers/ar6000/include/AR6001_regdump.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef __AR6000_REGDUMP_H__
+#define __AR6000_REGDUMP_H__
+
+#if !defined(__ASSEMBLER__)
+/*
+ * Target CPU state at the time of failure is reflected
+ * in a register dump, which the Host can fetch through
+ * the diagnostic window.
+ */
+
+struct MIPS_exception_frame_s {
+ A_UINT32 pc; /* Program Counter */
+ A_UINT32 at; /* MIPS General Purpose registers */
+ A_UINT32 v0;
+ A_UINT32 v1;
+ A_UINT32 a0;
+ A_UINT32 a1;
+ A_UINT32 a2;
+ A_UINT32 a3;
+ A_UINT32 t0;
+ A_UINT32 t1;
+ A_UINT32 t2;
+ A_UINT32 t3;
+ A_UINT32 t4;
+ A_UINT32 t5;
+ A_UINT32 t6;
+ A_UINT32 t7;
+ A_UINT32 s0;
+ A_UINT32 s1;
+ A_UINT32 s2;
+ A_UINT32 s3;
+ A_UINT32 s4;
+ A_UINT32 s5;
+ A_UINT32 s6;
+ A_UINT32 s7;
+ A_UINT32 t8;
+ A_UINT32 t9;
+ A_UINT32 k0;
+ A_UINT32 k1;
+ A_UINT32 gp;
+ A_UINT32 sp;
+ A_UINT32 s8;
+ A_UINT32 ra;
+ A_UINT32 cause; /* Selected coprocessor regs */
+ A_UINT32 status;
+};
+typedef struct MIPS_exception_frame_s CPU_exception_frame_t;
+
+#endif
+
+/*
+ * Offsets into MIPS_exception_frame structure, for use in assembler code
+ * MUST MATCH C STRUCTURE ABOVE
+ */
+#define RD_pc 0
+#define RD_at 1
+#define RD_v0 2
+#define RD_v1 3
+#define RD_a0 4
+#define RD_a1 5
+#define RD_a2 6
+#define RD_a3 7
+#define RD_t0 8
+#define RD_t1 9
+#define RD_t2 10
+#define RD_t3 11
+#define RD_t4 12
+#define RD_t5 13
+#define RD_t6 14
+#define RD_t7 15
+#define RD_s0 16
+#define RD_s1 17
+#define RD_s2 18
+#define RD_s3 19
+#define RD_s4 20
+#define RD_s5 21
+#define RD_s6 22
+#define RD_s7 23
+#define RD_t8 24
+#define RD_t9 25
+#define RD_k0 26
+#define RD_k1 27
+#define RD_gp 28
+#define RD_sp 29
+#define RD_s8 30
+#define RD_ra 31
+#define RD_cause 32
+#define RD_status 33
+
+#define RD_SIZE (34*4) /* Space for this number of words */
+
+#endif /* __AR6000_REGDUMP_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/AR6Khwreg.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This file contains the definitions for AR6001 registers
+ * that may be directly manipulated by Host software.
+ */
+
+#ifndef __AR6KHWREG_H__
+#define __AR6KHWREG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Host registers */
+#define HOST_INT_STATUS_ADDRESS 0x00000400
+#define CPU_INT_STATUS_ADDRESS 0x00000401
+#define ERROR_INT_STATUS_ADDRESS 0x00000402
+#define INT_STATUS_ENABLE_ADDRESS 0x00000418
+#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
+#define COUNT_ADDRESS 0x00000420
+#define COUNT_DEC_ADDRESS 0x00000440
+#define WINDOW_DATA_ADDRESS 0x00000474
+#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
+#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
+
+/* Target addresses */
+#define RESET_CONTROL_ADDRESS 0x0c000000
+#define MC_REMAP_VALID_ADDRESS 0x0c004080
+#define MC_REMAP_SIZE_ADDRESS 0x0c004100
+#define MC_REMAP_COMPARE_ADDRESS 0x0c004180
+#define MC_REMAP_TARGET_ADDRESS 0x0c004200
+#define LOCAL_COUNT_ADDRESS 0x0c014080
+#define LOCAL_SCRATCH_ADDRESS 0x0c0140c0
+
+
+#define INT_STATUS_ENABLE_ERROR_MSB 7
+#define INT_STATUS_ENABLE_ERROR_LSB 7
+#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
+#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
+#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
+
+#define INT_STATUS_ENABLE_CPU_MSB 6
+#define INT_STATUS_ENABLE_CPU_LSB 6
+#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
+#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
+#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
+
+#define INT_STATUS_ENABLE_COUNTER_MSB 4
+#define INT_STATUS_ENABLE_COUNTER_LSB 4
+#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
+#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
+#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
+
+#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
+#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
+#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
+
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
+
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
+
+
+#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
+#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
+#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
+#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
+
+#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
+#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
+#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
+
+#define ERROR_INT_STATUS_WAKEUP_MSB 2
+#define ERROR_INT_STATUS_WAKEUP_LSB 2
+#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
+#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
+#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
+
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
+#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
+#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
+
+#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
+#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
+#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
+
+#define HOST_INT_STATUS_ERROR_MSB 7
+#define HOST_INT_STATUS_ERROR_LSB 7
+#define HOST_INT_STATUS_ERROR_MASK 0x00000080
+#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
+#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
+
+#define HOST_INT_STATUS_CPU_MSB 6
+#define HOST_INT_STATUS_CPU_LSB 6
+#define HOST_INT_STATUS_CPU_MASK 0x00000040
+#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
+#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
+
+#define HOST_INT_STATUS_COUNTER_MSB 4
+#define HOST_INT_STATUS_COUNTER_LSB 4
+#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
+#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
+#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
+
+#define RESET_CONTROL_WARM_RST_MSB 7
+#define RESET_CONTROL_WARM_RST_LSB 7
+#define RESET_CONTROL_WARM_RST_MASK 0x00000080
+#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
+#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
+
+#define RESET_CONTROL_COLD_RST_MSB 8
+#define RESET_CONTROL_COLD_RST_LSB 8
+#define RESET_CONTROL_COLD_RST_MASK 0x00000100
+#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
+#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
+
+#define RESET_CAUSE_LAST_MSB 2
+#define RESET_CAUSE_LAST_LSB 0
+#define RESET_CAUSE_LAST_MASK 0x00000007
+#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
+#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AR6KHWREG_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/AR6K_version.h
@@ -0,0 +1,36 @@
+#define __VER_MAJOR_ 2
+#define __VER_MINOR_ 0
+#define __VER_PATCH_ 0
+
+
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * The makear6ksdk script (used for release builds) modifies the following line.
+ */
+#define __BUILD_NUMBER_ 18
+
+
+/* Format of the version number. */
+#define VER_MAJOR_BIT_OFFSET 28
+#define VER_MINOR_BIT_OFFSET 24
+#define VER_PATCH_BIT_OFFSET 16
+#define VER_BUILD_NUM_BIT_OFFSET 0
+
+
+/*
+ * The version has the following format:
+ * Bits 28-31: Major version
+ * Bits 24-27: Minor version
+ * Bits 16-23: Patch version
+ * Bits 0-15: Build number (automatically generated during build process )
+ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
+ *
+ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
+ */
+#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
+
+
--- /dev/null
+++ b/drivers/ar6000/include/AR6K_version.h.NEW
@@ -0,0 +1,36 @@
+#define __VER_MAJOR_ 2
+#define __VER_MINOR_ 0
+#define __VER_PATCH_ 0
+
+
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * The makear6ksdk script (used for release builds) modifies the following line.
+ */
+#define __BUILD_NUMBER_ 18
+
+
+/* Format of the version number. */
+#define VER_MAJOR_BIT_OFFSET 28
+#define VER_MINOR_BIT_OFFSET 24
+#define VER_PATCH_BIT_OFFSET 16
+#define VER_BUILD_NUM_BIT_OFFSET 0
+
+
+/*
+ * The version has the following format:
+ * Bits 28-31: Major version
+ * Bits 24-27: Minor version
+ * Bits 16-23: Patch version
+ * Bits 0-15: Build number (automatically generated during build process )
+ * E.g. Build 1.1.3.7 would be represented as 0x11030007.
+ *
+ * DO NOT split the following macro into multiple lines as this may confuse the build scripts.
+ */
+#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
+
+
--- /dev/null
+++ b/drivers/ar6000/include/athdefs.h
@@ -0,0 +1,85 @@
+#ifndef __ATHDEFS_H__
+#define __ATHDEFS_H__
+
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This file contains definitions that may be used across both
+ * Host and Target software. Nothing here is module-dependent
+ * or platform-dependent.
+ */
+
+/*
+ * Generic error codes that can be used by hw, sta, ap, sim, dk
+ * and any other environments. Since these are enums, feel free to
+ * add any more codes that you need.
+ */
+
+typedef enum {
+ A_ERROR = -1, /* Generic error return */
+ A_OK = 0, /* success */
+ /* Following values start at 1 */
+ A_DEVICE_NOT_FOUND, /* not able to find PCI device */
+ A_NO_MEMORY, /* not able to allocate memory, not available */
+ A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
+ A_NO_FREE_DESC, /* no free descriptors available */
+ A_BAD_ADDRESS, /* address does not match descriptor */
+ A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
+ A_REGS_NOT_MAPPED, /* registers not correctly mapped */
+ A_EPERM, /* Not superuser */
+ A_EACCES, /* Access denied */
+ A_ENOENT, /* No such entry, search failed, etc. */
+ A_EEXIST, /* The object already exists (can't create) */
+ A_EFAULT, /* Bad address fault */
+ A_EBUSY, /* Object is busy */
+ A_EINVAL, /* Invalid parameter */
+ A_EMSGSIZE, /* Inappropriate message buffer length */
+ A_ECANCELED, /* Operation canceled */
+ A_ENOTSUP, /* Operation not supported */
+ A_ECOMM, /* Communication error on send */
+ A_EPROTO, /* Protocol error */
+ A_ENODEV, /* No such device */
+ A_EDEVNOTUP, /* device is not UP */
+ A_NO_RESOURCE, /* No resources for requested operation */
+ A_HARDWARE, /* Hardware failure */
+ A_PENDING, /* Asynchronous routine; will send up results la
+ter (typically in callback) */
+ A_EBADCHANNEL, /* The channel cannot be used */
+ A_DECRYPT_ERROR, /* Decryption error */
+ A_PHY_ERROR, /* RX PHY error */
+ A_CONSUMED /* Object was consumed */
+} A_STATUS;
+
+#define A_SUCCESS(x) (x == A_OK)
+#define A_FAILED(x) (!A_SUCCESS(x))
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/*
+ * The following definition is WLAN specific definition
+ */
+typedef enum {
+ MODE_11A = 0, /* 11a Mode */
+ MODE_11G = 1, /* 11g + 11b Mode */
+ MODE_11B = 2, /* 11b Mode */
+ MODE_11GONLY = 3, /* 11g only Mode */
+ MODE_UNKNOWN = 4,
+ MODE_MAX = 4
+} WLAN_PHY_MODE;
+
+typedef enum {
+ WLAN_11A_CAPABILITY = 1,
+ WLAN_11G_CAPABILITY = 2,
+ WLAN_11AG_CAPABILITY = 3,
+}WLAN_CAPABILITY;
+
+#endif /* __ATHDEFS_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/athdrv.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _ATHDRV_H_
+#define _ATHDRV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ATHDRV_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/athendpack.h
@@ -0,0 +1,41 @@
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ * @file: athendpack.h
+ *
+ * @abstract: end compiler-specific structure packing
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#ifdef LINUX
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athendpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+#ifdef UNDER_CE
+#include "../os/wince/include/athendpack_wince.h"
+#endif /* WINCE */
+
--- /dev/null
+++ b/drivers/ar6000/include/athstartpack.h
@@ -0,0 +1,42 @@
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ * @file: athstartpack.h
+ *
+ * @abstract: start compiler-specific structure packing
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#ifdef LINUX
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */
+
+#ifdef INTEGRITY
+#include "integrity/athstartpack_integrity.h"
+#endif /* INTEGRITY */
+
+#ifdef NUCLEUS
+#endif /* NUCLEUS */
+
+#ifdef UNDER_CE
+#include "../os/wince/include/athstartpack_wince.h"
+#endif /* WINCE */
+
--- /dev/null
+++ b/drivers/ar6000/include/a_types.h
@@ -0,0 +1,28 @@
+#ifndef _A_TYPES_H_
+#define _A_TYPES_H_
+/*
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/a_types.h#1 $
+ *
+ * This file contains the definitions of the basic atheros data types.
+ * It is used to map the data types in atheros files to a platform specific
+ * type.
+ *
+ * Copyright 2003-2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "../ar6000/athtypes_linux.h"
+
+#endif /* _ATHTYPES_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/bmi.h
@@ -0,0 +1,100 @@
+#ifndef _BMI_H_
+#define _BMI_H_
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ * BMI declarations and prototypes
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "hif.h"
+#include "a_osapi.h"
+#include "bmi_msg.h"
+
+void
+BMIInit(void);
+
+A_STATUS
+BMIDone(HIF_DEVICE *device);
+
+A_STATUS
+BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
+
+A_STATUS
+BMIReadMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIWriteMemory(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length);
+
+A_STATUS
+BMIExecute(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param);
+
+A_STATUS
+BMISetAppStart(HIF_DEVICE *device,
+ A_UINT32 address);
+
+A_STATUS
+BMIReadSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 *param);
+
+A_STATUS
+BMIWriteSOCRegister(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UINT32 param);
+
+A_STATUS
+BMIrompatchInstall(HIF_DEVICE *device,
+ A_UINT32 ROM_addr,
+ A_UINT32 RAM_addr,
+ A_UINT32 nbytes,
+ A_UINT32 do_activate,
+ A_UINT32 *patch_id);
+
+A_STATUS
+BMIrompatchUninstall(HIF_DEVICE *device,
+ A_UINT32 rompatch_id);
+
+A_STATUS
+BMIrompatchActivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list);
+
+A_STATUS
+BMIrompatchDeactivate(HIF_DEVICE *device,
+ A_UINT32 rompatch_count,
+ A_UINT32 *rompatch_list);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BMI_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/bmi_msg.h
@@ -0,0 +1,199 @@
+#ifndef __BMI_MSG_H__
+#define __BMI_MSG_H__
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+/*
+ * Bootloader Messaging Interface (BMI)
+ *
+ * BMI is a very simple messaging interface used during initialization
+ * to read memory, write memory, execute code, and to define an
+ * application entry PC.
+ *
+ * It is used to download an application to AR6K, to provide
+ * patches to code that is already resident on AR6K, and generally
+ * to examine and modify state. The Host has an opportunity to use
+ * BMI only once during bootup. Once the Host issues a BMI_DONE
+ * command, this opportunity ends.
+ *
+ * The Host writes BMI requests to mailbox0, and reads BMI responses
+ * from mailbox0. BMI requests all begin with a command
+ * (see below for specific commands), and are followed by
+ * command-specific data.
+ *
+ * Flow control:
+ * The Host can only issue a command once the Target gives it a
+ * "BMI Command Credit", using AR6K Counter #4. As soon as the
+ * Target has completed a command, it issues another BMI Command
+ * Credit (so the Host can issue the next command).
+ *
+ * BMI handles all required Target-side cache flushing.
+ */
+
+
+/* Maximum data size used for BMI transfers */
+#define BMI_DATASZ_MAX 32
+
+/* BMI Commands */
+
+#define BMI_NO_COMMAND 0
+
+#define BMI_DONE 1
+ /*
+ * Semantics: Host is done using BMI
+ * Request format:
+ * A_UINT32 command (BMI_DONE)
+ * Response format: none
+ */
+
+#define BMI_READ_MEMORY 2
+ /*
+ * Semantics: Host reads AR6K memory
+ * Request format:
+ * A_UINT32 command (BMI_READ_MEMORY)
+ * A_UINT32 address
+ * A_UINT32 length, at most BMI_DATASZ_MAX
+ * Response format:
+ * A_UINT8 data[length]
+ */
+
+#define BMI_WRITE_MEMORY 3
+ /*
+ * Semantics: Host writes AR6K memory
+ * Request format:
+ * A_UINT32 command (BMI_WRITE_MEMORY)
+ * A_UINT32 address
+ * A_UINT32 length, at most BMI_DATASZ_MAX
+ * A_UINT8 data[length]
+ * Response format: none
+ */
+
+#define BMI_EXECUTE 4
+ /*
+ * Semantics: Causes AR6K to execute code
+ * Request format:
+ * A_UINT32 command (BMI_EXECUTE)
+ * A_UINT32 address
+ * A_UINT32 parameter
+ * Response format:
+ * A_UINT32 return value
+ */
+
+#define BMI_SET_APP_START 5
+ /*
+ * Semantics: Set Target application starting address
+ * Request format:
+ * A_UINT32 command (BMI_SET_APP_START)
+ * A_UINT32 address
+ * Response format: none
+ */
+
+#define BMI_READ_SOC_REGISTER 6
+ /*
+ * Semantics: Read a 32-bit Target SOC register.
+ * Request format:
+ * A_UINT32 command (BMI_READ_REGISTER)
+ * A_UINT32 address
+ * Response format:
+ * A_UINT32 value
+ */
+
+#define BMI_WRITE_SOC_REGISTER 7
+ /*
+ * Semantics: Write a 32-bit Target SOC register.
+ * Request format:
+ * A_UINT32 command (BMI_WRITE_REGISTER)
+ * A_UINT32 address
+ * A_UINT32 value
+ *
+ * Response format: none
+ */
+
+#define BMI_GET_TARGET_ID 8
+#define BMI_GET_TARGET_INFO 8
+ /*
+ * Semantics: Fetch the 4-byte Target information
+ * Request format:
+ * A_UINT32 command (BMI_GET_TARGET_ID/INFO)
+ * Response format1 (old firmware):
+ * A_UINT32 TargetVersionID
+ * Response format2 (newer firmware):
+ * A_UINT32 TARGET_VERSION_SENTINAL
+ * struct bmi_target_info;
+ */
+
+struct bmi_target_info {
+ A_UINT32 target_info_byte_count; /* size of this structure */
+ A_UINT32 target_ver; /* Target Version ID */
+ A_UINT32 target_type; /* Target type */
+};
+#define TARGET_VERSION_SENTINAL 0xffffffff
+#define TARGET_TYPE_AR6001 1
+#define TARGET_TYPE_AR6002 2
+
+
+#define BMI_ROMPATCH_INSTALL 9
+ /*
+ * Semantics: Install a ROM Patch.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_INSTALL)
+ * A_UINT32 Target ROM Address
+ * A_UINT32 Target RAM Address
+ * A_UINT32 Size, in bytes
+ * A_UINT32 Activate? 1-->activate;
+ * 0-->install but do not activate
+ * Response format:
+ * A_UINT32 PatchID
+ */
+
+#define BMI_ROMPATCH_UNINSTALL 10
+ /*
+ * Semantics: Uninstall a previously-installed ROM Patch,
+ * automatically deactivating, if necessary.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
+ * A_UINT32 PatchID
+ *
+ * Response format: none
+ */
+
+#define BMI_ROMPATCH_ACTIVATE 11
+ /*
+ * Semantics: Activate a list of previously-installed ROM Patches.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
+ * A_UINT32 rompatch_count
+ * A_UINT32 PatchID[rompatch_count]
+ *
+ * Response format: none
+ */
+
+#define BMI_ROMPATCH_DEACTIVATE 12
+ /*
+ * Semantics: Deactivate a list of active ROM Patches.
+ * Request format:
+ * A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
+ * A_UINT32 rompatch_count
+ * A_UINT32 PatchID[rompatch_count]
+ *
+ * Response format: none
+ */
+
+
+#endif /* __BMI_MSG_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/common_drv.h
@@ -0,0 +1,61 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+
+#ifndef COMMON_DRV_H_
+#define COMMON_DRV_H_
+
+#include "hif.h"
+#include "htc_packet.h"
+
+
+
+/* structure that is the state information for the default credit distribution callback
+ * drivers should instantiate (zero-init as well) this structure in their driver instance
+ * and pass it as a context to the HTC credit distribution functions */
+typedef struct _COMMON_CREDIT_STATE_INFO {
+ int TotalAvailableCredits; /* total credits in the system at startup */
+ int CurrentFreeCredits; /* credits available in the pool that have not been
+ given out to endpoints */
+ HTC_ENDPOINT_CREDIT_DIST *pLowestPriEpDist; /* pointer to the lowest priority endpoint dist struct */
+} COMMON_CREDIT_STATE_INFO;
+
+
+/* HTC TX packet tagging definitions */
+#define AR6K_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
+#define AR6K_DATA_PKT_TAG (AR6K_CONTROL_PKT_TAG + 1)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* OS-independent APIs */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo);
+A_STATUS ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+A_STATUS ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
+A_STATUS ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address, A_UCHAR *data, A_UINT32 length);
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType);
+A_STATUS ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*COMMON_DRV_H_*/
--- /dev/null
+++ b/drivers/ar6000/include/dbglog_api.h
@@ -0,0 +1,46 @@
+#ifndef _DBGLOG_API_H_
+#define _DBGLOG_API_H_
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ * This file contains host side debug primitives.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dbglog.h"
+
+#define DBGLOG_HOST_LOG_BUFFER_SIZE DBGLOG_LOG_BUFFER_SIZE
+
+#define DBGLOG_GET_DBGID(arg) \
+ ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
+
+#define DBGLOG_GET_MODULEID(arg) \
+ ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
+
+#define DBGLOG_GET_NUMARGS(arg) \
+ ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
+
+#define DBGLOG_GET_TIMESTAMP(arg) \
+ ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_API_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/dbglog.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This file contains the definitions and data structures associated with
+ * the log based debug mechanism.
+ *
+ */
+
+#ifndef _DBGLOG_H_
+#define _DBGLOG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DBGLOG_TIMESTAMP_OFFSET 0
+#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit
+ 8-23 of the LF0 timer */
+#define DBGLOG_DBGID_OFFSET 16
+#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */
+#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULEID_OFFSET 26
+#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */
+#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */
+
+/*
+ * Please ensure that the definition of any new module intrduced is captured
+ * between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
+ * structure is required for the parser to correctly pick up the values for
+ * different modules.
+ */
+#define DBGLOG_MODULEID_START
+#define DBGLOG_MODULEID_INF 0
+#define DBGLOG_MODULEID_WMI 1
+#define DBGLOG_MODULEID_CSERV 2
+#define DBGLOG_MODULEID_PM 3
+#define DBGLOG_MODULEID_TXRX_MGMTBUF 4
+#define DBGLOG_MODULEID_TXRX_TXBUF 5
+#define DBGLOG_MODULEID_TXRX_RXBUF 6
+#define DBGLOG_MODULEID_WOW 7
+#define DBGLOG_MODULEID_WHAL 8
+#define DBGLOG_MODULEID_END
+
+#define DBGLOG_NUM_ARGS_OFFSET 30
+#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */
+#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */
+
+#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0
+#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF
+
+#define DBGLOG_REPORTING_ENABLED_OFFSET 16
+#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000
+
+#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
+#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000
+
+#define DBGLOG_REPORT_SIZE_OFFSET 20
+#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000
+
+#define DBGLOG_LOG_BUFFER_SIZE 1500
+#define DBGLOG_DBGID_DEFINITION_LEN_MAX 64
+
+struct dbglog_buf_s {
+ struct dbglog_buf_s *next;
+ A_INT8 *buffer;
+ A_UINT32 bufsize;
+ A_UINT32 length;
+ A_UINT32 count;
+ A_UINT32 free;
+};
+
+struct dbglog_hdr_s {
+ struct dbglog_buf_s *dbuf;
+ A_UINT32 dropped;
+};
+
+struct dbglog_config_s {
+ A_UINT32 cfgvalid; /* Mask with valid config bits */
+ union {
+ /* TODO: Take care of endianness */
+ struct {
+ A_UINT32 mmask:16; /* Mask of modules with logging on */
+ A_UINT32 rep:1; /* Reporting enabled or not */
+ A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */
+ A_UINT32 size:10; /* Report size in number of messages */
+ A_UINT32 reserved:2;
+ } dbglog_config;
+
+ A_UINT32 value;
+ } u;
+};
+
+#define cfgmmask u.dbglog_config.mmask
+#define cfgrep u.dbglog_config.rep
+#define cfgtsr u.dbglog_config.tsr
+#define cfgsize u.dbglog_config.size
+#define cfgvalue u.value
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/dbglog_id.h
@@ -0,0 +1,307 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This file contains the definitions of the debug identifiers for different
+ * modules.
+ *
+ */
+
+#ifndef _DBGLOG_ID_H_
+#define _DBGLOG_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
+ * Please ensure that the definition of any new debugid introduced is captured
+ * between the <MODULE>_DBGID_DEFINITION_START and
+ * <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
+ * parser to correctly pick up the values for different debug identifiers.
+ */
+
+/* INF debug identifier definitions */
+#define INF_DBGID_DEFINITION_START
+#define INF_ASSERTION_FAILED 1
+#define INF_TARGET_ID 2
+#define INF_DBGID_DEFINITION_END
+
+/* WMI debug identifier definitions */
+#define WMI_DBGID_DEFINITION_START
+#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1
+#define WMI_EXTENDED_CMD_NOT_HANDLED 2
+#define WMI_CMD_RX_PKT_TOO_SHORT 3
+#define WMI_CALLING_WMI_EXTENSION_FN 4
+#define WMI_CMD_NOT_HANDLED 5
+#define WMI_IN_SYNC 6
+#define WMI_TARGET_WMI_SYNC_CMD 7
+#define WMI_SET_SNR_THRESHOLD_PARAMS 8
+#define WMI_SET_RSSI_THRESHOLD_PARAMS 9
+#define WMI_SET_LQ_TRESHOLD_PARAMS 10
+#define WMI_TARGET_CREATE_PSTREAM_CMD 11
+#define WMI_WI_DTM_INUSE 12
+#define WMI_TARGET_DELETE_PSTREAM_CMD 13
+#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14
+#define WMI_TARGET_GET_BIT_RATE_CMD 15
+#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16
+#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17
+#define WMI_TARGET_GET_TX_PWR_CMD 18
+#define WMI_FREE_EVBUF_WMIBUF 19
+#define WMI_FREE_EVBUF_DATABUF 20
+#define WMI_FREE_EVBUF_BADFLAG 21
+#define WMI_HTC_RX_ERROR_DATA_PACKET 22
+#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23
+#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24
+#define WMI_SENDING_READY_EVENT 25
+#define WMI_SETPOWER_MDOE_TO_MAXPERF 26
+#define WMI_SETPOWER_MDOE_TO_REC 27
+#define WMI_BSSINFO_EVENT_FROM 28
+#define WMI_TARGET_GET_STATS_CMD 29
+#define WMI_SENDING_SCAN_COMPLETE_EVENT 30
+#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31
+#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32
+#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33
+#define WMI_SENDING_ERROR_REPORT_EVENT 34
+#define WMI_SENDING_CAC_EVENT 35
+#define WMI_TARGET_GET_ROAM_TABLE_CMD 36
+#define WMI_TARGET_GET_ROAM_DATA_CMD 37
+#define WMI_SENDING_GPIO_INTR_EVENT 38
+#define WMI_SENDING_GPIO_ACK_EVENT 39
+#define WMI_SENDING_GPIO_DATA_EVENT 40
+#define WMI_CMD_RX 41
+#define WMI_CMD_RX_XTND 42
+#define WMI_EVENT_SEND 43
+#define WMI_EVENT_SEND_XTND 44
+#define WMI_DBGID_DEFINITION_END
+
+/* CSERV debug identifier definitions */
+#define CSERV_DBGID_DEFINITION_START
+#define CSERV_BEGIN_SCAN1 1
+#define CSERV_BEGIN_SCAN2 2
+#define CSERV_END_SCAN1 3
+#define CSERV_END_SCAN2 4
+#define CSERV_CHAN_SCAN_START 5
+#define CSERV_CHAN_SCAN_STOP 6
+#define CSERV_CHANNEL_OPPPORTUNITY 7
+#define CSERV_NC_TIMEOUT 8
+#define CSERV_BACK_HOME 10
+#define CSERV_CHMGR_CH_CALLBACK1 11
+#define CSERV_CHMGR_CH_CALLBACK2 12
+#define CSERV_CHMGR_CH_CALLBACK3 13
+#define CSERV_SET_SCAN_PARAMS1 14
+#define CSERV_SET_SCAN_PARAMS2 15
+#define CSERV_SET_SCAN_PARAMS3 16
+#define CSERV_SET_SCAN_PARAMS4 17
+#define CSERV_ABORT_SCAN 18
+#define CSERV_NEWSTATE 19
+#define CSERV_MINCHMGR_OP_END 20
+#define CSERV_CHMGR_OP_END 21
+#define CSERV_DISCONNECT_TIMEOUT 22
+#define CSERV_ROAM_TIMEOUT 23
+#define CSERV_FORCE_SCAN1 24
+#define CSERV_FORCE_SCAN2 25
+#define CSERV_FORCE_SCAN3 26
+#define CSERV_UTIL_TIMEOUT 27
+#define CSERV_RSSIPOLLER 28
+#define CSERV_RETRY_CONNECT_TIMEOUT 29
+#define CSERV_RSSIINDBMPOLLER 30
+#define CSERV_BGSCAN_ENABLE 31
+#define CSERV_BGSCAN_DISABLE 32
+#define CSERV_WLAN_START_SCAN_CMD1 33
+#define CSERV_WLAN_START_SCAN_CMD2 34
+#define CSERV_WLAN_START_SCAN_CMD3 35
+#define CSERV_START_SCAN_CMD 36
+#define CSERV_START_FORCE_SCAN 37
+#define CSERV_NEXT_CHAN 38
+#define CSERV_SET_REGCODE 39
+#define CSERV_START_ADHOC 40
+#define CSERV_ADHOC_AT_HOME 41
+#define CSERV_OPT_AT_HOME 42
+#define CSERV_WLAN_CONNECT_CMD 43
+#define CSERV_WLAN_RECONNECT_CMD 44
+#define CSERV_WLAN_DISCONNECT_CMD 45
+#define CSERV_BSS_CHANGE_CHANNEL 46
+#define CSERV_BEACON_RX 47
+#define CSERV_KEEPALIVE_CHECK 48
+#define CSERV_RC_BEGIN_SCAN 49
+#define CSERV_RC_SCAN_START 50
+#define CSERV_RC_SCAN_STOP 51
+#define CSERV_RC_NEXT 52
+#define CSERV_RC_SCAN_END 53
+#define CSERV_PROBE_CALLBACK 54
+#define CSERV_ROAM1 55
+#define CSERV_ROAM2 56
+#define CSERV_ROAM3 57
+#define CSERV_CONNECT_EVENT 58
+#define CSERV_DISCONNECT_EVENT 59
+#define CSERV_BMISS_HANDLER1 60
+#define CSERV_BMISS_HANDLER2 61
+#define CSERV_BMISS_HANDLER3 62
+#define CSERV_LOWRSSI_HANDLER 63
+#define CSERV_WLAN_SET_PMKID_CMD 64
+#define CSERV_RECONNECT_REQUEST 65
+#define CSERV_KEYSPLUMBED_EVENT 66
+#define CSERV_NEW_REG 67
+#define CSERV_SET_RSSI_THOLD 68
+#define CSERV_RSSITHRESHOLDCHECK 69
+#define CSERV_RSSIINDBMTHRESHOLDCHECK 70
+#define CSERV_WLAN_SET_OPT_CMD1 71
+#define CSERV_WLAN_SET_OPT_CMD2 72
+#define CSERV_WLAN_SET_OPT_CMD3 73
+#define CSERV_WLAN_SET_OPT_CMD4 74
+#define CSERV_SCAN_CONNECT_STOP 75
+#define CSERV_BMISS_HANDLER4 76
+#define CSERV_INITIALIZE_TIMER 77
+#define CSERV_ARM_TIMER 78
+#define CSERV_DISARM_TIMER 79
+#define CSERV_UNINITIALIZE_TIMER 80
+#define CSERV_DISCONNECT_EVENT2 81
+#define CSERV_SCAN_CONNECT_START 82
+#define CSERV_BSSINFO_MEMORY_ALLOC_FAILED 83
+#define CSERV_SET_SCAN_PARAMS5 84
+#define CSERV_DBGID_DEFINITION_END
+
+/* TXRX debug identifier definitions */
+#define TXRX_TXBUF_DBGID_DEFINITION_START
+#define TXRX_TXBUF_ALLOCATE_BUF 1
+#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2
+#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3
+#define TXRX_TXBUF_TXQ_DEPTH 4
+#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5
+#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6
+#define TXRX_TXBUF_INITIALIZE_TIMER 7
+#define TXRX_TXBUF_ARM_TIMER 8
+#define TXRX_TXBUF_DISARM_TIMER 9
+#define TXRX_TXBUF_UNINITIALIZE_TIMER 10
+#define TXRX_TXBUF_DBGID_DEFINITION_END
+
+#define TXRX_RXBUF_DBGID_DEFINITION_START
+#define TXRX_RXBUF_ALLOCATE_BUF 1
+#define TXRX_RXBUF_QUEUE_TO_HOST 2
+#define TXRX_RXBUF_QUEUE_TO_WLAN 3
+#define TXRX_RXBUF_ZERO_LEN_BUF 4
+#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5
+#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6
+#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7
+#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8
+#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9
+#define TXRX_RXBUF_DBGID_DEFINITION_END
+
+#define TXRX_MGMTBUF_DBGID_DEFINITION_START
+#define TXRX_MGMTBUF_ALLOCATE_BUF 1
+#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2
+#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3
+#define TXRX_MGMTBUF_GET_BUF 4
+#define TXRX_MGMTBUF_GET_SM_BUF 5
+#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6
+#define TXRX_MGMTBUF_REAPED_BUF 7
+#define TXRX_MGMTBUF_REAPED_SM_BUF 8
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9
+#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10
+#define TXRX_MGMTBUF_ENQUEUE_INTO_SFQ 11
+#define TXRX_MGMTBUF_DEQUEUE_FROM_SFQ 12
+#define TXRX_MGMTBUF_PAUSE_TXQ 13
+#define TXRX_MGMTBUF_RESUME_TXQ 14
+#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15
+#define TXRX_MGMTBUF_DRAINQ 16
+#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17
+#define TXRX_MGMTBUF_DBGID_DEFINITION_END
+
+/* PM (Power Module) debug identifier definitions */
+#define PM_DBGID_DEFINITION_START
+#define PM_INIT 1
+#define PM_ENABLE 2
+#define PM_SET_STATE 3
+#define PM_SET_POWERMODE 4
+#define PM_CONN_NOTIFY 5
+#define PM_REF_COUNT_NEGATIVE 6
+#define PM_APSD_ENABLE 7
+#define PM_UPDATE_APSD_STATE 8
+#define PM_CHAN_OP_REQ 9
+#define PM_SET_MY_BEACON_POLICY 10
+#define PM_SET_ALL_BEACON_POLICY 11
+#define PM_SET_PM_PARAMS1 12
+#define PM_SET_PM_PARAMS2 13
+#define PM_ADHOC_SET_PM_CAPS_FAIL 14
+#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15
+#define PM_DBGID_DEFINITION_END
+
+/* Wake on Wireless debug identifier definitions */
+#define WOW_DBGID_DEFINITION_START
+#define WOW_INIT 1
+#define WOW_GET_CONFIG_DSET 2
+#define WOW_NO_CONFIG_DSET 3
+#define WOW_INVALID_CONFIG_DSET 4
+#define WOW_USE_DEFAULT_CONFIG 5
+#define WOW_SETUP_GPIO 6
+#define WOW_INIT_DONE 7
+#define WOW_SET_GPIO_PIN 8
+#define WOW_CLEAR_GPIO_PIN 9
+#define WOW_SET_WOW_MODE_CMD 10
+#define WOW_SET_HOST_MODE_CMD 11
+#define WOW_ADD_WOW_PATTERN_CMD 12
+#define WOW_NEW_WOW_PATTERN_AT_INDEX 13
+#define WOW_DEL_WOW_PATTERN_CMD 14
+#define WOW_LIST_CONTAINS_PATTERNS 15
+#define WOW_GET_WOW_LIST_CMD 16
+#define WOW_INVALID_FILTER_ID 17
+#define WOW_INVALID_FILTER_LISTID 18
+#define WOW_NO_VALID_FILTER_AT_ID 19
+#define WOW_NO_VALID_LIST_AT_ID 20
+#define WOW_NUM_PATTERNS_EXCEEDED 21
+#define WOW_NUM_LISTS_EXCEEDED 22
+#define WOW_GET_WOW_STATS 23
+#define WOW_CLEAR_WOW_STATS 24
+#define WOW_WAKEUP_HOST 25
+#define WOW_EVENT_WAKEUP_HOST 26
+#define WOW_EVENT_DISCARD 27
+#define WOW_PATTERN_MATCH 28
+#define WOW_PATTERN_NOT_MATCH 29
+#define WOW_PATTERN_NOT_MATCH_OFFSET 30
+#define WOW_DISABLED_HOST_ASLEEP 31
+#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32
+#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33
+#define WOW_DBGID_DEFINITION_END
+
+/* WHAL debug identifier definitions */
+#define WHAL_DBGID_DEFINITION_START
+#define WHAL_ERROR_ANI_CONTROL 1
+#define WHAL_ERROR_CHIP_TEST1 2
+#define WHAL_ERROR_CHIP_TEST2 3
+#define WHAL_ERROR_EEPROM_CHECKSUM 4
+#define WHAL_ERROR_EEPROM_MACADDR 5
+#define WHAL_ERROR_INTERRUPT_HIU 6
+#define WHAL_ERROR_KEYCACHE_RESET 7
+#define WHAL_ERROR_KEYCACHE_SET 8
+#define WHAL_ERROR_KEYCACHE_TYPE 9
+#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10
+#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11
+#define WHAL_ERROR_PHY_INVALID_CHANNEL 12
+#define WHAL_ERROR_POWER_AWAKE 13
+#define WHAL_ERROR_POWER_SET 14
+#define WHAL_ERROR_RECV_STOPDMA 15
+#define WHAL_ERROR_RECV_STOPPCU 16
+#define WHAL_ERROR_RESET_CHANNF1 17
+#define WHAL_ERROR_RESET_CHANNF2 18
+#define WHAL_ERROR_RESET_PM 19
+#define WHAL_ERROR_RESET_OFFSETCAL 20
+#define WHAL_ERROR_RESET_RFGRANT 21
+#define WHAL_ERROR_RESET_RXFRAME 22
+#define WHAL_ERROR_RESET_STOPDMA 23
+#define WHAL_ERROR_RESET_RECOVER 24
+#define WHAL_ERROR_XMIT_COMPUTE 25
+#define WHAL_ERROR_XMIT_NOQUEUE 26
+#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27
+#define WHAL_ERROR_XMIT_BADTYPE 28
+#define WHAL_DBGID_DEFINITION_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DBGLOG_ID_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/dl_list.h
@@ -0,0 +1,114 @@
+/*
+ *
+ * Double-link list definitions (adapted from Atheros SDIO stack)
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+#ifndef __DL_LIST_H___
+#define __DL_LIST_H___
+
+#define A_CONTAINING_STRUCT(address, struct_type, field_name)\
+ ((struct_type *)((A_UINT32)(address) - (A_UINT32)(&((struct_type *)0)->field_name)))
+
+/* list functions */
+/* pointers for the list */
+typedef struct _DL_LIST {
+ struct _DL_LIST *pPrev;
+ struct _DL_LIST *pNext;
+}DL_LIST, *PDL_LIST;
+/*
+ * DL_LIST_INIT , initialize doubly linked list
+*/
+#define DL_LIST_INIT(pList)\
+ {(pList)->pPrev = pList; (pList)->pNext = pList;}
+
+#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
+#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
+#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
+/*
+ * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
+ * NOT: do not use this function if the items in the list are deleted inside the
+ * iteration loop
+*/
+#define ITERATE_OVER_LIST(pStart, pTemp) \
+ for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
+
+
+/* safe iterate macro that allows the item to be removed from the list
+ * the iteration continues to the next item in the list
+ */
+#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset) \
+{ \
+ PDL_LIST pTemp; \
+ pTemp = (pStart)->pNext; \
+ while (pTemp != (pStart)) { \
+ (pItem) = A_CONTAINING_STRUCT(pTemp,st,offset); \
+ pTemp = pTemp->pNext; \
+
+#define ITERATE_END }}
+
+/*
+ * DL_ListInsertTail - insert pAdd to the end of the list
+*/
+static INLINE PDL_LIST DL_ListInsertTail(PDL_LIST pList, PDL_LIST pAdd) {
+ /* insert at tail */
+ pAdd->pPrev = pList->pPrev;
+ pAdd->pNext = pList;
+ pList->pPrev->pNext = pAdd;
+ pList->pPrev = pAdd;
+ return pAdd;
+}
+
+/*
+ * DL_ListInsertHead - insert pAdd into the head of the list
+*/
+static INLINE PDL_LIST DL_ListInsertHead(PDL_LIST pList, PDL_LIST pAdd) {
+ /* insert at head */
+ pAdd->pPrev = pList;
+ pAdd->pNext = pList->pNext;
+ pList->pNext->pPrev = pAdd;
+ pList->pNext = pAdd;
+ return pAdd;
+}
+
+#define DL_ListAdd(pList,pItem) DL_ListInsertHead((pList),(pItem))
+/*
+ * DL_ListRemove - remove pDel from list
+*/
+static INLINE PDL_LIST DL_ListRemove(PDL_LIST pDel) {
+ pDel->pNext->pPrev = pDel->pPrev;
+ pDel->pPrev->pNext = pDel->pNext;
+ /* point back to itself just to be safe, incase remove is called again */
+ pDel->pNext = pDel;
+ pDel->pPrev = pDel;
+ return pDel;
+}
+
+/*
+ * DL_ListRemoveItemFromHead - get a list item from the head
+*/
+static INLINE PDL_LIST DL_ListRemoveItemFromHead(PDL_LIST pList) {
+ PDL_LIST pItem = NULL;
+ if (pList->pNext != pList) {
+ pItem = pList->pNext;
+ /* remove the first item from head */
+ DL_ListRemove(pItem);
+ }
+ return pItem;
+}
+
+#endif /* __DL_LIST_H___ */
--- /dev/null
+++ b/drivers/ar6000/include/dset_api.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/dset_api.h#1 $
+ *
+ * Host-side DataSet API.
+ *
+ */
+
+#ifndef _DSET_API_H_
+#define _DSET_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Host-side DataSet support is optional, and is not
+ * currently required for correct operation. To disable
+ * Host-side DataSet support, set this to 0.
+ */
+#ifndef CONFIG_HOST_DSET_SUPPORT
+#define CONFIG_HOST_DSET_SUPPORT 1
+#endif
+
+/* Called to send a DataSet Open Reply back to the Target. */
+A_STATUS wmi_dset_open_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT32 access_cookie,
+ A_UINT32 size,
+ A_UINT32 version,
+ A_UINT32 targ_handle,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+
+/* Called to send a DataSet Data Reply back to the Target. */
+A_STATUS wmi_dset_data_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT8 *host_buf,
+ A_UINT32 length,
+ A_UINT32 targ_buf,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+#endif /* _DSET_API_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/dsetid.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef __DSETID_H__
+#define __DSETID_H__
+
+/* Well-known DataSet IDs */
+#define DSETID_UNUSED 0x00000000
+#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */
+#define DSETID_REGDB 0x00000002 /* Regulatory Database */
+#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */
+#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */
+
+#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005
+#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025
+/*
+ * Get DSETID for various reference clock speeds.
+ * For each speed there are three DataSets that correspond
+ * to the three columns of bank6 data (addr, 11a, 11b/g).
+ * This macro returns the dsetid of the first of those
+ * three DataSets.
+ */
+#define ANALOG_CONTROL_DATA_DSETID(refclk) \
+ (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
+
+/*
+ * There are TWO STARTUP_PATCH DataSets.
+ * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
+ * earlier systems. On AR6002, it is applied after BMI, just like
+ * DSETID_STARTUP_PATCH2.
+ */
+#define DSETID_STARTUP_PATCH 0x00000026
+#define DSETID_GPIO_CONFIG_PATCH 0x00000027
+#define DSETID_WLANREGS 0x00000028 /* override wlan regs */
+#define DSETID_STARTUP_PATCH2 0x00000029
+
+#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */
+
+/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
+#define DSETID_INI_DATA 0x00000100
+/* Reserved for WHAL INI Tables: 0x100..0x11f */
+#define DSETID_INI_DATA_END 0x0000011f
+
+#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */
+
+#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the
+ end of a memory-based
+ DataSet Index */
+#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */
+
+/*
+ * PATCH DataSet format:
+ * A list of patches, terminated by a patch with
+ * address=PATCH_END.
+ *
+ * This allows for patches to be stored in flash.
+ */
+struct patch_s {
+ A_UINT32 *address;
+ A_UINT32 data;
+};
+
+/*
+ * Skip some patches. Can be used to erase a single patch in a
+ * patch DataSet without having to re-write the DataSet. May
+ * also be used to embed information for use by subsequent
+ * patch code. The "data" in a PATCH_SKIP tells how many
+ * bytes of length "patch_s" to skip.
+ */
+#define PATCH_SKIP ((A_UINT32 *)0x00000000)
+
+/*
+ * Execute code at the address specified by "data".
+ * The address of the patch structure is passed as
+ * the one parameter.
+ */
+#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001)
+
+/*
+ * Same as PATCH_CODE_ABS, but treat "data" as an
+ * offset from the start of the patch word.
+ */
+#define PATCH_CODE_REL ((A_UINT32 *)0x00000002)
+
+/* Mark the end of this patch DataSet. */
+#define PATCH_END ((A_UINT32 *)0xffffffff)
+
+/*
+ * A DataSet which contains a Binary Patch to some other DataSet
+ * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
+ * Such a BPatch DataSet consists of BPatch metadata followed by
+ * the bdiff bytes. BPatch metadata consists of a single 32-bit
+ * word that contains the size of the BPatched final image.
+ *
+ * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
+ * to create "diffs":
+ * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
+ * Then add BPatch metadata to the start of "diffs".
+ *
+ * NB: There are some implementation-induced restrictions
+ * on which DataSets can be BPatched.
+ */
+#define DSETID_BPATCH_FLAG 0x80000000
+
+#endif /* __DSETID_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/dset_internal.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef __DSET_INTERNAL_H__
+#define __DSET_INTERNAL_H__
+
+/*
+ * Internal dset definitions, common for DataSet layer.
+ */
+
+#define DSET_TYPE_STANDARD 0
+#define DSET_TYPE_BPATCHED 1
+#define DSET_TYPE_COMPRESSED 2
+
+/* Dataset descriptor */
+
+typedef struct dset_descriptor_s {
+ struct dset_descriptor_s *next; /* List link. NULL only at the last
+ descriptor */
+ A_UINT16 id; /* Dset ID */
+ A_UINT16 size; /* Dset size. */
+ void *DataPtr; /* Pointer to raw data for standard
+ DataSet or pointer to original
+ dset_descriptor for patched
+ DataSet */
+ A_UINT32 data_type; /* DSET_TYPE_*, above */
+
+ void *AuxPtr; /* Additional data that might
+ needed for data_type. For
+ example, pointer to patch
+ Dataset descriptor for BPatch. */
+} dset_descriptor_t;
+
+#endif /* __DSET_INTERNAL_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/gpio_api.h
@@ -0,0 +1,57 @@
+#ifndef _GPIO_API_H_
+#define _GPIO_API_H_
+/*
+ * Copyright 2005 Atheros Communications, Inc., All Rights Reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+/*
+ * Host-side General Purpose I/O API.
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/gpio_api.h#1 $
+ */
+
+/*
+ * Send a command to the Target in order to change output on GPIO pins.
+ */
+A_STATUS wmi_gpio_output_set(struct wmi_t *wmip,
+ A_UINT32 set_mask,
+ A_UINT32 clear_mask,
+ A_UINT32 enable_mask,
+ A_UINT32 disable_mask);
+
+/*
+ * Send a command to the Target requesting input state of GPIO pins.
+ */
+A_STATUS wmi_gpio_input_get(struct wmi_t *wmip);
+
+/*
+ * Send a command to the Target to change the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_set(struct wmi_t *wmip,
+ A_UINT32 gpioreg_id,
+ A_UINT32 value);
+
+/*
+ * Send a command to the Target to fetch the value of a GPIO register.
+ */
+A_STATUS wmi_gpio_register_get(struct wmi_t *wmip, A_UINT32 gpioreg_id);
+
+/*
+ * Send a command to the Target, acknowledging some GPIO interrupts.
+ */
+A_STATUS wmi_gpio_intr_ack(struct wmi_t *wmip, A_UINT32 ack_mask);
+
+#endif /* _GPIO_API_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#if defined(AR6001)
+#define GPIO_PIN_COUNT 18
+#else
+#define GPIO_PIN_COUNT 18
+#endif
+
+/*
+ * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
+ * NB: These match hardware order, so that addresses can
+ * easily be computed.
+ */
+#define GPIO_ID_OUT 0x00000000
+#define GPIO_ID_OUT_W1TS 0x00000001
+#define GPIO_ID_OUT_W1TC 0x00000002
+#define GPIO_ID_ENABLE 0x00000003
+#define GPIO_ID_ENABLE_W1TS 0x00000004
+#define GPIO_ID_ENABLE_W1TC 0x00000005
+#define GPIO_ID_IN 0x00000006
+#define GPIO_ID_STATUS 0x00000007
+#define GPIO_ID_STATUS_W1TS 0x00000008
+#define GPIO_ID_STATUS_W1TC 0x00000009
+#define GPIO_ID_PIN0 0x0000000a
+#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
+
+#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17)
+#define GPIO_ID_NONE 0xffffffff
--- /dev/null
+++ b/drivers/ar6000/include/hif.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ * HIF specific declarations and prototypes
+ */
+
+#ifndef _HIF_H_
+#define _HIF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Header files */
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+
+typedef struct htc_callbacks HTC_CALLBACKS;
+typedef struct hif_device HIF_DEVICE;
+
+/*
+ * direction - Direction of transfer (HIF_READ/HIF_WRITE).
+ */
+#define HIF_READ 0x00000001
+#define HIF_WRITE 0x00000002
+#define HIF_DIR_MASK (HIF_READ | HIF_WRITE)
+
+/*
+ * type - An interface may support different kind of read/write commands.
+ * The command type is divided into a basic and an extended command
+ * and can be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
+ */
+#define HIF_BASIC_IO 0x00000004
+#define HIF_EXTENDED_IO 0x00000008
+#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO)
+
+/*
+ * emode - This indicates the whether the command is to be executed in a
+ * blocking or non-blocking fashion (HIF_SYNCHRONOUS/
+ * HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
+ * implemented using the asynchronous mode allowing the the bus
+ * driver to indicate the completion of operation through the
+ * registered callback routine. The requirement primarily comes
+ * from the contexts these operations get called from (a driver's
+ * transmit context or the ISR context in case of receive).
+ * Support for both of these modes is essential.
+ */
+#define HIF_SYNCHRONOUS 0x00000010
+#define HIF_ASYNCHRONOUS 0x00000020
+#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
+
+/*
+ * dmode - An interface may support different kinds of commands based on
+ * the tradeoff between the amount of data it can carry and the
+ * setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
+ * HIF_BLOCK_BASIS). In case of latter, the data is rounded off
+ * to the nearest block size by padding. The size of the block is
+ * configurable at compile time using the HIF_BLOCK_SIZE and is
+ * negotiated with the target during initialization after the
+ * dragon interrupts are enabled.
+ */
+#define HIF_BYTE_BASIS 0x00000040
+#define HIF_BLOCK_BASIS 0x00000080
+#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
+
+/*
+ * amode - This indicates if the address has to be incremented on dragon
+ * after every read/write operation (HIF?FIXED_ADDRESS/
+ * HIF_INCREMENTAL_ADDRESS).
+ */
+#define HIF_FIXED_ADDRESS 0x00000100
+#define HIF_INCREMENTAL_ADDRESS 0x00000200
+#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | HIF_INCREMENTAL_ADDRESS)
+
+#define HIF_WR_ASYNC_BYTE_FIX \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_ASYNC_BYTE_INC \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_ASYNC_BLOCK_INC \
+ (HIF_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BYTE_FIX \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_WR_SYNC_BYTE_INC \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_WR_SYNC_BLOCK_INC \
+ (HIF_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BYTE_INC \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BYTE_FIX \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_FIX \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_FIX \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
+#define HIF_RD_ASYNC_BYTE_INC \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_ASYNC_BLOCK_INC \
+ (HIF_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+#define HIF_RD_SYNC_BLOCK_INC \
+ (HIF_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
+
+
+typedef enum {
+ HIF_DEVICE_POWER_STATE = 0,
+ HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
+ HIF_DEVICE_GET_MBOX_ADDR,
+ HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
+ HIF_DEVICE_GET_IRQ_PROC_MODE,
+ HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
+} HIF_DEVICE_CONFIG_OPCODE;
+
+/*
+ * HIF CONFIGURE definitions:
+ *
+ * HIF_DEVICE_GET_MBOX_BLOCK_SIZE
+ * input : none
+ * output : array of 4 A_UINT32s
+ * notes: block size is returned for each mailbox (4)
+ *
+ * HIF_DEVICE_GET_MBOX_ADDR
+ * input : none
+ * output : array of 4 A_UINT32
+ * notes: address is returned for each mailbox (4) in the array
+ *
+ * HIF_DEVICE_GET_PENDING_EVENTS_FUNC
+ * input : none
+ * output: HIF_PENDING_EVENTS_FUNC function pointer
+ * notes: this is optional for the HIF layer, if the request is
+ * not handled then it indicates that the upper layer can use
+ * the standard device methods to get pending events (IRQs, mailbox messages etc..)
+ * otherwise it can call the function pointer to check pending events.
+ *
+ * HIF_DEVICE_GET_IRQ_PROC_MODE
+ * input : none
+ * output : HIF_DEVICE_IRQ_PROCESSING_MODE (interrupt processing mode)
+ * note: the hif layer interfaces with the underlying OS-specific bus driver. The HIF
+ * layer can report whether IRQ processing is requires synchronous behavior or
+ * can be processed using asynchronous bus requests (typically faster).
+ *
+ * HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC
+ * input :
+ * output : HIF_MASK_UNMASK_RECV_EVENT function pointer
+ * notes: this is optional for the HIF layer. The HIF layer may require a special mechanism
+ * to mask receive message events. The upper layer can call this pointer when it needs
+ * to mask/unmask receive events (in case it runs out of buffers).
+ *
+ *
+ */
+
+typedef enum {
+ HIF_DEVICE_IRQ_SYNC_ONLY, /* for HIF implementations that require the DSR to process all
+ interrupts before returning */
+ HIF_DEVICE_IRQ_ASYNC_SYNC, /* for HIF implementations that allow DSR to process interrupts
+ using ASYNC I/O (that is HIFAckInterrupt can be called at a
+ later time */
+} HIF_DEVICE_IRQ_PROCESSING_MODE;
+
+#define HIF_MAX_DEVICES 1
+
+struct htc_callbacks {
+ A_UCHAR *name;
+ A_UINT32 id;
+ A_STATUS (* deviceInsertedHandler)(void *hif_handle);
+ A_STATUS (* deviceRemovedHandler)(void *htc_handle, A_STATUS status);
+ A_STATUS (* deviceSuspendHandler)(void *htc_handle);
+ A_STATUS (* deviceResumeHandler)(void *htc_handle);
+ A_STATUS (* deviceWakeupHandler)(void *htc_handle);
+ A_STATUS (* rwCompletionHandler)(void *context, A_STATUS status);
+ A_STATUS (* dsrHandler)(void *htc_handle);
+};
+
+
+#define HIF_OTHER_EVENTS (1 << 0) /* other interrupts (non-Recv) are pending, host
+ needs to read the register table to figure out what */
+#define HIF_RECV_MSG_AVAIL (1 << 1) /* pending recv packet */
+
+typedef struct _HIF_PENDING_EVENTS_INFO {
+ A_UINT32 Events;
+ A_UINT32 LookAhead;
+} HIF_PENDING_EVENTS_INFO;
+
+ /* function to get pending events , some HIF modules use special mechanisms
+ * to detect packet available and other interrupts */
+typedef A_STATUS ( *HIF_PENDING_EVENTS_FUNC)(HIF_DEVICE *device,
+ HIF_PENDING_EVENTS_INFO *pEvents,
+ void *AsyncContext);
+
+#define HIF_MASK_RECV TRUE
+#define HIF_UNMASK_RECV FALSE
+ /* function to mask recv events */
+typedef A_STATUS ( *HIF_MASK_UNMASK_RECV_EVENT)(HIF_DEVICE *device,
+ A_BOOL Mask,
+ void *AsyncContext);
+
+
+/*
+ * This API is used by the HTC layer to initialize the HIF layer and to
+ * register different callback routines. Support for following events has
+ * been captured - DSR, Read/Write completion, Device insertion/removal,
+ * Device suspension/resumption/wakeup. In addition to this, the API is
+ * also used to register the name and the revision of the chip. The latter
+ * can be used to verify the revision of the chip read from the device
+ * before reporting it to HTC.
+ */
+int HIFInit(HTC_CALLBACKS *callbacks);
+
+/*
+ * This API is used to provide the read/write interface over the specific bus
+ * interface.
+ * address - Starting address in the dragon's address space. For mailbox
+ * writes, it refers to the start of the mbox boundary. It should
+ * be ensured that the last byte falls on the mailbox's EOM. For
+ * mailbox reads, it refers to the end of the mbox boundary.
+ * buffer - Pointer to the buffer containg the data to be transmitted or
+ * received.
+ * length - Amount of data to be transmitted or received.
+ * request - Characterizes the attributes of the command.
+ */
+A_STATUS
+HIFReadWrite(HIF_DEVICE *device,
+ A_UINT32 address,
+ A_UCHAR *buffer,
+ A_UINT32 length,
+ A_UINT32 request,
+ void *context);
+
+/*
+ * This can be initiated from the unload driver context ie when the HTCShutdown
+ * routine is called.
+ */
+void HIFShutDownDevice(HIF_DEVICE *device);
+
+/*
+ * This should translate to an acknowledgment to the bus driver indicating that
+ * the previous interrupt request has been serviced and the all the relevant
+ * sources have been cleared. HTC is ready to process more interrupts.
+ * This should prevent the bus driver from raising an interrupt unless the
+ * previous one has been serviced and acknowledged using the previous API.
+ */
+void HIFAckInterrupt(HIF_DEVICE *device);
+
+void HIFMaskInterrupt(HIF_DEVICE *device);
+
+void HIFUnMaskInterrupt(HIF_DEVICE *device);
+
+/*
+ * This set of functions are to be used by the bus driver to notify
+ * the HIF module about various events.
+ * These are not implemented if the bus driver provides an alternative
+ * way for this notification though callbacks for instance.
+ */
+int HIFInsertEventNotify(void);
+
+int HIFRemoveEventNotify(void);
+
+int HIFIRQEventNotify(void);
+
+int HIFRWCompleteEventNotify(void);
+
+/*
+ * This function associates a opaque handle with the HIF layer
+ * to be used in communication with upper layer i.e. HTC.
+ * This would normaly be a pointer to htc_target data structure.
+ */
+void HIFSetHandle(void *hif_handle, void *handle);
+
+A_STATUS
+HIFConfigureDevice(HIF_DEVICE *device, HIF_DEVICE_CONFIG_OPCODE opcode,
+ void *config, A_UINT32 configLen);
+
+
+struct device;
+struct device*
+HIFGetOSDevice(HIF_DEVICE *device);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HIF_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/host_version.h
@@ -0,0 +1,49 @@
+#ifndef _HOST_VERSION_H_
+#define _HOST_VERSION_H_
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file contains version information for the sample host driver for the
+ * AR6000 chip
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/host_version.h#2 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <AR6K_version.h>
+
+/*
+ * The version number is made up of major, minor, patch and build
+ * numbers. These are 16 bit numbers. The build and release script will
+ * set the build number using a Perforce counter. Here the build number is
+ * set to 9999 so that builds done without the build-release script are easily
+ * identifiable.
+ */
+
+#define ATH_SW_VER_MAJOR __VER_MAJOR_
+#define ATH_SW_VER_MINOR __VER_MINOR_
+#define ATH_SW_VER_PATCH __VER_PATCH_
+#define ATH_SW_VER_BUILD 9999
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_VERSION_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/htc_api.h
@@ -0,0 +1,436 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef _HTC_API_H_
+#define _HTC_API_H_
+
+#include <htc.h>
+#include <htc_services.h>
+#include "htc_packet.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* TODO.. for BMI */
+#define ENDPOINT1 0
+// TODO -remove me, but we have to fix BMI first
+#define HTC_MAILBOX_NUM_MAX 4
+
+
+/* ------ Endpoint IDS ------ */
+typedef enum
+{
+ ENDPOINT_UNUSED = -1,
+ ENDPOINT_0 = 0,
+ ENDPOINT_1 = 1,
+ ENDPOINT_2 = 2,
+ ENDPOINT_3,
+ ENDPOINT_4,
+ ENDPOINT_5,
+ ENDPOINT_6,
+ ENDPOINT_7,
+ ENDPOINT_8,
+ ENDPOINT_MAX,
+} HTC_ENDPOINT_ID;
+
+/* this is the amount of header room required by users of HTC */
+#define HTC_HEADER_LEN HTC_HDR_LENGTH
+
+typedef void *HTC_HANDLE;
+
+typedef A_UINT16 HTC_SERVICE_ID;
+
+typedef struct _HTC_INIT_INFO {
+ void (*AddInstance)(HTC_HANDLE);
+ void (*DeleteInstance)(void *Instance);
+ void (*TargetFailure)(void *Instance, A_STATUS Status);
+} HTC_INIT_INFO;
+
+/* per service connection send completion */
+typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *,HTC_PACKET *);
+/* per service connection pkt received */
+typedef void (*HTC_EP_RECV_PKT)(void *,HTC_PACKET *);
+
+/* Optional per service connection receive buffer re-fill callback,
+ * On some OSes (like Linux) packets are allocated from a global pool and indicated up
+ * to the network stack. The driver never gets the packets back from the OS. For these OSes
+ * a refill callback can be used to allocate and re-queue buffers into HTC.
+ *
+ * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
+ * the driver can re-queue these buffers into HTC. In this regard a refill callback is
+ * unnecessary */
+typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
+
+/* Optional per service connection callback when a send queue is full. This can occur if the
+ * host continues queueing up TX packets faster than credits can arrive
+ * To prevent the host (on some Oses like Linux) from continuously queueing packets
+ * and consuming resources, this callback is provided so that that the host
+ * can disable TX in the subsystem (i.e. network stack)
+ * Other OSes require a "per-packet" indication_RAW_STREAM_NUM_MAX for each completed TX packet, this
+ * closed loop mechanism will prevent the network stack from overunning the NIC */
+typedef void (*HTC_EP_SEND_QUEUE_FULL)(void *, HTC_ENDPOINT_ID Endpoint);
+
+typedef struct _HTC_EP_CALLBACKS {
+ void *pContext; /* context for each callback */
+ HTC_EP_SEND_PKT_COMPLETE EpTxComplete; /* tx completion callback for connected endpoint */
+ HTC_EP_RECV_PKT EpRecv; /* receive callback for connected endpoint */
+ HTC_EP_RECV_REFILL EpRecvRefill; /* OPTIONAL receive re-fill callback for connected endpoint */
+ HTC_EP_SEND_QUEUE_FULL EpSendFull; /* OPTIONAL send full callback */
+} HTC_EP_CALLBACKS;
+
+/* service connection information */
+typedef struct _HTC_SERVICE_CONNECT_REQ {
+ HTC_SERVICE_ID ServiceID; /* service ID to connect to */
+ A_UINT16 ConnectionFlags; /* connection flags, see htc protocol definition */
+ A_UINT8 *pMetaData; /* ptr to optional service-specific meta-data */
+ A_UINT8 MetaDataLength; /* optional meta data length */
+ HTC_EP_CALLBACKS EpCallbacks; /* endpoint callbacks */
+ int MaxSendQueueDepth; /* maximum depth of any send queue */
+} HTC_SERVICE_CONNECT_REQ;
+
+/* service connection response information */
+typedef struct _HTC_SERVICE_CONNECT_RESP {
+ A_UINT8 *pMetaData; /* caller supplied buffer to optional meta-data */
+ A_UINT8 BufferLength; /* length of caller supplied buffer */
+ A_UINT8 ActualLength; /* actual length of meta data */
+ HTC_ENDPOINT_ID Endpoint; /* endpoint to communicate over */
+ int MaxMsgLength; /* max length of all messages over this endpoint */
+ A_UINT8 ConnectRespCode; /* connect response code from target */
+} HTC_SERVICE_CONNECT_RESP;
+
+/* endpoint distribution structure */
+typedef struct _HTC_ENDPOINT_CREDIT_DIST {
+ struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
+ struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
+ HTC_SERVICE_ID ServiceID; /* Service ID (set by HTC) */
+ HTC_ENDPOINT_ID Endpoint; /* endpoint for this distribution struct (set by HTC) */
+ A_UINT32 DistFlags; /* distribution flags, distribution function can
+ set default activity using SET_EP_ACTIVE() macro */
+ int TxCreditsNorm; /* credits for normal operation, anything above this
+ indicates the endpoint is over-subscribed, this field
+ is only relevant to the credit distribution function */
+ int TxCreditsMin; /* floor for credit distribution, this field is
+ only relevant to the credit distribution function */
+ int TxCreditsAssigned; /* number of credits assigned to this EP, this field
+ is only relevant to the credit dist function */
+ int TxCredits; /* current credits available, this field is used by
+ HTC to determine whether a message can be sent or
+ must be queued */
+ int TxCreditsToDist; /* pending credits to distribute on this endpoint, this
+ is set by HTC when credit reports arrive.
+ The credit distribution functions sets this to zero
+ when it distributes the credits */
+ int TxCreditsSeek; /* this is the number of credits that the current pending TX
+ packet needs to transmit. This is set by HTC when
+ and endpoint needs credits in order to transmit */
+ int TxCreditSize; /* size in bytes of each credit (set by HTC) */
+ int TxCreditsPerMaxMsg; /* credits required for a maximum sized messages (set by HTC) */
+ void *pHTCReserved; /* reserved for HTC use */
+} HTC_ENDPOINT_CREDIT_DIST;
+
+#define HTC_EP_ACTIVE (1 << 31)
+
+/* macro to check if an endpoint has gone active, useful for credit
+ * distributions */
+#define IS_EP_ACTIVE(epDist) ((epDist)->DistFlags & HTC_EP_ACTIVE)
+#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
+
+ /* credit distibution code that is passed into the distrbution function,
+ * there are mandatory and optional codes that must be handled */
+typedef enum _HTC_CREDIT_DIST_REASON {
+ HTC_CREDIT_DIST_SEND_COMPLETE = 0, /* credits available as a result of completed
+ send operations (MANDATORY) resulting in credit reports */
+ HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1, /* a change in endpoint activity occured (OPTIONAL) */
+ HTC_CREDIT_DIST_SEEK_CREDITS, /* an endpoint needs to "seek" credits (OPTIONAL) */
+ HTC_DUMP_CREDIT_STATE /* for debugging, dump any state information that is kept by
+ the distribution function */
+} HTC_CREDIT_DIST_REASON;
+
+typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ HTC_CREDIT_DIST_REASON Reason);
+
+typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ int TotalCredits);
+
+ /* endpoint statistics action */
+typedef enum _HTC_ENDPOINT_STAT_ACTION {
+ HTC_EP_STAT_SAMPLE = 0, /* only read statistics */
+ HTC_EP_STAT_SAMPLE_AND_CLEAR = 1, /* sample and immediately clear statistics */
+ HTC_EP_STAT_CLEAR /* clear only */
+} HTC_ENDPOINT_STAT_ACTION;
+
+ /* endpoint statistics */
+typedef struct _HTC_ENDPOINT_STATS {
+ A_UINT32 TxCreditLowIndications; /* number of times the host set the credit-low flag in a send message on
+ this endpoint */
+ A_UINT32 TxIssued; /* running count of TX packets issued */
+ A_UINT32 TxCreditRpts; /* running count of total credit reports received for this endpoint */
+ A_UINT32 TxCreditRptsFromRx;
+ A_UINT32 TxCreditRptsFromOther;
+ A_UINT32 TxCreditRptsFromEp0;
+ A_UINT32 TxCreditsFromRx; /* count of credits received via Rx packets on this endpoint */
+ A_UINT32 TxCreditsFromOther; /* count of credits received via another endpoint */
+ A_UINT32 TxCreditsFromEp0; /* count of credits received via another endpoint */
+ A_UINT32 TxCreditsConsummed; /* count of consummed credits */
+ A_UINT32 TxCreditsReturned; /* count of credits returned */
+ A_UINT32 RxReceived; /* count of RX packets received */
+ A_UINT32 RxLookAheads; /* count of lookahead records
+ found in messages received on this endpoint */
+} HTC_ENDPOINT_STATS;
+
+/* ------ Function Prototypes ------ */
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Initialize HTC
+ @function name: HTCInit
+ @input: pInfo - initialization information
+ @output:
+ @return: A_OK on success
+ @notes: The caller initializes global HTC state and registers various instance
+ notification callbacks (see HTC_INIT_INFO).
+
+ @example:
+ @see also: HTCShutdown
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCInit(HTC_INIT_INFO *pInfo);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Get the underlying HIF device handle
+ @function name: HTCGetHifDevice
+ @input: HTCHandle - handle passed into the AddInstance callback
+ @output:
+ @return: opaque HIF device handle usable in HIF API calls.
+ @notes:
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void *HTCGetHifDevice(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Set the associated instance for the HTC handle
+ @function name: HTCSetInstance
+ @input: HTCHandle - handle passed into the AddInstance callback
+ Instance - caller supplied instance object
+ @output:
+ @return:
+ @notes: Caller must set the instance information for the HTC handle in order to receive
+ notifications for instance deletion (DeleteInstance callback is called) and for target
+ failure notification.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCSetInstance(HTC_HANDLE HTCHandle, void *Instance);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Set credit distribution parameters
+ @function name: HTCSetCreditDistribution
+ @input: HTCHandle - HTC handle
+ pCreditDistCont - caller supplied context to pass into distribution functions
+ CreditDistFunc - Distribution function callback
+ CreditDistInit - Credit Distribution initialization callback
+ ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
+ priority
+ ListLength - number of elements in ServicePriorityOrder
+ @output:
+ @return:
+ @notes: The user can set a custom credit distribution function to handle special requirements
+ for each endpoint. A default credit distribution routine can be used by setting
+ CreditInitFunc to NULL. The default credit distribution is only provided for simple
+ "fair" credit distribution without regard to any prioritization.
+
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
+ void *pCreditDistContext,
+ HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
+ HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
+ HTC_SERVICE_ID ServicePriorityOrder[],
+ int ListLength);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Wait for the target to indicate the HTC layer is ready
+ @function name: HTCWaitTarget
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: This API blocks until the target responds with an HTC ready message.
+ The caller should not connect services until the target has indicated it is
+ ready.
+ @example:
+ @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Start target service communications
+ @function name: HTCStart
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: This API indicates to the target that the service connection phase is complete
+ and the target can freely start all connected services. This API should only be
+ called AFTER all service connections have been made. TCStart will issue a
+ SETUP_COMPLETE message to the target to indicate that all service connections
+ have been made and the target can start communicating over the endpoints.
+ @example:
+ @see also: HTCConnectService
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCStart(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Add receive packet to HTC
+ @function name: HTCAddReceivePkt
+ @input: HTCHandle - HTC handle
+ pPacket - HTC receive packet to add
+ @output:
+ @return: A_OK on success
+ @notes: user must supply HTC packets for capturing incomming HTC frames. The caller
+ must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
+ macro.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCAddReceivePkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Connect to an HTC service
+ @function name: HTCConnectService
+ @input: HTCHandle - HTC handle
+ pReq - connection details
+ @output: pResp - connection response
+ @return:
+ @notes: Service connections must be performed before HTCStart. User provides callback handlers
+ for various endpoint events.
+ @example:
+ @see also: HTCStart
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCConnectService(HTC_HANDLE HTCHandle,
+ HTC_SERVICE_CONNECT_REQ *pReq,
+ HTC_SERVICE_CONNECT_RESP *pResp);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Send an HTC packet
+ @function name: HTCSendPkt
+ @input: HTCHandle - HTC handle
+ pPacket - packet to send
+ @output:
+ @return: A_OK
+ @notes: Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
+ This interface is fully asynchronous. On error, HTC SendPkt will
+ call the registered Endpoint callback to cleanup the packet.
+ @example:
+ @see also: HTCFlushEndpoint
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_STATUS HTCSendPkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Stop HTC service communications
+ @function name: HTCStop
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: HTC communications is halted. All receive and pending TX packets will
+ be flushed.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCStop(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Shutdown HTC
+ @function name: HTCShutdown
+ @input:
+ @output:
+ @return:
+ @notes: This cleans up all resources allocated by HTCInit().
+ @example:
+ @see also: HTCInit
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCShutDown(void);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Flush pending TX packets
+ @function name: HTCFlushEndpoint
+ @input: HTCHandle - HTC handle
+ Endpoint - Endpoint to flush
+ Tag - flush tag
+ @output:
+ @return:
+ @notes: The Tag parameter is used to selectively flush packets with matching tags.
+ The value of 0 forces all packets to be flush regardless of tag.
+ @example:
+ @see also: HTCSendPkt
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCFlushEndpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint, HTC_TX_TAG Tag);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Dump credit distribution state
+ @function name: HTCDumpCreditStates
+ @input: HTCHandle - HTC handle
+ @output:
+ @return:
+ @notes: This dumps all credit distribution information to the debugger
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCDumpCreditStates(HTC_HANDLE HTCHandle);
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Indicate a traffic activity change on an endpoint
+ @function name: HTCIndicateActivityChange
+ @input: HTCHandle - HTC handle
+ Endpoint - endpoint in which activity has changed
+ Active - TRUE if active, FALSE if it has become inactive
+ @output:
+ @return:
+ @notes: This triggers the registered credit distribution function to
+ re-adjust credits for active/inactive endpoints.
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+void HTCIndicateActivityChange(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ A_BOOL Active);
+
+/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ @desc: Get endpoint statistics
+ @function name: HTCGetEndpointStatistics
+ @input: HTCHandle - HTC handle
+ Endpoint - Endpoint identifier
+ Action - action to take with statistics
+ @output:
+ pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
+
+ @return: TRUE if statistics profiling is enabled, otherwise FALSE.
+
+ @notes: Statistics is a compile-time option and this function may return FALSE
+ if HTC is not compiled with profiling.
+
+ The caller can specify the statistic "action" to take when sampling
+ the statistics. This includes:
+
+ HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
+ HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
+ are cleared.
+ HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
+ pStats
+
+ @example:
+ @see also:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
+ HTC_ENDPOINT_ID Endpoint,
+ HTC_ENDPOINT_STAT_ACTION Action,
+ HTC_ENDPOINT_STATS *pStats);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HTC_API_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/htc.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+
+#ifndef __HTC_H__
+#define __HTC_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+
+#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
+ (((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
+
+/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
+ * structure using only the type and field name.
+ * Use these macros if there is the potential for unaligned buffer accesses. */
+#define A_GET_UINT16_FIELD(p,type,field) \
+ ASSEMBLE_UNALIGNED_UINT16(p,\
+ A_OFFSETOF(type,field) + 1, \
+ A_OFFSETOF(type,field))
+
+#define A_SET_UINT16_FIELD(p,type,field,value) \
+{ \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
+}
+
+#define A_GET_UINT8_FIELD(p,type,field) \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
+
+#define A_SET_UINT8_FIELD(p,type,field,value) \
+ ((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
+
+/****** DANGER DANGER ***************
+ *
+ * The frame header length and message formats defined herein were
+ * selected to accommodate optimal alignment for target processing. This reduces code
+ * size and improves performance.
+ *
+ * Any changes to the header length may alter the alignment and cause exceptions
+ * on the target. When adding to the message structures insure that fields are
+ * properly aligned.
+ *
+ */
+
+/* HTC frame header */
+typedef PREPACK struct _HTC_FRAME_HDR{
+ /* do not remove or re-arrange these fields, these are minimally required
+ * to take advantage of 4-byte lookaheads in some hardware implementations */
+ A_UINT8 EndpointID;
+ A_UINT8 Flags;
+ A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */
+
+ /***** end of 4-byte lookahead ****/
+
+ A_UINT8 ControlBytes[2];
+
+ /* message payload starts after the header */
+
+} POSTPACK HTC_FRAME_HDR;
+
+/* frame header flags */
+#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
+#define HTC_FLAGS_RECV_TRAILER (1 << 1)
+
+
+#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
+#define HTC_MAX_TRAILER_LENGTH 255
+#define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR))
+
+/* HTC control message IDs */
+typedef enum {
+ HTC_MSG_READY_ID = 1,
+ HTC_MSG_CONNECT_SERVICE_ID = 2,
+ HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3,
+ HTC_MSG_SETUP_COMPLETE_ID = 4,
+} HTC_MSG_IDS;
+
+#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
+
+/* base message ID header */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+} POSTPACK HTC_UNKNOWN_MSG;
+
+/* HTC ready message
+ * direction : target-to-host */
+typedef PREPACK struct {
+ A_UINT16 MessageID; /* ID */
+ A_UINT16 CreditCount; /* number of credits the target can offer */
+ A_UINT16 CreditSize; /* size of each credit */
+ A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */
+ A_UINT8 _Pad1;
+} POSTPACK HTC_READY_MSG;
+
+#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
+
+/* connect service
+ * direction : host-to-target */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ A_UINT16 ServiceID; /* service ID of the service to connect to */
+ A_UINT16 ConnectionFlags; /* connection flags */
+
+#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
+ the host needs credits */
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
+
+ A_UINT8 ServiceMetaLength; /* length of meta data that follows */
+ A_UINT8 _Pad1;
+
+ /* service-specific meta data starts after the header */
+
+} POSTPACK HTC_CONNECT_SERVICE_MSG;
+
+/* connect response
+ * direction : target-to-host */
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ A_UINT16 ServiceID; /* service ID that the connection request was made */
+ A_UINT8 Status; /* service connection status */
+ A_UINT8 EndpointID; /* assigned endpoint ID */
+ A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */
+ A_UINT8 ServiceMetaLength; /* length of meta data that follows */
+ A_UINT8 _Pad1;
+
+ /* service-specific meta data starts after the header */
+
+} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
+
+typedef PREPACK struct {
+ A_UINT16 MessageID;
+ /* currently, no other fields */
+} POSTPACK HTC_SETUP_COMPLETE_MSG;
+
+
+/* connect response status codes */
+#define HTC_SERVICE_SUCCESS 0 /* success */
+#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
+#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
+#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
+#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
+ endpoints */
+
+/* report record IDs */
+typedef enum {
+ HTC_RECORD_NULL = 0,
+ HTC_RECORD_CREDITS = 1,
+ HTC_RECORD_LOOKAHEAD = 2,
+} HTC_RPT_IDS;
+
+typedef PREPACK struct {
+ A_UINT8 RecordID; /* Record ID */
+ A_UINT8 Length; /* Length of record */
+} POSTPACK HTC_RECORD_HDR;
+
+typedef PREPACK struct {
+ A_UINT8 EndpointID; /* Endpoint that owns these credits */
+ A_UINT8 Credits; /* credits to report since last report */
+} POSTPACK HTC_CREDIT_REPORT;
+
+typedef PREPACK struct {
+ A_UINT8 PreValid; /* pre valid guard */
+ A_UINT8 LookAhead[4]; /* 4 byte lookahead */
+ A_UINT8 PostValid; /* post valid guard */
+
+ /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
+ * The PreValid bytes must equal the inverse of the PostValid byte */
+
+} POSTPACK HTC_LOOKAHEAD_REPORT;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+
+#endif /* __HTC_H__ */
+
--- /dev/null
+++ b/drivers/ar6000/include/htc_packet.h
@@ -0,0 +1,138 @@
+/*
+ *
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifndef HTC_PACKET_H_
+#define HTC_PACKET_H_
+
+
+#include "dl_list.h"
+
+struct _HTC_PACKET;
+
+typedef void (* HTC_PACKET_COMPLETION)(void *,struct _HTC_PACKET *);
+
+typedef A_UINT16 HTC_TX_TAG;
+
+typedef struct _HTC_TX_PACKET_INFO {
+ HTC_TX_TAG Tag; /* tag used to selective flush packets */
+} HTC_TX_PACKET_INFO;
+
+#define HTC_TX_PACKET_TAG_ALL 0 /* a tag of zero is reserved and used to flush ALL packets */
+#define HTC_TX_PACKET_TAG_INTERNAL 1 /* internal tags start here */
+#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9) /* user-defined tags start here */
+
+typedef struct _HTC_RX_PACKET_INFO {
+ A_UINT32 Unused; /* for future use and to make compilers happy */
+} HTC_RX_PACKET_INFO;
+
+/* wrapper around endpoint-specific packets */
+typedef struct _HTC_PACKET {
+ DL_LIST ListLink; /* double link */
+ void *pPktContext; /* caller's per packet specific context */
+
+ A_UINT8 *pBufferStart; /* the true buffer start , the caller can
+ store the real buffer start here. In
+ receive callbacks, the HTC layer sets pBuffer
+ to the start of the payload past the header. This
+ field allows the caller to reset pBuffer when it
+ recycles receive packets back to HTC */
+ /*
+ * Pointer to the start of the buffer. In the transmit
+ * direction this points to the start of the payload. In the
+ * receive direction, however, the buffer when queued up
+ * points to the start of the HTC header but when returned
+ * to the caller points to the start of the payload
+ */
+ A_UINT8 *pBuffer; /* payload start (RX/TX) */
+ A_UINT32 BufferLength; /* length of buffer */
+ A_UINT32 ActualLength; /* actual length of payload */
+ int Endpoint; /* endpoint that this packet was sent/recv'd from */
+ A_STATUS Status; /* completion status */
+ union {
+ HTC_TX_PACKET_INFO AsTx; /* Tx Packet specific info */
+ HTC_RX_PACKET_INFO AsRx; /* Rx Packet specific info */
+ } PktInfo;
+
+ /* the following fields are for internal HTC use */
+ HTC_PACKET_COMPLETION Completion; /* completion */
+ void *pContext; /* HTC private completion context */
+ A_UINT32 HTCReserved; /* reserved */
+} HTC_PACKET;
+
+
+
+#define COMPLETE_HTC_PACKET(p,status) \
+{ \
+ (p)->Status = (status); \
+ (p)->Completion((p)->pContext,(p)); \
+}
+
+#define INIT_HTC_PACKET_INFO(p,b,len) \
+{ \
+ (p)->pBufferStart = (b); \
+ (p)->BufferLength = (len); \
+}
+
+/* macro to set an initial RX packet for refilling HTC */
+#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
+{ \
+ (p)->pPktContext = (c); \
+ (p)->pBuffer = (b); \
+ (p)->pBufferStart = (b); \
+ (p)->BufferLength = (len); \
+ (p)->Endpoint = (ep); \
+}
+
+/* fast macro to recycle an RX packet that will be re-queued to HTC */
+#define HTC_PACKET_RESET_RX(p) \
+ (p)->pBuffer = (p)->pBufferStart
+
+/* macro to set packet parameters for TX */
+#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag) \
+{ \
+ (p)->pPktContext = (c); \
+ (p)->pBuffer = (b); \
+ (p)->ActualLength = (len); \
+ (p)->Endpoint = (ep); \
+ (p)->PktInfo.AsTx.Tag = (tag); \
+}
+
+/* HTC Packet Queueing Macros */
+typedef DL_LIST HTC_PACKET_QUEUE;
+/* initialize queue */
+#define INIT_HTC_PACKET_QUEUE(pQ) DL_LIST_INIT((pQ))
+/* enqueue HTC packet to the tail of the queue */
+#define HTC_PACKET_ENQUEUE(pQ,p) DL_ListInsertTail((pQ),&(p)->ListLink)
+/* test if a queue is empty */
+#define HTC_QUEUE_EMPTY(pQ) DL_LIST_IS_EMPTY((pQ))
+/* get packet at head without removing it */
+#define HTC_GET_PKT_AT_HEAD(pQ) A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(pQ)),HTC_PACKET,ListLink);
+/* remove a packet from the current list it is linked to */
+#define HTC_PACKET_REMOVE(p) DL_ListRemove(&(p)->ListLink)
+
+/* dequeue an HTC packet from the head of the queue */
+static INLINE HTC_PACKET *HTC_PACKET_DEQUEUE(HTC_PACKET_QUEUE *queue) {
+ DL_LIST *pItem = DL_ListRemoveItemFromHead(queue);
+ if (pItem != NULL) {
+ return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
+ }
+ return NULL;
+}
+
+#endif /*HTC_PACKET_H_*/
--- /dev/null
+++ b/drivers/ar6000/include/htc_services.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef __HTC_SERVICES_H__
+#define __HTC_SERVICES_H__
+
+/* Current service IDs */
+
+typedef enum {
+ RSVD_SERVICE_GROUP = 0,
+ WMI_SERVICE_GROUP = 1,
+
+ HTC_TEST_GROUP = 254,
+ HTC_SERVICE_GROUP_LAST = 255
+}HTC_SERVICE_GROUP_IDS;
+
+#define MAKE_SERVICE_ID(group,index) \
+ (int)(((int)group << 8) | (int)(index))
+
+/* NOTE: service ID of 0x0000 is reserved and should never be used */
+#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
+#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
+#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
+#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
+#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
+#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
+#define WMI_MAX_SERVICES 5
+
+/* raw stream service (i.e. flash, tcmd, calibration apps) */
+#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
+
+#endif /*HTC_SERVICES_H_*/
--- /dev/null
+++ b/drivers/ar6000/include/ieee80211.h
@@ -0,0 +1,342 @@
+/*-
+ * Copyright (c) 2001 Atsushi Onoe
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
+ * Copyright (c) 2006 Atheros Communications, Inc.
+ *
+ * Wireless Network driver for Atheros AR6001
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _NET80211_IEEE80211_H_
+#define _NET80211_IEEE80211_H_
+
+#include "athstartpack.h"
+
+/*
+ * 802.11 protocol definitions.
+ */
+
+#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */
+/* is 802.11 address multicast/broadcast? */
+#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01)
+#define IEEE80211_ADDR_EQ(addr1, addr2) \
+ (A_MEMCMP(addr1, addr2, IEEE80211_ADDR_LEN) == 0)
+
+#define IEEE80211_KEYBUF_SIZE 16
+#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx and rx */
+
+/*
+ * NB: these values are ordered carefully; there are lots of
+ * of implications in any reordering. In particular beware
+ * that 4 is not used to avoid conflicting with IEEE80211_F_PRIVACY.
+ */
+#define IEEE80211_CIPHER_WEP 0
+#define IEEE80211_CIPHER_TKIP 1
+#define IEEE80211_CIPHER_AES_OCB 2
+#define IEEE80211_CIPHER_AES_CCM 3
+#define IEEE80211_CIPHER_CKIP 5
+#define IEEE80211_CIPHER_CCKM_KRK 6
+#define IEEE80211_CIPHER_NONE 7 /* pseudo value */
+
+#define IEEE80211_CIPHER_MAX (IEEE80211_CIPHER_NONE+1)
+
+#define IEEE80211_IS_VALID_WEP_CIPHER_LEN(len) \
+ (((len) == 5) || ((len) == 13) || ((len) == 16))
+
+
+
+/*
+ * generic definitions for IEEE 802.11 frames
+ */
+PREPACK struct ieee80211_frame {
+ A_UINT8 i_fc[2];
+ A_UINT8 i_dur[2];
+ A_UINT8 i_addr1[IEEE80211_ADDR_LEN];
+ A_UINT8 i_addr2[IEEE80211_ADDR_LEN];
+ A_UINT8 i_addr3[IEEE80211_ADDR_LEN];
+ A_UINT8 i_seq[2];
+ /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */
+ /* see below */
+} POSTPACK;
+
+#define IEEE80211_FC0_VERSION_MASK 0x03
+#define IEEE80211_FC0_VERSION_SHIFT 0
+#define IEEE80211_FC0_VERSION_0 0x00
+#define IEEE80211_FC0_TYPE_MASK 0x0c
+#define IEEE80211_FC0_TYPE_SHIFT 2
+#define IEEE80211_FC0_TYPE_MGT 0x00
+#define IEEE80211_FC0_TYPE_CTL 0x04
+#define IEEE80211_FC0_TYPE_DATA 0x08
+
+#define IEEE80211_FC0_SUBTYPE_MASK 0xf0
+#define IEEE80211_FC0_SUBTYPE_SHIFT 4
+/* for TYPE_MGT */
+#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00
+#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10
+#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20
+#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30
+#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40
+#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50
+#define IEEE80211_FC0_SUBTYPE_BEACON 0x80
+#define IEEE80211_FC0_SUBTYPE_ATIM 0x90
+#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0
+#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0
+#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0
+/* for TYPE_CTL */
+#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0
+#define IEEE80211_FC0_SUBTYPE_RTS 0xb0
+#define IEEE80211_FC0_SUBTYPE_CTS 0xc0
+#define IEEE80211_FC0_SUBTYPE_ACK 0xd0
+#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0
+#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0
+/* for TYPE_DATA (bit combination) */
+#define IEEE80211_FC0_SUBTYPE_DATA 0x00
+#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10
+#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20
+#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30
+#define IEEE80211_FC0_SUBTYPE_NODATA 0x40
+#define IEEE80211_FC0_SUBTYPE_CFACK 0x50
+#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60
+#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70
+#define IEEE80211_FC0_SUBTYPE_QOS 0x80
+#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0
+
+#define IEEE80211_FC1_DIR_MASK 0x03
+#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */
+#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */
+#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */
+#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */
+
+#define IEEE80211_FC1_MORE_FRAG 0x04
+#define IEEE80211_FC1_RETRY 0x08
+#define IEEE80211_FC1_PWR_MGT 0x10
+#define IEEE80211_FC1_MORE_DATA 0x20
+#define IEEE80211_FC1_WEP 0x40
+#define IEEE80211_FC1_ORDER 0x80
+
+#define IEEE80211_SEQ_FRAG_MASK 0x000f
+#define IEEE80211_SEQ_FRAG_SHIFT 0
+#define IEEE80211_SEQ_SEQ_MASK 0xfff0
+#define IEEE80211_SEQ_SEQ_SHIFT 4
+
+#define IEEE80211_NWID_LEN 32
+
+/*
+ * 802.11 rate set.
+ */
+#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */
+#define IEEE80211_RATE_MAXSIZE 15 /* max rates we'll handle */
+
+#define WMM_NUM_AC 4 /* 4 AC categories */
+
+#define WMM_PARAM_ACI_M 0x60 /* Mask for ACI field */
+#define WMM_PARAM_ACI_S 5 /* Shift for ACI field */
+#define WMM_PARAM_ACM_M 0x10 /* Mask for ACM bit */
+#define WMM_PARAM_ACM_S 4 /* Shift for ACM bit */
+#define WMM_PARAM_AIFSN_M 0x0f /* Mask for aifsn field */
+#define WMM_PARAM_LOGCWMIN_M 0x0f /* Mask for CwMin field (in log) */
+#define WMM_PARAM_LOGCWMAX_M 0xf0 /* Mask for CwMax field (in log) */
+#define WMM_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */
+
+#define WMM_AC_TO_TID(_ac) ( \
+ ((_ac) == WMM_AC_VO) ? 6 : \
+ ((_ac) == WMM_AC_VI) ? 5 : \
+ ((_ac) == WMM_AC_BK) ? 1 : \
+ 0)
+
+#define TID_TO_WMM_AC(_tid) ( \
+ ((_tid) < 1) ? WMM_AC_BE : \
+ ((_tid) < 3) ? WMM_AC_BK : \
+ ((_tid) < 6) ? WMM_AC_VI : \
+ WMM_AC_VO)
+/*
+ * Management information element payloads.
+ */
+
+enum {
+ IEEE80211_ELEMID_SSID = 0,
+ IEEE80211_ELEMID_RATES = 1,
+ IEEE80211_ELEMID_FHPARMS = 2,
+ IEEE80211_ELEMID_DSPARMS = 3,
+ IEEE80211_ELEMID_CFPARMS = 4,
+ IEEE80211_ELEMID_TIM = 5,
+ IEEE80211_ELEMID_IBSSPARMS = 6,
+ IEEE80211_ELEMID_COUNTRY = 7,
+ IEEE80211_ELEMID_CHALLENGE = 16,
+ /* 17-31 reserved for challenge text extension */
+ IEEE80211_ELEMID_PWRCNSTR = 32,
+ IEEE80211_ELEMID_PWRCAP = 33,
+ IEEE80211_ELEMID_TPCREQ = 34,
+ IEEE80211_ELEMID_TPCREP = 35,
+ IEEE80211_ELEMID_SUPPCHAN = 36,
+ IEEE80211_ELEMID_CHANSWITCH = 37,
+ IEEE80211_ELEMID_MEASREQ = 38,
+ IEEE80211_ELEMID_MEASREP = 39,
+ IEEE80211_ELEMID_QUIET = 40,
+ IEEE80211_ELEMID_IBSSDFS = 41,
+ IEEE80211_ELEMID_ERP = 42,
+ IEEE80211_ELEMID_RSN = 48,
+ IEEE80211_ELEMID_XRATES = 50,
+ IEEE80211_ELEMID_TPC = 150,
+ IEEE80211_ELEMID_CCKM = 156,
+ IEEE80211_ELEMID_VENDOR = 221, /* vendor private */
+};
+
+#define ATH_OUI 0x7f0300 /* Atheros OUI */
+#define ATH_OUI_TYPE 0x01
+#define ATH_OUI_SUBTYPE 0x01
+#define ATH_OUI_VERSION 0x00
+
+#define WPA_OUI 0xf25000
+#define WPA_OUI_TYPE 0x01
+#define WPA_VERSION 1 /* current supported version */
+
+#define WPA_CSE_NULL 0x00
+#define WPA_CSE_WEP40 0x01
+#define WPA_CSE_TKIP 0x02
+#define WPA_CSE_CCMP 0x04
+#define WPA_CSE_WEP104 0x05
+
+#define WPA_ASE_NONE 0x00
+#define WPA_ASE_8021X_UNSPEC 0x01
+#define WPA_ASE_8021X_PSK 0x02
+
+#define RSN_OUI 0xac0f00
+#define RSN_VERSION 1 /* current supported version */
+
+#define RSN_CSE_NULL 0x00
+#define RSN_CSE_WEP40 0x01
+#define RSN_CSE_TKIP 0x02
+#define RSN_CSE_WRAP 0x03
+#define RSN_CSE_CCMP 0x04
+#define RSN_CSE_WEP104 0x05
+
+#define RSN_ASE_NONE 0x00
+#define RSN_ASE_8021X_UNSPEC 0x01
+#define RSN_ASE_8021X_PSK 0x02
+
+#define RSN_CAP_PREAUTH 0x01
+
+#define WMM_OUI 0xf25000
+#define WMM_OUI_TYPE 0x02
+#define WMM_INFO_OUI_SUBTYPE 0x00
+#define WMM_PARAM_OUI_SUBTYPE 0x01
+#define WMM_VERSION 1
+
+/* WMM stream classes */
+#define WMM_NUM_AC 4
+#define WMM_AC_BE 0 /* best effort */
+#define WMM_AC_BK 1 /* background */
+#define WMM_AC_VI 2 /* video */
+#define WMM_AC_VO 3 /* voice */
+
+/* TSPEC related */
+#define ACTION_CATEGORY_CODE_TSPEC 17
+#define ACTION_CODE_TSPEC_ADDTS 0
+#define ACTION_CODE_TSPEC_ADDTS_RESP 1
+#define ACTION_CODE_TSPEC_DELTS 2
+
+typedef enum {
+ TSPEC_STATUS_CODE_ADMISSION_ACCEPTED = 0,
+ TSPEC_STATUS_CODE_ADDTS_INVALID_PARAMS = 0x1,
+ TSPEC_STATUS_CODE_ADDTS_REQUEST_REFUSED = 0x3,
+ TSPEC_STATUS_CODE_UNSPECIFIED_QOS_RELATED_FAILURE = 0xC8,
+ TSPEC_STATUS_CODE_REQUESTED_REFUSED_POLICY_CONFIGURATION = 0xC9,
+ TSPEC_STATUS_CODE_INSUFFCIENT_BANDWIDTH = 0xCA,
+ TSPEC_STATUS_CODE_INVALID_PARAMS = 0xCB,
+ TSPEC_STATUS_CODE_DELTS_SENT = 0x30,
+ TSPEC_STATUS_CODE_DELTS_RECV = 0x31,
+} TSPEC_STATUS_CODE;
+
+/*
+ * WMM/802.11e Tspec Element
+ */
+typedef PREPACK struct wmm_tspec_ie_t {
+ A_UINT8 elementId;
+ A_UINT8 len;
+ A_UINT8 oui[3];
+ A_UINT8 ouiType;
+ A_UINT8 ouiSubType;
+ A_UINT8 version;
+ A_UINT16 tsInfo_info;
+ A_UINT8 tsInfo_reserved;
+ A_UINT16 nominalMSDU;
+ A_UINT16 maxMSDU;
+ A_UINT32 minServiceInt;
+ A_UINT32 maxServiceInt;
+ A_UINT32 inactivityInt;
+ A_UINT32 suspensionInt;
+ A_UINT32 serviceStartTime;
+ A_UINT32 minDataRate;
+ A_UINT32 meanDataRate;
+ A_UINT32 peakDataRate;
+ A_UINT32 maxBurstSize;
+ A_UINT32 delayBound;
+ A_UINT32 minPhyRate;
+ A_UINT16 sba;
+ A_UINT16 mediumTime;
+} POSTPACK WMM_TSPEC_IE;
+
+
+/*
+ * BEACON management packets
+ *
+ * octet timestamp[8]
+ * octet beacon interval[2]
+ * octet capability information[2]
+ * information element
+ * octet elemid
+ * octet length
+ * octet information[length]
+ */
+
+#define IEEE80211_BEACON_INTERVAL(beacon) \
+ ((beacon)[8] | ((beacon)[9] << 8))
+#define IEEE80211_BEACON_CAPABILITY(beacon) \
+ ((beacon)[10] | ((beacon)[11] << 8))
+
+#define IEEE80211_CAPINFO_ESS 0x0001
+#define IEEE80211_CAPINFO_IBSS 0x0002
+#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004
+#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008
+#define IEEE80211_CAPINFO_PRIVACY 0x0010
+#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020
+#define IEEE80211_CAPINFO_PBCC 0x0040
+#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080
+/* bits 8-9 are reserved */
+#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400
+#define IEEE80211_CAPINFO_APSD 0x0800
+/* bit 12 is reserved */
+#define IEEE80211_CAPINFO_DSSSOFDM 0x2000
+/* bits 14-15 are reserved */
+
+/*
+ * Authentication Modes
+ */
+
+enum ieee80211_authmode {
+ IEEE80211_AUTH_NONE = 0,
+ IEEE80211_AUTH_OPEN = 1,
+ IEEE80211_AUTH_SHARED = 2,
+ IEEE80211_AUTH_8021X = 3,
+ IEEE80211_AUTH_AUTO = 4, /* auto-select/accept */
+ /* NB: these are used only for ioctls */
+ IEEE80211_AUTH_WPA = 5, /* WPA/RSN w/ 802.1x */
+ IEEE80211_AUTH_WPA_PSK = 6, /* WPA/RSN w/ PSK */
+ IEEE80211_AUTH_WPA_CCKM = 7, /* WPA/RSN IE w/ CCKM */
+};
+
+#include "athendpack.h"
+
+#endif /* _NET80211_IEEE80211_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/ieee80211_ioctl.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/os/linux/include/ieee80211_ioctl.h#1 $
+ */
+
+#ifndef _IEEE80211_IOCTL_H_
+#define _IEEE80211_IOCTL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Extracted from the MADWIFI net80211/ieee80211_ioctl.h
+ */
+
+/*
+ * WPA/RSN get/set key request. Specify the key/cipher
+ * type and whether the key is to be used for sending and/or
+ * receiving. The key index should be set only when working
+ * with global keys (use IEEE80211_KEYIX_NONE for ``no index'').
+ * Otherwise a unicast/pairwise key is specified by the bssid
+ * (on a station) or mac address (on an ap). They key length
+ * must include any MIC key data; otherwise it should be no
+ more than IEEE80211_KEYBUF_SIZE.
+ */
+struct ieee80211req_key {
+ u_int8_t ik_type; /* key/cipher type */
+ u_int8_t ik_pad;
+ u_int16_t ik_keyix; /* key index */
+ u_int8_t ik_keylen; /* key length in bytes */
+ u_int8_t ik_flags;
+#define IEEE80211_KEY_XMIT 0x01
+#define IEEE80211_KEY_RECV 0x02
+#define IEEE80211_KEY_DEFAULT 0x80 /* default xmit key */
+ u_int8_t ik_macaddr[IEEE80211_ADDR_LEN];
+ u_int64_t ik_keyrsc; /* key receive sequence counter */
+ u_int64_t ik_keytsc; /* key transmit sequence counter */
+ u_int8_t ik_keydata[IEEE80211_KEYBUF_SIZE+IEEE80211_MICBUF_SIZE];
+};
+/*
+ * Delete a key either by index or address. Set the index
+ * to IEEE80211_KEYIX_NONE when deleting a unicast key.
+ */
+struct ieee80211req_del_key {
+ u_int8_t idk_keyix; /* key index */
+ u_int8_t idk_macaddr[IEEE80211_ADDR_LEN];
+};
+/*
+ * MLME state manipulation request. IEEE80211_MLME_ASSOC
+ * only makes sense when operating as a station. The other
+ * requests can be used when operating as a station or an
+ * ap (to effect a station).
+ */
+struct ieee80211req_mlme {
+ u_int8_t im_op; /* operation to perform */
+#define IEEE80211_MLME_ASSOC 1 /* associate station */
+#define IEEE80211_MLME_DISASSOC 2 /* disassociate station */
+#define IEEE80211_MLME_DEAUTH 3 /* deauthenticate station */
+#define IEEE80211_MLME_AUTHORIZE 4 /* authorize station */
+#define IEEE80211_MLME_UNAUTHORIZE 5 /* unauthorize station */
+ u_int16_t im_reason; /* 802.11 reason code */
+ u_int8_t im_macaddr[IEEE80211_ADDR_LEN];
+};
+
+struct ieee80211req_addpmkid {
+ u_int8_t pi_bssid[IEEE80211_ADDR_LEN];
+ u_int8_t pi_enable;
+ u_int8_t pi_pmkid[16];
+};
+
+#define AUTH_ALG_OPEN_SYSTEM 0x01
+#define AUTH_ALG_SHARED_KEY 0x02
+#define AUTH_ALG_LEAP 0x04
+
+struct ieee80211req_authalg {
+ u_int8_t auth_alg;
+};
+
+/*
+ * Request to add an IE to a Management Frame
+ */
+enum{
+ IEEE80211_APPIE_FRAME_BEACON = 0,
+ IEEE80211_APPIE_FRAME_PROBE_REQ = 1,
+ IEEE80211_APPIE_FRAME_PROBE_RESP = 2,
+ IEEE80211_APPIE_FRAME_ASSOC_REQ = 3,
+ IEEE80211_APPIE_FRAME_ASSOC_RESP = 4,
+ IEEE80211_APPIE_NUM_OF_FRAME = 5
+};
+
+/*
+ * The Maximum length of the IE that can be added to a Management frame
+ */
+#define IEEE80211_APPIE_FRAME_MAX_LEN 78
+
+struct ieee80211req_getset_appiebuf {
+ u_int32_t app_frmtype; /* management frame type for which buffer is added */
+ u_int32_t app_buflen; /*application supplied buffer length */
+ u_int8_t app_buf[];
+};
+
+/*
+ * The following definitions are used by an application to set filter
+ * for receiving management frames
+ */
+enum {
+ IEEE80211_FILTER_TYPE_BEACON = 0x1,
+ IEEE80211_FILTER_TYPE_PROBE_REQ = 0x2,
+ IEEE80211_FILTER_TYPE_PROBE_RESP = 0x4,
+ IEEE80211_FILTER_TYPE_ASSOC_REQ = 0x8,
+ IEEE80211_FILTER_TYPE_ASSOC_RESP = 0x10,
+ IEEE80211_FILTER_TYPE_AUTH = 0x20,
+ IEEE80211_FILTER_TYPE_DEAUTH = 0x40,
+ IEEE80211_FILTER_TYPE_DISASSOC = 0x80,
+ IEEE80211_FILTER_TYPE_ALL = 0xFF /* used to check the valid filter bits */
+};
+
+struct ieee80211req_set_filter {
+ u_int32_t app_filterype; /* management frame filter type */
+};
+
+enum {
+ IEEE80211_PARAM_AUTHMODE = 3, /* Authentication Mode */
+ IEEE80211_PARAM_MCASTCIPHER = 5,
+ IEEE80211_PARAM_MCASTKEYLEN = 6, /* multicast key length */
+ IEEE80211_PARAM_UCASTCIPHER = 8,
+ IEEE80211_PARAM_UCASTKEYLEN = 9, /* unicast key length */
+ IEEE80211_PARAM_WPA = 10, /* WPA mode (0,1,2) */
+ IEEE80211_PARAM_ROAMING = 12, /* roaming mode */
+ IEEE80211_PARAM_PRIVACY = 13, /* privacy invoked */
+ IEEE80211_PARAM_COUNTERMEASURES = 14, /* WPA/TKIP countermeasures */
+ IEEE80211_PARAM_DROPUNENCRYPTED = 15, /* discard unencrypted frames */
+};
+
+/*
+ * Values for IEEE80211_PARAM_WPA
+ */
+#define WPA_MODE_WPA1 1
+#define WPA_MODE_WPA2 2
+#define WPA_MODE_AUTO 3
+#define WPA_MODE_NONE 4
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IEEE80211_IOCTL_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/ieee80211_node.h
@@ -0,0 +1,77 @@
+/*-
+ * Copyright (c) 2001 Atsushi Onoe
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
+ * Copyright (c) 2006 Atheros Communications, Inc.
+ *
+ * Wireless Network driver for Atheros AR6001
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef _IEEE80211_NODE_H_
+#define _IEEE80211_NODE_H_
+
+/*
+ * Node locking definitions.
+ */
+#define IEEE80211_NODE_LOCK_INIT(_nt) A_MUTEX_INIT(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_DESTROY(_nt)
+#define IEEE80211_NODE_LOCK(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_BH(_nt) A_MUTEX_LOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_UNLOCK_BH(_nt) A_MUTEX_UNLOCK(&(_nt)->nt_nodelock)
+#define IEEE80211_NODE_LOCK_ASSERT(_nt)
+
+/*
+ * Node reference counting definitions.
+ *
+ * ieee80211_node_initref initialize the reference count to 1
+ * ieee80211_node_incref add a reference
+ * ieee80211_node_decref remove a reference
+ * ieee80211_node_dectestref remove a reference and return 1 if this
+ * is the last reference, otherwise 0
+ * ieee80211_node_refcnt reference count for printing (only)
+ */
+#define ieee80211_node_initref(_ni) ((_ni)->ni_refcnt = 1)
+#define ieee80211_node_incref(_ni) ((_ni)->ni_refcnt++)
+#define ieee80211_node_decref(_ni) ((_ni)->ni_refcnt--)
+#define ieee80211_node_dectestref(_ni) (((_ni)->ni_refcnt--) == 0)
+#define ieee80211_node_refcnt(_ni) ((_ni)->ni_refcnt)
+
+#define IEEE80211_NODE_HASHSIZE 32
+/* simple hash is enough for variation of macaddr */
+#define IEEE80211_NODE_HASH(addr) \
+ (((const A_UINT8 *)(addr))[IEEE80211_ADDR_LEN - 1] % \
+ IEEE80211_NODE_HASHSIZE)
+
+/*
+ * Table of ieee80211_node instances. Each ieee80211com
+ * has at least one for holding the scan candidates.
+ * When operating as an access point or in ibss mode there
+ * is a second table for associated stations or neighbors.
+ */
+struct ieee80211_node_table {
+ void *nt_wmip; /* back reference */
+ A_MUTEX_T nt_nodelock; /* on node table */
+ struct bss *nt_node_first; /* information of all nodes */
+ struct bss *nt_node_last; /* information of all nodes */
+ struct bss *nt_hash[IEEE80211_NODE_HASHSIZE];
+ const char *nt_name; /* for debugging */
+ A_UINT32 nt_scangen; /* gen# for timeout scan */
+ A_TIMER nt_inact_timer;
+ A_UINT8 isTimerArmed; /* is the node timer armed */
+};
+
+#define WLAN_NODE_INACT_TIMEOUT_MSEC 10000
+
+#endif /* _IEEE80211_NODE_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/ini_dset.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+#ifndef _INI_DSET_H_
+#define _INI_DSET_H_
+
+/*
+ * Each of these represents a WHAL INI table, which consists
+ * of an "address column" followed by 1 or more "value columns".
+ *
+ * Software uses the base WHAL_INI_DATA_ID+column to access a
+ * DataSet that holds a particular column of data.
+ */
+typedef enum {
+ WHAL_INI_DATA_ID_NULL =0,
+ WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */
+ WHAL_INI_DATA_ID_COMMON =4, /* 5 */
+ WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */
+ WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */
+ WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */
+ WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */
+ WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */
+ WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */
+ WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */
+ WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
+
+ WHAL_INI_DATA_ID_MAX =25
+} WHAL_INI_DATA_ID;
+
+typedef PREPACK struct {
+ A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
+ A_UINT16 offset;
+ A_UINT32 newValue;
+} POSTPACK INI_DSET_REG_OVERRIDE;
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/include/regDb.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2005 Atheros Communications, Inc.
+ * All rights reserved.
+ *
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This module contains the header files for regulatory module,
+ * which include the DB schema and DB values.
+ * $Id:
+ */
+
+#ifndef __REG_DB_H__
+#define __REG_DB_H__
+
+#include "./regulatory/reg_dbschema.h"
+#include "./regulatory/reg_dbvalues.h"
+
+#endif /* __REG_DB_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/regdump.h
@@ -0,0 +1,33 @@
+#ifndef __REGDUMP_H__
+#define __REGDUMP_H__
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+#if defined(AR6001)
+#include "AR6001/AR6001_regdump.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/AR6002_regdump.h"
+#endif
+
+#if !defined(__ASSEMBLER__)
+/*
+ * Target CPU state at the time of failure is reflected
+ * in a register dump, which the Host can fetch through
+ * the diagnostic window.
+ */
+struct register_dump_s {
+ A_UINT32 target_id; /* Target ID */
+ A_UINT32 assline; /* Line number (if assertion failure) */
+ A_UINT32 pc; /* Program Counter at time of exception */
+ A_UINT32 badvaddr; /* Virtual address causing exception */
+ CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
+
+ /* Could copy top of stack here, too.... */
+};
+#endif /* __ASSEMBLER__ */
+#endif /* __REGDUMP_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/targaddrs.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef __TARGADDRS_H__
+#define __TARGADDRS_H__
+#if defined(AR6001)
+#include "AR6001/addrs.h"
+#endif
+#if defined(AR6002)
+#include "AR6002/addrs.h"
+#endif
+
+/*
+ * AR6K option bits, to enable/disable various features.
+ * By default, all option bits are 0.
+ * These bits can be set in LOCAL_SCRATCH register 0.
+ */
+#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
+#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
+#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
+#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
+#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
+#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
+#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
+#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
+
+/*
+ * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
+ * host_interest structure. It must match the address of the _host_interest
+ * symbol (see linker script).
+ *
+ * Host Interest is shared between Host and Target in order to coordinate
+ * between the two, and is intended to remain constant (with additions only
+ * at the end) across software releases.
+ */
+#define AR6001_HOST_INTEREST_ADDRESS 0x80000600
+#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
+
+#define HOST_INTEREST_MAX_SIZE 0x100
+
+#if !defined(__ASSEMBLER__)
+struct register_dump_s;
+struct dbglog_hdr_s;
+
+/*
+ * These are items that the Host may need to access
+ * via BMI or via the Diagnostic Window. The position
+ * of items in this structure must remain constant
+ * across firmware revisions!
+ *
+ * Types for each item must be fixed size across
+ * target and host platforms.
+ *
+ * More items may be added at the end.
+ */
+struct host_interest_s {
+ /*
+ * Pointer to application-defined area, if any.
+ * Set by Target application during startup.
+ */
+ A_UINT32 hi_app_host_interest; /* 0x00 */
+
+ /* Pointer to register dump area, valid after Target crash. */
+ A_UINT32 hi_failure_state; /* 0x04 */
+
+ /* Pointer to debug logging header */
+ A_UINT32 hi_dbglog_hdr; /* 0x08 */
+
+ /* Indicates whether or not flash is present on Target.
+ * NB: flash_is_present indicator is here not just
+ * because it might be of interest to the Host; but
+ * also because it's set early on by Target's startup
+ * asm code and we need it to have a special RAM address
+ * so that it doesn't get reinitialized with the rest
+ * of data.
+ */
+ A_UINT32 hi_flash_is_present; /* 0x0c */
+
+ /*
+ * General-purpose flag bits, similar to AR6000_OPTION_* flags.
+ * Can be used by application rather than by OS.
+ */
+ A_UINT32 hi_option_flag; /* 0x10 */
+
+ /*
+ * Boolean that determines whether or not to
+ * display messages on the serial port.
+ */
+ A_UINT32 hi_serial_enable; /* 0x14 */
+
+ /* Start address of Flash DataSet index, if any */
+ A_UINT32 hi_dset_list_head; /* 0x18 */
+
+ /* Override Target application start address */
+ A_UINT32 hi_app_start; /* 0x1c */
+
+ /* Clock and voltage tuning */
+ A_UINT32 hi_skip_clock_init; /* 0x20 */
+ A_UINT32 hi_core_clock_setting; /* 0x24 */
+ A_UINT32 hi_cpu_clock_setting; /* 0x28 */
+ A_UINT32 hi_system_sleep_setting; /* 0x2c */
+ A_UINT32 hi_xtal_control_setting; /* 0x30 */
+ A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
+ A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
+ A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
+ A_UINT32 hi_clock_info; /* 0x40 */
+
+ /*
+ * Flash configuration overrides, used only
+ * when firmware is not executing from flash.
+ * (When using flash, modify the global variables
+ * with equivalent names.)
+ */
+ A_UINT32 hi_bank0_addr_value; /* 0x44 */
+ A_UINT32 hi_bank0_read_value; /* 0x48 */
+ A_UINT32 hi_bank0_write_value; /* 0x4c */
+ A_UINT32 hi_bank0_config_value; /* 0x50 */
+
+ /* Pointer to Board Data */
+ A_UINT32 hi_board_data; /* 0x54 */
+ A_UINT32 hi_board_data_initialized; /* 0x58 */
+
+ A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
+
+ A_UINT32 hi_desired_baud_rate; /* 0x60 */
+ A_UINT32 hi_dbglog_config; /* 0x64 */
+ A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
+ A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
+
+ A_UINT32 hi_num_bpatch_streams; /* 0x70 */
+ A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
+
+ A_UINT32 hi_refclk_hz; /* 0x78 */
+};
+
+/* Bits defined in hi_option_flag */
+#define HI_OPTION_TIMER_WAR 1 /* not really used */
+
+/*
+ * Intended for use by Host software, this macro returns the Target RAM
+ * address of any item in the host_interest structure.
+ * Example: target_addr = AR6001_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
+ */
+#define AR6001_HOST_INTEREST_ITEM_ADDRESS(item) \
+ ((A_UINT32)&((((struct host_interest_s *)(AR6001_HOST_INTEREST_ADDRESS))->item)))
+
+#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
+ ((A_UINT32)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
+
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __TARGADDRS_H__ */
--- /dev/null
+++ b/drivers/ar6000/include/testcmd.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef TESTCMD_H_
+#define TESTCMD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ZEROES_PATTERN = 0,
+ ONES_PATTERN,
+ REPEATING_10,
+ PN7_PATTERN,
+ PN9_PATTERN,
+ PN15_PATTERN
+}TX_DATA_PATTERN;
+
+/* Continous tx
+ mode : TCMD_CONT_TX_OFF - Disabling continous tx
+ TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
+ TCMD_CONT_TX_FRAME- Enable continuous modulated tx
+ freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
+dataRate: 0 - 1 Mbps
+ 1 - 2 Mbps
+ 2 - 5.5 Mbps
+ 3 - 11 Mbps
+ 4 - 6 Mbps
+ 5 - 9 Mbps
+ 6 - 12 Mbps
+ 7 - 18 Mbps
+ 8 - 24 Mbps
+ 9 - 36 Mbps
+ 10 - 28 Mbps
+ 11 - 54 Mbps
+ txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
+antenna: 1 - one antenna
+ 2 - two antenna
+Note : Enable/disable continuous tx test cmd works only when target is awake.
+*/
+
+typedef enum {
+ TCMD_CONT_TX_OFF = 0,
+ TCMD_CONT_TX_SINE,
+ TCMD_CONT_TX_FRAME,
+ TCMD_CONT_TX_TX99,
+ TCMD_CONT_TX_TX100
+} TCMD_CONT_TX_MODE;
+
+typedef PREPACK struct {
+ A_UINT32 testCmdId;
+ A_UINT32 mode;
+ A_UINT32 freq;
+ A_UINT32 dataRate;
+ A_INT32 txPwr;
+ A_UINT32 antenna;
+ A_UINT32 enANI;
+ A_UINT32 scramblerOff;
+ A_UINT32 aifsn;
+ A_UINT16 pktSz;
+ A_UINT16 txPattern;
+} POSTPACK TCMD_CONT_TX;
+
+#define TCMD_TXPATTERN_ZERONE 0x1
+#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2
+
+/* Continuous Rx
+ act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
+ TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
+ address equal specified
+ mac address (set via act =3)
+ TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the
+ report from the last cont
+ Rx test)
+
+ TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
+ target. This Overrides
+ the default MAC address.)
+
+*/
+typedef enum {
+ TCMD_CONT_RX_PROMIS =0,
+ TCMD_CONT_RX_FILTER,
+ TCMD_CONT_RX_REPORT,
+ TCMD_CONT_RX_SETMAC
+} TCMD_CONT_RX_ACT;
+
+typedef PREPACK struct {
+ A_UINT32 testCmdId;
+ A_UINT32 act;
+ A_UINT32 enANI;
+ PREPACK union {
+ struct PREPACK TCMD_CONT_RX_PARA {
+ A_UINT32 freq;
+ A_UINT32 antenna;
+ } POSTPACK para;
+ struct PREPACK TCMD_CONT_RX_REPORT {
+ A_UINT32 totalPkt;
+ A_INT32 rssiInDBm;
+ } POSTPACK report;
+ struct PREPACK TCMD_CONT_RX_MAC {
+ A_UCHAR addr[ATH_MAC_LEN];
+ } POSTPACK mac;
+ } POSTPACK u;
+} POSTPACK TCMD_CONT_RX;
+
+/* Force sleep/wake test cmd
+ mode: TCMD_PM_WAKEUP - Wakeup the target
+ TCMD_PM_SLEEP - Force the target to sleep.
+ */
+typedef enum {
+ TCMD_PM_WAKEUP = 1, /* be consistent with target */
+ TCMD_PM_SLEEP
+} TCMD_PM_MODE;
+
+typedef PREPACK struct {
+ A_UINT32 testCmdId;
+ A_UINT32 mode;
+} POSTPACK TCMD_PM;
+
+typedef enum{
+ TCMD_CONT_TX_ID,
+ TCMD_CONT_RX_ID,
+ TCMD_PM_ID
+ } TCMD_ID;
+
+typedef PREPACK union {
+ TCMD_CONT_TX contTx;
+ TCMD_CONT_RX contRx;
+ TCMD_PM pm ;
+} POSTPACK TEST_CMD;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TESTCMD_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/wlan_api.h
@@ -0,0 +1,101 @@
+#ifndef _HOST_WLAN_API_H_
+#define _HOST_WLAN_API_H_
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file contains the API for the host wlan module
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/wlan_api.h#1 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ieee80211_node_table;
+struct ieee80211_frame;
+
+struct ieee80211_common_ie {
+ A_UINT16 ie_chan;
+ A_UINT8 *ie_tstamp;
+ A_UINT8 *ie_ssid;
+ A_UINT8 *ie_rates;
+ A_UINT8 *ie_xrates;
+ A_UINT8 *ie_country;
+ A_UINT8 *ie_wpa;
+ A_UINT8 *ie_rsn;
+ A_UINT8 *ie_wmm;
+ A_UINT8 *ie_ath;
+ A_UINT16 ie_capInfo;
+ A_UINT16 ie_beaconInt;
+ A_UINT8 *ie_tim;
+ A_UINT8 *ie_chswitch;
+ A_UINT8 ie_erp;
+ A_UINT8 *ie_wsc;
+};
+
+typedef struct bss {
+ A_UINT8 ni_macaddr[6];
+ A_UINT8 ni_snr;
+ A_INT16 ni_rssi;
+ struct bss *ni_list_next;
+ struct bss *ni_list_prev;
+ struct bss *ni_hash_next;
+ struct bss *ni_hash_prev;
+ struct ieee80211_common_ie ni_cie;
+ A_UINT8 *ni_buf;
+ struct ieee80211_node_table *ni_table;
+ A_UINT32 ni_refcnt;
+ int ni_scangen;
+ A_UINT32 ni_tstamp;
+} bss_t;
+
+typedef void wlan_node_iter_func(void *arg, bss_t *);
+
+bss_t *wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size);
+void wlan_node_free(bss_t *ni);
+void wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+ const A_UINT8 *macaddr);
+bss_t *wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr);
+void wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni);
+void wlan_free_allnodes(struct ieee80211_node_table *nt);
+void wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+ void *arg);
+
+void wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt);
+void wlan_node_table_reset(struct ieee80211_node_table *nt);
+void wlan_node_table_cleanup(struct ieee80211_node_table *nt);
+
+A_STATUS wlan_parse_beacon(A_UINT8 *buf, int framelen,
+ struct ieee80211_common_ie *cie);
+
+A_UINT16 wlan_ieee2freq(int chan);
+A_UINT32 wlan_freq2ieee(A_UINT16 freq);
+
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2);
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HOST_WLAN_API_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/wlan_dset.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2007 Atheros Communications, Inc.
+ * All rights reserved.
+ *
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ */
+
+#ifndef __WLAN_DSET_H__
+#define __WKAN_DSET_H__
+
+typedef PREPACK struct wow_config_dset {
+
+ A_UINT8 valid_dset;
+ A_UINT8 gpio_enable;
+ A_UINT16 gpio_pin;
+} POSTPACK WOW_CONFIG_DSET;
+
+#endif
--- /dev/null
+++ b/drivers/ar6000/include/wmi_api.h
@@ -0,0 +1,260 @@
+#ifndef _WMI_API_H_
+#define _WMI_API_H_
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file contains the definitions for the Wireless Module Interface (WMI).
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/include/wmi_api.h#2 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * IP QoS Field definitions according to 802.1p
+ */
+#define BEST_EFFORT_PRI 0
+#define BACKGROUND_PRI 1
+#define EXCELLENT_EFFORT_PRI 3
+#define CONTROLLED_LOAD_PRI 4
+#define VIDEO_PRI 5
+#define VOICE_PRI 6
+#define NETWORK_CONTROL_PRI 7
+#define MAX_NUM_PRI 8
+
+#define UNDEFINED_PRI (0xff)
+
+/* simple mapping of IP TOS field to a WMI priority stream
+ * this mapping was taken from the original linux driver implementation
+ * The operation maps the following
+ *
+ * */
+#define IP_TOS_TO_WMI_PRI(tos) \
+ ((WMI_PRI_STREAM_ID)(((tos) >> 1) & 0x03))
+
+#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000 /* 5 seconds */
+
+
+struct wmi_t;
+
+void *wmi_init(void *devt);
+
+void wmi_qos_state_init(struct wmi_t *wmip);
+void wmi_shutdown(struct wmi_t *wmip);
+A_UINT16 wmi_get_mapped_qos_queue(struct wmi_t *, A_UINT8);
+A_STATUS wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType);
+A_STATUS wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf);
+A_STATUS wmi_syncpoint(struct wmi_t *wmip);
+A_STATUS wmi_syncpoint_reset(struct wmi_t *wmip);
+WMI_PRI_STREAM_ID wmi_get_stream_id(struct wmi_t *wmip, A_UINT8 trafficClass);
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir, A_UINT8 up);
+
+A_STATUS wmi_control_rx(struct wmi_t *wmip, void *osbuf);
+void wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg);
+void wmi_free_allnodes(struct wmi_t *wmip);
+bss_t *wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr);
+
+
+typedef enum {
+ NO_SYNC_WMIFLAG = 0,
+ SYNC_BEFORE_WMIFLAG, /* transmit all queued data before cmd */
+ SYNC_AFTER_WMIFLAG, /* any new data waits until cmd execs */
+ SYNC_BOTH_WMIFLAG,
+ END_WMIFLAG /* end marker */
+} WMI_SYNC_FLAG;
+
+A_STATUS wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG flag);
+A_STATUS wmi_connect_cmd(struct wmi_t *wmip,
+ NETWORK_TYPE netType,
+ DOT11_AUTH_MODE dot11AuthMode,
+ AUTH_MODE authMode,
+ CRYPTO_TYPE pairwiseCrypto,
+ A_UINT8 pairwiseCryptoLen,
+ CRYPTO_TYPE groupCrypto,
+ A_UINT8 groupCryptoLen,
+ int ssidLength,
+ A_UCHAR *ssid,
+ A_UINT8 *bssid,
+ A_UINT16 channel,
+ A_UINT32 ctrl_flags);
+A_STATUS wmi_reconnect_cmd(struct wmi_t *wmip,
+ A_UINT8 *bssid,
+ A_UINT16 channel);
+A_STATUS wmi_disconnect_cmd(struct wmi_t *wmip);
+A_STATUS wmi_getrev_cmd(struct wmi_t *wmip);
+A_STATUS wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+ A_BOOL forceFgScan, A_BOOL isLegacy,
+ A_UINT32 homeDwellTime, A_UINT32 forceScanInterval);
+A_STATUS wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+ A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+ A_UINT16 minact_chdw_msec,
+ A_UINT16 maxact_chdw_msec, A_UINT16 pas_chdw_msec,
+ A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+ A_UINT32 max_dfsch_act_time);
+A_STATUS wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask);
+A_STATUS wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+ A_UINT8 ssidLength, A_UCHAR *ssid);
+A_STATUS wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons);
+A_STATUS wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmisstime, A_UINT16 bmissbeacons);
+A_STATUS wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+ A_UINT8 ieLen, A_UINT8 *ieInfo);
+A_STATUS wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode);
+A_STATUS wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+ A_UINT16 atim_windows, A_UINT16 timeout_value);
+A_STATUS wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+ A_UINT16 psPollNum, A_UINT16 dtimPolicy);
+A_STATUS wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout);
+A_STATUS wmi_sync_cmd(struct wmi_t *wmip, A_UINT8 syncNumber);
+A_STATUS wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *pstream);
+A_STATUS wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 streamID);
+A_STATUS wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate);
+A_STATUS wmi_get_bitrate_cmd(struct wmi_t *wmip);
+A_INT8 wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate);
+A_STATUS wmi_get_regDomain_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_channelList_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+ WMI_PHY_MODE mode, A_INT8 numChan,
+ A_UINT16 *channelList);
+
+A_STATUS wmi_set_snr_threshold_params(struct wmi_t *wmip,
+ WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd);
+A_STATUS wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd);
+A_STATUS wmi_clr_rssi_snr(struct wmi_t *wmip);
+A_STATUS wmi_set_lq_threshold_params(struct wmi_t *wmip,
+ WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd);
+A_STATUS wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold);
+A_STATUS wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status);
+
+A_STATUS wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 bitmask);
+
+A_STATUS wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie,
+ A_UINT32 source);
+A_STATUS wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+ A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+ A_UINT32 valid);
+A_STATUS wmi_get_stats_cmd(struct wmi_t *wmip);
+A_STATUS wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex,
+ CRYPTO_TYPE keyType, A_UINT8 keyUsage,
+ A_UINT8 keyLength,A_UINT8 *keyRSC,
+ A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl,
+ WMI_SYNC_FLAG sync_flag);
+A_STATUS wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk);
+A_STATUS wmi_delete_krk_cmd(struct wmi_t *wmip);
+A_STATUS wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex);
+A_STATUS wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+ WMI_SET_AKMP_PARAMS_CMD *akmpParams);
+A_STATUS wmi_get_pmkid_list_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+ WMI_SET_PMKID_LIST_CMD *pmkInfo);
+A_STATUS wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM);
+A_STATUS wmi_get_txPwr_cmd(struct wmi_t *wmip);
+A_STATUS wmi_switch_radio(struct wmi_t *wmip, A_UINT8 on);
+A_STATUS wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid);
+A_STATUS wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex);
+A_STATUS wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en);
+A_STATUS wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+ A_BOOL set);
+A_STATUS wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop,
+ A_UINT8 eCWmin, A_UINT8 eCWmax,
+ A_UINT8 aifsn);
+A_STATUS wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+ A_UINT8 trafficClass, A_UINT8 maxRetries,
+ A_UINT8 enableNotify);
+
+void wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid);
+
+A_STATUS wmi_get_roam_tbl_cmd(struct wmi_t *wmip);
+A_STATUS wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType);
+A_STATUS wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+ A_UINT8 size);
+A_STATUS wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+ WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+ A_UINT8 size);
+
+A_STATUS wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode);
+A_STATUS wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+ A_UINT8 frmType,
+ A_UINT8 *dstMacAddr,
+ A_UINT8 *bssid,
+ A_UINT16 optIEDataLen,
+ A_UINT8 *optIEData);
+
+A_STATUS wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl);
+A_STATUS wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize);
+A_STATUS wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSpLen);
+A_UINT8 convert_userPriority_to_trafficClass(A_UINT8 userPriority);
+A_UINT8 wmi_get_power_mode_cmd(struct wmi_t *wmip);
+A_STATUS wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance);
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+A_STATUS wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len);
+#endif
+
+A_STATUS wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status);
+A_STATUS wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd);
+
+
+/*
+ * This function is used to configure the fix rates mask to the target.
+ */
+A_STATUS wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask);
+A_STATUS wmi_get_ratemask_cmd(struct wmi_t *wmip);
+
+A_STATUS wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode);
+
+A_STATUS wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status);
+A_STATUS wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG txEnable);
+
+A_STATUS wmi_get_keepalive_configured(struct wmi_t *wmip);
+A_UINT8 wmi_get_keepalive_cmd(struct wmi_t *wmip);
+A_STATUS wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval);
+
+A_STATUS wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType,
+ A_UINT8 ieLen,A_UINT8 *ieInfo);
+
+A_STATUS wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen);
+A_INT32 wmi_get_rate(A_INT8 rateindex);
+
+/*Wake on Wireless WMI commands*/
+A_STATUS wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip, WMI_SET_HOST_SLEEP_MODE_CMD *cmd);
+A_STATUS wmi_set_wow_mode_cmd(struct wmi_t *wmip, WMI_SET_WOW_MODE_CMD *cmd);
+A_STATUS wmi_get_wow_list_cmd(struct wmi_t *wmip, WMI_GET_WOW_LIST_CMD *cmd);
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_ADD_WOW_PATTERN_CMD *cmd, A_UINT8* pattern, A_UINT8* mask, A_UINT8 pattern_size);
+A_STATUS wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_DEL_WOW_PATTERN_CMD *cmd);
+A_STATUS wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status);
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2);
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_API_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/wmi.h
@@ -0,0 +1,1743 @@
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This file contains the definitions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI). It includes definitions of all the
+ * commands and events. Commands are messages from the host to the WM.
+ * Events and Replies are messages from the WM to the host.
+ *
+ * Ownership of correctness in regards to WMI commands
+ * belongs to the host driver and the WM is not required to validate
+ * parameters for value, proper range, or any other checking.
+ *
+ */
+
+#ifndef _WMI_H_
+#define _WMI_H_
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "wmix.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define WMI_PROTOCOL_VERSION 0x0002
+#define WMI_PROTOCOL_REVISION 0x0000
+
+#define ATH_MAC_LEN 6 /* length of mac in bytes */
+#define WMI_CMD_MAX_LEN 100
+#define WMI_CONTROL_MSG_MAX_LEN 256
+#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536
+#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
+#define RFC1042OUI {0x00, 0x00, 0x00}
+
+#define IP_ETHERTYPE 0x0800
+
+#define WMI_IMPLICIT_PSTREAM 0xFF
+#define WMI_MAX_THINSTREAM 15
+
+struct host_app_area_s {
+ A_UINT32 wmi_protocol_ver;
+};
+
+/*
+ * Data Path
+ */
+typedef PREPACK struct {
+ A_UINT8 dstMac[ATH_MAC_LEN];
+ A_UINT8 srcMac[ATH_MAC_LEN];
+ A_UINT16 typeOrLen;
+} POSTPACK ATH_MAC_HDR;
+
+typedef PREPACK struct {
+ A_UINT8 dsap;
+ A_UINT8 ssap;
+ A_UINT8 cntl;
+ A_UINT8 orgCode[3];
+ A_UINT16 etherType;
+} POSTPACK ATH_LLC_SNAP_HDR;
+
+typedef enum {
+ DATA_MSGTYPE = 0x0,
+ CNTL_MSGTYPE,
+ SYNC_MSGTYPE
+} WMI_MSG_TYPE;
+
+
+typedef PREPACK struct {
+ A_INT8 rssi;
+ A_UINT8 info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */
+ /* UP in next 3 bits - b4b3b2 */
+#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03
+#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
+#define WMI_DATA_HDR_UP_MASK 0x07
+#define WMI_DATA_HDR_UP_SHIFT 2
+#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t))
+} POSTPACK WMI_DATA_HDR;
+
+
+#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT))
+#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT))
+
+/*
+ * Control Path
+ */
+typedef PREPACK struct {
+ A_UINT16 commandId;
+} POSTPACK WMI_CMD_HDR; /* used for commands and events */
+
+/*
+ * List of Commnands
+ */
+typedef enum {
+ WMI_CONNECT_CMDID = 0x0001,
+ WMI_RECONNECT_CMDID,
+ WMI_DISCONNECT_CMDID,
+ WMI_SYNCHRONIZE_CMDID,
+ WMI_CREATE_PSTREAM_CMDID,
+ WMI_DELETE_PSTREAM_CMDID,
+ WMI_START_SCAN_CMDID,
+ WMI_SET_SCAN_PARAMS_CMDID,
+ WMI_SET_BSS_FILTER_CMDID,
+ WMI_SET_PROBED_SSID_CMDID,
+ WMI_SET_LISTEN_INT_CMDID,
+ WMI_SET_BMISS_TIME_CMDID,
+ WMI_SET_DISC_TIMEOUT_CMDID,
+ WMI_GET_CHANNEL_LIST_CMDID,
+ WMI_SET_BEACON_INT_CMDID,
+ WMI_GET_STATISTICS_CMDID,
+ WMI_SET_CHANNEL_PARAMS_CMDID,
+ WMI_SET_POWER_MODE_CMDID,
+ WMI_SET_IBSS_PM_CAPS_CMDID,
+ WMI_SET_POWER_PARAMS_CMDID,
+ WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+ WMI_ADD_CIPHER_KEY_CMDID,
+ WMI_DELETE_CIPHER_KEY_CMDID,
+ WMI_ADD_KRK_CMDID,
+ WMI_DELETE_KRK_CMDID,
+ WMI_SET_PMKID_CMDID,
+ WMI_SET_TX_PWR_CMDID,
+ WMI_GET_TX_PWR_CMDID,
+ WMI_SET_ASSOC_INFO_CMDID,
+ WMI_ADD_BAD_AP_CMDID,
+ WMI_DELETE_BAD_AP_CMDID,
+ WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+ WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+ WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+ WMI_SET_ACCESS_PARAMS_CMDID,
+ WMI_SET_RETRY_LIMITS_CMDID,
+ WMI_SET_OPT_MODE_CMDID,
+ WMI_OPT_TX_FRAME_CMDID,
+ WMI_SET_VOICE_PKT_SIZE_CMDID,
+ WMI_SET_MAX_SP_LEN_CMDID,
+ WMI_SET_ROAM_CTRL_CMDID,
+ WMI_GET_ROAM_TBL_CMDID,
+ WMI_GET_ROAM_DATA_CMDID,
+ WMI_ENABLE_RM_CMDID,
+ WMI_SET_MAX_OFFHOME_DURATION_CMDID,
+ WMI_EXTENSION_CMDID, /* Non-wireless extensions */
+ WMI_SNR_THRESHOLD_PARAMS_CMDID,
+ WMI_LQ_THRESHOLD_PARAMS_CMDID,
+ WMI_SET_LPREAMBLE_CMDID,
+ WMI_SET_RTS_CMDID,
+ WMI_CLR_RSSI_SNR_CMDID,
+ WMI_SET_FIXRATES_CMDID,
+ WMI_GET_FIXRATES_CMDID,
+ WMI_SET_AUTH_MODE_CMDID,
+ WMI_SET_REASSOC_MODE_CMDID,
+ WMI_SET_WMM_CMDID,
+ WMI_SET_WMM_TXOP_CMDID,
+ WMI_TEST_CMDID,
+ WMI_SET_BT_STATUS_CMDID,
+ WMI_SET_BT_PARAMS_CMDID,
+
+ WMI_SET_KEEPALIVE_CMDID,
+ WMI_GET_KEEPALIVE_CMDID,
+ WMI_SET_APPIE_CMDID,
+ WMI_GET_APPIE_CMDID,
+ WMI_SET_WSC_STATUS_CMDID,
+
+ /* Wake on Wireless */
+ WMI_SET_HOST_SLEEP_MODE_CMDID,
+ WMI_SET_WOW_MODE_CMDID,
+ WMI_GET_WOW_LIST_CMDID,
+ WMI_ADD_WOW_PATTERN_CMDID,
+ WMI_DEL_WOW_PATTERN_CMDID,
+ WMI_SET_MAC_ADDRESS_CMDID,
+ WMI_SET_AKMP_PARAMS_CMDID,
+ WMI_SET_PMKID_LIST_CMDID,
+ WMI_GET_PMKID_LIST_CMDID,
+
+ /*
+ * Developer commands starts at 0xF000
+ */
+ WMI_SET_BITRATE_CMDID = 0xF000,
+ WMI_GET_BITRATE_CMDID,
+ WMI_SET_WHALPARAM_CMDID,
+
+} WMI_COMMAND_ID;
+
+/*
+ * Frame Types
+ */
+typedef enum {
+ WMI_FRAME_BEACON = 0,
+ WMI_FRAME_PROBE_REQ,
+ WMI_FRAME_PROBE_RESP,
+ WMI_FRAME_ASSOC_REQ,
+ WMI_FRAME_ASSOC_RESP,
+ WMI_NUM_MGMT_FRAME
+} WMI_MGMT_FRAME_TYPE;
+
+/*
+ * Connect Command
+ */
+typedef enum {
+ INFRA_NETWORK = 0x01,
+ ADHOC_NETWORK = 0x02,
+ ADHOC_CREATOR = 0x04,
+} NETWORK_TYPE;
+
+typedef enum {
+ OPEN_AUTH = 0x01,
+ SHARED_AUTH = 0x02,
+ LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */
+} DOT11_AUTH_MODE;
+
+typedef enum {
+ NONE_AUTH = 0x01,
+ WPA_AUTH = 0x02,
+ WPA_PSK_AUTH = 0x03,
+ WPA2_AUTH = 0x04,
+ WPA2_PSK_AUTH = 0x05,
+ WPA_AUTH_CCKM = 0x06,
+ WPA2_AUTH_CCKM = 0x07,
+} AUTH_MODE;
+
+typedef enum {
+ NONE_CRYPT = 0x01,
+ WEP_CRYPT = 0x02,
+ TKIP_CRYPT = 0x03,
+ AES_CRYPT = 0x04,
+} CRYPTO_TYPE;
+
+#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT
+#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1)
+
+#define WMI_MIN_KEY_INDEX 0
+#define WMI_MAX_KEY_INDEX 3
+
+#define WMI_MAX_KEY_LEN 32
+
+#define WMI_MAX_SSID_LEN 32
+
+typedef enum {
+ CONNECT_ASSOC_POLICY_USER = 0x0001,
+ CONNECT_SEND_REASSOC = 0x0002,
+ CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
+ CONNECT_PROFILE_MATCH_DONE = 0x0008,
+ CONNECT_IGNORE_AAC_BEACON = 0x0010,
+ CONNECT_CSA_FOLLOW_BSS = 0x0020,
+} WMI_CONNECT_CTRL_FLAGS_BITS;
+
+#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS)
+
+typedef PREPACK struct {
+ A_UINT8 networkType;
+ A_UINT8 dot11AuthMode;
+ A_UINT8 authMode;
+ A_UINT8 pairwiseCryptoType;
+ A_UINT8 pairwiseCryptoLen;
+ A_UINT8 groupCryptoType;
+ A_UINT8 groupCryptoLen;
+ A_UINT8 ssidLength;
+ A_UCHAR ssid[WMI_MAX_SSID_LEN];
+ A_UINT16 channel;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT32 ctrl_flags;
+} POSTPACK WMI_CONNECT_CMD;
+
+/*
+ * WMI_RECONNECT_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT16 channel; /* hint */
+ A_UINT8 bssid[ATH_MAC_LEN]; /* mandatory if set */
+} POSTPACK WMI_RECONNECT_CMD;
+
+/*
+ * WMI_ADD_CIPHER_KEY_CMDID
+ */
+typedef enum {
+ PAIRWISE_USAGE = 0x00,
+ GROUP_USAGE = 0x01,
+ TX_USAGE = 0x02, /* default Tx Key - Static WEP only */
+} KEY_USAGE;
+
+/*
+ * Bit Flag
+ * Bit 0 - Initialise TSC - default is Initialize
+ */
+#define KEY_OP_INIT_TSC 0x01
+#define KEY_OP_INIT_RSC 0x02
+
+#define KEY_OP_INIT_VAL 0x03 /* Default Initialise the TSC & RSC */
+#define KEY_OP_VALID_MASK 0x03
+
+typedef PREPACK struct {
+ A_UINT8 keyIndex;
+ A_UINT8 keyType;
+ A_UINT8 keyUsage; /* KEY_USAGE */
+ A_UINT8 keyLength;
+ A_UINT8 keyRSC[8]; /* key replay sequence counter */
+ A_UINT8 key[WMI_MAX_KEY_LEN];
+ A_UINT8 key_op_ctrl; /* Additional Key Control information */
+} POSTPACK WMI_ADD_CIPHER_KEY_CMD;
+
+/*
+ * WMI_DELETE_CIPHER_KEY_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 keyIndex;
+} POSTPACK WMI_DELETE_CIPHER_KEY_CMD;
+
+#define WMI_KRK_LEN 16
+/*
+ * WMI_ADD_KRK_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 krk[WMI_KRK_LEN];
+} POSTPACK WMI_ADD_KRK_CMD;
+
+/*
+ * WMI_SET_TKIP_COUNTERMEASURES_CMDID
+ */
+typedef enum {
+ WMI_TKIP_CM_DISABLE = 0x0,
+ WMI_TKIP_CM_ENABLE = 0x1,
+} WMI_TKIP_CM_CONTROL;
+
+typedef PREPACK struct {
+ A_UINT8 cm_en; /* WMI_TKIP_CM_CONTROL */
+} POSTPACK WMI_SET_TKIP_COUNTERMEASURES_CMD;
+
+/*
+ * WMI_SET_PMKID_CMDID
+ */
+
+#define WMI_PMKID_LEN 16
+
+typedef enum {
+ PMKID_DISABLE = 0,
+ PMKID_ENABLE = 1,
+} PMKID_ENABLE_FLG;
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 enable; /* PMKID_ENABLE_FLG */
+ A_UINT8 pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_SET_PMKID_CMD;
+
+/*
+ * WMI_START_SCAN_CMD
+ */
+typedef enum {
+ WMI_LONG_SCAN = 0,
+ WMI_SHORT_SCAN = 1,
+} WMI_SCAN_TYPE;
+
+typedef PREPACK struct {
+ A_BOOL forceFgScan;
+ A_BOOL isLegacy; /* For Legacy Cisco AP compatibility */
+ A_UINT32 homeDwellTime; /* Maximum duration in the home channel(milliseconds) */
+ A_UINT32 forceScanInterval; /* Time interval between scans (milliseconds)*/
+ A_UINT8 scanType; /* WMI_SCAN_TYPE */
+} POSTPACK WMI_START_SCAN_CMD;
+
+/*
+ * WMI_SET_SCAN_PARAMS_CMDID
+ */
+#define WMI_SHORTSCANRATIO_DEFAULT 3
+typedef enum {
+ CONNECT_SCAN_CTRL_FLAGS = 0x01, /* set if can scan in the Connect cmd */
+ SCAN_CONNECTED_CTRL_FLAGS = 0x02, /* set if scan for the SSID it is */
+ /* already connected to */
+ ACTIVE_SCAN_CTRL_FLAGS = 0x04, /* set if enable active scan */
+ ROAM_SCAN_CTRL_FLAGS = 0x08, /* set if enable roam scan when bmiss and lowrssi */
+ REPORT_BSSINFO_CTRL_FLAGS = 0x10, /* set if follows customer BSSINFO reporting rule */
+ ENABLE_AUTO_CTRL_FLAGS = 0x20, /* if disabled, target doesn't
+ scan after a disconnect event */
+ ENABLE_SCAN_ABORT_EVENT = 0x40 /* Scan complete event with canceled status will be generated when a scan is prempted before it gets completed */
+
+} WMI_SCAN_CTRL_FLAGS_BITS;
+
+#define CAN_SCAN_IN_CONNECT(flags) (flags & CONNECT_SCAN_CTRL_FLAGS)
+#define CAN_SCAN_CONNECTED(flags) (flags & SCAN_CONNECTED_CTRL_FLAGS)
+#define ENABLE_ACTIVE_SCAN(flags) (flags & ACTIVE_SCAN_CTRL_FLAGS)
+#define ENABLE_ROAM_SCAN(flags) (flags & ROAM_SCAN_CTRL_FLAGS)
+#define CONFIG_REPORT_BSSINFO(flags) (flags & REPORT_BSSINFO_CTRL_FLAGS)
+#define IS_AUTO_SCAN_ENABLED(flags) (flags & ENABLE_AUTO_CTRL_FLAGS)
+#define SCAN_ABORT_EVENT_ENABLED(flags) (flags & ENABLE_SCAN_ABORT_EVENT)
+
+#define DEFAULT_SCAN_CTRL_FLAGS (CONNECT_SCAN_CTRL_FLAGS| SCAN_CONNECTED_CTRL_FLAGS| ACTIVE_SCAN_CTRL_FLAGS| ROAM_SCAN_CTRL_FLAGS | ENABLE_AUTO_CTRL_FLAGS)
+
+
+typedef PREPACK struct {
+ A_UINT16 fg_start_period; /* seconds */
+ A_UINT16 fg_end_period; /* seconds */
+ A_UINT16 bg_period; /* seconds */
+ A_UINT16 maxact_chdwell_time; /* msec */
+ A_UINT16 pas_chdwell_time; /* msec */
+ A_UINT8 shortScanRatio; /* how many shorts scan for one long */
+ A_UINT8 scanCtrlFlags;
+ A_UINT16 minact_chdwell_time; /* msec */
+ A_UINT32 max_dfsch_act_time; /* msecs */
+} POSTPACK WMI_SCAN_PARAMS_CMD;
+
+/*
+ * WMI_SET_BSS_FILTER_CMDID
+ */
+typedef enum {
+ NONE_BSS_FILTER = 0x0, /* no beacons forwarded */
+ ALL_BSS_FILTER, /* all beacons forwarded */
+ PROFILE_FILTER, /* only beacons matching profile */
+ ALL_BUT_PROFILE_FILTER, /* all but beacons matching profile */
+ CURRENT_BSS_FILTER, /* only beacons matching current BSS */
+ ALL_BUT_BSS_FILTER, /* all but beacons matching BSS */
+ PROBED_SSID_FILTER, /* beacons matching probed ssid */
+ LAST_BSS_FILTER, /* marker only */
+} WMI_BSS_FILTER;
+
+typedef PREPACK struct {
+ A_UINT8 bssFilter; /* see WMI_BSS_FILTER */
+ A_UINT32 ieMask;
+} POSTPACK WMI_BSS_FILTER_CMD;
+
+/*
+ * WMI_SET_PROBED_SSID_CMDID
+ */
+#define MAX_PROBED_SSID_INDEX 5
+
+typedef enum {
+ DISABLE_SSID_FLAG = 0, /* disables entry */
+ SPECIFIC_SSID_FLAG = 0x01, /* probes specified ssid */
+ ANY_SSID_FLAG = 0x02, /* probes for any ssid */
+} WMI_SSID_FLAG;
+
+typedef PREPACK struct {
+ A_UINT8 entryIndex; /* 0 to MAX_PROBED_SSID_INDEX */
+ A_UINT8 flag; /* WMI_SSID_FLG */
+ A_UINT8 ssidLength;
+ A_UINT8 ssid[32];
+} POSTPACK WMI_PROBED_SSID_CMD;
+
+/*
+ * WMI_SET_LISTEN_INT_CMDID
+ * The Listen interval is between 15 and 3000 TUs
+ */
+#define MIN_LISTEN_INTERVAL 15
+#define MAX_LISTEN_INTERVAL 5000
+#define MIN_LISTEN_BEACONS 1
+#define MAX_LISTEN_BEACONS 50
+
+typedef PREPACK struct {
+ A_UINT16 listenInterval;
+ A_UINT16 numBeacons;
+} POSTPACK WMI_LISTEN_INT_CMD;
+
+/*
+ * WMI_SET_BEACON_INT_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT16 beaconInterval;
+} POSTPACK WMI_BEACON_INT_CMD;
+
+/*
+ * WMI_SET_BMISS_TIME_CMDID
+ * valid values are between 1000 and 5000 TUs
+ */
+
+#define MIN_BMISS_TIME 1000
+#define MAX_BMISS_TIME 5000
+#define MIN_BMISS_BEACONS 1
+#define MAX_BMISS_BEACONS 50
+
+typedef PREPACK struct {
+ A_UINT16 bmissTime;
+ A_UINT16 numBeacons;
+} POSTPACK WMI_BMISS_TIME_CMD;
+
+/*
+ * WMI_SET_POWER_MODE_CMDID
+ */
+typedef enum {
+ REC_POWER = 0x01,
+ MAX_PERF_POWER,
+} WMI_POWER_MODE;
+
+typedef PREPACK struct {
+ A_UINT8 powerMode; /* WMI_POWER_MODE */
+} POSTPACK WMI_POWER_MODE_CMD;
+
+/*
+ * WMI_SET_POWER_PARAMS_CMDID
+ */
+typedef enum {
+ IGNORE_DTIM = 0x01,
+ NORMAL_DTIM = 0x02,
+ STICK_DTIM = 0x03,
+} WMI_DTIM_POLICY;
+
+typedef PREPACK struct {
+ A_UINT16 idle_period; /* msec */
+ A_UINT16 pspoll_number;
+ A_UINT16 dtim_policy;
+} POSTPACK WMI_POWER_PARAMS_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 power_saving;
+ A_UINT8 ttl; /* number of beacon periods */
+ A_UINT16 atim_windows; /* msec */
+ A_UINT16 timeout_value; /* msec */
+} POSTPACK WMI_IBSS_PM_CAPS_CMD;
+
+/*
+ * WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID
+ */
+typedef enum {
+ IGNORE_TIM_ALL_QUEUES_APSD = 0,
+ PROCESS_TIM_ALL_QUEUES_APSD = 1,
+ IGNORE_TIM_SIMULATED_APSD = 2,
+ PROCESS_TIM_SIMULATED_APSD = 3,
+} APSD_TIM_POLICY;
+
+typedef PREPACK struct {
+ A_UINT16 psPollTimeout; /* msec */
+ A_UINT16 triggerTimeout; /* msec */
+ A_UINT32 apsdTimPolicy; /* TIM behavior with ques APSD enabled. Default is IGNORE_TIM_ALL_QUEUES_APSD */
+ A_UINT32 simulatedAPSDTimPolicy; /* TIM behavior with simulated APSD enabled. Default is PROCESS_TIM_SIMULATED_APSD */
+} POSTPACK WMI_POWERSAVE_TIMERS_POLICY_CMD;
+
+/*
+ * WMI_SET_VOICE_PKT_SIZE_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT16 voicePktSize;
+} POSTPACK WMI_SET_VOICE_PKT_SIZE_CMD;
+
+/*
+ * WMI_SET_MAX_SP_LEN_CMDID
+ */
+typedef enum {
+ DELIVER_ALL_PKT = 0x0,
+ DELIVER_2_PKT = 0x1,
+ DELIVER_4_PKT = 0x2,
+ DELIVER_6_PKT = 0x3,
+} APSD_SP_LEN_TYPE;
+
+typedef PREPACK struct {
+ A_UINT8 maxSPLen;
+} POSTPACK WMI_SET_MAX_SP_LEN_CMD;
+
+/*
+ * WMI_SET_DISC_TIMEOUT_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 disconnectTimeout; /* seconds */
+} POSTPACK WMI_DISC_TIMEOUT_CMD;
+
+typedef enum {
+ UPLINK_TRAFFIC = 0,
+ DNLINK_TRAFFIC = 1,
+ BIDIR_TRAFFIC = 2,
+} DIR_TYPE;
+
+typedef enum {
+ DISABLE_FOR_THIS_AC = 0,
+ ENABLE_FOR_THIS_AC = 1,
+ ENABLE_FOR_ALL_AC = 2,
+} VOICEPS_CAP_TYPE;
+
+typedef enum {
+ TRAFFIC_TYPE_APERIODIC = 0,
+ TRAFFIC_TYPE_PERIODIC = 1,
+}TRAFFIC_TYPE;
+
+/*
+ * WMI_CREATE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT32 minServiceInt; /* in milli-sec */
+ A_UINT32 maxServiceInt; /* in milli-sec */
+ A_UINT32 inactivityInt; /* in milli-sec */
+ A_UINT32 suspensionInt; /* in milli-sec */
+ A_UINT32 serviceStartTime;
+ A_UINT32 minDataRate; /* in bps */
+ A_UINT32 meanDataRate; /* in bps */
+ A_UINT32 peakDataRate; /* in bps */
+ A_UINT32 maxBurstSize;
+ A_UINT32 delayBound;
+ A_UINT32 minPhyRate; /* in bps */
+ A_UINT32 sba;
+ A_UINT32 mediumTime;
+ A_UINT16 nominalMSDU; /* in octects */
+ A_UINT16 maxMSDU; /* in octects */
+ A_UINT8 trafficClass;
+ A_UINT8 trafficType; /* TRAFFIC_TYPE */
+ A_UINT8 trafficDirection; /* TRAFFIC_DIR */
+ A_UINT8 voicePSCapability; /* VOICEPS_CAP_TYPE */
+ A_UINT8 tsid;
+ A_UINT8 userPriority; /* 802.1D user priority */
+} POSTPACK WMI_CREATE_PSTREAM_CMD;
+
+/*
+ * WMI_DELETE_PSTREAM_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 trafficClass;
+ A_UINT8 tsid;
+} POSTPACK WMI_DELETE_PSTREAM_CMD;
+
+/*
+ * WMI_SET_CHANNEL_PARAMS_CMDID
+ */
+typedef enum {
+ WMI_11A_MODE = 0x1,
+ WMI_11G_MODE = 0x2,
+ WMI_11AG_MODE = 0x3,
+ WMI_11B_MODE = 0x4,
+ WMI_11GONLY_MODE = 0x5,
+} WMI_PHY_MODE;
+
+#define WMI_MAX_CHANNELS 32
+
+typedef PREPACK struct {
+ A_UINT8 reserved1;
+ A_UINT8 scanParam; /* set if enable scan */
+ A_UINT8 phyMode; /* see WMI_PHY_MODE */
+ A_UINT8 numChannels; /* how many channels follow */
+ A_UINT16 channelList[1]; /* channels in Mhz */
+} POSTPACK WMI_CHANNEL_PARAMS_CMD;
+
+
+/*
+ * WMI_RSSI_THRESHOLD_PARAMS_CMDID
+ * Setting the polltime to 0 would disable polling.
+ * Threshold values are in the ascending order, and should agree to:
+ * (lowThreshold_lowerVal < lowThreshold_upperVal < highThreshold_lowerVal
+ * < highThreshold_upperVal)
+ */
+
+typedef PREPACK struct WMI_RSSI_THRESHOLD_PARAMS{
+ A_UINT32 pollTime; /* Polling time as a factor of LI */
+ A_INT16 thresholdAbove1_Val; /* lowest of upper */
+ A_INT16 thresholdAbove2_Val;
+ A_INT16 thresholdAbove3_Val;
+ A_INT16 thresholdAbove4_Val;
+ A_INT16 thresholdAbove5_Val;
+ A_INT16 thresholdAbove6_Val; /* highest of upper */
+ A_INT16 thresholdBelow1_Val; /* lowest of bellow */
+ A_INT16 thresholdBelow2_Val;
+ A_INT16 thresholdBelow3_Val;
+ A_INT16 thresholdBelow4_Val;
+ A_INT16 thresholdBelow5_Val;
+ A_INT16 thresholdBelow6_Val; /* highest of bellow */
+ A_UINT8 weight; /* "alpha" */
+ A_UINT8 reserved[3];
+} POSTPACK WMI_RSSI_THRESHOLD_PARAMS_CMD;
+
+/*
+ * WMI_SNR_THRESHOLD_PARAMS_CMDID
+ * Setting the polltime to 0 would disable polling.
+ */
+
+typedef PREPACK struct WMI_SNR_THRESHOLD_PARAMS{
+ A_UINT32 pollTime; /* Polling time as a factor of LI */
+ A_UINT8 weight; /* "alpha" */
+ A_UINT8 thresholdAbove1_Val; /* lowest of uppper*/
+ A_UINT8 thresholdAbove2_Val;
+ A_UINT8 thresholdAbove3_Val;
+ A_UINT8 thresholdAbove4_Val; /* highest of upper */
+ A_UINT8 thresholdBelow1_Val; /* lowest of bellow */
+ A_UINT8 thresholdBelow2_Val;
+ A_UINT8 thresholdBelow3_Val;
+ A_UINT8 thresholdBelow4_Val; /* highest of bellow */
+ A_UINT8 reserved[3];
+} POSTPACK WMI_SNR_THRESHOLD_PARAMS_CMD;
+
+/*
+ * WMI_LQ_THRESHOLD_PARAMS_CMDID
+ */
+typedef PREPACK struct WMI_LQ_THRESHOLD_PARAMS {
+ A_UINT8 enable;
+ A_UINT8 thresholdAbove1_Val;
+ A_UINT8 thresholdAbove2_Val;
+ A_UINT8 thresholdAbove3_Val;
+ A_UINT8 thresholdAbove4_Val;
+ A_UINT8 thresholdBelow1_Val;
+ A_UINT8 thresholdBelow2_Val;
+ A_UINT8 thresholdBelow3_Val;
+ A_UINT8 thresholdBelow4_Val;
+ A_UINT8 reserved[3];
+} POSTPACK WMI_LQ_THRESHOLD_PARAMS_CMD;
+
+typedef enum {
+ WMI_LPREAMBLE_DISABLED = 0,
+ WMI_LPREAMBLE_ENABLED
+} WMI_LPREAMBLE_STATUS;
+
+typedef PREPACK struct {
+ A_UINT8 status;
+}POSTPACK WMI_SET_LPREAMBLE_CMD;
+
+typedef PREPACK struct {
+ A_UINT16 threshold;
+}POSTPACK WMI_SET_RTS_CMD;
+
+/*
+ * WMI_TARGET_ERROR_REPORT_BITMASK_CMDID
+ * Sets the error reporting event bitmask in target. Target clears it
+ * upon an error. Subsequent errors are counted, but not reported
+ * via event, unless the bitmask is set again.
+ */
+typedef PREPACK struct {
+ A_UINT32 bitmask;
+} POSTPACK WMI_TARGET_ERROR_REPORT_BITMASK;
+
+/*
+ * WMI_SET_TX_PWR_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 dbM; /* in dbM units */
+} POSTPACK WMI_SET_TX_PWR_CMD, WMI_TX_PWR_REPLY;
+
+/*
+ * WMI_SET_ASSOC_INFO_CMDID
+ *
+ * A maximum of 2 private IEs can be sent in the [Re]Assoc request.
+ * A 3rd one, the CCX version IE can also be set from the host.
+ */
+#define WMI_MAX_ASSOC_INFO_TYPE 2
+#define WMI_CCX_VER_IE 2 /* ieType to set CCX Version IE */
+
+#define WMI_MAX_ASSOC_INFO_LEN 240
+
+typedef PREPACK struct {
+ A_UINT8 ieType;
+ A_UINT8 bufferSize;
+ A_UINT8 assocInfo[1]; /* up to WMI_MAX_ASSOC_INFO_LEN */
+} POSTPACK WMI_SET_ASSOC_INFO_CMD;
+
+
+/*
+ * WMI_GET_TX_PWR_CMDID does not take any parameters
+ */
+
+/*
+ * WMI_ADD_BAD_AP_CMDID
+ */
+#define WMI_MAX_BAD_AP_INDEX 1
+
+typedef PREPACK struct {
+ A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_ADD_BAD_AP_CMD;
+
+/*
+ * WMI_DELETE_BAD_AP_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 badApIndex; /* 0 to WMI_MAX_BAD_AP_INDEX */
+} POSTPACK WMI_DELETE_BAD_AP_CMD;
+
+/*
+ * WMI_SET_ACCESS_PARAMS_CMDID
+ */
+#define WMI_DEFAULT_TXOP_ACPARAM 0 /* implies one MSDU */
+#define WMI_DEFAULT_ECWMIN_ACPARAM 4 /* corresponds to CWmin of 15 */
+#define WMI_DEFAULT_ECWMAX_ACPARAM 10 /* corresponds to CWmax of 1023 */
+#define WMI_MAX_CW_ACPARAM 15 /* maximum eCWmin or eCWmax */
+#define WMI_DEFAULT_AIFSN_ACPARAM 2
+#define WMI_MAX_AIFSN_ACPARAM 15
+typedef PREPACK struct {
+ A_UINT16 txop; /* in units of 32 usec */
+ A_UINT8 eCWmin;
+ A_UINT8 eCWmax;
+ A_UINT8 aifsn;
+} POSTPACK WMI_SET_ACCESS_PARAMS_CMD;
+
+
+/*
+ * WMI_SET_RETRY_LIMITS_CMDID
+ *
+ * This command is used to customize the number of retries the
+ * wlan device will perform on a given frame.
+ */
+#define WMI_MIN_RETRIES 2
+#define WMI_MAX_RETRIES 13
+typedef enum {
+ MGMT_FRAMETYPE = 0,
+ CONTROL_FRAMETYPE = 1,
+ DATA_FRAMETYPE = 2
+} WMI_FRAMETYPE;
+
+typedef PREPACK struct {
+ A_UINT8 frameType; /* WMI_FRAMETYPE */
+ A_UINT8 trafficClass; /* applies only to DATA_FRAMETYPE */
+ A_UINT8 maxRetries;
+ A_UINT8 enableNotify;
+} POSTPACK WMI_SET_RETRY_LIMITS_CMD;
+
+/*
+ * WMI_SET_ROAM_CTRL_CMDID
+ *
+ * This command is used to influence the Roaming behaviour
+ * Set the host biases of the BSSs before setting the roam mode as bias
+ * based.
+ */
+
+/*
+ * Different types of Roam Control
+ */
+
+typedef enum {
+ WMI_FORCE_ROAM = 1, /* Roam to the specified BSSID */
+ WMI_SET_ROAM_MODE = 2, /* default ,progd bias, no roam */
+ WMI_SET_HOST_BIAS = 3, /* Set the Host Bias */
+ WMI_SET_LOWRSSI_SCAN_PARAMS = 4, /* Set lowrssi Scan parameters */
+} WMI_ROAM_CTRL_TYPE;
+
+#define WMI_MIN_ROAM_CTRL_TYPE WMI_FORCE_ROAM
+#define WMI_MAX_ROAM_CTRL_TYPE WMI_SET_LOWRSSI_SCAN_PARAMS
+
+/*
+ * ROAM MODES
+ */
+
+typedef enum {
+ WMI_DEFAULT_ROAM_MODE = 1, /* RSSI based ROAM */
+ WMI_HOST_BIAS_ROAM_MODE = 2, /* HOST BIAS based ROAM */
+ WMI_LOCK_BSS_MODE = 3 /* Lock to the Current BSS - no Roam */
+} WMI_ROAM_MODE;
+
+/*
+ * BSS HOST BIAS INFO
+ */
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_INT8 bias;
+} POSTPACK WMI_BSS_BIAS;
+
+typedef PREPACK struct {
+ A_UINT8 numBss;
+ WMI_BSS_BIAS bssBias[1];
+} POSTPACK WMI_BSS_BIAS_INFO;
+
+typedef PREPACK struct WMI_LOWRSSI_SCAN_PARAMS {
+ A_UINT16 lowrssi_scan_period;
+ A_INT16 lowrssi_scan_threshold;
+ A_INT16 lowrssi_roam_threshold;
+ A_UINT8 roam_rssi_floor;
+ A_UINT8 reserved[1]; /* For alignment */
+} POSTPACK WMI_LOWRSSI_SCAN_PARAMS;
+
+typedef PREPACK struct {
+ PREPACK union {
+ A_UINT8 bssid[ATH_MAC_LEN]; /* WMI_FORCE_ROAM */
+ A_UINT8 roamMode; /* WMI_SET_ROAM_MODE */
+ WMI_BSS_BIAS_INFO bssBiasInfo; /* WMI_SET_HOST_BIAS */
+ WMI_LOWRSSI_SCAN_PARAMS lrScanParams;
+ } POSTPACK info;
+ A_UINT8 roamCtrlType ;
+} POSTPACK WMI_SET_ROAM_CTRL_CMD;
+
+/*
+ * WMI_ENABLE_RM_CMDID
+ */
+typedef PREPACK struct {
+ A_BOOL enable_radio_measurements;
+} POSTPACK WMI_ENABLE_RM_CMD;
+
+/*
+ * WMI_SET_MAX_OFFHOME_DURATION_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 max_offhome_duration;
+} POSTPACK WMI_SET_MAX_OFFHOME_DURATION_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 frequency;
+ A_UINT8 threshold;
+} POSTPACK WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD;
+
+typedef enum {
+ BT_STREAM_UNDEF = 0,
+ BT_STREAM_SCO, /* SCO stream */
+ BT_STREAM_A2DP, /* A2DP stream */
+ BT_STREAM_MAX
+} BT_STREAM_TYPE;
+
+typedef enum {
+ BT_PARAM_SCO = 1, /* SCO stream parameters */
+ BT_PARAM_A2DP, /* A2DP stream parameters */
+ BT_PARAM_MISC, /* miscellaneous parameters */
+ BT_PARAM_REGS, /* co-existence register parameters */
+ BT_PARAM_MAX
+} BT_PARAM_TYPE;
+
+typedef enum {
+ BT_STATUS_UNDEF = 0,
+ BT_STATUS_START,
+ BT_STATUS_STOP,
+ BT_STATUS_RESUME,
+ BT_STATUS_SUSPEND,
+ BT_STATUS_MAX
+} BT_STREAM_STATUS;
+
+typedef PREPACK struct {
+ A_UINT8 streamType;
+ A_UINT8 status;
+} POSTPACK WMI_SET_BT_STATUS_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 noSCOPkts;
+ A_UINT8 pspollTimeout;
+ A_UINT8 stompbt;
+} POSTPACK BT_PARAMS_SCO;
+
+typedef PREPACK struct {
+ A_UINT32 period;
+ A_UINT32 dutycycle;
+ A_UINT8 stompbt;
+} POSTPACK BT_PARAMS_A2DP;
+
+typedef PREPACK struct {
+ A_UINT32 mode;
+ A_UINT32 scoWghts;
+ A_UINT32 a2dpWghts;
+ A_UINT32 genWghts;
+ A_UINT32 mode2;
+ A_UINT8 setVal;
+} POSTPACK BT_COEX_REGS;
+
+typedef enum {
+ WLAN_PROTECT_POLICY = 1,
+ WLAN_COEX_CTRL_FLAGS
+} BT_PARAMS_MISC_TYPE;
+
+typedef enum {
+ WLAN_PROTECT_PER_STREAM = 0x01, /* default */
+ WLAN_PROTECT_ANY_TX = 0x02
+} WLAN_PROTECT_FLAGS;
+
+
+#define WLAN_DISABLE_COEX_IN_DISCONNECT 0x01 /* default */
+#define WLAN_KEEP_COEX_IN_DISCONNECT 0x02
+#define WLAN_STOMPBT_IN_DISCONNECT 0x04
+
+#define WLAN_DISABLE_COEX_IN_ROAM 0x10 /* default */
+#define WLAN_KEEP_COEX_IN_ROAM 0x20
+#define WLAN_STOMPBT_IN_ROAM 0x40
+
+#define WLAN_DISABLE_COEX_IN_SCAN 0x100 /* default */
+#define WLAN_KEEP_COEX_IN_SCAN 0x200
+#define WLAN_STOMPBT_IN_SCAN 0x400
+
+#define WLAN_DISABLE_COEX_BT_OFF 0x1000 /* default */
+#define WLAN_KEEP_COEX_BT_OFF 0x2000
+#define WLAN_STOMPBT_BT_OFF 0x4000
+
+typedef PREPACK struct {
+ A_UINT32 period;
+ A_UINT32 dutycycle;
+ A_UINT8 stompbt;
+ A_UINT8 policy;
+} POSTPACK WLAN_PROTECT_POLICY_TYPE;
+
+typedef PREPACK struct {
+ PREPACK union {
+ WLAN_PROTECT_POLICY_TYPE protectParams;
+ A_UINT16 wlanCtrlFlags;
+ } POSTPACK info;
+ A_UINT8 paramType;
+} POSTPACK BT_PARAMS_MISC;
+
+typedef PREPACK struct {
+ PREPACK union {
+ BT_PARAMS_SCO scoParams;
+ BT_PARAMS_A2DP a2dpParams;
+ BT_PARAMS_MISC miscParams;
+ BT_COEX_REGS regs;
+ } POSTPACK info;
+ A_UINT8 paramType;
+} POSTPACK WMI_SET_BT_PARAMS_CMD;
+
+/*
+ * Command Replies
+ */
+
+/*
+ * WMI_GET_CHANNEL_LIST_CMDID reply
+ */
+typedef PREPACK struct {
+ A_UINT8 reserved1;
+ A_UINT8 numChannels; /* number of channels in reply */
+ A_UINT16 channelList[1]; /* channel in Mhz */
+} POSTPACK WMI_CHANNEL_LIST_REPLY;
+
+typedef enum {
+ A_SUCCEEDED = A_OK,
+ A_FAILED_DELETE_STREAM_DOESNOT_EXIST=250,
+ A_SUCCEEDED_MODIFY_STREAM=251,
+ A_FAILED_INVALID_STREAM = 252,
+ A_FAILED_MAX_THINSTREAMS = 253,
+ A_FAILED_CREATE_REMOVE_PSTREAM_FIRST = 254,
+} PSTREAM_REPLY_STATUS;
+
+/*
+ * List of Events (target to host)
+ */
+typedef enum {
+ WMI_READY_EVENTID = 0x1001,
+ WMI_CONNECT_EVENTID,
+ WMI_DISCONNECT_EVENTID,
+ WMI_BSSINFO_EVENTID,
+ WMI_CMDERROR_EVENTID,
+ WMI_REGDOMAIN_EVENTID,
+ WMI_PSTREAM_TIMEOUT_EVENTID,
+ WMI_NEIGHBOR_REPORT_EVENTID,
+ WMI_TKIP_MICERR_EVENTID,
+ WMI_SCAN_COMPLETE_EVENTID,
+ WMI_REPORT_STATISTICS_EVENTID,
+ WMI_RSSI_THRESHOLD_EVENTID,
+ WMI_ERROR_REPORT_EVENTID,
+ WMI_OPT_RX_FRAME_EVENTID,
+ WMI_REPORT_ROAM_TBL_EVENTID,
+ WMI_EXTENSION_EVENTID,
+ WMI_CAC_EVENTID,
+ WMI_SNR_THRESHOLD_EVENTID,
+ WMI_LQ_THRESHOLD_EVENTID,
+ WMI_TX_RETRY_ERR_EVENTID,
+ WMI_REPORT_ROAM_DATA_EVENTID,
+ WMI_TEST_EVENTID,
+ WMI_APLIST_EVENTID,
+ WMI_GET_WOW_LIST_EVENTID,
+ WMI_GET_PMKID_LIST_EVENTID
+} WMI_EVENT_ID;
+
+typedef enum {
+ WMI_11A_CAPABILITY = 1,
+ WMI_11G_CAPABILITY = 2,
+ WMI_11AG_CAPABILITY = 3,
+} WMI_PHY_CAPABILITY;
+
+typedef PREPACK struct {
+ A_UINT8 macaddr[ATH_MAC_LEN];
+ A_UINT8 phyCapability; /* WMI_PHY_CAPABILITY */
+} POSTPACK WMI_READY_EVENT;
+
+/*
+ * Connect Event
+ */
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT16 listenInterval;
+ A_UINT16 beaconInterval;
+ A_UINT32 networkType;
+ A_UINT8 beaconIeLen;
+ A_UINT8 assocReqLen;
+ A_UINT8 assocRespLen;
+ A_UINT8 assocInfo[1];
+} POSTPACK WMI_CONNECT_EVENT;
+
+/*
+ * Disconnect Event
+ */
+typedef enum {
+ NO_NETWORK_AVAIL = 0x01,
+ LOST_LINK = 0x02, /* bmiss */
+ DISCONNECT_CMD = 0x03,
+ BSS_DISCONNECTED = 0x04,
+ AUTH_FAILED = 0x05,
+ ASSOC_FAILED = 0x06,
+ NO_RESOURCES_AVAIL = 0x07,
+ CSERV_DISCONNECT = 0x08,
+ INVALID_PROFILE = 0x0a,
+ DOT11H_CHANNEL_SWITCH = 0x0b,
+} WMI_DISCONNECT_REASON;
+
+typedef PREPACK struct {
+ A_UINT16 protocolReasonStatus; /* reason code, see 802.11 spec. */
+ A_UINT8 bssid[ATH_MAC_LEN]; /* set if known */
+ A_UINT8 disconnectReason ; /* see WMI_DISCONNECT_REASON */
+ A_UINT8 assocRespLen;
+ A_UINT8 assocInfo[1];
+} POSTPACK WMI_DISCONNECT_EVENT;
+
+/*
+ * BSS Info Event.
+ * Mechanism used to inform host of the presence and characteristic of
+ * wireless networks present. Consists of bss info header followed by
+ * the beacon or probe-response frame body. The 802.11 header is not included.
+ */
+typedef enum {
+ BEACON_FTYPE = 0x1,
+ PROBERESP_FTYPE,
+ ACTION_MGMT_FTYPE,
+} WMI_BI_FTYPE;
+
+enum {
+ BSS_ELEMID_CHANSWITCH = 0x01,
+ BSS_ELEMID_ATHEROS = 0x02,
+};
+
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 frameType; /* see WMI_BI_FTYPE */
+ A_UINT8 snr;
+ A_INT16 rssi;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT32 ieMask;
+} POSTPACK WMI_BSS_INFO_HDR;
+
+/*
+ * Command Error Event
+ */
+typedef enum {
+ INVALID_PARAM = 0x01,
+ ILLEGAL_STATE = 0x02,
+ INTERNAL_ERROR = 0x03,
+} WMI_ERROR_CODE;
+
+typedef PREPACK struct {
+ A_UINT16 commandId;
+ A_UINT8 errorCode;
+} POSTPACK WMI_CMD_ERROR_EVENT;
+
+/*
+ * New Regulatory Domain Event
+ */
+typedef PREPACK struct {
+ A_UINT32 regDomain;
+} POSTPACK WMI_REG_DOMAIN_EVENT;
+
+typedef PREPACK struct {
+ A_UINT8 trafficClass;
+} POSTPACK WMI_PSTREAM_TIMEOUT_EVENT;
+
+/*
+ * The WMI_NEIGHBOR_REPORT Event is generated by the target to inform
+ * the host of BSS's it has found that matches the current profile.
+ * It can be used by the host to cache PMKs and/to initiate pre-authentication
+ * if the BSS supports it. The first bssid is always the current associated
+ * BSS.
+ * The bssid and bssFlags information repeats according to the number
+ * or APs reported.
+ */
+typedef enum {
+ WMI_DEFAULT_BSS_FLAGS = 0x00,
+ WMI_PREAUTH_CAPABLE_BSS = 0x01,
+ WMI_PMKID_VALID_BSS = 0x02,
+} WMI_BSS_FLAGS;
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 bssFlags; /* see WMI_BSS_FLAGS */
+} POSTPACK WMI_NEIGHBOR_INFO;
+
+typedef PREPACK struct {
+ A_INT8 numberOfAps;
+ WMI_NEIGHBOR_INFO neighbor[1];
+} POSTPACK WMI_NEIGHBOR_REPORT_EVENT;
+
+/*
+ * TKIP MIC Error Event
+ */
+typedef PREPACK struct {
+ A_UINT8 keyid;
+ A_UINT8 ismcast;
+} POSTPACK WMI_TKIP_MICERR_EVENT;
+
+/*
+ * WMI_SCAN_COMPLETE_EVENTID - no parameters (old), staus parameter (new)
+ */
+typedef PREPACK struct {
+ A_STATUS status;
+} POSTPACK WMI_SCAN_COMPLETE_EVENT;
+
+#define MAX_OPT_DATA_LEN 1400
+
+/*
+ * WMI_SET_ADHOC_BSSID_CMDID
+ */
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_SET_ADHOC_BSSID_CMD;
+
+/*
+ * WMI_SET_OPT_MODE_CMDID
+ */
+typedef enum {
+ SPECIAL_OFF,
+ SPECIAL_ON,
+} OPT_MODE_TYPE;
+
+typedef PREPACK struct {
+ A_UINT8 optMode;
+} POSTPACK WMI_SET_OPT_MODE_CMD;
+
+/*
+ * WMI_TX_OPT_FRAME_CMDID
+ */
+typedef enum {
+ OPT_PROBE_REQ = 0x01,
+ OPT_PROBE_RESP = 0x02,
+ OPT_CPPP_START = 0x03,
+ OPT_CPPP_STOP = 0x04,
+} WMI_OPT_FTYPE;
+
+typedef PREPACK struct {
+ A_UINT16 optIEDataLen;
+ A_UINT8 frmType;
+ A_UINT8 dstAddr[ATH_MAC_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 reserved; /* For alignment */
+ A_UINT8 optIEData[1];
+} POSTPACK WMI_OPT_TX_FRAME_CMD;
+
+/*
+ * Special frame receive Event.
+ * Mechanism used to inform host of the receiption of the special frames.
+ * Consists of special frame info header followed by special frame body.
+ * The 802.11 header is not included.
+ */
+typedef PREPACK struct {
+ A_UINT16 channel;
+ A_UINT8 frameType; /* see WMI_OPT_FTYPE */
+ A_INT8 snr;
+ A_UINT8 srcAddr[ATH_MAC_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+} POSTPACK WMI_OPT_RX_INFO_HDR;
+
+/*
+ * Reporting statistics.
+ */
+typedef PREPACK struct {
+ A_UINT32 tx_packets;
+ A_UINT32 tx_bytes;
+ A_UINT32 tx_unicast_pkts;
+ A_UINT32 tx_unicast_bytes;
+ A_UINT32 tx_multicast_pkts;
+ A_UINT32 tx_multicast_bytes;
+ A_UINT32 tx_broadcast_pkts;
+ A_UINT32 tx_broadcast_bytes;
+ A_UINT32 tx_rts_success_cnt;
+ A_UINT32 tx_packet_per_ac[4];
+ A_UINT32 tx_errors_per_ac[4];
+
+ A_UINT32 tx_errors;
+ A_UINT32 tx_failed_cnt;
+ A_UINT32 tx_retry_cnt;
+ A_UINT32 tx_rts_fail_cnt;
+ A_INT32 tx_unicast_rate;
+}POSTPACK tx_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 rx_packets;
+ A_UINT32 rx_bytes;
+ A_UINT32 rx_unicast_pkts;
+ A_UINT32 rx_unicast_bytes;
+ A_UINT32 rx_multicast_pkts;
+ A_UINT32 rx_multicast_bytes;
+ A_UINT32 rx_broadcast_pkts;
+ A_UINT32 rx_broadcast_bytes;
+ A_UINT32 rx_fragment_pkt;
+
+ A_UINT32 rx_errors;
+ A_UINT32 rx_crcerr;
+ A_UINT32 rx_key_cache_miss;
+ A_UINT32 rx_decrypt_err;
+ A_UINT32 rx_duplicate_frames;
+ A_INT32 rx_unicast_rate;
+}POSTPACK rx_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 tkip_local_mic_failure;
+ A_UINT32 tkip_counter_measures_invoked;
+ A_UINT32 tkip_replays;
+ A_UINT32 tkip_format_errors;
+ A_UINT32 ccmp_format_errors;
+ A_UINT32 ccmp_replays;
+}POSTPACK tkip_ccmp_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 power_save_failure_cnt;
+}POSTPACK pm_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 cs_bmiss_cnt;
+ A_UINT32 cs_lowRssi_cnt;
+ A_UINT16 cs_connect_cnt;
+ A_UINT16 cs_disconnect_cnt;
+ A_INT16 cs_aveBeacon_rssi;
+ A_UINT16 cs_roam_count;
+ A_UINT16 cs_rssi;
+ A_UINT8 cs_snr;
+ A_UINT8 cs_aveBeacon_snr;
+ A_UINT8 cs_lastRoam_msec;
+} POSTPACK cserv_stats_t;
+
+typedef PREPACK struct {
+ tx_stats_t tx_stats;
+ rx_stats_t rx_stats;
+ tkip_ccmp_stats_t tkipCcmpStats;
+}POSTPACK wlan_net_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 wow_num_pkts_dropped;
+ A_UINT16 wow_num_events_discarded;
+ A_UINT8 wow_num_host_pkt_wakeups;
+ A_UINT8 wow_num_host_event_wakeups;
+} POSTPACK wlan_wow_stats_t;
+
+typedef PREPACK struct {
+ A_UINT32 lqVal;
+ A_INT32 noise_floor_calibation;
+ pm_stats_t pmStats;
+ wlan_net_stats_t txrxStats;
+ wlan_wow_stats_t wowStats;
+ cserv_stats_t cservStats;
+} POSTPACK WMI_TARGET_STATS;
+
+/*
+ * WMI_RSSI_THRESHOLD_EVENTID.
+ * Indicate the RSSI events to host. Events are indicated when we breach a
+ * thresold value.
+ */
+typedef enum{
+ WMI_RSSI_THRESHOLD1_ABOVE = 0,
+ WMI_RSSI_THRESHOLD2_ABOVE,
+ WMI_RSSI_THRESHOLD3_ABOVE,
+ WMI_RSSI_THRESHOLD4_ABOVE,
+ WMI_RSSI_THRESHOLD5_ABOVE,
+ WMI_RSSI_THRESHOLD6_ABOVE,
+ WMI_RSSI_THRESHOLD1_BELOW,
+ WMI_RSSI_THRESHOLD2_BELOW,
+ WMI_RSSI_THRESHOLD3_BELOW,
+ WMI_RSSI_THRESHOLD4_BELOW,
+ WMI_RSSI_THRESHOLD5_BELOW,
+ WMI_RSSI_THRESHOLD6_BELOW
+}WMI_RSSI_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+ A_INT16 rssi;
+ A_UINT8 range;
+}POSTPACK WMI_RSSI_THRESHOLD_EVENT;
+
+/*
+ * WMI_ERROR_REPORT_EVENTID
+ */
+typedef enum{
+ WMI_TARGET_PM_ERR_FAIL = 0x00000001,
+ WMI_TARGET_KEY_NOT_FOUND = 0x00000002,
+ WMI_TARGET_DECRYPTION_ERR = 0x00000004,
+ WMI_TARGET_BMISS = 0x00000008,
+ WMI_PSDISABLE_NODE_JOIN = 0x00000010,
+ WMI_TARGET_COM_ERR = 0x00000020,
+ WMI_TARGET_FATAL_ERR = 0x00000040
+} WMI_TARGET_ERROR_VAL;
+
+typedef PREPACK struct {
+ A_UINT32 errorVal;
+}POSTPACK WMI_TARGET_ERROR_REPORT_EVENT;
+
+typedef PREPACK struct {
+ A_UINT8 retrys;
+}POSTPACK WMI_TX_RETRY_ERR_EVENT;
+
+typedef enum{
+ WMI_SNR_THRESHOLD1_ABOVE = 1,
+ WMI_SNR_THRESHOLD1_BELOW,
+ WMI_SNR_THRESHOLD2_ABOVE,
+ WMI_SNR_THRESHOLD2_BELOW,
+ WMI_SNR_THRESHOLD3_ABOVE,
+ WMI_SNR_THRESHOLD3_BELOW,
+ WMI_SNR_THRESHOLD4_ABOVE,
+ WMI_SNR_THRESHOLD4_BELOW
+} WMI_SNR_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+ A_UINT8 range; /* WMI_SNR_THRESHOLD_VAL */
+ A_UINT8 snr;
+}POSTPACK WMI_SNR_THRESHOLD_EVENT;
+
+typedef enum{
+ WMI_LQ_THRESHOLD1_ABOVE = 1,
+ WMI_LQ_THRESHOLD1_BELOW,
+ WMI_LQ_THRESHOLD2_ABOVE,
+ WMI_LQ_THRESHOLD2_BELOW,
+ WMI_LQ_THRESHOLD3_ABOVE,
+ WMI_LQ_THRESHOLD3_BELOW,
+ WMI_LQ_THRESHOLD4_ABOVE,
+ WMI_LQ_THRESHOLD4_BELOW
+} WMI_LQ_THRESHOLD_VAL;
+
+typedef PREPACK struct {
+ A_INT32 lq;
+ A_UINT8 range; /* WMI_LQ_THRESHOLD_VAL */
+}POSTPACK WMI_LQ_THRESHOLD_EVENT;
+/*
+ * WMI_REPORT_ROAM_TBL_EVENTID
+ */
+#define MAX_ROAM_TBL_CAND 5
+
+typedef PREPACK struct {
+ A_INT32 roam_util;
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_INT8 rssi;
+ A_INT8 rssidt;
+ A_INT8 last_rssi;
+ A_INT8 util;
+ A_INT8 bias;
+ A_UINT8 reserved; /* For alignment */
+} POSTPACK WMI_BSS_ROAM_INFO;
+
+
+typedef PREPACK struct {
+ A_UINT16 roamMode;
+ A_UINT16 numEntries;
+ WMI_BSS_ROAM_INFO bssRoamInfo[1];
+} POSTPACK WMI_TARGET_ROAM_TBL;
+
+/*
+ * WMI_CAC_EVENTID
+ */
+typedef enum {
+ CAC_INDICATION_ADMISSION = 0x00,
+ CAC_INDICATION_ADMISSION_RESP = 0x01,
+ CAC_INDICATION_DELETE = 0x02,
+ CAC_INDICATION_NO_RESP = 0x03,
+}CAC_INDICATION;
+
+#define WMM_TSPEC_IE_LEN 63
+
+typedef PREPACK struct {
+ A_UINT8 ac;
+ A_UINT8 cac_indication;
+ A_UINT8 statusCode;
+ A_UINT8 tspecSuggestion[WMM_TSPEC_IE_LEN];
+}POSTPACK WMI_CAC_EVENT;
+
+/*
+ * WMI_APLIST_EVENTID
+ */
+
+typedef enum {
+ APLIST_VER1 = 1,
+} APLIST_VER;
+
+typedef PREPACK struct {
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT16 channel;
+} POSTPACK WMI_AP_INFO_V1;
+
+typedef PREPACK union {
+ WMI_AP_INFO_V1 apInfoV1;
+} POSTPACK WMI_AP_INFO;
+
+typedef PREPACK struct {
+ A_UINT8 apListVer;
+ A_UINT8 numAP;
+ WMI_AP_INFO apList[1];
+} POSTPACK WMI_APLIST_EVENT;
+
+/*
+ * developer commands
+ */
+
+/*
+ * WMI_SET_BITRATE_CMDID
+ *
+ * Get bit rate cmd uses same definition as set bit rate cmd
+ */
+typedef enum {
+ RATE_AUTO = -1,
+ RATE_1Mb = 0,
+ RATE_2Mb = 1,
+ RATE_5_5Mb = 2,
+ RATE_11Mb = 3,
+ RATE_6Mb = 4,
+ RATE_9Mb = 5,
+ RATE_12Mb = 6,
+ RATE_18Mb = 7,
+ RATE_24Mb = 8,
+ RATE_36Mb = 9,
+ RATE_48Mb = 10,
+ RATE_54Mb = 11,
+} WMI_BIT_RATE;
+
+typedef PREPACK struct {
+ A_INT8 rateIndex; /* see WMI_BIT_RATE */
+} POSTPACK WMI_BIT_RATE_CMD, WMI_BIT_RATE_REPLY;
+
+/*
+ * WMI_SET_FIXRATES_CMDID
+ *
+ * Get fix rates cmd uses same definition as set fix rates cmd
+ */
+typedef enum {
+ FIX_RATE_1Mb = 0x1,
+ FIX_RATE_2Mb = 0x2,
+ FIX_RATE_5_5Mb = 0x4,
+ FIX_RATE_11Mb = 0x8,
+ FIX_RATE_6Mb = 0x10,
+ FIX_RATE_9Mb = 0x20,
+ FIX_RATE_12Mb = 0x40,
+ FIX_RATE_18Mb = 0x80,
+ FIX_RATE_24Mb = 0x100,
+ FIX_RATE_36Mb = 0x200,
+ FIX_RATE_48Mb = 0x400,
+ FIX_RATE_54Mb = 0x800,
+} WMI_FIX_RATES_MASK;
+
+typedef PREPACK struct {
+ A_UINT16 fixRateMask; /* see WMI_BIT_RATE */
+} POSTPACK WMI_FIX_RATES_CMD, WMI_FIX_RATES_REPLY;
+
+/*
+ * WMI_SET_RECONNECT_AUTH_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+ RECONN_DO_AUTH = 0x00,
+ RECONN_NOT_AUTH = 0x01
+} WMI_AUTH_MODE;
+
+typedef PREPACK struct {
+ A_UINT8 mode;
+} POSTPACK WMI_SET_AUTH_MODE_CMD;
+
+/*
+ * WMI_SET_REASSOC_MODE_CMDID
+ *
+ * Set authentication mode
+ */
+typedef enum {
+ REASSOC_DO_DISASSOC = 0x00,
+ REASSOC_DONOT_DISASSOC = 0x01
+} WMI_REASSOC_MODE;
+
+typedef PREPACK struct {
+ A_UINT8 mode;
+}POSTPACK WMI_SET_REASSOC_MODE_CMD;
+
+typedef enum {
+ ROAM_DATA_TIME = 1, /* Get The Roam Time Data */
+} ROAM_DATA_TYPE;
+
+typedef PREPACK struct {
+ A_UINT32 disassoc_time;
+ A_UINT32 no_txrx_time;
+ A_UINT32 assoc_time;
+ A_UINT32 allow_txrx_time;
+ A_UINT32 last_data_txrx_time;
+ A_UINT32 first_data_txrx_time;
+ A_UINT8 disassoc_bssid[ATH_MAC_LEN];
+ A_INT8 disassoc_bss_rssi;
+ A_UINT8 assoc_bssid[ATH_MAC_LEN];
+ A_INT8 assoc_bss_rssi;
+} POSTPACK WMI_TARGET_ROAM_TIME;
+
+typedef PREPACK struct {
+ PREPACK union {
+ WMI_TARGET_ROAM_TIME roamTime;
+ } POSTPACK u;
+ A_UINT8 roamDataType ;
+} POSTPACK WMI_TARGET_ROAM_DATA;
+
+typedef enum {
+ WMI_WMM_DISABLED = 0,
+ WMI_WMM_ENABLED
+} WMI_WMM_STATUS;
+
+typedef PREPACK struct {
+ A_UINT8 status;
+}POSTPACK WMI_SET_WMM_CMD;
+
+typedef enum {
+ WMI_TXOP_DISABLED = 0,
+ WMI_TXOP_ENABLED
+} WMI_TXOP_CFG;
+
+typedef PREPACK struct {
+ A_UINT8 txopEnable;
+}POSTPACK WMI_SET_WMM_TXOP_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 keepaliveInterval;
+} POSTPACK WMI_SET_KEEPALIVE_CMD;
+
+typedef PREPACK struct {
+ A_BOOL configured;
+ A_UINT8 keepaliveInterval;
+} POSTPACK WMI_GET_KEEPALIVE_CMD;
+
+/*
+ * Add Application specified IE to a management frame
+ */
+#define WMI_MAX_IE_LEN 78
+
+typedef PREPACK struct {
+ A_UINT8 mgmtFrmType; /* one of WMI_MGMT_FRAME_TYPE */
+ A_UINT8 ieLen; /* Length of the IE that should be added to the MGMT frame */
+ A_UINT8 ieInfo[1];
+} POSTPACK WMI_SET_APPIE_CMD;
+
+/*
+ * Notify the WSC registration status to the target
+ */
+#define WSC_REG_ACTIVE 1
+#define WSC_REG_INACTIVE 0
+/* Generic Hal Interface for setting hal paramters. */
+/* Add new Set HAL Param cmdIds here for newer params */
+typedef enum {
+ WHAL_SETCABTO_CMDID = 1,
+}WHAL_CMDID;
+
+typedef PREPACK struct {
+ A_UINT8 cabTimeOut;
+} POSTPACK WHAL_SETCABTO_PARAM;
+
+typedef PREPACK struct {
+ A_UINT8 whalCmdId;
+ A_UINT8 data[1];
+} POSTPACK WHAL_PARAMCMD;
+
+
+#define WOW_MAX_FILTER_LISTS 1 /*4*/
+#define WOW_MAX_FILTERS_PER_LIST 4
+#define WOW_PATTERN_SIZE 64
+#define WOW_MASK_SIZE 64
+
+typedef PREPACK struct {
+ A_UINT8 wow_valid_filter;
+ A_UINT8 wow_filter_id;
+ A_UINT8 wow_filter_size;
+ A_UINT8 wow_filter_offset;
+ A_UINT8 wow_filter_mask[WOW_MASK_SIZE];
+ A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE];
+} POSTPACK WOW_FILTER;
+
+
+typedef PREPACK struct {
+ A_UINT8 wow_valid_list;
+ A_UINT8 wow_list_id;
+ A_UINT8 wow_num_filters;
+ A_UINT8 wow_total_list_size;
+ WOW_FILTER list[WOW_MAX_FILTERS_PER_LIST];
+} POSTPACK WOW_FILTER_LIST;
+
+typedef PREPACK struct {
+ A_BOOL awake;
+ A_BOOL asleep;
+} POSTPACK WMI_SET_HOST_SLEEP_MODE_CMD;
+
+typedef PREPACK struct {
+ A_BOOL enable_wow;
+} POSTPACK WMI_SET_WOW_MODE_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 filter_list_id;
+} POSTPACK WMI_GET_WOW_LIST_CMD;
+
+/*
+ * WMI_GET_WOW_LIST_CMD reply
+ */
+typedef PREPACK struct {
+ A_UINT8 num_filters; /* number of patterns in reply */
+ A_UINT8 this_filter_num; /* this is filter # x of total num_filters */
+ A_UINT8 wow_mode;
+ A_UINT8 host_mode;
+ WOW_FILTER wow_filters[1];
+} POSTPACK WMI_GET_WOW_LIST_REPLY;
+
+typedef PREPACK struct {
+ A_UINT8 filter_list_id;
+ A_UINT8 filter_size;
+ A_UINT8 filter_offset;
+ A_UINT8 filter[1];
+} POSTPACK WMI_ADD_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+ A_UINT16 filter_list_id;
+ A_UINT16 filter_id;
+} POSTPACK WMI_DEL_WOW_PATTERN_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 macaddr[ATH_MAC_LEN];
+} POSTPACK WMI_SET_MAC_ADDRESS_CMD;
+
+/*
+ * WMI_SET_AKMP_PARAMS_CMD
+ */
+
+#define WMI_AKMP_MULTI_PMKID_EN 0x000001
+
+typedef PREPACK struct {
+ A_UINT32 akmpInfo;
+} POSTPACK WMI_SET_AKMP_PARAMS_CMD;
+
+typedef PREPACK struct {
+ A_UINT8 pmkid[WMI_PMKID_LEN];
+} POSTPACK WMI_PMKID;
+
+/*
+ * WMI_SET_PMKID_LIST_CMD
+ */
+#define WMI_MAX_PMKID_CACHE 8
+
+typedef PREPACK struct {
+ A_UINT32 numPMKID;
+ WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
+} POSTPACK WMI_SET_PMKID_LIST_CMD;
+
+/*
+ * WMI_GET_PMKID_LIST_CMD Reply
+ * Following the Number of PMKIDs is the list of PMKIDs
+ */
+typedef PREPACK struct {
+ A_UINT32 numPMKID;
+ WMI_PMKID pmkidList[1];
+} POSTPACK WMI_PMKID_LIST_REPLY;
+
+/* index used for priority streams */
+typedef enum {
+ WMI_NOT_MAPPED = -1,
+ WMI_CONTROL_PRI = 0,
+ WMI_BEST_EFFORT_PRI = 1,
+ WMI_LOW_PRI = 2,
+ WMI_HIGH_PRI = 3,
+ WMI_HIGHEST_PRI,
+ WMI_PRI_MAX_COUNT
+} WMI_PRI_STREAM_ID;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_H_ */
--- /dev/null
+++ b/drivers/ar6000/include/wmix.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * $ATH_LICENSE_HOSTSDK0_C$
+ *
+ * This file contains extensions of the WMI protocol specified in the
+ * Wireless Module Interface (WMI). It includes definitions of all
+ * extended commands and events. Extensions include useful commands
+ * that are not directly related to wireless activities. They may
+ * be hardware-specific, and they might not be supported on all
+ * implementations.
+ *
+ * Extended WMIX commands are encapsulated in a WMI message with
+ * cmd=WMI_EXTENSION_CMD.
+ *
+ */
+
+#ifndef _WMIX_H_
+#define _WMIX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+#include "dbglog.h"
+
+/*
+ * Extended WMI commands are those that are needed during wireless
+ * operation, but which are not really wireless commands. This allows,
+ * for instance, platform-specific commands. Extended WMI commands are
+ * embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
+ * Extended WMI events are similarly embedded in a WMI event message with
+ * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
+ */
+typedef PREPACK struct {
+ A_UINT32 commandId;
+} POSTPACK WMIX_CMD_HDR;
+
+typedef enum {
+ WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
+ WMIX_DSETDATA_REPLY_CMDID,
+ WMIX_GPIO_OUTPUT_SET_CMDID,
+ WMIX_GPIO_INPUT_GET_CMDID,
+ WMIX_GPIO_REGISTER_SET_CMDID,
+ WMIX_GPIO_REGISTER_GET_CMDID,
+ WMIX_GPIO_INTR_ACK_CMDID,
+ WMIX_HB_CHALLENGE_RESP_CMDID,
+ WMIX_DBGLOG_CFG_MODULE_CMDID,
+} WMIX_COMMAND_ID;
+
+typedef enum {
+ WMIX_DSETOPENREQ_EVENTID = 0x3001,
+ WMIX_DSETCLOSE_EVENTID,
+ WMIX_DSETDATAREQ_EVENTID,
+ WMIX_GPIO_INTR_EVENTID,
+ WMIX_GPIO_DATA_EVENTID,
+ WMIX_GPIO_ACK_EVENTID,
+ WMIX_HB_CHALLENGE_RESP_EVENTID,
+ WMIX_DBGLOG_EVENTID,
+} WMIX_EVENT_ID;
+
+/*
+ * =============DataSet support=================
+ */
+
+/*
+ * WMIX_DSETOPENREQ_EVENTID
+ * DataSet Open Request Event
+ */
+typedef PREPACK struct {
+ A_UINT32 dset_id;
+ A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETOPENREQ_EVENT;
+
+/*
+ * WMIX_DSETCLOSE_EVENTID
+ * DataSet Close Event
+ */
+typedef PREPACK struct {
+ A_UINT32 access_cookie;
+} POSTPACK WMIX_DSETCLOSE_EVENT;
+
+/*
+ * WMIX_DSETDATAREQ_EVENTID
+ * DataSet Data Request Event
+ */
+typedef PREPACK struct {
+ A_UINT32 access_cookie;
+ A_UINT32 offset;
+ A_UINT32 length;
+ A_UINT32 targ_buf; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
+ A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
+} POSTPACK WMIX_DSETDATAREQ_EVENT;
+
+typedef PREPACK struct {
+ A_UINT32 status;
+ A_UINT32 targ_dset_handle;
+ A_UINT32 targ_reply_fn;
+ A_UINT32 targ_reply_arg;
+ A_UINT32 access_cookie;
+ A_UINT32 size;
+ A_UINT32 version;
+} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
+
+typedef PREPACK struct {
+ A_UINT32 status;
+ A_UINT32 targ_buf;
+ A_UINT32 targ_reply_fn;
+ A_UINT32 targ_reply_arg;
+ A_UINT32 length;
+ A_UINT8 buf[1];
+} POSTPACK WMIX_DSETDATA_REPLY_CMD;
+
+
+/*
+ * =============GPIO support=================
+ * All masks are 18-bit masks with bit N operating on GPIO pin N.
+ */
+
+#include "gpio.h"
+
+/*
+ * Set GPIO pin output state.
+ * In order for output to be driven, a pin must be enabled for output.
+ * This can be done during initialization through the GPIO Configuration
+ * DataSet, or during operation with the enable_mask.
+ *
+ * If a request is made to simultaneously set/clear or set/disable or
+ * clear/disable or disable/enable, results are undefined.
+ */
+typedef PREPACK struct {
+ A_UINT32 set_mask; /* pins to set */
+ A_UINT32 clear_mask; /* pins to clear */
+ A_UINT32 enable_mask; /* pins to enable for output */
+ A_UINT32 disable_mask; /* pins to disable/tristate */
+} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
+
+/*
+ * Set a GPIO register. For debug/exceptional cases.
+ * Values for gpioreg_id are GPIO_REGISTER_IDs, defined in a
+ * platform-dependent header.
+ */
+typedef PREPACK struct {
+ A_UINT32 gpioreg_id; /* GPIO register ID */
+ A_UINT32 value; /* value to write */
+} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
+
+/* Get a GPIO register. For debug/exceptional cases. */
+typedef PREPACK struct {
+ A_UINT32 gpioreg_id; /* GPIO register to read */
+} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
+
+/*
+ * Host acknowledges and re-arms GPIO interrupts. A single
+ * message should be used to acknowledge all interrupts that
+ * were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
+ */
+typedef PREPACK struct {
+ A_UINT32 ack_mask; /* interrupts to acknowledge */
+} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
+
+/*
+ * Target informs Host of GPIO interrupts that have ocurred since the
+ * last WMIX_GIPO_INTR_ACK_CMD was received. Additional information --
+ * the current GPIO input values is provided -- in order to support
+ * use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
+ */
+typedef PREPACK struct {
+ A_UINT32 intr_mask; /* pending GPIO interrupts */
+ A_UINT32 input_values; /* recent GPIO input values */
+} POSTPACK WMIX_GPIO_INTR_EVENT;
+
+/*
+ * Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ * value set to the mask of GPIO pin inputs and
+ * reg_id set to GPIO_ID_NONE
+ *
+ *
+ * Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
+ * using a GPIO_DATA_EVENT with
+ * value set to the value of the requested register and
+ * reg_id identifying the register (reflects the original request)
+ * NB: reg_id supports the future possibility of unsolicited
+ * WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
+ * simplify Host GPIO support.
+ */
+typedef PREPACK struct {
+ A_UINT32 value;
+ A_UINT32 reg_id;
+} POSTPACK WMIX_GPIO_DATA_EVENT;
+
+/*
+ * =============Error Detection support=================
+ */
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_CMDID
+ * Heartbeat Challenge Response command
+ */
+typedef PREPACK struct {
+ A_UINT32 cookie;
+ A_UINT32 source;
+} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
+
+/*
+ * WMIX_HB_CHALLENGE_RESP_EVENTID
+ * Heartbeat Challenge Response Event
+ */
+#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
+
+typedef PREPACK struct {
+ struct dbglog_config_s config;
+} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMIX_H_ */
--- /dev/null
+++ b/drivers/ar6000/Kconfig
@@ -0,0 +1,7 @@
+config AR6000_WLAN
+ tristate "AR6000 wireless networking over SDIO"
+ depends on MMC
+ select WIRELESS_EXT
+ default m
+ help
+ good luck.
--- /dev/null
+++ b/drivers/ar6000/Makefile
@@ -0,0 +1,38 @@
+REV ?= 2
+
+PWD := $(shell pwd)
+
+EXTRA_CFLAGS += -I$(src)/include
+
+EXTRA_CFLAGS += -DLINUX -D__KERNEL__ -DHTC_RAW_INTERFACE\
+ -DTCMD -DUSER_KEYS \
+ -DNO_SYNC_FLUSH #\
+ -DMULTIPLE_FRAMES_PER_INTERRUPT -DAR6000REV$(REV) \
+ -DBLOCK_TX_PATH_FLAG \
+ -DSDIO \
+
+EXTRA_CFLAGS += -DKERNEL_2_6
+
+obj-$(CONFIG_AR6000_WLAN) += ar6000.o
+
+ar6000-objs += htc/ar6k.o \
+ htc/ar6k_events.o \
+ htc/htc_send.o \
+ htc/htc_recv.o \
+ htc/htc_services.o \
+ htc/htc.o \
+ hif/hif2.o \
+ bmi/bmi.o \
+ ar6000/ar6000_drv.o \
+ ar6000/ar6000_raw_if.o \
+ ar6000/netbuf.o \
+ ar6000/wireless_ext.o \
+ ar6000/ioctl.o \
+ miscdrv/common_drv.o \
+ miscdrv/credit_dist.o \
+ wmi/wmi.o \
+ wlan/wlan_node.o \
+ wlan/wlan_recv_beacon.o \
+ wlan/wlan_utils.o
+
+
--- /dev/null
+++ b/drivers/ar6000/miscdrv/common_drv.c
@@ -0,0 +1,467 @@
+
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "AR6Khwreg.h"
+#include "targaddrs.h"
+#include "a_osapi.h"
+#include "hif.h"
+#include "htc_api.h"
+#include "bmi.h"
+#include "bmi_msg.h"
+#include "common_drv.h"
+#include "a_debug.h"
+#include "targaddrs.h"
+
+#define HOST_INTEREST_ITEM_ADDRESS(target, item) \
+(((TargetType) == TARGET_TYPE_AR6001) ? \
+ AR6001_HOST_INTEREST_ITEM_ADDRESS(item) : \
+ AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
+
+
+/* Compile the 4BYTE version of the window register setup routine,
+ * This mitigates host interconnect issues with non-4byte aligned bus requests, some
+ * interconnects use bus adapters that impose strict limitations.
+ * Since diag window access is not intended for performance critical operations, the 4byte mode should
+ * be satisfactory even though it generates 4X the bus activity. */
+
+#ifdef USE_4BYTE_REGISTER_ACCESS
+
+ /* set the window address register (using 4-byte register access ). */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+ A_STATUS status;
+ A_UINT8 addrValue[4];
+ int i;
+
+ /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+ * last to initiate the access cycle */
+
+ for (i = 1; i <= 3; i++) {
+ /* fill the buffer with the address byte value we want to hit 4 times*/
+ addrValue[0] = ((A_UINT8 *)&Address)[i];
+ addrValue[1] = addrValue[0];
+ addrValue[2] = addrValue[0];
+ addrValue[3] = addrValue[0];
+
+ /* hit each byte of the register address with a 4-byte write operation to the same address,
+ * this is a harmless operation */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr+i,
+ addrValue,
+ 4,
+ HIF_WR_SYNC_BYTE_FIX,
+ NULL);
+ if (status != A_OK) {
+ break;
+ }
+ }
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+ RegisterAddr, Address));
+ return status;
+ }
+
+ /* write the address register again, this time write the whole 4-byte value.
+ * The effect here is that the LSB write causes the cycle to start, the extra
+ * 3 byte write to bytes 1,2,3 has no effect since we are writing the same values again */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr,
+ (A_UCHAR *)(&Address),
+ 4,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+ RegisterAddr, Address));
+ return status;
+ }
+
+ return A_OK;
+
+
+
+}
+
+
+#else
+
+ /* set the window address register */
+A_STATUS ar6000_SetAddressWindowRegister(HIF_DEVICE *hifDevice, A_UINT32 RegisterAddr, A_UINT32 Address)
+{
+ A_STATUS status;
+
+ /* write bytes 1,2,3 of the register to set the upper address bytes, the LSB is written
+ * last to initiate the access cycle */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr+1, /* write upper 3 bytes */
+ ((A_UCHAR *)(&Address))+1,
+ sizeof(A_UINT32)-1,
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write initial bytes of 0x%x to window reg: 0x%X \n",
+ RegisterAddr, Address));
+ return status;
+ }
+
+ /* write the LSB of the register, this initiates the operation */
+ status = HIFReadWrite(hifDevice,
+ RegisterAddr,
+ (A_UCHAR *)(&Address),
+ sizeof(A_UINT8),
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to window reg: 0x%X \n",
+ RegisterAddr, Address));
+ return status;
+ }
+
+ return A_OK;
+}
+
+#endif
+
+/*
+ * Read from the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+ A_STATUS status;
+
+ /* set window register to start read cycle */
+ status = ar6000_SetAddressWindowRegister(hifDevice,
+ WINDOW_READ_ADDR_ADDRESS,
+ *address);
+
+ if (status != A_OK) {
+ return status;
+ }
+
+ /* read the data */
+ status = HIFReadWrite(hifDevice,
+ WINDOW_DATA_ADDRESS,
+ (A_UCHAR *)data,
+ sizeof(A_UINT32),
+ HIF_RD_SYNC_BYTE_INC,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot read from WINDOW_DATA_ADDRESS\n"));
+ return status;
+ }
+
+ return status;
+}
+
+
+/*
+ * Write to the AR6000 through its diagnostic window.
+ * No cooperation from the Target is required for this.
+ */
+A_STATUS
+ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data)
+{
+ A_STATUS status;
+
+ /* set write data */
+ status = HIFReadWrite(hifDevice,
+ WINDOW_DATA_ADDRESS,
+ (A_UCHAR *)data,
+ sizeof(A_UINT32),
+ HIF_WR_SYNC_BYTE_INC,
+ NULL);
+ if (status != A_OK) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n", *data));
+ return status;
+ }
+
+ /* set window register, which starts the write cycle */
+ return ar6000_SetAddressWindowRegister(hifDevice,
+ WINDOW_WRITE_ADDR_ADDRESS,
+ *address);
+}
+
+A_STATUS
+ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length)
+{
+ A_UINT32 count;
+ A_STATUS status = A_OK;
+
+ for (count = 0; count < length; count += 4, address += 4) {
+ if ((status = ar6000_ReadRegDiag(hifDevice, &address,
+ (A_UINT32 *)&data[count])) != A_OK)
+ {
+ break;
+ }
+ }
+
+ return status;
+}
+
+A_STATUS
+ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
+ A_UCHAR *data, A_UINT32 length)
+{
+ A_UINT32 count;
+ A_STATUS status = A_OK;
+
+ for (count = 0; count < length; count += 4, address += 4) {
+ if ((status = ar6000_WriteRegDiag(hifDevice, &address,
+ (A_UINT32 *)&data[count])) != A_OK)
+ {
+ break;
+ }
+ }
+
+ return status;
+}
+
+A_STATUS
+ar6000_reset_device_skipflash(HIF_DEVICE *hifDevice)
+{
+ int i;
+ struct forceROM_s {
+ A_UINT32 addr;
+ A_UINT32 data;
+ };
+ struct forceROM_s *ForceROM;
+ int szForceROM;
+ A_UINT32 instruction;
+
+ static struct forceROM_s ForceROM_REV2[] = {
+ /* NB: This works for old REV2 ROM (old). */
+ {0x00001ff0, 0x175b0027}, /* jump instruction at 0xa0001ff0 */
+ {0x00001ff4, 0x00000000}, /* nop instruction at 0xa0001ff4 */
+
+ {MC_REMAP_TARGET_ADDRESS, 0x00001ff0}, /* remap to 0xa0001ff0 */
+ {MC_REMAP_COMPARE_ADDRESS, 0x01000040},/* ...from 0xbfc00040 */
+ {MC_REMAP_SIZE_ADDRESS, 0x00000000}, /* ...1 cache line */
+ {MC_REMAP_VALID_ADDRESS, 0x00000001}, /* ...remap is valid */
+
+ {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
+
+ {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
+ };
+
+ static struct forceROM_s ForceROM_NEW[] = {
+ /* NB: This works for AR6000 ROM REV3 and beyond. */
+ {LOCAL_SCRATCH_ADDRESS, AR6K_OPTION_IGNORE_FLASH},
+ {LOCAL_COUNT_ADDRESS+0x10, 0}, /* clear BMI credit counter */
+ {RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
+ };
+
+ /*
+ * Examine a semi-arbitrary instruction that's different
+ * in REV2 and other revisions.
+ * NB: If a Host port does not require simultaneous support
+ * for multiple revisions of Target ROM, this code can be elided.
+ */
+ (void)ar6000_ReadDataDiag(hifDevice, 0x01000040,
+ (A_UCHAR *)&instruction, 4);
+
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("instruction=0x%x\n", instruction));
+
+ if (instruction == 0x3c1aa200) {
+ /* It's an old ROM */
+ ForceROM = ForceROM_REV2;
+ szForceROM = sizeof(ForceROM_REV2)/sizeof(*ForceROM);
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using OLD method\n"));
+ } else {
+ ForceROM = ForceROM_NEW;
+ szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Using NEW method\n"));
+ }
+
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Force Target to execute from ROM....\n"));
+ for (i = 0; i < szForceROM; i++)
+ {
+ if (ar6000_WriteRegDiag(hifDevice,
+ &ForceROM[i].addr,
+ &ForceROM[i].data) != A_OK)
+ {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Cannot force Target to execute ROM!\n"));
+ return A_ERROR;
+ }
+ }
+
+ A_MDELAY(50); /* delay to allow dragon to come to BMI phase */
+ return A_OK;
+}
+
+/* reset device */
+A_STATUS ar6000_reset_device(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
+{
+
+#if !defined(DWSIM)
+ A_STATUS status = A_OK;
+ A_UINT32 address;
+ A_UINT32 data;
+
+ do {
+
+ // address = RESET_CONTROL_ADDRESS;
+ data = RESET_CONTROL_COLD_RST_MASK;
+
+ /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target type */
+ if (TargetType == TARGET_TYPE_AR6001) {
+ address = 0x0C000000;
+ } else {
+ if (TargetType == TARGET_TYPE_AR6002) {
+ address = 0x00004000;
+ } else {
+ A_ASSERT(0);
+ }
+ }
+
+ status = ar6000_WriteRegDiag(hifDevice, &address, &data);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ /*
+ * Read back the RESET CAUSE register to ensure that the cold reset
+ * went through.
+ */
+ A_MDELAY(2000); /* 2 second delay to allow things to settle down */
+
+
+ // address = RESET_CAUSE_ADDRESS;
+ /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type */
+ if (TargetType == TARGET_TYPE_AR6001) {
+ address = 0x0C0000CC;
+ } else {
+ if (TargetType == TARGET_TYPE_AR6002) {
+ address = 0x000040C0;
+ } else {
+ A_ASSERT(0);
+ }
+ }
+
+ data = 0;
+ status = ar6000_ReadRegDiag(hifDevice, &address, &data);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Reset Cause readback: 0x%X \n",data));
+ data &= RESET_CAUSE_LAST_MASK;
+ if (data != 2) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Unable to cold reset the target \n"));
+ }
+
+ } while (FALSE);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_LOG_ERR, ("Failed to reset target \n"));
+ }
+#endif
+ return A_OK;
+}
+
+#define REG_DUMP_COUNT_AR6001 38 /* WORDs, derived from AR6001_regdump.h */
+#define REG_DUMP_COUNT_AR6002 32 /* WORDs, derived from AR6002_regdump.h */
+
+
+#if REG_DUMP_COUNT_AR6001 <= REG_DUMP_COUNT_AR6002
+#define REGISTER_DUMP_LEN_MAX REG_DUMP_COUNT_AR6002
+#else
+#define REGISTER_DUMP_LEN_MAX REG_DUMP_COUNT_AR6001
+#endif
+
+void ar6000_dump_target_assert_info(HIF_DEVICE *hifDevice, A_UINT32 TargetType)
+{
+ A_UINT32 address;
+ A_UINT32 regDumpArea = 0;
+ A_STATUS status;
+ A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX];
+ A_UINT32 regDumpCount = 0;
+ A_UINT32 i;
+
+ do {
+
+ /* the reg dump pointer is copied to the host interest area */
+ address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state);
+
+ if (TargetType == TARGET_TYPE_AR6001) {
+ /* for AR6001, this is a fixed location because the ptr is actually stuck in cache,
+ * this may be fixed in later firmware versions */
+ address = 0x18a0;
+ regDumpCount = REG_DUMP_COUNT_AR6001;
+
+ } else if (TargetType == TARGET_TYPE_AR6002) {
+
+ regDumpCount = REG_DUMP_COUNT_AR6002;
+
+ } else {
+ A_ASSERT(0);
+ }
+
+ /* read RAM location through diagnostic window */
+ status = ar6000_ReadRegDiag(hifDevice, &address, &regDumpArea);
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get ptr to register dump area \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Location of register dump data: 0x%X \n",regDumpArea));
+
+ if (regDumpArea == 0) {
+ /* no reg dump */
+ break;
+ }
+
+ if (TargetType == TARGET_TYPE_AR6001) {
+ regDumpArea &= 0x0FFFFFFF; /* convert to physical address in target memory */
+ }
+
+ /* fetch register dump data */
+ status = ar6000_ReadDataDiag(hifDevice,
+ regDumpArea,
+ (A_UCHAR *)&regDumpValues[0],
+ regDumpCount * (sizeof(A_UINT32)));
+
+ if (A_FAILED(status)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Failed to get register dump \n"));
+ break;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("AR6K: Register Dump: \n"));
+
+ for (i = 0; i < regDumpCount; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" %d : 0x%8.8X \n",i, regDumpValues[i]));
+ }
+
+ } while (FALSE);
+
+}
+
--- /dev/null
+++ b/drivers/ar6000/miscdrv/credit_dist.c
@@ -0,0 +1,346 @@
+
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include "a_debug.h"
+#include "htc_api.h"
+#include "common_drv.h"
+
+/********* CREDIT DISTRIBUTION FUNCTIONS ******************************************/
+
+#define NO_VO_SERVICE 1 /* currently WMI only uses 3 data streams, so we leave VO service inactive */
+
+#ifdef NO_VO_SERVICE
+#define DATA_SVCS_USED 3
+#else
+#define DATA_SVCS_USED 4
+#endif
+
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList);
+
+/* reduce an ep's credits back to a set limit */
+static INLINE void ReduceCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEpDist,
+ int Limit)
+{
+ int credits;
+
+ /* set the new limit */
+ pEpDist->TxCreditsAssigned = Limit;
+
+ if (pEpDist->TxCredits <= Limit) {
+ return;
+ }
+
+ /* figure out how much to take away */
+ credits = pEpDist->TxCredits - Limit;
+ /* take them away */
+ pEpDist->TxCredits -= credits;
+ pCredInfo->CurrentFreeCredits += credits;
+}
+
+/* give an endpoint some credits from the free credit pool */
+#define GiveCredits(pCredInfo,pEpDist,credits) \
+{ \
+ (pEpDist)->TxCredits += (credits); \
+ (pEpDist)->TxCreditsAssigned += (credits); \
+ (pCredInfo)->CurrentFreeCredits -= (credits); \
+}
+
+
+/* default credit init callback.
+ * This function is called in the context of HTCStart() to setup initial (application-specific)
+ * credit distributions */
+static void ar6000_credit_init(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPList,
+ int TotalCredits)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ int count;
+ COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+ pCredInfo->CurrentFreeCredits = TotalCredits;
+ pCredInfo->TotalAvailableCredits = TotalCredits;
+
+ pCurEpDist = pEPList;
+
+ /* run through the list and initialize */
+ while (pCurEpDist != NULL) {
+
+ /* set minimums for each endpoint */
+ pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
+
+ if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+ /* give control service some credits */
+ GiveCredits(pCredInfo,pCurEpDist,pCurEpDist->TxCreditsMin);
+ /* control service is always marked active, it never goes inactive EVER */
+ SET_EP_ACTIVE(pCurEpDist);
+ } else if (pCurEpDist->ServiceID == WMI_DATA_BK_SVC) {
+ /* this is the lowest priority data endpoint, save this off for easy access */
+ pCredInfo->pLowestPriEpDist = pCurEpDist;
+ }
+
+ /* Streams have to be created (explicit | implicit)for all kinds
+ * of traffic. BE endpoints are also inactive in the beginning.
+ * When BE traffic starts it creates implicit streams that
+ * redistributes credits.
+ */
+
+ /* note, all other endpoints have minimums set but are initially given NO credits.
+ * Credits will be distributed as traffic activity demands */
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+ if (pCredInfo->CurrentFreeCredits <= 0) {
+ AR_DEBUG_PRINTF(ATH_LOG_INF, ("Not enough credits (%d) to do credit distributions \n", TotalCredits));
+ A_ASSERT(FALSE);
+ return;
+ }
+
+ /* reset list */
+ pCurEpDist = pEPList;
+ /* now run through the list and set max operating credit limits for everyone */
+ while (pCurEpDist != NULL) {
+ if (pCurEpDist->ServiceID == WMI_CONTROL_SVC) {
+ /* control service max is just 1 max message */
+ pCurEpDist->TxCreditsNorm = pCurEpDist->TxCreditsPerMaxMsg;
+ } else {
+ /* for the remaining data endpoints, we assume that each TxCreditsPerMaxMsg are
+ * the same.
+ * We use a simple calculation here, we take the remaining credits and
+ * determine how many max messages this can cover and then set each endpoint's
+ * normal value equal to half this amount.
+ * */
+ count = (pCredInfo->CurrentFreeCredits/pCurEpDist->TxCreditsPerMaxMsg) * pCurEpDist->TxCreditsPerMaxMsg;
+ count = count >> 1;
+ count = max(count,pCurEpDist->TxCreditsPerMaxMsg);
+ /* set normal */
+ pCurEpDist->TxCreditsNorm = count;
+
+ }
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+}
+
+
+/* default credit distribution callback
+ * This callback is invoked whenever endpoints require credit distributions.
+ * A lock is held while this function is invoked, this function shall NOT block.
+ * The pEPDistList is a list of distribution structures in prioritized order as
+ * defined by the call to the HTCSetCreditDistribution() api.
+ *
+ */
+static void ar6000_credit_distribute(void *Context,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
+ HTC_CREDIT_DIST_REASON Reason)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ COMMON_CREDIT_STATE_INFO *pCredInfo = (COMMON_CREDIT_STATE_INFO *)Context;
+
+ switch (Reason) {
+ case HTC_CREDIT_DIST_SEND_COMPLETE :
+ pCurEpDist = pEPDistList;
+ /* we are given the start of the endpoint distribution list.
+ * There may be one or more endpoints to service.
+ * Run through the list and distribute credits */
+ while (pCurEpDist != NULL) {
+
+ if (pCurEpDist->TxCreditsToDist > 0) {
+ /* return the credits back to the endpoint */
+ pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
+ /* always zero out when we are done */
+ pCurEpDist->TxCreditsToDist = 0;
+
+ if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsAssigned) {
+ /* reduce to the assigned limit, previous credit reductions
+ * could have caused the limit to change */
+ ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsAssigned);
+ }
+
+ if (pCurEpDist->TxCredits > pCurEpDist->TxCreditsNorm) {
+ /* oversubscribed endpoints need to reduce back to normal */
+ ReduceCredits(pCredInfo, pCurEpDist, pCurEpDist->TxCreditsNorm);
+ }
+ }
+
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+ A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
+
+ break;
+
+ case HTC_CREDIT_DIST_ACTIVITY_CHANGE :
+ RedistributeCredits(pCredInfo,pEPDistList);
+ break;
+ case HTC_CREDIT_DIST_SEEK_CREDITS :
+ SeekCredits(pCredInfo,pEPDistList);
+ break;
+ case HTC_DUMP_CREDIT_STATE :
+ AR_DEBUG_PRINTF(ATH_LOG_INF, ("Credit Distribution, total : %d, free : %d\n",
+ pCredInfo->TotalAvailableCredits, pCredInfo->CurrentFreeCredits));
+ break;
+ default:
+ break;
+
+ }
+
+}
+
+/* redistribute credits based on activity change */
+static void RedistributeCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDistList)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist = pEPDistList;
+
+ /* walk through the list and remove credits from inactive endpoints */
+ while (pCurEpDist != NULL) {
+
+ if (pCurEpDist->ServiceID != WMI_CONTROL_SVC) {
+ if (!IS_EP_ACTIVE(pCurEpDist)) {
+ /* EP is inactive, reduce credits back to zero */
+ ReduceCredits(pCredInfo, pCurEpDist, 0);
+ }
+ }
+
+ /* NOTE in the active case, we do not need to do anything further,
+ * when an EP goes active and needs credits, HTC will call into
+ * our distribution function using a reason code of HTC_CREDIT_DIST_SEEK_CREDITS */
+
+ pCurEpDist = pCurEpDist->pNext;
+ }
+
+ A_ASSERT(pCredInfo->CurrentFreeCredits <= pCredInfo->TotalAvailableCredits);
+
+}
+
+/* HTC has an endpoint that needs credits, pEPDist is the endpoint in question */
+static void SeekCredits(COMMON_CREDIT_STATE_INFO *pCredInfo,
+ HTC_ENDPOINT_CREDIT_DIST *pEPDist)
+{
+ HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
+ int credits = 0;
+ int need;
+
+ do {
+
+ if (pEPDist->ServiceID == WMI_CONTROL_SVC) {
+ /* we never oversubscribe on the control service, this is not
+ * a high performance path and the target never holds onto control
+ * credits for too long */
+ break;
+ }
+
+ /* for all other services, we follow a simple algorithm of
+ * 1. checking the free pool for credits
+ * 2. checking lower priority endpoints for credits to take */
+
+ if (pCredInfo->CurrentFreeCredits >= 2 * pEPDist->TxCreditsSeek) {
+ /* try to give more credits than it needs */
+ credits = 2 * pEPDist->TxCreditsSeek;
+ } else {
+ /* give what we can */
+ credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+ }
+
+ if (credits >= pEPDist->TxCreditsSeek) {
+ /* we found some to fullfill the seek request */
+ break;
+ }
+
+ /* we don't have enough in the free pool, try taking away from lower priority services
+ *
+ * The rule for taking away credits:
+ * 1. Only take from lower priority endpoints
+ * 2. Only take what is allocated above the minimum (never starve an endpoint completely)
+ * 3. Only take what you need.
+ *
+ * */
+
+ /* starting at the lowest priority */
+ pCurEpDist = pCredInfo->pLowestPriEpDist;
+
+ /* work backwards until we hit the endpoint again */
+ while (pCurEpDist != pEPDist) {
+ /* calculate how many we need so far */
+ need = pEPDist->TxCreditsSeek - pCredInfo->CurrentFreeCredits;
+
+ if ((pCurEpDist->TxCreditsAssigned - need) > pCurEpDist->TxCreditsMin) {
+ /* the current one has been allocated more than it's minimum and it
+ * has enough credits assigned above it's minimum to fullfill our need
+ * try to take away just enough to fullfill our need */
+ ReduceCredits(pCredInfo,
+ pCurEpDist,
+ pCurEpDist->TxCreditsAssigned - need);
+
+ if (pCredInfo->CurrentFreeCredits >= pEPDist->TxCreditsSeek) {
+ /* we have enough */
+ break;
+ }
+ }
+
+ pCurEpDist = pCurEpDist->pPrev;
+ }
+
+ /* return what we can get */
+ credits = min(pCredInfo->CurrentFreeCredits,pEPDist->TxCreditsSeek);
+
+ } while (FALSE);
+
+ /* did we find some credits? */
+ if (credits) {
+ /* give what we can */
+ GiveCredits(pCredInfo, pEPDist, credits);
+ }
+
+}
+
+/* initialize and setup credit distribution */
+A_STATUS ar6000_setup_credit_dist(HTC_HANDLE HTCHandle, COMMON_CREDIT_STATE_INFO *pCredInfo)
+{
+ HTC_SERVICE_ID servicepriority[5];
+
+ A_MEMZERO(pCredInfo,sizeof(COMMON_CREDIT_STATE_INFO));
+
+ servicepriority[0] = WMI_CONTROL_SVC; /* highest */
+ servicepriority[1] = WMI_DATA_VO_SVC;
+ servicepriority[2] = WMI_DATA_VI_SVC;
+ servicepriority[3] = WMI_DATA_BE_SVC;
+ servicepriority[4] = WMI_DATA_BK_SVC; /* lowest */
+
+ /* set callbacks and priority list */
+ HTCSetCreditDistribution(HTCHandle,
+ pCredInfo,
+ ar6000_credit_distribute,
+ ar6000_credit_init,
+ servicepriority,
+ 5);
+
+ return A_OK;
+}
+
--- /dev/null
+++ b/drivers/ar6000/wlan/wlan_node.c
@@ -0,0 +1,371 @@
+/*-
+ * Copyright (c) 2001 Atsushi Onoe
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
+ * Copyright (c) 2004-2005 Atheros Communications
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/wlan/src/wlan_node.c#1 $
+ */
+/*
+ * IEEE 802.11 node handling support.
+ */
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include <a_debug.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+#include <ieee80211_node.h>
+#include <htc_api.h>
+#include <wmi.h>
+#include <wmi_api.h>
+
+static void wlan_node_timeout(A_ATH_TIMER arg);
+static bss_t * _ieee80211_find_node(struct ieee80211_node_table *nt,
+ const A_UINT8 *macaddr);
+
+bss_t *
+wlan_node_alloc(struct ieee80211_node_table *nt, int wh_size)
+{
+ bss_t *ni;
+
+ ni = A_MALLOC_NOWAIT(sizeof(bss_t));
+
+ if (ni != NULL) {
+ ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
+ if (ni->ni_buf == NULL) {
+ A_FREE(ni);
+ ni = NULL;
+ return ni;
+ }
+ } else {
+ return ni;
+ }
+
+ /* Make sure our lists are clean */
+ ni->ni_list_next = NULL;
+ ni->ni_list_prev = NULL;
+ ni->ni_hash_next = NULL;
+ ni->ni_hash_prev = NULL;
+
+ //
+ // ni_scangen never initialized before and during suspend/resume of winmobile, customer (LG/SEMCO) identified
+ // that some junk has been stored in this, due to this scan list didn't properly updated
+ //
+ ni->ni_scangen = 0;
+
+ return ni;
+}
+
+void
+wlan_node_free(bss_t *ni)
+{
+ if (ni->ni_buf != NULL) {
+ A_FREE(ni->ni_buf);
+ }
+ A_FREE(ni);
+}
+
+void
+wlan_setup_node(struct ieee80211_node_table *nt, bss_t *ni,
+ const A_UINT8 *macaddr)
+{
+ int hash;
+
+ A_MEMCPY(ni->ni_macaddr, macaddr, IEEE80211_ADDR_LEN);
+ hash = IEEE80211_NODE_HASH(macaddr);
+ ieee80211_node_initref(ni); /* mark referenced */
+
+ ni->ni_tstamp = A_GET_MS(WLAN_NODE_INACT_TIMEOUT_MSEC);
+ IEEE80211_NODE_LOCK_BH(nt);
+
+ /* Insert at the end of the node list */
+ ni->ni_list_next = NULL;
+ ni->ni_list_prev = nt->nt_node_last;
+ if(nt->nt_node_last != NULL)
+ {
+ nt->nt_node_last->ni_list_next = ni;
+ }
+ nt->nt_node_last = ni;
+ if(nt->nt_node_first == NULL)
+ {
+ nt->nt_node_first = ni;
+ }
+
+ /* Insert into the hash list i.e. the bucket */
+ if((ni->ni_hash_next = nt->nt_hash[hash]) != NULL)
+ {
+ nt->nt_hash[hash]->ni_hash_prev = ni;
+ }
+ ni->ni_hash_prev = NULL;
+ nt->nt_hash[hash] = ni;
+
+ if (!nt->isTimerArmed) {
+ A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
+ nt->isTimerArmed = TRUE;
+ }
+
+ IEEE80211_NODE_UNLOCK_BH(nt);
+}
+
+static bss_t *
+_ieee80211_find_node(struct ieee80211_node_table *nt,
+ const A_UINT8 *macaddr)
+{
+ bss_t *ni;
+ int hash;
+
+ IEEE80211_NODE_LOCK_ASSERT(nt);
+
+ hash = IEEE80211_NODE_HASH(macaddr);
+ for(ni = nt->nt_hash[hash]; ni; ni = ni->ni_hash_next) {
+ if (IEEE80211_ADDR_EQ(ni->ni_macaddr, macaddr)) {
+ ieee80211_node_incref(ni); /* mark referenced */
+ return ni;
+ }
+ }
+ return NULL;
+}
+
+bss_t *
+wlan_find_node(struct ieee80211_node_table *nt, const A_UINT8 *macaddr)
+{
+ bss_t *ni;
+
+ IEEE80211_NODE_LOCK(nt);
+ ni = _ieee80211_find_node(nt, macaddr);
+ IEEE80211_NODE_UNLOCK(nt);
+ return ni;
+}
+
+/*
+ * Reclaim a node. If this is the last reference count then
+ * do the normal free work. Otherwise remove it from the node
+ * table and mark it gone by clearing the back-reference.
+ */
+void
+wlan_node_reclaim(struct ieee80211_node_table *nt, bss_t *ni)
+{
+ IEEE80211_NODE_LOCK(nt);
+
+ if(ni->ni_list_prev == NULL)
+ {
+ /* First in list so fix the list head */
+ nt->nt_node_first = ni->ni_list_next;
+ }
+ else
+ {
+ ni->ni_list_prev->ni_list_next = ni->ni_list_next;
+ }
+
+ if(ni->ni_list_next == NULL)
+ {
+ /* Last in list so fix list tail */
+ nt->nt_node_last = ni->ni_list_prev;
+ }
+ else
+ {
+ ni->ni_list_next->ni_list_prev = ni->ni_list_prev;
+ }
+
+ if(ni->ni_hash_prev == NULL)
+ {
+ /* First in list so fix the list head */
+ int hash;
+ hash = IEEE80211_NODE_HASH(ni->ni_macaddr);
+ nt->nt_hash[hash] = ni->ni_hash_next;
+ }
+ else
+ {
+ ni->ni_hash_prev->ni_hash_next = ni->ni_hash_next;
+ }
+
+ if(ni->ni_hash_next != NULL)
+ {
+ ni->ni_hash_next->ni_hash_prev = ni->ni_hash_prev;
+ }
+ wlan_node_free(ni);
+
+ IEEE80211_NODE_UNLOCK(nt);
+}
+
+static void
+wlan_node_dec_free(bss_t *ni)
+{
+ if (ieee80211_node_dectestref(ni)) {
+ wlan_node_free(ni);
+ }
+}
+
+void
+wlan_free_allnodes(struct ieee80211_node_table *nt)
+{
+ bss_t *ni;
+
+ while ((ni = nt->nt_node_first) != NULL) {
+ wlan_node_reclaim(nt, ni);
+ }
+}
+
+void
+wlan_iterate_nodes(struct ieee80211_node_table *nt, wlan_node_iter_func *f,
+ void *arg)
+{
+ bss_t *ni;
+ A_UINT32 gen;
+
+ gen = ++nt->nt_scangen;
+
+ IEEE80211_NODE_LOCK(nt);
+ for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+ if (ni->ni_scangen != gen) {
+ ni->ni_scangen = gen;
+ (void) ieee80211_node_incref(ni);
+ (*f)(arg, ni);
+ wlan_node_dec_free(ni);
+ }
+ }
+ IEEE80211_NODE_UNLOCK(nt);
+}
+
+/*
+ * Node table support.
+ */
+void
+wlan_node_table_init(void *wmip, struct ieee80211_node_table *nt)
+{
+ int i;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WLAN, ("node table = 0x%x\n", (A_UINT32)nt));
+ IEEE80211_NODE_LOCK_INIT(nt);
+
+ nt->nt_node_first = nt->nt_node_last = NULL;
+ for(i = 0; i < IEEE80211_NODE_HASHSIZE; i++)
+ {
+ nt->nt_hash[i] = NULL;
+ }
+ A_INIT_TIMER(&nt->nt_inact_timer, wlan_node_timeout, nt);
+ nt->isTimerArmed = FALSE;
+ nt->nt_wmip = wmip;
+}
+
+static void
+wlan_node_timeout(A_ATH_TIMER arg)
+{
+ struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
+ bss_t *bss, *nextBss;
+ A_UINT8 myBssid[IEEE80211_ADDR_LEN], reArmTimer = FALSE;
+
+ wmi_get_current_bssid(nt->nt_wmip, myBssid);
+
+ bss = nt->nt_node_first;
+ while (bss != NULL)
+ {
+ nextBss = bss->ni_list_next;
+ if (A_MEMCMP(myBssid, bss->ni_macaddr, sizeof(myBssid)) != 0)
+ {
+
+ if (bss->ni_tstamp <= A_GET_MS(0))
+ {
+ /*
+ * free up all but the current bss - if set
+ */
+ wlan_node_reclaim(nt, bss);
+ }
+ else
+ {
+ /*
+ * Re-arm timer, only when we have a bss other than
+ * current bss AND it is not aged-out.
+ */
+ reArmTimer = TRUE;
+ }
+ }
+ bss = nextBss;
+ }
+
+ if(reArmTimer)
+ A_TIMEOUT_MS(&nt->nt_inact_timer, WLAN_NODE_INACT_TIMEOUT_MSEC, 0);
+
+ nt->isTimerArmed = reArmTimer;
+}
+
+void
+wlan_node_table_cleanup(struct ieee80211_node_table *nt)
+{
+ A_UNTIMEOUT(&nt->nt_inact_timer);
+ A_DELETE_TIMER(&nt->nt_inact_timer);
+ wlan_free_allnodes(nt);
+ IEEE80211_NODE_LOCK_DESTROY(nt);
+}
+
+bss_t *
+wlan_find_Ssidnode (struct ieee80211_node_table *nt, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2)
+{
+ bss_t *ni = NULL;
+ A_UCHAR *pIESsid = NULL;
+
+ IEEE80211_NODE_LOCK (nt);
+
+ for (ni = nt->nt_node_first; ni; ni = ni->ni_list_next) {
+ pIESsid = ni->ni_cie.ie_ssid;
+ if (pIESsid[1] <= 32) {
+
+ // Step 1 : Check SSID
+ if (0x00 == memcmp (pSsid, &pIESsid[2], ssidLength)) {
+
+ // Step 2 : if SSID matches, check WPA or WPA2
+ if (TRUE == bIsWPA2 && NULL != ni->ni_cie.ie_rsn) {
+ ieee80211_node_incref (ni); /* mark referenced */
+ IEEE80211_NODE_UNLOCK (nt);
+ return ni;
+ }
+ if (FALSE == bIsWPA2 && NULL != ni->ni_cie.ie_wpa) {
+ ieee80211_node_incref(ni); /* mark referenced */
+ IEEE80211_NODE_UNLOCK (nt);
+ return ni;
+ }
+ }
+ }
+ }
+
+ IEEE80211_NODE_UNLOCK (nt);
+
+ return NULL;
+}
+
+void
+wlan_node_return (struct ieee80211_node_table *nt, bss_t *ni)
+{
+ IEEE80211_NODE_LOCK (nt);
+ wlan_node_dec_free (ni);
+ IEEE80211_NODE_UNLOCK (nt);
+}
--- /dev/null
+++ b/drivers/ar6000/wlan/wlan_recv_beacon.c
@@ -0,0 +1,192 @@
+/*-
+ * Copyright (c) 2001 Atsushi Onoe
+ * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * IEEE 802.11 input handling.
+ */
+
+#include "a_config.h"
+#include "athdefs.h"
+#include "a_types.h"
+#include "a_osapi.h"
+#include <wmi.h>
+#include <ieee80211.h>
+#include <wlan_api.h>
+
+#define IEEE80211_VERIFY_LENGTH(_len, _minlen) do { \
+ if ((_len) < (_minlen)) { \
+ return A_EINVAL; \
+ } \
+} while (0)
+
+#define IEEE80211_VERIFY_ELEMENT(__elem, __maxlen) do { \
+ if ((__elem) == NULL) { \
+ return A_EINVAL; \
+ } \
+ if ((__elem)[1] > (__maxlen)) { \
+ return A_EINVAL; \
+ } \
+} while (0)
+
+
+/* unaligned little endian access */
+#define LE_READ_2(p) \
+ ((A_UINT16) \
+ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8)))
+
+#define LE_READ_4(p) \
+ ((A_UINT32) \
+ ((((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \
+ (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24)))
+
+
+static int __inline
+iswpaoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((WPA_OUI_TYPE<<24)|WPA_OUI);
+}
+
+static int __inline
+iswmmoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((WMM_OUI_TYPE<<24)|WMM_OUI);
+}
+
+static int __inline
+iswmmparam(const A_UINT8 *frm)
+{
+ return frm[1] > 5 && frm[6] == WMM_PARAM_OUI_SUBTYPE;
+}
+
+static int __inline
+iswmminfo(const A_UINT8 *frm)
+{
+ return frm[1] > 5 && frm[6] == WMM_INFO_OUI_SUBTYPE;
+}
+
+static int __inline
+isatherosoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((ATH_OUI_TYPE<<24)|ATH_OUI);
+}
+
+static int __inline
+iswscoui(const A_UINT8 *frm)
+{
+ return frm[1] > 3 && LE_READ_4(frm+2) == ((0x04<<24)|WPA_OUI);
+}
+
+A_STATUS
+wlan_parse_beacon(A_UINT8 *buf, int framelen, struct ieee80211_common_ie *cie)
+{
+ A_UINT8 *frm, *efrm;
+
+ frm = buf;
+ efrm = (A_UINT8 *) (frm + framelen);
+
+ /*
+ * beacon/probe response frame format
+ * [8] time stamp
+ * [2] beacon interval
+ * [2] capability information
+ * [tlv] ssid
+ * [tlv] supported rates
+ * [tlv] country information
+ * [tlv] parameter set (FH/DS)
+ * [tlv] erp information
+ * [tlv] extended supported rates
+ * [tlv] WMM
+ * [tlv] WPA or RSN
+ * [tlv] Atheros Advanced Capabilities
+ */
+ IEEE80211_VERIFY_LENGTH(efrm - frm, 12);
+ A_MEMZERO(cie, sizeof(*cie));
+
+ cie->ie_tstamp = frm; frm += 8;
+ cie->ie_beaconInt = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2;
+ cie->ie_capInfo = A_LE2CPU16(*(A_UINT16 *)frm); frm += 2;
+ cie->ie_chan = 0;
+
+ while (frm < efrm) {
+ switch (*frm) {
+ case IEEE80211_ELEMID_SSID:
+ cie->ie_ssid = frm;
+ break;
+ case IEEE80211_ELEMID_RATES:
+ cie->ie_rates = frm;
+ break;
+ case IEEE80211_ELEMID_COUNTRY:
+ cie->ie_country = frm;
+ break;
+ case IEEE80211_ELEMID_FHPARMS:
+ break;
+ case IEEE80211_ELEMID_DSPARMS:
+ cie->ie_chan = frm[2];
+ break;
+ case IEEE80211_ELEMID_TIM:
+ cie->ie_tim = frm;
+ break;
+ case IEEE80211_ELEMID_IBSSPARMS:
+ break;
+ case IEEE80211_ELEMID_XRATES:
+ cie->ie_xrates = frm;
+ break;
+ case IEEE80211_ELEMID_ERP:
+ if (frm[1] != 1) {
+ //A_PRINTF("Discarding ERP Element - Bad Len\n");
+ return A_EINVAL;
+ }
+ cie->ie_erp = frm[2];
+ break;
+ case IEEE80211_ELEMID_RSN:
+ cie->ie_rsn = frm;
+ break;
+ case IEEE80211_ELEMID_VENDOR:
+ if (iswpaoui(frm)) {
+ cie->ie_wpa = frm;
+ } else if (iswmmoui(frm)) {
+ cie->ie_wmm = frm;
+ } else if (isatherosoui(frm)) {
+ cie->ie_ath = frm;
+ } else if(iswscoui(frm)) {
+ cie->ie_wsc = frm;
+ }
+ break;
+ default:
+ break;
+ }
+ frm += frm[1] + 2;
+ }
+ IEEE80211_VERIFY_ELEMENT(cie->ie_rates, IEEE80211_RATE_MAXSIZE);
+ IEEE80211_VERIFY_ELEMENT(cie->ie_ssid, IEEE80211_NWID_LEN);
+
+ return A_OK;
+}
--- /dev/null
+++ b/drivers/ar6000/wlan/wlan_utils.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2004-2005 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This module implements frequently used wlan utilies
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/wlan/src/wlan_utils.c#1 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+
+/*
+ * converts ieee channel number to frequency
+ */
+A_UINT16
+wlan_ieee2freq(int chan)
+{
+ if (chan == 14) {
+ return 2484;
+ }
+ if (chan < 14) { /* 0-13 */
+ return (2407 + (chan*5));
+ }
+ if (chan < 27) { /* 15-26 */
+ return (2512 + ((chan-15)*20));
+ }
+ return (5000 + (chan*5));
+}
+
+/*
+ * Converts MHz frequency to IEEE channel number.
+ */
+A_UINT32
+wlan_freq2ieee(A_UINT16 freq)
+{
+ if (freq == 2484)
+ return 14;
+ if (freq < 2484)
+ return (freq - 2407) / 5;
+ if (freq < 5000)
+ return 15 + ((freq - 2512) / 20);
+ return (freq - 5000) / 5;
+}
--- /dev/null
+++ b/drivers/ar6000/wmi/wmi.c
@@ -0,0 +1,3954 @@
+/*
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This module implements the hardware independent layer of the
+ * Wireless Module Interface (WMI) protocol.
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/wmi/wmi.c#3 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#include <a_config.h>
+#include <athdefs.h>
+#include <a_types.h>
+#include <a_osapi.h>
+#include "htc.h"
+#include "htc_api.h"
+#include "wmi.h"
+#include <ieee80211.h>
+#include <ieee80211_node.h>
+#include <wlan_api.h>
+#include <wmi_api.h>
+#include "dset_api.h"
+#include "gpio_api.h"
+#include "wmi_host.h"
+#include "a_drv.h"
+#include "a_drv_api.h"
+#include "a_debug.h"
+#include "dbglog_api.h"
+
+static A_STATUS wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_sync_point(struct wmi_t *wmip);
+
+static A_STATUS wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+
+static A_STATUS wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+
+static A_STATUS wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap,
+ int len);
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len);
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+static A_STATUS wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+#endif
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_UINT32 rateIndex);
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+static A_STATUS wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len);
+
+int wps_enable;
+static const A_INT32 wmi_rateTable[] = {
+ 1000,
+ 2000,
+ 5500,
+ 11000,
+ 6000,
+ 9000,
+ 12000,
+ 18000,
+ 24000,
+ 36000,
+ 48000,
+ 54000,
+ 0};
+
+#define MODE_A_SUPPORT_RATE_START 4
+#define MODE_A_SUPPORT_RATE_STOP 11
+
+#define MODE_GONLY_SUPPORT_RATE_START MODE_A_SUPPORT_RATE_START
+#define MODE_GONLY_SUPPORT_RATE_STOP MODE_A_SUPPORT_RATE_STOP
+
+#define MODE_B_SUPPORT_RATE_START 0
+#define MODE_B_SUPPORT_RATE_STOP 3
+
+#define MODE_G_SUPPORT_RATE_START 0
+#define MODE_G_SUPPORT_RATE_STOP 11
+
+#define MAX_NUMBER_OF_SUPPORT_RATES (MODE_G_SUPPORT_RATE_STOP + 1)
+
+/* 802.1d to AC mapping. Refer pg 57 of WMM-test-plan-v1.2 */
+const A_UINT8 up_to_ac[]= {
+ WMM_AC_BE,
+ WMM_AC_BK,
+ WMM_AC_BK,
+ WMM_AC_BE,
+ WMM_AC_VI,
+ WMM_AC_VI,
+ WMM_AC_VO,
+ WMM_AC_VO,
+ };
+
+void *
+wmi_init(void *devt)
+{
+ struct wmi_t *wmip;
+
+ wmip = A_MALLOC(sizeof(struct wmi_t));
+ if (wmip == NULL) {
+ return (NULL);
+ }
+ A_MEMZERO(wmip, sizeof(*wmip));
+ A_MUTEX_INIT(&wmip->wmi_lock);
+ wmip->wmi_devt = devt;
+ wlan_node_table_init(wmip, &wmip->wmi_scan_table);
+ wmi_qos_state_init(wmip);
+ wmip->wmi_powerMode = REC_POWER;
+ wmip->wmi_phyMode = WMI_11G_MODE;
+
+ return (wmip);
+}
+
+void
+wmi_qos_state_init(struct wmi_t *wmip)
+{
+ A_UINT8 i;
+
+ if (wmip == NULL) {
+ return;
+ }
+ LOCK_WMI(wmip);
+
+ /* Initialize QoS States */
+ wmip->wmi_numQoSStream = 0;
+
+ wmip->wmi_fatPipeExists = 0;
+
+ for (i=0; i < WMM_NUM_AC; i++) {
+ wmip->wmi_streamExistsForAC[i]=0;
+ }
+
+ /* Initialize the static Wmi stream Pri to WMM AC mappings Arrays */
+ WMI_INIT_WMISTREAM_AC_MAP(wmip);
+
+ UNLOCK_WMI(wmip);
+
+ A_WMI_SET_NUMDATAENDPTS(wmip->wmi_devt, 1);
+}
+
+void
+wmi_shutdown(struct wmi_t *wmip)
+{
+ if (wmip != NULL) {
+ wlan_node_table_cleanup(&wmip->wmi_scan_table);
+ if (A_IS_MUTEX_VALID(&wmip->wmi_lock)) {
+ A_MUTEX_DELETE(&wmip->wmi_lock);
+ }
+ A_FREE(wmip);
+ }
+}
+
+/*
+ * performs DIX to 802.3 encapsulation for transmit packets.
+ * uses passed in buffer. Returns buffer or NULL if failed.
+ * Assumes the entire DIX header is contigous and that there is
+ * enough room in the buffer for a 802.3 mac header and LLC+SNAP headers.
+ */
+A_STATUS
+wmi_dix_2_dot3(struct wmi_t *wmip, void *osbuf)
+{
+ A_UINT8 *datap;
+ A_UINT16 typeorlen;
+ ATH_MAC_HDR macHdr;
+ ATH_LLC_SNAP_HDR *llcHdr;
+
+ A_ASSERT(osbuf != NULL);
+
+ if (A_NETBUF_HEADROOM(osbuf) <
+ (sizeof(ATH_LLC_SNAP_HDR) + sizeof(WMI_DATA_HDR)))
+ {
+ return A_NO_MEMORY;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ typeorlen = *(A_UINT16 *)(datap + ATH_MAC_LEN + ATH_MAC_LEN);
+
+ if (!IS_ETHERTYPE(A_BE2CPU16(typeorlen))) {
+ /*
+ * packet is already in 802.3 format - return success
+ */
+ A_DPRINTF(DBG_WMI, (DBGFMT "packet already 802.3\n", DBGARG));
+ return (A_OK);
+ }
+
+ /*
+ * Save mac fields and length to be inserted later
+ */
+ A_MEMCPY(macHdr.dstMac, datap, ATH_MAC_LEN);
+ A_MEMCPY(macHdr.srcMac, datap + ATH_MAC_LEN, ATH_MAC_LEN);
+ macHdr.typeOrLen = A_CPU2BE16(A_NETBUF_LEN(osbuf) - sizeof(ATH_MAC_HDR) +
+ sizeof(ATH_LLC_SNAP_HDR));
+
+ /*
+ * Make room for LLC+SNAP headers
+ */
+ if (A_NETBUF_PUSH(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+ llcHdr->dsap = 0xAA;
+ llcHdr->ssap = 0xAA;
+ llcHdr->cntl = 0x03;
+ llcHdr->orgCode[0] = 0x0;
+ llcHdr->orgCode[1] = 0x0;
+ llcHdr->orgCode[2] = 0x0;
+ llcHdr->etherType = typeorlen;
+
+ return (A_OK);
+}
+
+/*
+ * Adds a WMI data header
+ * Assumes there is enough room in the buffer to add header.
+ */
+A_STATUS
+wmi_data_hdr_add(struct wmi_t *wmip, void *osbuf, A_UINT8 msgType)
+{
+ WMI_DATA_HDR *dtHdr;
+
+ A_ASSERT(osbuf != NULL);
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+ dtHdr->info = msgType;
+ dtHdr->rssi = 0;
+
+ return (A_OK);
+}
+
+A_UINT8 wmi_implicit_create_pstream(struct wmi_t *wmip, void *osbuf, A_UINT8 dir, A_UINT8 up)
+{
+ A_UINT8 *datap;
+ A_UINT8 trafficClass = WMM_AC_BE, userPriority = up;
+ ATH_LLC_SNAP_HDR *llcHdr;
+ A_UINT16 ipType = IP_ETHERTYPE;
+ WMI_DATA_HDR *dtHdr;
+ WMI_CREATE_PSTREAM_CMD cmd;
+ A_BOOL streamExists = FALSE;
+
+ A_ASSERT(osbuf != NULL);
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ if (up == UNDEFINED_PRI) {
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(WMI_DATA_HDR) +
+ sizeof(ATH_MAC_HDR));
+
+ if (llcHdr->etherType == A_CPU2BE16(ipType)) {
+ /* Extract the endpoint info from the TOS field in the IP header */
+ userPriority = A_WMI_IPTOS_TO_USERPRIORITY(((A_UINT8 *)llcHdr) + sizeof(ATH_LLC_SNAP_HDR));
+ }
+ }
+
+ if (userPriority < MAX_NUM_PRI) {
+ trafficClass = convert_userPriority_to_trafficClass(userPriority);
+ }
+
+ dtHdr = (WMI_DATA_HDR *)datap;
+ if(dir==UPLINK_TRAFFIC)
+ dtHdr->info |= (userPriority & WMI_DATA_HDR_UP_MASK) << WMI_DATA_HDR_UP_SHIFT; /* lower 3-bits are 802.1d priority */
+
+ LOCK_WMI(wmip);
+ streamExists = wmip->wmi_fatPipeExists;
+ UNLOCK_WMI(wmip);
+
+ if (!(streamExists & (1 << trafficClass))) {
+
+ A_MEMZERO(&cmd, sizeof(cmd));
+ cmd.trafficClass = trafficClass;
+ cmd.userPriority = userPriority;
+ cmd.inactivityInt = WMI_IMPLICIT_PSTREAM_INACTIVITY_INT;
+ /* Implicit streams are created with TSID 0xFF */
+ cmd.tsid = WMI_IMPLICIT_PSTREAM;
+ wmi_create_pstream_cmd(wmip, &cmd);
+ }
+
+ return trafficClass;
+}
+
+WMI_PRI_STREAM_ID
+wmi_get_stream_id(struct wmi_t *wmip, A_UINT8 trafficClass)
+{
+ return WMI_ACCESSCATEGORY_WMISTREAM(wmip, trafficClass);
+}
+
+/*
+ * performs 802.3 to DIX encapsulation for received packets.
+ * Assumes the entire 802.3 header is contigous.
+ */
+A_STATUS
+wmi_dot3_2_dix(struct wmi_t *wmip, void *osbuf)
+{
+ A_UINT8 *datap;
+ ATH_MAC_HDR macHdr;
+ ATH_LLC_SNAP_HDR *llcHdr;
+
+ A_ASSERT(osbuf != NULL);
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(&macHdr, datap, sizeof(ATH_MAC_HDR));
+ llcHdr = (ATH_LLC_SNAP_HDR *)(datap + sizeof(ATH_MAC_HDR));
+ macHdr.typeOrLen = llcHdr->etherType;
+
+ if (A_NETBUF_PULL(osbuf, sizeof(ATH_LLC_SNAP_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(datap, &macHdr, sizeof (ATH_MAC_HDR));
+
+ return (A_OK);
+}
+
+/*
+ * Removes a WMI data header
+ */
+A_STATUS
+wmi_data_hdr_remove(struct wmi_t *wmip, void *osbuf)
+{
+ A_ASSERT(osbuf != NULL);
+
+ return (A_NETBUF_PULL(osbuf, sizeof(WMI_DATA_HDR)));
+}
+
+void
+wmi_iterate_nodes(struct wmi_t *wmip, wlan_node_iter_func *f, void *arg)
+{
+ wlan_iterate_nodes(&wmip->wmi_scan_table, f, arg);
+}
+
+/*
+ * WMI Extended Event received from Target.
+ */
+A_STATUS
+wmi_control_rx_xtnd(struct wmi_t *wmip, void *osbuf)
+{
+ WMIX_CMD_HDR *cmd;
+ A_UINT16 id;
+ A_UINT8 *datap;
+ A_UINT32 len;
+ A_STATUS status = A_OK;
+
+ if (A_NETBUF_LEN(osbuf) < sizeof(WMIX_CMD_HDR)) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ A_NETBUF_FREE(osbuf);
+ return A_ERROR;
+ }
+
+ cmd = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ id = cmd->commandId;
+
+ if (A_NETBUF_PULL(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ A_NETBUF_FREE(osbuf);
+ return A_ERROR;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+ len = A_NETBUF_LEN(osbuf);
+
+ switch (id) {
+ case (WMIX_DSETOPENREQ_EVENTID):
+ status = wmi_dset_open_req_rx(wmip, datap, len);
+ break;
+#ifdef CONFIG_HOST_DSET_SUPPORT
+ case (WMIX_DSETCLOSE_EVENTID):
+ status = wmi_dset_close_rx(wmip, datap, len);
+ break;
+ case (WMIX_DSETDATAREQ_EVENTID):
+ status = wmi_dset_data_req_rx(wmip, datap, len);
+ break;
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+ case (WMIX_GPIO_INTR_EVENTID):
+ wmi_gpio_intr_rx(wmip, datap, len);
+ break;
+ case (WMIX_GPIO_DATA_EVENTID):
+ wmi_gpio_data_rx(wmip, datap, len);
+ break;
+ case (WMIX_GPIO_ACK_EVENTID):
+ wmi_gpio_ack_rx(wmip, datap, len);
+ break;
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+ case (WMIX_HB_CHALLENGE_RESP_EVENTID):
+ wmi_hbChallengeResp_rx(wmip, datap, len);
+ break;
+ case (WMIX_DBGLOG_EVENTID):
+ wmi_dbglog_event_rx(wmip, datap, len);
+ break;
+ default:
+ A_DPRINTF(DBG_WMI|DBG_ERROR,
+ (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+ wmip->wmi_stats.cmd_id_err++;
+ status = A_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/*
+ * Control Path
+ */
+A_UINT32 cmdRecvNum;
+
+A_STATUS
+wmi_control_rx(struct wmi_t *wmip, void *osbuf)
+{
+ WMI_CMD_HDR *cmd;
+ A_UINT16 id;
+ A_UINT8 *datap;
+ A_UINT32 len, i, loggingReq;
+ A_STATUS status = A_OK;
+
+ A_ASSERT(osbuf != NULL);
+ if (A_NETBUF_LEN(osbuf) < sizeof(WMI_CMD_HDR)) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 1\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ A_NETBUF_FREE(osbuf);
+ return A_ERROR;
+ }
+
+ cmd = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ id = cmd->commandId;
+
+ if (A_NETBUF_PULL(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "bad packet 2\n", DBGARG));
+ wmip->wmi_stats.cmd_len_err++;
+ A_NETBUF_FREE(osbuf);
+ return A_ERROR;
+ }
+
+ datap = A_NETBUF_DATA(osbuf);
+ len = A_NETBUF_LEN(osbuf);
+
+ ar6000_get_driver_cfg(wmip->wmi_devt,
+ AR6000_DRIVER_CFG_LOG_RAW_WMI_MSGS,
+ &loggingReq);
+
+ if(loggingReq) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI %d \n",id));
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("WMI recv, MsgNo %d : ", cmdRecvNum));
+ for(i = 0; i < len; i++)
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("%x ", datap[i]));
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("\n"));
+ }
+
+ LOCK_WMI(wmip);
+ cmdRecvNum++;
+ UNLOCK_WMI(wmip);
+
+ switch (id) {
+ case (WMI_GET_BITRATE_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_BITRATE_CMDID\n", DBGARG));
+ status = wmi_bitrate_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_CHANNEL_LIST_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_CHANNEL_LIST_CMDID\n", DBGARG));
+ status = wmi_channelList_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_TX_PWR_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_TX_PWR_CMDID\n", DBGARG));
+ status = wmi_txPwr_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_READY_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
+ status = wmi_ready_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
+ break;
+ case (WMI_CONNECT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
+ status = wmi_connect_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_DISCONNECT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
+ status = wmi_disconnect_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_TKIP_MICERR_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
+ status = wmi_tkip_micerr_event_rx(wmip, datap, len);
+ break;
+ case (WMI_BSSINFO_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BSSINFO_EVENTID\n", DBGARG));
+ status = wmi_bssInfo_event_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_REGDOMAIN_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REGDOMAIN_EVENTID\n", DBGARG));
+ status = wmi_regDomain_event_rx(wmip, datap, len);
+ break;
+ case (WMI_PSTREAM_TIMEOUT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
+ status = wmi_pstream_timeout_event_rx(wmip, datap, len);
+ /* pstreams are fatpipe abstractions that get implicitly created.
+ * User apps only deal with thinstreams. creation of a thinstream
+ * by the user or data traffic flow in an AC triggers implicit
+ * pstream creation. Do we need to send this event to App..?
+ * no harm in sending it.
+ */
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_NEIGHBOR_REPORT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
+ status = wmi_neighborReport_event_rx(wmip, datap, len);
+ break;
+ case (WMI_SCAN_COMPLETE_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
+ status = wmi_scanComplete_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_CMDERROR_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
+ status = wmi_errorEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_STATISTICS_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_STATISTICS_EVENTID\n", DBGARG));
+ status = wmi_statsEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_RSSI_THRESHOLD_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_RSSI_THRESHOLD_EVENTID\n", DBGARG));
+ status = wmi_rssiThresholdEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_ERROR_REPORT_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
+ status = wmi_reportErrorEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_OPT_RX_FRAME_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
+ status = wmi_opt_frame_event_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_ROAM_TBL_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_TBL_EVENTID\n", DBGARG));
+ status = wmi_roam_tbl_event_rx(wmip, datap, len);
+ break;
+ case (WMI_EXTENSION_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_EXTENSION_EVENTID\n", DBGARG));
+ status = wmi_control_rx_xtnd(wmip, osbuf);
+ break;
+ case (WMI_CAC_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CAC_EVENTID\n", DBGARG));
+ status = wmi_cac_event_rx(wmip, datap, len);
+ break;
+ case (WMI_REPORT_ROAM_DATA_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_REPORT_ROAM_DATA_EVENTID\n", DBGARG));
+ status = wmi_roam_data_event_rx(wmip, datap, len);
+ break;
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+ case (WMI_TEST_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TEST_EVENTID\n", DBGARG));
+ status = wmi_tcmd_test_report_rx(wmip, datap, len);
+ break;
+#endif
+ case (WMI_GET_FIXRATES_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_FIXRATES_CMDID\n", DBGARG));
+ status = wmi_ratemask_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_TX_RETRY_ERR_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
+ status = wmi_txRetryErrEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_SNR_THRESHOLD_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
+ status = wmi_snrThresholdEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_LQ_THRESHOLD_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
+ status = wmi_lqThresholdEvent_rx(wmip, datap, len);
+ A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
+ break;
+ case (WMI_APLIST_EVENTID):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
+ status = wmi_aplistEvent_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_KEEPALIVE_CMDID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_KEEPALIVE_CMDID\n", DBGARG));
+ status = wmi_keepalive_reply_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_WOW_LIST_EVENTID):
+ status = wmi_get_wow_list_event_rx(wmip, datap, len);
+ break;
+ case (WMI_GET_PMKID_LIST_EVENTID):
+ A_DPRINTF(DBG_WMI, (DBGFMT "WMI_GET_PMKID_LIST Event\n", DBGARG));
+ status = wmi_get_pmkid_list_event_rx(wmip, datap, len);
+ break;
+ default:
+ A_DPRINTF(DBG_WMI|DBG_ERROR,
+ (DBGFMT "Unknown id 0x%x\n", DBGARG, id));
+ wmip->wmi_stats.cmd_id_err++;
+ status = A_ERROR;
+ break;
+ }
+
+ A_NETBUF_FREE(osbuf);
+
+ return status;
+}
+
+static A_STATUS
+wmi_ready_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_READY_EVENT *ev = (WMI_READY_EVENT *)datap;
+
+ if (len < sizeof(WMI_READY_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+ wmip->wmi_ready = TRUE;
+ A_WMI_READY_EVENT(wmip->wmi_devt, ev->macaddr, ev->phyCapability);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_connect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CONNECT_EVENT *ev;
+
+ if (len < sizeof(WMI_CONNECT_EVENT)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_CONNECT_EVENT *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "freq %d bssid %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
+ DBGARG, ev->channel,
+ ev->bssid[0], ev->bssid[1], ev->bssid[2],
+ ev->bssid[3], ev->bssid[4], ev->bssid[5]));
+
+ A_MEMCPY(wmip->wmi_bssid, ev->bssid, ATH_MAC_LEN);
+
+ A_WMI_CONNECT_EVENT(wmip->wmi_devt, ev->channel, ev->bssid,
+ ev->listenInterval, ev->beaconInterval,
+ ev->networkType, ev->beaconIeLen,
+ ev->assocReqLen, ev->assocRespLen,
+ ev->assocInfo);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_regDomain_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_REG_DOMAIN_EVENT *ev;
+
+ if (len < sizeof(*ev)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_REG_DOMAIN_EVENT *)datap;
+
+ A_WMI_REGDOMAIN_EVENT(wmip->wmi_devt, ev->regDomain);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_neighborReport_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_NEIGHBOR_REPORT_EVENT *ev;
+ int numAps;
+
+ if (len < sizeof(*ev)) {
+ return A_EINVAL;
+ }
+ ev = (WMI_NEIGHBOR_REPORT_EVENT *)datap;
+ numAps = ev->numberOfAps;
+
+ if (len < (int)(sizeof(*ev) + ((numAps - 1) * sizeof(WMI_NEIGHBOR_INFO)))) {
+ return A_EINVAL;
+ }
+
+ A_WMI_NEIGHBORREPORT_EVENT(wmip->wmi_devt, numAps, ev->neighbor);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_disconnect_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_DISCONNECT_EVENT *ev;
+
+ if (len < sizeof(WMI_DISCONNECT_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ ev = (WMI_DISCONNECT_EVENT *)datap;
+
+ A_MEMZERO(wmip->wmi_bssid, sizeof(wmip->wmi_bssid));
+
+ A_WMI_DISCONNECT_EVENT(wmip->wmi_devt, ev->disconnectReason, ev->bssid,
+ ev->assocRespLen, ev->assocInfo, ev->protocolReasonStatus);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_tkip_micerr_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TKIP_MICERR_EVENT *ev;
+
+ if (len < sizeof(*ev)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ ev = (WMI_TKIP_MICERR_EVENT *)datap;
+ A_WMI_TKIP_MICERR_EVENT(wmip->wmi_devt, ev->keyid, ev->ismcast);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_bssInfo_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ bss_t *bss;
+ WMI_BSS_INFO_HDR *bih;
+ A_UINT8 *buf;
+ A_UINT32 nodeCachingAllowed;
+
+ if (len <= sizeof(WMI_BSS_INFO_HDR)) {
+ return A_EINVAL;
+ }
+
+ A_WMI_BSSINFO_EVENT_RX(wmip->wmi_devt, datap, len);
+ /* What is driver config for wlan node caching? */
+ if(ar6000_get_driver_cfg(wmip->wmi_devt,
+ AR6000_DRIVER_CFG_GET_WLANNODECACHING,
+ &nodeCachingAllowed) != A_OK) {
+ return A_EINVAL;
+ }
+
+ if(!nodeCachingAllowed) {
+ return A_OK;
+ }
+
+
+ bih = (WMI_BSS_INFO_HDR *)datap;
+ buf = datap + sizeof(WMI_BSS_INFO_HDR);
+ len -= sizeof(WMI_BSS_INFO_HDR);
+
+ A_DPRINTF(DBG_WMI2, (DBGFMT "bssInfo event - ch %u, rssi %02x, "
+ "bssid \"%02x:%02x:%02x:%02x:%02x:%02x\"\n", DBGARG,
+ bih->channel, (unsigned char) bih->rssi, bih->bssid[0],
+ bih->bssid[1], bih->bssid[2], bih->bssid[3], bih->bssid[4],
+ bih->bssid[5]));
+
+ if(wps_enable && (bih->frameType == PROBERESP_FTYPE) ) {
+ printk("%s() A_OK 2\n", __FUNCTION__);
+ return A_OK;
+ }
+
+ bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+ if (bss != NULL) {
+ /*
+ * Free up the node. Not the most efficient process given
+ * we are about to allocate a new node but it is simple and should be
+ * adequate.
+ */
+ wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+ }
+
+ bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+ if (bss == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ bss->ni_snr = bih->snr;
+ bss->ni_rssi = bih->rssi;
+ A_ASSERT(bss->ni_buf != NULL);
+ A_MEMCPY(bss->ni_buf, buf, len);
+
+ if (wlan_parse_beacon(bss->ni_buf, len, &bss->ni_cie) != A_OK) {
+ wlan_node_free(bss);
+ return A_EINVAL;
+ }
+
+ /*
+ * Update the frequency in ie_chan, overwriting of channel number
+ * which is done in wlan_parse_beacon
+ */
+ bss->ni_cie.ie_chan = bih->channel;
+ wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_opt_frame_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ bss_t *bss;
+ WMI_OPT_RX_INFO_HDR *bih;
+ A_UINT8 *buf;
+
+ if (len <= sizeof(WMI_OPT_RX_INFO_HDR)) {
+ return A_EINVAL;
+ }
+
+ bih = (WMI_OPT_RX_INFO_HDR *)datap;
+ buf = datap + sizeof(WMI_OPT_RX_INFO_HDR);
+ len -= sizeof(WMI_OPT_RX_INFO_HDR);
+
+ A_DPRINTF(DBG_WMI2, (DBGFMT "opt frame event %2.2x:%2.2x\n", DBGARG,
+ bih->bssid[4], bih->bssid[5]));
+
+ bss = wlan_find_node(&wmip->wmi_scan_table, bih->bssid);
+ if (bss != NULL) {
+ /*
+ * Free up the node. Not the most efficient process given
+ * we are about to allocate a new node but it is simple and should be
+ * adequate.
+ */
+ wlan_node_reclaim(&wmip->wmi_scan_table, bss);
+ }
+
+ bss = wlan_node_alloc(&wmip->wmi_scan_table, len);
+ if (bss == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ bss->ni_snr = bih->snr;
+ bss->ni_cie.ie_chan = bih->channel;
+ A_ASSERT(bss->ni_buf != NULL);
+ A_MEMCPY(bss->ni_buf, buf, len);
+ wlan_setup_node(&wmip->wmi_scan_table, bss, bih->bssid);
+
+ return A_OK;
+}
+
+ /* This event indicates inactivity timeout of a fatpipe(pstream)
+ * at the target
+ */
+static A_STATUS
+wmi_pstream_timeout_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_PSTREAM_TIMEOUT_EVENT *ev;
+
+ if (len < sizeof(WMI_PSTREAM_TIMEOUT_EVENT)) {
+ return A_EINVAL;
+ }
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "wmi_pstream_timeout_event_rx\n", DBGARG));
+
+ ev = (WMI_PSTREAM_TIMEOUT_EVENT *)datap;
+
+ /* When the pstream (fat pipe == AC) timesout, it means there were no
+ * thinStreams within this pstream & it got implicitly created due to
+ * data flow on this AC. We start the inactivity timer only for
+ * implicitly created pstream. Just reset the host state.
+ */
+ /* Set the activeTsids for this AC to 0 */
+ LOCK_WMI(wmip);
+ wmip->wmi_streamExistsForAC[ev->trafficClass]=0;
+ wmip->wmi_fatPipeExists &= ~(1 << ev->trafficClass);
+ UNLOCK_WMI(wmip);
+
+ /*Indicate inactivity to driver layer for this fatpipe (pstream)*/
+ A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, ev->trafficClass);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_bitrate_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_BIT_RATE_CMD *reply;
+ A_INT32 rate;
+
+ if (len < sizeof(WMI_BIT_RATE_CMD)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_BIT_RATE_CMD *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - rateindex %d\n", DBGARG, reply->rateIndex));
+
+ if (reply->rateIndex == RATE_AUTO) {
+ rate = RATE_AUTO;
+ } else {
+ rate = wmi_rateTable[(A_UINT32) reply->rateIndex];
+ }
+
+ A_WMI_BITRATE_RX(wmip->wmi_devt, rate);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_ratemask_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_FIX_RATES_CMD *reply;
+
+ if (len < sizeof(WMI_BIT_RATE_CMD)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_FIX_RATES_CMD *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - fixed rate mask %x\n", DBGARG, reply->fixRateMask));
+
+ A_WMI_RATEMASK_RX(wmip->wmi_devt, reply->fixRateMask);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_channelList_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CHANNEL_LIST_REPLY *reply;
+
+ if (len < sizeof(WMI_CHANNEL_LIST_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_CHANNEL_LIST_REPLY *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_CHANNELLIST_RX(wmip->wmi_devt, reply->numChannels,
+ reply->channelList);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_txPwr_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TX_PWR_REPLY *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TX_PWR_REPLY *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TXPWR_RX(wmip->wmi_devt, reply->dbM);
+
+ return A_OK;
+}
+static A_STATUS
+wmi_keepalive_reply_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_GET_KEEPALIVE_CMD *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_GET_KEEPALIVE_CMD *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_KEEPALIVE_RX(wmip->wmi_devt, reply->configured);
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_dset_open_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_DSETOPENREQ_EVENT *dsetopenreq;
+
+ if (len < sizeof(WMIX_DSETOPENREQ_EVENT)) {
+ return A_EINVAL;
+ }
+ dsetopenreq = (WMIX_DSETOPENREQ_EVENT *)datap;
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - dset_id=0x%x\n", DBGARG, dsetopenreq->dset_id));
+ A_WMI_DSET_OPEN_REQ(wmip->wmi_devt,
+ dsetopenreq->dset_id,
+ dsetopenreq->targ_dset_handle,
+ dsetopenreq->targ_reply_fn,
+ dsetopenreq->targ_reply_arg);
+
+ return A_OK;
+}
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+static A_STATUS
+wmi_dset_close_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_DSETCLOSE_EVENT *dsetclose;
+
+ if (len < sizeof(WMIX_DSETCLOSE_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ dsetclose = (WMIX_DSETCLOSE_EVENT *)datap;
+ A_WMI_DSET_CLOSE(wmip->wmi_devt, dsetclose->access_cookie);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_dset_data_req_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_DSETDATAREQ_EVENT *dsetdatareq;
+
+ if (len < sizeof(WMIX_DSETDATAREQ_EVENT)) {
+ return A_EINVAL;
+ }
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ dsetdatareq = (WMIX_DSETDATAREQ_EVENT *)datap;
+ A_WMI_DSET_DATA_REQ(wmip->wmi_devt,
+ dsetdatareq->access_cookie,
+ dsetdatareq->offset,
+ dsetdatareq->length,
+ dsetdatareq->targ_buf,
+ dsetdatareq->targ_reply_fn,
+ dsetdatareq->targ_reply_arg);
+
+ return A_OK;
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+static A_STATUS
+wmi_scanComplete_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_SCAN_COMPLETE_EVENT *ev;
+
+ ev = (WMI_SCAN_COMPLETE_EVENT *)datap;
+ A_WMI_SCANCOMPLETE_EVENT(wmip->wmi_devt, ev->status);
+
+ return A_OK;
+}
+
+/*
+ * Target is reporting a programming error. This is for
+ * developer aid only. Target only checks a few common violations
+ * and it is responsibility of host to do all error checking.
+ * Behavior of target after wmi error event is undefined.
+ * A reset is recommended.
+ */
+static A_STATUS
+wmi_errorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CMD_ERROR_EVENT *ev;
+
+ ev = (WMI_CMD_ERROR_EVENT *)datap;
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Programming Error: cmd=%d ", ev->commandId));
+ switch (ev->errorCode) {
+ case (INVALID_PARAM):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal Parameter\n"));
+ break;
+ case (ILLEGAL_STATE):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Illegal State\n"));
+ break;
+ case (INTERNAL_ERROR):
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Internal Error\n"));
+ break;
+ }
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_statsEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_STATS *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_STATS *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TARGETSTATS_EVENT(wmip->wmi_devt, reply);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_rssiThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_RSSI_THRESHOLD_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_RSSI_THRESHOLD_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_RSSI_THRESHOLD_EVENT(wmip->wmi_devt, reply->range, reply->rssi);
+
+ return A_OK;
+}
+
+
+static A_STATUS
+wmi_reportErrorEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_ERROR_REPORT_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_ERROR_REPORT_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_REPORT_ERROR_EVENT(wmip->wmi_devt, reply->errorVal);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_cac_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_CAC_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_CAC_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_CAC_EVENT(wmip->wmi_devt, reply->ac,
+ reply->cac_indication, reply->statusCode,
+ reply->tspecSuggestion);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_hbChallengeResp_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_HB_CHALLENGE_RESP_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMIX_HB_CHALLENGE_RESP_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "wmi: challenge response event\n", DBGARG));
+
+ A_WMI_HBCHALLENGERESP_EVENT(wmip->wmi_devt, reply->cookie, reply->source);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_roam_tbl_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_ROAM_TBL *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_ROAM_TBL *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_ROAM_TABLE_EVENT(wmip->wmi_devt, reply);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_roam_data_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TARGET_ROAM_DATA *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TARGET_ROAM_DATA *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_ROAM_DATA_EVENT(wmip->wmi_devt, reply);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_txRetryErrEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_TX_RETRY_ERR_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_TX_RETRY_ERR_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TX_RETRY_ERR_EVENT(wmip->wmi_devt);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_snrThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_SNR_THRESHOLD_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_SNR_THRESHOLD_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_SNR_THRESHOLD_EVENT_RX(wmip->wmi_devt, reply->range, reply->snr);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_lqThresholdEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_LQ_THRESHOLD_EVENT *reply;
+
+ if (len < sizeof(*reply)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_LQ_THRESHOLD_EVENT *)datap;
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_LQ_THRESHOLD_EVENT_RX(wmip->wmi_devt, reply->range, reply->lq);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_aplistEvent_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_UINT16 ap_info_entry_size;
+ WMI_APLIST_EVENT *ev = (WMI_APLIST_EVENT *)datap;
+ WMI_AP_INFO_V1 *ap_info_v1;
+ A_UINT8 i;
+
+ if (len < sizeof(WMI_APLIST_EVENT)) {
+ return A_EINVAL;
+ }
+
+ if (ev->apListVer == APLIST_VER1) {
+ ap_info_entry_size = sizeof(WMI_AP_INFO_V1);
+ ap_info_v1 = (WMI_AP_INFO_V1 *)ev->apList;
+ } else {
+ return A_EINVAL;
+ }
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Number of APs in APLIST Event is %d\n", ev->numAP));
+ if (len < (int)(sizeof(WMI_APLIST_EVENT) +
+ (ev->numAP - 1) * ap_info_entry_size))
+ {
+ return A_EINVAL;
+ }
+
+ /*
+ * AP List Ver1 Contents
+ */
+ for (i = 0; i < ev->numAP; i++) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("AP#%d BSSID %2.2x %2.2x %2.2x %2.2x %2.2x %2.2x "\
+ "Channel %d\n", i,
+ ap_info_v1->bssid[0], ap_info_v1->bssid[1],
+ ap_info_v1->bssid[2], ap_info_v1->bssid[3],
+ ap_info_v1->bssid[4], ap_info_v1->bssid[5],
+ ap_info_v1->channel));
+ ap_info_v1++;
+ }
+ return A_OK;
+}
+
+static A_STATUS
+wmi_dbglog_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_UINT32 dropped;
+
+ dropped = *((A_UINT32 *)datap);
+ datap += sizeof(dropped);
+ len -= sizeof(dropped);
+ A_WMI_DBGLOG_EVENT(wmip->wmi_devt, dropped, datap, len);
+ return A_OK;
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+static A_STATUS
+wmi_gpio_intr_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
+ gpio_intr->intr_mask, gpio_intr->input_values));
+
+ A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_data_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
+ gpio_data->reg_id, gpio_data->value));
+
+ A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
+
+ return A_OK;
+}
+
+static A_STATUS
+wmi_gpio_ack_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_GPIO_ACK_RX();
+
+ return A_OK;
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+/*
+ * Called to send a wmi command. Command specific data is already built
+ * on osbuf and current osbuf->data points to it.
+ */
+A_STATUS
+wmi_cmd_send(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG syncflag)
+{
+#define IS_LONG_CMD(cmdId) ((cmdId == WMI_OPT_TX_FRAME_CMDID) || (cmdId == WMI_ADD_WOW_PATTERN_CMDID))
+ WMI_CMD_HDR *cHdr;
+ WMI_PRI_STREAM_ID streamID = WMI_CONTROL_PRI;
+
+ A_ASSERT(osbuf != NULL);
+
+ if (syncflag >= END_WMIFLAG) {
+ return A_EINVAL;
+ }
+
+ if ((syncflag == SYNC_BEFORE_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+ /*
+ * We want to make sure all data currently queued is transmitted before
+ * the cmd execution. Establish a new sync point.
+ */
+ wmi_sync_point(wmip);
+ }
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMI_CMD_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ cHdr = (WMI_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ cHdr->commandId = cmdId;
+
+ /*
+ * Send cmd, some via control pipe, others via data pipe
+ */
+ if (IS_LONG_CMD(cmdId)) {
+ wmi_data_hdr_add(wmip, osbuf, CNTL_MSGTYPE);
+ // TODO ... these can now go through the control endpoint via HTC 2.0
+ streamID = WMI_BEST_EFFORT_PRI;
+ }
+ A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, streamID);
+
+ if ((syncflag == SYNC_AFTER_WMIFLAG) || (syncflag == SYNC_BOTH_WMIFLAG)) {
+ /*
+ * We want to make sure all new data queued waits for the command to
+ * execute. Establish a new sync point.
+ */
+ wmi_sync_point(wmip);
+ }
+ return (A_OK);
+#undef IS_LONG_CMD
+}
+
+A_STATUS
+wmi_cmd_send_xtnd(struct wmi_t *wmip, void *osbuf, WMI_COMMAND_ID cmdId,
+ WMI_SYNC_FLAG syncflag)
+{
+ WMIX_CMD_HDR *cHdr;
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMIX_CMD_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ cHdr = (WMIX_CMD_HDR *)A_NETBUF_DATA(osbuf);
+ cHdr->commandId = cmdId;
+
+ return wmi_cmd_send(wmip, osbuf, WMI_EXTENSION_CMDID, syncflag);
+}
+
+A_STATUS
+wmi_connect_cmd(struct wmi_t *wmip, NETWORK_TYPE netType,
+ DOT11_AUTH_MODE dot11AuthMode, AUTH_MODE authMode,
+ CRYPTO_TYPE pairwiseCrypto, A_UINT8 pairwiseCryptoLen,
+ CRYPTO_TYPE groupCrypto,A_UINT8 groupCryptoLen,
+ int ssidLength, A_UCHAR *ssid,
+ A_UINT8 *bssid, A_UINT16 channel, A_UINT32 ctrl_flags)
+{
+ void *osbuf;
+ WMI_CONNECT_CMD *cc;
+
+ if ((pairwiseCrypto == NONE_CRYPT) && (groupCrypto != NONE_CRYPT)) {
+ return A_EINVAL;
+ }
+ if ((pairwiseCrypto != NONE_CRYPT) && (groupCrypto == NONE_CRYPT)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_CONNECT_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_CONNECT_CMD));
+
+ cc = (WMI_CONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cc, sizeof(*cc));
+
+ A_MEMCPY(cc->ssid, ssid, ssidLength);
+ cc->ssidLength = ssidLength;
+ cc->networkType = netType;
+ cc->dot11AuthMode = dot11AuthMode;
+ cc->authMode = authMode;
+ cc->pairwiseCryptoType = pairwiseCrypto;
+ cc->pairwiseCryptoLen = pairwiseCryptoLen;
+ cc->groupCryptoType = groupCrypto;
+ cc->groupCryptoLen = groupCryptoLen;
+ cc->channel = channel;
+ cc->ctrl_flags = ctrl_flags;
+
+ if (bssid != NULL) {
+ A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+ }
+ if (wmi_set_keepalive_cmd(wmip, wmip->wmi_keepaliveInterval) != A_OK) {
+ return(A_ERROR);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_CONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_reconnect_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT16 channel)
+{
+ void *osbuf;
+ WMI_RECONNECT_CMD *cc;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(WMI_RECONNECT_CMD));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(WMI_RECONNECT_CMD));
+
+ cc = (WMI_RECONNECT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cc, sizeof(*cc));
+
+ cc->channel = channel;
+
+ if (bssid != NULL) {
+ A_MEMCPY(cc->bssid, bssid, ATH_MAC_LEN);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_RECONNECT_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disconnect_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+ A_STATUS status;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ /* Bug fix for 24817(elevator bug) - the disconnect command does not
+ need to do a SYNC before.*/
+ status = (wmi_cmd_send(wmip, osbuf, WMI_DISCONNECT_CMDID,
+ NO_SYNC_WMIFLAG));
+
+ return status;
+}
+
+A_STATUS
+wmi_startscan_cmd(struct wmi_t *wmip, WMI_SCAN_TYPE scanType,
+ A_BOOL forceFgScan, A_BOOL isLegacy,
+ A_UINT32 homeDwellTime, A_UINT32 forceScanInterval)
+{
+ void *osbuf;
+ WMI_START_SCAN_CMD *sc;
+
+ if ((scanType != WMI_LONG_SCAN) && (scanType != WMI_SHORT_SCAN)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*sc));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*sc));
+
+ sc = (WMI_START_SCAN_CMD *)(A_NETBUF_DATA(osbuf));
+ sc->scanType = scanType;
+ sc->forceFgScan = forceFgScan;
+ sc->isLegacy = isLegacy;
+ sc->homeDwellTime = homeDwellTime;
+ sc->forceScanInterval = forceScanInterval;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_START_SCAN_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_scanparams_cmd(struct wmi_t *wmip, A_UINT16 fg_start_sec,
+ A_UINT16 fg_end_sec, A_UINT16 bg_sec,
+ A_UINT16 minact_chdw_msec, A_UINT16 maxact_chdw_msec,
+ A_UINT16 pas_chdw_msec,
+ A_UINT8 shScanRatio, A_UINT8 scanCtrlFlags,
+ A_UINT32 max_dfsch_act_time)
+{
+ void *osbuf;
+ WMI_SCAN_PARAMS_CMD *sc;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*sc));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*sc));
+
+ sc = (WMI_SCAN_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(sc, sizeof(*sc));
+ sc->fg_start_period = fg_start_sec;
+ sc->fg_end_period = fg_end_sec;
+ sc->bg_period = bg_sec;
+ sc->minact_chdwell_time = minact_chdw_msec;
+ sc->maxact_chdwell_time = maxact_chdw_msec;
+ sc->pas_chdwell_time = pas_chdw_msec;
+ sc->shortScanRatio = shScanRatio;
+ sc->scanCtrlFlags = scanCtrlFlags;
+ sc->max_dfsch_act_time = max_dfsch_act_time;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_SCAN_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bssfilter_cmd(struct wmi_t *wmip, A_UINT8 filter, A_UINT32 ieMask)
+{
+ void *osbuf;
+ WMI_BSS_FILTER_CMD *cmd;
+
+ if (filter >= LAST_BSS_FILTER) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BSS_FILTER_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->bssFilter = filter;
+ cmd->ieMask = ieMask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BSS_FILTER_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_probedSsid_cmd(struct wmi_t *wmip, A_UINT8 index, A_UINT8 flag,
+ A_UINT8 ssidLength, A_UCHAR *ssid)
+{
+ void *osbuf;
+ WMI_PROBED_SSID_CMD *cmd;
+
+ if (index > MAX_PROBED_SSID_INDEX) {
+ return A_EINVAL;
+ }
+ if (ssidLength > sizeof(cmd->ssid)) {
+ return A_EINVAL;
+ }
+ if ((flag & (DISABLE_SSID_FLAG | ANY_SSID_FLAG)) && (ssidLength > 0)) {
+ return A_EINVAL;
+ }
+ if ((flag & SPECIFIC_SSID_FLAG) && !ssidLength) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_PROBED_SSID_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->entryIndex = index;
+ cmd->flag = flag;
+ cmd->ssidLength = ssidLength;
+ A_MEMCPY(cmd->ssid, ssid, ssidLength);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PROBED_SSID_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_listeninterval_cmd(struct wmi_t *wmip, A_UINT16 listenInterval, A_UINT16 listenBeacons)
+{
+ void *osbuf;
+ WMI_LISTEN_INT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_LISTEN_INT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->listenInterval = listenInterval;
+ cmd->numBeacons = listenBeacons;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_LISTEN_INT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_bmisstime_cmd(struct wmi_t *wmip, A_UINT16 bmissTime, A_UINT16 bmissBeacons)
+{
+ void *osbuf;
+ WMI_BMISS_TIME_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BMISS_TIME_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->bmissTime = bmissTime;
+ cmd->numBeacons = bmissBeacons;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BMISS_TIME_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_associnfo_cmd(struct wmi_t *wmip, A_UINT8 ieType,
+ A_UINT8 ieLen, A_UINT8 *ieInfo)
+{
+ void *osbuf;
+ WMI_SET_ASSOC_INFO_CMD *cmd;
+ A_UINT16 cmdLen;
+
+ cmdLen = sizeof(*cmd) + ieLen - 1;
+ osbuf = A_NETBUF_ALLOC(cmdLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, cmdLen);
+
+ cmd = (WMI_SET_ASSOC_INFO_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, cmdLen);
+ cmd->ieType = ieType;
+ cmd->bufferSize = ieLen;
+ A_MEMCPY(cmd->assocInfo, ieInfo, ieLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ASSOC_INFO_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_powermode_cmd(struct wmi_t *wmip, A_UINT8 powerMode)
+{
+ void *osbuf;
+ WMI_POWER_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_POWER_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->powerMode = powerMode;
+ wmip->wmi_powerMode = powerMode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_ibsspmcaps_cmd(struct wmi_t *wmip, A_UINT8 pmEnable, A_UINT8 ttl,
+ A_UINT16 atim_windows, A_UINT16 timeout_value)
+{
+ void *osbuf;
+ WMI_IBSS_PM_CAPS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_IBSS_PM_CAPS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->power_saving = pmEnable;
+ cmd->ttl = ttl;
+ cmd->atim_windows = atim_windows;
+ cmd->timeout_value = timeout_value;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_IBSS_PM_CAPS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_pmparams_cmd(struct wmi_t *wmip, A_UINT16 idlePeriod,
+ A_UINT16 psPollNum, A_UINT16 dtimPolicy)
+{
+ void *osbuf;
+ WMI_POWER_PARAMS_CMD *pm;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*pm));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*pm));
+
+ pm = (WMI_POWER_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(pm, sizeof(*pm));
+ pm->idle_period = idlePeriod;
+ pm->pspoll_number = psPollNum;
+ pm->dtim_policy = dtimPolicy;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWER_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_disctimeout_cmd(struct wmi_t *wmip, A_UINT8 timeout)
+{
+ void *osbuf;
+ WMI_DISC_TIMEOUT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DISC_TIMEOUT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->disconnectTimeout = timeout;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_DISC_TIMEOUT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_addKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex, CRYPTO_TYPE keyType,
+ A_UINT8 keyUsage, A_UINT8 keyLength, A_UINT8 *keyRSC,
+ A_UINT8 *keyMaterial, A_UINT8 key_op_ctrl,
+ WMI_SYNC_FLAG sync_flag)
+{
+ void *osbuf;
+ WMI_ADD_CIPHER_KEY_CMD *cmd;
+
+ if ((keyIndex > WMI_MAX_KEY_INDEX) || (keyLength > WMI_MAX_KEY_LEN) ||
+ (keyMaterial == NULL))
+ {
+ return A_EINVAL;
+ }
+
+ if ((WEP_CRYPT != keyType) && (NULL == keyRSC)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADD_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->keyIndex = keyIndex;
+ cmd->keyType = keyType;
+ cmd->keyUsage = keyUsage;
+ cmd->keyLength = keyLength;
+ A_MEMCPY(cmd->key, keyMaterial, keyLength);
+ if (NULL != keyRSC) {
+ A_MEMCPY(cmd->keyRSC, keyRSC, sizeof(cmd->keyRSC));
+ }
+ cmd->key_op_ctrl = key_op_ctrl;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_CIPHER_KEY_CMDID, sync_flag));
+}
+
+A_STATUS
+wmi_add_krk_cmd(struct wmi_t *wmip, A_UINT8 *krk)
+{
+ void *osbuf;
+ WMI_ADD_KRK_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADD_KRK_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ A_MEMCPY(cmd->krk, krk, WMI_KRK_LEN);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_KRK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_krk_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0);
+
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_KRK_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_deleteKey_cmd(struct wmi_t *wmip, A_UINT8 keyIndex)
+{
+ void *osbuf;
+ WMI_DELETE_CIPHER_KEY_CMD *cmd;
+
+ if (keyIndex > WMI_MAX_KEY_INDEX) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELETE_CIPHER_KEY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->keyIndex = keyIndex;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_CIPHER_KEY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_setPmkid_cmd(struct wmi_t *wmip, A_UINT8 *bssid, A_UINT8 *pmkId,
+ A_BOOL set)
+{
+ void *osbuf;
+ WMI_SET_PMKID_CMD *cmd;
+
+ if (bssid == NULL) {
+ return A_EINVAL;
+ }
+
+ if ((set == TRUE) && (pmkId == NULL)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_PMKID_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+ if (set == TRUE) {
+ A_MEMCPY(cmd->pmkid, pmkId, sizeof(cmd->pmkid));
+ cmd->enable = PMKID_ENABLE;
+ } else {
+ A_MEMZERO(cmd->pmkid, sizeof(cmd->pmkid));
+ cmd->enable = PMKID_DISABLE;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_tkip_countermeasures_cmd(struct wmi_t *wmip, A_BOOL en)
+{
+ void *osbuf;
+ WMI_SET_TKIP_COUNTERMEASURES_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_TKIP_COUNTERMEASURES_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->cm_en = (en == TRUE)? WMI_TKIP_CM_ENABLE : WMI_TKIP_CM_DISABLE;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TKIP_COUNTERMEASURES_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_akmp_params_cmd(struct wmi_t *wmip,
+ WMI_SET_AKMP_PARAMS_CMD *akmpParams)
+{
+ void *osbuf;
+ WMI_SET_AKMP_PARAMS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ cmd = (WMI_SET_AKMP_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->akmpInfo = akmpParams->akmpInfo;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_AKMP_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_pmkid_list_cmd(struct wmi_t *wmip,
+ WMI_SET_PMKID_LIST_CMD *pmkInfo)
+{
+ void *osbuf;
+ WMI_SET_PMKID_LIST_CMD *cmd;
+ A_UINT16 cmdLen;
+ A_UINT8 i;
+
+ cmdLen = sizeof(pmkInfo->numPMKID) +
+ pmkInfo->numPMKID * sizeof(WMI_PMKID);
+
+ osbuf = A_NETBUF_ALLOC(cmdLen);
+
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, cmdLen);
+ cmd = (WMI_SET_PMKID_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->numPMKID = pmkInfo->numPMKID;
+
+ for (i = 0; i < cmd->numPMKID; i++) {
+ A_MEMCPY(&cmd->pmkidList[i], &pmkInfo->pmkidList[i],
+ WMI_PMKID_LEN);
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_PMKID_LIST_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_pmkid_list_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_PMKID_LIST_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_dataSync_send(struct wmi_t *wmip, void *osbuf, WMI_PRI_STREAM_ID streamID)
+{
+ WMI_DATA_HDR *dtHdr;
+
+ A_ASSERT(streamID != WMI_CONTROL_PRI);
+ A_ASSERT(osbuf != NULL);
+
+ if (A_NETBUF_PUSH(osbuf, sizeof(WMI_DATA_HDR)) != A_OK) {
+ return A_NO_MEMORY;
+ }
+
+ dtHdr = (WMI_DATA_HDR *)A_NETBUF_DATA(osbuf);
+ dtHdr->info =
+ (SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter - streamID %d\n", DBGARG, streamID));
+
+ return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, streamID));
+}
+
+typedef struct _WMI_DATA_SYNC_BUFS {
+ A_UINT8 trafficClass;
+ void *osbuf;
+}WMI_DATA_SYNC_BUFS;
+
+static A_STATUS
+wmi_sync_point(struct wmi_t *wmip)
+{
+ void *cmd_osbuf;
+ WMI_DATA_SYNC_BUFS dataSyncBufs[WMM_NUM_AC];
+ A_UINT8 i,numPriStreams=0;
+ A_STATUS status;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ memset(dataSyncBufs,0,sizeof(dataSyncBufs));
+
+ /* lock out while we walk through the priority list and assemble our local array */
+ LOCK_WMI(wmip);
+
+ for (i=0; i < WMM_NUM_AC ; i++) {
+ if (wmip->wmi_fatPipeExists & (1 << i)) {
+ numPriStreams++;
+ dataSyncBufs[numPriStreams-1].trafficClass = i;
+ }
+ }
+
+ UNLOCK_WMI(wmip);
+
+ /* dataSyncBufs is now filled with entries (starting at index 0) containing valid streamIDs */
+
+ do {
+ /*
+ * We allocate all network buffers needed so we will be able to
+ * send all required frames.
+ */
+ cmd_osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (cmd_osbuf == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+
+ for (i=0; i < numPriStreams ; i++) {
+ dataSyncBufs[i].osbuf = A_NETBUF_ALLOC(0);
+ if (dataSyncBufs[i].osbuf == NULL) {
+ status = A_NO_MEMORY;
+ break;
+ }
+ } //end for
+
+ /*
+ * Send sync cmd followed by sync data messages on all endpoints being
+ * used
+ */
+ status = wmi_cmd_send(wmip, cmd_osbuf, WMI_SYNCHRONIZE_CMDID,
+ NO_SYNC_WMIFLAG);
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* cmd buffer sent, we no longer own it */
+ cmd_osbuf = NULL;
+
+ for(i=0; i < numPriStreams; i++) {
+ A_ASSERT(dataSyncBufs[i].osbuf != NULL);
+
+ status = wmi_dataSync_send(wmip, dataSyncBufs[i].osbuf,
+ WMI_ACCESSCATEGORY_WMISTREAM(wmip,dataSyncBufs[i].trafficClass));
+
+ if (A_FAILED(status)) {
+ break;
+ }
+ /* we don't own this buffer anymore, NULL it out of the array so it
+ * won't get cleaned up */
+ dataSyncBufs[i].osbuf = NULL;
+ } //end for
+
+ } while(FALSE);
+
+ /* free up any resources left over (possibly due to an error) */
+
+ if (cmd_osbuf != NULL) {
+ A_NETBUF_FREE(cmd_osbuf);
+ }
+
+ for (i = 0; i < numPriStreams; i++) {
+ if (dataSyncBufs[i].osbuf != NULL) {
+ A_NETBUF_FREE(dataSyncBufs[i].osbuf);
+ }
+ }
+
+ return (status);
+}
+
+A_STATUS
+wmi_create_pstream_cmd(struct wmi_t *wmip, WMI_CREATE_PSTREAM_CMD *params)
+{
+ void *osbuf;
+ WMI_CREATE_PSTREAM_CMD *cmd;
+ A_UINT16 activeTsids=0;
+ A_UINT8 fatPipeExistsForAC=0;
+
+ /* Validate all the parameters. */
+ if( !((params->userPriority < 8) &&
+ (params->userPriority <= 0x7) &&
+ (convert_userPriority_to_trafficClass(params->userPriority) == params->trafficClass) &&
+ (params->trafficDirection == UPLINK_TRAFFIC ||
+ params->trafficDirection == DNLINK_TRAFFIC ||
+ params->trafficDirection == BIDIR_TRAFFIC) &&
+ (params->trafficType == TRAFFIC_TYPE_APERIODIC ||
+ params->trafficType == TRAFFIC_TYPE_PERIODIC ) &&
+ (params->voicePSCapability == DISABLE_FOR_THIS_AC ||
+ params->voicePSCapability == ENABLE_FOR_THIS_AC ||
+ params->voicePSCapability == ENABLE_FOR_ALL_AC) &&
+ (params->tsid == WMI_IMPLICIT_PSTREAM || params->tsid <= WMI_MAX_THINSTREAM)) )
+ {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Sending create_pstream_cmd: ac=%d tsid:%d\n", DBGARG,
+ params->trafficClass, params->tsid));
+
+ cmd = (WMI_CREATE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ A_MEMCPY(cmd, params, sizeof(*cmd));
+
+ /* this is an implicitly created Fat pipe */
+ if (params->tsid == WMI_IMPLICIT_PSTREAM) {
+ LOCK_WMI(wmip);
+ fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+ wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+ UNLOCK_WMI(wmip);
+ } else {
+ /* this is an explicitly created thin stream within a fat pipe */
+ LOCK_WMI(wmip);
+ fatPipeExistsForAC = (wmip->wmi_fatPipeExists & (1 << params->trafficClass));
+ activeTsids = wmip->wmi_streamExistsForAC[params->trafficClass];
+ wmip->wmi_streamExistsForAC[params->trafficClass] |= (1<<params->tsid);
+ /* if a thinstream becomes active, the fat pipe automatically
+ * becomes active
+ */
+ wmip->wmi_fatPipeExists |= (1<<params->trafficClass);
+ UNLOCK_WMI(wmip);
+ }
+
+ /* Indicate activty change to driver layer only if this is the
+ * first TSID to get created in this AC explicitly or an implicit
+ * fat pipe is getting created.
+ */
+ if (!fatPipeExistsForAC) {
+ A_WMI_STREAM_TX_ACTIVE(wmip->wmi_devt, params->trafficClass);
+ }
+
+ /* mike: should be SYNC_BEFORE_WMIFLAG */
+ return (wmi_cmd_send(wmip, osbuf, WMI_CREATE_PSTREAM_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_delete_pstream_cmd(struct wmi_t *wmip, A_UINT8 trafficClass, A_UINT8 tsid)
+{
+ void *osbuf;
+ WMI_DELETE_PSTREAM_CMD *cmd;
+ A_STATUS status;
+ A_UINT16 activeTsids=0;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELETE_PSTREAM_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->trafficClass = trafficClass;
+ cmd->tsid = tsid;
+
+ LOCK_WMI(wmip);
+ activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+ UNLOCK_WMI(wmip);
+
+ /* Check if the tsid was created & exists */
+ if (!(activeTsids & (1<<tsid))) {
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "TSID %d does'nt exist for trafficClass: %d\n", DBGARG, tsid, trafficClass));
+ /* TODO: return a more appropriate err code */
+ return A_ERROR;
+ }
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Sending delete_pstream_cmd: trafficClass: %d tsid=%d\n", DBGARG, trafficClass, tsid));
+
+ status = (wmi_cmd_send(wmip, osbuf, WMI_DELETE_PSTREAM_CMDID,
+ SYNC_BEFORE_WMIFLAG));
+
+ LOCK_WMI(wmip);
+ wmip->wmi_streamExistsForAC[trafficClass] &= ~(1<<tsid);
+ activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+ UNLOCK_WMI(wmip);
+
+
+ /* Indicate stream inactivity to driver layer only if all tsids
+ * within this AC are deleted.
+ */
+ if(!activeTsids) {
+ A_WMI_STREAM_TX_INACTIVE(wmip->wmi_devt, trafficClass);
+ wmip->wmi_fatPipeExists &= ~(1<<trafficClass);
+ }
+
+ return status;
+}
+
+/*
+ * used to set the bit rate. rate is in Kbps. If rate == -1
+ * then auto selection is used.
+ */
+A_STATUS
+wmi_set_bitrate_cmd(struct wmi_t *wmip, A_INT32 rate)
+{
+ void *osbuf;
+ WMI_BIT_RATE_CMD *cmd;
+ A_INT8 index;
+
+ if (rate != -1) {
+ index = wmi_validate_bitrate(wmip, rate);
+ if(index == A_EINVAL){
+ return A_EINVAL;
+ }
+ } else {
+ index = -1;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BIT_RATE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->rateIndex = index;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_bitrate_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_BITRATE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+/*
+ * Returns TRUE iff the given rate index is legal in the current PHY mode.
+ */
+A_BOOL
+wmi_is_bitrate_index_valid(struct wmi_t *wmip, A_UINT32 rateIndex)
+{
+ WMI_PHY_MODE phyMode = wmip->wmi_phyMode;
+ A_BOOL isValid = TRUE;
+ switch(phyMode) {
+ case WMI_11A_MODE:
+ if ((rateIndex < MODE_A_SUPPORT_RATE_START) || (rateIndex > MODE_A_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ case WMI_11B_MODE:
+ if ((rateIndex < MODE_B_SUPPORT_RATE_START) || (rateIndex > MODE_B_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ case WMI_11GONLY_MODE:
+ if ((rateIndex < MODE_GONLY_SUPPORT_RATE_START) || (rateIndex > MODE_GONLY_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ case WMI_11G_MODE:
+ case WMI_11AG_MODE:
+ if ((rateIndex < MODE_G_SUPPORT_RATE_START) || (rateIndex > MODE_G_SUPPORT_RATE_STOP)) {
+ isValid = FALSE;
+ }
+ break;
+
+ default:
+ A_ASSERT(FALSE);
+ break;
+ }
+
+ return isValid;
+}
+
+A_INT8
+wmi_validate_bitrate(struct wmi_t *wmip, A_INT32 rate)
+{
+ A_INT8 i;
+ if (rate != -1)
+ {
+ for (i=0;;i++)
+ {
+ if (wmi_rateTable[(A_UINT32) i] == 0) {
+ return A_EINVAL;
+ }
+ if (wmi_rateTable[(A_UINT32) i] == rate) {
+ break;
+ }
+ }
+ }
+ else{
+ i = -1;
+ }
+
+ if(wmi_is_bitrate_index_valid(wmip, i) != TRUE) {
+ return A_EINVAL;
+ }
+
+ return i;
+}
+
+A_STATUS
+wmi_set_fixrates_cmd(struct wmi_t *wmip, A_INT16 fixRatesMask)
+{
+ void *osbuf;
+ WMI_FIX_RATES_CMD *cmd;
+ A_UINT32 rateIndex;
+
+ /* Make sure all rates in the mask are valid in the current PHY mode */
+ for(rateIndex = 0; rateIndex < MAX_NUMBER_OF_SUPPORT_RATES; rateIndex++) {
+ if((1 << rateIndex) & (A_UINT32)fixRatesMask) {
+ if(wmi_is_bitrate_index_valid(wmip, rateIndex) != TRUE) {
+ A_DPRINTF(DBG_WMI, (DBGFMT "Set Fix Rates command failed: Given rate is illegal in current PHY mode\n", DBGARG));
+ return A_EINVAL;
+ }
+ }
+ }
+
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_FIX_RATES_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+
+ cmd->fixRateMask = fixRatesMask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_ratemask_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_FIXRATES_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_channelList_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_CHANNEL_LIST_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/*
+ * used to generate a wmi sey channel Parameters cmd.
+ * mode should always be specified and corresponds to the phy mode of the
+ * wlan.
+ * numChan should alway sbe specified. If zero indicates that all available
+ * channels should be used.
+ * channelList is an array of channel frequencies (in Mhz) which the radio
+ * should limit its operation to. It should be NULL if numChan == 0. Size of
+ * array should correspond to numChan entries.
+ */
+A_STATUS
+wmi_set_channelParams_cmd(struct wmi_t *wmip, A_UINT8 scanParam,
+ WMI_PHY_MODE mode, A_INT8 numChan,
+ A_UINT16 *channelList)
+{
+ void *osbuf;
+ WMI_CHANNEL_PARAMS_CMD *cmd;
+ A_INT8 size;
+
+ size = sizeof (*cmd);
+
+ if (numChan) {
+ if (numChan > WMI_MAX_CHANNELS) {
+ return A_EINVAL;
+ }
+ size += sizeof(A_UINT16) * (numChan - 1);
+ }
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_CHANNEL_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ wmip->wmi_phyMode = mode;
+ cmd->scanParam = scanParam;
+ cmd->phyMode = mode;
+ cmd->numChannels = numChan;
+ A_MEMCPY(cmd->channelList, channelList, numChan * sizeof(A_UINT16));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_CHANNEL_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_rssi_threshold_params(struct wmi_t *wmip,
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *rssiCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_RSSI_THRESHOLD_PARAMS_CMD *cmd;
+ /* These values are in ascending order */
+ if( rssiCmd->thresholdAbove6_Val <= rssiCmd->thresholdAbove5_Val ||
+ rssiCmd->thresholdAbove5_Val <= rssiCmd->thresholdAbove4_Val ||
+ rssiCmd->thresholdAbove4_Val <= rssiCmd->thresholdAbove3_Val ||
+ rssiCmd->thresholdAbove3_Val <= rssiCmd->thresholdAbove2_Val ||
+ rssiCmd->thresholdAbove2_Val <= rssiCmd->thresholdAbove1_Val ||
+ rssiCmd->thresholdBelow6_Val <= rssiCmd->thresholdBelow5_Val ||
+ rssiCmd->thresholdBelow5_Val <= rssiCmd->thresholdBelow4_Val ||
+ rssiCmd->thresholdBelow4_Val <= rssiCmd->thresholdBelow3_Val ||
+ rssiCmd->thresholdBelow3_Val <= rssiCmd->thresholdBelow2_Val ||
+ rssiCmd->thresholdBelow2_Val <= rssiCmd->thresholdBelow1_Val) {
+
+ return A_EINVAL;
+ }
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_RSSI_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, rssiCmd, sizeof(WMI_RSSI_THRESHOLD_PARAMS_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_RSSI_THRESHOLD_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_host_sleep_mode_cmd(struct wmi_t *wmip,
+ WMI_SET_HOST_SLEEP_MODE_CMD *hostModeCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_SET_HOST_SLEEP_MODE_CMD *cmd;
+
+ if( hostModeCmd->awake == hostModeCmd->asleep) {
+ return A_EINVAL;
+ }
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SET_HOST_SLEEP_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, hostModeCmd, sizeof(WMI_SET_HOST_SLEEP_MODE_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_HOST_SLEEP_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wow_mode_cmd(struct wmi_t *wmip,
+ WMI_SET_WOW_MODE_CMD *wowModeCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_SET_WOW_MODE_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SET_WOW_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, wowModeCmd, sizeof(WMI_SET_WOW_MODE_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WOW_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_get_wow_list_cmd(struct wmi_t *wmip,
+ WMI_GET_WOW_LIST_CMD *wowListCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_GET_WOW_LIST_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_GET_WOW_LIST_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, wowListCmd, sizeof(WMI_GET_WOW_LIST_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_WOW_LIST_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+static A_STATUS
+wmi_get_wow_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+ WMI_GET_WOW_LIST_REPLY *reply;
+
+ if (len < sizeof(WMI_GET_WOW_LIST_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_GET_WOW_LIST_REPLY *)datap;
+
+ A_WMI_WOW_LIST_EVENT(wmip->wmi_devt, reply->num_filters,
+ reply);
+
+ return A_OK;
+}
+
+A_STATUS wmi_add_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_ADD_WOW_PATTERN_CMD *addWowCmd,
+ A_UINT8* pattern, A_UINT8* mask,
+ A_UINT8 pattern_size)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_ADD_WOW_PATTERN_CMD *cmd;
+ A_UINT8 *filter_mask = NULL;
+
+ size = sizeof (*cmd);
+
+ size += ((2 * addWowCmd->filter_size)* sizeof(A_UINT8));
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_ADD_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->filter_list_id = addWowCmd->filter_list_id;
+ cmd->filter_offset = addWowCmd->filter_offset;
+ cmd->filter_size = addWowCmd->filter_size;
+
+ A_MEMCPY(cmd->filter, pattern, addWowCmd->filter_size);
+
+ filter_mask = (A_UINT8*)(cmd->filter + cmd->filter_size);
+ A_MEMCPY(filter_mask, mask, addWowCmd->filter_size);
+
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_WOW_PATTERN_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_del_wow_pattern_cmd(struct wmi_t *wmip,
+ WMI_DEL_WOW_PATTERN_CMD *delWowCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_DEL_WOW_PATTERN_CMD *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_DEL_WOW_PATTERN_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, delWowCmd, sizeof(WMI_DEL_WOW_PATTERN_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DEL_WOW_PATTERN_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_snr_threshold_params(struct wmi_t *wmip,
+ WMI_SNR_THRESHOLD_PARAMS_CMD *snrCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_SNR_THRESHOLD_PARAMS_CMD *cmd;
+ /* These values are in ascending order */
+ if( snrCmd->thresholdAbove4_Val <= snrCmd->thresholdAbove3_Val ||
+ snrCmd->thresholdAbove3_Val <= snrCmd->thresholdAbove2_Val ||
+ snrCmd->thresholdAbove2_Val <= snrCmd->thresholdAbove1_Val ||
+ snrCmd->thresholdBelow4_Val <= snrCmd->thresholdBelow3_Val ||
+ snrCmd->thresholdBelow3_Val <= snrCmd->thresholdBelow2_Val ||
+ snrCmd->thresholdBelow2_Val <= snrCmd->thresholdBelow1_Val) {
+
+ return A_EINVAL;
+ }
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SNR_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, snrCmd, sizeof(WMI_SNR_THRESHOLD_PARAMS_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SNR_THRESHOLD_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_clr_rssi_snr(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(int));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_CLR_RSSI_SNR_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lq_threshold_params(struct wmi_t *wmip,
+ WMI_LQ_THRESHOLD_PARAMS_CMD *lqCmd)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_LQ_THRESHOLD_PARAMS_CMD *cmd;
+ /* These values are in ascending order */
+ if( lqCmd->thresholdAbove4_Val <= lqCmd->thresholdAbove3_Val ||
+ lqCmd->thresholdAbove3_Val <= lqCmd->thresholdAbove2_Val ||
+ lqCmd->thresholdAbove2_Val <= lqCmd->thresholdAbove1_Val ||
+ lqCmd->thresholdBelow4_Val <= lqCmd->thresholdBelow3_Val ||
+ lqCmd->thresholdBelow3_Val <= lqCmd->thresholdBelow2_Val ||
+ lqCmd->thresholdBelow2_Val <= lqCmd->thresholdBelow1_Val ) {
+
+ return A_EINVAL;
+ }
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_LQ_THRESHOLD_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+ A_MEMCPY(cmd, lqCmd, sizeof(WMI_LQ_THRESHOLD_PARAMS_CMD));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_LQ_THRESHOLD_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_error_report_bitmask(struct wmi_t *wmip, A_UINT32 mask)
+{
+ void *osbuf;
+ A_INT8 size;
+ WMI_TARGET_ERROR_REPORT_BITMASK *cmd;
+
+ size = sizeof (*cmd);
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_TARGET_ERROR_REPORT_BITMASK *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ cmd->bitmask = mask;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_TARGET_ERROR_REPORT_BITMASK_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_challenge_resp_cmd(struct wmi_t *wmip, A_UINT32 cookie, A_UINT32 source)
+{
+ void *osbuf;
+ WMIX_HB_CHALLENGE_RESP_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMIX_HB_CHALLENGE_RESP_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->cookie = cookie;
+ cmd->source = source;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_HB_CHALLENGE_RESP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_config_debug_module_cmd(struct wmi_t *wmip, A_UINT16 mmask,
+ A_UINT16 tsr, A_BOOL rep, A_UINT16 size,
+ A_UINT32 valid)
+{
+ void *osbuf;
+ WMIX_DBGLOG_CFG_MODULE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMIX_DBGLOG_CFG_MODULE_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->config.cfgmmask = mmask;
+ cmd->config.cfgtsr = tsr;
+ cmd->config.cfgrep = rep;
+ cmd->config.cfgsize = size;
+ cmd->config.cfgvalid = valid;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DBGLOG_CFG_MODULE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_stats_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_STATISTICS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_addBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex, A_UINT8 *bssid)
+{
+ void *osbuf;
+ WMI_ADD_BAD_AP_CMD *cmd;
+
+ if ((bssid == NULL) || (apIndex > WMI_MAX_BAD_AP_INDEX)) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_ADD_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->badApIndex = apIndex;
+ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_ADD_BAD_AP_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_deleteBadAp_cmd(struct wmi_t *wmip, A_UINT8 apIndex)
+{
+ void *osbuf;
+ WMI_DELETE_BAD_AP_CMD *cmd;
+
+ if (apIndex > WMI_MAX_BAD_AP_INDEX) {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_DELETE_BAD_AP_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->badApIndex = apIndex;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_DELETE_BAD_AP_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_txPwr_cmd(struct wmi_t *wmip, A_UINT8 dbM)
+{
+ void *osbuf;
+ WMI_SET_TX_PWR_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_TX_PWR_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->dbM = dbM;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_txPwr_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_TX_PWR_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_switch_radio(struct wmi_t *wmip, A_UINT8 on)
+{
+ WMI_SCAN_PARAMS_CMD scParams = {0, 0, 0, 0, 0,
+ WMI_SHORTSCANRATIO_DEFAULT,
+ DEFAULT_SCAN_CTRL_FLAGS,
+ 0};
+
+ if (on) {
+ /* Enable foreground scanning */
+ if (wmi_scanparams_cmd(wmip, scParams.fg_start_period,
+ scParams.fg_end_period,
+ scParams.bg_period,
+ scParams.minact_chdwell_time,
+ scParams.maxact_chdwell_time,
+ scParams.pas_chdwell_time,
+ scParams.shortScanRatio,
+ scParams.scanCtrlFlags,
+ scParams.max_dfsch_act_time) != A_OK) {
+ return -EIO;
+ }
+ } else {
+ wmi_disconnect_cmd(wmip);
+ if (wmi_scanparams_cmd(wmip, 0xFFFF, 0, 0, 0,
+ 0, 0, 0, 0xFF, 0) != A_OK) {
+ return -EIO;
+ }
+ }
+
+ return A_OK;
+}
+
+
+A_UINT16
+wmi_get_mapped_qos_queue(struct wmi_t *wmip, A_UINT8 trafficClass)
+{
+ A_UINT16 activeTsids=0;
+
+ LOCK_WMI(wmip);
+ activeTsids = wmip->wmi_streamExistsForAC[trafficClass];
+ UNLOCK_WMI(wmip);
+
+ return activeTsids;
+}
+
+A_STATUS
+wmi_get_roam_tbl_cmd(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ osbuf = A_NETBUF_ALLOC(0); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_TBL_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_roam_data_cmd(struct wmi_t *wmip, A_UINT8 roamDataType)
+{
+ void *osbuf;
+ A_UINT32 size = sizeof(A_UINT8);
+ WMI_TARGET_ROAM_DATA *cmd;
+
+ osbuf = A_NETBUF_ALLOC(size); /* no payload */
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_TARGET_ROAM_DATA *)(A_NETBUF_DATA(osbuf));
+ cmd->roamDataType = roamDataType;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_ROAM_DATA_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_roam_ctrl_cmd(struct wmi_t *wmip, WMI_SET_ROAM_CTRL_CMD *p,
+ A_UINT8 size)
+{
+ void *osbuf;
+ WMI_SET_ROAM_CTRL_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_SET_ROAM_CTRL_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ A_MEMCPY(cmd, p, size);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ROAM_CTRL_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_powersave_timers_cmd(struct wmi_t *wmip,
+ WMI_POWERSAVE_TIMERS_POLICY_CMD *pCmd,
+ A_UINT8 size)
+{
+ void *osbuf;
+ WMI_POWERSAVE_TIMERS_POLICY_CMD *cmd;
+
+ /* These timers can't be zero */
+ if(!pCmd->psPollTimeout || !pCmd->triggerTimeout ||
+ !(pCmd->apsdTimPolicy == IGNORE_TIM_ALL_QUEUES_APSD ||
+ pCmd->apsdTimPolicy == PROCESS_TIM_ALL_QUEUES_APSD) ||
+ !(pCmd->simulatedAPSDTimPolicy == IGNORE_TIM_SIMULATED_APSD ||
+ pCmd->simulatedAPSDTimPolicy == PROCESS_TIM_SIMULATED_APSD))
+ return A_EINVAL;
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, size);
+
+ cmd = (WMI_POWERSAVE_TIMERS_POLICY_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, size);
+
+ A_MEMCPY(cmd, pCmd, size);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_POWERSAVE_TIMERS_POLICY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+#ifdef CONFIG_HOST_GPIO_SUPPORT
+/* Send a command to Target to change GPIO output pins. */
+A_STATUS
+wmi_gpio_output_set(struct wmi_t *wmip,
+ A_UINT32 set_mask,
+ A_UINT32 clear_mask,
+ A_UINT32 enable_mask,
+ A_UINT32 disable_mask)
+{
+ void *osbuf;
+ WMIX_GPIO_OUTPUT_SET_CMD *output_set;
+ int size;
+
+ size = sizeof(*output_set);
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
+ set_mask, clear_mask, enable_mask, disable_mask));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+ output_set->set_mask = set_mask;
+ output_set->clear_mask = clear_mask;
+ output_set->enable_mask = enable_mask;
+ output_set->disable_mask = disable_mask;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target requesting state of the GPIO input pins */
+A_STATUS
+wmi_gpio_input_get(struct wmi_t *wmip)
+{
+ void *osbuf;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ osbuf = A_NETBUF_ALLOC(0);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INPUT_GET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target that changes the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_set(struct wmi_t *wmip,
+ A_UINT32 gpioreg_id,
+ A_UINT32 value)
+{
+ void *osbuf;
+ WMIX_GPIO_REGISTER_SET_CMD *register_set;
+ int size;
+
+ size = sizeof(*register_set);
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
+
+ register_set->gpioreg_id = gpioreg_id;
+ register_set->value = value;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target to fetch the value of a GPIO register. */
+A_STATUS
+wmi_gpio_register_get(struct wmi_t *wmip,
+ A_UINT32 gpioreg_id)
+{
+ void *osbuf;
+ WMIX_GPIO_REGISTER_GET_CMD *register_get;
+ int size;
+
+ size = sizeof(*register_get);
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
+
+ register_get->gpioreg_id = gpioreg_id;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+/* Send a command to the Target acknowledging some GPIO interrupts. */
+A_STATUS
+wmi_gpio_intr_ack(struct wmi_t *wmip,
+ A_UINT32 ack_mask)
+{
+ void *osbuf;
+ WMIX_GPIO_INTR_ACK_CMD *intr_ack;
+ int size;
+
+ size = sizeof(*intr_ack);
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
+
+ intr_ack->ack_mask = ack_mask;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_GPIO_SUPPORT */
+
+A_STATUS
+wmi_set_access_params_cmd(struct wmi_t *wmip, A_UINT16 txop, A_UINT8 eCWmin,
+ A_UINT8 eCWmax, A_UINT8 aifsn)
+{
+ void *osbuf;
+ WMI_SET_ACCESS_PARAMS_CMD *cmd;
+
+ if ((eCWmin > WMI_MAX_CW_ACPARAM) || (eCWmax > WMI_MAX_CW_ACPARAM) ||
+ (aifsn > WMI_MAX_AIFSN_ACPARAM))
+ {
+ return A_EINVAL;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_ACCESS_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->txop = txop;
+ cmd->eCWmin = eCWmin;
+ cmd->eCWmax = eCWmax;
+ cmd->aifsn = aifsn;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_ACCESS_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_retry_limits_cmd(struct wmi_t *wmip, A_UINT8 frameType,
+ A_UINT8 trafficClass, A_UINT8 maxRetries,
+ A_UINT8 enableNotify)
+{
+ void *osbuf;
+ WMI_SET_RETRY_LIMITS_CMD *cmd;
+
+ if ((frameType != MGMT_FRAMETYPE) && (frameType != CONTROL_FRAMETYPE) &&
+ (frameType != DATA_FRAMETYPE))
+ {
+ return A_EINVAL;
+ }
+
+ if (maxRetries > WMI_MAX_RETRIES) {
+ return A_EINVAL;
+ }
+
+ if (frameType != DATA_FRAMETYPE) {
+ trafficClass = 0;
+ }
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_RETRY_LIMITS_CMD *)(A_NETBUF_DATA(osbuf));
+ cmd->frameType = frameType;
+ cmd->trafficClass = trafficClass;
+ cmd->maxRetries = maxRetries;
+ cmd->enableNotify = enableNotify;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_RETRY_LIMITS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+void
+wmi_get_current_bssid(struct wmi_t *wmip, A_UINT8 *bssid)
+{
+ if (bssid != NULL) {
+ A_MEMCPY(bssid, wmip->wmi_bssid, ATH_MAC_LEN);
+ }
+}
+
+A_STATUS
+wmi_set_opt_mode_cmd(struct wmi_t *wmip, A_UINT8 optMode)
+{
+ void *osbuf;
+ WMI_SET_OPT_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_OPT_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->optMode = optMode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_OPT_MODE_CMDID,
+ SYNC_BOTH_WMIFLAG));
+}
+
+A_STATUS
+wmi_opt_tx_frame_cmd(struct wmi_t *wmip,
+ A_UINT8 frmType,
+ A_UINT8 *dstMacAddr,
+ A_UINT8 *bssid,
+ A_UINT16 optIEDataLen,
+ A_UINT8 *optIEData)
+{
+ void *osbuf;
+ WMI_OPT_TX_FRAME_CMD *cmd;
+ osbuf = A_NETBUF_ALLOC(optIEDataLen + sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, (optIEDataLen + sizeof(*cmd)));
+
+ cmd = (WMI_OPT_TX_FRAME_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, (optIEDataLen + sizeof(*cmd)-1));
+
+ cmd->frmType = frmType;
+ cmd->optIEDataLen = optIEDataLen;
+ //cmd->optIEData = (A_UINT8 *)((int)cmd + sizeof(*cmd));
+ A_MEMCPY(cmd->bssid, bssid, sizeof(cmd->bssid));
+ A_MEMCPY(cmd->dstAddr, dstMacAddr, sizeof(cmd->dstAddr));
+ A_MEMCPY(&cmd->optIEData[0], optIEData, optIEDataLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_OPT_TX_FRAME_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_adhoc_bconIntvl_cmd(struct wmi_t *wmip, A_UINT16 intvl)
+{
+ void *osbuf;
+ WMI_BEACON_INT_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_BEACON_INT_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->beaconInterval = intvl;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BEACON_INT_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_voice_pkt_size_cmd(struct wmi_t *wmip, A_UINT16 voicePktSize)
+{
+ void *osbuf;
+ WMI_SET_VOICE_PKT_SIZE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_VOICE_PKT_SIZE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->voicePktSize = voicePktSize;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_VOICE_PKT_SIZE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+
+A_STATUS
+wmi_set_max_sp_len_cmd(struct wmi_t *wmip, A_UINT8 maxSPLen)
+{
+ void *osbuf;
+ WMI_SET_MAX_SP_LEN_CMD *cmd;
+
+ /* maxSPLen is a two-bit value. If user trys to set anything
+ * other than this, then its invalid
+ */
+ if(maxSPLen & ~0x03)
+ return A_EINVAL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_MAX_SP_LEN_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->maxSPLen = maxSPLen;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_MAX_SP_LEN_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+convert_userPriority_to_trafficClass(A_UINT8 userPriority)
+{
+ return (up_to_ac[userPriority & 0x7]);
+}
+
+A_UINT8
+wmi_get_power_mode_cmd(struct wmi_t *wmip)
+{
+ return wmip->wmi_powerMode;
+}
+
+A_STATUS
+wmi_verify_tspec_params(WMI_CREATE_PSTREAM_CMD *pCmd, A_BOOL tspecCompliance)
+{
+ return A_OK;
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+static A_STATUS
+wmi_tcmd_test_report_rx(struct wmi_t *wmip, A_UINT8 *datap, int len)
+{
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
+
+ return A_OK;
+}
+
+#endif /* CONFIG_HOST_TCMD_SUPPORT*/
+
+A_STATUS
+wmi_set_authmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+ void *osbuf;
+ WMI_SET_AUTH_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_AUTH_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->mode = mode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_AUTH_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_reassocmode_cmd(struct wmi_t *wmip, A_UINT8 mode)
+{
+ void *osbuf;
+ WMI_SET_REASSOC_MODE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_REASSOC_MODE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->mode = mode;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_REASSOC_MODE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_lpreamble_cmd(struct wmi_t *wmip, A_UINT8 status)
+{
+ void *osbuf;
+ WMI_SET_LPREAMBLE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_LPREAMBLE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->status = status;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_LPREAMBLE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_rts_cmd(struct wmi_t *wmip, A_UINT16 threshold)
+{
+ void *osbuf;
+ WMI_SET_RTS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_RTS_CMD*)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->threshold = threshold;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_RTS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_wmm_cmd(struct wmi_t *wmip, WMI_WMM_STATUS status)
+{
+ void *osbuf;
+ WMI_SET_WMM_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_WMM_CMD*)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->status = status;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+A_STATUS
+wmi_set_wmm_txop(struct wmi_t *wmip, WMI_TXOP_CFG cfg)
+{
+ void *osbuf;
+ WMI_SET_WMM_TXOP_CMD *cmd;
+
+ if( !((cfg == WMI_TXOP_DISABLED) || (cfg == WMI_TXOP_ENABLED)) )
+ return A_EINVAL;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_WMM_TXOP_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->txopEnable = cfg;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WMM_TXOP_CMDID,
+ NO_SYNC_WMIFLAG));
+
+}
+
+#ifdef CONFIG_HOST_TCMD_SUPPORT
+/* WMI layer doesn't need to know the data type of the test cmd.
+ This would be beneficial for customers like Qualcomm, who might
+ have different test command requirements from differnt manufacturers
+ */
+A_STATUS
+wmi_test_cmd(struct wmi_t *wmip, A_UINT8 *buf, A_UINT32 len)
+{
+ void *osbuf;
+ char *data;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
+
+ osbuf= A_NETBUF_ALLOC(len);
+ if(osbuf == NULL)
+ {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, len);
+ data = A_NETBUF_DATA(osbuf);
+ A_MEMCPY(data, buf, len);
+
+ return(wmi_cmd_send(wmip, osbuf, WMI_TEST_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+#endif
+
+A_STATUS
+wmi_set_bt_status_cmd(struct wmi_t *wmip, A_UINT8 streamType, A_UINT8 status)
+{
+ void *osbuf;
+ WMI_SET_BT_STATUS_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_BT_STATUS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->streamType = streamType;
+ cmd->status = status;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_STATUS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_bt_params_cmd(struct wmi_t *wmip, WMI_SET_BT_PARAMS_CMD* cmd)
+{
+ void *osbuf;
+ WMI_SET_BT_PARAMS_CMD* alloc_cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ alloc_cmd = (WMI_SET_BT_PARAMS_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(alloc_cmd, sizeof(*cmd));
+ A_MEMCPY(alloc_cmd, cmd, sizeof(*cmd));
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_BT_PARAMS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_get_keepalive_configured(struct wmi_t *wmip)
+{
+ void *osbuf;
+ WMI_GET_KEEPALIVE_CMD *cmd;
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+ cmd = (WMI_GET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ return (wmi_cmd_send(wmip, osbuf, WMI_GET_KEEPALIVE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_UINT8
+wmi_get_keepalive_cmd(struct wmi_t *wmip)
+{
+ return wmip->wmi_keepaliveInterval;
+}
+
+A_STATUS
+wmi_set_keepalive_cmd(struct wmi_t *wmip, A_UINT8 keepaliveInterval)
+{
+ void *osbuf;
+ WMI_SET_KEEPALIVE_CMD *cmd;
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*cmd));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*cmd));
+
+ cmd = (WMI_SET_KEEPALIVE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd->keepaliveInterval = keepaliveInterval;
+ wmip->wmi_keepaliveInterval = keepaliveInterval;
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_KEEPALIVE_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_appie_cmd(struct wmi_t *wmip, A_UINT8 mgmtFrmType, A_UINT8 ieLen,
+ A_UINT8 *ieInfo)
+{
+ void *osbuf;
+ WMI_SET_APPIE_CMD *cmd;
+ A_UINT16 cmdLen;
+
+ if (ieLen > WMI_MAX_IE_LEN) {
+ return A_ERROR;
+ }
+ cmdLen = sizeof(*cmd) + ieLen - 1;
+ osbuf = A_NETBUF_ALLOC(cmdLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, cmdLen);
+
+ cmd = (WMI_SET_APPIE_CMD *)(A_NETBUF_DATA(osbuf));
+ A_MEMZERO(cmd, cmdLen);
+
+ cmd->mgmtFrmType = mgmtFrmType;
+ cmd->ieLen = ieLen;
+ A_MEMCPY(cmd->ieInfo, ieInfo, ieLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_APPIE_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_STATUS
+wmi_set_halparam_cmd(struct wmi_t *wmip, A_UINT8 *cmd, A_UINT16 dataLen)
+{
+ void *osbuf;
+ A_UINT8 *data;
+
+ osbuf = A_NETBUF_ALLOC(dataLen);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, dataLen);
+
+ data = A_NETBUF_DATA(osbuf);
+
+ A_MEMCPY(data, cmd, dataLen);
+
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WHALPARAM_CMDID, NO_SYNC_WMIFLAG));
+}
+
+A_INT32
+wmi_get_rate(A_INT8 rateindex)
+{
+ if (rateindex == RATE_AUTO) {
+ return 0;
+ } else {
+ return(wmi_rateTable[(A_UINT32) rateindex]);
+ }
+}
+
+void
+wmi_node_return (struct wmi_t *wmip, bss_t *bss)
+{
+ if (NULL != bss)
+ {
+ wlan_node_return (&wmip->wmi_scan_table, bss);
+ }
+}
+
+bss_t *
+wmi_find_Ssidnode (struct wmi_t *wmip, A_UCHAR *pSsid,
+ A_UINT32 ssidLength, A_BOOL bIsWPA2)
+{
+ bss_t *node = NULL;
+ node = wlan_find_Ssidnode (&wmip->wmi_scan_table, pSsid,
+ ssidLength, bIsWPA2);
+ return node;
+}
+
+void
+wmi_free_allnodes(struct wmi_t *wmip)
+{
+ wlan_free_allnodes(&wmip->wmi_scan_table);
+}
+
+bss_t *
+wmi_find_node(struct wmi_t *wmip, const A_UINT8 *macaddr)
+{
+ bss_t *ni=NULL;
+ ni=wlan_find_node(&wmip->wmi_scan_table,macaddr);
+ return ni;
+}
+
+A_STATUS
+wmi_dset_open_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT32 access_cookie,
+ A_UINT32 dset_size,
+ A_UINT32 dset_version,
+ A_UINT32 targ_handle,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg)
+{
+ void *osbuf;
+ WMIX_DSETOPEN_REPLY_CMD *open_reply;
+
+ A_DPRINTF(DBG_WMI, (DBGFMT "Enter - wmip=0x%x\n", DBGARG, (int)wmip));
+
+ osbuf = A_NETBUF_ALLOC(sizeof(*open_reply));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ A_NETBUF_PUT(osbuf, sizeof(*open_reply));
+ open_reply = (WMIX_DSETOPEN_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+ open_reply->status = status;
+ open_reply->targ_dset_handle = targ_handle;
+ open_reply->targ_reply_fn = targ_reply_fn;
+ open_reply->targ_reply_arg = targ_reply_arg;
+ open_reply->access_cookie = access_cookie;
+ open_reply->size = dset_size;
+ open_reply->version = dset_version;
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETOPEN_REPLY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
+static A_STATUS
+wmi_get_pmkid_list_event_rx(struct wmi_t *wmip, A_UINT8 *datap, A_UINT32 len)
+{
+ WMI_PMKID_LIST_REPLY *reply;
+ A_UINT32 expected_len;
+
+ if (len < sizeof(WMI_PMKID_LIST_REPLY)) {
+ return A_EINVAL;
+ }
+ reply = (WMI_PMKID_LIST_REPLY *)datap;
+ expected_len = sizeof(reply->numPMKID) + reply->numPMKID * WMI_PMKID_LEN;
+
+ if (len < expected_len) {
+ return A_EINVAL;
+ }
+
+ A_WMI_PMKID_LIST_EVENT(wmip->wmi_devt, reply->numPMKID,
+ reply->pmkidList);
+
+ return A_OK;
+}
+
+#ifdef CONFIG_HOST_DSET_SUPPORT
+A_STATUS
+wmi_dset_data_reply(struct wmi_t *wmip,
+ A_UINT32 status,
+ A_UINT8 *user_buf,
+ A_UINT32 length,
+ A_UINT32 targ_buf,
+ A_UINT32 targ_reply_fn,
+ A_UINT32 targ_reply_arg)
+{
+ void *osbuf;
+ WMIX_DSETDATA_REPLY_CMD *data_reply;
+ int size;
+
+ size = sizeof(*data_reply) + length;
+
+ A_DPRINTF(DBG_WMI,
+ (DBGFMT "Enter - length=%d status=%d\n", DBGARG, length, status));
+
+ osbuf = A_NETBUF_ALLOC(size);
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+ A_NETBUF_PUT(osbuf, size);
+ data_reply = (WMIX_DSETDATA_REPLY_CMD *)(A_NETBUF_DATA(osbuf));
+
+ data_reply->status = status;
+ data_reply->targ_buf = targ_buf;
+ data_reply->targ_reply_fn = targ_reply_fn;
+ data_reply->targ_reply_arg = targ_reply_arg;
+ data_reply->length = length;
+
+ if (status == A_OK) {
+ if (a_copy_from_user(data_reply->buf, user_buf, length)) {
+ return A_ERROR;
+ }
+ }
+
+ return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_DSETDATA_REPLY_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+#endif /* CONFIG_HOST_DSET_SUPPORT */
+
+A_STATUS
+wmi_set_wsc_status_cmd(struct wmi_t *wmip, A_UINT32 status)
+{
+ void *osbuf;
+ char *cmd;
+
+ wps_enable = status;
+
+ osbuf = a_netbuf_alloc(sizeof(1));
+ if (osbuf == NULL) {
+ return A_NO_MEMORY;
+ }
+
+ a_netbuf_put(osbuf, sizeof(1));
+
+ cmd = (char *)(a_netbuf_to_data(osbuf));
+
+ A_MEMZERO(cmd, sizeof(*cmd));
+ cmd[0] = (status?1:0);
+ return (wmi_cmd_send(wmip, osbuf, WMI_SET_WSC_STATUS_CMDID,
+ NO_SYNC_WMIFLAG));
+}
+
--- /dev/null
+++ b/drivers/ar6000/wmi/wmi_doc.h
@@ -0,0 +1,4421 @@
+/*
+ *
+ * Copyright (c) 2004-2007 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+
+#if 0
+Wireless Module Interface (WMI) Documentaion
+
+ This section describes the format and the usage model for WMI control and
+ data messages between the host and the AR6000-based targets. The header
+ file include/wmi.h contains all command and event manifest constants as
+ well as structure typedefs for each set of command and reply parameters.
+
+Data Frames
+
+ The data payload transmitted and received by the target follows RFC-1042
+ encapsulation and thus starts with an 802.2-style LLC-SNAP header. The
+ WLAN module completes 802.11 encapsulation of the payload, including the
+ MAC header, FCS, and WLAN security related fields. At the interface to the
+ message transport (HTC), a data frame is encapsulated in a WMI message.
+
+WMI Message Structure
+
+ The WMI protocol leverages an 802.3-style Ethernet header in communicating
+ the source and destination information between the host and the AR6000
+ modules using a 14-byte 802.3 header ahead of the 802.2-style payload. In
+ addition, the WMI protocol adds a header to all data messages:
+
+ {
+ INT8 rssi
+ The RSSI of the received packet and its units are shown in db above the
+ noise floor, and the noise floor is shown in dbm.
+ UINT8 info
+ Contains information on message type and user priority. Message type
+ differentiates between a data packet and a synchronization message.
+ } WMI_DATA_HDR
+
+ User priority contains the 802.1d user priority info from host to target. Host
+ software translates the host Ethernet format to 802.3 format prior to Tx and
+ 802.3 format to host format in the Rx direction. The host does not transmit the
+ FCS that follows the data. MsgType differentiates between a regular data
+ packet (msgType=0) and a synchronization message (msgType=1).
+
+Data Endpoints
+
+ The AR6000 chipset provides several data endpoints to support quality of
+ service (QoS) and maintains separate queues and separate DMA engines for
+ each data endpoint. A data endpoint can be bi-directional.
+
+ Best effort (BE) class traffic uses the default data endpoint (2). The host can
+ establish up to two additional data endpoints for other traffic classes. Once
+ such a data endpoint is established, it sends and receives corresponding QoS
+ traffic in a manner similar to the default data endpoint.
+
+ If QoS is desired over the interconnect, host software must classify each data
+ packet and place it on the appropriate data endpoint. The information
+ required to classify data is generally available in-band as an 802.1p/q style
+ tag or as the ToS field in the IP header. The information may also be available
+ out-of-band depending on the host DDI.
+
+Connection States
+
+ Table B-1 describes the AR6000 WLAN connection states:
+
+ Table B-1. AR6000 Connection States
+
+Connection State
+ Description
+
+ DISCONNECTED
+ In this state, the AR6000 device is not connected to a wireless
+ network. The device is in this state after reset when it sends the
+ WIRELESS MODULE <20>READY<44> EVENT, after it processes a
+ DISCONNECT command, and when it loses its link with the
+ access point (AP) that it was connected to. The device signals a
+ transition to the DISCONNECTED state with a <20>DISCONNECT<43>
+ event.
+
+CONNECTED
+ In this state, the AR6000 device is connected to wireless networks.
+ The device enters this state after successfully processing a
+ CONNECT, which establishes a connection with a wireless
+ network. The device signals a transition to the CONNECTED state
+ with a <20>CONNECT<43> event.
+
+
+Message Types
+
+ WMI uses commands, replies, and events for the control and configuration of
+ the AR6000 device. The control protocol is asynchronous. Table B-2 describes
+ AR6000 message types:
+
+Table B-2. AR6000 Message Types
+
+Message Type
+ Description
+
+Commands
+ Control messages that flow from the host to the device
+
+Replies/Events
+ Control messages that flow from the device to the host.
+
+ The device issues a reply to some WMI commands, but not to others.
+ The payload in a reply is command-specific, and some commands do
+ not trigger a reply message at all. Events are control messages issued
+ by the device to signal the occurrence of an asynchronous event.
+
+
+WMI Message Format
+
+ All WMI control commands, replies and events use the header format:
+
+ WMI_CMD_HDR Header Format
+ {
+ UINT16 id
+ This 16-bit constant identifies which WMI command the host is issuing,
+ which command the target is replying to, or which event has occurred.
+ WMI_CMD_HDR
+ }
+
+
+ A variable-size command-, reply-, or event-specific payload follows the
+ header. Over the interconnect, all fields in control messages (including
+ WMI_CMD_HDR and the command specific payload) use 32-bit little Endian
+ byte ordering and fields are packed. The AR6000 device always executes
+ commands in order, and the host may send multiple commands without
+ waiting for previous commands to complete. A majority of commands are
+ processed to completion once received. Other commands trigger a longer
+ duration activity whose completion is signaled to the host through an event.
+
+Command Restrictions
+
+ Some commands may only be issued when the AR6000 device is in a certain
+ state. The host is required to wait for an event signaling a state transition
+ before such a command can be issued. For example, if a command requires
+ the device to be in the CONNECTED state, then the host is required to wait
+ for a <20>CONNECT<43> event before it issues that command.
+
+ The device ignores any commands inappropriate for its current state. If the
+ command triggers a reply, the device generates an error reply. Otherwise, the
+ device silently ignores the inappropriate command.
+
+Command and Data Synchronization
+
+ WMI provides a mechanism for a host to advise the device of necessary
+ synchronization between commands and data. The device implements
+ synchronization; no implicit synchronization exists between endpoints.
+
+ The host controls synchronization using the <20>SYNCHRONIZE<5A> command
+ over the control channel and synchronization messages over data channels.
+ The device stops each data channel upon receiving a synchronization message
+ on that channel, processing all data packets received prior to that message.
+ After the device receives synchronization messages for each data endpoint
+ and the <20>SYNCHRONIZE<5A> command, it resumes all channels.
+
+ When the host must guarantee a command executes before processing new
+ data packets, it first issues the command, then issues the <20>SYNCHRONIZE<5A>
+ command and sends synchronization messages on data channels. When the
+ host must guarantee the device has processed all old data packets before a
+ processing a new command, it issues a <20>SYNCHRONIZE<5A> command and
+ synchronization messages on all data channels, then issues the desired
+ command.
+
+
+
+WMI Commands
+
+ ADD_BAD_AP
+ Cause the AR6000 device to avoid a particular AP
+ ADD_CIPHER_KEY
+ Add or replace any of the four AR6000 encryption keys
+ ADD_WOW_PATTERN
+ Used to add a pattern to the WoW pattern list
+ CLR_RSSI_SNR
+ Clear the current calculated RSSI and SNR value
+ CONNECT_CMD
+ Request that the AR6000 device establish a wireless connection
+ with the specified SSID
+ CREATE_PSTREAM
+ Create prioritized data endpoint between the host and device
+ DELETE_BAD_AP
+ Clear an entry in the bad AP table
+ DELETE_CIPHER_KEY
+ Delete a previously added cipher key
+ DELETE_PSTREAM
+ Delete a prioritized data endpoint
+ DELETE_WOW_PATTERN
+ Remove a pre-specified pattern from the WoW pattern list
+ EXTENSION
+ WMI message interface command
+ GET_BIT_RATE
+ Retrieve rate most recently used by the AR6000
+ GET_CHANNEL_LIST
+ Retrieve list of channels used by the AR6000
+ GET_FIXRATES
+ Retrieves the rate-mask set via the SET_FIXRATES command.
+ GET_PMKID_LIST_CMD
+ Retrieve the firmware list of PMKIDs
+ GET_ROAM_DATA
+ Internal use for data collection; available in special build only
+ GET_ROAM_TBL
+ Retrieve the roaming table maintained on the target
+ GET_TARGET_STATS
+ Request that the target send the statistics it maintains
+ GET_TX_PWR
+ Retrieve the current AR6000 device Tx power levels
+ GET_WOW_LIST
+ Retrieve the current list of WoW patterns
+ LQ_THRESHOLD_PARAMS
+ Set the link quality thresholds
+ OPT_TX_FRAME
+ Send a special frame (special feature)
+ RECONNECT
+ Request a reconnection to a BSS
+ RSSI_THRESHOLD_PARAMS
+ Configure how the AR6000 device monitors and reports signal
+ strength (RSSI) of the connected BSS
+ SCAN_PARAMS
+ Determine dwell time and changes scanned channels
+ SET_ACCESS_PARAMS
+ Set access parameters for the wireless network
+ SET_ADHOC_BSSID
+ Set the BSSID for an ad hoc network
+ SET_AKMP_PARAMS
+ Set multiPMKID mode
+ SET_APPIE
+ Add application-specified IE to a management frame
+ SET_ASSOC_INFO
+ Specify the IEs the device should add to association or
+ reassociation requests
+ SET_AUTH_MODE
+ Set 802.11 authentication mode of reconnection
+ SET_BEACON_INT
+ Set the beacon interval for an ad hoc network
+ SET_BIT_RATE
+ Set the AR6000 to a specific fixed bit rate
+ SET_BMISS_TIME
+ Set the beacon miss time
+ SET_BSS_FILTER
+ Inform the AR6000 of network types about which it wants to
+ receive information using a <20>BSSINFO<46> event
+ SET_BT_PARAMS
+ Set the status of a Bluetooth stream (SCO or A2DP) or set
+ Bluetooth coexistence register parameters
+ SET_BT_STATUS
+ Set the status of a Bluetooth stream (SCO or A2DP)
+ SET_CHANNEL_PARAMETERS
+ Configure WLAN channel parameters
+ SET_DISC_TIMEOUT
+ Set the amount of time the AR6000 spends attempting to
+ reestablish a connection
+ SET_FIXRATES
+ Set the device to a specific fixed PHY rate (supported subset)
+ SET_HALPARAM
+ Internal AR6000 command to set certain hardware parameters
+ SET_HOST_SLEEP_MODE
+ Set the host mode to asleep or awake
+ SET_IBSS_PM_CAPS
+ Support a non-standard power management scheme for an
+ ad hoc network
+ SET_LISTEN_INT
+ Request a listen interval
+ SET_LPREAMBLE
+ Override the short preamble capability of the AR6000 device
+ SET_MAX_SP_LEN
+ Set the maximum service period
+ SET_OPT_MODE
+ Set the special mode on/off (special feature)
+ SET_PMKID
+ Set the pairwise master key ID (PMKID)
+ SET_PMKID_LIST_CMD
+ Configure the firmware list of PMKIDs
+ SET_POWER_MODE
+ Set guidelines on trade-off between power utilization
+ SET_POWER_PARAMS
+ Configure power parameters
+ SET_POWERSAVE_PARAMS
+ Set the two AR6000 power save timers
+ SET_PROBED_SSID
+ Provide list of SSIDs the device should seek
+ SET_REASSOC_MODE
+ Specify whether the disassociated frame should be sent upon
+ reassociation
+ SET_RETRY_LIMITS
+ Limit how many times the device tries to send a frame
+ SET_ROAM_CTRL
+ Control roaming behavior
+ SET_RTS
+ Determine when RTS should be sent
+ SET_SCAN_PARAMS
+ Set the AR6000 scan parameters
+ SET_TKIP_COUNTERMEASURES
+ Enable/disable reports of TKIP MIC errors
+ SET_TX_PWR
+ Specify the AR6000 device Tx power levels
+ SET_VOICE_PKT_SIZE
+ Set voice packet size
+ SET_WMM
+ Override the AR6000 WMM capability
+ SET_WMM_TXOP
+ Configure TxOP bursting when sending traffic to a WMM-
+ capable AP
+ SET_WOW_MODE
+ Enable/disable WoW mode
+ SET_WSC_STATUS
+ Enable/disable profile check in cserv when the WPS protocol
+ is in progress
+ SNR_THRESHOLD_PARAMS
+ Configure how the device monitors and reports SNR of BSS
+ START_SCAN
+ Start a long or short channel scan
+ SYNCHRONIZE
+ Force a synchronization point between command and data
+ paths
+ TARGET_REPORT_ERROR_BITMASK
+ Control <20>ERROR_REPORT<52> events from the AR6000
+
+
+
+
+Name
+ ADD_BAD_AP
+
+Synopsis
+ The host uses this command to cause the AR6000 to avoid a particular AP. The
+ AR6000 maintain a table with up to two APs to avoid. An ADD_BAD_AP command
+ adds or replaces the specified entry in this bad AP table.
+
+ If the AR6000 are currently connected to the AP specified in this command, they
+ disassociate.
+
+Command
+ wmiconfig eth1 --badap <bssid> <badApIndex>
+
+Command Parameters
+ UINT8 badApIndex Index [0...1] that identifies which entry in the
+ bad AP table to use
+
+
+ UINT8 bssid[6] MAC address of the AP to avoid
+
+Command Values
+ badApIndex = 0, 1 Entry in the bad AP table to use
+
+Reset Value
+ The bad AP table is cleared
+
+Restrictions
+ None
+
+See Also
+ <20>DELETE_BAD_AP<41> on page B-13
+
+=====================================================================
+Name
+ ADD_CIPHER_KEY
+
+Synopsis
+ The host uses this command to add/replace any of four encryption keys on the
+ AR6000. The ADD_CIPHER_KEY command is issued after the CONNECT event
+ has been received by the host for all dot11Auth modes except for SHARED_AUTH.
+ When the dot11AuthMode is SHARED_AUTH, then the ADD_CIPHER_KEY
+ command should be issued before the <20>CONNECT<43> command.
+
+Command
+ wmiconfig eth1 --cipherkey <keyIndex> <keyType> <keyUsage>
+ <keyLength> <keyopctrl> <keyRSC> <key>
+
+Command Parameters
+ UINT8 keyIndex Index (0...3) of the key to add/replace;
+ uniquely identifies the key
+ UINT8 keyType CRYPTO_TYPE
+ UINT8 keyUsage Specifies usage parameters of the key when
+ keyType = WEP_CRYPT
+ UINT8 keyLength Length of the key in bytes
+ UINT8 keyOpCtrl bit[0] = Initialize TSC (default),
+ bit[1] = Initialize RSC
+ UINT8 keyRSC[8] Key replay sequence counter (RSC) initial
+ value the device should use
+ UINT8 key[32] Key material used for this connection
+ Command Values
+ {
+ NONE_CRYPT = 1
+ WEP_CRYPT = 2
+ TKIP_CRYPT = 3
+ AES_CRYPT = 4
+ KEY_OP_INIT_TSC 0x01
+ KEY_OP_INIT_RSC 0x02
+ KEY_OP_INIT_VAL 0x03
+ Default is to Initialize the TSC
+ KEY_OP_VALID_MASK 0x04
+ Two operations defined
+ } CRYPTO_TYPE
+
+ {
+ PAIRWISE_USAGE = 0 Set if the key is used for unicast traffic only
+ GROUP_USAGE = 1 Set if the key is used to receive multicast
+ traffic (also set for static WEP keys)
+ TX_USAGE = 2 Set for the GROUP key used to transmit frames
+ All others are reserved
+ } KEY_USAGE
+
+Reset Value
+ The four available keys are disabled.
+
+Restrictions
+ The cipher should correspond to the encryption mode specified in the <20>CONNECT<43>
+ command.
+
+See Also
+ <20>DELETE_CIPHER_KEY<45>
+
+=====================================================================
+
+
+Name
+ ADD_WOW_PATTERN
+
+Synopsis
+ The host uses this command to add a pattern to the WoW pattern list; used for
+ pattern-matching for host wakeups by the WoW module. If the host mode is asleep
+ and WoW is enabled, all packets are matched against the existing WoW patterns. If a
+ packet matches any of the patterns specified, the target will wake up the host. All
+ non-matching packets are discarded by the target without being sent up to the host.
+
+Command
+ wmiconfig <20>addwowpattern <list-id> <filter-size> <filter-offset>
+ <pattern> <mask>
+
+Command Parameters
+ A_UINT8 filter_list_id ID of the list that is to include the new pattern
+ A_UINT8 filter_size Size of the new pattern
+ A_UINT8 filter_offset Offset at which the pattern matching for this
+ new pattern should begin at
+ A_UINT8 filter[1] Byte stream that contains both the pattern and
+ the mask of the new WoW wake-up pattern
+
+Reply Parameters
+ None
+
+Reset Value
+ None defined (default host mode is awake)
+
+Restrictions
+ None
+
+See Also
+ <20>DELETE_WOW_PATTERN<52>
+
+=====================================================================
+
+
+Name
+ CLR_RSSI_SNR
+
+Synopsis
+ Clears the current calculated RSSI and SNR value. RSSI and SNR are reported by
+ running-average value. This command will clear the history and have a fresh start
+ for the running-average mechanism.
+
+Command
+ wmiconfig eth1 --cleanRssiSnr
+
+Command Parameters
+ None
+
+Reply Parameters
+ None
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+=====================================================================
+
+Name
+ CONNECT_CMD
+
+Synopsis
+ New connect control information (connectCtrl) is added, with 32 possible modifiers.
+
+ CONNECT_SEND_REASSOC
+ Valid only for a host-controlled connection to a
+ particular AP. If this bit is set, a reassociation frame is
+ sent. If this bit is clear, an association request frame is
+ sent to the AP.
+
+ CONNECT_IGNORE_WPAx_GROUP_CIPHER
+ No group key is issued in the CONNECT command,
+ so use the group key advertised by the AP. In a target-
+ initiated roaming situation this allows a STA to roam
+ between APs that support different multicast ciphers.
+
+ CONNECT_PROFILE_MATCH_DONE
+ In a host-controlled connection case, it is possible that
+ during connect, firmware may not have the
+ information for a profile match (e.g, when the AP
+ supports hidden SSIDs and the device may not
+ transmit probe requests during connect). By setting
+ this bit in the connection control information, the
+ firmware waits for a beacon from the AP with the
+ BSSID supplied in the CONNECT command. No
+ additional profile checks are done.
+
+ CONNECT_IGNORE_AAC_BEACON
+ Ignore the Admission Capacity information in the
+ beacon of the AP
+
+ CONNECT_ASSOC_POLICY_USER
+ When set, the CONNECT_SEND_REASSOC setting
+ determines if an Assoc or Reassoc is sent to an AP
+
+Command
+ wmiconfig --setconnectctrl <ctrl flags bitmask>
+
+Command Parameters
+ typedef struct{
+ A_UINT8 networktype;
+ A_UINT8 dot11authmode;
+ A_UINT8 authmode;
+ A_UINT8 pairwiseCryptoType; /*CRYPTO_TYPE*/
+ A_UINT8 pairwiseCryptoLen;
+ A_UINT8 groupCryptoType; /*CRYPTO_TYPE*/
+ A_UINT8 groupCryptoLen;
+ A_UINT8 ssidLength;
+ A_UCHAR ssid[WMI_MAX_SSID_LEN];
+ A_UINT16 channel;
+ A_UINT8 bssid[AUTH_MAC_LEN];
+ A_UINT8 ctrl_flags; /*WMI_CONNECT_CTRL_FLAGS_BITS*/
+ } WMI_CONNECT_CMD;
+
+ ctrl flags bitmask
+ = 0x0001 CONNECT_ASSOC_POLICY_USER
+ Assoc frames are sent using the policy specified by
+ the flag
+ = 0x0002 CONNECT_SEND_REASSOC
+ Send Reassoc frame while connecting, otherwise send
+ assoc frames
+ = 0x0004 CONNECT_IGNORE_WPAx_GROUP_CIPHER
+ Ignore WPAx group cipher for WPA/WPA2
+ = 0x0008 CONNECT_PROFILE_MATCH_DONE
+ Ignore any profile check
+ = 0x0010 CONNECT_IGNORE_AAC_BEACON
+ Ignore the admission control information in the
+ beacon
+ ... CONNECT_CMD, continued
+ Command Values
+ typedef enum {
+ INFRA_NETWORK = 0x01,
+ ADHOC_NETWORK = 0x02,
+ ADHOC_CREATOR = 0x04,
+ } NETWORK_TYPE;
+
+ typedef enum {
+ OPEN_AUTH = 0x01,
+ SHARED_AUTH = 0x02,
+ LEAP_AUTH = 0x04,
+ } DOT11_AUTH_MODE;
+ typedef enum {
+ NONE_AUTH = 0x01,
+ WPA_AUTH = 0x02,
+ WPA_PSK_AUTH = 0x03,
+ WPA2_AUTH = 0x04,
+ WPA2_PSK_AUTH = 0x05,
+ WPA_AUTH_CCKM = 0x06,
+ WPA2_AUTH_CCKM = 0x07,
+ } AUTH_MODE;
+ typedef enum {
+ NONE_CRYPT = 0x01,
+ WEP_CRYPT = 0x02,
+ TKIP_CRYPT = 0x03,
+ AES_CRYPT = 0x04,
+ } CRYPTO_TYPE;
+ typedef enum {
+ CONNECT_ASSOC_POLICY_USER = 0x0001,
+ CONNECT_SEND_REASSOC = 0x0002,
+ CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004,
+ CONNECT_PROFILE_MATCH_DONE = 0x0008,
+ CONNECT_IGNORE_AAC_BEACON = 0x0010,
+ } WMI_CONNECT_CTRL_FLAGS_BITS;
+
+ pairwiseCryptoLen and groupCryptoLen are valid when the respective
+ CryptoTypesis WEP_CRYPT, otherwise this value should be 0. This is the length in
+ bytes.
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ CREATE_PSTREAM
+
+Synopsis
+ The host uses this command to create a new prioritized data endpoint between the
+ host and the AR6000 device that carries a prioritized stream of data. If the AP that the
+ device connects to requires TSPEC stream establishment, the device requests the
+ corresponding TSPEC with the AP. The maximum and minimum service interval
+ ranges from 0 <20> 0x7FFFFFFF (ms), where 0 = disabled. The device does not send a
+ reply event for this command, as it is always assumed the command has succeeded.
+ An AP admission control response comes to the host via a WMI_CAC_INDICATION
+ event, once the response for the ADDTS frame comes.
+
+ Examples of cases where reassociation is generated (when WMM) and cases where
+ ADDTS is generated (when WMM and enabling ACM) are when:
+ Changing UAPSD flags in WMM mode, reassociation is generated
+ Changing the interval of sending auto QoS Null frame in WMM mode;
+ reassociation is not generated
+ Issuing a command with same previous parameters in WMM mode and enabling
+ ACM, an ADDTS request is generated
+ Changing the interval of a QoS null frame sending in WMM mode and enabling
+ ACM, an ADDTS request is generated
+ Issuing the command in disconnected state, reassociation or ADDTS is not
+ generated but the parameters are available after (re)association
+
+Command
+ --createqos <user priority> <direction> <traffic class>
+<trafficType> <voice PS capability> <min service interval> <max
+service interval> <inactivity interval> <suspension interval>
+<service start time> <tsid> <nominal MSDU> <max MSDU> <min data
+rate> <mean data rate> <peak data rate> <max burst size> <delay
+bound> <min phy rate> <sba> <medium time> where:
+
+ <user priority>
+ 802.1D user priority range (0<>7)
+ <direction>
+ = 0 Tx (uplink) traffic
+ = 1 Rx (downlink) traffic
+ = 2 Bi-directional traffic
+ <traffic class>
+ = 1 BK
+ = 2 VI
+ = 3 VO
+ <trafficType>
+ = 0 Aperiodic
+ = 1 Periodic
+ <voice PS capability>
+ Specifies whether the voice power save mechanism
+ (APSD if AP supports it or legacy/simulated APSD
+ [using PS-Poll]) should be used
+ = 0 Disable voice power save for traffic class
+ = 1 Enable APSD voice power save for traffic class
+ = 2 Enable voice power save for all traffic classes
+ <min service interval>
+ (In ms)
+ <max service interval>
+ Inactivity interval (in ms) (0 = Infinite)
+ <suspension interval>
+ (In ms)
+ <service start time>
+ Service start time
+ <tsid>
+ TSID range (0<>15)
+ <nominal MSDU>
+ Nominal MAC SDU size
+ <max MSDU>
+ Maximum MAC SDU size
+ <min data rate>
+ Minimum data rate (in bps)
+ <mean data rate>
+ Mean data rate (in bps)
+ <peak data rate>
+ Peak data rate (in bps)
+ <max burst size>
+ Maximum burst size (in bps)
+ <delay bound>
+ Delay bound
+ <min phy rate>
+ Minimum PHY rate (in bps)
+ <sba>
+ Surplus bandwidth allowance
+ <medium time>
+ Medium time in TU of 32-ms periods per sec
+ ... CREATE_PSTREAM (continued)
+
+Command Parameters
+ UINT8 trafficClass TRAFFIC_CLASS value
+ UINT8 traffic
+ Direction
+ DIR_TYPE value
+ UINT8 rxQueueNum
+ AR6000 device mailbox index (2 or 3)
+ corresponding to the endpoint the host
+ wishes to use to receive packets for the
+ prioritized stream
+ UINT8 trafficType TRAFFIC_TYPE value
+ UINT8 voicePS
+Capability
+ VOICEPS_CAP_TYPE value
+ UINT8 tsid Traffic stream ID
+ UINT8 userPriority 802.1D user priority
+ UINT16 nominalMSDU Nominal MSDU in octets
+ UINT16 maxMSDU Maximum MSDU in octets
+ UINT32 minServiceInt Minimum service interval: the min.
+ period of traffic specified (in ms)
+ UINT32 maxServiceInt Maximum service interval: the max.
+ period of traffic specified (in ms)
+ UINT32 inactivityInt Indicates how many ms an established
+ stream is inactive before the prioritized
+ data endpoint is taken down and the
+ corresponding T-SPEC deleted
+ UINT32 suspensionInt Suspension interval (in ms)
+ UINT32 service StartTime Service start time
+ UINT32 minDataRate Minimum data rate (in bps)
+ UINT32 meanDataRate Mean data rate (in bps)
+ UINT32 peakDataRate Peak data rate (in bps)
+ UINT32 maxBurstSize
+ UINT32 delayBound
+ UINT32 minPhyRate Minimum PHY rate for TSPEC (in bps)
+ UINT32 sba Surplus bandwidth allowance
+ UINT32 mediumTime Medium TSPEC time (in units of 32 ms)
+Command Values
+ {
+ WMM_AC_BE = 0 Best Effort
+ WMM_AC_BK = 1 Background
+ WMM_AC_VI = 2 Video
+ WMM_AC_VO = 3 Voice
+ All other values reserved
+ } TRAFFIC_CLASS
+ {
+ UPLINK_TRAFFIC = 0 From the AR6000 device to the AP
+ DOWNLINK_TRAFFIC = 1 From the AP to the AR6000 device
+ BIDIR_TRAFFIC = 2 Bi-directional traffic
+ All other values reserved
+ } DIR_TYPE
+ {
+ DISABLE_FOR_THIS_AC = 0
+ ENABLE_FOR_THIS_AC = 1
+ ENABLE_FOR_ALL_AC = 2
+ All other values reserved
+ } VOICEPS_CAP_TYPE
+
+ ... CREATE_PSTREAM (continued)
+
+
+ VI BE BK Supported, Y/N?
+ 0 0 0 0 Y
+ 0 0 0 1 Y
+ 0 0 1 0 N
+ 0 0 1 1 N
+ 0 1 0 0 Y
+ 0 1 0 1 Y
+ 0 1 1 0 N
+ 0 1 1 1 N
+ 1 0 0 0 Y
+ 1 0 0 1 Y
+ 1 0 1 0 N
+ 1 1 0 0 N
+ 1 1 0 1 Y
+ 1 1 0 0 N
+ 1 1 1 0 N
+ 1 1 1 1 Y
+
+Reset Value
+ No pstream is present after reset; each of the BE, BK, VI,VO pstreams must be created
+ (either implicitly by data flow or explicitly by user)
+
+Restrictions
+ This command can only be issued when the device is in the CONNECTED state. If
+ the device receives the command while in DISCONNECTED state, it replies with a
+ failure indication. At most four prioritized data endpoints can be created, one for
+ each AC.
+
+See Also
+ <20>DELETE_PSTREAM<41>
+=====================================================================
+
+Name
+ DELETE_BAD_AP
+
+Synopsis
+ The host uses this command to clear a particular entry in the bad AP table
+
+Command
+ wmiconfig eth1 --rmAP [--num=<index>] // used to clear a badAP
+ entry. num is index from 0-3
+
+Command Parameters
+ UINT8 badApIndex Index [0...n] that identifies the entry in the bad
+ AP table to delete
+
+Command Values
+ badApIndex = 0, 1, 2, 3
+ Entry in the bad AP table
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+See Also
+ <20>ADD_BAD_AP<41>
+
+=====================================================================
+
+
+Name
+ DELETE_CIPHER_KEY
+
+Synopsis
+ The host uses this command to delete a key that was previously added with the
+ <20>ADD_CIPHER_KEY<45> command.
+
+Command
+ TBD
+
+Command Parameters
+ UINT8 keyIndex Index (0...3) of the key to be deleted
+
+Command Values
+ keyIndex = 0, 1,2, 3 Key to delete
+
+Reset Value
+ None
+
+Restrictions
+ The host should not delete a key that is currently in use by the AR6000.
+
+See Also
+ <20>ADD_CIPHER_KEY<45>
+
+=====================================================================
+
+Name
+ DELETE_PSTREAM
+
+Synopsis
+ The host uses this command to delete a prioritized data endpoint created by a
+ previous <20>CREATE_PSTREAM<41> command
+
+Command
+ --deleteqos <trafficClass> <tsid>, where:
+
+ <traffic class>
+ = 0 BE
+ = 1 BK
+ = 2 VI
+ = 3 VO
+ <tsid>
+ The TSpec ID; use the -qosqueue option
+ to get the active TSpec IDs for each traffic class
+
+Command Parameters
+ A_UINT8 trafficClass Indicate the traffic class of the stream
+ being deleted
+
+Command Values
+ {
+ WMM_AC_BE = 0 Best effort
+ WMM_AC_BK = 1 Background
+ WMM_AC_VI = 2 Video
+ WMM_AC_VO = 3 Voice
+ } TRAFFIC CLASS
+
+ 0-15 for TSID
+
+Reply Values
+ N/A
+
+Restrictions
+ This command should only be issued after a <20>CREATE_PSTREAM<41> command has
+ successfully created a prioritized stream
+
+See Also
+ <20>CREATE_PSTREAM<41>
+
+=====================================================================
+
+
+Name
+ DELETE_WOW_PATTERN
+
+Synopsis
+ The host uses this command to remove a pre-specified pattern from the
+ WoW pattern list.
+
+Command
+ wmiconfig <20>delwowpattern <list-id> <pattern-id>
+
+Command Parameters
+ A_UINT8 filter_list_id ID of the list that contains the WoW filter
+ pattern to delete
+ A_UINT8 filter_id ID of the WoW filter pattern to delete
+
+Reply Parameters
+ None
+
+
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+See Also
+ <20>ADD_WOW_PATTERN<52>
+
+=====================================================================
+
+
+Name
+ EXTENSION
+
+Synopsis
+ The WMI message interface is used mostly for wireless control messages to a wireless
+ module applicable to wireless module management regardless of the target platform
+ implementation. However, some commands only peripherally related to wireless
+ management are desired during operation. These wireless extension commands may
+ be platform-specific or implementation-dependent.
+
+Command
+ N/A
+
+Command Parameters
+ Command-specific
+
+Command Values
+ Command-specific
+
+Reply Parameters
+ Command-specific
+
+Reset Values
+ None defined
+
+Restrictions
+ None defined
+
+=====================================================================
+
+
+Name
+ GET_BIT_RATE
+
+Synopsis
+ Used by the host to obtain the rate most recently used by the AR6000 device
+
+Command
+ wmiconfig eth1 --getfixrates
+
+Command Parameters
+ None
+
+
+
+Reply Parameters
+ INT8
+ rateIndex
+ See the <20>SET_BIT_RATE<54> command
+
+Reset Values
+ None
+
+Restrictions
+ This command should only be used during development/debug; it is not intended
+for use in production. It is only valid when the device is in the CONNECTED state
+
+See Also
+ <20>SET_BIT_RATE<54>
+
+=====================================================================
+
+
+Name
+ GET_CHANNEL_LIST
+
+Synopsis
+ Used by the host uses to retrieve the list of channels that can be used by the device
+ while in the current wireless mode and in the current regulatory domain.
+
+Command
+ TBD
+
+Command Parameters
+ None
+
+Reply Parameters
+ UINT8 reserved Reserved
+ UINT8 numberOfChannels Number of channels the reply contains
+ UINT16 channelList[numberOfChannels] Array of channel frequencies (in MHz)
+
+Reset Values
+ None defined
+
+Restrictions
+ The maximum number of channels that can be reported are 32
+
+=====================================================================
+
+
+Name
+ GET_FIXRATES
+
+Synopsis
+ Clears the current calculated RSSI and SNR value. RSSI and SNR are reported by
+ running-average value. This command will clear the history and have a fresh start for
+ the running-average mechanism.
+
+Synopsis
+ This returns rate-mask set via WMI_SET_FIXRATES to retrieve the current fixed rate
+ that the AR6001 or AR6001 is using. See <20>SET_FIXRATES<45>.
+
+Command
+ wmiconfig eth1 --getfixrates
+
+Command Parameters
+ A_UINT16 fixRateMask; Note: if this command is used prior to
+ using WMI_SET_FIXRATES, AR6000
+ returns 0xffff as fixRateMask, indicating
+ all the rates are enabled
+
+Reply Parameters
+ None
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+See Also
+ <20>SET_FIXRATES<45>
+
+=====================================================================
+
+
+
+Name
+ GET_PMKID_LIST_CMD
+
+Synopsis
+ Retrieves the list of PMKIDs on the firmware. The
+ WMI_GET_PMKID_LIST_EVENT is generated by the firmware.
+
+Command
+ TBD
+
+Command Parameters
+
+Reset Values
+ None
+
+Restrictions
+ None
+
+See Also
+ SET_PMKID_LIST_CMD GET_PMKID_LIST_EVENT
+
+=====================================================================
+
+
+Name
+ GET_ROAM_TBL
+
+Synopsis
+ Retrieve the roaming table maintained on the target. The response is reported
+ asynchronously through the ROAM_TBL_EVENT.
+
+Command
+ wmiconfig --getroamtable <roamctrl> <info>
+
+Command Parameters
+ A_UINT8 roamCtrlType;
+ A_UINT16 roamMode
+ A_UINT16 numEntries
+ WMI_BSS_ROAM_INFO bssRoamInfo[1]
+
+Reply Value
+ Reported asynchronously through the ROAM_TBL_EVENT
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+See Also
+ SET_KEEPALIVE
+
+=====================================================================
+
+
+Name
+ GET_TARGET_STATS
+
+Synopsis
+ The host uses this command to request that the target send the statistics that it
+ maintains. The statistics obtained from the target are accrued in the host every time
+ the GET_TARGET_STATS command is issued. The --clearStats option is added to
+ clear the target statistics maintained in the host.
+
+Command
+ wmiconfig --getTargetStats --clearStats
+
+Command Parameters
+ TARGET_STATS targetStats
+ WMI_TARGET_STATS
+ UINT8 clearStats
+
+
+Reply Value
+ RSSI return value (0<>100)
+
+Reset Values
+ All statistics are cleared (zeroed)
+
+Restrictions
+ The --getTargetStats option must be used; the --clearStats option is also available also
+
+
+=====================================================================
+
+Name
+ GET_TX_PWR
+
+Synopsis
+ The host uses this command to retrieve the current Tx power level
+
+Command
+ wmiconfig -i eth1 --getpower
+
+Command Parameters
+ None
+
+Reply Parameters
+ UINT16 dbM The current Tx power level specified in dbM
+
+Reset Values
+ The maximum permitted by the regulatory domain
+
+Restrictions
+ None
+
+See Also
+ <20>SET_TX_PWR<57>
+
+=====================================================================
+
+
+Name
+ GET_WOW_LIST
+
+Synopsis
+ The host uses this command to retrieve the current list of WoW patterns.
+
+Command
+ wmiconfig <20>getwowlist <list-id>
+
+Command Parameters
+ A_UINT8 filter_list_id ID of the list of WoW patterns to retrieve
+
+Reply Value(s)
+ A_UINT16 num_filters Number of WoW patterns contained in the list
+ A_UINT8 wow_mode Current mode of WoW (enabled or disabled)
+ A_UINT8 host_mode Current host mode (asleep or awake)
+ WOW_FILTER wow_filters[1]
+ Contents of the WoW filter pattern list
+ (contains mask, pattern, offset and size
+ information for each of the patterns)
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+See Also
+ <20>SET_WSC_STATUS<55>
+
+=====================================================================
+
+
+Name
+ LQ_THRESHOLD_PARAMS
+
+Synopsis
+ Sets Link Quality thresholds, the sampling will happen at every unicast data frame
+ Tx if a certain threshold is met, and the corresponding event will be sent to the host.
+
+Command
+ --lqThreshold <enable> <upper_threshold_1> ...
+ <upper_threshold_4> <lower_threshold_1> ... <lower_threshold_4>
+
+Command Parameters
+ <enable> = 0 Disable link quality sampling
+ = 1 Enable link quality sampling
+ <upper_threshold_x> Above thresholds (value in [0,100]), in
+ ascending order
+ <lower_threshold_x> Below thresholds (value in [0,100]), in
+ ascending order
+
+Command Values
+ See command parameters
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ OPT_TX_FRAME
+
+Synopsis
+ Special feature, sends a special frame.
+
+Command
+ wmiconfig --sendframe <frmType> <dstaddr> <bssid> <optIEDatalen>
+ <optIEData>
+
+Command Parameters
+ {
+ A_UINT16 optIEDataLen;
+ A_UINT8 frmType;
+ A_UINT8 dstAddr[ATH_MAC_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT8 optIEData[1];
+ } WMI_OPT_TX_FRAME_CMD;
+
+Command Values
+ <frmtype> = 1 Probe request frame
+ = 2 Probe response frame
+ = 3 CPPP start
+ = 4 CPPP stop
+
+Reset Value
+ None defined
+
+Restrictions
+ Send a special frame only when special mode is on.
+
+=====================================================================
+
+
+Name
+ RECONNECT
+
+Synopsis
+ This command requests a reconnection to a BSS to which the AR6000 device was
+ formerly connected
+
+Command
+ TBD
+
+Command Parameters
+ UINT16 channel Provides a hint as to which channel was
+ used for a previous connection
+ UINT8 bssid[6] If set, indicates which BSSID to connect to
+
+Command Values
+ None
+
+Reset Values
+ None
+
+Restrictions
+ None
+
+See Also
+ <20>CONNECT_CMD<4D>
+
+=====================================================================
+
+
+Name
+ RSSI_THRESHOLD_PARAMS
+
+Synopsis
+ Configures how the AR6000 device monitors and reports signal strength (RSSI) of the
+ connected BSS, which is used as a link quality metric. The four RSSI threshold sets (in
+ dbM) of the host specification divide the signal strength range into six segments.
+ When signal strength increases or decreases across one of the boundaries, an
+ RSSI_THRESHOLD event is signaled to the host. The host may then choose to take
+ action (such as influencing roaming).
+
+Command
+ wmiconfig eth1 --rssiThreshold <weight> <pollTime>
+ <above_threshold_val_1> ... <above_threshold_tag_6>
+ <above_threshold_val_6>
+ <below_threshold_tag_1> <below_threshold_val_1> ...
+ <below_threshold_tag_6> <below_threshold_val_6>
+
+Command Parameters
+ UINT8 weight Range in [1, 16] used to calculate average RSSI
+ UINT32 pollTime RSSI (signal strength) sampling frequency in
+ seconds (if pollTime = 0, single strength
+ sampling is disabled)
+ USER_RSS__THOLD tholds[12] Thresholds (6 x 2)
+
+Command Values
+ None defined
+
+Reset Values
+ pollTime is 0, and sampling is disabled
+
+Restrictions
+ Can only be issued if the AR6000 device is connected
+
+
+=====================================================================
+
+Name
+ SCAN_PARAMS
+
+Synopsis
+ The minact parameter determines the minimum active channel dwell time, within
+ which if the STA receives any beacon, it remains on that channel until the maxact
+ channel dwell time. If the STA does not receive a beacon within the minact dwell
+ time, it switches to scan the next channel.
+
+Command
+ wmiconfig -scan -minact=<ms> --maxact=<ms>
+
+Command Parameters
+ UINT16 maxact Channel dwell time (in ms), default = 0
+ UINT16 minact Channel dwell time (in ms), default = 105
+
+Command Values
+ See channel parameters
+
+Reset Values
+ None defined
+
+Restrictions
+ The minact value should be greater than 0; maxact should be between 5<>65535 ms
+ and greater than minact
+
+=====================================================================
+
+
+Name
+ SET_ACCESS_PARAMS
+
+Synopsis
+ Allows the host to set access parameters for the wireless network. A thorough
+ understanding of IEEE 802.11 is required to properly manipulate these parameters.
+
+Command
+ wmiconfig eth1 --acparams --txop <limit> --cwmin <0-15>
+ --cwmax <0-15> --aifsn<0-15>
+
+Command Parameters
+ UINT16 txop The maximum time (expressed in units of
+ 32 ms) the device can spend transmitting
+ after acquiring the right to transmit
+ UINT8 eCWmin Minimum contention window
+ UINT8 eCWmax Maximum contention window
+ UINT8 aifsn The arbitration inter-frame space number
+
+Command Values
+ None
+
+Reset Values
+ Reasonable defaults that vary, between endpoints (prioritized streams)
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_ADHOC_BSSID
+
+Synopsis
+ Allows the host to set the BSSID for an ad hoc network. If a network with this BSSID
+ is not found, the target creates an ad hoc network with this BSSID after the connect
+ WMI command is triggered (e.g., by the SIOCSIWESSID IOCTL).
+
+Command
+ wmiconfig eth1 --adhocbssid <bssid>
+
+Command Parameters
+ A_UINT8 bssid[ATH_MAC_LEN] BSSID is specified in xx:xx:xx:xx:xx:xx format
+
+Command Values
+ None
+
+Reset Values
+ None
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_AKMP_PARAMS
+
+Synopsis
+ Enables or disables multi PMKID mode.
+
+Command
+ wmiconfig eth1 --setakmp --multipmkid=<on/off>
+
+Command Parameters
+ typedef struct {
+ A_UINT32 akmpInfo;
+ } WMI_SET_AKMP_PARAMS_CMD;
+
+Command Values
+ akmpInfo;
+ bit[0] = 0
+ MultiPMKID mode is disabled and PMKIDs that
+ were set using the WMI_SET_PMKID_CMD are
+ used in the [Re]AssocRequest frame.
+ bit[0] = 1
+ MultiPMKID mode is enabled and PMKIDs issued
+ by the WMI_SET_PMKID_LIST_CMD are used in
+ the next [Re]AssocRequest sent to the AP.
+
+Reset Values
+ MultiPMKID mode is disabled
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_APPIE
+
+Synopsis
+ Add an application-specified IE to a management frame. The maximum length is
+ 76 bytes. Including the length and the element ID, this translates to 78 bytes.
+
+Command
+ wmiconfig --setappie <frame> <IE>, where:
+
+ frame
+ One of beacon, probe, respon, assoc
+
+ IE
+ A hex string beginning with DD (if = 0, no
+ IE is sent in the management frame)
+
+Command Parameters
+ mgmtFrmType;
+ A WMI_MGMT_FRAME_TYPE
+
+ ieLen;
+ Length of the IE to add to the GMT frame
+
+Command Values
+ None
+
+Reset Value
+ None defined
+
+Restrictions
+ Supported only for the probe request and association request management frame
+types. Also, only one IE can be added per management frame type.
+
+=====================================================================
+
+
+Name
+ SET_ASSOC_INFO
+
+Synopsis
+ The host uses this command to specify any information elements (IEs) it wishes the
+ AR6000 device to add to all future association and reassociation requests. IEs must be
+ correct and are used as is by the device. IEs specified through this command are
+ cleared with a DISCONNECT.
+
+Command
+ wmiconfig eth1 --setAssocIe <IE>
+
+Command Parameters
+ UINT8 ieType Used directly in 802.11 frames
+ UINT8 bufferSize Size of assocInfo (in bytes) ranging from
+ 0<>240. If = 0, previously set IEs are cleared.
+ UINT8 assocInfo[bufferSize] Used directly in 802.11 frames
+
+Command Values
+ None
+
+Reset Values
+ IEs are cleared
+
+Restrictions
+ This command can only be issued in the DISCONNECTED state
+
+=====================================================================
+
+
+Name
+ SET_AUTHMODE
+
+Synopsis
+ Sets the 802.11 authentication mode of reconnection
+
+Command
+ wmiconfig eth1 --setauthmode <mode>
+
+Command Parameters
+ UINT8 mode
+
+Command Values
+ mode = 0x00 Proceed with authentication during reconnect
+ = 0x01 Do not proceed with authentication during reconnect
+
+Reset Values
+ Authentication
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_BEACON_INT
+
+Synopsis
+ Sets the beacon interval for an ad hoc network. Beacon interval selection may have an
+ impact on power savings. To some degree, a longer interval reduces power
+ consumption but also decreases throughput. A thorough understanding of IEEE
+ 802.11 ad hoc networks is required to use this command effectively.
+
+Command
+ wmiconfig eth1 --ibssconintv
+
+Command Parameters
+ UINT16 beaconInterval Specifies the beacon interval in TU units (1024 ms)
+
+Command Values
+ None
+
+Reset Values
+ The default beacon interval is 100 TUs (102.4 ms)
+
+Restrictions
+ This command can only be issued before the AR6000 device starts an ad hoc network
+
+See Also
+ <20>SET_IBSS_PM_CAPS<50>
+
+=====================================================================
+
+
+Name
+ SET_BIT_RATE
+
+Synopsis
+ The host uses this command to set the AR6000 device to a specific fixed rate.
+
+Command
+ wmiconfig eth1 --setfixrates <rate_0> ... <rate_n>
+
+Command Parameters
+ INT8 rateIndex
+ A WMI_BIT_RATE value
+ {
+ RATE_AUTO = -1
+ RATE_1Mb = 0
+ RATE_2Mb = 1
+ RATE_5_5M = 2
+ RATE_11Mb = 3
+ RATE_6Mb = 4
+ RATE_9Mb = 5
+ RATE_12Mb = 6
+ RATE_18Mb = 7
+ RATE_24Mb = 8
+ RATE_36Mb = 9
+ RATE_48Mb = 10
+ RATE_54Mb = 11
+ } WMI_BIT_RATE
+
+
+Command Values
+ See command parameters
+
+Reset Values
+ The dynamic rate is determined by the AR6000 device
+
+Restrictions
+ This command is intended for use only during development/debug; it is not
+intended for use in production
+
+See Also
+ <20>GET_BIT_RATE<54>
+
+=====================================================================
+
+
+Name
+ SET_BMISS_TIME
+
+Synopsis
+ This command sets the beacon miss (BMISS) time, which the AR6000 hardware use
+ to recognize missed beacons. When an excessive number (15) of consecutive beacons
+ are missed, the AR6000 consider switching to a different BSS. The time can be
+ specified in number of beacons or in TUs.
+
+Command(s)
+ wmiconfig eth1 --setbmissbeacons=<val>
+ wmiconfig eth1 --setbmisstime=<val>
+
+Command Parameters
+ UINT16 bmissTime Specifies the beacon miss time
+ [1000...5000] in TUs (1024 ms)
+ UINT16 bmissbeacons Specifies the number of beacons [5...50]
+
+Command Values
+ None
+
+Reset Values
+ bmissTime is 1500 TUs (1536 ms)
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_BSS_FILTER
+
+Synopsis
+ The host uses this to inform the AR6000 device of the types of networks about which
+ it wants to receive information from the <20>BSSINFO<46> event. As the device performs
+ either foreground or background scans, it applies the filter and sends <20>BSSINFO<46>
+ events only for the networks that pass the filter. If any of the bssFilter or the ieMask
+ filter matches, a BSS Info is sent to the host. The ieMask currently is used as a match
+ for the IEs in the beacons, probe reponses and channel switch action management
+ frame. See also <20>Scan and Roam<61> on page C-1.
+
+ The BSS filter command has been enhanced to support IE based filtering. The IEs can
+ be specified as a bitmask through this command using this enum.
+
+Command
+ wmiconfig eth1 <20>filter = <filter> --ieMask 0x<mask>
+
+Command Parameters
+ UINT8 BssFilter
+
+ Command Values
+ typedef struct {
+ A_UINT8 bssFilter; See WMI_BSS_FILTER
+ A_UINT32 ieMask;
+ } __ATTRIB_PACK WMI_BSS_FILTER_CMD;
+
+ The ieMask can take this combination of values:
+
+ enum {
+ BSS_ELEMID_CHANSWITCH = 0x01
+ BSS_ELEMID_ATHEROS = 0x02,
+ }
+
+Reply Value
+ None
+
+Reset Value
+ BssFilter = NONE_BSS_FILTER (0)
+
+Restrictions
+ None
+
+See Also
+ <20>CONNECT_CMD<4D>
+
+=====================================================================
+
+
+Name
+ SET_BT_PARAMS
+
+Synopsis
+ This command is used to set the status of a Bluetooth stream or set Bluetooth
+ coexistence register parameters. The stream may be an SCO or an A2DP stream and
+ its status can be started/stopped/suspended/resumed.
+
+Command
+ wmiconfig <20>setBTparams <paramType> <params>
+
+Command Parameters
+ struct {
+ union {
+ BT_PARAMS_SCO scoParams;
+ BT_PARAMS_A2DP a2dpParams;
+ BT_PARAMS_MISC miscParams;
+ BT_COEX_REGS regs;
+ } info;
+ A_UINT8 paramType;
+ struct {
+ A_UINT8 noSCOPkts; Number of SCO packets between consecutive PS-POLLs
+ A_UINT8 pspollTimeout;
+ A_UINT8 stompbt;
+ } BT_PARAMS_SCO;
+ struct {
+ A2DP BT stream parameters
+ A_UINT32 period;
+ A_UINT32 dutycycle;
+ A_UINT8 stompbt;
+ } BT_PARAMS_A2DP;
+ struct {
+ union {
+ WLAN_PROTECT_POLICY_TYPE protectParams;
+ A_UINT16 wlanCtrlFlags;
+ }info;
+ A_UINT8 paramType;
+ } BT_PARAMS_MISC;
+ struct {
+ BT coexistence registers values
+ A_UINT32 mode; Coexistence mode
+ A_UINT32 scoWghts; WLAN and BT weights
+ A_UINT32 a2dpWghts;
+ A_UINT32 genWghts;
+ A_UINT32 mode2; Coexistence mode2
+ A_UINT8 setVal;
+ } BT_COEX_REGS;
+
+Command Values
+ None defined
+
+Reset Value
+ None
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_BT_STATUS
+
+Synopsis
+ Sets the status of a Bluetooth stream. The stream may be a SCO or an A2DP stream
+ and its status can be started/stopped/suspended/resumed.
+
+Command
+ wmiconfig <20>setBTstatus <streamType> <status>
+
+Command Parameters
+ {
+ A_UINT8 streamType; Stream type
+ A_UINT8 status; Stream status
+ }WMI_SET_BT_STATUS_CMD;
+
+Command Values
+ {
+ BT_STREAM_UNDEF = 0
+ BT_STREAM_SCO
+ SCO stream
+ BT_STREAM_A2DP
+ A2DP stream
+ BT_STREAM_MAX
+ } BT_STREAM_TYPE;
+
+ {
+ BT_STATUS_UNDEF = 0
+ BT_STATUS_START
+ BT_STATUS_STOP
+ BT_STATUS_RESUME
+ BT_STATUS_SUSPEND
+ BT_STATUS_MAX
+ } BT_STREAM_STATUS;
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_CHANNEL_PARAMETERS
+
+Synopsis
+ Configures various WLAN parameters related to channels, sets the wireless mode,
+ and can restrict the AR6000 device to a subset of available channels. The list of
+ available channels varies depending on the wireless mode and the regulatory
+ domain. The device never operates on a channel outside of its regulatory domain. The
+ device starts to scan the list of channels right after this command.
+
+Command
+ wmiconfig eth1 --wmode <mode> <list>
+
+Command Parameters
+ UINT8 phyMode See Values below.
+ UINT8 numberOfChannels
+ Number of channels in the channel array that
+ follows. If = 0, then the device uses all of the
+ channels permitted by the regulatory domain
+ and by the specified phyMode.
+ UINT16 channel[numberOfChannels]
+ Array listing the subset of channels (expressed
+ as frequencies in MHz) the host wants the
+ device to use. Any channel not permitted by
+ the specified phyMode or by the specified
+ regulatory domain is ignored by the device.
+
+Command Values
+ phyMode = {
+ Wireless mode
+ 11a = 0x01
+ 11g = 0x02
+ 11ag = 0x03
+ 11b = 0x04
+ 11g only = 0x05
+ }
+
+Reset Values
+ phyMode
+ 11ag
+ 802.11a/g modules
+ 11g
+ 802.11g module
+ channels
+ Defaults to all channels permitted by the
+ current regulatory domain.
+
+Restrictions
+ This command, if issued, should be issued soon after reset and prior to the first
+ connection. This command should only be issued in the DISCONNECTED state.
+
+=====================================================================
+
+
+Name
+ SET_DISC_TIMEOUT
+
+Synopsis
+ The host uses this command to configure the amount of time that the AR6000 should
+ spend when it attempts to reestablish a connection after losing link with its current
+ BSS. If this time limit is exceeded, the AR6000 send a <20>DISCONNECT<43> event. After
+ sending the <20>DISCONNECT<43> event the AR6000 continues to attempt to reestablish a
+ connection, but they do so at the interval corresponding to a foreground scan as
+ established by the <20>SET_SCAN_PARAMS<4D> command.
+
+ A timeout value of 0 indicates that the AR6000 will disable all autonomous roaming,
+ so that the AR6000 will not perform any scans after sending a <20>DISCONNECT<43>
+ event to the host. The state is maintained until a shutdown or host sets different
+ timeout value from 0.
+
+Command
+ wmiconfig eth1 --disc=<timeout in seconds>
+
+Command Parameters
+ UINT8 disconnectTimeout
+ Specifies the time limit (in seconds) after
+ which a failure to reestablish a connection
+ results in a <20>DISCONNECT<43> event
+
+Command Values
+ None
+
+Reset Values
+ disconnectTimeout is 10 seconds
+
+Restrictions
+ This command can only be issued while in a DISCONNECTED state
+
+=====================================================================
+
+
+Name
+ SET_FIXRATES
+
+Synopsis
+ By default, the AR6000 device uses all PHY rates based on mode of operation. If the
+ host application requires the device to use subset of supported rates, it can set those
+ rates with this command. In 802.11g mode, the AR6000 device takes the entire
+ 802.11g basic rate set and the rates specified with this command and uses it as the
+ supported rate set.
+
+ This rate set is advertised in the probe request and the assoc/re-assoc request as
+ supported rates. Upon successful association, the device modifies the rate set pool
+ using the: intersection of AP-supported rates with the union of the 802.11g basic rate
+ set and rates set using this command. The device picks transmission rates from this
+ pool based on a rate control algorithm.
+
+Command
+ TBD
+
+Command Parameters
+ A_UINT16 fixRateMask;
+ The individual bit is an index for rate table,
+ and setting the that index to 1 would set that
+ corresponding rate. E.g., fixRateMask = 9
+ (1001) sets 1 Mbps and 11 Mbps.
+
+Command Values
+ None
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+See Also
+ <20>GET_FIXRATES<45>
+
+=====================================================================
+
+
+Name
+ SET_WHAL_PARAM
+
+Synopsis
+ An internal AR6000 command that is used to set certain hardware parameters. The
+ description of this command is in $WORKAREA/include/halapi.h.
+
+Command
+ TBD
+
+Command Parameters
+ ATH_HAL_SETCABTO_CMDID
+ Sets the timeout waiting for the multicast
+ traffic after a DTIM beacon (in TUs).
+
+Command Values
+ None
+
+Reset Value
+ Default = 10 TUs
+
+Restrictions
+ This command should be executed before issuing a connect command.
+
+=====================================================================
+
+
+Name
+ SET_HOST_SLEEP_MODE
+
+Synopsis
+ The host uses this command to set the host mode to asleep or awake. All packets are
+ delivered to the host when the host mode is awake. When host mode is asleep, only if
+ WoW is enabled and the incoming packet matches one of the specified WoW
+ patterns, will the packet be delivered to the host. The host will also be woken up by
+ the target for pattern-matching packets and important events.
+
+Command
+ wmiconfig <20>sethostmode=<asleep/awake>
+
+Command Parameters
+ A_BOOL awake Set the host mode to awake
+ A_BOOL asleep Set the host mode to asleep
+
+Command Values
+ 1 = awake, 0 = asleep
+
+Reset Value
+ None defined (default host mode is awake)
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ SET_IBSS_PM_CAPS
+
+Synopsis
+ Used to support a non-standard power management scheme for an ad hoc wireless
+ network consisting of up to eight stations (STAs) that support this form of power
+ saving (e.g., Atheros-based STAs). A thorough understanding of IEEE 802.11 ad hoc
+ networks is required to use this command effectively.
+
+Command
+ wmiconfig eth1 --ibsspmcaps --ps=<enable/disable>
+ --aw=<ATIM Windows in ms>
+ --ttl=<Time to live in number of beacon periods>
+ --to=<timeout in ms>
+
+Command Parameters
+ UINT8 power_saving
+ = 0
+ The non-standard power saving scheme is
+ disabled and maximum throughput (with no
+ power saving) is obtained.
+
+ = 1
+ Ad hoc power saving scheme is enabled (but
+ throughput may be decreased)
+
+ UINT16 atim_windows
+ Specifies the length (in ms) of the ad hoc traffic
+ indication message (ATIM) windows used in an ad
+ hoc network. All Atheros-based STAs that join the
+ network use this duration ATIM window.
+
+ The duration is communicated between wireless
+ STAs through an IE in beacons and probe responses.
+
+ The host sets atim_windows to control trade-offs
+ between power use and throughput. The value
+ chosen should be based on the beacon interval (see
+ the <20>SET_BEACON_INT<4E> command) on the
+ expected number of STAs in the IBSS, and on the
+ amount of traffic and traffic patterns between STAs.
+
+ UINT16 timeout_value
+ Specifies the timeout (in ms). The value is the same
+ for all ad hoc connections, but tracks separately for
+ each.
+
+ Applicable only for a beacon period and used to
+ derive actual timeout values on the Tx and Rx sides.
+ On the Tx side, the value defines a window during
+ which the STA accepts the frame(s) from the host for a
+ particular connection. Until closed, the window
+ restarts with every frame received from the host. On
+ the Rx side, indicates the time until which the STA
+ continues accepting frames from a particular
+ connection. The value resets with every frame
+ received. The value can be used to determine the
+ trade off between throughput and power.
+ Default = 10 ms
+
+ UINT8 ttl
+ Specifies the value in number of beacon periods. The
+ value is used to set a limit on the time until which a
+ frame is kept alive in the AR6001 before being
+ discarded. Default = 5
+
+Command Values
+ None
+
+Reset Values
+ By default, power_saving is enabled with atim_window = 20 ms
+
+Restrictions
+ Can only be issued before the AR6000 starts an ad hoc network
+
+See Also
+ <20>SET_BEACON_INT<4E>
+
+=====================================================================
+
+
+
+Name
+ SET_LISTEN_INT
+
+Synopsis
+ The host uses this command to request a listen interval, which determines how often
+ the AR6000 device should wake up and listen for traffic. The listen interval can be set
+ by the TUs or by the number of beacons. The device may not be able to comply with
+ the request (e.g., if the beacon interval is greater than the requested listen interval, the
+ device sets the listen interval to the beacon interval). The actual listen interval used
+ by the device is available in the <20>CONNECT<43> event.
+
+Command
+ wmiconfig eth1 --listen=<#of TUs, can range from 15 to 3000>
+
+ --listenbeacons=<#of beacons, can range from 1 to 50>
+
+Command Parameters
+ UINT16 listenInterval
+ Specifies the listen interval in Kms
+ (1024 ms), ranging from 100 to 1000
+
+ UINT16 listenbeacons
+ Specifies the listen interval in beacons,
+ ranging from 1 to 50
+
+Command Values
+ None
+
+Reset Values
+ The device sets the listen interval equal to the beacon interval of the AP it associates
+ to.
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_LPREAMBLE
+
+Synopsis
+ Overrides the short preamble capability of the AR6000 device
+
+Command
+ TBD
+
+Command Parameters
+ WMI_LPREAMBLE_DISABLED
+ The device is short-preamble capable
+
+ WMI_LPREAMBLE_ENABLED
+ The device supports only the long-
+ preamble mode
+
+Command Values
+ None
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ SET_MAX_SP_LEN
+
+Synopsis
+ Set the maximum service period; indicates the number of packets the AR6001 can
+ receive from the AP when triggered
+
+Command
+ wmiconfig eth1 --setMaxSPLength <maxSPLen>
+
+Command Parameters
+ UINT8 maxSPLen
+ An APSD_SP_LEN_TYPE value
+
+Command Values
+ {
+ DELIVER_ALL_PKT = 0x0
+ DELIVER_2_PKT = 0x1
+ DELIVER_4_PKT = 0x2
+ DELIVER_6_PKT = 0x3
+ }APSD_SP_LEN_TYPE
+
+
+Reset Values
+ maxSPLen is DELIVER_ALL_PKT
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_OPT_MODE
+
+Synopsis
+ Special feature, sets the special mode on/off
+
+Command
+ wmiconfig eth1 --mode <mode>
+ Set the optional mode, where mode is special or off
+
+Command Parameters
+ enum {
+ SPECIAL_OFF
+ SPECIAL_ON
+ } OPT_MODE_TYPE;
+
+Command Values
+
+Reset Value
+ Mode = Off
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_PMKID
+
+Synopsis
+ The host uses this command to enable or disable a pairwise master key ID (PMKID)
+ in the AR6000 PMKID cache. The AR6000 clears its PMKID cache on receipt of a
+ DISCONNECT command from the host. Individual entries in the cache might be
+ deleted as the AR6000 detect new APs and decides to remove old ones.
+
+Command
+ wmiconfig eth1 --setbsspmkid --bssid=<aabbccddeeff>
+ --bsspmkid=<pmkid>
+
+Command Parameters
+ UINT8 bssid[6]
+ The MAC address of the AP that the
+ PMKID corresponds to (6 bytes in hex
+ format)
+
+ UINT8 enable
+ Either PMKID_DISABLE (0) to disable
+ the PMKID or PMKID_ENABLE (1) to
+ enable it (16 bytes in hex format)
+
+ UINT8 pmkid[16]
+ Meaningful only if enable is
+ PMKID_ENABLE, when it is the PMKID
+ that the AR6000 should use on the next
+ reassociation with the specified AP
+
+Command Values
+ enable
+ = 0 (disable), 1 (enable)
+ PKMID enabled/disabled
+
+Reset Values
+ None defined
+
+Restrictions
+ Only supported in infrastructure networks
+
+=====================================================================
+
+
+Name
+ SET_PMKID_LIST_CMD
+
+Synopsis
+ Configures the list of PMKIDs on the firmware.
+
+Command
+ wmiconfig --setpmkidlist --numpmkid=<n> --pmkid=<pmkid_1>
+ ... --pmkid=<pmkid_n>
+
+ Where n is the number of pmkids (maximum = 8) and pmkid_i is the ith pmkid (16
+ bytes in hex format)
+
+Command Parameters
+ {
+ A_UINT8 pmkid[WMI_PMKID_LEN];
+ } __ATTRIB_PACK WMI_PMKID;
+
+ {
+ A_UINT32 numPMKID;
+ WMI_PMKID pmkidList[WMI_MAX_PMKID_CACHE];
+ } __ATTRIB_PACK WMI_SET_PMKID_LIST_CMD;
+
+Command Values
+ None
+
+Reset Values
+ None
+
+Restrictions
+ Supported only in infrastructure modes
+
+=====================================================================
+
+
+Name
+ SET_POWER_MODE
+
+Synopsis
+ The host uses this command to provide the AR6000 device with guidelines on the
+ desired trade-off between power utilization and performance.
+
+ In normal power mode, the device enters a sleep state if they have nothing to do,
+ which conserves power but may cost performance as it can take up to 2 ms to
+ resume operation after leaving sleep state.
+
+ In maximum performance mode, the device never enters sleep state, thus no time
+ is spent waking up, resulting in higher power consumption and better
+ performance.
+
+Command
+ TBD
+
+Command Parameters
+ UINT8 powerMode
+ WMI_POWER_MODE value
+ {
+ REC_POWER = 1
+ (Recommended setting) Tries to conserve
+ power without sacrificing performance
+ MAX_PERF_POWER = 2
+ Setting that maximizes performance at
+ the expense of power
+
+ All other values are reserved
+ } WMI_POWER_MODE
+
+Command Values
+ See command parameters
+
+Reset Values
+ powerMode is REC_POWER
+
+Restrictions
+ This command should only be issued in the DISCONNECTED state for the
+ infrastructure network.
+
+ For a PM-disabled ad hoc network, the power mode should remain in
+ MAX_PERF_POWER.
+
+ For a PM-enabled ad hoc network, the device can have REC_POWER or
+ MAX_PERF_POWER set, but either way it must follow the power save ad hoc
+ protocol. The host can change power modes in the CONNECTED state.
+
+ Host changes to the PS setting when the STA is off the home channel take no effect
+ and cause a TARGET_PM_FAIL event.
+
+=====================================================================
+
+
+Name
+ SET_POWER_PARAMS
+
+Synopsis
+ The host uses this command to configure power parameters
+
+Command
+ wmiconfig eth1 --pmparams --it=<ms> --np=<number of PS POLL>
+ --dp=<DTIM policy: ignore/normal/stick>
+
+Command Parameters
+ UINT16 idle_period
+ Length of time (in ms) the AR6000 device
+ remains awake after frame Rx/Tx before going
+ to SLEEP state
+
+ UINT16 pspoll_number
+ The number of PowerSavePoll (PS-poll)
+ messages the device should send before
+ notifying the AP it is awake
+
+ UINT16 dtim_policy
+ A WMI_POWER_PARAMS_CMD value
+
+ {
+ IGNORE_DTIM =1
+ The device does not listen to any content after
+ beacon (CAB) traffic
+ NORMAL_DTIM = 2
+ DTIM period follows the listen interval (e.g., if
+ the listen interval is 4 and the DTIM period is 2,
+ the device wakes up every fourth beacon)
+ STICK_DTIM = 3
+ Device attempt to receive all CAB traffic (e.g., if
+ the DTIM period is 2 and the listen interval is 4,
+ the device wakes up every second beacon)
+ } WMI_POWER_PARAMS_CMD
+
+Command Parameters
+ See command parameters
+
+Reset Values
+ idle_period
+ 200 ms
+
+ pspoll_number
+ = 1
+
+ dtim_policy
+ = NORMAL_DTIM
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_POWERSAVE_PARAMS
+
+Synopsis
+ Set the two AR6000 power save timers (PS-POLL timer and APSD trigger timer) and
+ the two ASPD TIM policies
+
+Command
+ wmiconfig eth1--psparams --psPollTimer=<psPollTimeout in ms>
+ --triggerTimer=<triggerTimeout in ms> --apsdTimPolicy=<ignore/
+ adhere> --simulatedAPSDTimPolicy=<ignore/adhere>
+
+Command Parameters
+ typedef struct {
+ A_UINT16 psPollTimeout;
+ Timeout (in ms) after sending PS-POLL; the
+ AR6000 device sleeps if it does not receive a
+ data packet from the AP
+
+ A_UINT16 triggerTimeout;
+ Timeout (in ms) after sending a trigger; the
+ device sleeps if it does not receive any data
+ or null frame from the AP
+
+ APSD_TIM_POLICY apsdTimPolicy;
+ TIM behavior with queue APSD enabled
+
+ APSD_TIM_POLICY simulatedAPSD
+
+ TimPolicy;
+ TIM behavior with simulated APSD
+ enabled
+
+ typedef enum {
+ IGNORE_TIM_ALL_QUEUES_APSD = 0,
+ PROCESS_TIM_ALL_QUEUES_APSD = 1,
+ IGNORE_TIM_SIMULATED_APSD = 2,
+ POWERSAVE_TIMERS_POLICY = 3,
+ } APSD_TIM_POLICY;
+
+Command Values
+ None
+
+Reset Values
+ psPollTimeout is 50 ms; triggerTimeout is 10 ms;
+ apsdTimPolicy = IGNORE_TIM_ALL_QUEUES_APSD;
+ simulatedAPSDTimPolicy = POWERSAVE_TIMERS_POLICY
+
+Restrictions
+ When this command is used, all parameters must be set; this command does not
+ allow setting only one parameter.
+
+=====================================================================
+
+
+Name
+ SET_PROBED_SSID
+
+Synopsis
+ The host uses this command to provide a list of up to MAX_PROBED_SSID_INDEX
+ (six) SSIDs that the AR6000 device should actively look for. It lists the active SSID
+ table. By default, the device actively looks for only the SSID specified in the
+ <20>CONNECT_CMD<4D> command, and only when the regulatory domain allows active
+ probing. With this command, specified SSIDs are probed for, even if they are hidden.
+
+Command
+ wmiconfig eth1 --ssid=<ssid> [--num=<index>]
+
+Command Parameters
+ {
+ A_UINT8 numSsids
+ A number from 0 to
+ MAX_PROBED_SSID_INDEX indicating
+ the active SSID table entry index for this
+ command (if the specified entry index
+ already has an SSID, the SSID specified in
+ this command replaces it)
+
+ WMI_PROBED_SSID_INFO probedSSID[1]
+ } WMI_PROBED_SSID_CMD
+
+ {
+ A_UINT8 flag
+ WMI_SSID_FLAG indicates the current
+ entry in the active SSID table
+ A_UINT8 ssidLength
+ Length of the specified SSID in bytes.
+ If = 0, the entry corresponding to the
+ index is erased
+ A_UINT8 ssid[32]
+ SSID string actively probed for when
+ permitted by the regulatory domain
+ } WMI_PROBED_SSID_INFO
+
+Command Values
+ WMI_SSID_FLAG
+ {
+ DISABLE_SSID_FLAG = 0
+ Disables entry
+ SPECIFIC_SSID_FLAG = 1
+ Probes specified SSID
+ ANY_SSID_FLAG = 2
+ Probes for any SSID
+ } WMI_SSID_FLAG
+
+Reset Value
+ The entries are unused.
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_REASSOC_MODE
+
+Synopsis
+ Specify whether the disassociated frame should be sent or not upon reassociation.
+
+Command
+ wmiconfig eth1 --setreassocmode <mode>
+
+Command Parameters
+ UINT8 mode
+
+Command Values
+ mode
+ = 0x00
+ Send disassoc to a previously connected AP
+ upon reassociation
+ = 0x01
+ Do not send disassoc to previously connected
+ AP upon reassociation
+
+Reset Values
+ None defined
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ SET_RETRY_LIMITS
+
+Synopsis
+ Allows the host to influence the number of times that the AR6000 device should
+ attempt to send a frame before they give up.
+
+Command
+ wmiconfig --setretrylimits <frameType> <trafficClass> <maxRetries>
+ <enableNotify>
+
+Command Parameters
+ {
+ UINT8 frameType
+ A WMI_FRAMETYPE specifying
+ which type of frame is of interest.
+ UINT8 trafficClass
+ Specifies a traffic class (see
+ <20>CREATE_PSTREAM<41>). This
+ parameter is only significant when
+ frameType = DATA_FRAMETYPE.
+ UINT8 maxRetries
+ Maximum number of times the
+ device attempts to retry a frame Tx,
+ ranging from WMI_MIN_RETRIES
+ (2) to WMI_MAX_RETRIES (15). If
+ the special value 0 is used,
+ maxRetries is set to 15.
+ A_UINT8 enableNotify
+ Notify when enabled
+ } WMI_RETRY_LIMIT_INFO
+
+ {
+ A_UINT8 numEntries
+ WMI_RETRY_LIMIT_INFO retryLimitInfo[1]
+ } WMI_SET_RETRY_LIMITS_CMD
+
+Command Values
+ {
+ MGMT_FRAMETYPE = 0 Management frame
+ CONTROL_FRAMETYPE = 1 Control frame
+ DATA_FRAMETYPE = 2 Data frame
+ } WMI_FRAMETYPE
+
+Reset Values
+ Retries are set to 15
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_ROAM_CTRL
+
+Synopsis
+ Affects how the AR6000 device selects a BSS. The host uses this command to set and
+ enable low RSSI scan parameters. The time period of low RSSI background scan is
+ mentioned in scan period. Low RSSI scan is triggered when the current RSSI
+ threshold (75% of current RSSI) is equal to or less than scan threshold.
+
+ Low RSSI roam is triggered when the current RSSI threshold falls below the roam
+ threshold and roams to a better AP by the end of the scan cycle. During Low RSSI
+ roam, if the STA finds a new AP with an RSSI greater than roam RSSI to floor, during
+ scan, it roams immediately to it instead of waiting for the end of the scan cycle. See
+ also <20>Scan and Roam<61> on page C-1.
+
+Command
+ wmiconfig --roam <roamctrl> <info>, where info is <scan period>
+ <scan threshold> <roam threshold> <roam rssi floor>
+
+Command Parameters
+ A_UINT8 roamCtrlType;
+
+Command Values
+ WMI_FORCE_ROAM = 1
+ Roam to the specified BSSID
+
+ WMI_SET_ROAM_MODE = 2
+ Default, progd bias, no roam
+
+ WMI_SET_HOST_BIAS = 3
+ Set the host bias
+
+ WMI_SET_LOWRSSI_SCAN_PARAMS = 4
+ Info parameters
+
+ A_UINT8 bssid[ATH_MAC_LEN];
+ WMI_FORCE_ROAM
+
+ A_UINT8 roamMode;
+ WMI_SET_ROAM_MODE
+
+ A_UINT8 bssBiasInfo;
+ WMI_SET_HOST_BIAS
+
+ A_UINT16 lowrssi_scan_period;
+ WMI_SET_LOWRSSI_SCAN_PARAMS
+
+ A_INT16
+ lowrssi_scan_threshold;
+ WMI_SET_LOWRSSI_SCAN_PARAMS
+
+ A_INT16 lowrssi_roam_threshold;
+ WMI_SET_LOWRSSI_SCAN_PARAMS
+
+ A_UINT8 roam_rssi_floor;
+ WMI_SET_LOWRSSI_SCAN_PARAMS
+
+Reset Value
+ None defined (default lowrssi scan is disabled. Enabled only when scan period is set.)
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_RTS
+
+Synopsis
+ Decides when RTS should be sent.
+
+Command
+ wmiconfig eth1 --setRTS <pkt length threshold>
+
+Command Parameters
+ A_UINT16
+ threshold;
+ Command parameter threshold in bytes. An RTS is
+ sent if the data length is more than this threshold.
+ The default is to NOT send RTS.
+
+Command Values
+ None
+
+Reset Value
+ Not to send RTS.
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ SET_SCAN_PARAMS
+
+Synopsis
+ The host uses this command to set the AR6000 scan parameters, including the duty
+ cycle for both foreground and background scanning. Foreground scanning takes
+ place when the AR6000 device is not connected, and discovers all available wireless
+ networks to find the best BSS to join. Background scanning takes place when the
+ device is already connected to a network and scans for potential roaming candidates
+ and maintains them in order of best to worst. A second priority of background
+ scanning is to find new wireless networks.
+
+ The device initiates a scan when necessary. For example, a foreground scan is always
+ started on receipt of a <20>CONNECT_CMD<4D> command or when the device cannot find
+ a BSS to connect to. Foreground scanning is disabled by default until receipt of a
+ CONNECT command. Background scanning is enabled by default and occurs every
+ 60 seconds after the device is connected.
+
+ The device implements a binary backoff interval for foreground scanning when it
+ enters the DISCONNECTED state after losing connectivity with an AP or when a
+ CONNECT command is received. The first interval is ForegroundScanStartPeriod,
+ which doubles after each scan until the interval reaches ForegroundScanEndPeriod.
+ If the host terminates a connection with DISCONNECT, the foreground scan period
+ is ForegroundScanEndPeriod. All scan intervals are measured from the time a full
+ scan ends to the time the next full scan starts. The host starts a scan by issuing a
+ <20>START_SCAN<41> command. See also <20>Scan and Roam<61> on page C-1.
+
+Command
+ wmiconfig eth1 --scan --fgstart=<sec> --fgend=<sec> --bg=<sec> --
+ act=<msec> --pas=<msec> --sr=<short scan ratio> --scanctrlflags
+ <connScan> <scanConnected> <activeScan> <reportBSSINFO>
+
+Command Parameters
+ UINT16 fgStartPeriod
+ First interval used by the device when it
+ disconnects from an AP or receives a
+ CONNECT command, specified in seconds (0<>
+ 65535). If = 0, the device uses the reset value.
+ If = 65535, the device disables foreground
+ scanning.
+
+ UINT16 fgEndPeriod
+ The maximum interval the device waits between
+ foreground scans specified in seconds (from
+ ForegroundScanStartPeriod to 65535). If = 0, the
+ device uses the reset value.
+
+ UINT16 bgScanPeriod
+ The period of background scan specified in
+ seconds (0<>65535). By default, it is set to the reset
+ value of 60 seconds. If 0 or 65535 is specified, the
+ device disables background scanning.
+
+ UINT16 maxactChDwellTime
+ The period of time the device stays on a
+ particular channel while active scanning. It is
+ specified in ms (10<31>65535). If the special value of
+ 0 is specified, the device uses the reset value.
+
+ UINT16 PasChDwellTime
+ The period of time the device remains on a
+ particular channel while passive scanning. It is
+ specified in ms (10<31>65535). If the special value of
+ 0 is specified, the device uses the reset value.
+
+ UINT8 shortScanRatio
+ Number of short scans to perform for each
+ long scan.
+
+ UINT8 scanCtrlFlasgs
+
+ UINT16 minactChDwellTime
+ Specified in ms
+
+ UINT32 maxDFSchActTime
+ The maximum time a DFS channel can stay
+ active before being marked passive, specified in
+ ms.
+
+Command Values
+ None
+
+Reset Values
+ ForegroundScanStart
+Period
+ 1 sec
+
+ ForegroundScanEndPeriod
+ 60 sec
+
+ BackgroundScanPeriod
+ 60 sec
+
+ ActiveChannelDwellTime
+ 105 ms
+
+=====================================================================
+
+
+Name
+ SET_TKIP_COUNTERMEASURES
+
+Synopsis
+ The host issues this command to tell the target whether to enable or disable TKIP
+ countermeasures.
+
+Command
+ TBD
+
+Command Parameters
+ UINT8 WMI_TKIP_CM_ENABLE
+ Enables the countermeasures
+
+
+ UINT8 TKIP_CM_DISABLE
+ Disables the countermeasures
+
+Command Values
+ None
+
+Reset Values
+ By default, TKIP MIC reporting is disabled
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_TX_PWR
+
+Synopsis
+ The host uses this command to specify the Tx power level of the AR6000. Cannot be
+ used to exceed the power limit permitted by the regulatory domain. The maximum
+ output power is limited in the chip to 31.5 dBm; the range is 0 <20> 31.5 dbm.
+
+Command
+ wmiconfig --power <dbM>
+
+Command Parameters
+ UINT8 dbM
+ The desired Tx power specified in dbM.
+ If = 0, the device chooses the maximum
+ permitted by the regulatory domain.
+
+Command Values
+ None
+
+Reset Values
+ The maximum permitted by the regulatory domain
+
+Restrictions
+ None
+
+See Also
+ <20>GET_TX_PWR<57>
+
+
+=====================================================================
+
+Name
+ SET_VOICE_PKT_SIZE
+
+Synopsis
+ If an AP does not support WMM, it has no way to differentiate voice from data.
+ Because the voice packet is typically small, packet in size less than voicePktSize are
+ assumed to be voice, otherwise it is treated as data.
+
+Command
+ wmiconfig eth1 --setVoicePktSize <size-in-bytes>
+
+Command Parameters
+ UINT16 voicePktSize
+ Packet size in octets
+
+Command Values
+ None
+
+Reset Values
+ voicePktSize default is 400 bytes
+
+Restrictions
+ No effect if WMM is unavailable
+
+
+=====================================================================
+
+Name
+ SET_WMM
+
+Synopsis
+ Overrides the AR6000 device WMM capability
+
+Command
+ wmiconfig eth1 --setwmm <enable>
+
+Command Parameters
+ WMI_WMM_ENABLED
+ Enables WMM
+
+ WMI_WMM_DISABLED
+ Disables WMM support
+
+Command Values
+ 0 = disabled
+ 1 = enabled
+
+Reset Value
+ WMM Disabled
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ SET_WMM_TXOP
+
+Synopsis
+ Configures TxOP Bursting when sending traffic to a WMM capable AP
+
+Command
+ wmiconfig eth1 --txopbursting <burstEnable>
+
+ <burstEnable>
+ = 0
+ Disallow TxOp bursting
+
+ = 1
+ Allow TxOp bursting
+
+Command Parameters
+ txopEnable
+ = WMI_TXOP_DISABLED
+ Disabled
+
+ = WMI_TXOP_ENABLED
+ Enabled
+
+Command Values
+ txopEnable
+ = 0 Disabled
+
+ = 1 Enabled
+
+Reset Value
+ Bursting is off by default
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ SET_WOW_MODE
+
+Synopsis
+ The host uses this command to enable or disable the WoW mode. When WoW mode
+ is enabled and the host is asleep, pattern matching takes place at the target level.
+ Only packets that match any of the pre-specified WoW filter patterns, will be passed
+ up to the host. The host will also be woken up by the target. Packets which do not
+ match any of the WoW patterns are discarded.
+
+Command
+ wmiconfig <20>setwowmode <enable/disable>
+
+Command Parameters
+ A_BOOL enable_wow
+ Enable or disable WoW:
+
+Command Values
+ = 0
+ Disable WoW
+
+ = 1
+ Enable WoW
+
+Reset Value
+ None defined (default WoW mode is disabled).
+
+Restrictions
+ None
+
+See Also
+ <20>GET_WOW_LIST<53>
+
+
+=====================================================================
+
+Name
+ SET_WSC_STATUS
+
+Synopsis
+ The supplicant uses this command to inform the target about the status of the WSC
+ registration protocol. During the WSC registration protocol, a flag is set so the target
+ bypasses some of the checks in the CSERV module. At the end of the registration, this
+ flag is reset.
+
+Command
+ N/A
+
+Command Parameters
+ A_BOOL status
+ = 1 WSC registration in progress
+ = 0 WSC protocol not running
+
+Reply Parameters
+ None
+
+Reset Value
+ None defined (default = 0)
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ SNR_THRESHOLD_PARAMS
+
+Synopsis
+ Configures how the AR6000 device monitors and reports SNR of the connected BSS,
+ used as a link quality metric.
+
+Command
+ --snrThreshold <weight> <upper_threshold_1> ...
+ <upper_threshold_4> <lower_threshold_1> ... <lower_threshold_4>
+ <pollTimer>
+
+Command Parameters
+ <weight>
+ Share with rssiThreshold. Range in [1, 16], used
+ in the formula to calculate average RSSI
+
+ <upper_threshold_x>
+ Above thresholds expressed in db, in ascending
+ order
+
+ <lower_threshold_x>
+ Below thresholds expressed in db, in ascending
+ order
+
+ <pollTimer>
+ The signal strength sampling frequency in
+ seconds. If polltime = 0, signal strength
+ sampling is disabled
+
+Command Values
+ None
+
+Reset Value
+ None defined
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ START_SCAN
+
+Synopsis
+ The host uses this command to start a long or short channel scan. All future scans are
+ relative to the time the AR6000 device processes this command. The device performs
+ a channel scan on receipt of this command, even if a scan was already in progress.
+ The host uses this command when it wishes to refresh its cached database of wireless
+ networks. The isLegacy field will be removed (0 for now) because it is achieved by
+ setting CONNECT_PROFILE_MATCH_DONE in the CONNECT command. See also
+ <20>Scan and Roam<61>
+
+Command
+ wmiconfig eth1 --startscan <scan type> <forcefgscan> 0
+ <homeDwellTime> <forceScanInterval>
+
+Command Parameters
+ UINT8 scanType
+ WMI_SCAN_TYPE
+
+Command Values
+ {
+ WMI_LONG_SCAN =0x0
+ Requests a full scan
+ WMI_SHORT_SCAN =0x1
+ Requests a short scan
+ } WMI_SCAN_TYPE
+
+ A_BOOL forceFgScan
+ forceFgScan
+ = 0
+ Disable the foreground scan
+
+ forceFgScan
+ = 1
+ Forces a foreground scan
+
+ A_UINT32 homeDwellTime
+ Maximum duration in the home
+ channel (in ms)
+
+ A_UINT32 forceScanInterval
+ Time interval between scans (in ms)
+
+ A_UINT32 scanType
+ WMI_SCAN_TYPE
+
+Reset Value
+ Disable forcing foreground scan
+
+Restrictions
+ isLegacy field will no longer be supported (pass as 0 for now)
+
+
+=====================================================================
+
+Name
+ SYNCHRONIZE
+
+Synopsis
+ The host uses this command to force a synchronization point between the command
+ and data paths
+
+Command
+ TBD
+
+Command Parameters
+ None
+
+
+
+Command Values
+ None
+
+
+
+Reset Values
+ None
+
+
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ TARGET_ERROR_REPORT_BITMASK
+
+Synopsis
+ Allows the host to control <20>ERROR_REPORT<52> events from the AR6000 device.
+
+ If error reporting is disabled for an error type, a count of errors of that type is
+ maintained by the device.
+
+ If error reporting is enabled for an error type, an <20>ERROR_REPORT<52> event is
+ sent when an error occurs and the error report bit is cleared.
+
+ Error counts for each error type are available through the <20>GET_TARGET_STATS<54>
+ command.
+
+Command
+ wmiconfig eth1 --setErrorReportingBitmask
+
+Command Parameters
+ UINT32 bitmask
+ Represents the set of
+ WMI_TARGET_ERROR_VAL error types
+ enabled for reporting
+
+Command Values
+ {
+ WMI_TARGET_PM_ERR_FAIL = 0x00000001
+ Power save fails (only two cases):
+ Retry out of null function/QoS null
+ function to associated AP for PS
+ indication'
+ Host changes the PS setting when
+ STA is off home channel
+
+ WMI_TARGET_KEY_NOT_FOUND = 0x00000002
+ No cipher key
+ WMI_TARGET_DECRYPTION_ERR = 0x00000004
+ Decryption error
+ WMI_TARGET_BMISS = 0x00000008
+ Beacon miss
+ WMI_PSDISABLE_NODE_JOIN = 0x00000010
+ A non-PS-enabled STA joined the
+ PS-enabled network
+ WMI_TARGET_COM_ERR = 0x00000020
+ Host/target communication error
+ WMI_TARGET_FATAL_ERR = 0x00000040
+ Fatal error
+ } WMI_TARGET_ERROR_VAL
+
+Reset Values
+ Bitmask is 0, and all error reporting is disabled
+
+Restrictions
+ None
+
+
+=====================================================================
+WMI Events
+
+Event
+ Description
+ Page
+
+
+BSSINFO
+ Contains information describing BSSs collected during a scan
+
+CAC_EVENTID
+ Indicates signalling events in admission control
+
+CMDERROR
+ The AR6000 device encounters an error while attempting to process
+ a command
+
+CONNECT
+ The device has connected to a wireless network
+
+DISCONNECT
+ The device lost connectivity with a wireless network
+
+ERROR_REPORT
+ An error has occurred for which the host previously requested
+ notification with the command
+ <20>TARGET_ERROR_REPORT_BITMASK<53>
+
+EXTENSION
+ WMI extension event
+
+GET_PMKID_LIST_EVENT
+ Created in response to a <20>GET_PMKID_LIST_CMD<4D> command
+
+GET_WOW_LIST_EVENT
+ Response to the wmiconfig <20>GET_WOW_LIST<53> command to
+ retrieve the configured WoW patterns
+
+NEIGHBOR_REPORT
+ Neighbor APs that match the current profile were detected
+
+OPT_RX_FRAME_EVENT
+ (Special feature) informs the host of the reception of a special frame
+
+PSTREAM_TIMEOUT
+ A prioritized stream has been idle for a specified interval
+
+READY
+ The AR6000 device is ready to accept commands
+
+REGDOMAIN
+ The regulatory domain has changed
+
+REPORT_ROAM_DATA_EVENT
+ Reports the roam time calculations made by the device
+ (generated with a special build)
+ <20>
+
+REPORT_STATISTICS
+ Reply to a <20>GET_TARGET_STATS<54> command
+
+ROAM_TBL_EVENT
+ Reports the roam table
+
+RSSI_THRESHOLD
+ Signal strength from the connected AP has crossed the threshold
+ defined in the <20>RSSI_THRESHOLD_PARAMS<4D> command
+
+SCAN_COMPLETE_EVENT
+ A scan has completed (added status SCAN_ABORTED in release 2.0)
+
+TEST_EVENT
+ Event generated by the TCMD
+
+TKIP_MICERROR
+ TKIP MIC errors were detected
+
+=====================================================================
+
+Name
+ BSSINFO
+
+Synopsis
+ Contains information describing one or more BSSs as collected during a scan.
+ Information includes the BSSID, SSID, RSSI, network type, channel, supported rates,
+ and IEs. BSSINFO events are sent only after the device receives a beacon or probe-
+ response frame that pass the filter specified in the <20>SET_BSS_FILTER<45> command.
+ BSSINFO events consist of a small header followed by a copy of the beacon or probe
+ response frame. The 802.11 header is not present. For formats of beacon and probe-
+ response frames please consult the IEEE 802.11 specification.
+
+ The beacons or probe responses containing the IE specified by the
+ WMI_BSS_FILTER_CMD are passed to the host through the
+ WMI_BSSINFO_EVENT. The event carries a 32-bit bitmask that indicates the IEs that
+ were detected in the management frame. The frame type field has been extended to
+ indicate action management frames. This would be helpful to route these frames
+ through the same event mechanism as used by the beacon processing function.
+
+ If the bssFilter in the SET_BSS_FILTER matches, then the ieMask is not relevant
+ because the BSSINFO event is sent to the host. If the bssFilter doesnot match in the
+ beacons/probe respones, then the ieMask match dictates whether the BSSINFO
+ event is sent to the host. In the case of action management frames, the ieMask is the
+ filter that is applied.
+
+Event ID
+ 0x1004
+
+Event Parameters
+ typedef struct {
+ A_UINT16 channel;
+ Specifies the frequency (in MHz) where the
+ frame was received
+ A_UINT8 frameType;
+ A WMI_BI_FTYPE value
+ A_UINT8 snr;
+ A_INT16 rssi;
+ Indicates signal strength
+ A_UINT8 bssid[ATH_MAC_LEN];
+ A_UINT32 ieMask;
+ } _ATTRIB_PACK_WMI_BSS_INFO_HDR;
+
+ Beacon or Probe Response Frame
+
+Event Values
+ {
+ BEACON_FTYPE = 0x1
+ Indicates a beacon frame
+ PROBERESP_FTYPE
+ Indicates a probe response frame
+ ACTION_MGMT_FTYPE
+ } WMI_BI_FTYPE
+
+=====================================================================
+
+Name
+ CAC_EVENTID
+
+Synopsis
+ Indicates signalling events in admission control. Events are generated when
+ admission is accepted, rejected, or deleted by either the host or the AP. If the AP does
+ not respond to an admission request within a timeout of 500 ms, an event is
+ generated to the host.
+
+Event ID
+ 0x1011
+
+Event Parameters
+ UINT8
+ ac
+ Access class pertaining to the
+signalling
+
+ UINT8 cac_indication
+ Type of indication; indications are
+ listed in WMI_CAC_INDICATION
+
+ UINT8 statusCode
+ AP response status code for a
+ request
+
+ UINT8 tspecSuggestion[63]
+ Suggested TSPEC from AP
+
+Event Values
+ {
+ CAC_INDICATION_ADMISSION = 0x00
+ CAC_INDICATION_ADMISSION_RESP = 0x01
+ CAC_INDICATION_DELETE = 0x02
+ CAC_INDICATION_NO_RESP = 0x03
+ } WMI_CAC_INDICATION
+
+
+=====================================================================
+
+
+Name
+ CMDERROR
+
+Synopsis
+ Indicates that the AR6000 device encountered an error while attempting to process a
+ command. This error is fatal and indicates that the device requires a reset.
+
+Event ID
+ 0x1005
+
+Event Parameters
+ UINT16 commandId
+ Corresponds to the command which generated
+ the error
+ UINT8 errorCode
+ A WMI_ERROR_CODE value
+
+Event Values
+ {
+ INVALID_PARAM = 1
+ Invalid parameter
+ ILLEGAL_STATE = 2
+ Illegal state
+ INTERNAL_ERROR = 3
+ Internal Error
+ All other values reserved
+ } WMI_ERROR_CODE
+
+
+=====================================================================
+
+
+Name
+ CONNECT
+
+Synopsis
+ Signals that the AR6000 connected to a wireless network. Connection occurs due to a
+ <20>CONNECT<43> command or roaming to a new AP. For infrastructure networks, shows
+ that the AR6000 successfully performed 802.11 authentication and AP association.
+
+Event ID
+ 0x1002
+
+Event Parameters
+ UINT16 channel
+ Channel frequency (in MHz) of the network the
+ AR6000 are connected to
+
+ UINT8 bssid[6]
+ MAC address of the AP the AR6000 are
+ connected to or the BSSID of the ad hoc
+ network
+
+ UINT16 listenInterval
+ Listen interval (in Kms) that the AR6000 are
+ using
+
+ UINT 8 beaconIeLen
+ Length (in bytes) of the beacon IEs
+
+ UINT8 assocInfo
+ Pointer to an array containing beacon IEs,
+ followed first by association request IEs then by
+ association response IEs
+
+ UINT8 assocReqLen
+ Length (in bytes) of the assocReqIEs array
+
+ UINT8 assocRespLen
+ Length (in bytes) of the assocRespIEs array
+
+Event Values
+ None defined
+
+=====================================================================
+
+
+Name
+ DISCONNECT
+
+Synopsis
+ Signals that the AR6000 device lost connectivity with the wireless network.
+ DISCONENCT is generated when the device fails to complete a <20>CONNECT<43>
+ command or as a result of a transition from a connected state to disconnected state.
+
+ After sending the <20>DISCONNECT<43> event the device continually tries to re-establish
+ a connection. A LOST_LINK occurs when STA cannot receive beacons within the
+ specified time for the SET_BMISS_TIME command.
+
+Event ID
+ 0x1003
+
+Event Parameters
+ UINT8 disconnect
+ Reason
+ A WMI_DISCONNECT_REASON value
+
+ UINT8 bssid[6]
+ Indicates which BSS the device was connected to
+
+ UINT8 assocRespLen
+ Length of the 802.11 association response frame
+ that triggered this event, or 0 if not applicable
+
+ UINT8 assocInfo[assocRespLen]
+ Copy of the 802.11 association response frame
+
+Event Values
+ {
+ NO_NETWORK_AVAIL =0x01
+ Indicates that the device was unable to
+ establish or find the desired network
+ LOST_LINK =0x02
+ Indicates the devices is no longer receiving
+ beacons from the BSS it was previously
+ connected to
+
+ DISCONNECT_CMD =0x03
+ Indicates a <20>DISCONNECT<43> command was
+ processed
+ BSS_DISCONNECTED =0x04
+ Indicates the BSS explicitly disconnected the
+ device. Possible mechanisms include the AP
+ sending 802.11 management frames
+ (e.g., disassociate or deauthentication
+ messages).
+ AUTH_FAILED =0x05
+ Indicates that the device failed 802.11
+ authentication with the BSS
+ ASSOC_FAILED =0x06
+ Indicates that the device failed 802.11
+ association with the BSS
+ NO_RESOURCES_AVAIL =0x07
+ Indicates that a connection failed because the
+ AP had insufficient resources to complete the
+ connection
+ CSERV_DISCONNECT =0x08
+ Indicates that the device<63>s connection services
+ module decided to disconnect from a BSS,
+ which can happen for a variety of reasons (e.g.,
+ the host marks the current connected AP as a
+ bad AP).
+ INVALID_PROFILE =0x0A
+ Indicates that an attempt was made to
+ reconnect to a BSS that no longer matches the
+ current profile
+ All other values are reserved
+ } WMI_DISCONNECT_REASON
+
+
+=====================================================================
+
+
+Name
+ ERROR_REPORT
+
+Synopsis
+ Signals that a type of error has occurred for which the host previously requested
+ notification through the <20>TARGET_ERROR_REPORT_BITMASK<53> command.
+
+Event ID
+ 0x100D
+
+Event Parameters
+ UINT32 errorVal
+ WMI_TARGET_ERROR_VAL value. See
+ <20>TARGET_ERROR_REPORT_BITMASK<53>.
+
+Event Values
+ errorVal
+ = 0x00000001
+ Power save fails
+
+ = 0x00000002
+ No cipher key
+
+ = 0x00000004
+ Decryption error
+
+ = 0x00000008
+ Beacon miss
+
+ = 0x00000010
+ A non-power save disabled node has joined
+ the PS-enabled network
+
+
+=====================================================================
+
+
+Name
+ EXTENSION
+
+Synopsis
+ The WMI is used mostly for wireless control messages to a wireless module that
+ apply to wireless module management regardless of the target platform
+ implementation. However, some events peripherally related to wireless management
+ are desired during operation. These wireless extension events may be platform-
+ specific or implementation-dependent. See <20>WMI Extension Commands<64>
+
+
+Event ID
+ 0x1010
+
+
+=====================================================================
+
+
+Name
+ GET_PMKID_LIST_EVENT
+
+Synopsis
+ Generated by firmware in response to a <20>GET_PMKID_LIST_CMD<4D> command.
+
+Event Parameters
+ typedef struct {
+ A_UINT32 numPMKID;
+ Contains the number of PMKIDs in the reply
+ WMI_PMKID pmkidList[1];
+ } __ATTRIB_PACK WMI_PMKID_LIST_REPLY;
+
+Event Values
+ None
+
+
+=====================================================================
+
+
+Name
+ GET_WOW_LIST_EVENT
+
+Synopsis
+ Response to the wmiconfig <20>getwowlist command to retrieve the configured Wake on
+ Wireless patterns
+
+Event ID
+ 0x10018
+
+Event Parameters
+ {
+
+ A_UINT8 num_filters
+ Total number of patterns in the list
+ A_UINT8 this_filter_num
+ The filter number
+ A_UINT8 wow_mode
+ Shows whether WoW is enabled or disabled
+ A_UINT8 host_mode
+ Shows whether the host is asleep or awake
+ WOW_FILTER wow_filters[1]
+ List of WoW filters (pattern and mask data bytes)
+ } WMI_GET_WOW_LIST_REPLY;
+
+ {
+ Each wow_filter_list element shows:
+ A_UINT8 wow_valid_filter
+ Whether the filter is valid
+ A_UINT8 wow_filter_list_id
+ Filter List ID (23 = default)
+ A_UINT8 wow_filter_size
+ Size in bytes of the filter
+ A_UINT8 wow_filter_offset
+ Offset of the pattern to search in the data packet
+ A_UINT8 wow_filter_mask[MASK_SIZE]
+ The mask to be applied to the pattern
+ A_UINT8 wow_filter_pattern[WOW_PATTERN_SIZE]
+ The pattern that to match to wake up the host
+ } WOW_FILTER
+
+Event Values
+ None
+
+=====================================================================
+
+
+
+Name
+ NEIGHBOR_REPORT
+
+Synopsis
+ Indicates the existence of neighbor APs that match the current profile. The host uses
+ this event to populate the PMKID cache on the AR6000 and/or to perform
+ preauthentication. This event is only generated in infrastructure mode.
+
+ A total of numberOfAps pairs of bssid/bssFlags exist, one pair for each AP.
+
+Event ID
+ 0x1008
+
+Event Parameters
+ UINT8 numberOfAps
+ The number of APs reported about in
+ this event
+ {
+ UINT8 bssid[6]
+ MAC address of a neighbor AP
+ UINT8 bssFlags
+ A WMI_BSS_FLAGS value
+ }[numberOfAps]
+
+
+Event Values
+ {
+ WMI_DEFAULT_BSS_FLAGS = 0
+ Logical OR of 1 or more
+ WMI_BSS_FLAGS
+ WMI_PREAUTH_CAPABLE_BSS
+ = 1
+ Indicates that this AP is capable of
+ preauthentication
+ WMI_PMKID_VALID_BSS
+ = 2
+ Indicates that the AR6000 have a
+ valid pairwise master key for this AP
+ } WMI_BSS_FLAGS
+
+
+=====================================================================
+
+
+
+Name
+ OPT_RX_FRAME_EVENT
+
+Synopsis
+ Special feature, informs host of the reception of a special frame.
+
+Event ID
+ 0x100E
+
+Event Parameters
+ {
+ A_UINT16 channel;
+ A_UINT8 frameType;
+ A_INT8 snr;
+ A_UINT8 srcAddr[ATH_MAC_LEN];
+ A_UINT8 bssid[ATH_MAC_LEN];
+ }WMI_OPT_RX_INFO_HDR
+
+Event Values
+ None
+
+=====================================================================
+
+
+
+Name
+ PSTREAM_TIMEOUT
+
+Synopsis
+ Indicates that a priority stream that got created as a result of priority-marked data
+ flow (priority marked in IP TOS) being idle for the default inactivity interval period
+ (specified in the <20>CREATE_PSTREAM<41> command) used for priority streams created
+ implicitly by the driver. This event is not indicated for user-created priority streams.
+ User-created priority streams exist until the users delete them explicitly. They do not
+ timeout due to data inactivity.
+
+Event ID
+ 0x1007
+
+Event Parameters
+ A_UINT8
+ trafficClass
+ Indicated the traffic class of priority
+ stream that timed out
+
+Event Values
+ {
+ WMM_AC_BE = 0
+ Best effort
+ WMM_AC_BK = 1
+ Background
+ WMM_AC_VI = 2
+ Video
+ WMM_AC_VO = 3
+ Voice
+ } TRAFFIC CLASS
+
+
+=====================================================================
+
+Name
+ READY
+
+Synopsis
+ Indicates that the AR6000 device is prepared to accept commands. It is sent once after
+ power on or reset. It also indicates the MAC address of the device.
+
+Event ID
+ 0x1001
+
+Event Parameters
+ UINT8 macAddr[6]
+ Device MAC address
+ UINT8 phyCapability
+ A WMI_PHY_CAPABILITY value. Indicates the
+ capabilities of the device wireless module<6C>s radio
+
+Event Values
+ {
+ WMI_11A_CAPABILITY = 1
+ WMI_11G_CAPABILITY = 2
+ WMI_11AG_CAPABILITY = 3
+ } WMI_PHY_CAPABILITY
+
+
+=====================================================================
+
+Name
+ REGDOMAIN
+
+Synopsis
+ Indicates that the regulatory domain has changed. It initially occurs when the
+ AR6000 device reads the board data information. The regulatory domain can also
+ change when the device is a world-mode SKU. In this case, the regulatory domain is
+ based on the country advertised by APs per the IEEE 802.11d specification. A
+ potential side effect of a regulatory domain change is a change in the list of available
+ channels. Any channel restrictions that exist as a result of a previous
+ <20>SET_CHANNEL_PARAMETERS<52> command are lifted.
+
+Event ID
+ 0x1006
+
+Event Parameters
+ UINT32 regDomain
+ The range of 0x0000 <20> 0x00FF
+ corresponds to an ISO country code.
+
+ Other regCodes are reserved for world
+ mode settings and specific regulatory
+ domains.
+
+Event Values
+ None
+
+
+=====================================================================
+
+
+
+Name
+ REPORT_STATISTICS
+
+Synopsis
+ A reply to a <20>GET_TARGET_STATS<54> command.
+
+Event ID
+ 0x100B
+
+Event Parameters
+ When the statistics are sent to the host, the AR6001 clear them so that a new set of
+ statistics are collected for the next report.
+
+ UINT32 tx_packets
+ UINT32 tx_bytes
+ UINT32 tx_unicast_pkts
+ UINT32 tx_unicast_bytes
+ UINT32 tx_multicast_pkts
+ UINT32 tx_multicast_bytes
+ UINT32 tx_broadcast_pkts
+ UINT32 tx_broadcast_bytes
+ UINT32 tx_rts_success_cnt
+ UINT32 tx_packet_per_ac[4]
+ Tx packets per AC: [0] = BE, [1] = BK,
+ [2] = VI, [3] = VO
+ UINT32 tx_errors
+ Number of packets which failed Tx, due
+ to all failures
+ ... REPORT_STATISTICS, continued
+ UINT32 tx_failed_cnt
+ Number of data packets that failed Tx
+ UINT32 tx_retry_cnt
+ Number of Tx retries for all packets
+ UINT32 tx_rts_fail_cnt
+ Number of RTS Tx failed count
+ UINT32 rx_packets
+ UINT32 rx_bytes
+ UINT32 rx_unicast_pkts
+ UINT32 rx_unicast_bytes
+ UINT32 rx_multicast_pkts
+ UINT32 rx_multicast_bytes
+ UINT32 rx_broadcast_pkts
+ UINT32 rx_broadcast_bytes
+ UINT32 rx_fragment_pkt
+ Number of fragmented packets received
+ UINT32 rx_errors
+ Number of Rx errors due to all failures
+ UINT32 rx_crcerr
+ Number of Rx errors due to CRC errors
+ UINT32 rx_key_cache_miss
+ Number of Rx errors due to a key not
+ being plumbed
+ UINT32 rx_decrypt_err
+ Number of Rx errors due to decryption
+ failure
+ UINT32 rx_duplicate_frames
+ Number of duplicate frames received
+ UINT32 tkip_local_mic_failure
+ Number of TKIP MIC errors detected
+ UINT32 tkip_counter_measures_invoked
+ Number of times TKIP countermeasures
+ were invoked
+ UINT32 tkip_replays
+ Number of frames that replayed a TKIP
+ encrypted frame received earlier
+ UINT32 tkip_format_errors
+ Number of frames that did not conform
+ to the TKIP frame format
+ UINT32 ccmp_format_errors
+ Number of frames that did not conform
+ to the CCMP frame format
+ UINT32 ccmp_replays
+ Number of frames that replayed a CCMP
+ encrypted frame received earlier
+ UINT32 power_save_failure_cnt
+ Number of failures that occurred when
+ the AR6001 could not go to sleep
+ UINT32 cs_bmiss_cnt
+ Number of BMISS interrupts since
+ connection
+ UINT32 cs_lowRssi_cnt
+ Number of the times the RSSI went below
+ the low RSSI threshold
+ UINT16 cs_connect_cnt
+ Number of connection times
+ UINT16 cs_disconnect_cnt
+ Number of disconnection times
+ UINT8 cs_aveBeacon_rssi
+ The current averaged value of the RSSI
+ from the beacons of the connected BSS
+ UINT8 cs_lastRoam_msec
+ Time that the last roaming took, in ms.
+ This time is the difference between
+ roaming start and actual connection.
+
+Event Values
+ None defined
+
+
+=====================================================================
+
+Name
+ ROAM_TBL_EVENT
+
+Synopsis
+ Reports the roam table, which contains the current roam mode and this information
+ for every BSS:
+
+Event ID
+ 0x100F
+
+Event Parameters
+ A_UINT8 bssid[ATH_MAC_LEN];
+ BSSID
+ A_UINT8 rssi
+ Averaged RSSI
+ A_UINT8 rssidt
+ Change in RSSI
+ A_UINT8 last_rssi
+ Last recorded RSSI
+ A_UINT8 roam_util
+ Utility value used in roaming decision
+ A_UINT8 util
+ Base utility with the BSS
+ A_UINT8 bias
+ Host configured for this BSS
+
+Event Values
+ roamMode
+ Current roam mode
+
+ = 1
+ RSSI based roam
+
+ = 2
+ Host bias-based roam
+
+ = 3
+ Lock to the current BSS
+
+ = 4
+ Autonomous roaming disabled
+
+
+=====================================================================
+
+Name
+ RSSI_THRESHOLD
+
+Synopsis
+ Alerts the host that the signal strength from the connected AP has crossed a
+ interesting threshold as defined in a previous <20>RSSI_THRESHOLD_PARAMS<4D>
+ command.
+
+Event ID
+ 0x100C
+
+Event Parameters
+ UINT8 range
+ A WMI_RSSI_THRESHOLD_VAL
+ value, which indicates the range of
+ the average signal strength
+
+Event Values
+ {
+ WMI_RSSI_LOWTHRESHOLD_BELOW_LOWERVAL = 1
+ WMI_RSSI_LOWTHRESHOLD_LOWERVAL = 2
+ WMI_RSSI_LOWTHRESHOLD_UPPERVAL = 3
+ WMI_RSSI_HIGHTHRESHOLD_LOWERVAL = 4
+ WMI_RSSI_HIGHTHRESHOLD_HIGHERVAL = 5
+ } WMI_RSSI_THRESHOLD_VAL
+
+
+=====================================================================
+
+Name
+ SCAN_COMPLETE_EVENT
+
+Synopsis
+ Indicates the scan status. if the Scan was not completed, this event is generated with
+ the status A_ECANCELED.
+
+Event ID
+ 0x100A
+
+Event Parameters
+ A_UINT8 scanStatus
+
+Event Values
+ {
+ #define SCAN_ABORTED 16
+ #define SCAN_COMPLETED 0
+ A_UINT8 scanStatus
+ A_OK or A_ECANCELED
+ } WMI_SCAN_COMPLETE_EVENT;
+
+
+=====================================================================
+
+Name
+ TEST_EVENT
+
+Synopsis
+ The TCMD application uses a single WMI event (WMI_TEST_EVENTID) to
+ communicate events from target to host. The events are parsed by the TCMD
+ application and WMI layer is oblivious of it.
+
+Event ID
+ 0x1016
+
+Event Parameters
+ WMI_TEST_EVENTID
+
+
+Event Values
+ None
+
+
+=====================================================================
+
+
+
+Name
+ TKIP_MICERR
+
+Synopsis
+ Indicates that TKIP MIC errors were detected.
+
+Event ID
+ 0x1009
+
+Event Parameters
+ UINT8 keyid
+ Indicates the TKIP key ID
+
+ UINT8 ismcast
+ 0 = Unicast
+ 1 = Multicast
+
+Event Values
+ See event parameters
+
+=====================================================================
+
+WMI Extension Commands
+
+The WMI EXTENSION command is used to multiplex a collection of
+commands that:
+
+ Are not generic wireless commands
+ May be implementation-specific
+ May be target platform-specific
+ May be optional for a host implementation
+
+ An extension command is sent to the AR6000 targets like any other WMI
+command message and uses the WMI_EXTENSION. The first field of the
+payload for this EXTENSION command is another commandId, sometimes
+called the subcommandId, which indicates which extension command is
+being used. A subcommandId-specific payload follows the subcommandId.
+
+All extensions (subcommandIds) are listed in the header file include/wmix.h.
+See also <20>WMI Extension Events<74> on page B-58.
+
+
+WMI Extension Commands
+
+
+GPIO_INPUT_GET
+ Read GPIO pins configured for input
+
+GPIO_INTR_ACK
+ Acknowledge and re-arm GPIO interrupts reported earlier
+
+GPIO_OUTPUT_SET
+ Manage output on GPIO pins configured for output
+
+GPIO_REGISTER_GET
+ Read an arbitrary GPIO register
+
+GPIO_REGISTER_SET
+ Dynamically change GPIO configuration
+
+SET_LQTHRESHOLD
+ Set link quality thresholds; the sampling happens at every unicast
+ data frame Tx, if certain thresholds are met, and corresponding
+ events are sent to the host
+
+
+=====================================================================
+
+Name
+ GPIO_INPUT_GET
+
+Synopsis
+ Allows the host to read GPIO pins that are configured for input. The values read are
+ returned through a <20>GPIO_DATA<54> extension event.
+
+NOTE: Support for GPIO is optional.
+
+Command
+ N/A
+
+Command Parameters
+ None
+
+
+
+Reply Parameters
+ None
+
+
+Reset Value
+ None
+
+
+
+Restrictions
+ None
+
+=====================================================================
+
+
+Name
+ GPIO_INTR_ACK
+
+Synopsis
+ The host uses this command to acknowledge and to re-arm GPIO interrupts reported
+ through an earlier <20>GPIO_INTR<54> extension event. A single <20>GPIO_INTR_ACK<43>
+ command should be used to acknowledge all GPIO interrupts that the host knows to
+ be outstanding (if pending interrupts are not acknowledged through
+ <20>GPIO_INTR_ACK<43>, another <20>GPIO_INTR<54> extension event is raised).
+
+NOTE: Support for GPIO is optional.
+
+Command
+ N/A
+
+Command Parameters
+ UINT32 ack_mask
+ A mask of interrupting GPIO pins (e.g., ack_mask
+ bit [3] acknowledges an interrupt from the pin GPIO3).
+
+Command Values
+ None
+
+Reset Value
+ None
+
+Restrictions
+ The host should acknowledge only interrupts about which it was notified.
+
+
+=====================================================================
+
+Name
+ GPIO_OUTPUT_SET
+
+Synopsis
+ Manages output on GPIO pins configured for output.
+
+ Conflicts between set_mask and clear_mask or enable_mask and disable_mask result
+ in undefined behavior.
+
+NOTE: Support for GPIO is optional.
+
+Command
+ N/A
+
+Command Parameters
+ UINT32 set_mask
+ Specifies which pins should drive a 1 out
+ UINT32 clear_mask
+ Specifies which pins should drive a 0 out
+ UINT32 enable_mask
+ Specifies which pins should be enabled for output
+ UINT32 disable_mask
+ Specifies which pins should be disabled for output
+
+Command Values
+ None
+
+
+Reset Value
+ None
+
+
+Restrictions
+ None
+
+
+
+=====================================================================
+
+
+Name
+ GPIO_REGISTER_GET
+
+Synopsis
+ Allows the host to read an arbitrary GPIO register. It is intended for use during
+ bringup/debug. The target responds to this command with a <20>GPIO_DATA<54> event.
+
+NOTE: Support for GPIO is optional.
+
+Command
+ N/A
+
+Command Parameters
+ UINT32
+ gpioreg_id
+ Specifies a GPIO register identifier, as defined
+in include/AR6000/AR6000_gpio.h
+
+Reply Parameters
+ None
+
+Reset Value
+ N/A
+
+Restrictions
+ None
+
+
+=====================================================================
+
+Name
+ GPIO_REGISTER_SET
+
+Synopsis
+ Allows the host to dynamically change GPIO configuration (usually handled
+ statically through the GPIO configuration DataSet).
+
+NOTE: Support for GPIO is optional.
+
+Command
+ N/A
+
+Command Parameters
+ UINT32 gpioreg_id
+ Specifies a GPIO register identifier, as defined in
+ include/AR6000/AR6000_gpio.h
+ UINT32 value
+ Specifies a value to write to the specified
+ GPIO register
+
+Command Values
+ None
+
+
+Reset Value
+ Initial hardware configuration is as defined in the AR6001 or AR6002 ROCmTM
+ Single-Chip MAC/BB/Radio for 2.4/5 GHz Embedded WLAN Applications data sheet. This
+ configuration is modified by the GPIO Configuration DataSet, if one exists.
+
+Restrictions
+ None
+
+
+=====================================================================
+
+
+Name
+ SET_LQTHRESHOLD
+
+Synopsis
+ Set link quality thresholds, the sampling happens at every unicast data frame Tx, if
+ certain threshold is met, corresponding event will be sent to host.
+
+Command
+ wmiconfig eth1 --lqThreshold <enable> <upper_threshold_1>...
+ <upper_threshold_4> <lower_threshold_1>... <lower_threshold_4>
+
+Command Parameters
+ A_UINT8 enable;
+ A_UINT8 thresholdAbove1_Val;
+ A_UINT8 thresholdAbove2_Val;
+ A_UINT8 thresholdAbove3_Val;
+ A_UINT8 thresholdAbove4_Val;
+ A_UINT8 thresholdBelow1_Val;
+ A_UINT8 thresholdBelow2_Val;
+ A_UINT8 thresholdBelow3_Val;
+ A_UINT8 thresholdBelow4_Val;
+
+Command Values
+ enable
+ = 0
+ Disable link quality sampling
+
+ = 1
+ Enable link quality sampling
+
+
+ thresholdAbove_Val
+ [1...4]
+ Above thresholds (value in [0,100]), in ascending
+ order threshold
+
+ Below_Val [1...4] = below thresholds (value
+ in [0,100]), in ascending order
+
+Reset Values
+ None
+
+Restrictions
+ None
+
+=====================================================================
+WMI Extension Events
+
+The WMI EXTENSION event is used for a collection of events that:
+
+ Are not generic wireless events
+ May be implementation-specific
+ May be target platform-specific
+ May be optional for a host implementation
+
+ An extension event is sent from the AR6000 device targets to the host just like
+any other WMI event message, using the WMI_EXTENSION_EVENTID. The
+first field of the payload for this <20>EXTENSION<4F> event is another commandId
+(sometimes called the subcommandId) that indicates which <20>EXTENSION<4F>
+event is being used. A subcommandId-specific payload follows the
+subcommandId.
+
+All extensions (subcommandIds) are listed in the header file include/wmix.h.
+See also <20>WMI Extension Commands<64> on page B-55.
+
+
+WMI Extension Events
+
+
+GPIO_ACK
+ Acknowledges a host set command has been processed by the device
+
+GPIO_DATA
+ Response to a host<73>s request for data
+
+GPIO_INTR
+ Signals that GPIO interrupts are pending
+
+
+=====================================================================
+
+Name
+ GPIO_ACK
+
+Synopsis
+ Acknowledges that a host set command (either <20>GPIO_OUTPUT_SET<45> or
+ <20>GPIO_REGISTER_SET<45>) has been processed by the AR6000 device.
+
+NOTE: Support for GPIO is optional.
+
+Event ID
+ N/A
+
+Event Parameters
+ None
+
+
+Event Values
+ None
+
+=====================================================================
+
+
+Name
+ GPIO_DATA
+
+Synopsis
+ The AR6000 device uses this event to respond to the host<73>s earlier request for data
+ (through either a <20>GPIO_REGISTER_GET<45> or a <20>GPIO_INPUT_GET<45> command).
+
+NOTE: Support for GPIO is optional.
+
+Event ID
+ N/A
+
+Event Parameters
+ UINT32 value
+ Holds the data of interest, which is either a register value
+ (in the case of <20>GPIO_REGISTER_GET<45>) or a mask of
+ pin inputs (in the case of <20>GPIO_INPUT_GET<45>).
+ UINT32 reg_id
+ Indicates which register was read (in the case of
+ <20>GPIO_REGISTER_GET<45>) or is GPIO_ID_NONE (in the
+ case of <20>GPIO_INPUT_GET<45>)
+
+Event Values
+ None
+
+
+=====================================================================
+
+
+
+Name
+ GPIO_INTR
+
+Synopsis
+ The AR6000 device raises this event to signal that GPIO interrupts are pending.
+ These GPIOs may be interrupts that occurred after the last <20>GPIO_INTR_ACK<43>
+ command was issued, or may be GPIO interrupts that the host failed to acknowledge
+ in the last <20>GPIO_INTR_ACK<43>. The AR6000 will not raise another GPIO_INTR
+ event until this event is acknowledged through a <20>GPIO_INTR_ACK<43> command.
+
+NOTE: Support for GPIO is optional.
+
+Event ID
+ N/A
+
+Event Parameters
+ UINT32 intr_mask
+ Indicates which GPIO interrupts are currently pending
+
+ UINT32 input_values
+ A recent copy of the GPIO input values, taken at the
+ time the most recent GPIO interrupt was processed
+
+Event Values
+ None
+
+
+
+=====================================================================
+#endif
--- /dev/null
+++ b/drivers/ar6000/wmi/wmi_host.h
@@ -0,0 +1,71 @@
+#ifndef _WMI_HOST_H_
+#define _WMI_HOST_H_
+/*
+ * Copyright (c) 2004-2006 Atheros Communications Inc.
+ * All rights reserved.
+ *
+ * This file contains local definitios for the wmi host module.
+ *
+ * $Id: //depot/sw/releases/olca2.0-GPL/host/wmi/wmi_host.h#1 $
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ *
+ * Software distributed under the License is distributed on an "AS
+ * IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+ * implied. See the License for the specific language governing
+ * rights and limitations under the License.
+ *
+ *
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct wmi_stats {
+ A_UINT32 cmd_len_err;
+ A_UINT32 cmd_id_err;
+};
+
+struct wmi_t {
+ A_BOOL wmi_ready;
+ A_BOOL wmi_numQoSStream;
+ A_UINT8 wmi_wmiStream2AcMapping[WMI_PRI_MAX_COUNT];
+ WMI_PRI_STREAM_ID wmi_ac2WmiStreamMapping[WMM_NUM_AC];
+ A_UINT16 wmi_streamExistsForAC[WMM_NUM_AC];
+ A_UINT8 wmi_fatPipeExists;
+ void *wmi_devt;
+ struct wmi_stats wmi_stats;
+ struct ieee80211_node_table wmi_scan_table;
+ A_UINT8 wmi_bssid[ATH_MAC_LEN];
+ A_UINT8 wmi_powerMode;
+ A_UINT8 wmi_phyMode;
+ A_UINT8 wmi_keepaliveInterval;
+ A_MUTEX_T wmi_lock;
+};
+
+#define WMI_INIT_WMISTREAM_AC_MAP(w) \
+{ (w)->wmi_wmiStream2AcMapping[WMI_BEST_EFFORT_PRI] = WMM_AC_BE; \
+ (w)->wmi_wmiStream2AcMapping[WMI_LOW_PRI] = WMM_AC_BK; \
+ (w)->wmi_wmiStream2AcMapping[WMI_HIGH_PRI] = WMM_AC_VI; \
+ (w)->wmi_wmiStream2AcMapping[WMI_HIGHEST_PRI] = WMM_AC_VO; \
+ (w)->wmi_ac2WmiStreamMapping[WMM_AC_BE] = WMI_BEST_EFFORT_PRI; \
+ (w)->wmi_ac2WmiStreamMapping[WMM_AC_BK] = WMI_LOW_PRI; \
+ (w)->wmi_ac2WmiStreamMapping[WMM_AC_VI] = WMI_HIGH_PRI; \
+ (w)->wmi_ac2WmiStreamMapping[WMM_AC_VO] = WMI_HIGHEST_PRI; }
+
+#define WMI_WMISTREAM_ACCESSCATEGORY(w,s) (w)->wmi_wmiStream2AcMapping[s]
+#define WMI_ACCESSCATEGORY_WMISTREAM(w,ac) (w)->wmi_ac2WmiStreamMapping[ac]
+
+#define LOCK_WMI(w) A_MUTEX_LOCK(&(w)->wmi_lock);
+#define UNLOCK_WMI(w) A_MUTEX_UNLOCK(&(w)->wmi_lock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WMI_HOST_H_ */
--- a/drivers/base/bus.c
+++ b/drivers/base/bus.c
@@ -141,6 +141,29 @@
}
EXPORT_SYMBOL_GPL(bus_remove_file);
+int bus_create_device_link(struct bus_type *bus, struct kobject *target,
+ const char *name)
+{
+ int error;
+ if (bus_get(bus)) {
+ error = sysfs_create_link(&bus->p->devices_kset->kobj, target,
+ name);
+ bus_put(bus);
+ } else
+ error = -EINVAL;
+ return error;
+}
+EXPORT_SYMBOL_GPL(bus_create_device_link);
+
+void bus_remove_device_link(struct bus_type *bus, const char *name)
+{
+ if (bus_get(bus)) {
+ sysfs_remove_link(&bus->p->devices_kset->kobj, name);
+ bus_put(bus);
+ }
+}
+EXPORT_SYMBOL_GPL(bus_remove_device_link);
+
static struct kobj_type bus_ktype = {
.sysfs_ops = &bus_sysfs_ops,
};
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -55,6 +55,11 @@
*/
const char *dev_driver_string(const struct device *dev)
{
+ if (!dev) {
+ printk(KERN_ERR"Null dev to dev_driver_string\n");
+ dump_stack();
+ return "*NULL*";
+ }
return dev->driver ? dev->driver->name :
(dev->bus ? dev->bus->name :
(dev->class ? dev->class->name : ""));
--- a/drivers/base/power/main.c
+++ b/drivers/base/power/main.c
@@ -69,9 +69,9 @@
*/
void device_pm_add(struct device *dev)
{
- pr_debug("PM: Adding info for %s:%s\n",
+ /* pr_debug("PM: Adding info for %s:%s\n",
dev->bus ? dev->bus->name : "No Bus",
- kobject_name(&dev->kobj));
+ kobject_name(&dev->kobj)); */
mutex_lock(&dpm_list_mtx);
if (dev->parent) {
if (dev->parent->power.status >= DPM_SUSPENDING)
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -66,6 +66,18 @@
If unsure, say Y.
+config NR_TTY_DEVICES
+ int "Maximum tty device number"
+ depends on VT
+ default 63
+ ---help---
+ This is the highest numbered device created in /dev. You will actually have
+ NR_TTY_DEVICES+1 devices in /dev. The default is 63, which will result in
+ 64 /dev entries. The lowest number you can set is 11, anything below that,
+ and it will default to 11. 63 is also the upper limit so we don't overrun
+ the serial consoles.
+
+
config HW_CONSOLE
bool
depends on VT && !S390 && !UML
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -6,8 +6,7 @@
#include <linux/err.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
-#include <linux/gpio.h>
-
+#include <mach/gpio.h>
/* Optional implementation infrastructure for GPIO interfaces.
*
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -34,14 +34,12 @@
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
+#include <linux/io.h>
-#include <mach/hardware.h>
#include <asm/irq.h>
-#include <asm/io.h>
-#include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-iic.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
/* i2c controller state */
@@ -64,6 +62,7 @@
unsigned int msg_ptr;
unsigned int tx_setup;
+ unsigned int irq;
enum s3c24xx_i2c_state state;
unsigned long clkrate;
@@ -71,7 +70,6 @@
void __iomem *regs;
struct clk *clk;
struct device *dev;
- struct resource *irq;
struct resource *ioarea;
struct i2c_adapter adap;
@@ -80,16 +78,7 @@
#endif
};
-/* default platform data to use if not supplied in the platform_device
-*/
-
-static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
- .flags = 0,
- .slave_addr = 0x10,
- .bus_freq = 100*1000,
- .max_freq = 400*1000,
- .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
-};
+/* default platform data removed, dev should always carry data. */
/* s3c24xx_i2c_is2440()
*
@@ -103,21 +92,6 @@
return !strcmp(pdev->name, "s3c2440-i2c");
}
-
-/* s3c24xx_i2c_get_platformdata
- *
- * get the platform data associated with the given device, or return
- * the default if there is none
-*/
-
-static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
-{
- if (dev->platform_data != NULL)
- return (struct s3c2410_platform_i2c *)dev->platform_data;
-
- return &s3c24xx_i2c_default_platform;
-}
-
/* s3c24xx_i2c_master_complete
*
* complete the message and wake up the caller, using the given return code,
@@ -130,7 +104,7 @@
i2c->msg_ptr = 0;
i2c->msg = NULL;
- i2c->msg_idx ++;
+ i2c->msg_idx++;
i2c->msg_num = 0;
if (ret)
i2c->msg_idx = ret;
@@ -141,19 +115,17 @@
static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;
-
+
tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
-
}
static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;
-
+
tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
-
}
/* irq enable/disable functions */
@@ -161,15 +133,23 @@
static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;
-
+
tmp = readl(i2c->regs + S3C2410_IICCON);
+
+/* S3c2442 datasheet
+ *
+ * If the IICCON[5]=0, IICCON[4] does not operate correctly.
+ * So, It is recommended that you should set IICCON[5]=1,
+ * although you does not use the IIC interrupt.
+ */
+
writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
}
static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;
-
+
tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
}
@@ -177,10 +157,10 @@
/* s3c24xx_i2c_message_start
*
- * put the start of a message onto the bus
+ * put the start of a message onto the bus
*/
-static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
+static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
struct i2c_msg *msg)
{
unsigned int addr = (msg->addr & 0x7f) << 1;
@@ -199,15 +179,15 @@
if (msg->flags & I2C_M_REV_DIR_ADDR)
addr ^= 1;
- // todo - check for wether ack wanted or not
+ /* todo - check for wether ack wanted or not */
s3c24xx_i2c_enable_ack(i2c);
iiccon = readl(i2c->regs + S3C2410_IICCON);
writel(stat, i2c->regs + S3C2410_IICSTAT);
-
+
dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
writeb(addr, i2c->regs + S3C2410_IICDS);
-
+
/* delay here to ensure the data byte has gotten onto the bus
* before the transaction is started */
@@ -215,8 +195,8 @@
dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
writel(iiccon, i2c->regs + S3C2410_IICCON);
-
- stat |= S3C2410_IICSTAT_START;
+
+ stat |= S3C2410_IICSTAT_START;
writel(stat, i2c->regs + S3C2410_IICSTAT);
}
@@ -227,11 +207,11 @@
dev_dbg(i2c->dev, "STOP\n");
/* stop the transfer */
- iicstat &= ~ S3C2410_IICSTAT_START;
+ iicstat &= ~S3C2410_IICSTAT_START;
writel(iicstat, i2c->regs + S3C2410_IICSTAT);
-
+
i2c->state = STATE_STOP;
-
+
s3c24xx_i2c_master_complete(i2c, ret);
s3c24xx_i2c_disable_irq(i2c);
}
@@ -241,7 +221,7 @@
/* is_lastmsg()
*
- * returns TRUE if the current message is the last in the set
+ * returns TRUE if the current message is the last in the set
*/
static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
@@ -289,14 +269,14 @@
case STATE_STOP:
dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
- s3c24xx_i2c_disable_irq(i2c);
+ s3c24xx_i2c_disable_irq(i2c);
goto out_ack;
case STATE_START:
/* last thing we did was send a start condition on the
* bus, or started a new i2c message
*/
-
+
if (iicstat & S3C2410_IICSTAT_LASTBIT &&
!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
/* ack was not received... */
@@ -322,7 +302,7 @@
if (i2c->state == STATE_READ)
goto prepare_read;
- /* fall through to the write state, as we will need to
+ /* fall through to the write state, as we will need to
* send a byte as well */
case STATE_WRITE:
@@ -339,7 +319,7 @@
}
}
- retry_write:
+ retry_write:
if (!is_msgend(i2c)) {
byte = i2c->msg->buf[i2c->msg_ptr++];
@@ -359,9 +339,9 @@
dev_dbg(i2c->dev, "WRITE: Next Message\n");
i2c->msg_ptr = 0;
- i2c->msg_idx ++;
+ i2c->msg_idx++;
i2c->msg++;
-
+
/* check to see if we need to do another message */
if (i2c->msg->flags & I2C_M_NOSTART) {
@@ -375,7 +355,6 @@
goto retry_write;
} else {
-
/* send the new start */
s3c24xx_i2c_message_start(i2c, i2c->msg);
i2c->state = STATE_START;
@@ -389,7 +368,7 @@
break;
case STATE_READ:
- /* we have a byte of data in the data register, do
+ /* we have a byte of data in the data register, do
* something with it, and then work out wether we are
* going to do any more read/write
*/
@@ -397,13 +376,13 @@
byte = readb(i2c->regs + S3C2410_IICDS);
i2c->msg->buf[i2c->msg_ptr++] = byte;
- prepare_read:
+ prepare_read:
if (is_msglast(i2c)) {
/* last byte of buffer */
if (is_lastmsg(i2c))
s3c24xx_i2c_disable_ack(i2c);
-
+
} else if (is_msgend(i2c)) {
/* ok, we've read the entire buffer, see if there
* is anything else we need to do */
@@ -429,7 +408,7 @@
/* acknowlegde the IRQ and get back on with the work */
out_ack:
- tmp = readl(i2c->regs + S3C2410_IICCON);
+ tmp = readl(i2c->regs + S3C2410_IICCON);
tmp &= ~S3C2410_IICCON_IRQPEND;
writel(tmp, i2c->regs + S3C2410_IICCON);
out:
@@ -450,19 +429,19 @@
status = readl(i2c->regs + S3C2410_IICSTAT);
if (status & S3C2410_IICSTAT_ARBITR) {
- // deal with arbitration loss
+ /* deal with arbitration loss */
dev_err(i2c->dev, "deal with arbitration loss\n");
}
if (i2c->state == STATE_IDLE) {
dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
- tmp = readl(i2c->regs + S3C2410_IICCON);
+ tmp = readl(i2c->regs + S3C2410_IICCON);
tmp &= ~S3C2410_IICCON_IRQPEND;
writel(tmp, i2c->regs + S3C2410_IICCON);
goto out;
}
-
+
/* pretty much this leaves us with the fact that we've
* transmitted or received whatever byte we last sent */
@@ -485,16 +464,13 @@
while (timeout-- > 0) {
iicstat = readl(i2c->regs + S3C2410_IICSTAT);
-
+
if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
return 0;
msleep(1);
}
- dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
- __raw_readl(S3C2410_GPEDAT));
-
return -ETIMEDOUT;
}
@@ -503,7 +479,8 @@
* this starts an i2c transfer
*/
-static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
+static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
+ struct i2c_msg *msgs, int num)
{
unsigned long timeout;
int ret;
@@ -511,6 +488,15 @@
if (i2c->suspended)
return -EIO;
+ if (i2c->suspended) {
+ dev_err(i2c->dev,
+ "Hey I am still asleep (suspended: %d), retry later\n",
+ i2c->suspended);
+ dump_stack();
+ ret = -EAGAIN;
+ goto out;
+ }
+
ret = s3c24xx_i2c_set_master(i2c);
if (ret != 0) {
dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
@@ -529,12 +515,12 @@
s3c24xx_i2c_enable_irq(i2c);
s3c24xx_i2c_message_start(i2c, msgs);
spin_unlock_irq(&i2c->lock);
-
+
timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
ret = i2c->msg_idx;
- /* having these next two as dev_err() makes life very
+ /* having these next two as dev_err() makes life very
* noisy when doing an i2cdetect */
if (timeout == 0)
@@ -591,19 +577,6 @@
.functionality = s3c24xx_i2c_func,
};
-static struct s3c24xx_i2c s3c24xx_i2c = {
- .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
- .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
- .tx_setup = 50,
- .adap = {
- .name = "s3c2410-i2c",
- .owner = THIS_MODULE,
- .algo = &s3c24xx_i2c_algorithm,
- .retries = 2,
- .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
- },
-};
-
/* s3c24xx_i2c_calcdivisor
*
* return the divisor settings for a given frequency
@@ -643,7 +616,7 @@
{
int diff = freq - wanted;
- return (diff >= -2 && diff <= 2);
+ return diff >= -2 && diff <= 2;
}
/* s3c24xx_i2c_clockrate
@@ -655,7 +628,7 @@
static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
{
- struct s3c2410_platform_i2c *pdata;
+ struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
unsigned long clkin = clk_get_rate(i2c->clk);
unsigned int divs, div1;
u32 iiccon;
@@ -663,10 +636,8 @@
int start, end;
i2c->clkrate = clkin;
-
- pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
clkin /= 1000; /* clkin now in KHz */
-
+
dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
@@ -774,7 +745,7 @@
/* s3c24xx_i2c_init
*
- * initialise the controller, set the IO lines and frequency
+ * initialise the controller, set the IO lines and frequency
*/
static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
@@ -785,15 +756,15 @@
/* get the plafrom data */
- pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
+ pdata = i2c->dev->platform_data;
/* inititalise the gpio */
- s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
- s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
+ if (pdata->cfg_gpio)
+ pdata->cfg_gpio(to_platform_device(i2c->dev));
/* write slave address */
-
+
writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
@@ -831,12 +802,32 @@
static int s3c24xx_i2c_probe(struct platform_device *pdev)
{
- struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
+ struct s3c24xx_i2c *i2c;
struct s3c2410_platform_i2c *pdata;
struct resource *res;
int ret;
- pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data\n");
+ return -EINVAL;
+ }
+
+ i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
+ if (!i2c) {
+ dev_err(&pdev->dev, "no memory for state\n");
+ return -ENOMEM;
+ }
+
+ strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
+ i2c->adap.owner = THIS_MODULE;
+ i2c->adap.algo = &s3c24xx_i2c_algorithm;
+ i2c->adap.retries = 2;
+ i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+ i2c->tx_setup = 50;
+
+ spin_lock_init(&i2c->lock);
+ init_waitqueue_head(&i2c->wait);
/* find the clock and enable it */
@@ -878,7 +869,8 @@
goto err_ioarea;
}
- dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
+ dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
+ i2c->regs, i2c->ioarea, res);
/* setup info block for the i2c core */
@@ -892,29 +884,23 @@
goto err_iomap;
/* find the IRQ for this unit (note, this relies on the init call to
- * ensure no current IRQs pending
+ * ensure no current IRQs pending
*/
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (res == NULL) {
+ i2c->irq = ret = platform_get_irq(pdev, 0);
+ if (ret <= 0) {
dev_err(&pdev->dev, "cannot find IRQ\n");
- ret = -ENOENT;
goto err_iomap;
}
- ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
- pdev->name, i2c);
+ ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
+ dev_name(&pdev->dev), i2c);
if (ret != 0) {
- dev_err(&pdev->dev, "cannot claim IRQ\n");
+ dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
goto err_iomap;
}
- i2c->irq = res;
-
- dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
- (unsigned long)res->start);
-
ret = s3c24xx_i2c_register_cpufreq(i2c);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
@@ -944,7 +930,7 @@
s3c24xx_i2c_deregister_cpufreq(i2c);
err_irq:
- free_irq(i2c->irq->start, i2c);
+ free_irq(i2c->irq, i2c);
err_iomap:
iounmap(i2c->regs);
@@ -958,6 +944,7 @@
clk_put(i2c->clk);
err_noclk:
+ kfree(i2c);
return ret;
}
@@ -973,7 +960,7 @@
s3c24xx_i2c_deregister_cpufreq(i2c);
i2c_del_adapter(&i2c->adap);
- free_irq(i2c->irq->start, i2c);
+ free_irq(i2c->irq, i2c);
clk_disable(i2c->clk);
clk_put(i2c->clk);
@@ -982,6 +969,7 @@
release_resource(i2c->ioarea);
kfree(i2c->ioarea);
+ kfree(i2c);
return 0;
}
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -455,11 +455,12 @@
I2C bus.
config I2C_S3C2410
- tristate "S3C2410 I2C Driver"
- depends on ARCH_S3C2410
+ tristate "Samsung SoC I2C Driver (S3C24XX and S3C64XX series)"
+ depends on ARCH_S3C2410 || ARCH_S3C64XX
help
Say Y here to include support for I2C controller in the
- Samsung S3C2410 based System-on-Chip devices.
+ Samsung S3C based System-on-Chip devices such as the S3C2410,
+ S3C2440, S3C2442, S3C2443 and S3C6410.
config I2C_SH7760
tristate "Renesas SH7760 I2C Controller"
--- a/drivers/i2c/chips/Kconfig
+++ b/drivers/i2c/chips/Kconfig
@@ -53,6 +53,26 @@
This driver can also be built as a module. If so, the module
will be called eeprom.
+config SENSORS_PCF50606
+ tristate "Philips/NXP PCF50606"
+ depends on I2C
+ help
+ If you say yes here you get support for Philips/NXP PCF50606
+ PMU (Power Management Unit) chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called pcf50606.
+
+config SENSORS_PCF50633
+ tristate "Philips PCF50633"
+ depends on I2C
+ help
+ If you say yes here you get support for Philips PCF50633
+ PMU (Power Management Unit) chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called pcf50633.
+
config SENSORS_PCF8574
tristate "Philips PCF8574 and PCF8574A (DEPRECATED)"
depends on EXPERIMENTAL && GPIO_PCF857X = "n"
@@ -185,4 +205,23 @@
also register MCU GPIOs with the generic GPIO API, so you'll able
to use MCU pins as GPIOs.
+config SENSORS_TSL256X
+ tristate "Texas TSL256X Ambient Light Sensor"
+ depends on I2C
+ help
+ If you say yes here you get support for the Texas TSL256X
+ ambient light sensor chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called tsl256x.
+
+config PCA9632
+ tristate "Philips/NXP PCA9632 low power LED driver"
+ depends on I2C
+ help
+ If you say yes here you get support for the Philips/NXP PCA9632
+ LED driver.
+
+ This driver can also be built as a module. If so, the module
+ will be called pca9632.
endmenu
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -15,6 +15,8 @@
obj-$(CONFIG_SENSORS_EEPROM) += eeprom.o
obj-$(CONFIG_SENSORS_MAX6875) += max6875.o
obj-$(CONFIG_SENSORS_PCA9539) += pca9539.o
+obj-$(CONFIG_SENSORS_PCF50606) += pcf50606.o
+obj-$(CONFIG_SENSORS_PCF50633) += pcf50633.o
obj-$(CONFIG_SENSORS_PCF8574) += pcf8574.o
obj-$(CONFIG_PCF8575) += pcf8575.o
obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o
@@ -23,6 +25,8 @@
obj-$(CONFIG_MENELAUS) += menelaus.o
obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o
obj-$(CONFIG_MCU_MPC8349EMITX) += mcu_mpc8349emitx.o
+obj-$(CONFIG_SENSORS_TSL256X) += tsl256x.o
+obj-$(CONFIG_PCA9632) += pca9632.o
ifeq ($(CONFIG_I2C_DEBUG_CHIP),y)
EXTRA_CFLAGS += -DDEBUG
--- /dev/null
+++ b/drivers/i2c/chips/pca9632.c
@@ -0,0 +1,551 @@
+/*
+ * Philips/NXP PCA9632 low power LED driver.
+ * Copyright (C) 2008 Matt Hsu <matt_hsu@openmoko.org>
+ *
+ * low_level implementation are based on pcf50606 driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * TODO:
+ * - attach ledclass??
+ * - add platform data
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+
+#include "pca9632.h"
+
+/* Addresses to scan */
+static unsigned short normal_i2c[] = { 0x62, I2C_CLIENT_END };
+
+/* Insmod parameters */
+I2C_CLIENT_INSMOD_1(pca9632);
+
+enum pca9632_pwr_state {
+ PCA9632_NORMAL,
+ PCA9632_SLEEP,
+};
+
+enum pca9632_led_output {
+ PCA9632_OFF,
+ PCA9632_ON,
+ PCA9632_CTRL_BY_PWM,
+ PCA9632_CTRL_BY_PWM_GRPPWM,
+};
+
+static const char *led_output_name[] = {
+ [PCA9632_OFF] = "off",
+ [PCA9632_ON] = "fully-on",
+ [PCA9632_CTRL_BY_PWM] = "ctrl-by-pwm",
+ [PCA9632_CTRL_BY_PWM_GRPPWM] = "ctrl-by-pwm-grppwm",
+};
+
+struct pca9632_data {
+ struct i2c_client client;
+ struct mutex lock;
+};
+
+static struct i2c_driver pca9632_driver;
+static struct platform_device *pca9632_pdev;
+
+static int pca9632_attach_adapter(struct i2c_adapter *adapter);
+static int pca9632_detach_client(struct i2c_client *client);
+
+static int __reg_write(struct pca9632_data *pca, u_int8_t reg, u_int8_t val)
+{
+ return i2c_smbus_write_byte_data(&pca->client, reg, val);
+}
+
+static int reg_write(struct pca9632_data *pca, u_int8_t reg, u_int8_t val)
+{
+ int ret;
+
+ mutex_lock(&pca->lock);
+ ret = __reg_write(pca, reg, val);
+ mutex_unlock(&pca->lock);
+
+ return ret;
+}
+
+static int32_t __reg_read(struct pca9632_data *pca, u_int8_t reg)
+{
+ int32_t ret;
+
+ ret = i2c_smbus_read_byte_data(&pca->client, reg);
+
+ return ret;
+}
+
+static u_int8_t reg_read(struct pca9632_data *pca, u_int8_t reg)
+{
+ int32_t ret;
+
+ mutex_lock(&pca->lock);
+ ret = __reg_read(pca, reg);
+ mutex_unlock(&pca->lock);
+
+ return ret & 0xff;
+}
+
+static int reg_set_bit_mask(struct pca9632_data *pca,
+ u_int8_t reg, u_int8_t mask, u_int8_t val)
+{
+ int ret;
+ u_int8_t tmp;
+
+ val &= mask;
+
+ mutex_lock(&pca->lock);
+
+ tmp = __reg_read(pca, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ ret = __reg_write(pca, reg, tmp);
+
+ mutex_unlock(&pca->lock);
+
+ return ret;
+}
+
+static inline int calc_dc(uint8_t idc)
+{
+ return (idc * 100) / 256;
+}
+
+/*
+ * Software reset
+ */
+static int software_rst(struct i2c_adapter *adapter)
+{
+ u8 buf[] = { 0xa5, 0x5a };
+
+ struct i2c_msg msg[] = {
+ {
+ .addr = 0x3,
+ .flags = 0,
+ .buf = &buf,
+ .len = sizeof(buf)
+ }
+ };
+
+ return i2c_transfer(adapter, msg, 1);
+}
+
+/*
+ * Group dmblnk control
+ */
+static void config_group_dmblnk(struct pca9632_data *pca, int group_dmblnk_mode)
+{
+ reg_set_bit_mask(pca, PCA9632_REG_MODE2, 0x20,
+ group_dmblnk_mode << PCA9632_DMBLNK_SHIFT);
+}
+
+static int get_group_dmblnk(struct pca9632_data *pca)
+{
+ return reg_read(pca, PCA9632_REG_MODE2) >> PCA9632_DMBLNK_SHIFT;
+}
+
+static ssize_t show_group_dmblnk(struct device *dev, struct device_attribute
+ *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+
+ if (get_group_dmblnk(pca))
+ return sprintf(buf, "blinking\n");
+ else
+ return sprintf(buf, "dimming\n");
+}
+
+static ssize_t set_group_dmblnk(struct device *dev, struct device_attribute
+ *attr, const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+ unsigned int mode = simple_strtoul(buf, NULL, 10);
+
+ if (mode)
+ dev_info(&pca->client.dev, "blinking\n");
+ else
+ dev_info(&pca->client.dev, "dimming\n");
+
+ config_group_dmblnk(pca, mode);
+
+ return count;
+}
+
+static DEVICE_ATTR(group_dmblnk, S_IRUGO | S_IWUSR, show_group_dmblnk,
+ set_group_dmblnk);
+
+static int reg_id_by_name(const char *name)
+{
+ int reg_id = -1;
+
+ if (!strncmp(name, "led0", 4))
+ reg_id = PCA9632_REG_PWM0;
+ else if (!strncmp(name, "led1", 4))
+ reg_id = PCA9632_REG_PWM1;
+ else if (!strncmp(name, "led2", 4))
+ reg_id = PCA9632_REG_PWM2;
+ else if (!strncmp(name, "led3", 4))
+ reg_id = PCA9632_REG_PWM3;
+
+ return reg_id;
+}
+
+static int get_led_output(struct pca9632_data *pca, int ldrx)
+{
+ u_int8_t led_state;
+
+ ldrx = ldrx - 2;
+ led_state = reg_read(pca, PCA9632_REG_LEDOUT);
+ led_state = (led_state >> (2 * ldrx)) & 0x03;
+
+ return led_state;
+}
+
+static void config_led_output(struct pca9632_data *pca, int ldrx,
+ enum pca9632_led_output led_output)
+{
+ u_int8_t mask;
+ int tmp;
+
+ ldrx = ldrx - 2;
+ mask = 0x03 << (2 * ldrx);
+ tmp = reg_set_bit_mask(pca, PCA9632_REG_LEDOUT,
+ mask, led_output << (2 * ldrx));
+}
+
+/*
+ * Individual brightness control
+ */
+static ssize_t show_brightness(struct device *dev, struct device_attribute
+ *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+ int ldrx;
+
+ ldrx = reg_id_by_name(attr->attr.name);
+
+ switch (get_led_output(pca, ldrx)) {
+
+ case PCA9632_OFF:
+ case PCA9632_ON:
+ return sprintf(buf, "%s",
+ led_output_name[get_led_output(pca, ldrx)]);
+
+ case PCA9632_CTRL_BY_PWM:
+ return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca, ldrx)));
+
+ case PCA9632_CTRL_BY_PWM_GRPPWM:
+ /* check group dmblnk */
+ if (get_group_dmblnk(pca))
+ return sprintf(buf, "%d%% \n",
+ calc_dc(reg_read(pca, ldrx)));
+ return sprintf(buf, "%d%% \n",
+ calc_dc((reg_read(pca, ldrx) & 0xfc)));
+ default:
+ break;
+ }
+
+ return sprintf(buf, "invalid argument\n");
+}
+
+static ssize_t set_brightness(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+ unsigned int pwm = simple_strtoul(buf, NULL, 10);
+ int ldrx;
+
+ ldrx = reg_id_by_name(attr->attr.name);
+ reg_set_bit_mask(pca, ldrx, 0xff, pwm);
+
+ return count;
+}
+
+static
+DEVICE_ATTR(led0_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
+static
+DEVICE_ATTR(led1_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
+static
+DEVICE_ATTR(led2_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
+static
+DEVICE_ATTR(led3_pwm, S_IRUGO | S_IWUSR, show_brightness, set_brightness);
+
+/*
+ * Group frequency control
+ */
+static ssize_t show_group_freq(struct device *dev, struct device_attribute
+ *attr, char *buf)
+{
+ uint32_t period;
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+
+ period = ((reg_read(pca, PCA9632_REG_GRPFREQ) + 1) * 1000) / 24;
+
+ return sprintf(buf, "%d ms\n", period);
+}
+
+static ssize_t set_group_freq(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+
+ unsigned int freq = simple_strtoul(buf, NULL, 10);
+ reg_write(pca, PCA9632_REG_GRPFREQ, freq);
+ return count;
+}
+
+static
+DEVICE_ATTR(group_freq, S_IRUGO | S_IWUSR, show_group_freq, set_group_freq);
+
+/*
+ * Group duty cycle tonrol*
+ */
+static ssize_t show_group_dc(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+
+ if (get_group_dmblnk(pca)) {
+
+ if (reg_read(pca, PCA9632_REG_GRPFREQ) <= 0x03)
+ return sprintf(buf, "%d%% \n",
+ calc_dc(reg_read(pca, PCA9632_REG_GRPPWM) & 0xfc));
+
+ return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca,
+ PCA9632_REG_GRPPWM)));
+ }
+
+ return sprintf(buf, "%d%% \n", calc_dc(reg_read(pca,
+ PCA9632_REG_GRPPWM) & 0xf0));
+}
+
+static ssize_t set_group_dc(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+
+ unsigned int dc = simple_strtoul(buf, NULL, 10);
+
+ reg_set_bit_mask(pca, PCA9632_REG_GRPPWM, 0xff, dc);
+
+ return count;
+}
+
+static DEVICE_ATTR(group_dc, S_IRUGO | S_IWUSR, show_group_dc, set_group_dc);
+
+/*
+ * LED driver output
+ */
+static ssize_t show_led_output(struct device *dev, struct device_attribute
+ *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+ int ldrx;
+
+ ldrx = reg_id_by_name(attr->attr.name);
+
+ return sprintf(buf, "%s \n",
+ led_output_name[get_led_output(pca, ldrx)]);
+
+}
+static ssize_t set_led_output(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pca9632_data *pca = i2c_get_clientdata(client);
+ enum pca9632_led_output led_output;
+ int ldrx;
+
+ led_output = simple_strtoul(buf, NULL, 10);
+ ldrx = reg_id_by_name(attr->attr.name);
+ config_led_output(pca, ldrx, led_output);
+
+ return count;
+}
+
+static
+DEVICE_ATTR(led0_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
+static
+DEVICE_ATTR(led1_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
+static
+DEVICE_ATTR(led2_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
+static
+DEVICE_ATTR(led3_output, S_IRUGO | S_IWUSR, show_led_output, set_led_output);
+
+static struct attribute *pca_sysfs_entries[] = {
+ &dev_attr_group_dmblnk.attr,
+ &dev_attr_led0_pwm.attr,
+ &dev_attr_led1_pwm.attr,
+ &dev_attr_led2_pwm.attr,
+ &dev_attr_led3_pwm.attr,
+ &dev_attr_group_dc.attr,
+ &dev_attr_group_freq.attr,
+ &dev_attr_led0_output.attr,
+ &dev_attr_led1_output.attr,
+ &dev_attr_led2_output.attr,
+ &dev_attr_led3_output.attr,
+ NULL
+};
+
+static struct attribute_group pca_attr_group = {
+ .name = NULL, /* put in device directory */
+ .attrs = pca_sysfs_entries,
+};
+
+#ifdef CONFIG_PM
+static int pca9632_suspend(struct device *dev, pm_message_t state)
+{
+ /* FIXME: Not implemented */
+ return 0;
+}
+
+static int pca9632_resume(struct device *dev)
+{
+ /* FIXME: Not implemented */
+ return 0;
+}
+#else
+#define pca9632_suspend NULL
+#define pca9632_resume NULL
+#endif
+
+static struct i2c_driver pca9632_driver = {
+ .driver = {
+ .name = "pca9632",
+ .suspend = pca9632_suspend,
+ .resume = pca9632_resume,
+ },
+ .id = I2C_DRIVERID_PCA9632,
+ .attach_adapter = pca9632_attach_adapter,
+ .detach_client = pca9632_detach_client,
+};
+
+static int pca9632_detect(struct i2c_adapter *adapter, int address, int kind)
+{
+ struct i2c_client *new_client;
+ struct pca9632_data *pca;
+ int err;
+
+ pca = kzalloc(sizeof(struct pca9632_data), GFP_KERNEL);
+ if (!pca)
+ return -ENOMEM;
+
+ mutex_init(&pca->lock);
+
+ new_client = &pca->client;
+ i2c_set_clientdata(new_client, pca);
+ new_client->addr = address;
+ new_client->adapter = adapter;
+ new_client->driver = &pca9632_driver;
+ new_client->flags = 0;
+
+ strlcpy(new_client->name, "pca9632", I2C_NAME_SIZE);
+
+ /* register with i2c core */
+ err = i2c_attach_client(new_client);
+ if (err)
+ goto exit_kfree;
+
+ err = sysfs_create_group(&new_client->dev.kobj, &pca_attr_group);
+ if (err)
+ goto exit_detach;
+
+ /* software reset */
+ if (!software_rst(adapter))
+ dev_info(&pca->client.dev, "pca9632 sw-rst done\n");
+
+ /* enter normal mode */
+ reg_set_bit_mask(pca, PCA9632_REG_MODE1, 0x10, PCA9632_NORMAL);
+
+ return 0;
+
+exit_detach:
+ i2c_detach_client(new_client);
+exit_kfree:
+ kfree(pca);
+
+ return err;
+}
+
+static int pca9632_attach_adapter(struct i2c_adapter *adapter)
+{
+ return i2c_probe(adapter, &addr_data, pca9632_detect);
+}
+
+static int pca9632_detach_client(struct i2c_client *client)
+{
+ int err;
+
+ sysfs_remove_group(&client->dev.kobj, &pca_attr_group);
+ err = i2c_detach_client(client);
+
+ if (err)
+ return err;
+
+ kfree(i2c_get_clientdata(client));
+
+ return 0;
+}
+
+static int __init pca9632_plat_probe(struct platform_device *pdev)
+{
+ /* FIXME: platform data should be attached here */
+ pca9632_pdev = pdev;
+
+ return 0;
+}
+
+static int pca9632_plat_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver pca9632_plat_driver = {
+ .probe = pca9632_plat_probe,
+ .remove = pca9632_plat_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "pca9632",
+ },
+};
+
+static int __init pca9632_init(void)
+{
+ int rc;
+
+ rc = platform_driver_register(&pca9632_plat_driver);
+ if (!rc)
+ i2c_add_driver(&pca9632_driver);
+
+ return rc;
+}
+
+static void __exit pca9632_exit(void)
+{
+ i2c_del_driver(&pca9632_driver);
+
+ platform_driver_unregister(&pca9632_plat_driver);
+}
+
+MODULE_AUTHOR("Matt Hsu <matt_hsu@openmoko.org>");
+MODULE_DESCRIPTION("NXP PCA9632 driver");
+MODULE_LICENSE("GPL");
+
+module_init(pca9632_init);
+module_exit(pca9632_exit);
--- /dev/null
+++ b/drivers/i2c/chips/pca9632.h
@@ -0,0 +1,24 @@
+#ifndef _PCA9632_H
+#define _PCA9632_H
+
+
+enum pca9632_regs{
+
+ PCA9632_REG_MODE1 = 0x00,
+ PCA9632_REG_MODE2 = 0x01,
+ PCA9632_REG_PWM0 = 0x02,
+ PCA9632_REG_PWM1 = 0x03,
+ PCA9632_REG_PWM2 = 0x04,
+ PCA9632_REG_PWM3 = 0x05,
+ PCA9632_REG_GRPPWM = 0x06,
+ PCA9632_REG_GRPFREQ = 0x07,
+ PCA9632_REG_LEDOUT = 0x08,
+ PCA9632_REG_SUBADDR1 = 0x09,
+ PCA9632_REG_SUBADDR2 = 0x0a,
+ PCA9632_REG_SUBADDR3 = 0x0b,
+ PCA9632_REG_ALLCALLADR1 = 0x0c,
+};
+
+#define PCA9632_DMBLNK_SHIFT 5
+
+#endif /* _PCA9632_H */
--- /dev/null
+++ b/drivers/i2c/chips/pcf50606.c
@@ -0,0 +1,2193 @@
+/* Philips/NXP PCF50606 Power Management Unit (PMU) driver
+ *
+ * (C) 2006-2007 by Openmoko, Inc.
+ * Authors: Harald Welte <laforge@openmoko.org>,
+ * Matt Hsu <matt@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This driver is a monster ;) It provides the following features
+ * - voltage control for a dozen different voltage domains
+ * - charging control for main and backup battery
+ * - rtc / alarm
+ * - watchdog
+ * - adc driver (hw_sensors like)
+ * - pwm driver
+ * - backlight
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/watchdog.h>
+#include <linux/miscdevice.h>
+#include <linux/input.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/pcf50606.h>
+#include <linux/apm-emulation.h>
+
+#include <asm/mach-types.h>
+#include <mach/gta01.h>
+
+#include "pcf50606.h"
+
+/* we use dev_dbg() throughout the code, but sometimes don't want to
+ * write an entire line of debug related information. This DEBUGPC
+ * macro is a continuation for dev_dbg() */
+#ifdef DEBUG
+#define DEBUGPC(x, args ...) printk(x, ## args)
+#else
+#define DEBUGPC(x, args ...)
+#endif
+
+/***********************************************************************
+ * Static data / structures
+ ***********************************************************************/
+
+static unsigned short normal_i2c[] = { 0x08, I2C_CLIENT_END };
+
+I2C_CLIENT_INSMOD_1(pcf50606);
+
+#define PCF50606_B_CHG_FAST 0 /* Charger Fast allowed */
+#define PCF50606_B_CHG_PRESENT 1 /* Charger present */
+#define PCF50606_B_CHG_FOK 2 /* Fast OK for battery */
+#define PCF50606_B_CHG_ERR 3 /* Charger Error */
+#define PCF50606_B_CHG_PROT 4 /* Charger Protection */
+#define PCF50606_B_CHG_READY 5 /* Charging completed */
+
+#define PCF50606_F_CHG_FAST (1<<PCF50606_B_CHG_FAST)
+#define PCF50606_F_CHG_PRESENT (1<<PCF50606_B_CHG_PRESENT)
+#define PCF50606_F_CHG_FOK (1<<PCF50606_B_CHG_FOK)
+#define PCF50606_F_CHG_ERR (1<<PCF50606_B_CHG_ERR)
+#define PCF50606_F_CHG_PROT (1<<PCF50606_B_CHG_PROT)
+#define PCF50606_F_CHG_READY (1<<PCF50606_B_CHG_READY)
+#define PCF50606_F_CHG_MASK 0x000000fc
+
+#define PCF50606_F_PWR_PRESSED 0x00000100
+#define PCF50606_F_RTC_SECOND 0x00000200
+
+enum close_state {
+ CLOSE_STATE_NOT,
+ CLOSE_STATE_ALLOW = 0x2342,
+};
+
+enum pcf50606_suspend_states {
+ PCF50606_SS_RUNNING,
+ PCF50606_SS_STARTING_SUSPEND,
+ PCF50606_SS_COMPLETED_SUSPEND,
+ PCF50606_SS_RESUMING_BUT_NOT_US_YET,
+ PCF50606_SS_STARTING_RESUME,
+ PCF50606_SS_COMPLETED_RESUME,
+};
+
+struct pcf50606_data {
+ struct i2c_client client;
+ struct pcf50606_platform_data *pdata;
+ struct backlight_device *backlight;
+ struct mutex lock;
+ unsigned int flags;
+ unsigned int working;
+ struct mutex working_lock;
+ struct work_struct work;
+ struct rtc_device *rtc;
+ struct input_dev *input_dev;
+ int allow_close;
+ int onkey_seconds;
+ int irq;
+ int coldplug_done;
+ int suppress_onkey_events;
+ enum pcf50606_suspend_states suspend_state;
+#ifdef CONFIG_PM
+ struct {
+ u_int8_t dcdc1, dcdc2;
+ u_int8_t dcdec1;
+ u_int8_t dcudc1;
+ u_int8_t ioregc;
+ u_int8_t d1regc1;
+ u_int8_t d2regc1;
+ u_int8_t d3regc1;
+ u_int8_t lpregc1;
+ u_int8_t adcc1, adcc2;
+ u_int8_t pwmc1;
+ u_int8_t int1m, int2m, int3m;
+ } standby_regs;
+#endif
+};
+
+static struct i2c_driver pcf50606_driver;
+
+/* This is an ugly construct on how to access the (currently single/global)
+ * pcf50606 handle from other code in the kernel. I didn't really come up with
+ * a more decent method of dynamically resolving this */
+struct pcf50606_data *pcf50606_global;
+EXPORT_SYMBOL_GPL(pcf50606_global);
+
+static struct platform_device *pcf50606_pdev;
+
+/* This is a 10k, B=3370 NTC Thermistor -10..79 centigrade */
+/* Table entries are offset by +0.5C so a properly rounded value is generated */
+static const u_int16_t ntc_table_10k_3370B[] = {
+ /* -10 */
+ 43888, 41819, 39862, 38010, 36257, 34596, 33024, 31534, 30121, 28781,
+ 27510, 26304, 25159, 24071, 23038, 22056, 21122, 20234, 19390, 18586,
+ 17821, 17093, 16399, 15738, 15107, 14506, 13933, 13387, 12865, 12367,
+ 11891, 11437, 11003, 10588, 10192, 9813, 9450, 9103, 8771, 8453,
+ 8149, 7857, 7578, 7310, 7054, 6808, 6572, 6346, 6129, 5920,
+ 5720, 5528, 5344, 5167, 4996, 4833, 4675, 4524, 4379, 4239,
+ 4104, 3975, 3850, 3730, 3614, 3503, 3396, 3292, 3193, 3097,
+ 3004, 2915, 2829, 2745, 2665, 2588, 2513, 2441, 2371, 2304,
+ 2239, 2176, 2116, 2057, 2000, 1945, 1892, 1841, 1791, 1743,
+};
+
+
+/***********************************************************************
+ * Low-Level routines
+ ***********************************************************************/
+
+static inline int __reg_write(struct pcf50606_data *pcf, u_int8_t reg,
+ u_int8_t val)
+{
+ if (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND) {
+ dev_err(&pcf->client.dev, "__reg_write while suspended.\n");
+ dump_stack();
+ }
+ return i2c_smbus_write_byte_data(&pcf->client, reg, val);
+}
+
+static int reg_write(struct pcf50606_data *pcf, u_int8_t reg, u_int8_t val)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = __reg_write(pcf, reg, val);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+
+static inline int32_t __reg_read(struct pcf50606_data *pcf, u_int8_t reg)
+{
+ int32_t ret;
+
+ if (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND) {
+ dev_err(&pcf->client.dev, "__reg_read while suspended.\n");
+ dump_stack();
+ }
+ ret = i2c_smbus_read_byte_data(&pcf->client, reg);
+
+ return ret;
+}
+
+static u_int8_t reg_read(struct pcf50606_data *pcf, u_int8_t reg)
+{
+ int32_t ret;
+
+ mutex_lock(&pcf->lock);
+ ret = __reg_read(pcf, reg);
+ mutex_unlock(&pcf->lock);
+
+ return ret & 0xff;
+}
+
+static int reg_set_bit_mask(struct pcf50606_data *pcf,
+ u_int8_t reg, u_int8_t mask, u_int8_t val)
+{
+ int ret;
+ u_int8_t tmp;
+
+ val &= mask;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = __reg_read(pcf, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ ret = __reg_write(pcf, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+
+static int reg_clear_bits(struct pcf50606_data *pcf, u_int8_t reg, u_int8_t val)
+{
+ int ret;
+ u_int8_t tmp;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = __reg_read(pcf, reg);
+ tmp &= ~val;
+ ret = __reg_write(pcf, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+
+/* synchronously read one ADC channel (busy-wait for result to be complete) */
+static u_int16_t adc_read(struct pcf50606_data *pcf, int channel,
+ u_int16_t *data2)
+{
+ u_int8_t adcs2, adcs1;
+ u_int16_t ret;
+
+ dev_dbg(&pcf->client.dev, "entering (pcf=%p, channel=%u, data2=%p)\n",
+ pcf, channel, data2);
+
+ channel &= PCF50606_ADCC2_ADCMUX_MASK;
+
+ mutex_lock(&pcf->lock);
+
+ /* start ADC conversion of selected channel */
+ __reg_write(pcf, PCF50606_REG_ADCC2, channel |
+ PCF50606_ADCC2_ADCSTART | PCF50606_ADCC2_RES_10BIT);
+
+ do {
+ adcs2 = __reg_read(pcf, PCF50606_REG_ADCS2);
+ } while (!(adcs2 & PCF50606_ADCS2_ADCRDY));
+
+ adcs1 = __reg_read(pcf, PCF50606_REG_ADCS1);
+ ret = (adcs1 << 2) | (adcs2 & 0x03);
+
+ if (data2) {
+ adcs1 = __reg_read(pcf, PCF50606_REG_ADCS3);
+ *data2 = (adcs1 << 2) | ((adcs2 & 0x0c) >> 2);
+ }
+
+ mutex_unlock(&pcf->lock);
+
+ dev_dbg(&pcf->client.dev, "returning %u %u\n", ret,
+ data2 ? *data2 : 0);
+
+ return ret;
+}
+
+/***********************************************************************
+ * Voltage / ADC
+ ***********************************************************************/
+
+static u_int8_t dcudc_voltage(unsigned int millivolts)
+{
+ if (millivolts < 900)
+ return 0;
+ if (millivolts > 5500)
+ return 0x1f;
+ if (millivolts <= 3300) {
+ millivolts -= 900;
+ return millivolts/300;
+ }
+ if (millivolts < 4000)
+ return 0x0f;
+ else {
+ millivolts -= 4000;
+ return millivolts/100;
+ }
+}
+
+static unsigned int dcudc_2voltage(u_int8_t bits)
+{
+ bits &= 0x1f;
+ if (bits < 0x08)
+ return 900 + bits * 300;
+ else if (bits < 0x10)
+ return 3300;
+ else
+ return 4000 + bits * 100;
+}
+
+static u_int8_t dcdec_voltage(unsigned int millivolts)
+{
+ if (millivolts < 900)
+ return 0;
+ else if (millivolts > 3300)
+ return 0x0f;
+
+ millivolts -= 900;
+ return millivolts/300;
+}
+
+static unsigned int dcdec_2voltage(u_int8_t bits)
+{
+ bits &= 0x0f;
+ return 900 + bits*300;
+}
+
+static u_int8_t dcdc_voltage(unsigned int millivolts)
+{
+ if (millivolts < 900)
+ return 0;
+ else if (millivolts > 3600)
+ return 0x1f;
+
+ if (millivolts < 1500) {
+ millivolts -= 900;
+ return millivolts/25;
+ } else {
+ millivolts -= 1500;
+ return 0x18 + millivolts/300;
+ }
+}
+
+static unsigned int dcdc_2voltage(u_int8_t bits)
+{
+ bits &= 0x1f;
+ if ((bits & 0x18) == 0x18)
+ return 1500 + ((bits & 0x7) * 300);
+ else
+ return 900 + (bits * 25);
+}
+
+static u_int8_t dx_voltage(unsigned int millivolts)
+{
+ if (millivolts < 900)
+ return 0;
+ else if (millivolts > 3300)
+ return 0x18;
+
+ millivolts -= 900;
+ return millivolts/100;
+}
+
+static unsigned int dx_2voltage(u_int8_t bits)
+{
+ bits &= 0x1f;
+ return 900 + (bits * 100);
+}
+
+static const u_int8_t regulator_registers[__NUM_PCF50606_REGULATORS] = {
+ [PCF50606_REGULATOR_DCD] = PCF50606_REG_DCDC1,
+ [PCF50606_REGULATOR_DCDE] = PCF50606_REG_DCDEC1,
+ [PCF50606_REGULATOR_DCUD] = PCF50606_REG_DCUDC1,
+ [PCF50606_REGULATOR_D1REG] = PCF50606_REG_D1REGC1,
+ [PCF50606_REGULATOR_D2REG] = PCF50606_REG_D2REGC1,
+ [PCF50606_REGULATOR_D3REG] = PCF50606_REG_D3REGC1,
+ [PCF50606_REGULATOR_LPREG] = PCF50606_REG_LPREGC1,
+ [PCF50606_REGULATOR_IOREG] = PCF50606_REG_IOREGC,
+};
+
+int pcf50606_onoff_set(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg, int on)
+{
+ u_int8_t addr;
+
+ if (reg >= __NUM_PCF50606_REGULATORS)
+ return -EINVAL;
+
+ /* IOREG cannot be powered off since it powers the PMU I2C */
+ if (reg == PCF50606_REGULATOR_IOREG)
+ return -EIO;
+
+ addr = regulator_registers[reg];
+
+ if (on == 0)
+ reg_set_bit_mask(pcf, addr, 0xe0, 0x00);
+ else
+ reg_set_bit_mask(pcf, addr, 0xe0, 0xe0);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50606_onoff_set);
+
+int pcf50606_onoff_get(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg)
+{
+ u_int8_t val, addr;
+
+ if (reg >= __NUM_PCF50606_REGULATORS)
+ return -EINVAL;
+
+ addr = regulator_registers[reg];
+ val = (reg_read(pcf, addr) & 0xe0) >> 5;
+
+ /* PWREN1 = 1, PWREN2 = 1, see table 16 of datasheet */
+ switch (val) {
+ case 0:
+ case 5:
+ return 0;
+ default:
+ return 1;
+ }
+}
+EXPORT_SYMBOL_GPL(pcf50606_onoff_get);
+
+int pcf50606_voltage_set(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg,
+ unsigned int millivolts)
+{
+ u_int8_t volt_bits;
+ u_int8_t regnr;
+ int rc;
+
+ dev_dbg(&pcf->client.dev, "pcf=%p, reg=%d, mvolts=%d\n", pcf, reg,
+ millivolts);
+
+ if (reg >= __NUM_PCF50606_REGULATORS)
+ return -EINVAL;
+
+ if (millivolts > pcf->pdata->rails[reg].voltage.max)
+ return -EINVAL;
+
+ switch (reg) {
+ case PCF50606_REGULATOR_DCD:
+ volt_bits = dcdc_voltage(millivolts);
+ rc = reg_set_bit_mask(pcf, PCF50606_REG_DCDC1, 0x1f,
+ volt_bits);
+ break;
+ case PCF50606_REGULATOR_DCDE:
+ volt_bits = dcdec_voltage(millivolts);
+ rc = reg_set_bit_mask(pcf, PCF50606_REG_DCDEC1, 0x0f,
+ volt_bits);
+ break;
+ case PCF50606_REGULATOR_DCUD:
+ volt_bits = dcudc_voltage(millivolts);
+ rc = reg_set_bit_mask(pcf, PCF50606_REG_DCUDC1, 0x1f,
+ volt_bits);
+ break;
+ case PCF50606_REGULATOR_D1REG:
+ case PCF50606_REGULATOR_D2REG:
+ case PCF50606_REGULATOR_D3REG:
+ regnr = PCF50606_REG_D1REGC1 + (reg - PCF50606_REGULATOR_D1REG);
+ volt_bits = dx_voltage(millivolts);
+ rc = reg_set_bit_mask(pcf, regnr, 0x1f, volt_bits);
+ break;
+ case PCF50606_REGULATOR_LPREG:
+ volt_bits = dx_voltage(millivolts);
+ rc = reg_set_bit_mask(pcf, PCF50606_REG_LPREGC1, 0x1f,
+ volt_bits);
+ break;
+ case PCF50606_REGULATOR_IOREG:
+ if (millivolts < 1800)
+ return -EINVAL;
+ volt_bits = dx_voltage(millivolts);
+ rc = reg_set_bit_mask(pcf, PCF50606_REG_IOREGC, 0x1f,
+ volt_bits);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pcf50606_voltage_set);
+
+unsigned int pcf50606_voltage_get(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg)
+{
+ u_int8_t volt_bits;
+ u_int8_t regnr;
+ unsigned int rc = 0;
+
+ if (reg >= __NUM_PCF50606_REGULATORS)
+ return -EINVAL;
+
+ switch (reg) {
+ case PCF50606_REGULATOR_DCD:
+ volt_bits = reg_read(pcf, PCF50606_REG_DCDC1) & 0x1f;
+ rc = dcdc_2voltage(volt_bits);
+ break;
+ case PCF50606_REGULATOR_DCDE:
+ volt_bits = reg_read(pcf, PCF50606_REG_DCDEC1) & 0x0f;
+ rc = dcdec_2voltage(volt_bits);
+ break;
+ case PCF50606_REGULATOR_DCUD:
+ volt_bits = reg_read(pcf, PCF50606_REG_DCUDC1) & 0x1f;
+ rc = dcudc_2voltage(volt_bits);
+ break;
+ case PCF50606_REGULATOR_D1REG:
+ case PCF50606_REGULATOR_D2REG:
+ case PCF50606_REGULATOR_D3REG:
+ regnr = PCF50606_REG_D1REGC1 + (reg - PCF50606_REGULATOR_D1REG);
+ volt_bits = reg_read(pcf, regnr) & 0x1f;
+ if (volt_bits > 0x18)
+ volt_bits = 0x18;
+ rc = dx_2voltage(volt_bits);
+ break;
+ case PCF50606_REGULATOR_LPREG:
+ volt_bits = reg_read(pcf, PCF50606_REG_LPREGC1) & 0x1f;
+ if (volt_bits > 0x18)
+ volt_bits = 0x18;
+ rc = dx_2voltage(volt_bits);
+ break;
+ case PCF50606_REGULATOR_IOREG:
+ volt_bits = reg_read(pcf, PCF50606_REG_IOREGC) & 0x1f;
+ if (volt_bits > 0x18)
+ volt_bits = 0x18;
+ rc = dx_2voltage(volt_bits);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(pcf50606_voltage_get);
+
+/* go into 'STANDBY' mode, i.e. power off the main CPU and peripherals */
+void pcf50606_go_standby(void)
+{
+ reg_write(pcf50606_global, PCF50606_REG_OOCC1,
+ PCF50606_OOCC1_GOSTDBY);
+}
+EXPORT_SYMBOL_GPL(pcf50606_go_standby);
+
+void pcf50606_gpo0_set(struct pcf50606_data *pcf, int on)
+{
+ u_int8_t val;
+
+ if (on)
+ val = 0x07;
+ else
+ val = 0x0f;
+
+ reg_set_bit_mask(pcf, PCF50606_REG_GPOC1, 0x0f, val);
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo0_set);
+
+int pcf50606_gpo0_get(struct pcf50606_data *pcf)
+{
+ u_int8_t reg = reg_read(pcf, PCF50606_REG_GPOC1) & 0x0f;
+
+ if (reg == 0x07 || reg == 0x08)
+ return 1;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo0_get);
+
+static void pcf50606_work(struct work_struct *work)
+{
+ struct pcf50606_data *pcf =
+ container_of(work, struct pcf50606_data, work);
+ u_int8_t pcfirq[3];
+ int ret;
+
+ mutex_lock(&pcf->working_lock);
+ pcf->working = 1;
+
+ /* sanity */
+ if (!&pcf->client.dev)
+ goto bail;
+
+ /*
+ * if we are presently suspending, we are not in a position to deal
+ * with pcf50606 interrupts at all.
+ *
+ * Because we didn't clear the int pending registers, there will be
+ * no edge / interrupt waiting for us when we wake. But it is OK
+ * because at the end of our resume, we call this workqueue function
+ * gratuitously, clearing the pending register and re-enabling
+ * servicing this interrupt.
+ */
+
+ if ((pcf->suspend_state == PCF50606_SS_STARTING_SUSPEND) ||
+ (pcf->suspend_state == PCF50606_SS_COMPLETED_SUSPEND))
+ goto bail;
+
+ /*
+ * If we are inside suspend -> resume completion time we don't attempt
+ * service until we have fully resumed. Although we could talk to the
+ * device as soon as I2C is up, the regs in the device which we might
+ * choose to modify as part of the service action have not been
+ * reloaded with their pre-suspend states yet. Therefore we will
+ * defer our service if we are called like that until our resume has
+ * completed.
+ *
+ * This shouldn't happen any more because we disable servicing this
+ * interrupt in suspend and don't re-enable it until resume is
+ * completed.
+ */
+
+ if (pcf->suspend_state &&
+ (pcf->suspend_state != PCF50606_SS_COMPLETED_RESUME))
+ goto reschedule;
+
+ /* this is the case early in resume! Sanity check! */
+ if (i2c_get_clientdata(&pcf->client) == NULL)
+ goto reschedule;
+
+ /*
+ * p35 pcf50606 datasheet rev 2.2:
+ * ''The system controller shall read all interrupt registers in
+ * one I2C read action''
+ * because if you don't INT# gets stuck asserted forever after a
+ * while
+ */
+ ret = i2c_smbus_read_i2c_block_data(&pcf->client, PCF50606_REG_INT1,
+ sizeof(pcfirq), pcfirq);
+ if (ret != sizeof(pcfirq)) {
+ DEBUGPC("Oh crap PMU IRQ register read failed %d\n", ret);
+ /*
+ * it shouldn't fail, we no longer attempt to use
+ * I2C while it can be suspended. But we don't have
+ * much option but to retry if if it ever did fail,
+ * because if we don't service the interrupt to clear
+ * it, we will never see another PMU interrupt edge.
+ */
+ goto reschedule;
+ }
+
+ /* hey did we just resume? (because we don't get here unless we are
+ * running normally or the first call after resumption)
+ *
+ * pcf50606 resume is really really over now then.
+ */
+ if (pcf->suspend_state != PCF50606_SS_RUNNING) {
+ pcf->suspend_state = PCF50606_SS_RUNNING;
+
+ /* peek at the IRQ reason, if power button then set a flag
+ * so that we do not signal the event to userspace
+ */
+ if (pcfirq[0] & (PCF50606_INT1_ONKEYF | PCF50606_INT1_ONKEYR)) {
+ pcf->suppress_onkey_events = 1;
+ dev_dbg(&pcf->client.dev,
+ "Wake by ONKEY, suppressing ONKEY events");
+ } else {
+ pcf->suppress_onkey_events = 0;
+ }
+ }
+
+ if (!pcf->coldplug_done) {
+ DEBUGPC("PMU Coldplug init\n");
+
+ /* we used SECOND to kick ourselves started -- turn it off */
+ pcfirq[0] &= ~PCF50606_INT1_SECOND;
+ reg_set_bit_mask(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND,
+ PCF50606_INT1_SECOND);
+
+ /* coldplug the USB if present */
+ if (__reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON) {
+ /* Charger inserted */
+ DEBUGPC("COLD CHGINS ");
+ input_report_key(pcf->input_dev, KEY_BATTERY, 1);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags |= PCF50606_F_CHG_PRESENT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client.dev,
+ PCF50606_FEAT_MBC,
+ PMU_EVT_INSERT);
+ }
+
+ pcf->coldplug_done = 1;
+ }
+
+
+ dev_dbg(&pcf->client.dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x:",
+ pcfirq[0], pcfirq[1], pcfirq[2]);
+
+ if (pcfirq[0] & PCF50606_INT1_ONKEYF) {
+ /* ONKEY falling edge (start of button press) */
+ pcf->flags |= PCF50606_F_PWR_PRESSED;
+ if (!pcf->suppress_onkey_events) {
+ DEBUGPC("ONKEYF ");
+ input_report_key(pcf->input_dev, KEY_POWER, 1);
+ } else {
+ DEBUGPC("ONKEYF(unreported) ");
+ }
+ }
+ if (pcfirq[0] & PCF50606_INT1_ONKEY1S) {
+ /* ONKEY pressed for more than 1 second */
+ pcf->onkey_seconds = 0;
+ DEBUGPC("ONKEY1S ");
+ /* Tell PMU we are taking care of this */
+ reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
+ PCF50606_OOCC1_TOTRST,
+ PCF50606_OOCC1_TOTRST);
+ /* enable SECOND interrupt (hz tick) */
+ reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND);
+ }
+ if (pcfirq[0] & PCF50606_INT1_ONKEYR) {
+ /* ONKEY rising edge (end of button press) */
+ pcf->flags &= ~PCF50606_F_PWR_PRESSED;
+ pcf->onkey_seconds = -1;
+ if (!pcf->suppress_onkey_events) {
+ DEBUGPC("ONKEYR ");
+ input_report_key(pcf->input_dev, KEY_POWER, 0);
+ } else {
+ DEBUGPC("ONKEYR(suppressed) ");
+ /* don't suppress any more power button events */
+ pcf->suppress_onkey_events = 0;
+ }
+ /* disable SECOND interrupt in case RTC didn't
+ * request it */
+ if (!(pcf->flags & PCF50606_F_RTC_SECOND))
+ reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
+ PCF50606_INT1_SECOND,
+ PCF50606_INT1_SECOND);
+ }
+ if (pcfirq[0] & PCF50606_INT1_EXTONR) {
+ DEBUGPC("EXTONR ");
+ input_report_key(pcf->input_dev, KEY_POWER2, 1);
+ }
+ if (pcfirq[0] & PCF50606_INT1_EXTONF) {
+ DEBUGPC("EXTONF ");
+ input_report_key(pcf->input_dev, KEY_POWER2, 0);
+ }
+ if (pcfirq[0] & PCF50606_INT1_SECOND) {
+ DEBUGPC("SECOND ");
+ if (pcf->flags & PCF50606_F_RTC_SECOND)
+ rtc_update_irq(pcf->rtc, 1,
+ RTC_PF | RTC_IRQF);
+
+ if (pcf->onkey_seconds >= 0 &&
+ pcf->flags & PCF50606_F_PWR_PRESSED) {
+ DEBUGPC("ONKEY_SECONDS(%u, OOCC1=0x%02x) ",
+ pcf->onkey_seconds,
+ reg_read(pcf, PCF50606_REG_OOCC1));
+ pcf->onkey_seconds++;
+ if (pcf->onkey_seconds >=
+ pcf->pdata->onkey_seconds_required) {
+ /* Ask init to do 'ctrlaltdel' */
+ /*
+ * currently Linux reacts badly to issuing a
+ * signal to PID #1 before init is started.
+ * What happens is that the next kernel thread
+ * to start, which is the JFFS2 Garbage
+ * collector in our case, gets the signal
+ * instead and proceeds to fail to fork --
+ * which is very bad. Therefore we confirm
+ * PID #1 exists before issuing the signal
+ */
+ if (find_task_by_pid_ns(1, &init_pid_ns)) {
+ kill_pid(task_pid(find_task_by_pid_ns(1,
+ &init_pid_ns)), SIGINT, 1);
+ DEBUGPC("SIGINT(init) ");
+ }
+ /* FIXME: what to do if userspace doesn't
+ * shut down? Do we want to force it? */
+ }
+ }
+ }
+ if (pcfirq[0] & PCF50606_INT1_ALARM) {
+ DEBUGPC("ALARM ");
+ if (pcf->pdata->used_features & PCF50606_FEAT_RTC)
+ rtc_update_irq(pcf->rtc, 1,
+ RTC_AF | RTC_IRQF);
+ }
+
+ if (pcfirq[1] & PCF50606_INT2_CHGINS) {
+ /* Charger inserted */
+ DEBUGPC("CHGINS ");
+ input_report_key(pcf->input_dev, KEY_BATTERY, 1);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags |= PCF50606_F_CHG_PRESENT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client.dev,
+ PCF50606_FEAT_MBC, PMU_EVT_INSERT);
+ /* FIXME: how to signal this to userspace */
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGRM) {
+ /* Charger removed */
+ DEBUGPC("CHGRM ");
+ input_report_key(pcf->input_dev, KEY_BATTERY, 0);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags &= ~(PCF50606_F_CHG_MASK|PCF50606_F_CHG_PRESENT);
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client.dev,
+ PCF50606_FEAT_MBC, PMU_EVT_INSERT);
+ /* FIXME: how signal this to userspace */
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGFOK) {
+ /* Battery ready for fast charging */
+ DEBUGPC("CHGFOK ");
+ pcf->flags |= PCF50606_F_CHG_FOK;
+ /* FIXME: how to signal this to userspace */
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGERR) {
+ /* Error in charge mode */
+ DEBUGPC("CHGERR ");
+ pcf->flags |= PCF50606_F_CHG_ERR;
+ pcf->flags &= ~(PCF50606_F_CHG_FOK|PCF50606_F_CHG_READY);
+ /* FIXME: how to signal this to userspace */
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGFRDY) {
+ /* Fast charge completed */
+ DEBUGPC("CHGFRDY ");
+ pcf->flags |= PCF50606_F_CHG_READY;
+ pcf->flags &= ~PCF50606_F_CHG_FOK;
+ /* FIXME: how to signal this to userspace */
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGPROT) {
+ /* Charging protection interrupt */
+ DEBUGPC("CHGPROT ");
+ pcf->flags &= ~(PCF50606_F_CHG_FOK|PCF50606_F_CHG_READY);
+ /* FIXME: signal this to userspace */
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGWD10S) {
+ /* Charger watchdog will expire in 10 seconds */
+ DEBUGPC("CHGWD10S ");
+ reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
+ PCF50606_OOCC1_WDTRST,
+ PCF50606_OOCC1_WDTRST);
+ }
+ if (pcfirq[1] & PCF50606_INT2_CHGWDEXP) {
+ /* Charger watchdog expires */
+ DEBUGPC("CHGWDEXP ");
+ /* FIXME: how to signal this to userspace */
+ }
+
+ if (pcfirq[2] & PCF50606_INT3_ADCRDY) {
+ /* ADC result ready */
+ DEBUGPC("ADCRDY ");
+ }
+ if (pcfirq[2] & PCF50606_INT3_ACDINS) {
+ /* Accessory insertion detected */
+ DEBUGPC("ACDINS ");
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client.dev,
+ PCF50606_FEAT_ACD, PMU_EVT_INSERT);
+ }
+ if (pcfirq[2] & PCF50606_INT3_ACDREM) {
+ /* Accessory removal detected */
+ DEBUGPC("ACDREM ");
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client.dev,
+ PCF50606_FEAT_ACD, PMU_EVT_REMOVE);
+ }
+ /* FIXME: TSCPRES */
+ if (pcfirq[2] & PCF50606_INT3_LOWBAT) {
+ if (__reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON) {
+ /*
+ * hey no need to freak out, we have some kind of
+ * valid charger power
+ */
+ DEBUGPC("(NO)BAT ");
+ } else {
+ /* Really low battery voltage, we have 8 seconds left */
+ DEBUGPC("LOWBAT ");
+ /*
+ * currently Linux reacts badly to issuing a signal to
+ * PID #1 before init is started. What happens is that
+ * the next kernel thread to start, which is the JFFS2
+ * Garbage collector in our case, gets the signal
+ * instead and proceeds to fail to fork -- which is
+ * very bad. Therefore we confirm PID #1 exists
+ * before issuing SPIGPWR
+ */
+ if (find_task_by_pid_ns(1, &init_pid_ns)) {
+ apm_queue_event(APM_LOW_BATTERY);
+ DEBUGPC("SIGPWR(init) ");
+ kill_pid(task_pid(find_task_by_pid_ns(1, &init_pid_ns)), SIGPWR, 1);
+ } else
+ /*
+ * well, our situation is like this: we do not
+ * have any external power, we have a low
+ * battery and since PID #1 doesn't exist yet,
+ * we are early in the boot, likely before
+ * rootfs mount. We should just call it a day
+ */
+ apm_queue_event(APM_CRITICAL_SUSPEND);
+ }
+ /* Tell PMU we are taking care of this */
+ reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
+ PCF50606_OOCC1_TOTRST,
+ PCF50606_OOCC1_TOTRST);
+ }
+ if (pcfirq[2] & PCF50606_INT3_HIGHTMP) {
+ /* High temperature */
+ DEBUGPC("HIGHTMP ");
+ apm_queue_event(APM_CRITICAL_SUSPEND);
+ }
+
+ DEBUGPC("\n");
+
+bail:
+ pcf->working = 0;
+ input_sync(pcf->input_dev);
+ put_device(&pcf->client.dev);
+ mutex_unlock(&pcf->working_lock);
+
+ return;
+
+reschedule:
+
+ if ((pcf->suspend_state != PCF50606_SS_STARTING_SUSPEND) &&
+ (pcf->suspend_state != PCF50606_SS_COMPLETED_SUSPEND)) {
+ msleep(10);
+ dev_info(&pcf->client.dev, "rescheduling interrupt service\n");
+ }
+ if (!schedule_work(&pcf->work))
+ dev_err(&pcf->client.dev, "int service reschedule failed\n");
+
+ /* we don't put the device here, hold it for next time */
+ mutex_unlock(&pcf->working_lock);
+}
+
+static irqreturn_t pcf50606_irq(int irq, void *_pcf)
+{
+ struct pcf50606_data *pcf = _pcf;
+
+ dev_dbg(&pcf->client.dev, "entering(irq=%u, pcf=%p): scheduling work\n",
+ irq, _pcf);
+ get_device(&pcf->client.dev);
+ if (!schedule_work(&pcf->work) && !pcf->working)
+ dev_err(&pcf->client.dev, "pcf irq work already queued.\n");
+
+ return IRQ_HANDLED;
+}
+
+static u_int16_t adc_to_batt_millivolts(u_int16_t adc)
+{
+ u_int16_t mvolts;
+
+ mvolts = (adc * 6000) / 1024;
+
+ return mvolts;
+}
+
+#define BATTVOLT_SCALE_START 2800
+#define BATTVOLT_SCALE_END 4200
+#define BATTVOLT_SCALE_DIVIDER ((BATTVOLT_SCALE_END - BATTVOLT_SCALE_START)/100)
+
+static u_int8_t battvolt_scale(u_int16_t battvolt)
+{
+ /* FIXME: this linear scale is completely bogus */
+ u_int16_t battvolt_relative = battvolt - BATTVOLT_SCALE_START;
+ unsigned int percent = battvolt_relative / BATTVOLT_SCALE_DIVIDER;
+
+ return percent;
+}
+
+u_int16_t pcf50606_battvolt(struct pcf50606_data *pcf)
+{
+ u_int16_t adc;
+ adc = adc_read(pcf, PCF50606_ADCMUX_BATVOLT_RES, NULL);
+
+ return adc_to_batt_millivolts(adc);
+}
+EXPORT_SYMBOL_GPL(pcf50606_battvolt);
+
+static ssize_t show_battvolt(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+
+ return sprintf(buf, "%u\n", pcf50606_battvolt(pcf));
+}
+static DEVICE_ATTR(battvolt, S_IRUGO | S_IWUSR, show_battvolt, NULL);
+
+static int reg_id_by_name(const char *name)
+{
+ int reg_id;
+
+ if (!strcmp(name, "voltage_dcd"))
+ reg_id = PCF50606_REGULATOR_DCD;
+ else if (!strcmp(name, "voltage_dcde"))
+ reg_id = PCF50606_REGULATOR_DCDE;
+ else if (!strcmp(name, "voltage_dcud"))
+ reg_id = PCF50606_REGULATOR_DCUD;
+ else if (!strcmp(name, "voltage_d1reg"))
+ reg_id = PCF50606_REGULATOR_D1REG;
+ else if (!strcmp(name, "voltage_d2reg"))
+ reg_id = PCF50606_REGULATOR_D2REG;
+ else if (!strcmp(name, "voltage_d3reg"))
+ reg_id = PCF50606_REGULATOR_D3REG;
+ else if (!strcmp(name, "voltage_lpreg"))
+ reg_id = PCF50606_REGULATOR_LPREG;
+ else if (!strcmp(name, "voltage_ioreg"))
+ reg_id = PCF50606_REGULATOR_IOREG;
+ else
+ reg_id = -1;
+
+ return reg_id;
+}
+
+static ssize_t show_vreg(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ unsigned int reg_id;
+
+ reg_id = reg_id_by_name(attr->attr.name);
+ if (reg_id < 0)
+ return 0;
+
+ if (pcf50606_onoff_get(pcf, reg_id) > 0)
+ return sprintf(buf, "%u\n", pcf50606_voltage_get(pcf, reg_id));
+ else
+ return strlcpy(buf, "0\n", PAGE_SIZE);
+}
+
+static ssize_t set_vreg(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ unsigned long mvolts = simple_strtoul(buf, NULL, 10);
+ unsigned int reg_id;
+
+ reg_id = reg_id_by_name(attr->attr.name);
+ if (reg_id < 0)
+ return -EIO;
+
+ dev_dbg(dev, "attempting to set %s(%d) to %lu mvolts\n",
+ attr->attr.name, reg_id, mvolts);
+
+ if (mvolts == 0) {
+ pcf50606_onoff_set(pcf, reg_id, 0);
+ } else {
+ if (pcf50606_voltage_set(pcf, reg_id, mvolts) < 0) {
+ dev_warn(dev, "refusing to set %s(%d) to %lu mvolts "
+ "(max=%u)\n", attr->attr.name, reg_id, mvolts,
+ pcf->pdata->rails[reg_id].voltage.max);
+ return -EINVAL;
+ }
+ pcf50606_onoff_set(pcf, reg_id, 1);
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR(voltage_dcd, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_dcde, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_dcud, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_d1reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_d2reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_d3reg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_lpreg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+static DEVICE_ATTR(voltage_ioreg, S_IRUGO | S_IWUSR, show_vreg, set_vreg);
+
+/***********************************************************************
+ * Charger Control
+ ***********************************************************************/
+
+/* Enable/disable fast charging (500mA in the GTA01) */
+void pcf50606_charge_fast(struct pcf50606_data *pcf, int on)
+{
+ if (!(pcf->pdata->used_features & PCF50606_FEAT_MBC))
+ return;
+
+ if (on) {
+ /* We can allow PCF to automatically charge
+ * using Ifast */
+ pcf->flags |= PCF50606_F_CHG_FAST;
+ reg_set_bit_mask(pcf, PCF50606_REG_MBCC1,
+ PCF50606_MBCC1_AUTOFST,
+ PCF50606_MBCC1_AUTOFST);
+ } else {
+ pcf->flags &= ~PCF50606_F_CHG_FAST;
+ /* disable automatic fast-charge */
+ reg_clear_bits(pcf, PCF50606_REG_MBCC1,
+ PCF50606_MBCC1_AUTOFST);
+ /* switch to idle mode to abort existing charge
+ * process */
+ reg_set_bit_mask(pcf, PCF50606_REG_MBCC1,
+ PCF50606_MBCC1_CHGMOD_MASK,
+ PCF50606_MBCC1_CHGMOD_IDLE);
+ }
+}
+EXPORT_SYMBOL_GPL(pcf50606_charge_fast);
+
+static inline u_int16_t adc_to_rntc(struct pcf50606_data *pcf, u_int16_t adc)
+{
+ u_int32_t r_ntc = (adc * (u_int32_t)pcf->pdata->r_fix_batt)
+ / (1023 - adc);
+
+ return r_ntc;
+}
+
+static inline int16_t rntc_to_temp(u_int16_t rntc)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ntc_table_10k_3370B); i++) {
+ if (rntc > ntc_table_10k_3370B[i])
+ return i - 10; /* First element is -10 */
+ }
+ return -99; /* Below our range */
+}
+
+static ssize_t show_battemp(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int16_t adc;
+
+ adc = adc_read(pcf, PCF50606_ADCMUX_BATTEMP, NULL);
+
+ return sprintf(buf, "%d\n", rntc_to_temp(adc_to_rntc(pcf, adc)));
+}
+static DEVICE_ATTR(battemp, S_IRUGO | S_IWUSR, show_battemp, NULL);
+
+static inline int16_t adc_to_chg_milliamps(struct pcf50606_data *pcf,
+ u_int16_t adc_adcin1,
+ u_int16_t adc_batvolt)
+{
+ int32_t res = (adc_adcin1 - adc_batvolt) * 2400;
+ return (res * 1000) / (pcf->pdata->r_sense_milli * 1024);
+}
+
+static ssize_t show_chgcur(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int16_t adc_batvolt, adc_adcin1;
+ int16_t ma;
+
+ adc_batvolt = adc_read(pcf, PCF50606_ADCMUX_BATVOLT_ADCIN1,
+ &adc_adcin1);
+ ma = adc_to_chg_milliamps(pcf, adc_adcin1, adc_batvolt);
+
+ return sprintf(buf, "%d\n", ma);
+}
+static DEVICE_ATTR(chgcur, S_IRUGO | S_IWUSR, show_chgcur, NULL);
+
+static const char *chgmode_names[] = {
+ [PCF50606_MBCC1_CHGMOD_QUAL] = "qualification",
+ [PCF50606_MBCC1_CHGMOD_PRE] = "pre",
+ [PCF50606_MBCC1_CHGMOD_TRICKLE] = "trickle",
+ [PCF50606_MBCC1_CHGMOD_FAST_CCCV] = "fast_cccv",
+ [PCF50606_MBCC1_CHGMOD_FAST_NOCC] = "fast_nocc",
+ [PCF50606_MBCC1_CHGMOD_FAST_NOCV] = "fast_nocv",
+ [PCF50606_MBCC1_CHGMOD_FAST_SW] = "fast_switch",
+ [PCF50606_MBCC1_CHGMOD_IDLE] = "idle",
+};
+
+static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
+ u_int8_t chgmod = (mbcc1 & PCF50606_MBCC1_CHGMOD_MASK);
+
+ return sprintf(buf, "%s\n", chgmode_names[chgmod]);
+}
+
+static ssize_t set_chgmode(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
+
+ mbcc1 &= ~PCF50606_MBCC1_CHGMOD_MASK;
+
+ if (!strcmp(buf, "qualification"))
+ mbcc1 |= PCF50606_MBCC1_CHGMOD_QUAL;
+ else if (!strcmp(buf, "pre"))
+ mbcc1 |= PCF50606_MBCC1_CHGMOD_PRE;
+ else if (!strcmp(buf, "trickle"))
+ mbcc1 |= PCF50606_MBCC1_CHGMOD_TRICKLE;
+ else if (!strcmp(buf, "fast_cccv"))
+ mbcc1 |= PCF50606_MBCC1_CHGMOD_FAST_CCCV;
+ /* We don't allow the other fast modes for security reasons */
+ else if (!strcmp(buf, "idle"))
+ mbcc1 |= PCF50606_MBCC1_CHGMOD_IDLE;
+ else
+ return -EINVAL;
+
+ reg_write(pcf, PCF50606_REG_MBCC1, mbcc1);
+
+ return count;
+}
+
+static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, set_chgmode);
+
+static const char *chgstate_names[] = {
+ [PCF50606_B_CHG_FAST] = "fast_enabled",
+ [PCF50606_B_CHG_PRESENT] = "present",
+ [PCF50606_B_CHG_FOK] = "fast_ok",
+ [PCF50606_B_CHG_ERR] = "error",
+ [PCF50606_B_CHG_PROT] = "protection",
+ [PCF50606_B_CHG_READY] = "ready",
+};
+
+static ssize_t show_chgstate(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ char *b = buf;
+ int i;
+
+ for (i = 0; i < 32; i++)
+ if (pcf->flags & (1 << i) && i < ARRAY_SIZE(chgstate_names))
+ b += sprintf(b, "%s ", chgstate_names[i]);
+
+ if (b > buf)
+ b += sprintf(b, "\n");
+
+ return b - buf;
+}
+static DEVICE_ATTR(chgstate, S_IRUGO | S_IWUSR, show_chgstate, NULL);
+
+/***********************************************************************
+ * APM emulation
+ ***********************************************************************/
+
+static void pcf50606_get_power_status(struct apm_power_info *info)
+{
+ struct pcf50606_data *pcf = pcf50606_global;
+ u_int8_t mbcc1 = reg_read(pcf, PCF50606_REG_MBCC1);
+ u_int8_t chgmod = mbcc1 & PCF50606_MBCC1_CHGMOD_MASK;
+ u_int16_t battvolt = pcf50606_battvolt(pcf);
+
+ if (reg_read(pcf, PCF50606_REG_OOCS) & PCF50606_OOCS_EXTON)
+ info->ac_line_status = APM_AC_ONLINE;
+ else
+ info->ac_line_status = APM_AC_OFFLINE;
+
+ switch (chgmod) {
+ case PCF50606_MBCC1_CHGMOD_QUAL:
+ case PCF50606_MBCC1_CHGMOD_PRE:
+ case PCF50606_MBCC1_CHGMOD_IDLE:
+ info->battery_life = battvolt_scale(battvolt);
+ break;
+ default:
+ info->battery_status = APM_BATTERY_STATUS_CHARGING;
+ info->battery_flag = APM_BATTERY_FLAG_CHARGING;
+ break;
+ }
+}
+
+/***********************************************************************
+ * RTC
+ ***********************************************************************/
+
+struct pcf50606_time {
+ u_int8_t sec;
+ u_int8_t min;
+ u_int8_t hour;
+ u_int8_t wkday;
+ u_int8_t day;
+ u_int8_t month;
+ u_int8_t year;
+};
+
+static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50606_time *pcf)
+{
+ rtc->tm_sec = bcd2bin(pcf->sec);
+ rtc->tm_min = bcd2bin(pcf->min);
+ rtc->tm_hour = bcd2bin(pcf->hour);
+ rtc->tm_wday = bcd2bin(pcf->wkday);
+ rtc->tm_mday = bcd2bin(pcf->day);
+ rtc->tm_mon = bcd2bin(pcf->month);
+ rtc->tm_year = bcd2bin(pcf->year) + 100;
+}
+
+static void rtc2pcf_time(struct pcf50606_time *pcf, struct rtc_time *rtc)
+{
+ pcf->sec = bin2bcd(rtc->tm_sec);
+ pcf->min = bin2bcd(rtc->tm_min);
+ pcf->hour = bin2bcd(rtc->tm_hour);
+ pcf->wkday = bin2bcd(rtc->tm_wday);
+ pcf->day = bin2bcd(rtc->tm_mday);
+ pcf->month = bin2bcd(rtc->tm_mon);
+ pcf->year = bin2bcd(rtc->tm_year - 100);
+}
+
+static int pcf50606_rtc_ioctl(struct device *dev, unsigned int cmd,
+ unsigned long arg)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+
+ switch (cmd) {
+ case RTC_AIE_OFF:
+ /* disable the alarm interrupt */
+ reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
+ PCF50606_INT1_ALARM, PCF50606_INT1_ALARM);
+ return 0;
+ case RTC_AIE_ON:
+ /* enable the alarm interrupt */
+ reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_ALARM);
+ return 0;
+ case RTC_PIE_OFF:
+ /* disable periodic interrupt (hz tick) */
+ pcf->flags &= ~PCF50606_F_RTC_SECOND;
+ reg_set_bit_mask(pcf, PCF50606_REG_INT1M,
+ PCF50606_INT1_SECOND, PCF50606_INT1_SECOND);
+ return 0;
+ case RTC_PIE_ON:
+ /* ensable periodic interrupt (hz tick) */
+ pcf->flags |= PCF50606_F_RTC_SECOND;
+ reg_clear_bits(pcf, PCF50606_REG_INT1M, PCF50606_INT1_SECOND);
+ return 0;
+ }
+ return -ENOIOCTLCMD;
+}
+
+static int pcf50606_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ struct pcf50606_time pcf_tm;
+
+ mutex_lock(&pcf->lock);
+ pcf_tm.sec = __reg_read(pcf, PCF50606_REG_RTCSC);
+ pcf_tm.min = __reg_read(pcf, PCF50606_REG_RTCMN);
+ pcf_tm.hour = __reg_read(pcf, PCF50606_REG_RTCHR);
+ pcf_tm.wkday = __reg_read(pcf, PCF50606_REG_RTCWD);
+ pcf_tm.day = __reg_read(pcf, PCF50606_REG_RTCDT);
+ pcf_tm.month = __reg_read(pcf, PCF50606_REG_RTCMT);
+ pcf_tm.year = __reg_read(pcf, PCF50606_REG_RTCYR);
+ mutex_unlock(&pcf->lock);
+
+ dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
+ pcf_tm.day, pcf_tm.month, pcf_tm.year,
+ pcf_tm.hour, pcf_tm.min, pcf_tm.sec);
+
+ pcf2rtc_time(tm, &pcf_tm);
+
+ dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
+ tm->tm_mday, tm->tm_mon, tm->tm_year,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
+
+static int pcf50606_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ struct pcf50606_time pcf_tm;
+ u_int8_t int1m;
+
+ dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
+ tm->tm_mday, tm->tm_mon, tm->tm_year,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+ rtc2pcf_time(&pcf_tm, tm);
+ dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
+ pcf_tm.day, pcf_tm.month, pcf_tm.year,
+ pcf_tm.hour, pcf_tm.min, pcf_tm.sec);
+
+ mutex_lock(&pcf->lock);
+
+ /* disable SECOND interrupt */
+ int1m = __reg_read(pcf, PCF50606_REG_INT1M);
+ __reg_write(pcf, PCF50606_REG_INT1M, int1m | PCF50606_INT1_SECOND);
+
+ __reg_write(pcf, PCF50606_REG_RTCSC, pcf_tm.sec);
+ __reg_write(pcf, PCF50606_REG_RTCMN, pcf_tm.min);
+ __reg_write(pcf, PCF50606_REG_RTCHR, pcf_tm.hour);
+ __reg_write(pcf, PCF50606_REG_RTCWD, pcf_tm.wkday);
+ __reg_write(pcf, PCF50606_REG_RTCDT, pcf_tm.day);
+ __reg_write(pcf, PCF50606_REG_RTCMT, pcf_tm.month);
+ __reg_write(pcf, PCF50606_REG_RTCYR, pcf_tm.year);
+
+ /* restore INT1M, potentially re-enable SECOND interrupt */
+ __reg_write(pcf, PCF50606_REG_INT1M, int1m);
+
+ mutex_unlock(&pcf->lock);
+
+ return 0;
+}
+
+static int pcf50606_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ struct pcf50606_time pcf_tm;
+
+ mutex_lock(&pcf->lock);
+ alrm->enabled =
+ __reg_read(pcf, PCF50606_REG_INT1M) & PCF50606_INT1_ALARM
+ ? 0 : 1;
+ pcf_tm.sec = __reg_read(pcf, PCF50606_REG_RTCSCA);
+ pcf_tm.min = __reg_read(pcf, PCF50606_REG_RTCMNA);
+ pcf_tm.hour = __reg_read(pcf, PCF50606_REG_RTCHRA);
+ pcf_tm.wkday = __reg_read(pcf, PCF50606_REG_RTCWDA);
+ pcf_tm.day = __reg_read(pcf, PCF50606_REG_RTCDTA);
+ pcf_tm.month = __reg_read(pcf, PCF50606_REG_RTCMTA);
+ pcf_tm.year = __reg_read(pcf, PCF50606_REG_RTCYRA);
+ mutex_unlock(&pcf->lock);
+
+ pcf2rtc_time(&alrm->time, &pcf_tm);
+
+ return 0;
+}
+
+static int pcf50606_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ struct pcf50606_time pcf_tm;
+ u_int8_t irqmask;
+
+ rtc2pcf_time(&pcf_tm, &alrm->time);
+
+ mutex_lock(&pcf->lock);
+
+ /* disable alarm interrupt */
+ irqmask = __reg_read(pcf, PCF50606_REG_INT1M);
+ irqmask |= PCF50606_INT1_ALARM;
+ __reg_write(pcf, PCF50606_REG_INT1M, irqmask);
+
+ __reg_write(pcf, PCF50606_REG_RTCSCA, pcf_tm.sec);
+ __reg_write(pcf, PCF50606_REG_RTCMNA, pcf_tm.min);
+ __reg_write(pcf, PCF50606_REG_RTCHRA, pcf_tm.hour);
+ __reg_write(pcf, PCF50606_REG_RTCWDA, pcf_tm.wkday);
+ __reg_write(pcf, PCF50606_REG_RTCDTA, pcf_tm.day);
+ __reg_write(pcf, PCF50606_REG_RTCMTA, pcf_tm.month);
+ __reg_write(pcf, PCF50606_REG_RTCYRA, pcf_tm.year);
+
+ if (alrm->enabled) {
+ /* (re-)enaable alarm interrupt */
+ irqmask = __reg_read(pcf, PCF50606_REG_INT1M);
+ irqmask &= ~PCF50606_INT1_ALARM;
+ __reg_write(pcf, PCF50606_REG_INT1M, irqmask);
+ }
+
+ mutex_unlock(&pcf->lock);
+
+ /* FIXME */
+ return 0;
+}
+
+static struct rtc_class_ops pcf50606_rtc_ops = {
+ .ioctl = pcf50606_rtc_ioctl,
+ .read_time = pcf50606_rtc_read_time,
+ .set_time = pcf50606_rtc_set_time,
+ .read_alarm = pcf50606_rtc_read_alarm,
+ .set_alarm = pcf50606_rtc_set_alarm,
+};
+
+/***********************************************************************
+ * Watchdog
+ ***********************************************************************/
+
+static void pcf50606_wdt_start(struct pcf50606_data *pcf)
+{
+ reg_set_bit_mask(pcf, PCF50606_REG_OOCC1, PCF50606_OOCC1_WDTRST,
+ PCF50606_OOCC1_WDTRST);
+}
+
+static void pcf50606_wdt_stop(struct pcf50606_data *pcf)
+{
+ reg_clear_bits(pcf, PCF50606_REG_OOCS, PCF50606_OOCS_WDTEXP);
+}
+
+static void pcf50606_wdt_keepalive(struct pcf50606_data *pcf)
+{
+ pcf50606_wdt_start(pcf);
+}
+
+static int pcf50606_wdt_open(struct inode *inode, struct file *file)
+{
+ struct pcf50606_data *pcf = pcf50606_global;
+
+ file->private_data = pcf;
+
+ /* start the timer */
+ pcf50606_wdt_start(pcf);
+
+ return nonseekable_open(inode, file);
+}
+
+static int pcf50606_wdt_release(struct inode *inode, struct file *file)
+{
+ struct pcf50606_data *pcf = file->private_data;
+
+ if (pcf->allow_close == CLOSE_STATE_ALLOW)
+ pcf50606_wdt_stop(pcf);
+ else {
+ printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
+ pcf50606_wdt_keepalive(pcf);
+ }
+
+ pcf->allow_close = CLOSE_STATE_NOT;
+
+ return 0;
+}
+
+static ssize_t pcf50606_wdt_write(struct file *file, const char __user *data,
+ size_t len, loff_t *ppos)
+{
+ struct pcf50606_data *pcf = file->private_data;
+ if (len) {
+ size_t i;
+
+ for (i = 0; i != len; i++) {
+ char c;
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ pcf->allow_close = CLOSE_STATE_ALLOW;
+ }
+ pcf50606_wdt_keepalive(pcf);
+ }
+
+ return len;
+}
+
+static struct watchdog_info pcf50606_wdt_ident = {
+ .options = WDIOF_MAGICCLOSE,
+ .firmware_version = 0,
+ .identity = "PCF50606 Watchdog",
+};
+
+static int pcf50606_wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ struct pcf50606_data *pcf = file->private_data;
+ void __user *argp = (void __user *)arg;
+ int __user *p = argp;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ return copy_to_user(argp, &pcf50606_wdt_ident,
+ sizeof(pcf50606_wdt_ident)) ? -EFAULT : 0;
+ break;
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0, p);
+ case WDIOC_KEEPALIVE:
+ pcf50606_wdt_keepalive(pcf);
+ return 0;
+ case WDIOC_GETTIMEOUT:
+ return put_user(8, p);
+ default:
+ return -ENOIOCTLCMD;
+ }
+}
+
+static struct file_operations pcf50606_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = &pcf50606_wdt_write,
+ .ioctl = &pcf50606_wdt_ioctl,
+ .open = &pcf50606_wdt_open,
+ .release = &pcf50606_wdt_release,
+};
+
+static struct miscdevice pcf50606_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &pcf50606_wdt_fops,
+};
+
+/***********************************************************************
+ * PWM
+ ***********************************************************************/
+
+static const char *pwm_dc_table[] = {
+ "0/16", "1/16", "2/16", "3/16",
+ "4/16", "5/16", "6/16", "7/16",
+ "8/16", "9/16", "10/16", "11/16",
+ "12/16", "13/16", "14/16", "15/16",
+};
+
+static ssize_t show_pwm_dc(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int8_t val;
+
+ val = reg_read(pcf, PCF50606_REG_PWMC1) >> PCF50606_PWMC1_DC_SHIFT;
+ val &= 0xf;
+
+ return sprintf(buf, "%s\n", pwm_dc_table[val]);
+}
+
+static ssize_t set_pwm_dc(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int8_t i;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_dc_table); i++) {
+ if (!strncmp(buf, pwm_dc_table[i], strlen(pwm_dc_table[i]))) {
+ dev_dbg(dev, "setting pwm dc %s\n\r", pwm_dc_table[i]);
+ reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0x1e,
+ (i << PCF50606_PWMC1_DC_SHIFT));
+ }
+ }
+ return count;
+}
+
+static DEVICE_ATTR(pwm_dc, S_IRUGO | S_IWUSR, show_pwm_dc, set_pwm_dc);
+
+static const char *pwm_clk_table[] = {
+ "512", "256", "128", "64",
+ "56300", "28100", "14100", "7000",
+};
+
+static ssize_t show_pwm_clk(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int8_t val;
+
+ val = reg_read(pcf, PCF50606_REG_PWMC1) >> PCF50606_PWMC1_CLK_SHIFT;
+ val &= 0x7;
+
+ return sprintf(buf, "%s\n", pwm_clk_table[val]);
+}
+
+static ssize_t set_pwm_clk(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ u_int8_t i;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_clk_table); i++) {
+ if (!strncmp(buf, pwm_clk_table[i], strlen(pwm_clk_table[i]))) {
+ dev_dbg(dev, "setting pwm clk %s\n\r",
+ pwm_clk_table[i]);
+ reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0xe0,
+ (i << PCF50606_PWMC1_CLK_SHIFT));
+ }
+ }
+ return count;
+}
+
+static DEVICE_ATTR(pwm_clk, S_IRUGO | S_IWUSR, show_pwm_clk, set_pwm_clk);
+
+static int pcf50606bl_get_intensity(struct backlight_device *bd)
+{
+ struct pcf50606_data *pcf = bl_get_data(bd);
+ int intensity = reg_read(pcf, PCF50606_REG_PWMC1);
+ intensity = (intensity >> PCF50606_PWMC1_DC_SHIFT);
+
+ return intensity & 0xf;
+}
+
+static int pcf50606bl_set_intensity(struct backlight_device *bd)
+{
+ struct pcf50606_data *pcf = bl_get_data(bd);
+ int intensity = bd->props.brightness;
+
+ if (bd->props.power != FB_BLANK_UNBLANK)
+ intensity = 0;
+ if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+ intensity = 0;
+
+ return reg_set_bit_mask(pcf, PCF50606_REG_PWMC1, 0x1e,
+ (intensity << PCF50606_PWMC1_DC_SHIFT));
+}
+
+static struct backlight_ops pcf50606bl_ops = {
+ .get_brightness = pcf50606bl_get_intensity,
+ .update_status = pcf50606bl_set_intensity,
+};
+
+/***********************************************************************
+ * Driver initialization
+ ***********************************************************************/
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+/* We currently place those platform devices here to make sure the device
+ * suspend/resume order is correct */
+static struct platform_device gta01_pm_gps_dev = {
+ .name = "neo1973-pm-gps",
+};
+
+static struct platform_device gta01_pm_bt_dev = {
+ .name = "neo1973-pm-bt",
+};
+#endif
+
+static struct attribute *pcf_sysfs_entries[16] = {
+ &dev_attr_voltage_dcd.attr,
+ &dev_attr_voltage_dcde.attr,
+ &dev_attr_voltage_dcud.attr,
+ &dev_attr_voltage_d1reg.attr,
+ &dev_attr_voltage_d2reg.attr,
+ &dev_attr_voltage_d3reg.attr,
+ &dev_attr_voltage_lpreg.attr,
+ &dev_attr_voltage_ioreg.attr,
+ NULL
+};
+
+static struct attribute_group pcf_attr_group = {
+ .name = NULL, /* put in device directory */
+ .attrs = pcf_sysfs_entries,
+};
+
+static void populate_sysfs_group(struct pcf50606_data *pcf)
+{
+ int i = 0;
+ struct attribute **attr;
+
+ for (attr = pcf_sysfs_entries; *attr; attr++)
+ i++;
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_MBC) {
+ pcf_sysfs_entries[i++] = &dev_attr_chgstate.attr;
+ pcf_sysfs_entries[i++] = &dev_attr_chgmode.attr;
+ }
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_CHGCUR)
+ pcf_sysfs_entries[i++] = &dev_attr_chgcur.attr;
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_BATVOLT)
+ pcf_sysfs_entries[i++] = &dev_attr_battvolt.attr;
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_BATTEMP)
+ pcf_sysfs_entries[i++] = &dev_attr_battemp.attr;
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_PWM) {
+ pcf_sysfs_entries[i++] = &dev_attr_pwm_dc.attr;
+ pcf_sysfs_entries[i++] = &dev_attr_pwm_clk.attr;
+ }
+}
+
+static int pcf50606_detect(struct i2c_adapter *adapter, int address, int kind)
+{
+ struct i2c_client *new_client;
+ struct pcf50606_data *data;
+ int err = 0;
+ int irq;
+
+ if (!pcf50606_pdev) {
+ printk(KERN_ERR "pcf50606: driver needs a platform_device!\n");
+ return -EIO;
+ }
+
+ irq = platform_get_irq(pcf50606_pdev, 0);
+ if (irq < 0) {
+ dev_err(&pcf50606_pdev->dev, "no irq in platform resources!\n");
+ return -EIO;
+ }
+
+ /* At the moment, we only support one PCF50606 in a system */
+ if (pcf50606_global) {
+ dev_err(&pcf50606_pdev->dev,
+ "currently only one chip supported\n");
+ return -EBUSY;
+ }
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ mutex_init(&data->lock);
+ mutex_init(&data->working_lock);
+ INIT_WORK(&data->work, pcf50606_work);
+ data->irq = irq;
+ data->working = 0;
+ data->suppress_onkey_events = 0;
+ data->onkey_seconds = -1;
+ data->pdata = pcf50606_pdev->dev.platform_data;
+
+ new_client = &data->client;
+ i2c_set_clientdata(new_client, data);
+ new_client->addr = address;
+ new_client->adapter = adapter;
+ new_client->driver = &pcf50606_driver;
+ new_client->flags = 0;
+ strlcpy(new_client->name, "pcf50606", I2C_NAME_SIZE);
+
+ /* now we try to detect the chip */
+
+ /* register with i2c core */
+ err = i2c_attach_client(new_client);
+ if (err) {
+ dev_err(&new_client->dev,
+ "error during i2c_attach_client()\n");
+ goto exit_free;
+ }
+
+ populate_sysfs_group(data);
+
+ err = sysfs_create_group(&new_client->dev.kobj, &pcf_attr_group);
+ if (err) {
+ dev_err(&new_client->dev, "error creating sysfs group\n");
+ goto exit_detach;
+ }
+
+ /* create virtual charger 'device' */
+
+ /* input device registration */
+ data->input_dev = input_allocate_device();
+ if (!data->input_dev)
+ goto exit_sysfs;
+
+ data->input_dev->name = "FIC Neo1973 PMU events";
+ data->input_dev->phys = "I2C";
+ data->input_dev->id.bustype = BUS_I2C;
+
+ data->input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
+ set_bit(KEY_POWER, data->input_dev->keybit);
+ set_bit(KEY_POWER2, data->input_dev->keybit);
+ set_bit(KEY_BATTERY, data->input_dev->keybit);
+
+ err = input_register_device(data->input_dev);
+ if (err)
+ goto exit_sysfs;
+
+ /* register power off handler with core power management */
+ pm_power_off = &pcf50606_go_standby;
+
+ /* configure interrupt mask */
+ /* we don't mask SECOND here, because we want one to do coldplug with */
+ reg_write(data, PCF50606_REG_INT1M, 0x00);
+ reg_write(data, PCF50606_REG_INT2M, 0x00);
+ reg_write(data, PCF50606_REG_INT3M, PCF50606_INT3_TSCPRES);
+
+ err = request_irq(irq, pcf50606_irq, IRQF_TRIGGER_FALLING,
+ "pcf50606", data);
+ if (err < 0)
+ goto exit_input;
+
+ if (enable_irq_wake(irq) < 0)
+ dev_err(&new_client->dev, "IRQ %u cannot be enabled as wake-up"
+ "source in this hardware revision!", irq);
+
+ pcf50606_global = data;
+
+ if (data->pdata->used_features & PCF50606_FEAT_RTC) {
+ data->rtc = rtc_device_register("pcf50606", &new_client->dev,
+ &pcf50606_rtc_ops, THIS_MODULE);
+ if (IS_ERR(data->rtc)) {
+ err = PTR_ERR(data->rtc);
+ goto exit_irq;
+ }
+ }
+
+ if (data->pdata->used_features & PCF50606_FEAT_WDT) {
+ err = misc_register(&pcf50606_wdt_miscdev);
+ if (err) {
+ dev_err(&new_client->dev, "cannot register miscdev on "
+ "minor=%d (%d)\n", WATCHDOG_MINOR, err);
+ goto exit_rtc;
+ }
+ }
+
+ if (data->pdata->used_features & PCF50606_FEAT_PWM) {
+ /* enable PWM controller */
+ reg_set_bit_mask(data, PCF50606_REG_PWMC1,
+ PCF50606_PWMC1_ACTSET,
+ PCF50606_PWMC1_ACTSET);
+ }
+
+ if (data->pdata->used_features & PCF50606_FEAT_PWM_BL) {
+ data->backlight = backlight_device_register("pcf50606-bl",
+ &new_client->dev,
+ data,
+ &pcf50606bl_ops);
+ if (!data->backlight)
+ goto exit_misc;
+ data->backlight->props.max_brightness = 16;
+ data->backlight->props.power = FB_BLANK_UNBLANK;
+ data->backlight->props.brightness =
+ data->pdata->init_brightness;
+ backlight_update_status(data->backlight);
+ }
+
+ apm_get_power_status = pcf50606_get_power_status;
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ if (machine_is_neo1973_gta01()) {
+ gta01_pm_gps_dev.dev.parent = &new_client->dev;
+ switch (system_rev) {
+ case GTA01Bv2_SYSTEM_REV:
+ case GTA01Bv3_SYSTEM_REV:
+ case GTA01Bv4_SYSTEM_REV:
+ gta01_pm_bt_dev.dev.parent = &new_client->dev;
+ platform_device_register(&gta01_pm_bt_dev);
+ break;
+ }
+ platform_device_register(&gta01_pm_gps_dev);
+ /* a link for gllin compatibility */
+ err = bus_create_device_link(&platform_bus_type,
+ &gta01_pm_gps_dev.dev.kobj, "gta01-pm-gps.0");
+ if (err)
+ printk(KERN_ERR
+ "sysfs_create_link (gta01-pm-gps.0): %d\n", err);
+ }
+#endif
+
+ if (data->pdata->used_features & PCF50606_FEAT_ACD)
+ reg_set_bit_mask(data, PCF50606_REG_ACDC1,
+ PCF50606_ACDC1_ACDAPE, PCF50606_ACDC1_ACDAPE);
+ else
+ reg_clear_bits(data, PCF50606_REG_ACDC1,
+ PCF50606_ACDC1_ACDAPE);
+
+ return 0;
+
+exit_misc:
+ if (data->pdata->used_features & PCF50606_FEAT_WDT)
+ misc_deregister(&pcf50606_wdt_miscdev);
+exit_rtc:
+ if (data->pdata->used_features & PCF50606_FEAT_RTC)
+ rtc_device_unregister(pcf50606_global->rtc);
+exit_irq:
+ free_irq(pcf50606_global->irq, pcf50606_global);
+ pcf50606_global = NULL;
+exit_input:
+ pm_power_off = NULL;
+ input_unregister_device(data->input_dev);
+exit_sysfs:
+ sysfs_remove_group(&new_client->dev.kobj, &pcf_attr_group);
+exit_detach:
+ i2c_detach_client(new_client);
+exit_free:
+ kfree(data);
+ return err;
+}
+
+static int pcf50606_attach_adapter(struct i2c_adapter *adapter)
+{
+ return i2c_probe(adapter, &addr_data, &pcf50606_detect);
+}
+
+static int pcf50606_detach_client(struct i2c_client *client)
+{
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+
+ apm_get_power_status = NULL;
+ input_unregister_device(pcf->input_dev);
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_PWM_BL)
+ backlight_device_unregister(pcf->backlight);
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_WDT)
+ misc_deregister(&pcf50606_wdt_miscdev);
+
+ if (pcf->pdata->used_features & PCF50606_FEAT_RTC)
+ rtc_device_unregister(pcf->rtc);
+
+ free_irq(pcf->irq, pcf);
+
+ sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
+
+ pm_power_off = NULL;
+
+ kfree(pcf);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+#define INT1M_RESUMERS (PCF50606_INT1_ALARM | \
+ PCF50606_INT1_ONKEYF | \
+ PCF50606_INT1_EXTONR)
+#define INT2M_RESUMERS (PCF50606_INT2_CHGWD10S | \
+ PCF50606_INT2_CHGPROT | \
+ PCF50606_INT2_CHGERR)
+#define INT3M_RESUMERS (PCF50606_INT3_LOWBAT | \
+ PCF50606_INT3_HIGHTMP | \
+ PCF50606_INT3_ACDINS)
+static int pcf50606_suspend(struct device *dev, pm_message_t state)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+ int i;
+
+ /* we suspend once (!) as late as possible in the suspend sequencing */
+
+ if ((state.event != PM_EVENT_SUSPEND) ||
+ (pcf->suspend_state != PCF50606_SS_RUNNING))
+ return -EBUSY;
+
+ /* The general idea is to power down all unused power supplies,
+ * and then mask all PCF50606 interrup sources but EXTONR, ONKEYF
+ * and ALARM */
+
+ mutex_lock(&pcf->lock);
+
+ pcf->suspend_state = PCF50606_SS_STARTING_SUSPEND;
+
+ /* we are not going to service any further interrupts until we
+ * resume. If the IRQ workqueue is still pending in the background,
+ * it will bail when it sees we set suspend state above.
+ */
+
+ disable_irq(pcf->irq);
+
+ /* Save all registers that don't "survive" standby state */
+ pcf->standby_regs.dcdc1 = __reg_read(pcf, PCF50606_REG_DCDC1);
+ pcf->standby_regs.dcdc2 = __reg_read(pcf, PCF50606_REG_DCDC2);
+ pcf->standby_regs.dcdec1 = __reg_read(pcf, PCF50606_REG_DCDEC1);
+ pcf->standby_regs.dcudc1 = __reg_read(pcf, PCF50606_REG_DCUDC1);
+ pcf->standby_regs.ioregc = __reg_read(pcf, PCF50606_REG_IOREGC);
+ pcf->standby_regs.d1regc1 = __reg_read(pcf, PCF50606_REG_D1REGC1);
+ pcf->standby_regs.d2regc1 = __reg_read(pcf, PCF50606_REG_D2REGC1);
+ pcf->standby_regs.d3regc1 = __reg_read(pcf, PCF50606_REG_D3REGC1);
+ pcf->standby_regs.lpregc1 = __reg_read(pcf, PCF50606_REG_LPREGC1);
+ pcf->standby_regs.adcc1 = __reg_read(pcf, PCF50606_REG_ADCC1);
+ pcf->standby_regs.adcc2 = __reg_read(pcf, PCF50606_REG_ADCC2);
+ pcf->standby_regs.pwmc1 = __reg_read(pcf, PCF50606_REG_PWMC1);
+
+ /* switch off power supplies that are not needed during suspend */
+ for (i = 0; i < __NUM_PCF50606_REGULATORS; i++) {
+ if (!(pcf->pdata->rails[i].flags & PMU_VRAIL_F_SUSPEND_ON)) {
+ u_int8_t tmp;
+
+ /* IOREG powers the I@C interface so we cannot switch
+ * it off */
+ if (i == PCF50606_REGULATOR_IOREG)
+ continue;
+
+ dev_dbg(dev, "disabling pcf50606 regulator %u\n", i);
+ /* we cannot use pcf50606_onoff_set() because we're
+ * already under the mutex */
+ tmp = __reg_read(pcf, regulator_registers[i]);
+ tmp &= 0x1f;
+ __reg_write(pcf, regulator_registers[i], tmp);
+ }
+ }
+
+ pcf->standby_regs.int1m = __reg_read(pcf, PCF50606_REG_INT1M);
+ pcf->standby_regs.int2m = __reg_read(pcf, PCF50606_REG_INT2M);
+ pcf->standby_regs.int3m = __reg_read(pcf, PCF50606_REG_INT3M);
+ __reg_write(pcf, PCF50606_REG_INT1M, ~INT1M_RESUMERS & 0xff);
+ __reg_write(pcf, PCF50606_REG_INT2M, ~INT2M_RESUMERS & 0xff);
+ __reg_write(pcf, PCF50606_REG_INT3M, ~INT3M_RESUMERS & 0xff);
+
+ pcf->suspend_state = PCF50606_SS_COMPLETED_SUSPEND;
+
+ mutex_unlock(&pcf->lock);
+
+ return 0;
+}
+
+static int pcf50606_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50606_data *pcf = i2c_get_clientdata(client);
+
+ mutex_lock(&pcf->lock);
+
+ pcf->suspend_state = PCF50606_SS_STARTING_RESUME;
+
+ /* Resume all saved registers that don't "survive" standby state */
+ __reg_write(pcf, PCF50606_REG_INT1M, pcf->standby_regs.int1m);
+ __reg_write(pcf, PCF50606_REG_INT2M, pcf->standby_regs.int2m);
+ __reg_write(pcf, PCF50606_REG_INT3M, pcf->standby_regs.int3m);
+
+ __reg_write(pcf, PCF50606_REG_DCDC1, pcf->standby_regs.dcdc1);
+ __reg_write(pcf, PCF50606_REG_DCDC2, pcf->standby_regs.dcdc2);
+ __reg_write(pcf, PCF50606_REG_DCDEC1, pcf->standby_regs.dcdec1);
+ __reg_write(pcf, PCF50606_REG_DCUDC1, pcf->standby_regs.dcudc1);
+ __reg_write(pcf, PCF50606_REG_IOREGC, pcf->standby_regs.ioregc);
+ __reg_write(pcf, PCF50606_REG_D1REGC1, pcf->standby_regs.d1regc1);
+ __reg_write(pcf, PCF50606_REG_D2REGC1, pcf->standby_regs.d2regc1);
+ __reg_write(pcf, PCF50606_REG_D3REGC1, pcf->standby_regs.d3regc1);
+ __reg_write(pcf, PCF50606_REG_LPREGC1, pcf->standby_regs.lpregc1);
+ __reg_write(pcf, PCF50606_REG_ADCC1, pcf->standby_regs.adcc1);
+ __reg_write(pcf, PCF50606_REG_ADCC2, pcf->standby_regs.adcc2);
+ __reg_write(pcf, PCF50606_REG_PWMC1, pcf->standby_regs.pwmc1);
+
+ pcf->suspend_state = PCF50606_SS_COMPLETED_RESUME;
+
+ enable_irq(pcf->irq);
+
+ mutex_unlock(&pcf->lock);
+
+ /* Call PCF work function; this fixes an issue on the gta01 where
+ * the power button "goes away" if it is used to wake the device.
+ */
+ get_device(&pcf->client.dev);
+ pcf50606_work(&pcf->work);
+
+ return 0;
+}
+#else
+#define pcf50606_suspend NULL
+#define pcf50606_resume NULL
+#endif
+
+static struct i2c_driver pcf50606_driver = {
+ .driver = {
+ .name = "pcf50606",
+ .suspend = pcf50606_suspend,
+ .resume = pcf50606_resume,
+ },
+ .id = I2C_DRIVERID_PCF50606,
+ .attach_adapter = pcf50606_attach_adapter,
+ .detach_client = pcf50606_detach_client,
+};
+
+/* platform driver, since i2c devices don't have platform_data */
+static int __init pcf50606_plat_probe(struct platform_device *pdev)
+{
+ struct pcf50606_platform_data *pdata = pdev->dev.platform_data;
+
+ if (!pdata)
+ return -ENODEV;
+
+ pcf50606_pdev = pdev;
+
+ return 0;
+}
+
+static int pcf50606_plat_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+/* We have this purely to capture an early indication that we are coming out
+ * of suspend, before our device resume got called; async interrupt service is
+ * interested in this.
+ */
+
+static int pcf50606_plat_resume(struct platform_device *pdev)
+{
+ /* i2c_get_clientdata(to_i2c_client(&pdev->dev)) returns NULL at this
+ * early resume time so we have to use pcf50606_global
+ */
+ pcf50606_global->suspend_state = PCF50606_SS_RESUMING_BUT_NOT_US_YET;
+
+ return 0;
+}
+
+static struct platform_driver pcf50606_plat_driver = {
+ .probe = pcf50606_plat_probe,
+ .remove = pcf50606_plat_remove,
+ .resume_early = pcf50606_plat_resume,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "pcf50606",
+ },
+};
+
+static int __init pcf50606_init(void)
+{
+ int rc;
+
+ rc = platform_driver_register(&pcf50606_plat_driver);
+ if (!rc)
+ rc = i2c_add_driver(&pcf50606_driver);
+
+ return rc;
+}
+
+static void pcf50606_exit(void)
+{
+ i2c_del_driver(&pcf50606_driver);
+ platform_driver_unregister(&pcf50606_plat_driver);
+}
+
+MODULE_DESCRIPTION("I2C chip driver for NXP PCF50606 power management unit");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
+
+module_init(pcf50606_init);
+module_exit(pcf50606_exit);
--- /dev/null
+++ b/drivers/i2c/chips/pcf50606.h
@@ -0,0 +1,302 @@
+#ifndef _PCF50606_H
+#define _PCF50606_H
+
+/* Philips PCF50606 Power Managemnt Unit (PMU) driver
+ * (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ *
+ */
+
+enum pfc50606_regs {
+ PCF50606_REG_ID = 0x00,
+ PCF50606_REG_OOCS = 0x01,
+ PCF50606_REG_INT1 = 0x02, /* Interrupt Status */
+ PCF50606_REG_INT2 = 0x03, /* Interrupt Status */
+ PCF50606_REG_INT3 = 0x04, /* Interrupt Status */
+ PCF50606_REG_INT1M = 0x05, /* Interrupt Mask */
+ PCF50606_REG_INT2M = 0x06, /* Interrupt Mask */
+ PCF50606_REG_INT3M = 0x07, /* Interrupt Mask */
+ PCF50606_REG_OOCC1 = 0x08,
+ PCF50606_REG_OOCC2 = 0x09,
+ PCF50606_REG_RTCSC = 0x0a, /* Second */
+ PCF50606_REG_RTCMN = 0x0b, /* Minute */
+ PCF50606_REG_RTCHR = 0x0c, /* Hour */
+ PCF50606_REG_RTCWD = 0x0d, /* Weekday */
+ PCF50606_REG_RTCDT = 0x0e, /* Day */
+ PCF50606_REG_RTCMT = 0x0f, /* Month */
+ PCF50606_REG_RTCYR = 0x10, /* Year */
+ PCF50606_REG_RTCSCA = 0x11, /* Alarm Second */
+ PCF50606_REG_RTCMNA = 0x12, /* Alarm Minute */
+ PCF50606_REG_RTCHRA = 0x13, /* Alarm Hour */
+ PCF50606_REG_RTCWDA = 0x14, /* Alarm Weekday */
+ PCF50606_REG_RTCDTA = 0x15, /* Alarm Day */
+ PCF50606_REG_RTCMTA = 0x16, /* Alarm Month */
+ PCF50606_REG_RTCYRA = 0x17, /* Alarm Year */
+ PCF50606_REG_PSSC = 0x18, /* Power sequencing */
+ PCF50606_REG_PWROKM = 0x19, /* PWROK mask */
+ PCF50606_REG_PWROKS = 0x1a, /* PWROK status */
+ PCF50606_REG_DCDC1 = 0x1b,
+ PCF50606_REG_DCDC2 = 0x1c,
+ PCF50606_REG_DCDC3 = 0x1d,
+ PCF50606_REG_DCDC4 = 0x1e,
+ PCF50606_REG_DCDEC1 = 0x1f,
+ PCF50606_REG_DCDEC2 = 0x20,
+ PCF50606_REG_DCUDC1 = 0x21,
+ PCF50606_REG_DCUDC2 = 0x22,
+ PCF50606_REG_IOREGC = 0x23,
+ PCF50606_REG_D1REGC1 = 0x24,
+ PCF50606_REG_D2REGC1 = 0x25,
+ PCF50606_REG_D3REGC1 = 0x26,
+ PCF50606_REG_LPREGC1 = 0x27,
+ PCF50606_REG_LPREGC2 = 0x28,
+ PCF50606_REG_MBCC1 = 0x29,
+ PCF50606_REG_MBCC2 = 0x2a,
+ PCF50606_REG_MBCC3 = 0x2b,
+ PCF50606_REG_MBCS1 = 0x2c,
+ PCF50606_REG_BBCC = 0x2d,
+ PCF50606_REG_ADCC1 = 0x2e,
+ PCF50606_REG_ADCC2 = 0x2f,
+ PCF50606_REG_ADCS1 = 0x30,
+ PCF50606_REG_ADCS2 = 0x31,
+ PCF50606_REG_ADCS3 = 0x32,
+ PCF50606_REG_ACDC1 = 0x33,
+ PCF50606_REG_BVMC = 0x34,
+ PCF50606_REG_PWMC1 = 0x35,
+ PCF50606_REG_LEDC1 = 0x36,
+ PCF50606_REG_LEDC2 = 0x37,
+ PCF50606_REG_GPOC1 = 0x38,
+ PCF50606_REG_GPOC2 = 0x39,
+ PCF50606_REG_GPOC3 = 0x3a,
+ PCF50606_REG_GPOC4 = 0x3b,
+ PCF50606_REG_GPOC5 = 0x3c,
+ __NUM_PCF50606_REGS
+};
+
+enum pcf50606_reg_oocs {
+ PFC50606_OOCS_ONKEY = 0x01,
+ PCF50606_OOCS_EXTON = 0x02,
+ PCF50606_OOCS_PWROKRST = 0x04,
+ PCF50606_OOCS_BATOK = 0x08,
+ PCF50606_OOCS_BACKOK = 0x10,
+ PCF50606_OOCS_CHGOK = 0x20,
+ PCF50606_OOCS_TEMPOK = 0x40,
+ PCF50606_OOCS_WDTEXP = 0x80,
+};
+
+enum pcf50606_reg_oocc1 {
+ PCF50606_OOCC1_GOSTDBY = 0x01,
+ PCF50606_OOCC1_TOTRST = 0x02,
+ PCF50606_OOCC1_CLK32ON = 0x04,
+ PCF50606_OOCC1_WDTRST = 0x08,
+ PCF50606_OOCC1_RTCWAK = 0x10,
+ PCF50606_OOCC1_CHGWAK = 0x20,
+ PCF50606_OOCC1_EXTONWAK_HIGH = 0x40,
+ PCF50606_OOCC1_EXTONWAK_LOW = 0x80,
+};
+
+enum pcf50606_reg_oocc2 {
+ PCF50606_OOCC2_ONKEYDB_NONE = 0x00,
+ PCF50606_OOCC2_ONKEYDB_14ms = 0x01,
+ PCF50606_OOCC2_ONKEYDB_62ms = 0x02,
+ PCF50606_OOCC2_ONKEYDB_500ms = 0x03,
+ PCF50606_OOCC2_EXTONDB_NONE = 0x00,
+ PCF50606_OOCC2_EXTONDB_14ms = 0x04,
+ PCF50606_OOCC2_EXTONDB_62ms = 0x08,
+ PCF50606_OOCC2_EXTONDB_500ms = 0x0c,
+};
+
+enum pcf50606_reg_int1 {
+ PCF50606_INT1_ONKEYR = 0x01, /* ONKEY rising edge */
+ PCF50606_INT1_ONKEYF = 0x02, /* ONKEY falling edge */
+ PCF50606_INT1_ONKEY1S = 0x04, /* OMKEY at least 1sec low */
+ PCF50606_INT1_EXTONR = 0x08, /* EXTON rising edge */
+ PCF50606_INT1_EXTONF = 0x10, /* EXTON falling edge */
+ PCF50606_INT1_SECOND = 0x40, /* RTC periodic second interrupt */
+ PCF50606_INT1_ALARM = 0x80, /* RTC alarm time is reached */
+};
+
+enum pcf50606_reg_int2 {
+ PCF50606_INT2_CHGINS = 0x01, /* Charger inserted */
+ PCF50606_INT2_CHGRM = 0x02, /* Charger removed */
+ PCF50606_INT2_CHGFOK = 0x04, /* Fast charging OK */
+ PCF50606_INT2_CHGERR = 0x08, /* Error in charging mode */
+ PCF50606_INT2_CHGFRDY = 0x10, /* Fast charge completed */
+ PCF50606_INT2_CHGPROT = 0x20, /* Charging protection interrupt */
+ PCF50606_INT2_CHGWD10S = 0x40, /* Charger watchdig expires in 10s */
+ PCF50606_INT2_CHGWDEXP = 0x80, /* Charger watchdog expires */
+};
+
+enum pcf50606_reg_int3 {
+ PCF50606_INT3_ADCRDY = 0x01, /* ADC conversion finished */
+ PCF50606_INT3_ACDINS = 0x02, /* Accessory inserted */
+ PCF50606_INT3_ACDREM = 0x04, /* Accessory removed */
+ PCF50606_INT3_TSCPRES = 0x08, /* Touch screen pressed */
+ PCF50606_INT3_LOWBAT = 0x40, /* Low battery voltage */
+ PCF50606_INT3_HIGHTMP = 0x80, /* High temperature */
+};
+
+/* used by PSSC, PWROKM, PWROKS, */
+enum pcf50606_regu {
+ PCF50606_REGU_DCD = 0x01, /* DCD in phase 2 */
+ PCF50606_REGU_DCDE = 0x02, /* DCDE in phase 2 */
+ PCF50606_REGU_DCUD = 0x04, /* DCDU in phase 2 */
+ PCF50606_REGU_IO = 0x08, /* IO in phase 2 */
+ PCF50606_REGU_D1 = 0x10, /* D1 in phase 2 */
+ PCF50606_REGU_D2 = 0x20, /* D2 in phase 2 */
+ PCF50606_REGU_D3 = 0x40, /* D3 in phase 2 */
+ PCF50606_REGU_LP = 0x80, /* LP in phase 2 */
+};
+
+enum pcf50606_reg_dcdc4 {
+ PCF50606_DCDC4_MODE_AUTO = 0x00,
+ PCF50606_DCDC4_MODE_PWM = 0x01,
+ PCF50606_DCDC4_MODE_PCF = 0x02,
+ PCF50606_DCDC4_OFF_FLOAT = 0x00,
+ PCF50606_DCDC4_OFF_BYPASS = 0x04,
+ PCF50606_DCDC4_OFF_PULLDOWN = 0x08,
+ PCF50606_DCDC4_CURLIM_500mA = 0x00,
+ PCF50606_DCDC4_CURLIM_750mA = 0x10,
+ PCF50606_DCDC4_CURLIM_1000mA = 0x20,
+ PCF50606_DCDC4_CURLIM_1250mA = 0x30,
+ PCF50606_DCDC4_TOGGLE = 0x40,
+ PCF50606_DCDC4_REGSEL_DCDC2 = 0x80,
+};
+
+enum pcf50606_reg_dcdec2 {
+ PCF50606_DCDEC2_MODE_AUTO = 0x00,
+ PCF50606_DCDEC2_MODE_PWM = 0x01,
+ PCF50606_DCDEC2_MODE_PCF = 0x02,
+ PCF50606_DCDEC2_OFF_FLOAT = 0x00,
+ PCF50606_DCDEC2_OFF_BYPASS = 0x04,
+};
+
+enum pcf50606_reg_dcudc2 {
+ PCF50606_DCUDC2_MODE_AUTO = 0x00,
+ PCF50606_DCUDC2_MODE_PWM = 0x01,
+ PCF50606_DCUDC2_MODE_PCF = 0x02,
+ PCF50606_DCUDC2_OFF_FLOAT = 0x00,
+ PCF50606_DCUDC2_OFF_BYPASS = 0x04,
+};
+
+enum pcf50606_reg_adcc1 {
+ PCF50606_ADCC1_TSCMODACT = 0x01,
+ PCF50606_ADCC1_TSCMODSTB = 0x02,
+ PCF50606_ADCC1_TRATSET = 0x04,
+ PCF50606_ADCC1_NTCSWAPE = 0x08,
+ PCF50606_ADCC1_NTCSWAOFF = 0x10,
+ PCF50606_ADCC1_EXTSYNCBREAK = 0x20,
+ /* reserved */
+ PCF50606_ADCC1_TSCINT = 0x80,
+};
+
+enum pcf50606_reg_adcc2 {
+ PCF50606_ADCC2_ADCSTART = 0x01,
+ /* see enum pcf50606_adcc2_adcmux */
+ PCF50606_ADCC2_SYNC_NONE = 0x00,
+ PCF50606_ADCC2_SYNC_TXON = 0x20,
+ PCF50606_ADCC2_SYNC_PWREN1 = 0x40,
+ PCF50606_ADCC2_SYNC_PWREN2 = 0x60,
+ PCF50606_ADCC2_RES_10BIT = 0x00,
+ PCF50606_ADCC2_RES_8BIT = 0x80,
+};
+
+#define PCF50606_ADCC2_ADCMUX_MASK (0xf << 1)
+
+#define ADCMUX_SHIFT 1
+enum pcf50606_adcc2_adcmux {
+ PCF50606_ADCMUX_BATVOLT_RES = 0x0 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_BATVOLT_SUBTR = 0x1 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_ADCIN1_RES = 0x2 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_ADCIN1_SUBTR = 0x3 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_BATTEMP = 0x4 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_ADCIN2 = 0x5 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_ADCIN3 = 0x6 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_ADCIN3_RATIO = 0x7 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_XPOS = 0x8 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_YPOS = 0x9 << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_P1 = 0xa << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_P2 = 0xb << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_BATVOLT_ADCIN1 = 0xc << ADCMUX_SHIFT,
+ PCF50606_ADCMUX_XY_SEQUENCE = 0xe << ADCMUX_SHIFT,
+ PCF50606_P1_P2_RESISTANCE = 0xf << ADCMUX_SHIFT,
+};
+
+enum pcf50606_adcs2 {
+ PCF50606_ADCS2_ADCRDY = 0x80,
+};
+
+enum pcf50606_reg_mbcc1 {
+ PCF50606_MBCC1_CHGAPE = 0x01,
+ PCF50606_MBCC1_AUTOFST = 0x02,
+#define PCF50606_MBCC1_CHGMOD_MASK 0x1c
+#define PCF50606_MBCC1_CHGMOD_SHIFT 2
+ PCF50606_MBCC1_CHGMOD_QUAL = 0x00,
+ PCF50606_MBCC1_CHGMOD_PRE = 0x04,
+ PCF50606_MBCC1_CHGMOD_TRICKLE = 0x08,
+ PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
+ PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
+ PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
+ PCF50606_MBCC1_CHGMOD_FAST_SW = 0x18,
+ PCF50606_MBCC1_CHGMOD_IDLE = 0x1c,
+ PCF50606_MBCC1_DETMOD_LOWCHG = 0x20,
+ PCF50606_MBCC1_DETMOD_WDRST = 0x40,
+};
+
+enum pcf50606_reg_acdc1 {
+ PCF50606_ACDC1_ACDDET = 0x01,
+ PCF50606_ACDC1_THRSHLD_1V0 = 0x00,
+ PCF50606_ACDC1_THRSHLD_1V2 = 0x02,
+ PCF50606_ACDC1_THRSHLD_1V4 = 0x04,
+ PCF50606_ACDC1_THRSHLD_1V6 = 0x06,
+ PCF50606_ACDC1_THRSHLD_1V8 = 0x08,
+ PCF50606_ACDC1_THRSHLD_2V0 = 0x0a,
+ PCF50606_ACDC1_THRSHLD_2V2 = 0x0c,
+ PCF50606_ACDC1_THRSHLD_2V4 = 0x0e,
+ PCF50606_ACDC1_DISDB = 0x10,
+ PCF50606_ACDC1_ACDAPE = 0x80,
+};
+
+enum pcf50606_reg_bvmc {
+ PCF50606_BVMC_LOWBAT = 0x01,
+ PCF50606_BVMC_THRSHLD_NULL = 0x00,
+ PCF50606_BVMC_THRSHLD_2V8 = 0x02,
+ PCF50606_BVMC_THRSHLD_2V9 = 0x04,
+ PCF50606_BVMC_THRSHLD_3V = 0x08,
+ PCF50606_BVMC_THRSHLD_3V1 = 0x08,
+ PCF50606_BVMC_THRSHLD_3V2 = 0x0a,
+ PCF50606_BVMC_THRSHLD_3V3 = 0x0c,
+ PCF50606_BVMC_THRSHLD_3V4 = 0x0e,
+ PCF50606_BVMC_DISDB = 0x10,
+};
+
+enum pcf50606_reg_pwmc1 {
+ PCF50606_PWMC1_ACTSET = 0x01,
+ PCF50606_PWMC1_PWMDC_0_16 = 0x00,
+ PCF50606_PWMC1_PWMDC_1_16 = 0x02,
+ PCF50606_PWMC1_PWMDC_2_16 = 0x04,
+ PCF50606_PWMC1_PWMDC_3_16 = 0x06,
+ PCF50606_PWMC1_PWMDC_4_16 = 0x08,
+ PCF50606_PWMC1_PWMDC_5_16 = 0x0a,
+ PCF50606_PWMC1_PWMDC_6_16 = 0x0c,
+ PCF50606_PWMC1_PWMDC_7_16 = 0x0e,
+ PCF50606_PWMC1_PWMDC_8_16 = 0x10,
+ PCF50606_PWMC1_PWMDC_9_16 = 0x12,
+ PCF50606_PWMC1_PWMDC_10_16 = 0x14,
+ PCF50606_PWMC1_PWMDC_11_16 = 0x16,
+ PCF50606_PWMC1_PWMDC_12_16 = 0x18,
+ PCF50606_PWMC1_PWMDC_13_16 = 0x1a,
+ PCF50606_PWMC1_PWMDC_14_16 = 0x1c,
+ PCF50606_PWMC1_PWMDC_15_16 = 0x1e,
+ PCF50606_PWMC1_PRESC_512Hz = 0x20,
+ PCF50606_PWMC1_PRESC_256Hz = 0x40,
+ PCF50606_PWMC1_PRESC_64Hz = 0x60,
+ PCF50606_PWMC1_PRESC_56kHz = 0x80,
+ PCF50606_PWMC1_PRESC_28kHz = 0xa0,
+ PCF50606_PWMC1_PRESC_14kHz = 0xc0,
+ PCF50606_PWMC1_PRESC_7kHz = 0xe0,
+};
+#define PCF50606_PWMC1_CLK_SHIFT 5
+#define PCF50606_PWMC1_DC_SHIFT 1
+
+#endif /* _PCF50606_H */
+
--- /dev/null
+++ b/drivers/i2c/chips/pcf50633.c
@@ -0,0 +1,1883 @@
+/* Philips PCF50633 Power Management Unit (PMU) driver
+ *
+ * (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This driver is a monster ;) It provides the following features
+ * - voltage control for a dozen different voltage domains
+ * - charging control for main and backup battery
+ * - adc driver (hw_sensors like)
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/bcd.h>
+#include <linux/watchdog.h>
+#include <linux/miscdevice.h>
+#include <linux/input.h>
+#include <linux/fb.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/pcf50633.h>
+#include <linux/apm-emulation.h>
+#include <linux/jiffies.h>
+
+#include <asm/mach-types.h>
+
+#include <linux/pcf50633.h>
+#include <linux/regulator/pcf50633.h>
+#include <linux/rtc/pcf50633.h>
+
+#if 0
+#define DEBUGP(x, args ...) printk("%s: " x, __FUNCTION__, ## args)
+#define DEBUGPC(x, args ...) printk(x, ## args)
+#else
+#define DEBUGP(x, args ...)
+#define DEBUGPC(x, args ...)
+#endif
+
+/***********************************************************************
+ * Static data / structures
+ ***********************************************************************/
+
+static unsigned short normal_i2c[] = { 0x73, I2C_CLIENT_END };
+
+I2C_CLIENT_INSMOD_1(pcf50633);
+
+enum close_state {
+ CLOSE_STATE_NOT,
+ CLOSE_STATE_ALLOW = 0x2342,
+};
+
+static struct i2c_driver pcf50633_driver;
+
+static void pcf50633_usb_curlim_set(struct pcf50633_data *pcf, int ma);
+static void pcf50633_charge_enable(struct pcf50633_data *pcf, int on);
+
+
+/***********************************************************************
+ * Low-Level routines
+ ***********************************************************************/
+
+/* Read a block of upto 32 regs
+ *
+ * Locks assumed to be held by caller
+ */
+int pcf50633_read(struct pcf50633_data *pcf, u_int8_t reg, int nr_regs, u_int8_t *data)
+{
+ return i2c_smbus_read_i2c_block_data(pcf->client, reg, nr_regs, data);
+}
+EXPORT_SYMBOL(pcf50633_read);
+
+/* Read a block of upto 32 regs
+ *
+ * Locks assumed to be held by caller
+ */
+int pcf50633_write(struct pcf50633_data *pcf, u_int8_t reg, int nr_regs, u_int8_t *data)
+{
+ return i2c_smbus_write_i2c_block_data(pcf->client, reg, nr_regs, data);
+}
+EXPORT_SYMBOL(pcf50633_write);
+
+static int __reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
+{
+ if (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND) {
+ dev_err(&pcf->client->dev, "__reg_write while suspended\n");
+ dump_stack();
+ }
+ return i2c_smbus_write_byte_data(pcf->client, reg, val);
+}
+
+int pcf50633_reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = __reg_write(pcf, reg, val);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(pcf50633_reg_write);
+
+static int32_t __reg_read(struct pcf50633_data *pcf, u_int8_t reg)
+{
+ int32_t ret;
+
+ if (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND) {
+ dev_err(&pcf->client->dev, "__reg_read while suspended\n");
+ dump_stack();
+ }
+ ret = i2c_smbus_read_byte_data(pcf->client, reg);
+
+ return ret;
+}
+
+u_int8_t pcf50633_reg_read(struct pcf50633_data *pcf, u_int8_t reg)
+{
+ int32_t ret;
+
+ mutex_lock(&pcf->lock);
+ ret = __reg_read(pcf, reg);
+ mutex_unlock(&pcf->lock);
+
+ return ret & 0xff;
+}
+EXPORT_SYMBOL(pcf50633_reg_read);
+
+int pcf50633_reg_set_bit_mask(struct pcf50633_data *pcf,
+ u_int8_t reg, u_int8_t mask, u_int8_t val)
+{
+ int ret;
+ u_int8_t tmp;
+
+ val &= mask;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = __reg_read(pcf, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ ret = __reg_write(pcf, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(pcf50633_reg_set_bit_mask);
+
+int pcf50633_reg_clear_bits(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val)
+{
+ int ret;
+ u_int8_t tmp;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = __reg_read(pcf, reg);
+ tmp &= ~val;
+ ret = __reg_write(pcf, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(pcf50633_reg_clear_bits);
+
+/* asynchronously setup reading one ADC channel */
+static void async_adc_read_setup(struct pcf50633_data *pcf,
+ int channel, int avg)
+{
+ channel &= PCF50633_ADCC1_ADCMUX_MASK;
+
+ /* kill ratiometric, but enable ACCSW biasing */
+ __reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
+ __reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
+
+ /* start ADC conversion of selected channel */
+ __reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
+ PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
+
+}
+
+static u_int16_t adc_read_result(struct pcf50633_data *pcf)
+{
+ u_int16_t ret = (__reg_read(pcf, PCF50633_REG_ADCS1) << 2) |
+ (__reg_read(pcf, PCF50633_REG_ADCS3) &
+ PCF50633_ADCS3_ADCDAT1L_MASK);
+
+ DEBUGPC("adc result = %d\n", ret);
+
+ return ret;
+}
+
+/* go into 'STANDBY' mode, i.e. power off the main CPU and peripherals */
+void pcf50633_go_standby(struct pcf50633_data *pcf)
+{
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
+ PCF50633_OOCSHDWN_GOSTDBY, PCF50633_OOCSHDWN_GOSTDBY);
+}
+EXPORT_SYMBOL_GPL(pcf50633_go_standby);
+
+void pcf50633_gpio_set(struct pcf50633_data *pcf, enum pcf50633_gpio gpio,
+ int on)
+{
+ u_int8_t reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
+
+ if (on)
+ pcf50633_reg_set_bit_mask(pcf, reg, 0x0f, 0x07);
+ else
+ pcf50633_reg_set_bit_mask(pcf, reg, 0x0f, 0x00);
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
+
+int pcf50633_gpio_get(struct pcf50633_data *pcf, enum pcf50633_gpio gpio)
+{
+ u_int8_t reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
+ u_int8_t val = pcf50633_reg_read(pcf, reg) & 0x0f;
+
+ if (val == PCF50633_GPOCFG_GPOSEL_1 ||
+ val == (PCF50633_GPOCFG_GPOSEL_0|PCF50633_GPOCFG_GPOSEL_INVERSE))
+ return 1;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
+
+static int interpret_charger_type_from_adc(struct pcf50633_data *pcf,
+ int sample)
+{
+ /* 1A capable charger? */
+
+ if (sample < ((ADC_NOM_CHG_DETECT_NONE + ADC_NOM_CHG_DETECT_1A) / 2))
+ return CHARGER_TYPE_1A;
+
+ /* well then, nothing in the USB hole, or USB host / unk adapter */
+
+ if (pcf->flags & PCF50633_F_USB_PRESENT) /* ooh power is in there */
+ return CHARGER_TYPE_HOSTUSB; /* HOSTUSB is the catchall */
+
+ return CHARGER_TYPE_NONE; /* no really -- nothing in there */
+}
+
+
+
+static void
+configure_pmu_for_charger(struct pcf50633_data *pcf,
+ void *unused, int adc_result_raw)
+{
+ int type;
+
+ type = interpret_charger_type_from_adc(
+ pcf, adc_result_raw);
+ switch (type) {
+ case CHARGER_TYPE_NONE:
+ pcf50633_usb_curlim_set(pcf, 0);
+ break;
+ /*
+ * the PCF50633 has a feature that it will supply only excess current
+ * from the charger that is not used to power the device. So this
+ * 500mA setting is "up to 500mA" according to that.
+ */
+ case CHARGER_TYPE_HOSTUSB:
+ /* USB subsystem should call pcf50633_usb_curlim_set to set
+ * what was negotiated with the host when it is enumerated
+ * successfully. If we get called again after a good
+ * negotiation, we keep what was negotiated. (Removal of
+ * USB plug destroys pcf->last_curlim_set to 0)
+ */
+ if (pcf->last_curlim_set > 100)
+ pcf50633_usb_curlim_set(pcf, pcf->last_curlim_set);
+ else
+ pcf50633_usb_curlim_set(pcf, 100);
+ break;
+ case CHARGER_TYPE_1A:
+ pcf50633_usb_curlim_set(pcf, 1000);
+ /*
+ * stop GPO / EN_HOSTUSB power driving out on the same
+ * USB power pins we have a 1A charger on right now!
+ */
+ dev_dbg(&pcf->client->dev, "Charger -> CHARGER_TYPE_1A\n");
+ __reg_write(pcf, PCF50633_GPO - PCF50633_GPIO1 +
+ PCF50633_REG_GPIO1CFG,
+ __reg_read(pcf, PCF50633_GPO - PCF50633_GPIO1 +
+ PCF50633_REG_GPIO1CFG) & 0xf0);
+ break;
+ }
+
+ /* max out USB fast charge current -- actual current drawn is
+ * additionally limited by USB limit so no worries
+ */
+ __reg_write(pcf, PCF50633_REG_MBCC5, 0xff);
+
+}
+
+static void trigger_next_adc_job_if_any(struct pcf50633_data *pcf)
+{
+ if (pcf->adc_queue_head == pcf->adc_queue_tail)
+ return;
+ async_adc_read_setup(pcf,
+ pcf->adc_queue[pcf->adc_queue_tail]->mux,
+ pcf->adc_queue[pcf->adc_queue_tail]->avg);
+}
+
+
+static void
+adc_add_request_to_queue(struct pcf50633_data *pcf, struct adc_request *req)
+{
+ int old_head = pcf->adc_queue_head;
+ pcf->adc_queue[pcf->adc_queue_head] = req;
+
+ pcf->adc_queue_head = (pcf->adc_queue_head + 1) &
+ (MAX_ADC_FIFO_DEPTH - 1);
+
+ /* it was idle before we just added this? we need to kick it then */
+ if (old_head == pcf->adc_queue_tail)
+ trigger_next_adc_job_if_any(pcf);
+}
+
+static void
+__pcf50633_adc_sync_read_callback(struct pcf50633_data *pcf, void *param, int result)
+{
+ struct adc_request *req;
+
+ /*We know here that the passed param is an adc_request object */
+ req = (struct adc_request *)param;
+
+ req->result = result;
+ complete(&req->completion);
+}
+
+int pcf50633_adc_sync_read(struct pcf50633_data *pcf, int mux, int avg)
+{
+
+ struct adc_request *req;
+ int result;
+
+ /* req is freed when the result is ready, in pcf50633_work*/
+ req = kmalloc(sizeof(*req), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->mux = mux;
+ req->avg = avg;
+ req->callback = __pcf50633_adc_sync_read_callback;
+ req->callback_param = req;
+ init_completion(&req->completion);
+
+ adc_add_request_to_queue(pcf, req);
+
+ wait_for_completion(&req->completion);
+ result = req->result;
+
+ return result;
+}
+
+int pcf50633_adc_async_read(struct pcf50633_data *pcf, int mux, int avg,
+ void (*callback)(struct pcf50633_data *, void *,int),
+ void *callback_param)
+{
+ struct adc_request *req;
+
+ /* req is freed when the result is ready, in pcf50633_work*/
+ req = kmalloc(sizeof(*req), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->mux = mux;
+ req->avg = avg;
+ req->callback = callback;
+ req->callback_param = callback_param;
+
+ adc_add_request_to_queue(pcf, req);
+
+ return 0;
+}
+
+/*
+ * we get run to handle servicing the async notification from USB stack that
+ * we got enumerated and allowed to draw a particular amount of current
+ */
+
+static void pcf50633_work_usbcurlim(struct work_struct *work)
+{
+ struct pcf50633_data *pcf =
+ container_of(work, struct pcf50633_data, work_usb_curlimit);
+
+ mutex_lock(&pcf->working_lock_usb_curlimit);
+
+ /* just can't cope with it if we are suspending, don't reschedule */
+ if ((pcf->suspend_state == PCF50633_SS_STARTING_SUSPEND) ||
+ (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND))
+ goto bail;
+
+ dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim\n");
+
+ if (!pcf->probe_completed)
+ goto reschedule;
+
+ /* we got a notification from USB stack before we completed resume...
+ * that can only make trouble, reschedule for a retry
+ */
+ if (pcf->suspend_state &&
+ (pcf->suspend_state < PCF50633_SS_COMPLETED_RESUME))
+ goto reschedule;
+
+ /*
+ * did he pull USB before we managed to set the limit?
+ */
+ if (pcf->usb_removal_count_usb_curlimit != pcf->usb_removal_count)
+ goto bail;
+
+ /* OK let's set the requested limit and finish */
+
+ dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim setting %dmA\n",
+ pcf->pending_curlimit);
+ pcf50633_usb_curlim_set(pcf, pcf->pending_curlimit);
+
+bail:
+ mutex_unlock(&pcf->working_lock_usb_curlimit);
+ return;
+
+reschedule:
+ dev_dbg(&pcf->client->dev, "pcf50633_work_usbcurlim rescheduling\n");
+ if (!schedule_work(&pcf->work_usb_curlimit))
+ dev_err(&pcf->client->dev, "curlim reschedule work "
+ "already queued\n");
+
+ mutex_unlock(&pcf->working_lock_usb_curlimit);
+ /* don't spew, delaying whatever else is happening */
+ msleep(1);
+}
+
+
+/* this is an export to allow machine to set USB current limit according to
+ * notifications of USB stack about enumeration state. We spawn a work
+ * function to handle the actual setting, because suspend / resume and such
+ * can be in a bad state since this gets called externally asychronous to
+ * anything else going on in pcf50633.
+ */
+
+int pcf50633_notify_usb_current_limit_change(struct pcf50633_data *pcf,
+ unsigned int ma)
+{
+ /* can happen if he calls before probe
+ * have to bail with error since we can't even schedule the work
+ */
+ if (!pcf) {
+ printk(KERN_ERR "pcf50633_notify_usb_current_limit called with NULL pcf\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(&pcf->client->dev,
+ "pcf50633_notify_usb_current_limit_change %dmA\n", ma);
+
+ /* prepare to detect USB power removal before we complete */
+ pcf->usb_removal_count_usb_curlimit = pcf->usb_removal_count;
+
+ pcf->pending_curlimit = ma;
+
+ if (!schedule_work(&pcf->work_usb_curlimit))
+ dev_err(&pcf->client->dev, "curlim work item already queued\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50633_notify_usb_current_limit_change);
+
+
+/* we are run when we see a NOBAT situation, because there is no interrupt
+ * source in pcf50633 that triggers on resuming charging. It watches to see
+ * if charging resumes, it reassesses the charging source if it does. If the
+ * USB power disappears, it is also a sign there must be a battery and it is
+ * NOT being charged, so it exits since the next move must be USB insertion for
+ * change of charger state
+ */
+
+static void pcf50633_work_nobat(struct work_struct *work)
+{
+ struct pcf50633_data *pcf =
+ container_of(work, struct pcf50633_data, work_nobat);
+
+ mutex_lock(&pcf->working_lock_nobat);
+ pcf->working_nobat = 1;
+ mutex_unlock(&pcf->working_lock_nobat);
+
+ while (1) {
+ msleep(1000);
+
+ if (pcf->suspend_state != PCF50633_SS_RUNNING)
+ continue;
+
+ /* there's a battery in there now? */
+ if (pcf50633_reg_read(pcf, PCF50633_REG_MBCS3) & 0x40) {
+
+ pcf->jiffies_last_bat_ins = jiffies;
+
+ /* figure out our charging stance */
+ (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16,
+ configure_pmu_for_charger,
+ NULL);
+ goto bail;
+ }
+
+ /* he pulled USB cable since we were started? exit then */
+ if (pcf->usb_removal_count_nobat != pcf->usb_removal_count)
+ goto bail;
+ }
+
+bail:
+ mutex_lock(&pcf->working_lock_nobat);
+ pcf->working_nobat = 0;
+ mutex_unlock(&pcf->working_lock_nobat);
+}
+
+
+static void pcf50633_work(struct work_struct *work)
+{
+ struct pcf50633_data *pcf =
+ container_of(work, struct pcf50633_data, work);
+ u_int8_t pcfirq[5];
+ int ret;
+ int tail;
+ struct adc_request *req;
+
+ mutex_lock(&pcf->working_lock);
+ pcf->working = 1;
+
+ /* sanity */
+ if (!&pcf->client->dev)
+ goto bail;
+
+ /*
+ * if we are presently suspending, we are not in a position to deal
+ * with pcf50633 interrupts at all.
+ *
+ * Because we didn't clear the int pending registers, there will be
+ * no edge / interrupt waiting for us when we wake. But it is OK
+ * because at the end of our resume, we call this workqueue function
+ * gratuitously, clearing the pending register and re-enabling
+ * servicing this interrupt.
+ */
+
+ if ((pcf->suspend_state == PCF50633_SS_STARTING_SUSPEND) ||
+ (pcf->suspend_state == PCF50633_SS_COMPLETED_SUSPEND))
+ goto bail;
+
+ /*
+ * If we are inside suspend -> resume completion time we don't attempt
+ * service until we have fully resumed. Although we could talk to the
+ * device as soon as I2C is up, the regs in the device which we might
+ * choose to modify as part of the service action have not been
+ * reloaded with their pre-suspend states yet. Therefore we will
+ * defer our service if we are called like that until our resume has
+ * completed.
+ *
+ * This shouldn't happen any more because we disable servicing this
+ * interrupt in suspend and don't re-enable it until resume is
+ * completed.
+ */
+
+ if (pcf->suspend_state &&
+ (pcf->suspend_state != PCF50633_SS_COMPLETED_RESUME))
+ goto reschedule;
+
+ /* this is the case early in resume! Sanity check! */
+ if (i2c_get_clientdata(pcf->client) == NULL)
+ goto reschedule;
+
+ /*
+ * datasheet says we have to read the five IRQ
+ * status regs in one transaction
+ */
+ ret = pcf50633_read(pcf, PCF50633_REG_INT1,
+ sizeof(pcfirq), pcfirq);
+ if (ret != sizeof(pcfirq)) {
+ dev_info(&pcf->client->dev,
+ "Oh crap PMU IRQ register read failed -- "
+ "retrying later %d\n", ret);
+ /*
+ * it shouldn't fail, we no longer attempt to use
+ * I2C while it can be suspended. But we don't have
+ * much option but to retry if if it ever did fail,
+ * because if we don't service the interrupt to clear
+ * it, we will never see another PMU interrupt edge.
+ */
+ goto reschedule;
+ }
+
+ /* hey did we just resume? (because we don't get here unless we are
+ * running normally or the first call after resumption)
+ */
+
+ if (pcf->suspend_state != PCF50633_SS_RUNNING) {
+ /*
+ * grab a copy of resume interrupt reasons
+ * from pcf50633 POV
+ */
+ memcpy(pcf->pcfirq_resume, pcfirq, sizeof(pcf->pcfirq_resume));
+
+ /* pcf50633 resume is really really over now then */
+ pcf->suspend_state = PCF50633_SS_RUNNING;
+
+ /* peek at the IRQ reason, if power button then set a flag
+ * so that we do not signal the event to userspace
+ */
+ if (pcfirq[1] & (PCF50633_INT2_ONKEYF | PCF50633_INT2_ONKEYR)) {
+ pcf->suppress_onkey_events = 1;
+ DEBUGP("Wake by ONKEY, suppressing ONKEY event");
+ } else {
+ pcf->suppress_onkey_events = 0;
+ }
+ }
+
+ if (!pcf->coldplug_done) {
+ DEBUGP("PMU Coldplug init\n");
+
+ /* we used SECOND to kick ourselves started -- turn it off */
+ pcfirq[0] &= ~PCF50633_INT1_SECOND;
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_INT1M,
+ PCF50633_INT1_SECOND,
+ PCF50633_INT1_SECOND);
+
+ /* coldplug the USB if present */
+ if ((__reg_read(pcf, PCF50633_REG_MBCS1) &
+ (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) ==
+ (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) {
+ DEBUGPC("COLD USBINS\n");
+ input_report_key(pcf->input_dev, KEY_POWER2, 1);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags |= PCF50633_F_USB_PRESENT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_USB_INSERT);
+ }
+
+ /* figure out our initial charging stance */
+ (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16,
+ configure_pmu_for_charger, NULL);
+
+ pcf->coldplug_done = 1;
+ }
+
+ DEBUGP("INT1=0x%02x INT2=0x%02x INT3=0x%02x INT4=0x%02x INT5=0x%02x\n",
+ pcfirq[0], pcfirq[1], pcfirq[2], pcfirq[3], pcfirq[4]);
+
+ if (pcfirq[0] & PCF50633_INT1_ADPINS) {
+ /* Charger inserted */
+ DEBUGPC("ADPINS ");
+ input_report_key(pcf->input_dev, KEY_BATTERY, 1);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags |= PCF50633_F_CHG_PRESENT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_INSERT);
+ }
+ if (pcfirq[0] & PCF50633_INT1_ADPREM) {
+ /* Charger removed */
+ DEBUGPC("ADPREM ");
+ input_report_key(pcf->input_dev, KEY_BATTERY, 0);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags &= ~PCF50633_F_CHG_PRESENT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_REMOVE);
+ }
+ if (pcfirq[0] & PCF50633_INT1_USBINS) {
+ DEBUGPC("USBINS ");
+ input_report_key(pcf->input_dev, KEY_POWER2, 1);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags |= PCF50633_F_USB_PRESENT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_USB_INSERT);
+ msleep(500); /* debounce, allow to see any ID resistor */
+ /* completion irq will figure out our charging stance */
+ (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16,
+ configure_pmu_for_charger, NULL);
+ }
+ if (pcfirq[0] & PCF50633_INT1_USBREM &&
+ !(pcfirq[0] & PCF50633_INT1_USBINS)) {
+ /* the occurrence of USBINS and USBREM
+ * should be exclusive in one schedule work
+ */
+ DEBUGPC("USBREM ");
+
+ pcf->usb_removal_count++;
+
+ /* only deal if we had understood it was in */
+ if (pcf->flags & PCF50633_F_USB_PRESENT) {
+ input_report_key(pcf->input_dev, KEY_POWER2, 0);
+ apm_queue_event(APM_POWER_STATUS_CHANGE);
+ pcf->flags &= ~PCF50633_F_USB_PRESENT;
+
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_USB_REMOVE);
+
+ /* destroy any memory of grant of power from host */
+ pcf->last_curlim_set = 0;
+
+ /* completion irq will figure out our charging stance */
+ (void)pcf50633_adc_async_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16,
+ configure_pmu_for_charger, NULL);
+ }
+ }
+ if (pcfirq[0] & PCF50633_INT1_ALARM) {
+ DEBUGPC("ALARM ");
+ if (pcf->pdata->used_features & PCF50633_FEAT_RTC)
+ pcf50633_rtc_handle_event(pcf,
+ PCF50633_RTC_EVENT_ALARM);
+ }
+ if (pcfirq[0] & PCF50633_INT1_SECOND) {
+ DEBUGPC("SECOND ");
+ if (pcf->flags & PCF50633_F_RTC_SECOND)
+ pcf50633_rtc_handle_event(pcf,
+ PCF50633_RTC_EVENT_SECOND);
+
+ if (pcf->onkey_seconds >= 0 &&
+ pcf->flags & PCF50633_F_PWR_PRESSED) {
+ DEBUGP("ONKEY_SECONDS(%u, OOCSTAT=0x%02x) ",
+ pcf->onkey_seconds,
+ pcf50633_reg_read(pcf, PCF50633_REG_OOCSTAT));
+ pcf->onkey_seconds++;
+ if (pcf->onkey_seconds >=
+ pcf->pdata->onkey_seconds_sig_init) {
+ /* Ask init to do 'ctrlaltdel' */
+ /*
+ * currently Linux reacts badly to issuing a
+ * signal to PID #1 before init is started.
+ * What happens is that the next kernel thread
+ * to start, which is the JFFS2 Garbage
+ * collector in our case, gets the signal
+ * instead and proceeds to fail to fork --
+ * which is very bad. Therefore we confirm
+ * PID #1 exists before issuing the signal
+ */
+ if (find_task_by_pid_ns(1, &init_pid_ns)) {
+ kill_pid(task_pid(find_task_by_pid_ns(1,
+ &init_pid_ns)), SIGPWR, 1);
+ DEBUGPC("SIGINT(init) ");
+ }
+ /* FIXME: what if userspace doesn't shut down? */
+ }
+ if (pcf->onkey_seconds >=
+ pcf->pdata->onkey_seconds_shutdown) {
+ DEBUGPC("Power Off ");
+ pcf50633_go_standby(pcf);
+ }
+ }
+ }
+
+ if (pcfirq[1] & PCF50633_INT2_ONKEYF) {
+ /* ONKEY falling edge (start of button press) */
+ pcf->flags |= PCF50633_F_PWR_PRESSED;
+ if (!pcf->suppress_onkey_events) {
+ DEBUGPC("ONKEYF ");
+ input_report_key(pcf->input_dev, KEY_POWER, 1);
+ } else {
+ DEBUGPC("ONKEYF(unreported) ");
+ }
+ }
+ if (pcfirq[1] & PCF50633_INT2_ONKEYR) {
+ /* ONKEY rising edge (end of button press) */
+ pcf->flags &= ~PCF50633_F_PWR_PRESSED;
+ pcf->onkey_seconds = -1;
+ if (!pcf->suppress_onkey_events) {
+ DEBUGPC("ONKEYR ");
+ input_report_key(pcf->input_dev, KEY_POWER, 0);
+ } else {
+ DEBUGPC("ONKEYR(unreported) ");
+ /* don't suppress any more power button events */
+ pcf->suppress_onkey_events = 0;
+ }
+ /* disable SECOND interrupt in case RTC didn't
+ * request it */
+ if (!(pcf->flags & PCF50633_F_RTC_SECOND))
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_INT1M,
+ PCF50633_INT1_SECOND,
+ PCF50633_INT1_SECOND);
+ }
+ /* FIXME: we don't use EXTON1/2/3. thats why we skip it */
+
+ if (pcfirq[2] & PCF50633_INT3_BATFULL) {
+ DEBUGPC("BATFULL ");
+
+ /* the problem is, we get a false BATFULL if we inserted battery
+ * while USB powered. Defeat BATFULL if we recently inserted
+ * battery
+ */
+
+ if ((jiffies - pcf->jiffies_last_bat_ins) < (HZ * 2)) {
+
+ DEBUGPC("*** Ignoring BATFULL ***\n");
+
+ ret = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
+ PCF56033_MBCC7_USB_MASK;
+
+
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
+ PCF56033_MBCC7_USB_MASK,
+ PCF50633_MBCC7_USB_SUSPEND);
+
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
+ PCF56033_MBCC7_USB_MASK,
+ ret);
+ } else {
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
+ }
+
+ /* FIXME: signal this to userspace */
+ }
+ if (pcfirq[2] & PCF50633_INT3_CHGHALT) {
+ DEBUGPC("CHGHALT ");
+ /*
+ * this is really "battery not pulling current" -- it can
+ * appear with no battery attached
+ */
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
+ }
+ if (pcfirq[2] & PCF50633_INT3_THLIMON) {
+ DEBUGPC("THLIMON ");
+ pcf->flags |= PCF50633_F_CHG_PROT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
+ }
+ if (pcfirq[2] & PCF50633_INT3_THLIMOFF) {
+ DEBUGPC("THLIMOFF ");
+ pcf->flags &= ~PCF50633_F_CHG_PROT;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
+ }
+ if (pcfirq[2] & PCF50633_INT3_USBLIMON) {
+ DEBUGPC("USBLIMON ");
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
+ }
+ if (pcfirq[2] & PCF50633_INT3_USBLIMOFF) {
+ DEBUGPC("USBLIMOFF ");
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_CHANGE);
+ }
+ if (pcfirq[2] & PCF50633_INT3_ADCRDY) {
+ /* ADC result ready */
+ DEBUGPC("ADCRDY ");
+ tail = pcf->adc_queue_tail;
+ pcf->adc_queue_tail = (pcf->adc_queue_tail + 1) &
+ (MAX_ADC_FIFO_DEPTH - 1);
+ req = pcf->adc_queue[tail];
+ req->callback(pcf, req->callback_param,
+ adc_read_result(pcf));
+ kfree(req);
+
+ trigger_next_adc_job_if_any(pcf);
+ }
+ if (pcfirq[2] & PCF50633_INT3_ONKEY1S) {
+ /* ONKEY pressed for more than 1 second */
+ pcf->onkey_seconds = 0;
+ DEBUGPC("ONKEY1S ");
+ /* Tell PMU we are taking care of this */
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
+ PCF50633_OOCSHDWN_TOTRST,
+ PCF50633_OOCSHDWN_TOTRST);
+ /* enable SECOND interrupt (hz tick) */
+ pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, PCF50633_INT1_SECOND);
+ }
+
+ if (pcfirq[3] & (PCF50633_INT4_LOWBAT|PCF50633_INT4_LOWSYS)) {
+ if ((__reg_read(pcf, PCF50633_REG_MBCS1) &
+ (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) ==
+ (PCF50633_MBCS1_USBPRES | PCF50633_MBCS1_USBOK)) {
+ /*
+ * hey no need to freak out, we have some kind of
+ * valid charger power to keep us going -- but note that
+ * we are not actually charging anything
+ */
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
+
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_RESUME,
+ PCF50633_MBCC1_RESUME);
+
+ /*
+ * Well, we are not charging anything right this second
+ * ... however in the next ~30s before we get the next
+ * NOBAT, he might insert a battery. So we schedule a
+ * work function checking to see if
+ * we started charging something during that time.
+ * USB removal as well as charging terminates the work
+ * function so we can't get terminally confused
+ */
+ mutex_lock(&pcf->working_lock_nobat);
+ if (!pcf->working_nobat) {
+ pcf->usb_removal_count_nobat =
+ pcf->usb_removal_count;
+
+ if (!schedule_work(&pcf->work_nobat))
+ DEBUGPC("failed to schedule nobat\n");
+ }
+ mutex_unlock(&pcf->working_lock_nobat);
+
+
+ DEBUGPC("(NO)BAT ");
+ } else {
+ /* Really low battery voltage, we have 8 seconds left */
+ DEBUGPC("LOWBAT ");
+ /*
+ * currently Linux reacts badly to issuing a signal to
+ * PID #1 before init is started. What happens is that
+ * the next kernel thread to start, which is the JFFS2
+ * Garbage collector in our case, gets the signal
+ * instead and proceeds to fail to fork -- which is
+ * very bad. Therefore we confirm PID #1 exists
+ * before issuing SPIGPWR
+ */
+
+ if (find_task_by_pid_ns(1, &init_pid_ns)) {
+ apm_queue_event(APM_LOW_BATTERY);
+ DEBUGPC("SIGPWR(init) ");
+ kill_pid(task_pid(find_task_by_pid_ns(1, &init_pid_ns)), SIGPWR, 1);
+ } else
+ /*
+ * well, our situation is like this: we do not
+ * have any external power, we have a low
+ * battery and since PID #1 doesn't exist yet,
+ * we are early in the boot, likely before
+ * rootfs mount. We should just call it a day
+ */
+ apm_queue_event(APM_CRITICAL_SUSPEND);
+ }
+
+ /* Tell PMU we are taking care of this */
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_OOCSHDWN,
+ PCF50633_OOCSHDWN_TOTRST,
+ PCF50633_OOCSHDWN_TOTRST);
+ }
+ if (pcfirq[3] & PCF50633_INT4_HIGHTMP) {
+ /* High temperature */
+ DEBUGPC("HIGHTMP ");
+ apm_queue_event(APM_CRITICAL_SUSPEND);
+ }
+ if (pcfirq[3] & PCF50633_INT4_AUTOPWRFAIL) {
+ DEBUGPC("PCF50633_INT4_AUTOPWRFAIL ");
+ /* FIXME: deal with this */
+ }
+ if (pcfirq[3] & PCF50633_INT4_DWN1PWRFAIL) {
+ DEBUGPC("PCF50633_INT4_DWN1PWRFAIL ");
+ /* FIXME: deal with this */
+ }
+ if (pcfirq[3] & PCF50633_INT4_DWN2PWRFAIL) {
+ DEBUGPC("PCF50633_INT4_DWN2PWRFAIL ");
+ /* FIXME: deal with this */
+ }
+ if (pcfirq[3] & PCF50633_INT4_LEDPWRFAIL) {
+ DEBUGPC("PCF50633_INT4_LEDPWRFAIL ");
+ /* FIXME: deal with this */
+ }
+ if (pcfirq[3] & PCF50633_INT4_LEDOVP) {
+ DEBUGPC("PCF50633_INT4_LEDOVP ");
+ /* FIXME: deal with this */
+ }
+
+ DEBUGPC("\n");
+
+bail:
+ pcf->working = 0;
+ input_sync(pcf->input_dev);
+ put_device(&pcf->client->dev);
+ mutex_unlock(&pcf->working_lock);
+
+ return;
+
+reschedule:
+ /* don't spew, delaying whatever else is happening */
+ /* EXCEPTION: if we are in the middle of suspending, we don't have
+ * time to hang around since we may be turned off core 1V3 already
+ */
+ if ((pcf->suspend_state != PCF50633_SS_STARTING_SUSPEND) &&
+ (pcf->suspend_state != PCF50633_SS_COMPLETED_SUSPEND)) {
+ msleep(10);
+ dev_dbg(&pcf->client->dev, "rescheduling interrupt service\n");
+ }
+ if (!schedule_work(&pcf->work))
+ dev_err(&pcf->client->dev, "int service reschedule failed\n");
+
+ /* we don't put the device here, hold it for next time */
+ mutex_unlock(&pcf->working_lock);
+}
+
+static irqreturn_t pcf50633_irq(int irq, void *_pcf)
+{
+ struct pcf50633_data *pcf = _pcf;
+
+ DEBUGP("entering(irq=%u, pcf=%p): scheduling work\n", irq, _pcf);
+ dev_dbg(&pcf->client->dev, "pcf50633_irq scheduling work\n");
+
+ get_device(&pcf->client->dev);
+ if (!schedule_work(&pcf->work) && !pcf->working)
+ dev_err(&pcf->client->dev, "pcf irq work already queued\n");
+
+ return IRQ_HANDLED;
+}
+
+static u_int16_t adc_to_batt_millivolts(u_int16_t adc)
+{
+ u_int16_t mvolts;
+
+ mvolts = (adc * 6000) / 1024;
+
+ return mvolts;
+}
+
+#define BATTVOLT_SCALE_START 2800
+#define BATTVOLT_SCALE_END 4200
+#define BATTVOLT_SCALE_DIVIDER ((BATTVOLT_SCALE_END - BATTVOLT_SCALE_START)/100)
+
+static u_int8_t battvolt_scale(u_int16_t battvolt)
+{
+ /* FIXME: this linear scale is completely bogus */
+ u_int16_t battvolt_relative = battvolt - BATTVOLT_SCALE_START;
+ unsigned int percent = battvolt_relative / BATTVOLT_SCALE_DIVIDER;
+
+ return percent;
+}
+
+u_int16_t pcf50633_battvolt(struct pcf50633_data *pcf)
+{
+ int ret;
+
+ ret = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_BATSNS_RES,
+ PCF50633_ADCC1_AVERAGE_16);
+
+ if (ret < 0)
+ return ret;
+
+ return adc_to_batt_millivolts(ret);
+}
+
+EXPORT_SYMBOL_GPL(pcf50633_battvolt);
+
+static ssize_t show_battvolt(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+
+ return sprintf(buf, "%u\n", pcf50633_battvolt(pcf));
+}
+static DEVICE_ATTR(battvolt, S_IRUGO | S_IWUSR, show_battvolt, NULL);
+
+/***********************************************************************
+ * Charger Control
+ ***********************************************************************/
+
+/* Set maximum USB current limit */
+static void pcf50633_usb_curlim_set(struct pcf50633_data *pcf, int ma)
+{
+ u_int8_t bits;
+ int active = 0;
+
+ pcf->last_curlim_set = ma;
+
+ dev_dbg(&pcf->client->dev, "setting usb current limit to %d ma", ma);
+
+ if (ma >= 1000) {
+ bits = PCF50633_MBCC7_USB_1000mA;
+ }
+ else if (ma >= 500)
+ bits = PCF50633_MBCC7_USB_500mA;
+ else if (ma >= 100)
+ bits = PCF50633_MBCC7_USB_100mA;
+ else
+ bits = PCF50633_MBCC7_USB_SUSPEND;
+
+ /* set the nearest charging limit */
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7, PCF56033_MBCC7_USB_MASK,
+ bits);
+
+ /* with this charging limit, is charging actually meaningful? */
+ switch (bits) {
+ case PCF50633_MBCC7_USB_500mA:
+ case PCF50633_MBCC7_USB_1000mA:
+ /* yes with this charging limit, we can do real charging */
+ active = 1;
+ break;
+ default: /* right charging context that if there is power, we charge */
+ if (pcf->flags & PCF50633_F_USB_PRESENT)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_ACTIVE);
+ break;
+ }
+ /*
+ * enable or disable charging according to current limit -- this will
+ * also throw a platform notification callback about it
+ */
+ pcf50633_charge_enable(pcf, active);
+
+ /* clear batfull */
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_AUTORES,
+ 0);
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_RESUME,
+ PCF50633_MBCC1_RESUME);
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_AUTORES,
+ PCF50633_MBCC1_AUTORES);
+
+}
+
+static ssize_t show_usblim(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ u_int8_t usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
+ PCF56033_MBCC7_USB_MASK;
+ unsigned int ma;
+
+ if (usblim == PCF50633_MBCC7_USB_1000mA)
+ ma = 1000;
+ else if (usblim == PCF50633_MBCC7_USB_500mA)
+ ma = 500;
+ else if (usblim == PCF50633_MBCC7_USB_100mA)
+ ma = 100;
+ else
+ ma = 0;
+
+ return sprintf(buf, "%u\n", ma);
+}
+static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, NULL);
+
+/* Enable/disable charging */
+static void pcf50633_charge_enable(struct pcf50633_data *pcf, int on)
+{
+ u_int8_t bits;
+ u_int8_t usblim;
+
+ if (!(pcf->pdata->used_features & PCF50633_FEAT_MBC))
+ return;
+
+ DEBUGPC("pcf50633_charge_enable %d\n", on);
+
+ if (on) {
+ pcf->flags |= PCF50633_F_CHG_ENABLED;
+ bits = PCF50633_MBCC1_CHGENA;
+ usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
+ PCF56033_MBCC7_USB_MASK;
+ switch (usblim) {
+ case PCF50633_MBCC7_USB_1000mA:
+ case PCF50633_MBCC7_USB_500mA:
+ if (pcf->flags & PCF50633_F_USB_PRESENT)
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC,
+ PMU_EVT_CHARGER_ACTIVE);
+ break;
+ default:
+ break;
+ }
+ } else {
+ pcf->flags &= ~PCF50633_F_CHG_ENABLED;
+ bits = 0;
+ if (pcf->pdata->cb)
+ pcf->pdata->cb(&pcf->client->dev,
+ PCF50633_FEAT_MBC, PMU_EVT_CHARGER_IDLE);
+ }
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1, PCF50633_MBCC1_CHGENA,
+ bits);
+}
+
+#if 0
+#define ONE 1000000
+static u_int16_t adc_to_rntc(struct pcf50633_data *pcf, u_int16_t adc)
+{
+ u_int32_t r_batt = (adc * pcf->pdata->r_fix_batt) / (1023 - adc);
+ u_int16_t r_ntc;
+
+ /* The battery NTC has a parallell 10kOhms resistor */
+ r_ntc = ONE / ((ONE/r_batt) - (ONE/pcf->pdata->r_fix_batt_par));
+
+ return r_ntc;
+}
+#endif
+static ssize_t show_battemp(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "\n");
+}
+static DEVICE_ATTR(battemp, S_IRUGO | S_IWUSR, show_battemp, NULL);
+#if 0
+static u_int16_t adc_to_chg_milliamps(struct pcf50633_data *pcf,
+ u_int16_t adc_adcin1,
+ u_int16_t adc_batvolt)
+{
+ u_int32_t res = ((adc_adcin1 - adc_batvolt) * 6000);
+ return res / (pcf->pdata->r_sense_milli * 1024 / 1000);
+}
+#endif
+static ssize_t show_chgcur(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "\n");
+}
+static DEVICE_ATTR(chgcur, S_IRUGO | S_IWUSR, show_chgcur, NULL);
+
+static const char *chgmode_names[] = {
+ [PCF50633_MBCS2_MBC_PLAY] = "play-only",
+ [PCF50633_MBCS2_MBC_USB_PRE] = "pre",
+ [PCF50633_MBCS2_MBC_ADP_PRE] = "pre",
+ [PCF50633_MBCS2_MBC_USB_PRE_WAIT] = "pre-wait",
+ [PCF50633_MBCS2_MBC_ADP_PRE_WAIT] = "pre-wait",
+ [PCF50633_MBCS2_MBC_USB_FAST] = "fast",
+ [PCF50633_MBCS2_MBC_ADP_FAST] = "fast",
+ [PCF50633_MBCS2_MBC_USB_FAST_WAIT] = "fast-wait",
+ [PCF50633_MBCS2_MBC_ADP_FAST_WAIT] = "fast-wait",
+ [PCF50633_MBCS2_MBC_ADP_FAST_WAIT] = "bat-full",
+};
+
+static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ u_int8_t mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
+ u_int8_t chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
+
+ return sprintf(buf, "%s\n", chgmode_names[chgmod]);
+}
+
+static ssize_t set_chgmode(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+
+ /* As opposed to the PCF50606, we can only enable or disable
+ * charging and not directly jump into a certain mode! */
+
+ if (!strcmp(buf, "0\n"))
+ pcf50633_charge_enable(pcf, 0);
+ else
+ pcf50633_charge_enable(pcf, 1);
+
+ return count;
+}
+
+static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, set_chgmode);
+
+static const char *chgstate_names[] = {
+ [PCF50633_FIDX_CHG_ENABLED] = "enabled",
+ [PCF50633_FIDX_CHG_PRESENT] = "charger_present",
+ [PCF50633_FIDX_USB_PRESENT] = "usb_present",
+ [PCF50633_FIDX_CHG_ERR] = "error",
+ [PCF50633_FIDX_CHG_PROT] = "protection",
+ [PCF50633_FIDX_CHG_READY] = "ready",
+};
+
+static ssize_t show_chgstate(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+
+ char *b = buf;
+ int i;
+
+ for (i = 0; i < 32; i++)
+ if (pcf->flags & (1 << i) && i < ARRAY_SIZE(chgstate_names))
+ b += sprintf(b, "%s ", chgstate_names[i]);
+
+ if (b > buf)
+ b += sprintf(b, "\n");
+
+ return b - buf;
+}
+static DEVICE_ATTR(chgstate, S_IRUGO | S_IWUSR, show_chgstate, NULL);
+
+/*
+ * Charger type
+ */
+
+static ssize_t show_charger_type(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ int adc_raw_result, charger_type;
+
+ static const char *names_charger_type[] = {
+ [CHARGER_TYPE_NONE] = "none",
+ [CHARGER_TYPE_HOSTUSB] = "host/500mA usb",
+ [CHARGER_TYPE_1A] = "charger 1A",
+ };
+ static const char *names_charger_modes[] = {
+ [PCF50633_MBCC7_USB_1000mA] = "1A",
+ [PCF50633_MBCC7_USB_500mA] = "500mA",
+ [PCF50633_MBCC7_USB_100mA] = "100mA",
+ [PCF50633_MBCC7_USB_SUSPEND] = "suspend",
+ };
+ int mode = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) & PCF56033_MBCC7_USB_MASK;
+
+ adc_raw_result = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16);
+ charger_type = interpret_charger_type_from_adc(pcf, adc_raw_result);
+ return sprintf(buf, "%s mode %s\n",
+ names_charger_type[charger_type],
+ names_charger_modes[mode]);
+}
+
+static DEVICE_ATTR(charger_type, 0444, show_charger_type, NULL);
+
+static ssize_t force_usb_limit_dangerous(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ int ma = simple_strtoul(buf, NULL, 10);
+
+ pcf50633_usb_curlim_set(pcf, ma);
+ return count;
+}
+
+static DEVICE_ATTR(force_usb_limit_dangerous, 0600,
+ NULL, force_usb_limit_dangerous);
+
+/*
+ * Charger adc
+ */
+
+static ssize_t show_charger_adc(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ int result;
+
+ result = pcf50633_adc_sync_read(pcf, PCF50633_ADCC1_MUX_ADCIN1,
+ PCF50633_ADCC1_AVERAGE_16);
+ if (result < 0)
+ return result;
+
+ return sprintf(buf, "%d\n", result);
+}
+
+static DEVICE_ATTR(charger_adc, 0444, show_charger_adc, NULL);
+
+/*
+ * Dump regs
+ */
+
+static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ u8 dump[16];
+ int n, n1, idx = 0;
+ char *buf1 = buf;
+ static u8 address_no_read[] = { /* must be ascending */
+ PCF50633_REG_INT1,
+ PCF50633_REG_INT2,
+ PCF50633_REG_INT3,
+ PCF50633_REG_INT4,
+ PCF50633_REG_INT5,
+ 0 /* terminator */
+ };
+
+ for (n = 0; n < 256; n += sizeof(dump)) {
+
+ for (n1 = 0; n1 < sizeof(dump); n1++)
+ if (n == address_no_read[idx]) {
+ idx++;
+ dump[n1] = 0x00;
+ } else
+ dump[n1] = pcf50633_reg_read(pcf, n + n1);
+
+ hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
+ buf1 += strlen(buf1);
+ *buf1++ = '\n';
+ *buf1 = '\0';
+ }
+
+ return buf1 - buf;
+}
+
+static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
+
+
+/***********************************************************************
+ * Driver initialization
+ ***********************************************************************/
+
+/*
+ * CARE! This table is modified at runtime!
+ */
+static struct attribute *pcf_sysfs_entries[] = {
+ &dev_attr_charger_type.attr,
+ &dev_attr_force_usb_limit_dangerous.attr,
+ &dev_attr_charger_adc.attr,
+ &dev_attr_dump_regs.attr,
+ NULL, /* going to add things at this point! */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static struct attribute_group pcf_attr_group = {
+ .name = NULL, /* put in device directory */
+ .attrs = pcf_sysfs_entries,
+};
+
+static void populate_sysfs_group(struct pcf50633_data *pcf)
+{
+ int i = 0;
+ struct attribute **attr;
+
+ for (attr = pcf_sysfs_entries; *attr; attr++)
+ i++;
+
+ if (pcf->pdata->used_features & PCF50633_FEAT_MBC) {
+ pcf_sysfs_entries[i++] = &dev_attr_chgstate.attr;
+ pcf_sysfs_entries[i++] = &dev_attr_chgmode.attr;
+ pcf_sysfs_entries[i++] = &dev_attr_usb_curlim.attr;
+ }
+
+ if (pcf->pdata->used_features & PCF50633_FEAT_CHGCUR)
+ pcf_sysfs_entries[i++] = &dev_attr_chgcur.attr;
+
+ if (pcf->pdata->used_features & PCF50633_FEAT_BATVOLT)
+ pcf_sysfs_entries[i++] = &dev_attr_battvolt.attr;
+
+ if (pcf->pdata->used_features & PCF50633_FEAT_BATTEMP)
+ pcf_sysfs_entries[i++] = &dev_attr_battemp.attr;
+
+}
+
+static struct platform_device pcf50633_rtc_pdev = {
+ .name = "pcf50633-rtc",
+ .id = -1,
+};
+
+static int pcf50633_probe(struct i2c_client *client, const struct i2c_device_id *ids)
+{
+ struct pcf50633_data *pcf;
+ struct pcf50633_platform_data *pdata;
+ int err = 0;
+ int irq;
+ int i;
+
+ DEBUGP("entering probe\n");
+
+ pdata = client->dev.platform_data;
+
+ pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
+ if (!pcf)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, pcf);
+ irq = client->irq;
+ mutex_init(&pcf->lock);
+ mutex_init(&pcf->working_lock);
+ mutex_init(&pcf->working_lock_nobat);
+ mutex_init(&pcf->working_lock_usb_curlimit);
+ INIT_WORK(&pcf->work, pcf50633_work);
+ INIT_WORK(&pcf->work_nobat, pcf50633_work_nobat);
+ INIT_WORK(&pcf->work_usb_curlimit, pcf50633_work_usbcurlim);
+
+ pcf->client = client;
+ pcf->irq = irq;
+ pcf->working = 0;
+ pcf->suppress_onkey_events = 0;
+ pcf->onkey_seconds = -1;
+ pcf->pdata = pdata;
+
+ /* FIXME: now we try to detect the chip */
+
+ populate_sysfs_group(pcf);
+
+ err = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
+ if (err) {
+ dev_err(&client->dev, "error creating sysfs group\n");
+ goto exit_free;
+ }
+
+ /* create virtual charger 'device' */
+
+ /* register power off handler with core power management */
+ /* FIXME : pm_power_off = &pcf50633_go_standby; */
+
+ pcf->input_dev = input_allocate_device();
+ if (!pcf->input_dev)
+ goto exit_sysfs;
+
+ pcf->input_dev->name = "GTA02 PMU events";
+ pcf->input_dev->phys = "FIXME";
+ pcf->input_dev->id.bustype = BUS_I2C;
+
+ pcf->input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
+ set_bit(KEY_POWER, pcf->input_dev->keybit);
+ set_bit(KEY_POWER2, pcf->input_dev->keybit);
+ set_bit(KEY_BATTERY, pcf->input_dev->keybit);
+
+ err = input_register_device(pcf->input_dev);
+ if (err)
+ goto exit_sysfs;
+
+ /* configure interrupt mask */
+
+ /* we want SECOND to kick for the coldplug initialisation */
+ pcf50633_reg_write(pcf, PCF50633_REG_INT1M, 0x00);
+
+ pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
+
+ /* force the backlight up, Qi does not do this for us */
+
+ /* pcf50633 manual p60
+ * "led_out should never be set to 000000, as this would result
+ * in a deadlock making it impossible to program another value.
+ * If led_out should be inadvertently set to 000000, the
+ * LEDOUT register can be reset by disabling and enabling the
+ * LED converter via control bit led_on in the LEDENA register"
+ */
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDDIM, 0x01);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDENA, 0x01);
+ pcf50633_reg_write(pcf, PCF50633_REG_LEDOUT, 0x3f);
+
+ err = request_irq(irq, pcf50633_irq, IRQF_TRIGGER_FALLING,
+ "pcf50633", pcf);
+ if (err < 0)
+ goto exit_input;
+
+ if (enable_irq_wake(irq) < 0)
+ dev_err(&client->dev, "IRQ %u cannot be enabled as wake-up"
+ "source in this hardware revision!\n", irq);
+
+ if (pcf->pdata->used_features & PCF50633_FEAT_RTC) {
+ pcf50633_rtc_pdev.dev.platform_data = pcf;
+
+ err = platform_device_register(&pcf50633_rtc_pdev);
+ if (err)
+ goto exit_irq;
+ }
+
+ if (pcf->pdata->flag_use_apm_emulation)
+ apm_get_power_status = NULL;
+
+ pdata->pcf = pcf;
+
+ /* Create platform regulator devices from the platform data */
+ for (i = 0; i < __NUM_PCF50633_REGULATORS; i++) {
+ struct platform_device *pdev;
+
+ pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+ /* FIXME : Handle failure */
+
+ pdev->name = "pcf50633-regltr";
+ pdev->id = i;
+ pdev->dev.parent = &client->dev;
+ pdev->dev.platform_data = &pdata->reg_init_data[i];
+ pdev->dev.driver_data = pcf;
+ pcf->regulator_pdev[i] = pdev;
+
+ platform_device_register(pdev);
+ }
+
+ pcf->probe_completed = 1;
+
+ /* if platform was interested, give him a chance to register
+ * platform devices that switch power with us as the parent
+ * at registration time -- ensures suspend / resume ordering
+ */
+ if (pcf->pdata->attach_child_devices)
+ (pcf->pdata->attach_child_devices)(&client->dev);
+
+ dev_info(&client->dev, "probe completed\n");
+
+ return 0;
+exit_irq:
+ free_irq(pcf->irq, pcf);
+exit_input:
+ input_unregister_device(pcf->input_dev);
+exit_sysfs:
+ pm_power_off = NULL;
+ sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
+exit_free:
+ kfree(pcf);
+ return err;
+}
+
+static int pcf50633_remove(struct i2c_client *client)
+{
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+
+ DEBUGP("entering\n");
+
+ apm_get_power_status = NULL;
+
+ free_irq(pcf->irq, pcf);
+
+ input_unregister_device(pcf->input_dev);
+
+ if (pcf->pdata->used_features & PCF50633_FEAT_RTC)
+ rtc_device_unregister(pcf->rtc);
+
+ sysfs_remove_group(&client->dev.kobj, &pcf_attr_group);
+
+ pm_power_off = NULL;
+
+ kfree(pcf);
+
+ return 0;
+}
+
+/* you're going to need >300 bytes in buf */
+
+int pcf50633_report_resumers(struct pcf50633_data *pcf, char *buf)
+{
+ static char *int_names[] = {
+ "adpins",
+ "adprem",
+ "usbins",
+ "usbrem",
+ NULL,
+ NULL,
+ "rtcalarm",
+ "second",
+
+ "onkeyr",
+ "onkeyf",
+ "exton1r",
+ "exton1f",
+ "exton2r",
+ "exton2f",
+ "exton3r",
+ "exton3f",
+
+ "batfull",
+ "chghalt",
+ "thlimon",
+ "thlimoff",
+ "usblimon",
+ "usblimoff",
+ "adcrdy",
+ "onkey1s",
+
+ "lowsys",
+ "lowbat",
+ "hightmp",
+ "autopwrfail",
+ "dwn1pwrfail",
+ "dwn2pwrfail",
+ "ledpwrfail",
+ "ledovp",
+
+ "ldo1pwrfail",
+ "ldo2pwrfail",
+ "ldo3pwrfail",
+ "ldo4pwrfail",
+ "ldo5pwrfail",
+ "ldo6pwrfail",
+ "hcidopwrfail",
+ "hcidoovl"
+ };
+ char *end = buf;
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(int_names); n++)
+ if (int_names[n]) {
+ if (pcf->pcfirq_resume[n >> 3] & (1 >> (n & 7)))
+ end += sprintf(end, " * %s\n", int_names[n]);
+ else
+ end += sprintf(end, " %s\n", int_names[n]);
+ }
+
+ return end - buf;
+}
+
+
+#ifdef CONFIG_PM
+
+static int pcf50633_suspend(struct device *dev, pm_message_t state)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ int i;
+ int ret;
+ u_int8_t res[5];
+
+ dev_err(dev, "pcf50633_suspend\n");
+
+ /* we suspend once (!) as late as possible in the suspend sequencing */
+
+ if ((state.event != PM_EVENT_SUSPEND) ||
+ (pcf->suspend_state != PCF50633_SS_RUNNING))
+ return -EBUSY;
+
+ /* The general idea is to power down all unused power supplies,
+ * and then mask all PCF50633 interrupt sources but EXTONR, ONKEYF
+ * and ALARM */
+
+ mutex_lock(&pcf->lock);
+
+ pcf->suspend_state = PCF50633_SS_STARTING_SUSPEND;
+
+ /* we are not going to service any further interrupts until we
+ * resume. If the IRQ workqueue is still pending in the background,
+ * it will bail when it sees we set suspend state above
+ */
+
+ disable_irq(pcf->irq);
+
+ /* set interrupt masks so only those sources we want to wake
+ * us are able to
+ */
+ for (i = 0; i < 5; i++)
+ res[i] = ~pcf->pdata->resumers[i];
+
+ ret = pcf50633_write(pcf, PCF50633_REG_INT1M, 5, &res[0]);
+ if (ret)
+ dev_err(dev, "Failed to set wake masks :-( %d\n", ret);
+
+ pcf->suspend_state = PCF50633_SS_COMPLETED_SUSPEND;
+
+ mutex_unlock(&pcf->lock);
+
+ return 0;
+}
+
+
+int pcf50633_ready(struct pcf50633_data *pcf)
+{
+ if (!pcf)
+ return -EACCES;
+
+ /* this was seen during boot with Qi, mmc_rescan racing us */
+ if (!pcf->probe_completed)
+ return -EACCES;
+
+ if ((pcf->suspend_state != PCF50633_SS_RUNNING) &&
+ (pcf->suspend_state < PCF50633_SS_COMPLETED_RESUME))
+ return -EBUSY;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50633_ready);
+
+int pcf50633_wait_for_ready(struct pcf50633_data *pcf, int timeout_ms,
+ char *name)
+{
+ /* so we always go once */
+ timeout_ms += 5;
+
+ while ((timeout_ms >= 5) && (pcf50633_ready(pcf))) {
+ timeout_ms -= 5; /* well, it isn't very accurate, but OK */
+ msleep(5);
+ }
+
+ if (timeout_ms < 5) {
+ printk(KERN_ERR"pcf50633_wait_for_ready: "
+ "%s BAILING on timeout\n", name);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50633_wait_for_ready);
+
+static int pcf50633_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct pcf50633_data *pcf = i2c_get_clientdata(client);
+ int ret;
+ u8 res[5];
+
+ dev_dbg(dev, "pcf50633_resume suspended on entry = %d\n",
+ (int)pcf->suspend_state);
+ mutex_lock(&pcf->lock);
+
+ pcf->suspend_state = PCF50633_SS_STARTING_RESUME;
+
+ memset(res, 0, sizeof(res));
+ /* not interested in second on resume */
+ res[0] = PCF50633_INT1_SECOND;
+ ret = pcf50633_write(pcf, PCF50633_REG_INT1M, 5, &res[0]);
+ if (ret)
+ dev_err(dev, "Failed to set int masks :-( %d\n", ret);
+
+ pcf->suspend_state = PCF50633_SS_COMPLETED_RESUME;
+
+ enable_irq(pcf->irq);
+
+ mutex_unlock(&pcf->lock);
+
+ /* gratuitous call to PCF work function, in the case that the PCF
+ * interrupt edge was missed during resume, this forces the pending
+ * register clear and lifts the interrupt back high again. In the
+ * case nothing is waiting for service, no harm done.
+ */
+
+ get_device(&pcf->client->dev);
+ pcf50633_work(&pcf->work);
+
+ return 0;
+}
+#else
+#define pcf50633_suspend NULL
+#define pcf50633_resume NULL
+#endif
+
+static struct i2c_device_id pcf50633_id_table[] = {
+ {"pcf50633", 0x73},
+};
+
+static struct i2c_driver pcf50633_driver = {
+ .driver = {
+ .name = "pcf50633",
+ .suspend= pcf50633_suspend,
+ .resume = pcf50633_resume,
+ },
+ .id_table = pcf50633_id_table,
+ .probe = pcf50633_probe,
+ .remove = pcf50633_remove,
+};
+
+static int __init pcf50633_init(void)
+{
+ return i2c_add_driver(&pcf50633_driver);
+}
+
+static void pcf50633_exit(void)
+{
+ i2c_del_driver(&pcf50633_driver);
+}
+
+MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 power management unit");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
+
+module_init(pcf50633_init);
+module_exit(pcf50633_exit);
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -1,4 +1,3 @@
-/* i2c-core.c - a device driver for the iic-bus interface */
/* ------------------------------------------------------------------------- */
/* Copyright (C) 1995-99 Simon G. Vogl
@@ -158,10 +157,16 @@
if (!dev->driver)
return 0;
+#if 0
driver = to_i2c_driver(dev->driver);
if (!driver->suspend)
return 0;
return driver->suspend(to_i2c_client(dev), mesg);
+#else
+ if (!dev->driver->suspend)
+ return 0;
+ return dev->driver->suspend(dev, mesg);
+#endif
}
static int i2c_device_resume(struct device * dev)
@@ -170,10 +175,16 @@
if (!dev->driver)
return 0;
+#if 0
driver = to_i2c_driver(dev->driver);
if (!driver->resume)
return 0;
return driver->resume(to_i2c_client(dev));
+#else
+ if (!dev->driver->resume)
+ return 0;
+ return dev->driver->resume(dev);
+#endif
}
static void i2c_client_release(struct device *dev)
@@ -1129,11 +1140,11 @@
int err;
/* Make sure the address is valid */
- if (addr < 0x03 || addr > 0x77) {
+ /*if (addr < 0x03 || addr > 0x77) {
dev_warn(&adapter->dev, "Invalid probe address 0x%02x\n",
addr);
return -EINVAL;
- }
+ }*/
/* Skip if already in use */
if (i2c_check_addr(adapter, addr))
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -23,7 +23,7 @@
#include <linux/input.h>
#include <linux/gpio_keys.h>
-#include <asm/gpio.h>
+#include <mach/gpio.h>
struct gpio_button_data {
struct gpio_keys_button *button;
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -323,4 +323,21 @@
To compile this driver as a module, choose M here: the
module will be called sh_keysc.
+config KEYBOARD_NEO1973
+ tristate "FIC Neo1973 buttons"
+ depends on MACH_NEO1973
+ default y
+ help
+ Say Y here to enable the buttons on the FIC Neo1973
+ GSM phone.
+
+ To compile this driver as a module, choose M here: the
+ module will be called neo1973kbd.
+
+config KEYBOARD_QT2410
+ tristate "QT2410 buttons"
+ depends on MACH_QT2410
+ default y
+
+
endif
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -14,6 +14,8 @@
obj-$(CONFIG_KEYBOARD_NEWTON) += newtonkbd.o
obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o
obj-$(CONFIG_KEYBOARD_CORGI) += corgikbd.o
+obj-$(CONFIG_KEYBOARD_NEO1973) += neo1973kbd.o
+obj-$(CONFIG_KEYBOARD_QT2410) += qt2410kbd.o
obj-$(CONFIG_KEYBOARD_SPITZ) += spitzkbd.o
obj-$(CONFIG_KEYBOARD_TOSA) += tosakbd.o
obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o
--- /dev/null
+++ b/drivers/input/keyboard/neo1973kbd.c
@@ -0,0 +1,465 @@
+/*
+ * Keyboard driver for FIC Neo1973 GSM phone
+ *
+ * (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * inspired by corkgbd.c by Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#include <mach/gpio.h>
+#include <asm/mach-types.h>
+
+extern int global_inside_suspend;
+
+struct neo1973kbd {
+ struct platform_device *pdev;
+ struct input_dev *input;
+ struct device *cdev;
+ struct work_struct work;
+ int aux_state;
+ int work_in_progress;
+ int hp_irq_count_in_work;
+ int hp_irq_count;
+ int jack_irq;
+};
+
+static struct class *neo1973kbd_switch_class;
+
+enum keys {
+ NEO1973_KEY_AUX, /* GTA01 / 02 only */
+ NEO1973_KEY_HOLD,
+ NEO1973_KEY_JACK,
+ NEO1973_KEY_PLUS, /* GTA03 only */
+ NEO1973_KEY_MINUS, /* GTA03 only */
+};
+
+struct neo1973kbd_key {
+ const char * name;
+ irqreturn_t (*isr)(int irq, void *dev_id);
+ int irq;
+ int input_key;
+};
+
+static irqreturn_t neo1973kbd_aux_irq(int irq, void *dev_id);
+static irqreturn_t neo1973kbd_headphone_irq(int irq, void *dev_id);
+static irqreturn_t neo1973kbd_default_key_irq(int irq, void *dev_id);
+
+
+static struct neo1973kbd_key keys[] = {
+ [NEO1973_KEY_AUX] = {
+ .name = "Neo1973 AUX button",
+ .isr = neo1973kbd_aux_irq,
+ .input_key = KEY_PHONE,
+ },
+ [NEO1973_KEY_HOLD] = {
+ .name = "Neo1973 HOLD button",
+ .isr = neo1973kbd_default_key_irq,
+ .input_key = KEY_PAUSE,
+ },
+ [NEO1973_KEY_JACK] = {
+ .name = "Neo1973 Headphone jack",
+ .isr = neo1973kbd_headphone_irq,
+ },
+ [NEO1973_KEY_PLUS] = {
+ .name = "GTA03 PLUS button",
+ .isr = neo1973kbd_default_key_irq,
+ .input_key = KEY_KPPLUS,
+ },
+ [NEO1973_KEY_MINUS] = {
+ .name = "GTA03 MINUS button",
+ .isr = neo1973kbd_default_key_irq,
+ .input_key = KEY_KPMINUS,
+ },
+};
+
+/* This timer section filters AUX button IRQ bouncing */
+
+static void aux_key_timer_f(unsigned long data);
+
+static struct timer_list aux_key_timer =
+ TIMER_INITIALIZER(aux_key_timer_f, 0, 0);
+
+#define AUX_TIMER_TIMEOUT (HZ >> 7)
+#define AUX_TIMER_ALLOWED_NOOP 2
+#define AUX_TIMER_CONSECUTIVE_EVENTS 5
+
+struct neo1973kbd *timer_kbd;
+
+static void aux_key_timer_f(unsigned long data)
+{
+ static int noop_counter;
+ static int last_key = -1;
+ static int last_count;
+ int key_pressed;
+
+ key_pressed =
+ !gpio_get_value(timer_kbd->pdev->resource[NEO1973_KEY_AUX].start);
+ if (machine_is_neo1973_gta02())
+ key_pressed = !key_pressed;
+
+ if (likely(key_pressed == last_key))
+ last_count++;
+ else {
+ last_count = 1;
+ last_key = key_pressed;
+ }
+
+ if (unlikely(last_count >= AUX_TIMER_CONSECUTIVE_EVENTS)) {
+ if (timer_kbd->aux_state != last_key) {
+ input_report_key(timer_kbd->input, KEY_PHONE, last_key);
+ input_sync(timer_kbd->input);
+
+ timer_kbd->aux_state = last_key;
+ noop_counter = 0;
+ }
+ last_count = 0;
+ if (unlikely(++noop_counter > AUX_TIMER_ALLOWED_NOOP)) {
+ noop_counter = 0;
+ return;
+ }
+ }
+
+ mod_timer(&aux_key_timer, jiffies + AUX_TIMER_TIMEOUT);
+}
+
+static irqreturn_t neo1973kbd_aux_irq(int irq, void *dev)
+{
+ int *p = NULL;
+
+ /* if you stall inside resume then AUX will force a panic,
+ which in turn forces a dump of the pending syslog */
+
+ if (global_inside_suspend)
+ printk(KERN_ERR "death %d\n", *p);
+
+ mod_timer(&aux_key_timer, jiffies + AUX_TIMER_TIMEOUT);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t neo1973kbd_default_key_irq(int irq, void *dev_id)
+{
+ struct neo1973kbd *kbd = dev_id;
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(keys); n++) {
+
+ if (irq != keys[n].irq)
+ continue;
+
+ input_report_key(kbd->input, keys[n].input_key,
+ gpio_get_value(kbd->pdev->resource[n].start));
+ input_sync(kbd->input);
+ }
+
+ return IRQ_HANDLED;
+}
+
+
+static const char *event_array_jack[2][4] = {
+ [0] = {
+ "SWITCH_NAME=headset",
+ "SWITCH_STATE=0",
+ "EVENT=remove",
+ NULL
+ },
+ [1] = {
+ "SWITCH_NAME=headset",
+ "SWITCH_STATE=1",
+ "EVENT=insert",
+ NULL
+ },
+};
+
+static void neo1973kbd_jack_event(struct device *dev, int num)
+{
+ kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, (char **)event_array_jack[!!num]);
+}
+
+
+static void neo1973kbd_debounce_jack(struct work_struct *work)
+{
+ struct neo1973kbd *kbd = container_of(work, struct neo1973kbd, work);
+ unsigned long flags;
+ int loop = 0;
+ int level;
+
+ do {
+ /*
+ * we wait out any multiple interrupt
+ * stuttering in 100ms lumps
+ */
+ do {
+ kbd->hp_irq_count_in_work = kbd->hp_irq_count;
+ msleep(100);
+ } while (kbd->hp_irq_count != kbd->hp_irq_count_in_work);
+ /*
+ * no new interrupts on jack for 100ms...
+ * ok we will report it
+ */
+ level = gpio_get_value(kbd->pdev->resource[NEO1973_KEY_JACK].start);
+ input_report_switch(kbd->input, SW_HEADPHONE_INSERT, level);
+ input_sync(kbd->input);
+ neo1973kbd_jack_event(kbd->cdev, level);
+ /*
+ * we go around the outer loop again if we detect that more
+ * interrupts came while we are servicing here. But we have
+ * to sequence it carefully with interrupts off
+ */
+ local_save_flags(flags);
+ /* no interrupts during this work means we can exit the work */
+ loop = !!(kbd->hp_irq_count != kbd->hp_irq_count_in_work);
+ if (!loop)
+ kbd->work_in_progress = 0;
+ local_irq_restore(flags);
+ /*
+ * interrupt that comes here will either queue a new work action
+ * since work_in_progress is cleared now, or be dealt with
+ * when we loop.
+ */
+ } while (loop);
+}
+
+
+static irqreturn_t neo1973kbd_headphone_irq(int irq, void *dev_id)
+{
+ struct neo1973kbd *neo1973kbd_data = dev_id;
+
+ /*
+ * this interrupt is prone to bouncing and userspace doesn't like
+ * to have to deal with that kind of thing. So we do not accept
+ * that a jack interrupt is equal to a jack event. Instead we fire
+ * some work on the first interrupt, and it hangs about in 100ms units
+ * until no more interrupts come. Then it accepts the state it finds
+ * for jack insert and reports it once
+ */
+
+ neo1973kbd_data->hp_irq_count++;
+ /*
+ * the first interrupt we see for a while, we fire the work item
+ * and record the interrupt count when we did that. If more interrupts
+ * come in the meanwhile, we can tell by the difference in that
+ * stored count and hp_irq_count which increments every interrupt
+ */
+ if (!neo1973kbd_data->work_in_progress) {
+ neo1973kbd_data->jack_irq = irq;
+ neo1973kbd_data->hp_irq_count_in_work =
+ neo1973kbd_data->hp_irq_count;
+ if (!schedule_work(&neo1973kbd_data->work))
+ printk(KERN_ERR
+ "Unable to schedule headphone debounce\n");
+ else
+ neo1973kbd_data->work_in_progress = 1;
+ }
+
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_PM
+static int neo1973kbd_suspend(struct platform_device *dev, pm_message_t state)
+{
+ return 0;
+}
+
+static int neo1973kbd_resume(struct platform_device *dev)
+{
+ return 0;
+}
+#else
+#define neo1973kbd_suspend NULL
+#define neo1973kbd_resume NULL
+#endif
+
+static ssize_t neo1973kbd_switch_name_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", "neo1973 Headset Jack");
+}
+
+static ssize_t neo1973kbd_switch_state_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct neo1973kbd *kbd = dev_get_drvdata(dev);
+ return sprintf(buf, "%d\n",
+ gpio_get_value(kbd->pdev->resource[NEO1973_KEY_JACK].start));
+}
+
+static DEVICE_ATTR(name, S_IRUGO , neo1973kbd_switch_name_show, NULL);
+static DEVICE_ATTR(state, S_IRUGO , neo1973kbd_switch_state_show, NULL);
+
+static int neo1973kbd_probe(struct platform_device *pdev)
+{
+ struct neo1973kbd *neo1973kbd;
+ struct input_dev *input_dev;
+ int rc;
+ int irq;
+ int n;
+
+ neo1973kbd = kzalloc(sizeof(struct neo1973kbd), GFP_KERNEL);
+ input_dev = input_allocate_device();
+ if (!neo1973kbd || !input_dev) {
+ kfree(neo1973kbd);
+ input_free_device(input_dev);
+ return -ENOMEM;
+ }
+
+ neo1973kbd->pdev = pdev;
+ timer_kbd = neo1973kbd;
+
+ if (pdev->resource[0].flags != 0)
+ return -EINVAL;
+
+ platform_set_drvdata(pdev, neo1973kbd);
+
+ neo1973kbd->input = input_dev;
+
+ INIT_WORK(&neo1973kbd->work, neo1973kbd_debounce_jack);
+
+ input_dev->name = "Neo1973 Buttons";
+ input_dev->phys = "neo1973kbd/input0";
+ input_dev->id.bustype = BUS_HOST;
+ input_dev->id.vendor = 0x0001;
+ input_dev->id.product = 0x0001;
+ input_dev->id.version = 0x0100;
+ input_dev->dev.parent = &pdev->dev;
+
+ input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_SW);
+ set_bit(SW_HEADPHONE_INSERT, input_dev->swbit);
+ set_bit(KEY_PHONE, input_dev->keybit);
+ set_bit(KEY_PAUSE, input_dev->keybit);
+
+ rc = input_register_device(neo1973kbd->input);
+ if (rc)
+ goto out_register;
+
+ neo1973kbd->cdev = device_create(neo1973kbd_switch_class,
+ &pdev->dev, 0, neo1973kbd, "headset");
+ if (unlikely(IS_ERR(neo1973kbd->cdev))) {
+ rc = PTR_ERR(neo1973kbd->cdev);
+ goto out_device_create;
+ }
+
+ rc = device_create_file(neo1973kbd->cdev, &dev_attr_name);
+ if(rc)
+ goto out_device_create_file;
+
+ rc = device_create_file(neo1973kbd->cdev, &dev_attr_state);
+ if(rc)
+ goto out_device_create_file;
+
+ /* register GPIO IRQs */
+
+ for(n = 0; n < ARRAY_SIZE(keys); n++) {
+
+ if (!pdev->resource[0].start)
+ continue;
+
+ irq = gpio_to_irq(pdev->resource[n].start);
+ if (irq < 0)
+ continue;
+
+ if (request_irq(irq, keys[n].isr, IRQF_DISABLED |
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ keys[n].name, neo1973kbd)) {
+ dev_err(&pdev->dev, "Can't get IRQ %u\n", irq);
+
+ /* unwind any irq registrations and fail */
+
+ while (n > 0) {
+ n--;
+ free_irq(gpio_to_irq(pdev->resource[n].start),
+ neo1973kbd);
+ }
+ goto out_device_create_file;
+ }
+
+ keys[n].irq = irq;
+ }
+
+ /*
+ * GTA01 revisions before Bv4 can't be resumed by the PMU, so we use
+ * resume by AUX.
+ */
+ if (machine_is_neo1973_gta01())
+ enable_irq_wake(keys[NEO1973_KEY_AUX].irq);
+
+ enable_irq_wake(keys[NEO1973_KEY_JACK].irq);
+
+ return 0;
+
+out_device_create_file:
+ device_unregister(neo1973kbd->cdev);
+out_device_create:
+ input_unregister_device(neo1973kbd->input);
+out_register:
+ input_free_device(neo1973kbd->input);
+ platform_set_drvdata(pdev, NULL);
+ kfree(neo1973kbd);
+
+ return -ENODEV;
+}
+
+static int neo1973kbd_remove(struct platform_device *pdev)
+{
+ struct neo1973kbd *neo1973kbd = platform_get_drvdata(pdev);
+
+ free_irq(gpio_to_irq(pdev->resource[2].start), neo1973kbd);
+ free_irq(gpio_to_irq(pdev->resource[1].start), neo1973kbd);
+ free_irq(gpio_to_irq(pdev->resource[0].start), neo1973kbd);
+
+ device_unregister(neo1973kbd->cdev);
+ input_unregister_device(neo1973kbd->input);
+ input_free_device(neo1973kbd->input);
+ platform_set_drvdata(pdev, NULL);
+ kfree(neo1973kbd);
+
+ return 0;
+}
+
+static struct platform_driver neo1973kbd_driver = {
+ .probe = neo1973kbd_probe,
+ .remove = neo1973kbd_remove,
+ .suspend = neo1973kbd_suspend,
+ .resume = neo1973kbd_resume,
+ .driver = {
+ .name = "neo1973-button",
+ },
+};
+
+static int __devinit neo1973kbd_init(void)
+{
+ neo1973kbd_switch_class = class_create(THIS_MODULE, "switch");
+ if (IS_ERR(neo1973kbd_switch_class))
+ return PTR_ERR(neo1973kbd_switch_class);
+ return platform_driver_register(&neo1973kbd_driver);
+}
+
+static void __exit neo1973kbd_exit(void)
+{
+ platform_driver_unregister(&neo1973kbd_driver);
+ class_destroy(neo1973kbd_switch_class);
+}
+
+module_init(neo1973kbd_init);
+module_exit(neo1973kbd_exit);
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("FIC Neo1973 buttons input driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/input/keyboard/qt2410kbd.c
@@ -0,0 +1,231 @@
+/*
+ * Keyboard driver for Armzone QT2410
+ *
+ * (C) 2006 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include <mach/hardware.h>
+#include <mach/gta01.h>
+
+struct gta01kbd {
+ struct input_dev *input;
+ unsigned int suspended;
+ unsigned long suspend_jiffies;
+};
+
+static irqreturn_t gta01kbd_interrupt(int irq, void *dev_id)
+{
+ struct gta01kbd *gta01kbd_data = dev_id;
+
+ /* FIXME: use GPIO from platform_dev resources */
+ if (s3c2410_gpio_getpin(S3C2410_GPF0))
+ input_report_key(gta01kbd_data->input, KEY_PHONE, 1);
+ else
+ input_report_key(gta01kbd_data->input, KEY_PHONE, 0);
+
+ input_sync(gta01kbd_data->input);
+
+ return IRQ_HANDLED;
+}
+
+
+#ifdef CONFIG_PM
+static int gta01kbd_suspend(struct platform_device *dev, pm_message_t state)
+{
+ struct gta01kbd *gta01kbd = platform_get_drvdata(dev);
+
+ gta01kbd->suspended = 1;
+
+ return 0;
+}
+
+static int gta01kbd_resume(struct platform_device *dev)
+{
+ struct gta01kbd *gta01kbd = platform_get_drvdata(dev);
+
+ gta01kbd->suspended = 0;
+
+ return 0;
+}
+#else
+#define gta01kbd_suspend NULL
+#define gta01kbd_resume NULL
+#endif
+
+static int gta01kbd_probe(struct platform_device *pdev)
+{
+ struct gta01kbd *gta01kbd;
+ struct input_dev *input_dev;
+ int irq_911;
+ int rc = 0;
+
+ gta01kbd = kzalloc(sizeof(struct gta01kbd), GFP_KERNEL);
+ if (!gta01kbd) {
+ rc = -ENOMEM;
+ goto bail;
+ }
+ input_dev = input_allocate_device();
+ if (!gta01kbd || !input_dev) {
+ rc = -ENOMEM;
+ goto bail_free;
+ }
+
+ if (pdev->resource[0].flags != 0) {\
+ rc = -EINVAL;
+ goto bail_free_dev;
+ }
+
+ irq_911 = s3c2410_gpio_getirq(pdev->resource[0].start);
+ if (irq_911 < 0) {
+ rc = -EINVAL;
+ goto bail_free_dev;
+ }
+
+ platform_set_drvdata(pdev, gta01kbd);
+
+ gta01kbd->input = input_dev;
+
+#if 0
+ spin_lock_init(&gta01kbd->lock);
+ /* Init Keyboard rescan timer */
+ init_timer(&corgikbd->timer);
+ corgikbd->timer.function = corgikbd_timer_callback;
+ corgikbd->timer.data = (unsigned long) corgikbd;
+
+ /* Init Hinge Timer */
+ init_timer(&corgikbd->htimer);
+ corgikbd->htimer.function = corgikbd_hinge_timer;
+ corgikbd->htimer.data = (unsigned long) corgikbd;
+
+ corgikbd->suspend_jiffies=jiffies;
+
+ memcpy(corgikbd->keycode, corgikbd_keycode, sizeof(corgikbd->keycode));
+#endif
+
+ input_dev->name = "QT2410 Buttons";
+ input_dev->phys = "qt2410kbd/input0";
+ input_dev->id.bustype = BUS_HOST;
+ input_dev->id.vendor = 0x0001;
+ input_dev->id.product = 0x0001;
+ input_dev->id.version = 0x0100;
+
+ input_dev->evbit[0] = BIT(EV_KEY);
+#if 0
+ input_dev->keycode = gta01kbd->keycode;
+ input_dev->keycodesize = sizeof(unsigned char);
+ input_dev->keycodemax = ARRAY_SIZE(corgikbd_keycode);
+
+ for (i = 0; i < ARRAY_SIZE(corgikbd_keycode); i++)
+ set_bit(corgikbd->keycode[i], input_dev->keybit);
+ clear_bit(0, input_dev->keybit);
+ set_bit(SW_LID, input_dev->swbit);
+ set_bit(SW_TABLET_MODE, input_dev->swbit);
+ set_bit(SW_HEADPHONE_INSERT, input_dev->swbit);
+#endif
+
+ rc = input_register_device(gta01kbd->input);
+ if (rc)
+ goto bail_free_dev;
+
+ s3c2410_gpio_cfgpin(S3C2410_GPF0, S3C2410_GPF0_EINT0);
+ if (request_irq(irq_911, gta01kbd_interrupt,
+ IRQF_DISABLED | IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING, "qt2410kbd_eint0", gta01kbd))
+ printk(KERN_WARNING "gta01kbd: Can't get IRQ\n");
+ enable_irq_wake(irq_911);
+
+ /* FIXME: headphone insert */
+
+#if 0
+ mod_timer(&corgikbd->htimer, jiffies + msecs_to_jiffies(HINGE_SCAN_INTERVAL));
+
+ /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */
+ for (i = 0; i < CORGI_KEY_SENSE_NUM; i++) {
+ pxa_gpio_mode(CORGI_GPIO_KEY_SENSE(i) | GPIO_IN);
+ if (request_irq(CORGI_IRQ_GPIO_KEY_SENSE(i), corgikbd_interrupt,
+ SA_INTERRUPT | SA_TRIGGER_RISING,
+ "corgikbd", corgikbd))
+ printk(KERN_WARNING "corgikbd: Can't get IRQ: %d!\n", i);
+ }
+
+ /* Set Strobe lines as outputs - set high */
+ for (i = 0; i < CORGI_KEY_STROBE_NUM; i++)
+ pxa_gpio_mode(CORGI_GPIO_KEY_STROBE(i) | GPIO_OUT | GPIO_DFLT_HIGH);
+
+ /* Setup the headphone jack as an input */
+ pxa_gpio_mode(CORGI_GPIO_AK_INT | GPIO_IN);
+#endif
+
+ return 0;
+
+bail_free_dev:
+ input_free_device(input_dev);
+bail_free:
+ kfree(gta01kbd);
+bail:
+ return rc;
+}
+
+static int gta01kbd_remove(struct platform_device *pdev)
+{
+ struct gta01kbd *gta01kbd = platform_get_drvdata(pdev);
+
+ free_irq(s3c2410_gpio_getirq(pdev->resource[0].start), gta01kbd);
+#if 0
+ int i;
+
+ for (i = 0; i < CORGI_KEY_SENSE_NUM; i++)
+ free_irq(CORGI_IRQ_GPIO_KEY_SENSE(i), corgikbd);
+
+ del_timer_sync(&corgikbd->htimer);
+ del_timer_sync(&corgikbd->timer);
+#endif
+ input_unregister_device(gta01kbd->input);
+
+ kfree(gta01kbd);
+
+ return 0;
+}
+
+static struct platform_driver gta01kbd_driver = {
+ .probe = gta01kbd_probe,
+ .remove = gta01kbd_remove,
+ .suspend = gta01kbd_suspend,
+ .resume = gta01kbd_resume,
+ .driver = {
+ .name = "qt2410-button",
+ },
+};
+
+static int __devinit gta01kbd_init(void)
+{
+ return platform_driver_register(&gta01kbd_driver);
+}
+
+static void __exit gta01kbd_exit(void)
+{
+ platform_driver_unregister(&gta01kbd_driver);
+}
+
+module_init(gta01kbd_init);
+module_exit(gta01kbd_exit);
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("Armzone QT2410 Buttons Driver");
+MODULE_LICENSE("GPL");
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -236,4 +236,25 @@
To compile this driver as a module, choose M here: the
module will be called gpio-buttons.
+config INPUT_LIS302DL
+ tristate "STmicro LIS302DL 3-axis accelerometer"
+ depends on SPI_MASTER
+ help
+ SPI driver for the STmicro LIS302DL 3-axis accelerometer.
+
+ The userspece interface is a 3-axis (X/Y/Z) relative movement
+ Linux input device, reporting REL_[XYZ] events.
+
+config INPUT_PCF50633_PMU
+ tristate "PCF50633 PMU events"
+ depends on MFD_PCF50633
+ help
+ Say Y to include support for input events on NXP PCF50633.
+
+config INPUT_PCF50606_PMU
+ tristate "PCF50606 PMU events"
+ depends on MFD_PCF50606
+ help
+ Say Y to include support for input events on NXP PCF50606.
+
endif
--- /dev/null
+++ b/drivers/input/misc/lis302dl.c
@@ -0,0 +1,874 @@
+/* Linux kernel driver for the ST LIS302D 3-axis accelerometer
+ *
+ * Copyright (C) 2007-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * converted to private bitbang by:
+ * Andy Green <andy@openmoko.com>
+ * ability to set acceleration threshold added by:
+ * Simon Kagstrom <simon.kagstrom@gmail.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * TODO
+ * * statistics for overflow events
+ * * configuration interface (sysfs) for
+ * * enable/disable x/y/z axis data ready
+ * * enable/disable resume from freee fall / click
+ * * free fall / click parameters
+ * * high pass filter parameters
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/sysfs.h>
+
+#include <linux/lis302dl.h>
+
+/* Utility functions */
+static u8 __reg_read(struct lis302dl_info *lis, u8 reg)
+{
+ return (lis->pdata->lis302dl_bitbang_reg_read)(lis, reg);
+}
+
+static void __reg_write(struct lis302dl_info *lis, u8 reg, u8 val)
+{
+ (lis->pdata->lis302dl_bitbang_reg_write)(lis, reg, val);
+}
+
+static void __reg_set_bit_mask(struct lis302dl_info *lis, u8 reg, u8 mask,
+ u8 val)
+{
+ u_int8_t tmp;
+
+ val &= mask;
+
+ tmp = __reg_read(lis, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ __reg_write(lis, reg, tmp);
+}
+
+static int __ms_to_duration(struct lis302dl_info *lis, int ms)
+{
+ /* If we have 400 ms sampling rate, the stepping is 2.5 ms,
+ * on 100 ms the stepping is 10ms */
+ if (lis->flags & LIS302DL_F_DR)
+ return min((ms * 10) / 25, 637);
+
+ return min(ms / 10, 2550);
+}
+
+static int __duration_to_ms(struct lis302dl_info *lis, int duration)
+{
+ if (lis->flags & LIS302DL_F_DR)
+ return (duration * 25) / 10;
+
+ return duration * 10;
+}
+
+static u8 __mg_to_threshold(struct lis302dl_info *lis, int mg)
+{
+ /* If FS is set each bit is 71mg, otherwise 18mg. The THS register
+ * has 7 bits for the threshold value */
+ if (lis->flags & LIS302DL_F_FS)
+ return min(mg / 71, 127);
+
+ return min(mg / 18, 127);
+}
+
+static int __threshold_to_mg(struct lis302dl_info *lis, u8 threshold)
+{
+ if (lis->flags & LIS302DL_F_FS)
+ return threshold * 71;
+
+ return threshold * 18;
+}
+
+/* interrupt handling related */
+
+enum lis302dl_intmode {
+ LIS302DL_INTMODE_GND = 0x00,
+ LIS302DL_INTMODE_FF_WU_1 = 0x01,
+ LIS302DL_INTMODE_FF_WU_2 = 0x02,
+ LIS302DL_INTMODE_FF_WU_12 = 0x03,
+ LIS302DL_INTMODE_DATA_READY = 0x04,
+ LIS302DL_INTMODE_CLICK = 0x07,
+};
+
+static void __lis302dl_int_mode(struct device *dev, int int_pin,
+ enum lis302dl_intmode mode)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+
+ switch (int_pin) {
+ case 1:
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL3, 0x07, mode);
+ break;
+ case 2:
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL3, 0x38, mode << 3);
+ break;
+ default:
+ BUG();
+ }
+}
+
+static void __enable_wakeup(struct lis302dl_info *lis)
+{
+ __reg_write(lis, LIS302DL_REG_CTRL1, 0);
+
+ /* First zero to get to a known state */
+ __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1, LIS302DL_FFWUCFG_XHIE |
+ LIS302DL_FFWUCFG_YHIE | LIS302DL_FFWUCFG_ZHIE |
+ LIS302DL_FFWUCFG_LIR);
+ __reg_write(lis, LIS302DL_REG_FF_WU_THS_1,
+ __mg_to_threshold(lis, lis->wakeup.threshold));
+ __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
+ __ms_to_duration(lis, lis->wakeup.duration));
+
+ /* Route the interrupt for wakeup */
+ __lis302dl_int_mode(lis->dev, 1,
+ LIS302DL_INTMODE_FF_WU_1);
+
+ __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
+ __reg_read(lis, LIS302DL_REG_OUT_X);
+ __reg_read(lis, LIS302DL_REG_OUT_Y);
+ __reg_read(lis, LIS302DL_REG_OUT_Z);
+ __reg_read(lis, LIS302DL_REG_STATUS);
+ __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
+ __reg_read(lis, LIS302DL_REG_FF_WU_SRC_2);
+ __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD | 7);
+}
+
+static void __enable_data_collection(struct lis302dl_info *lis)
+{
+ u_int8_t ctrl1 = LIS302DL_CTRL1_PD | LIS302DL_CTRL1_Xen |
+ LIS302DL_CTRL1_Yen | LIS302DL_CTRL1_Zen;
+
+ /* make sure we're powered up and generate data ready */
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, ctrl1, ctrl1);
+
+ /* If the threshold is zero, let the device generated an interrupt
+ * on each datum */
+ if (lis->threshold == 0) {
+ __reg_write(lis, LIS302DL_REG_CTRL2, 0);
+ __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_DATA_READY);
+ __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_DATA_READY);
+ } else {
+ __reg_write(lis, LIS302DL_REG_CTRL2,
+ LIS302DL_CTRL2_HPFF1);
+ __reg_write(lis, LIS302DL_REG_FF_WU_THS_1,
+ __mg_to_threshold(lis, lis->threshold));
+ __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
+ __ms_to_duration(lis, lis->duration));
+
+ /* Clear the HP filter "starting point" */
+ __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
+ __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1,
+ LIS302DL_FFWUCFG_XHIE | LIS302DL_FFWUCFG_YHIE |
+ LIS302DL_FFWUCFG_ZHIE | LIS302DL_FFWUCFG_LIR);
+ __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_FF_WU_12);
+ __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_FF_WU_12);
+ }
+}
+
+#if 0
+static void _report_btn_single(struct input_dev *inp, int btn)
+{
+ input_report_key(inp, btn, 1);
+ input_sync(inp);
+ input_report_key(inp, btn, 0);
+}
+
+static void _report_btn_double(struct input_dev *inp, int btn)
+{
+ input_report_key(inp, btn, 1);
+ input_sync(inp);
+ input_report_key(inp, btn, 0);
+ input_sync(inp);
+ input_report_key(inp, btn, 1);
+ input_sync(inp);
+ input_report_key(inp, btn, 0);
+}
+#endif
+
+
+static void lis302dl_bitbang_read_sample(struct lis302dl_info *lis)
+{
+ u8 data = 0xc0 | LIS302DL_REG_OUT_X; /* read, autoincrement */
+ u8 read[5];
+ unsigned long flags;
+ int mg_per_sample;
+
+ local_irq_save(flags);
+ mg_per_sample = __threshold_to_mg(lis, 1);
+
+ (lis->pdata->lis302dl_bitbang)(lis, &data, 1, &read[0], 5);
+
+ local_irq_restore(flags);
+
+ input_report_rel(lis->input_dev, REL_X, mg_per_sample * (s8)read[0]);
+ input_report_rel(lis->input_dev, REL_Y, mg_per_sample * (s8)read[2]);
+ input_report_rel(lis->input_dev, REL_Z, mg_per_sample * (s8)read[4]);
+
+ input_sync(lis->input_dev);
+
+ /* Reset the HP filter */
+ __reg_read(lis, LIS302DL_REG_HP_FILTER_RESET);
+ __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
+}
+
+static irqreturn_t lis302dl_interrupt(int irq, void *_lis)
+{
+ struct lis302dl_info *lis = _lis;
+
+ lis302dl_bitbang_read_sample(lis);
+ return IRQ_HANDLED;
+}
+
+/* sysfs */
+
+static ssize_t show_rate(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ u8 ctrl1;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ ctrl1 = __reg_read(lis, LIS302DL_REG_CTRL1);
+ local_irq_restore(flags);
+
+ return sprintf(buf, "%d\n", ctrl1 & LIS302DL_CTRL1_DR ? 400 : 100);
+}
+
+static ssize_t set_rate(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ if (!strcmp(buf, "400\n")) {
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_DR,
+ LIS302DL_CTRL1_DR);
+ lis->flags |= LIS302DL_F_DR;
+ } else {
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_DR,
+ 0);
+ lis->flags &= ~LIS302DL_F_DR;
+ }
+ local_irq_restore(flags);
+
+ return count;
+}
+
+static DEVICE_ATTR(sample_rate, S_IRUGO | S_IWUSR, show_rate, set_rate);
+
+static ssize_t show_scale(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ u_int8_t ctrl1;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ ctrl1 = __reg_read(lis, LIS302DL_REG_CTRL1);
+ local_irq_restore(flags);
+
+ return sprintf(buf, "%s\n", ctrl1 & LIS302DL_CTRL1_FS ? "9.2" : "2.3");
+}
+
+static ssize_t set_scale(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ if (!strcmp(buf, "9.2\n")) {
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_FS,
+ LIS302DL_CTRL1_FS);
+ lis->flags |= LIS302DL_F_FS;
+ } else {
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_FS,
+ 0);
+ lis->flags &= ~LIS302DL_F_FS;
+ }
+
+ if (lis->flags & LIS302DL_F_INPUT_OPEN)
+ __enable_data_collection(lis);
+
+ local_irq_restore(flags);
+
+ return count;
+}
+
+static DEVICE_ATTR(full_scale, S_IRUGO | S_IWUSR, show_scale, set_scale);
+
+static ssize_t show_threshold(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+
+ /* Display the device view of the threshold setting */
+ return sprintf(buf, "%d\n", __threshold_to_mg(lis,
+ __mg_to_threshold(lis, lis->threshold)));
+}
+
+static ssize_t set_threshold(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ /* 8g is the maximum if FS is 1 */
+ if (val > 8000)
+ return -ERANGE;
+
+ /* Set the threshold and write it out if the device is used */
+ lis->threshold = val;
+
+ if (lis->flags & LIS302DL_F_INPUT_OPEN) {
+ unsigned long flags;
+
+ local_irq_save(flags);
+ __enable_data_collection(lis);
+ local_irq_restore(flags);
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR(threshold, S_IRUGO | S_IWUSR, show_threshold, set_threshold);
+
+static ssize_t show_duration(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+
+ return sprintf(buf, "%d\n", __duration_to_ms(lis,
+ __ms_to_duration(lis, lis->duration)));
+}
+
+static ssize_t set_duration(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ unsigned int val;
+
+ if (sscanf(buf, "%u\n", &val) != 1)
+ return -EINVAL;
+ if (val > 2550)
+ return -ERANGE;
+
+ lis->duration = val;
+ if (lis->flags & LIS302DL_F_INPUT_OPEN)
+ __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1,
+ __ms_to_duration(lis, lis->duration));
+
+ return count;
+}
+
+static DEVICE_ATTR(duration, S_IRUGO | S_IWUSR, show_duration, set_duration);
+
+static ssize_t lis302dl_dump(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ int n = 0;
+ u8 reg[0x40];
+ char *end = buf;
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ for (n = 0; n < sizeof(reg); n++)
+ reg[n] = __reg_read(lis, n);
+
+ local_irq_restore(flags);
+
+ for (n = 0; n < sizeof(reg); n += 16) {
+ hex_dump_to_buffer(reg + n, 16, 16, 1, end, 128, 0);
+ end += strlen(end);
+ *end++ = '\n';
+ *end++ = '\0';
+ }
+
+ return end - buf;
+}
+static DEVICE_ATTR(dump, S_IRUGO, lis302dl_dump, NULL);
+
+/* Configure freefall/wakeup interrupts */
+static ssize_t set_wakeup_threshold(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ unsigned int threshold;
+
+ if (sscanf(buf, "%u\n", &threshold) != 1)
+ return -EINVAL;
+
+ if (threshold > 8000)
+ return -ERANGE;
+
+ /* Zero turns the feature off */
+ if (threshold == 0) {
+ if (lis->flags & LIS302DL_F_IRQ_WAKE) {
+ disable_irq_wake(lis->pdata->interrupt);
+ lis->flags &= ~LIS302DL_F_IRQ_WAKE;
+ }
+
+ return count;
+ }
+
+ lis->wakeup.threshold = threshold;
+
+ if (!(lis->flags & LIS302DL_F_IRQ_WAKE)) {
+ enable_irq_wake(lis->pdata->interrupt);
+ lis->flags |= LIS302DL_F_IRQ_WAKE;
+ }
+
+ return count;
+}
+
+static ssize_t show_wakeup_threshold(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+
+ /* All events off? */
+ if (lis->wakeup.threshold == 0)
+ return sprintf(buf, "off\n");
+
+ return sprintf(buf, "%u\n", lis->wakeup.threshold);
+}
+
+static DEVICE_ATTR(wakeup_threshold, S_IRUGO | S_IWUSR, show_wakeup_threshold,
+ set_wakeup_threshold);
+
+static ssize_t set_wakeup_duration(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+ unsigned int duration;
+
+ if (sscanf(buf, "%u\n", &duration) != 1)
+ return -EINVAL;
+
+ if (duration > 2550)
+ return -ERANGE;
+
+ lis->wakeup.duration = duration;
+
+ return count;
+}
+
+static ssize_t show_wakeup_duration(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(dev);
+
+ return sprintf(buf, "%u\n", lis->wakeup.duration);
+}
+
+static DEVICE_ATTR(wakeup_duration, S_IRUGO | S_IWUSR, show_wakeup_duration,
+ set_wakeup_duration);
+
+static struct attribute *lis302dl_sysfs_entries[] = {
+ &dev_attr_sample_rate.attr,
+ &dev_attr_full_scale.attr,
+ &dev_attr_threshold.attr,
+ &dev_attr_duration.attr,
+ &dev_attr_dump.attr,
+ &dev_attr_wakeup_threshold.attr,
+ &dev_attr_wakeup_duration.attr,
+ NULL
+};
+
+static struct attribute_group lis302dl_attr_group = {
+ .name = NULL,
+ .attrs = lis302dl_sysfs_entries,
+};
+
+/* input device handling and driver core interaction */
+
+static int lis302dl_input_open(struct input_dev *inp)
+{
+ struct lis302dl_info *lis = input_get_drvdata(inp);
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ __enable_data_collection(lis);
+ lis->flags |= LIS302DL_F_INPUT_OPEN;
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static void lis302dl_input_close(struct input_dev *inp)
+{
+ struct lis302dl_info *lis = input_get_drvdata(inp);
+ u_int8_t ctrl1 = LIS302DL_CTRL1_Xen | LIS302DL_CTRL1_Yen |
+ LIS302DL_CTRL1_Zen;
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ /* since the input core already serializes access and makes sure we
+ * only see close() for the close of the last user, we can safely
+ * disable the data ready events */
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, ctrl1, 0x00);
+ lis->flags &= ~LIS302DL_F_INPUT_OPEN;
+
+ /* however, don't power down the whole device if still needed */
+ if (!(lis->flags & LIS302DL_F_WUP_FF ||
+ lis->flags & LIS302DL_F_WUP_CLICK)) {
+ __reg_set_bit_mask(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD,
+ 0x00);
+ }
+ local_irq_restore(flags);
+}
+
+/* get the device to reload its coefficients from EEPROM and wait for it
+ * to complete
+ */
+
+static int __lis302dl_reset_device(struct lis302dl_info *lis)
+{
+ int timeout = 10;
+
+ __reg_write(lis, LIS302DL_REG_CTRL2,
+ LIS302DL_CTRL2_BOOT | LIS302DL_CTRL2_FDS);
+
+ while ((__reg_read(lis, LIS302DL_REG_CTRL2)
+ & LIS302DL_CTRL2_BOOT) && (timeout--))
+ mdelay(1);
+
+ return !!(timeout < 0);
+}
+
+static int __devinit lis302dl_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct lis302dl_info *lis;
+ u_int8_t wai;
+ unsigned long flags;
+ struct lis302dl_platform_data *pdata = pdev->dev.platform_data;
+
+ lis = kzalloc(sizeof(*lis), GFP_KERNEL);
+ if (!lis)
+ return -ENOMEM;
+
+ lis->dev = &pdev->dev;
+
+ dev_set_drvdata(lis->dev, lis);
+
+ lis->pdata = pdata;
+
+ rc = sysfs_create_group(&lis->dev->kobj, &lis302dl_attr_group);
+ if (rc) {
+ dev_err(lis->dev, "error creating sysfs group\n");
+ goto bail_free_lis;
+ }
+
+ /* initialize input layer details */
+ lis->input_dev = input_allocate_device();
+ if (!lis->input_dev) {
+ dev_err(lis->dev, "Unable to allocate input device\n");
+ goto bail_sysfs;
+ }
+
+ input_set_drvdata(lis->input_dev, lis);
+ lis->input_dev->name = pdata->name;
+ /* SPI Bus not defined as a valid bus for input subsystem*/
+ lis->input_dev->id.bustype = BUS_I2C; /* lie about it */
+ lis->input_dev->open = lis302dl_input_open;
+ lis->input_dev->close = lis302dl_input_close;
+
+ rc = input_register_device(lis->input_dev);
+ if (rc) {
+ dev_err(lis->dev, "error %d registering input device\n", rc);
+ goto bail_inp_dev;
+ }
+
+ local_irq_save(flags);
+ /* Configure our IO */
+ (lis->pdata->lis302dl_suspend_io)(lis, 1);
+
+ wai = __reg_read(lis, LIS302DL_REG_WHO_AM_I);
+ if (wai != LIS302DL_WHO_AM_I_MAGIC) {
+ dev_err(lis->dev, "unknown who_am_i signature 0x%02x\n", wai);
+ dev_set_drvdata(lis->dev, NULL);
+ rc = -ENODEV;
+ local_irq_restore(flags);
+ goto bail_inp_reg;
+ }
+
+ set_bit(EV_REL, lis->input_dev->evbit);
+ set_bit(REL_X, lis->input_dev->relbit);
+ set_bit(REL_Y, lis->input_dev->relbit);
+ set_bit(REL_Z, lis->input_dev->relbit);
+/* set_bit(EV_KEY, lis->input_dev->evbit);
+ set_bit(BTN_X, lis->input_dev->keybit);
+ set_bit(BTN_Y, lis->input_dev->keybit);
+ set_bit(BTN_Z, lis->input_dev->keybit);
+*/
+ lis->threshold = 0;
+ lis->duration = 0;
+ memset(&lis->wakeup, 0, sizeof(lis->wakeup));
+
+ if (__lis302dl_reset_device(lis))
+ dev_err(lis->dev, "device BOOT reload failed\n");
+
+ /* force us powered */
+ __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_PD |
+ LIS302DL_CTRL1_Xen |
+ LIS302DL_CTRL1_Yen |
+ LIS302DL_CTRL1_Zen);
+ mdelay(1);
+
+ __reg_write(lis, LIS302DL_REG_CTRL2, 0);
+ __reg_write(lis, LIS302DL_REG_CTRL3,
+ LIS302DL_CTRL3_PP_OD | LIS302DL_CTRL3_IHL);
+ __reg_write(lis, LIS302DL_REG_FF_WU_THS_1, 0x0);
+ __reg_write(lis, LIS302DL_REG_FF_WU_DURATION_1, 0x00);
+ __reg_write(lis, LIS302DL_REG_FF_WU_CFG_1, 0x0);
+
+ /* start off in powered down mode; we power up when someone opens us */
+ __reg_write(lis, LIS302DL_REG_CTRL1, LIS302DL_CTRL1_Xen |
+ LIS302DL_CTRL1_Yen | LIS302DL_CTRL1_Zen);
+
+ if (pdata->open_drain)
+ /* switch interrupt to open collector, active-low */
+ __reg_write(lis, LIS302DL_REG_CTRL3,
+ LIS302DL_CTRL3_PP_OD | LIS302DL_CTRL3_IHL);
+ else
+ /* push-pull, active-low */
+ __reg_write(lis, LIS302DL_REG_CTRL3, LIS302DL_CTRL3_IHL);
+
+ __lis302dl_int_mode(lis->dev, 1, LIS302DL_INTMODE_GND);
+ __lis302dl_int_mode(lis->dev, 2, LIS302DL_INTMODE_GND);
+
+ __reg_read(lis, LIS302DL_REG_STATUS);
+ __reg_read(lis, LIS302DL_REG_FF_WU_SRC_1);
+ __reg_read(lis, LIS302DL_REG_FF_WU_SRC_2);
+ __reg_read(lis, LIS302DL_REG_CLICK_SRC);
+ local_irq_restore(flags);
+
+ dev_info(lis->dev, "Found %s\n", pdata->name);
+
+ lis->pdata = pdata;
+
+ set_irq_handler(lis->pdata->interrupt, handle_level_irq);
+
+ rc = request_irq(lis->pdata->interrupt, lis302dl_interrupt,
+ IRQF_TRIGGER_LOW, "lis302dl", lis);
+
+ if (rc < 0) {
+ dev_err(lis->dev, "error requesting IRQ %d\n",
+ lis->pdata->interrupt);
+ goto bail_inp_reg;
+ }
+ return 0;
+
+bail_inp_reg:
+ input_unregister_device(lis->input_dev);
+bail_inp_dev:
+ input_free_device(lis->input_dev);
+bail_sysfs:
+ sysfs_remove_group(&lis->dev->kobj, &lis302dl_attr_group);
+bail_free_lis:
+ kfree(lis);
+ return rc;
+}
+
+static int __devexit lis302dl_remove(struct platform_device *pdev)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
+ unsigned long flags;
+
+ /* Disable interrupts */
+ if (lis->flags & LIS302DL_F_IRQ_WAKE)
+ disable_irq_wake(lis->pdata->interrupt);
+ free_irq(lis->pdata->interrupt, lis);
+
+ /* Reset and power down the device */
+ local_irq_save(flags);
+ __reg_write(lis, LIS302DL_REG_CTRL3, 0x00);
+ __reg_write(lis, LIS302DL_REG_CTRL2, 0x00);
+ __reg_write(lis, LIS302DL_REG_CTRL1, 0x00);
+ local_irq_restore(flags);
+
+ /* Cleanup resources */
+ sysfs_remove_group(&pdev->dev.kobj, &lis302dl_attr_group);
+ input_unregister_device(lis->input_dev);
+ if (lis->input_dev)
+ input_free_device(lis->input_dev);
+ dev_set_drvdata(lis->dev, NULL);
+ kfree(lis);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static u8 regs_to_save[] = {
+ LIS302DL_REG_CTRL1,
+ LIS302DL_REG_CTRL2,
+ LIS302DL_REG_CTRL3,
+ LIS302DL_REG_FF_WU_CFG_1,
+ LIS302DL_REG_FF_WU_THS_1,
+ LIS302DL_REG_FF_WU_DURATION_1,
+ LIS302DL_REG_FF_WU_CFG_2,
+ LIS302DL_REG_FF_WU_THS_2,
+ LIS302DL_REG_FF_WU_DURATION_2,
+ LIS302DL_REG_CLICK_CFG,
+ LIS302DL_REG_CLICK_THSY_X,
+ LIS302DL_REG_CLICK_THSZ,
+ LIS302DL_REG_CLICK_TIME_LIMIT,
+ LIS302DL_REG_CLICK_LATENCY,
+ LIS302DL_REG_CLICK_WINDOW,
+
+};
+
+static int lis302dl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
+ unsigned long flags;
+ u_int8_t tmp;
+ int n;
+
+ /* determine if we want to wake up from the accel. */
+ if (lis->flags & LIS302DL_F_WUP_CLICK)
+ return 0;
+
+ disable_irq(lis->pdata->interrupt);
+ local_irq_save(flags);
+
+ /*
+ * When we share SPI over multiple sensors, there is a race here
+ * that one or more sensors will lose. In that case, the shared
+ * SPI bus GPIO will be in sleep mode and partially pulled down. So
+ * we explicitly put our IO into "wake" mode here before the final
+ * traffic to the sensor.
+ */
+ (lis->pdata->lis302dl_suspend_io)(lis, 1);
+
+ /* save registers */
+ for (n = 0; n < ARRAY_SIZE(regs_to_save); n++)
+ lis->regs[regs_to_save[n]] =
+ __reg_read(lis, regs_to_save[n]);
+
+ /* power down or enable wakeup */
+
+ if (lis->wakeup.threshold == 0) {
+ tmp = __reg_read(lis, LIS302DL_REG_CTRL1);
+ tmp &= ~LIS302DL_CTRL1_PD;
+ __reg_write(lis, LIS302DL_REG_CTRL1, tmp);
+ } else
+ __enable_wakeup(lis);
+
+ /* place our IO to the device in sleep-compatible states */
+ (lis->pdata->lis302dl_suspend_io)(lis, 0);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int lis302dl_resume(struct platform_device *pdev)
+{
+ struct lis302dl_info *lis = dev_get_drvdata(&pdev->dev);
+ unsigned long flags;
+ int n;
+
+ if (lis->flags & LIS302DL_F_WUP_CLICK)
+ return 0;
+
+ local_irq_save(flags);
+
+ /* get our IO to the device back in operational states */
+ (lis->pdata->lis302dl_suspend_io)(lis, 1);
+
+ /* resume from powerdown first! */
+ __reg_write(lis, LIS302DL_REG_CTRL1,
+ LIS302DL_CTRL1_PD |
+ LIS302DL_CTRL1_Xen |
+ LIS302DL_CTRL1_Yen |
+ LIS302DL_CTRL1_Zen);
+ mdelay(1);
+
+ if (__lis302dl_reset_device(lis))
+ dev_err(&pdev->dev, "device BOOT reload failed\n");
+
+ lis->regs[LIS302DL_REG_CTRL1] |= LIS302DL_CTRL1_PD |
+ LIS302DL_CTRL1_Xen |
+ LIS302DL_CTRL1_Yen |
+ LIS302DL_CTRL1_Zen;
+
+ /* restore registers after resume */
+ for (n = 0; n < ARRAY_SIZE(regs_to_save); n++)
+ __reg_write(lis, regs_to_save[n], lis->regs[regs_to_save[n]]);
+
+ local_irq_restore(flags);
+ enable_irq(lis->pdata->interrupt);
+
+ return 0;
+}
+#else
+#define lis302dl_suspend NULL
+#define lis302dl_resume NULL
+#endif
+
+static struct platform_driver lis302dl_driver = {
+ .driver = {
+ .name = "lis302dl",
+ .owner = THIS_MODULE,
+ },
+
+ .probe = lis302dl_probe,
+ .remove = __devexit_p(lis302dl_remove),
+ .suspend = lis302dl_suspend,
+ .resume = lis302dl_resume,
+};
+
+static int __devinit lis302dl_init(void)
+{
+ return platform_driver_register(&lis302dl_driver);
+}
+
+static void __exit lis302dl_exit(void)
+{
+ platform_driver_unregister(&lis302dl_driver);
+}
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
+
+module_init(lis302dl_init);
+module_exit(lis302dl_exit);
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -22,3 +22,6 @@
obj-$(CONFIG_INPUT_APANEL) += apanel.o
obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o
obj-$(CONFIG_INPUT_GPIO_BUTTONS) += gpio_buttons.o
+obj-$(CONFIG_INPUT_LIS302DL) += lis302dl.o
+obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o
+obj-$(CONFIG_INPUT_PCF50606_PMU) += pcf50606-input.o
--- /dev/null
+++ b/drivers/input/misc/pcf50606-input.c
@@ -0,0 +1,123 @@
+/* Philips PCF50606 Input Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50606 driver mainly by
+ * Harald Welte, Matt Hsu, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 060, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/input.h>
+
+#include <linux/mfd/pcf50606/core.h>
+#include <linux/mfd/pcf50606/input.h>
+
+static void
+pcf50606_input_irq(struct pcf50606 *pcf, int irq, void *data)
+{
+ struct input_dev *input_dev = pcf->input.input_dev;
+ int onkey_released;
+
+ /* We report only one event depending on if the key status */
+ onkey_released = pcf50606_reg_read(pcf, PCF50606_REG_OOCS) &
+ PCF50606_OOCS_ONKEY;
+
+ if (irq == PCF50606_IRQ_ONKEYF && !onkey_released)
+ input_report_key(input_dev, KEY_POWER, 1);
+ else if (irq == PCF50606_IRQ_ONKEYR && onkey_released)
+ input_report_key(input_dev, KEY_POWER, 0);
+
+ input_sync(input_dev);
+}
+
+int __init pcf50606_input_probe(struct platform_device *pdev)
+{
+ struct pcf50606 *pcf;
+ struct input_dev *input_dev;
+ int ret;
+
+ pcf = platform_get_drvdata(pdev);
+
+ input_dev = input_allocate_device();
+ if (!input_dev)
+ return -ENODEV;
+
+ input_dev->name = "PCF50606 PMU events";
+ input_dev->id.bustype = BUS_I2C;
+
+ input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
+ set_bit(KEY_POWER, input_dev->keybit);
+ set_bit(KEY_POWER2, input_dev->keybit);
+
+ ret = input_register_device(input_dev);
+ if (ret)
+ goto out;
+
+ pcf->input.input_dev = input_dev;
+
+ /* Currently we care only about ONKEY and USBINS/USBREM
+ *
+ * USBINS/USBREM are told to us by mbc driver as we can't setup
+ * two handlers for an IRQ
+ */
+ pcf->irq_handler[PCF50606_IRQ_ONKEYR].handler = pcf50606_input_irq;
+
+ pcf->irq_handler[PCF50606_IRQ_ONKEYF].handler = pcf50606_input_irq;
+
+ return 0;
+
+out:
+ input_free_device(input_dev);
+ return ret;
+}
+
+static int __devexit pcf50606_input_remove(struct platform_device *pdev)
+{
+ struct pcf50606 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+ input_unregister_device(pcf->input.input_dev);
+
+ return 0;
+}
+
+struct platform_driver pcf50606_input_driver = {
+ .driver = {
+ .name = "pcf50606-input",
+ },
+ .probe = pcf50606_input_probe,
+ .remove = __devexit_p(pcf50606_input_remove),
+};
+
+static int __init pcf50606_input_init(void)
+{
+ return platform_driver_register(&pcf50606_input_driver);
+}
+module_init(pcf50606_input_init);
+
+static void __exit pcf50606_input_exit(void)
+{
+ platform_driver_unregister(&pcf50606_input_driver);
+}
+module_exit(pcf50606_input_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50606 input driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50606-input");
--- /dev/null
+++ b/drivers/input/misc/pcf50633-input.c
@@ -0,0 +1,123 @@
+/* Philips PCF50633 Input Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50633 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/input.h>
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/input.h>
+
+static void
+pcf50633_input_irq(struct pcf50633 *pcf, int irq, void *data)
+{
+ struct input_dev *input_dev = pcf->input.input_dev;
+ int onkey_released;
+
+ /* We report only one event depending on if the key status */
+ onkey_released = pcf50633_reg_read(pcf, PCF50633_REG_OOCSTAT) &
+ PCF50633_OOCSTAT_ONKEY;
+
+ if (irq == PCF50633_IRQ_ONKEYF && !onkey_released)
+ input_report_key(input_dev, KEY_POWER, 1);
+ else if (irq == PCF50633_IRQ_ONKEYR && onkey_released)
+ input_report_key(input_dev, KEY_POWER, 0);
+
+ input_sync(input_dev);
+}
+
+int __init pcf50633_input_probe(struct platform_device *pdev)
+{
+ struct pcf50633 *pcf;
+ struct input_dev *input_dev;
+ int ret;
+
+ pcf = platform_get_drvdata(pdev);
+
+ input_dev = input_allocate_device();
+ if (!input_dev)
+ return -ENODEV;
+
+ input_dev->name = "GTA02 PMU events";
+ input_dev->id.bustype = BUS_I2C;
+
+ input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_PWR);
+ set_bit(KEY_POWER, input_dev->keybit);
+ set_bit(KEY_POWER2, input_dev->keybit);
+
+ ret = input_register_device(input_dev);
+ if (ret)
+ goto out;
+
+ pcf->input.input_dev = input_dev;
+
+ /* Currently we care only about ONKEY and USBINS/USBREM
+ *
+ * USBINS/USBREM are told to us by mbc driver as we can't setup
+ * two handlers for an IRQ
+ */
+ pcf->irq_handler[PCF50633_IRQ_ONKEYR].handler = pcf50633_input_irq;
+
+ pcf->irq_handler[PCF50633_IRQ_ONKEYF].handler = pcf50633_input_irq;
+
+ return 0;
+
+out:
+ input_free_device(input_dev);
+ return ret;
+}
+
+static int __devexit pcf50633_input_remove(struct platform_device *pdev)
+{
+ struct pcf50633 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+ input_unregister_device(pcf->input.input_dev);
+
+ return 0;
+}
+
+struct platform_driver pcf50633_input_driver = {
+ .driver = {
+ .name = "pcf50633-input",
+ },
+ .probe = pcf50633_input_probe,
+ .remove = __devexit_p(pcf50633_input_remove),
+};
+
+static int __init pcf50633_input_init(void)
+{
+ return platform_driver_register(&pcf50633_input_driver);
+}
+module_init(pcf50633_input_init);
+
+static void __exit pcf50633_input_exit(void)
+{
+ platform_driver_unregister(&pcf50633_input_driver);
+}
+module_exit(pcf50633_input_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50633 input driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50633-input");
--- a/drivers/input/mousedev.c
+++ b/drivers/input/mousedev.c
@@ -1016,6 +1016,7 @@
.evbit = { BIT_MASK(EV_KEY) | BIT_MASK(EV_REL) },
.relbit = { BIT_MASK(REL_WHEEL) },
}, /* A separate scrollwheel */
+#if 0
{
.flags = INPUT_DEVICE_ID_MATCH_EVBIT |
INPUT_DEVICE_ID_MATCH_KEYBIT |
@@ -1025,6 +1026,7 @@
.absbit = { BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
}, /* A tablet like device, at least touch detection,
two absolute axes */
+#endif
{
.flags = INPUT_DEVICE_ID_MATCH_EVBIT |
INPUT_DEVICE_ID_MATCH_KEYBIT |
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -11,6 +11,50 @@
if INPUT_TOUCHSCREEN
+menuconfig TOUCHSCREEN_FILTER
+ boolean "Touchscreen Filtering"
+ depends on INPUT_TOUCHSCREEN
+ help
+ Select this to include kernel touchscreen filter support. The filters
+ can be combined in any order in your machine init and the parameters
+ for them can also be set there.
+
+if TOUCHSCREEN_FILTER
+
+config TOUCHSCREEN_FILTER_GROUP
+ bool "Group Touchscreen Filter"
+ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
+ default Y
+ help
+ Say Y here if you want to use the Group touchscreen filter, it
+ avoids using atypical samples.
+
+config TOUCHSCREEN_FILTER_MEDIAN
+ bool "Median Average Touchscreen Filter"
+ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
+ default Y
+ help
+ Say Y here if you want to use the Median touchscreen filter, it's
+ highly effective if you data is noisy with occasional excursions.
+
+config TOUCHSCREEN_FILTER_MEAN
+ bool "Mean Average Touchscreen Filter"
+ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
+ default Y
+ help
+ Say Y here if you want to use the Mean touchscreen filter, it
+ can further improve decent quality data by removing jitter
+
+config TOUCHSCREEN_FILTER_LINEAR
+ bool "Linear Touchscreen Filter"
+ depends on INPUT_TOUCHSCREEN && TOUCHSCREEN_FILTER
+ default Y
+ help
+ Say Y here if you want to use the Mean touchscreen filter, it
+ enables the use of calibration data for the touchscreen.
+
+endif
+
config TOUCHSCREEN_ADS7846
tristate "ADS7846/TSC2046 and ADS7843 based touchscreens"
depends on SPI_MASTER
@@ -71,6 +115,25 @@
To compile this driver as a module, choose M here: the
module will be called fujitsu-ts.
+config TOUCHSCREEN_S3C2410
+ tristate "Samsung S3C2410 touchscreen input driver"
+ depends on ARCH_S3C2410 && INPUT && INPUT_TOUCHSCREEN
+ select SERIO
+ select TOUCHSCREEN_FILTER
+ help
+ Say Y here if you have the s3c2410 touchscreen.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called s3c2410_ts.
+
+config TOUCHSCREEN_S3C2410_DEBUG
+ boolean "Samsung S3C2410 touchscreen debug messages"
+ depends on TOUCHSCREEN_S3C2410
+ help
+ Select this if you want debug messages
+
config TOUCHSCREEN_GUNZE
tristate "Gunze AHL-51S touchscreen"
select SERIO
@@ -376,4 +439,15 @@
To compile this driver as a module, choose M here: the
module will be called touchit213.
+config TOUCHSCREEN_PCAP7200
+ tristate "EETI Projected capacitive touchscreen controller"
+ help
+ Say Y here if you have the EETI PCAP7200 touchscreen
+ controller chip in your system.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called pcap7200.
endif
+
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -31,3 +31,10 @@
wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o
wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o
obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o
+obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o
+obj-$(CONFIG_TOUCHSCREEN_FILTER) += ts_filter.o
+obj-$(CONFIG_TOUCHSCREEN_FILTER_GROUP) += ts_filter_group.o
+obj-$(CONFIG_TOUCHSCREEN_FILTER_LINEAR) += ts_filter_linear.o
+obj-$(CONFIG_TOUCHSCREEN_FILTER_MEDIAN) += ts_filter_median.o
+obj-$(CONFIG_TOUCHSCREEN_FILTER_MEAN) += ts_filter_mean.o
+obj-$(CONFIG_TOUCHSCREEN_PCAP7200) += pcap7200_ts.o
--- /dev/null
+++ b/drivers/input/touchscreen/s3c2410_ts.c
@@ -0,0 +1,618 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * iPAQ H1940 touchscreen support
+ *
+ * ChangeLog
+ *
+ * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
+ * - added clock (de-)allocation code
+ *
+ * 2005-03-06: Arnaud Patard <arnaud.patard@rtp-net.org>
+ * - h1940_ -> s3c2410 (this driver is now also used on the n30
+ * machines :P)
+ * - Debug messages are now enabled with the config option
+ * TOUCHSCREEN_S3C2410_DEBUG
+ * - Changed the way the value are read
+ * - Input subsystem should now work
+ * - Use ioremap and readl/writel
+ *
+ * 2005-03-23: Arnaud Patard <arnaud.patard@rtp-net.org>
+ * - Make use of some undocumented features of the touchscreen
+ * controller
+ *
+ * 2007-05-23: Harald Welte <laforge@openmoko.org>
+ * - Add proper support for S32440
+ *
+ * 2008-06-23: Andy Green <andy@openmoko.com>
+ * - removed averaging system
+ * - added generic Touchscreen filter stuff
+ *
+ * 2008-11-27: Nelson Castillo <arhuaco@freaks-unidos.net>
+ * - improve interrupt handling
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/init.h>
+#include <linux/serio.h>
+#include <linux/timer.h>
+#include <linux/kfifo.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/ts.h>
+
+#include <plat/regs-adc.h>
+
+#include <linux/ts_filter.h>
+
+/* For ts.dev.id.version */
+#define S3C2410TSVERSION 0x0101
+
+#define TSC_SLEEP (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0))
+
+#define WAIT4INT(x) (((x)<<8) | \
+ S3C2410_ADCTSC_YM_SEN | \
+ S3C2410_ADCTSC_YP_SEN | \
+ S3C2410_ADCTSC_XP_SEN | \
+ S3C2410_ADCTSC_XY_PST(3))
+
+#define AUTOPST (S3C2410_ADCTSC_YM_SEN | \
+ S3C2410_ADCTSC_YP_SEN | \
+ S3C2410_ADCTSC_XP_SEN | \
+ S3C2410_ADCTSC_AUTO_PST | \
+ S3C2410_ADCTSC_XY_PST(0))
+
+#define DEBUG_LVL KERN_DEBUG
+
+MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
+MODULE_DESCRIPTION("s3c2410 touchscreen driver");
+MODULE_LICENSE("GPL");
+
+/*
+ * Definitions & global arrays.
+ */
+
+static char *s3c2410ts_name = "s3c2410 TouchScreen";
+
+#define TS_RELEASE_TIMEOUT (HZ >> 4) /* ~ 60 milliseconds */
+#define TS_EVENT_FIFO_SIZE (2 << 6) /* must be a power of 2 */
+
+#define TS_STATE_STANDBY 0 /* initial state */
+#define TS_STATE_PRESSED 1
+#define TS_STATE_RELEASE_PENDING 2
+#define TS_STATE_RELEASE 3
+
+/*
+ * Per-touchscreen data.
+ */
+
+struct s3c2410ts {
+ struct input_dev *dev;
+ struct ts_filter *tsf[MAX_TS_FILTER_CHAIN];
+ int coords[2]; /* just X and Y for us */
+ int is_down;
+ int state;
+ struct kfifo *event_fifo;
+};
+
+static struct s3c2410ts ts;
+
+static void __iomem *base_addr;
+
+/*
+ * A few low level functions.
+ */
+
+static inline void s3c2410_ts_connect(void)
+{
+ s3c2410_gpio_cfgpin(S3C2410_GPG12, S3C2410_GPG12_XMON);
+ s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPG13_nXPON);
+ s3c2410_gpio_cfgpin(S3C2410_GPG14, S3C2410_GPG14_YMON);
+ s3c2410_gpio_cfgpin(S3C2410_GPG15, S3C2410_GPG15_nYPON);
+}
+
+static void s3c2410_ts_start_adc_conversion(void)
+{
+ writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST,
+ base_addr + S3C2410_ADCTSC);
+ writel(readl(base_addr + S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START,
+ base_addr + S3C2410_ADCCON);
+}
+
+/*
+ * Just send the input events.
+ */
+
+enum ts_input_event {IE_DOWN = 0, IE_UP};
+
+static void ts_input_report(int event, int coords[])
+{
+#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
+ static char *s[] = {"down", "up"};
+ struct timeval tv;
+
+ do_gettimeofday(&tv);
+#endif
+
+ if (event == IE_DOWN) {
+ input_report_abs(ts.dev, ABS_X, coords[0]);
+ input_report_abs(ts.dev, ABS_Y, coords[1]);
+ input_report_key(ts.dev, BTN_TOUCH, 1);
+ input_report_abs(ts.dev, ABS_PRESSURE, 1);
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
+ printk(DEBUG_LVL "T:%06d %6s (X:%03d, Y:%03d)\n",
+ (int)tv.tv_usec, s[event], coords[0], coords[1]);
+#endif
+ } else {
+ input_report_key(ts.dev, BTN_TOUCH, 0);
+ input_report_abs(ts.dev, ABS_PRESSURE, 0);
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
+ printk(DEBUG_LVL "T:%06d %6s\n",
+ (int)tv.tv_usec, s[event]);
+#endif
+ }
+
+ input_sync(ts.dev);
+}
+
+/*
+ * Manage the state of the touchscreen.
+ */
+
+static void event_send_timer_f(unsigned long data);
+
+static struct timer_list event_send_timer =
+ TIMER_INITIALIZER(event_send_timer_f, 0, 0);
+
+static void event_send_timer_f(unsigned long data)
+{
+ static unsigned long running;
+ static int noop_counter;
+ int event_type;
+
+ if (unlikely(test_and_set_bit(0, &running))) {
+ mod_timer(&event_send_timer,
+ jiffies + TS_RELEASE_TIMEOUT);
+ return;
+ }
+
+ while (__kfifo_get(ts.event_fifo, (unsigned char *)&event_type,
+ sizeof(int))) {
+ int buf[2];
+
+ switch (event_type) {
+ case 'D':
+ if (ts.state == TS_STATE_RELEASE_PENDING)
+ /* Ignore short UP event */
+ ts.state = TS_STATE_PRESSED;
+ break;
+
+ case 'U':
+ ts.state = TS_STATE_RELEASE_PENDING;
+ break;
+
+ case 'P':
+ if (ts.is_down) /* stylus_action needs a conversion */
+ s3c2410_ts_start_adc_conversion();
+
+ if (unlikely(__kfifo_get(ts.event_fifo,
+ (unsigned char *)buf,
+ sizeof(int) * 2)
+ != sizeof(int) * 2))
+ goto ts_exit_error;
+
+ ts_input_report(IE_DOWN, buf);
+ ts.state = TS_STATE_PRESSED;
+ break;
+
+ default:
+ goto ts_exit_error;
+ }
+
+ noop_counter = 0;
+ }
+
+ if (noop_counter++ >= 1) {
+ noop_counter = 0;
+ if (ts.state == TS_STATE_RELEASE_PENDING) {
+ /* We delay the UP event for a
+ * while to avoid jitter. If we get a DOWN
+ * event we do not send it. */
+
+ ts_input_report(IE_UP, NULL);
+ ts.state = TS_STATE_STANDBY;
+
+ if (ts.tsf[0])
+ (ts.tsf[0]->api->clear)(ts.tsf[0]);
+ }
+ } else {
+ mod_timer(&event_send_timer, jiffies + TS_RELEASE_TIMEOUT);
+ }
+
+ clear_bit(0, &running);
+
+ return;
+
+ts_exit_error: /* should not happen unless we have a bug */
+ printk(KERN_ERR __FILE__ ": event_send_timer_f failed\n");
+}
+
+/*
+ * Manage interrupts.
+ */
+
+static irqreturn_t stylus_updown(int irq, void *dev_id)
+{
+ unsigned long data0;
+ unsigned long data1;
+ int event_type;
+
+ data0 = readl(base_addr+S3C2410_ADCDAT0);
+ data1 = readl(base_addr+S3C2410_ADCDAT1);
+
+ ts.is_down = (!(data0 & S3C2410_ADCDAT0_UPDOWN)) &&
+ (!(data1 & S3C2410_ADCDAT0_UPDOWN));
+
+ event_type = ts.is_down ? 'D' : 'U';
+
+ if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)&event_type,
+ sizeof(int)) != sizeof(int))) /* should not happen */
+ printk(KERN_ERR __FILE__": stylus_updown lost event!\n");
+
+ if (ts.is_down)
+ s3c2410_ts_start_adc_conversion();
+ else
+ writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
+
+ mod_timer(&event_send_timer, jiffies + 1);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t stylus_action(int irq, void *dev_id)
+{
+ int buf[3];
+
+ /* grab the ADC results */
+ ts.coords[0] = readl(base_addr + S3C2410_ADCDAT0) &
+ S3C2410_ADCDAT0_XPDATA_MASK;
+ ts.coords[1] = readl(base_addr + S3C2410_ADCDAT1) &
+ S3C2410_ADCDAT1_YPDATA_MASK;
+
+ if (ts.tsf[0]) { /* filtering is enabled, don't use raw directly */
+ switch ((ts.tsf[0]->api->process)(ts.tsf[0], &ts.coords[0])) {
+ case 0: /*
+ * no real sample came out of processing yet,
+ * get another raw result to feed it
+ */
+ s3c2410_ts_start_adc_conversion();
+ return IRQ_HANDLED;
+ case 1: /* filters are ready to deliver a sample */
+ (ts.tsf[0]->api->scale)(ts.tsf[0], &ts.coords[0]);
+ break;
+ case -1:
+ /* error in filters, ignore the event */
+ (ts.tsf[0]->api->clear)(ts.tsf[0]);
+ writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
+ return IRQ_HANDLED;
+ default:
+ printk(KERN_ERR":stylus_action error\n");
+ }
+ }
+
+ /* We use a buffer because want an atomic operation */
+ buf[0] = 'P';
+ buf[1] = ts.coords[0];
+ buf[2] = ts.coords[1];
+
+ if (unlikely(__kfifo_put(ts.event_fifo, (unsigned char *)buf,
+ sizeof(int) * 3) != sizeof(int) * 3))
+ /* should not happen */
+ printk(KERN_ERR":stylus_action error\n");
+
+ writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
+ mod_timer(&event_send_timer, jiffies + 1);
+
+ return IRQ_HANDLED;
+}
+
+static struct clk *adc_clock;
+
+/*
+ * The functions for inserting/removing us as a module.
+ */
+
+static int __init s3c2410ts_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct s3c2410_ts_mach_info *info;
+ struct input_dev *input_dev;
+ int ret = 0;
+
+ dev_info(&pdev->dev, "Starting\n");
+
+ info = (struct s3c2410_ts_mach_info *)pdev->dev.platform_data;
+
+ if (!info)
+ {
+ dev_err(&pdev->dev, "Hm... too bad: no platform data for ts\n");
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
+ printk(DEBUG_LVL "Entering s3c2410ts_init\n");
+#endif
+
+ adc_clock = clk_get(NULL, "adc");
+ if (!adc_clock) {
+ dev_err(&pdev->dev, "failed to get adc clock source\n");
+ return -ENOENT;
+ }
+ clk_enable(adc_clock);
+
+#ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG
+ printk(DEBUG_LVL "got and enabled clock\n");
+#endif
+
+ base_addr = ioremap(S3C2410_PA_ADC,0x20);
+ if (base_addr == NULL) {
+ dev_err(&pdev->dev, "Failed to remap register block\n");
+ ret = -ENOMEM;
+ goto bail0;
+ }
+
+
+ /* If we acutally are a S3C2410: Configure GPIOs */
+ if (!strcmp(pdev->name, "s3c2410-ts"))
+ s3c2410_ts_connect();
+
+ if ((info->presc & 0xff) > 0)
+ writel(S3C2410_ADCCON_PRSCEN |
+ S3C2410_ADCCON_PRSCVL(info->presc&0xFF),
+ base_addr + S3C2410_ADCCON);
+ else
+ writel(0, base_addr+S3C2410_ADCCON);
+
+ /* Initialise registers */
+ if ((info->delay & 0xffff) > 0)
+ writel(info->delay & 0xffff, base_addr + S3C2410_ADCDLY);
+
+ writel(WAIT4INT(0), base_addr + S3C2410_ADCTSC);
+
+ /* Initialise input stuff */
+ memset(&ts, 0, sizeof(struct s3c2410ts));
+ input_dev = input_allocate_device();
+
+ if (!input_dev) {
+ dev_err(&pdev->dev, "Unable to allocate the input device\n");
+ ret = -ENOMEM;
+ goto bail1;
+ }
+
+ ts.dev = input_dev;
+ ts.dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) |
+ BIT_MASK(EV_ABS);
+ ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+ input_set_abs_params(ts.dev, ABS_X, 0, 0x3FF, 0, 0);
+ input_set_abs_params(ts.dev, ABS_Y, 0, 0x3FF, 0, 0);
+ input_set_abs_params(ts.dev, ABS_PRESSURE, 0, 1, 0, 0);
+
+ ts.dev->name = s3c2410ts_name;
+ ts.dev->id.bustype = BUS_RS232;
+ ts.dev->id.vendor = 0xDEAD;
+ ts.dev->id.product = 0xBEEF;
+ ts.dev->id.version = S3C2410TSVERSION;
+ ts.state = TS_STATE_STANDBY;
+ ts.event_fifo = kfifo_alloc(TS_EVENT_FIFO_SIZE, GFP_KERNEL, NULL);
+ if (IS_ERR(ts.event_fifo)) {
+ ret = -EIO;
+ goto bail2;
+ }
+
+ /* create the filter chain set up for the 2 coordinates we produce */
+ ret = ts_filter_create_chain(
+ pdev, (struct ts_filter_api **)&info->filter_sequence,
+ (void *)&info->filter_config, ts.tsf, ARRAY_SIZE(ts.coords));
+ if (ret)
+ dev_info(&pdev->dev, "%d filter(s) initialized\n", ret);
+ else /* this is OK, just means there won't be any filtering */
+ dev_info(&pdev->dev, "Unfiltered output selected\n");
+
+ if (ts.tsf[0])
+ (ts.tsf[0]->api->clear)(ts.tsf[0]);
+ else
+ dev_info(&pdev->dev, "No filtering\n");
+
+ /* Get irqs */
+ if (request_irq(IRQ_ADC, stylus_action, IRQF_SAMPLE_RANDOM,
+ "s3c2410_action", ts.dev)) {
+ dev_err(&pdev->dev, "Could not allocate ts IRQ_ADC !\n");
+ iounmap(base_addr);
+ ret = -EIO;
+ goto bail3;
+ }
+ if (request_irq(IRQ_TC, stylus_updown, IRQF_SAMPLE_RANDOM,
+ "s3c2410_action", ts.dev)) {
+ dev_err(&pdev->dev, "Could not allocate ts IRQ_TC !\n");
+ free_irq(IRQ_ADC, ts.dev);
+ iounmap(base_addr);
+ ret = -EIO;
+ goto bail4;
+ }
+
+ dev_info(&pdev->dev, "successfully loaded\n");
+
+ /* All went ok, so register to the input system */
+ rc = input_register_device(ts.dev);
+ if (rc) {
+ ret = -EIO;
+ goto bail5;
+ }
+
+ return 0;
+
+bail5:
+ free_irq(IRQ_TC, ts.dev);
+ free_irq(IRQ_ADC, ts.dev);
+ clk_disable(adc_clock);
+ iounmap(base_addr);
+ disable_irq(IRQ_TC);
+bail4:
+ disable_irq(IRQ_ADC);
+bail3:
+ ts_filter_destroy_chain(pdev, ts.tsf);
+ kfifo_free(ts.event_fifo);
+bail2:
+ input_unregister_device(ts.dev);
+bail1:
+ iounmap(base_addr);
+bail0:
+
+ return ret;
+}
+
+static int s3c2410ts_remove(struct platform_device *pdev)
+{
+ disable_irq(IRQ_ADC);
+ disable_irq(IRQ_TC);
+ free_irq(IRQ_TC,ts.dev);
+ free_irq(IRQ_ADC,ts.dev);
+
+ if (adc_clock) {
+ clk_disable(adc_clock);
+ clk_put(adc_clock);
+ adc_clock = NULL;
+ }
+
+ input_unregister_device(ts.dev);
+ iounmap(base_addr);
+
+ ts_filter_destroy_chain(pdev, ts.tsf);
+
+ kfifo_free(ts.event_fifo);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c2410ts_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ writel(TSC_SLEEP, base_addr+S3C2410_ADCTSC);
+ writel(readl(base_addr+S3C2410_ADCCON) | S3C2410_ADCCON_STDBM,
+ base_addr+S3C2410_ADCCON);
+
+ disable_irq(IRQ_ADC);
+ disable_irq(IRQ_TC);
+
+ clk_disable(adc_clock);
+
+ return 0;
+}
+
+static int s3c2410ts_resume(struct platform_device *pdev)
+{
+ struct s3c2410_ts_mach_info *info =
+ ( struct s3c2410_ts_mach_info *)pdev->dev.platform_data;
+
+ clk_enable(adc_clock);
+ mdelay(1);
+
+ if (ts.tsf[0])
+ (ts.tsf[0]->api->clear)(ts.tsf[0]);
+
+ enable_irq(IRQ_ADC);
+ enable_irq(IRQ_TC);
+
+ if ((info->presc&0xff) > 0)
+ writel(S3C2410_ADCCON_PRSCEN |
+ S3C2410_ADCCON_PRSCVL(info->presc&0xFF),
+ base_addr+S3C2410_ADCCON);
+ else
+ writel(0,base_addr+S3C2410_ADCCON);
+
+ /* Initialise registers */
+ if ((info->delay & 0xffff) > 0)
+ writel(info->delay & 0xffff, base_addr+S3C2410_ADCDLY);
+
+ writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
+
+ return 0;
+}
+
+#else
+#define s3c2410ts_suspend NULL
+#define s3c2410ts_resume NULL
+#endif
+
+static struct platform_driver s3c2410ts_driver = {
+ .driver = {
+ .name = "s3c2410-ts",
+ .owner = THIS_MODULE,
+ },
+ .probe = s3c2410ts_probe,
+ .remove = s3c2410ts_remove,
+ .suspend = s3c2410ts_suspend,
+ .resume = s3c2410ts_resume,
+
+};
+
+static struct platform_driver s3c2440ts_driver = {
+ .driver = {
+ .name = "s3c2440-ts",
+ .owner = THIS_MODULE,
+ },
+ .probe = s3c2410ts_probe,
+ .remove = s3c2410ts_remove,
+ .suspend = s3c2410ts_suspend,
+ .resume = s3c2410ts_resume,
+
+};
+
+static int __init s3c2410ts_init(void)
+{
+ int rc;
+
+ rc = platform_driver_register(&s3c2410ts_driver);
+ if (rc < 0)
+ return rc;
+
+ rc = platform_driver_register(&s3c2440ts_driver);
+ if (rc < 0)
+ platform_driver_unregister(&s3c2410ts_driver);
+
+ return rc;
+}
+
+static void __exit s3c2410ts_exit(void)
+{
+ platform_driver_unregister(&s3c2440ts_driver);
+ platform_driver_unregister(&s3c2410ts_driver);
+}
+
+module_init(s3c2410ts_init);
+module_exit(s3c2410ts_exit);
+
--- /dev/null
+++ b/drivers/input/touchscreen/ts_filter.c
@@ -0,0 +1,64 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (c) 2008 Andy Green <andy@openmoko.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/ts_filter.h>
+
+int ts_filter_create_chain(struct platform_device *pdev,
+ struct ts_filter_api **api, void **config,
+ struct ts_filter **list, int count_coords)
+{
+ int count = 0;
+ struct ts_filter *last = NULL;
+
+ if (!api)
+ return 0;
+
+ while (*api && count < MAX_TS_FILTER_CHAIN) {
+ *list = ((*api)->create)(pdev, *config++, count_coords);
+ if (!*list) {
+ printk(KERN_ERR "Filter %d failed init\n", count);
+ return count;
+ }
+ (*list)->api = *api++;
+ if (last)
+ last->next = *list;
+ last = *list;
+ list++;
+ count++;
+ }
+
+ return count;
+}
+EXPORT_SYMBOL_GPL(ts_filter_create_chain);
+
+void ts_filter_destroy_chain(struct platform_device *pdev,
+ struct ts_filter **list)
+{
+ struct ts_filter **first;
+ int count = 0;
+
+ first = list;
+ while (*list && count++ < MAX_TS_FILTER_CHAIN) {
+ ((*list)->api->destroy)(pdev, *list);
+ list++;
+ }
+ *first = NULL;
+}
+EXPORT_SYMBOL_GPL(ts_filter_destroy_chain);
--- /dev/null
+++ b/drivers/input/touchscreen/ts_filter_group.c
@@ -0,0 +1,219 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (C) 2008 by Openmoko, Inc.
+ * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
+ * All rights reserved.
+ *
+ * This filter is useful to reject samples that are not reliable. We consider
+ * that a sample is not reliable if it deviates form the Majority.
+ *
+ * 1) We collect S samples.
+ *
+ * 2) For each dimension:
+ *
+ * - We sort the points.
+ * - Points that are "close enough" are considered to be in the same set.
+ * - We choose the set with more elements. If more than "threshold"
+ * points are in this set we use the first and the last point of the set
+ * to define the valid range for this dimension [min, max], otherwise we
+ * discard all the points and go to step 1.
+ *
+ * 3) We consider the unsorted S samples and try to feed them to the next
+ * filter in the chain. If one of the points of each sample
+ * is not in the allowed range for its dimension, we discard the sample.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/sort.h>
+#include <linux/ts_filter_group.h>
+
+static void ts_filter_group_clear_internal(struct ts_filter_group *tsfg,
+ int attempts)
+{
+ tsfg->N = 0;
+ tsfg->tries_left = attempts;
+}
+
+static void ts_filter_group_clear(struct ts_filter *tsf)
+{
+ struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
+
+ ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
+
+ if (tsf->next) /* chain */
+ (tsf->next->api->clear)(tsf->next);
+}
+
+static struct ts_filter *ts_filter_group_create(struct platform_device *pdev,
+ void *conf, int count_coords)
+{
+ struct ts_filter_group *tsfg;
+ int i;
+
+ BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
+
+ tsfg = kzalloc(sizeof(struct ts_filter_group), GFP_KERNEL);
+ if (!tsfg)
+ return NULL;
+
+ tsfg->config = (struct ts_filter_group_configuration *)conf;
+ tsfg->tsf.count_coords = count_coords;
+
+ BUG_ON(tsfg->config->attempts <= 0);
+
+ tsfg->samples[0] = kmalloc((2 + count_coords) * sizeof(int) *
+ tsfg->config->extent, GFP_KERNEL);
+ if (!tsfg->samples[0]) {
+ kfree(tsfg);
+ return NULL;
+ }
+ for (i = 1; i < count_coords; ++i)
+ tsfg->samples[i] = tsfg->samples[0] + i * tsfg->config->extent;
+ tsfg->sorted_samples = tsfg->samples[0] + count_coords *
+ tsfg->config->extent;
+ tsfg->group_size = tsfg->samples[0] + (1 + count_coords) *
+ tsfg->config->extent;
+
+ ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
+
+ printk(KERN_INFO" Created group ts filter len %d depth %d close %d "
+ "thresh %d\n", tsfg->config->extent, count_coords,
+ tsfg->config->close_enough, tsfg->config->threshold);
+
+ return &tsfg->tsf;
+}
+
+static void ts_filter_group_destroy(struct platform_device *pdev,
+ struct ts_filter *tsf)
+{
+ struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
+
+ kfree(tsfg->samples[0]); /* first guy has pointer from kmalloc */
+ kfree(tsf);
+}
+
+static void ts_filter_group_scale(struct ts_filter *tsf, int *coords)
+{
+ if (tsf->next)
+ (tsf->next->api->scale)(tsf->next, coords);
+}
+
+static int int_cmp(const void *_a, const void *_b)
+{
+ const int *a = _a;
+ const int *b = _b;
+
+ if (*a > *b)
+ return 1;
+ if (*a < *b)
+ return -1;
+ return 0;
+}
+
+static int ts_filter_group_process(struct ts_filter *tsf, int *coords)
+{
+ struct ts_filter_group *tsfg = (struct ts_filter_group *)tsf;
+ int n;
+ int i;
+ int ret = 0; /* ask for more samples by default */
+
+ BUG_ON(tsfg->N >= tsfg->config->extent);
+
+ for (n = 0; n < tsf->count_coords; n++)
+ tsfg->samples[n][tsfg->N] = coords[n];
+
+ if (++tsfg->N < tsfg->config->extent)
+ return 0; /* we meed more samples */
+
+ for (n = 0; n < tsfg->tsf.count_coords; n++) {
+ int *v = tsfg->sorted_samples;
+ int ngroups = 0;
+ int best_size;
+ int best_idx = 0;
+ int idx = 0;
+
+ memcpy(v, tsfg->samples[n], tsfg->N * sizeof(int));
+ sort(v, tsfg->N, sizeof(int), int_cmp, NULL);
+
+ tsfg->group_size[0] = 1;
+ for (i = 1; i < tsfg->N; ++i) {
+ if (v[i] - v[i - 1] <= tsfg->config->close_enough)
+ tsfg->group_size[ngroups]++;
+ else
+ tsfg->group_size[++ngroups] = 1;
+ }
+ ngroups++;
+
+ best_size = tsfg->group_size[0];
+ for (i = 1; i < ngroups; i++) {
+ idx += tsfg->group_size[i - 1];
+ if (best_size < tsfg->group_size[i]) {
+ best_size = tsfg->group_size[i];
+ best_idx = idx;
+ }
+ }
+
+ if (best_size < tsfg->config->threshold) {
+ /* this set is not good enough for us */
+ if (--tsfg->tries_left) {
+ ts_filter_group_clear_internal
+ (tsfg, tsfg->tries_left);
+ return 0; /* ask for more samples */
+ }
+ return -1; /* we give up */
+ }
+
+ tsfg->range_min[n] = v[best_idx];
+ tsfg->range_max[n] = v[best_idx + best_size - 1];
+ }
+
+ BUG_ON(!tsf->next);
+
+ for (i = 0; i < tsfg->N; ++i) {
+ int r;
+
+ for (n = 0; n < tsfg->tsf.count_coords; ++n) {
+ coords[n] = tsfg->samples[n][i];
+ if (coords[n] < tsfg->range_min[n] ||
+ coords[n] > tsfg->range_max[n])
+ break;
+ }
+
+ if (n != tsfg->tsf.count_coords) /* sample not OK */
+ continue;
+
+ r = (tsf->next->api->process)(tsf->next, coords);
+ if (r) {
+ ret = r;
+ break;
+ }
+ }
+
+ ts_filter_group_clear_internal(tsfg, tsfg->config->attempts);
+
+ return ret;
+}
+
+struct ts_filter_api ts_filter_group_api = {
+ .create = ts_filter_group_create,
+ .destroy = ts_filter_group_destroy,
+ .clear = ts_filter_group_clear,
+ .process = ts_filter_group_process,
+ .scale = ts_filter_group_scale,
+};
+
--- /dev/null
+++ b/drivers/input/touchscreen/ts_filter_linear.c
@@ -0,0 +1,178 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (C) 2008 by Openmoko, Inc.
+ * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
+ * All rights reserved.
+ *
+ * Linearly scale touchscreen values.
+ *
+ * Expose the TS_FILTER_LINEAR_NCONSTANTS for the linear transformation
+ * using sysfs.
+ *
+ */
+
+#include <linux/ts_filter_linear.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+
+/*
+ * sysfs functions
+ */
+
+
+static ssize_t const_attr_show(struct kobject *kobj,
+ struct attribute *attr,
+ char *buf)
+{
+ struct const_attribute *a = to_const_attr(attr);
+
+ return a->show(to_const_obj(kobj), a, buf);
+}
+
+static ssize_t const_attr_store(struct kobject *kobj,
+ struct attribute *attr,
+ const char *buf, size_t len)
+{
+ struct const_attribute *a = to_const_attr(attr);
+
+ return a->store(to_const_obj(kobj), a, buf, len);
+}
+
+static struct sysfs_ops const_sysfs_ops = {
+ .show = const_attr_show,
+ .store = const_attr_store,
+};
+
+static void const_release(struct kobject *kobj)
+{
+ kfree(to_const_obj(kobj)->tsfl);
+}
+
+static ssize_t const_show(struct const_obj *obj, struct const_attribute *attr,
+ char *buf)
+{
+ int who;
+
+ sscanf(attr->attr.name, "%d", &who);
+ return sprintf(buf, "%d\n", obj->tsfl->constants[who]);
+}
+
+static ssize_t const_store(struct const_obj *obj, struct const_attribute *attr,
+ const char *buf, size_t count)
+{
+ int who;
+
+ sscanf(attr->attr.name, "%d", &who);
+ sscanf(buf, "%d", &obj->tsfl->constants[who]);
+ return count;
+}
+
+/*
+ * filter functions
+ */
+
+static struct ts_filter *ts_filter_linear_create(struct platform_device *pdev,
+ void *conf, int count_coords)
+{
+ struct ts_filter_linear *tsfl;
+ int i;
+ int ret;
+
+ tsfl = kzalloc(sizeof(struct ts_filter_linear), GFP_KERNEL);
+ if (!tsfl)
+ return NULL;
+
+ tsfl->config = (struct ts_filter_linear_configuration *)conf;
+ tsfl->tsf.count_coords = count_coords;
+
+ for (i = 0; i < TS_FILTER_LINEAR_NCONSTANTS; ++i) {
+ tsfl->constants[i] = tsfl->config->constants[i];
+
+ /* sysfs */
+ sprintf(tsfl->attr_names[i], "%d", i);
+ tsfl->kattrs[i].attr.name = tsfl->attr_names[i];
+ tsfl->kattrs[i].attr.mode = 0666;
+ tsfl->kattrs[i].show = const_show;
+ tsfl->kattrs[i].store = const_store;
+ tsfl->attrs[i] = &tsfl->kattrs[i].attr;
+ }
+ tsfl->attrs[i] = NULL;
+
+ tsfl->const_ktype.sysfs_ops = &const_sysfs_ops;
+ tsfl->const_ktype.release = const_release;
+ tsfl->const_ktype.default_attrs = tsfl->attrs;
+ tsfl->c_obj.tsfl = tsfl; /* kernel frees tsfl in const_release */
+
+ /* TODO: /sys/ts-calibration is not OK */
+ ret = kobject_init_and_add(&tsfl->c_obj.kobj, &tsfl->const_ktype,
+ &pdev->dev.kobj, "calibration");
+ if (ret) {
+ kobject_put(&tsfl->c_obj.kobj);
+ return NULL;
+ }
+
+ printk(KERN_INFO" Created Linear ts filter depth %d\n", count_coords);
+
+ return &tsfl->tsf;
+}
+
+static void ts_filter_linear_destroy(struct platform_device *pdev,
+ struct ts_filter *tsf)
+{
+ struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf;
+
+ /* kernel frees tsfl in const_release */
+ kobject_put(&tsfl->c_obj.kobj);
+}
+
+static void ts_filter_linear_clear(struct ts_filter *tsf)
+{
+ if (tsf->next) /* chain */
+ (tsf->next->api->clear)(tsf->next);
+}
+
+
+static void ts_filter_linear_scale(struct ts_filter *tsf, int *coords)
+{
+ struct ts_filter_linear *tsfl = (struct ts_filter_linear *)tsf;
+ int *k = tsfl->constants;
+ int c0 = coords[tsfl->config->coord0];
+ int c1 = coords[tsfl->config->coord1];
+
+ coords[tsfl->config->coord0] = (k[2] + k[0] * c0 + k[1] * c1) / k[6];
+ coords[tsfl->config->coord1] = (k[5] + k[3] * c0 + k[4] * c1) / k[6];
+
+ if (tsf->next)
+ (tsf->next->api->scale)(tsf->next, coords);
+}
+
+static int ts_filter_linear_process(struct ts_filter *tsf, int *coords)
+{
+ if (tsf->next)
+ return (tsf->next->api->process)(tsf->next, coords);
+
+ return 1;
+}
+
+struct ts_filter_api ts_filter_linear_api = {
+ .create = ts_filter_linear_create,
+ .destroy = ts_filter_linear_destroy,
+ .clear = ts_filter_linear_clear,
+ .process = ts_filter_linear_process,
+ .scale = ts_filter_linear_scale,
+};
--- /dev/null
+++ b/drivers/input/touchscreen/ts_filter_mean.c
@@ -0,0 +1,172 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (c) 2008 Andy Green <andy@openmoko.com>
+ *
+ *
+ * Mean has no effect if the samples are changing by more that the
+ * threshold set by averaging_threshold in the configuration.
+ *
+ * However while samples come in that don't go outside this threshold from
+ * the last reported sample, Mean replaces the samples with a simple mean
+ * of a configurable number of samples (set by bits_filter_length in config,
+ * which is 2^n, so 5 there makes 32 sample averaging).
+ *
+ * Mean works well if the input data is already good quality, reducing + / - 1
+ * sample jitter when the stylus is still, or moving very slowly, without
+ * introducing abrupt transitions or reducing ability to follow larger
+ * movements. If you set the threshold higher than the dynamic range of the
+ * coordinates, you can just use it as a simple mean average.
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/ts_filter_mean.h>
+
+static void ts_filter_mean_clear_internal(struct ts_filter *tsf)
+{
+ struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
+ int n;
+
+ for (n = 0; n < tsfs->tsf.count_coords; n++) {
+ tsfs->fhead[n] = 0;
+ tsfs->ftail[n] = 0;
+ tsfs->lowpass[n] = 0;
+ }
+}
+
+static void ts_filter_mean_clear(struct ts_filter *tsf)
+{
+ ts_filter_mean_clear_internal(tsf);
+
+ if (tsf->next) /* chain */
+ (tsf->next->api->clear)(tsf->next);
+}
+
+static struct ts_filter *ts_filter_mean_create(struct platform_device *pdev,
+ void *config, int count_coords)
+{
+ int *p;
+ int n;
+ struct ts_filter_mean *tsfs = kzalloc(
+ sizeof(struct ts_filter_mean), GFP_KERNEL);
+
+ if (!tsfs)
+ return NULL;
+
+ BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
+ tsfs->tsf.count_coords = count_coords;
+
+ tsfs->config = (struct ts_filter_mean_configuration *)config;
+
+ tsfs->config->extent = 1 << tsfs->config->bits_filter_length;
+ BUG_ON((tsfs->config->extent > 256) || (!tsfs->config->extent));
+
+ p = kmalloc(tsfs->config->extent * sizeof(int) * count_coords,
+ GFP_KERNEL);
+ if (!p)
+ return NULL;
+
+ for (n = 0; n < count_coords; n++) {
+ tsfs->fifo[n] = p;
+ p += tsfs->config->extent;
+ }
+
+ if (!tsfs->config->averaging_threshold)
+ tsfs->config->averaging_threshold = 0xffff; /* always active */
+
+ ts_filter_mean_clear_internal(&tsfs->tsf);
+
+ printk(KERN_INFO" Created Mean ts filter len %d depth %d thresh %d\n",
+ tsfs->config->extent, count_coords,
+ tsfs->config->averaging_threshold);
+
+ return &tsfs->tsf;
+}
+
+static void ts_filter_mean_destroy(struct platform_device *pdev,
+ struct ts_filter *tsf)
+{
+ struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
+
+ kfree(tsfs->fifo[0]); /* first guy has pointer from kmalloc */
+ kfree(tsf);
+}
+
+static void ts_filter_mean_scale(struct ts_filter *tsf, int *coords)
+{
+ if (tsf->next) /* chain */
+ (tsf->next->api->scale)(tsf->next, coords);
+}
+
+/* give us the raw sample data in x and y, and if we return 1 then you can
+ * get a filtered coordinate from tsm->x and tsm->y: if we return 0 you didn't
+ * fill the filter with samples yet.
+ */
+
+static int ts_filter_mean_process(struct ts_filter *tsf, int *coords)
+{
+ struct ts_filter_mean *tsfs = (struct ts_filter_mean *)tsf;
+ int n;
+ int len;
+
+ for (n = 0; n < tsf->count_coords; n++) {
+
+ /* has he moved far enough away that we should abandon current
+ * low pass filtering state?
+ */
+ if ((coords[n] < (tsfs->reported[n] -
+ tsfs->config->averaging_threshold)) ||
+ (coords[n] > (tsfs->reported[n] +
+ tsfs->config->averaging_threshold))) {
+ tsfs->fhead[n] = 0;
+ tsfs->ftail[n] = 0;
+ tsfs->lowpass[n] = 0;
+ }
+
+ /* capture this sample into fifo and sum */
+ tsfs->fifo[n][tsfs->fhead[n]++] = coords[n];
+ if (tsfs->fhead[n] == tsfs->config->extent)
+ tsfs->fhead[n] = 0;
+ tsfs->lowpass[n] += coords[n];
+
+ /* adjust the sum into an average and use that*/
+ len = (tsfs->fhead[n] - tsfs->ftail[n]) &
+ (tsfs->config->extent - 1);
+ coords[n] = (tsfs->lowpass[n] + (len >> 1)) / len;
+ tsfs->reported[n] = coords[n];
+
+ /* remove oldest sample if we are full */
+ if (len == (tsfs->config->extent - 1)) {
+ tsfs->lowpass[n] -= tsfs->fifo[n][tsfs->ftail[n]++];
+ if (tsfs->ftail[n] == tsfs->config->extent)
+ tsfs->ftail[n] = 0;
+ }
+ }
+
+ if (tsf->next) /* chain */
+ return (tsf->next->api->process)(tsf->next, coords);
+
+ return 1;
+}
+
+struct ts_filter_api ts_filter_mean_api = {
+ .create = ts_filter_mean_create,
+ .destroy = ts_filter_mean_destroy,
+ .clear = ts_filter_mean_clear,
+ .process = ts_filter_mean_process,
+ .scale = ts_filter_mean_scale,
+};
--- /dev/null
+++ b/drivers/input/touchscreen/ts_filter_median.c
@@ -0,0 +1,215 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Copyright (c) 2008 Andy Green <andy@openmoko.com>
+ *
+ *
+ * Median averaging stuff. We sort incoming raw samples into an array of
+ * MEDIAN_SIZE length, discarding the oldest sample each time once we are full.
+ * We then return the sum of the middle three samples for X and Y. It means
+ * the final result must be divided by (3 * scaling factor) to correct for
+ * avoiding the repeated /3.
+ *
+ * This strongly rejects brief excursions away from a central point that is
+ * sticky in time compared to the excursion duration.
+ *
+ * Thanks to Dale Schumacher (who wrote some example code) and Carl-Daniel
+ * Halifinger who pointed out this would be a good method.
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/ts_filter_median.h>
+
+static void ts_filter_median_insert(int *p, int sample, int count)
+{
+ int n;
+
+ /* search through what we got so far to find where to put sample */
+ for (n = 0; n < count; n++)
+ /* we met somebody bigger than us? */
+ if (sample < p[n]) {
+ /* starting from the end, push bigger guys down one */
+ for (count--; count >= n; count--)
+ p[count + 1] = p[count];
+ p[n] = sample; /* and put us in place of first bigger */
+ return;
+ }
+
+ p[count] = sample; /* nobody was bigger than us, add us on the end */
+}
+
+static void ts_filter_median_del(int *p, int value, int count)
+{
+ int index;
+
+ for (index = 0; index < count; index++)
+ if (p[index] == value) {
+ for (; index < count; index++)
+ p[index] = p[index + 1];
+ return;
+ }
+}
+
+
+static void ts_filter_median_clear_internal(struct ts_filter *tsf)
+{
+ struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
+
+ tsfm->pos = 0;
+ tsfm->valid = 0;
+
+}
+static void ts_filter_median_clear(struct ts_filter *tsf)
+{
+ ts_filter_median_clear_internal(tsf);
+
+ if (tsf->next) /* chain */
+ (tsf->next->api->clear)(tsf->next);
+}
+
+static struct ts_filter *ts_filter_median_create(struct platform_device *pdev,
+ void *conf, int count_coords)
+{
+ int *p;
+ int n;
+ struct ts_filter_median *tsfm = kzalloc(sizeof(struct ts_filter_median),
+ GFP_KERNEL);
+
+ if (!tsfm)
+ return NULL;
+
+ tsfm->config = (struct ts_filter_median_configuration *)conf;
+ BUG_ON((count_coords < 1) || (count_coords > MAX_TS_FILTER_COORDS));
+ tsfm->tsf.count_coords = count_coords;
+
+ tsfm->config->midpoint = (tsfm->config->extent >> 1) + 1;
+
+ p = kmalloc(2 * count_coords * sizeof(int) * (tsfm->config->extent + 1),
+ GFP_KERNEL);
+ if (!p) {
+ kfree(tsfm);
+ return NULL;
+ }
+
+ for (n = 0; n < count_coords; n++) {
+ tsfm->sort[n] = p;
+ p += tsfm->config->extent + 1;
+ tsfm->fifo[n] = p;
+ p += tsfm->config->extent + 1;
+ }
+
+ ts_filter_median_clear_internal(&tsfm->tsf);
+
+ printk(KERN_INFO" Created Median ts filter len %d depth %d dec %d\n",
+ tsfm->config->extent, count_coords,
+ tsfm->config->decimation_threshold);
+
+ return &tsfm->tsf;
+}
+
+static void ts_filter_median_destroy(struct platform_device *pdev,
+ struct ts_filter *tsf)
+{
+ struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
+
+ kfree(tsfm->sort[0]); /* first guy has pointer from kmalloc */
+ kfree(tsf);
+}
+
+static void ts_filter_median_scale(struct ts_filter *tsf, int *coords)
+{
+ int n;
+
+ for (n = 0; n < tsf->count_coords; n++)
+ coords[n] = (coords[n] + 2) / 3;
+
+ if (tsf->next) /* chain */
+ (tsf->next->api->scale)(tsf->next, coords);
+}
+
+/* give us the raw sample data coords, and if we return 1 then you can
+ * get a filtered coordinate from coords: if we return 0 you didn't
+ * fill all the filters with samples yet.
+ */
+
+static int ts_filter_median_process(struct ts_filter *tsf, int *coords)
+{
+ struct ts_filter_median *tsfm = (struct ts_filter_median *)tsf;
+ int n;
+ int movement = 1;
+
+ for (n = 0; n < tsf->count_coords; n++) {
+ /* grab copy in insertion order to remove when oldest */
+ tsfm->fifo[n][tsfm->pos] = coords[n];
+ /* insert these samples in sorted order in the median arrays */
+ ts_filter_median_insert(tsfm->sort[n], coords[n], tsfm->valid);
+ }
+ /* move us on in the fifo */
+ if (++tsfm->pos == (tsfm->config->extent + 1))
+ tsfm->pos = 0;
+
+ /* we have finished a median sampling? */
+ if (++tsfm->valid != tsfm->config->extent)
+ return 0; /* no valid sample to use */
+
+ /* discard the oldest sample in median sorted array */
+ tsfm->valid--;
+
+ /* sum the middle 3 in the median sorted arrays. We don't divide back
+ * down which increases the sum resolution by a factor of 3 until the
+ * scale API is called
+ */
+ for (n = 0; n < tsfm->tsf.count_coords; n++)
+ /* perform the deletion of the oldest sample */
+ ts_filter_median_del(tsfm->sort[n], tsfm->fifo[n][tsfm->pos],
+ tsfm->valid);
+
+ tsfm->decimation_count--;
+ if (tsfm->decimation_count >= 0)
+ return 0;
+
+ for (n = 0; n < tsfm->tsf.count_coords; n++) {
+ /* give the coordinate result from summing median 3 */
+ coords[n] = tsfm->sort[n][tsfm->config->midpoint - 1] +
+ tsfm->sort[n][tsfm->config->midpoint] +
+ tsfm->sort[n][tsfm->config->midpoint + 1]
+ ;
+
+ movement += abs(tsfm->last_issued[n] - coords[n]);
+ }
+
+ if (movement > tsfm->config->decimation_threshold) /* fast */
+ tsfm->decimation_count = tsfm->config->decimation_above;
+ else
+ tsfm->decimation_count = tsfm->config->decimation_below;
+
+ memcpy(&tsfm->last_issued[0], coords,
+ tsfm->tsf.count_coords * sizeof(int));
+
+ if (tsf->next) /* chain */
+ return (tsf->next->api->process)(tsf->next, coords);
+
+ return 1;
+}
+
+struct ts_filter_api ts_filter_median_api = {
+ .create = ts_filter_median_create,
+ .destroy = ts_filter_median_destroy,
+ .clear = ts_filter_median_clear,
+ .process = ts_filter_median_process,
+ .scale = ts_filter_median_scale,
+};
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -107,4 +107,6 @@
source "drivers/xen/Kconfig"
source "drivers/staging/Kconfig"
+
+source "drivers/android/Kconfig"
endmenu
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -33,7 +33,7 @@
config LEDS_S3C24XX
tristate "LED Support for Samsung S3C24XX GPIO LEDs"
- depends on LEDS_CLASS && ARCH_S3C2410
+ depends on LEDS_CLASS && ARCH_S3C2410 && S3C2410_PWM
help
This option enables support for LEDs connected to GPIO lines
on Samsung S3C24XX series CPUs, such as the S3C2410 and S3C2440.
@@ -171,6 +171,18 @@
This option enables support for on-chip LED drivers found
on Dialog Semiconductor DA9030/DA9034 PMICs.
+config LEDS_NEO1973_VIBRATOR
+ tristate "Vibrator Support for the FIC Neo1973 GSM phone"
+ depends on LEDS_CLASS && MACH_NEO1973
+ help
+ This option enables support for the vibrator on the FIC Neo1973.
+
+config LEDS_NEO1973_GTA02
+ tristate "LED Support for the FIC Neo1973 (GTA02)"
+ depends on LEDS_CLASS && MACH_NEO1973_GTA02
+ help
+ This option enables support for the LEDs on the FIC Neo1973.
+
comment "LED Triggers"
config LEDS_TRIGGERS
--- a/drivers/leds/led-class.c
+++ b/drivers/leds/led-class.c
@@ -56,8 +56,10 @@
if (count == size) {
ret = count;
+#if 0 /* This is really bad. Don't do it!!!! */
if (state == LED_OFF)
led_trigger_remove(led_cdev);
+#endif
led_set_brightness(led_cdev, state);
}
--- /dev/null
+++ b/drivers/leds/leds-neo1973-gta02.c
@@ -0,0 +1,179 @@
+/*
+ * LED driver for the Openmoko GTA02 GSM phone
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <mach/gta02.h>
+#include <plat/regs-timer.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+
+#define MAX_LEDS 3
+#define COUNTER 256
+
+struct gta02_led_priv
+{
+ spinlock_t lock;
+ struct led_classdev cdev;
+ unsigned int gpio;
+};
+
+struct gta02_led_bundle
+{
+ int num_leds;
+ struct gta02_led_priv led[MAX_LEDS];
+};
+
+static inline struct gta02_led_priv *to_priv(struct led_classdev *led_cdev)
+{
+ return container_of(led_cdev, struct gta02_led_priv, cdev);
+}
+
+static inline struct gta02_led_bundle *to_bundle(struct led_classdev *led_cdev)
+{
+ return dev_get_drvdata(led_cdev->dev->parent);
+}
+
+static void gta02led_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+ unsigned long flags;
+ struct gta02_led_priv *lp = to_priv(led_cdev);
+
+ spin_lock_irqsave(&lp->lock, flags);
+ neo1973_gpb_setpin(lp->gpio, value ? 1 : 0);
+ spin_unlock_irqrestore(&lp->lock, flags);
+}
+
+#ifdef CONFIG_PM
+static int gta02led_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < bundle->num_leds; i++)
+ led_classdev_suspend(&bundle->led[i].cdev);
+
+ return 0;
+}
+
+static int gta02led_resume(struct platform_device *pdev)
+{
+ struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < bundle->num_leds; i++)
+ led_classdev_resume(&bundle->led[i].cdev);
+
+ return 0;
+}
+#endif
+
+static int __init gta02led_probe(struct platform_device *pdev)
+{
+ int i, rc;
+ struct gta02_led_bundle *bundle;
+
+ if (!machine_is_neo1973_gta02())
+ return -EIO;
+
+ bundle = kzalloc(sizeof(struct gta02_led_bundle), GFP_KERNEL);
+ if (!bundle)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, bundle);
+
+ for (i = 0; i < pdev->num_resources; i++) {
+ struct gta02_led_priv *lp;
+ struct resource *r;
+
+ if (i >= MAX_LEDS)
+ break;
+
+ r = platform_get_resource(pdev, 0, i);
+ if (!r || !r->start || !r->name)
+ continue;
+
+ lp = &bundle->led[i];
+
+ lp->gpio = r->start;
+ lp->cdev.name = r->name;
+ lp->cdev.brightness_set = gta02led_set;
+
+ switch (lp->gpio) {
+ case S3C2410_GPB0:
+ case S3C2410_GPB1:
+ case S3C2410_GPB2:
+ s3c2410_gpio_cfgpin(lp->gpio, S3C2410_GPIO_OUTPUT);
+ neo1973_gpb_add_shadow_gpio(lp->gpio);
+ break;
+ default:
+ break;
+ }
+
+ spin_lock_init(&lp->lock);
+ rc = led_classdev_register(&pdev->dev, &lp->cdev);
+ }
+
+ bundle->num_leds = i;
+
+ return 0;
+}
+
+static int gta02led_remove(struct platform_device *pdev)
+{
+ struct gta02_led_bundle *bundle = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < bundle->num_leds; i++) {
+ struct gta02_led_priv *lp = &bundle->led[i];
+ gta02led_set(&lp->cdev, 0);
+ led_classdev_unregister(&lp->cdev);
+ }
+
+ platform_set_drvdata(pdev, NULL);
+ kfree(bundle);
+
+ return 0;
+}
+
+static struct platform_driver gta02led_driver = {
+ .probe = gta02led_probe,
+ .remove = gta02led_remove,
+#ifdef CONFIG_PM
+ .suspend = gta02led_suspend,
+ .resume = gta02led_resume,
+#endif
+ .driver = {
+ .name = "gta02-led",
+ },
+};
+
+static int __init gta02led_init(void)
+{
+ return platform_driver_register(&gta02led_driver);
+}
+
+static void __exit gta02led_exit(void)
+{
+ platform_driver_unregister(&gta02led_driver);
+}
+
+module_init(gta02led_init);
+module_exit(gta02led_exit);
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("Openmoko GTA02 LED driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/leds/leds-neo1973-vibrator.c
@@ -0,0 +1,209 @@
+/*
+ * LED driver for the vibrator of the Openmoko GTA01/GTA02 GSM Phones
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Javi Roman <javiroman@kernel-labs.org>:
+ * Implement PWM support for GTA01Bv4 and later
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <mach/pwm.h>
+#include <mach/gta01.h>
+#include <plat/regs-timer.h>
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+#include <mach/fiq_ipc_gta02.h>
+#endif
+#include <asm/plat-s3c24xx/neo1973.h>
+
+#define COUNTER 64
+
+struct neo1973_vib_priv {
+ struct led_classdev cdev;
+ unsigned int gpio;
+ spinlock_t lock;
+ unsigned int has_pwm;
+ struct s3c2410_pwm pwm;
+};
+
+static void neo1973_vib_vib_set(struct led_classdev *led_cdev,
+ enum led_brightness value)
+{
+ unsigned long flags;
+ struct neo1973_vib_priv *vp = container_of(led_cdev,
+ struct neo1973_vib_priv,
+ cdev);
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ if (machine_is_neo1973_gta02()) { /* use FIQ to control GPIO */
+ fiq_ipc.vib_pwm = value; /* set it for FIQ */
+ fiq_kick(); /* start up FIQs if not already going */
+ return;
+ }
+#endif
+ /*
+ * value == 255 -> 99% duty cycle (full power)
+ * value == 128 -> 50% duty cycle (medium power)
+ * value == 0 -> 0% duty cycle (zero power)
+ */
+ spin_lock_irqsave(&vp->lock, flags);
+ if (vp->has_pwm) {
+ s3c2410_pwm_duty_cycle(value / 4, &vp->pwm);
+ }
+ else {
+ neo1973_gpb_setpin(vp->gpio, value ? 1 : 0);
+ }
+ spin_unlock_irqrestore(&vp->lock, flags);
+}
+
+static struct neo1973_vib_priv neo1973_vib_led = {
+ .cdev = {
+ .name = "neo1973:vibrator",
+ .brightness_set = neo1973_vib_vib_set,
+ },
+};
+
+static int neo1973_vib_init_hw(struct neo1973_vib_priv *vp)
+{
+ int rc;
+
+ rc = s3c2410_pwm_init(&vp->pwm);
+ if (rc)
+ return rc;
+
+ vp->pwm.timerid = PWM3;
+ /* use same prescaler as arch/arm/plat-s3c24xx/time.c */
+ vp->pwm.prescaler = (6 - 1) / 2;
+ vp->pwm.divider = S3C2410_TCFG1_MUX3_DIV2;
+ vp->pwm.counter = COUNTER;
+ vp->pwm.comparer = COUNTER;
+
+ rc = s3c2410_pwm_enable(&vp->pwm);
+ if (rc)
+ return rc;
+
+ s3c2410_pwm_start(&vp->pwm);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int neo1973_vib_suspend(struct platform_device *dev, pm_message_t state)
+{
+ led_classdev_suspend(&neo1973_vib_led.cdev);
+ return 0;
+}
+
+static int neo1973_vib_resume(struct platform_device *dev)
+{
+ struct neo1973_vib_priv *vp = platform_get_drvdata(dev);
+
+ if (vp->has_pwm)
+ neo1973_vib_init_hw(vp);
+
+ led_classdev_resume(&neo1973_vib_led.cdev);
+
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+static int __init neo1973_vib_probe(struct platform_device *pdev)
+{
+ struct resource *r;
+ int rc;
+
+ if (!machine_is_neo1973_gta01() && !machine_is_neo1973_gta02())
+ return -EIO;
+
+ r = platform_get_resource(pdev, 0, 0);
+ if (!r || !r->start)
+ return -EIO;
+
+ neo1973_vib_led.gpio = r->start;
+ platform_set_drvdata(pdev, &neo1973_vib_led);
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ if (machine_is_neo1973_gta02()) { /* use FIQ to control GPIO */
+ neo1973_gpb_setpin(neo1973_vib_led.gpio, 0); /* off */
+ s3c2410_gpio_cfgpin(neo1973_vib_led.gpio, S3C2410_GPIO_OUTPUT);
+ /* safe, kmalloc'd copy needed for FIQ ISR */
+ fiq_ipc.vib_gpio_pin = neo1973_vib_led.gpio;
+ fiq_ipc.vib_pwm = 0; /* off */
+ goto configured;
+ }
+#endif
+
+ /* TOUT3 */
+ if (neo1973_vib_led.gpio == S3C2410_GPB3) {
+ rc = neo1973_vib_init_hw(&neo1973_vib_led);
+ if (rc)
+ return rc;
+
+ s3c2410_pwm_duty_cycle(0, &neo1973_vib_led.pwm);
+ s3c2410_gpio_cfgpin(neo1973_vib_led.gpio, S3C2410_GPB3_TOUT3);
+ neo1973_vib_led.has_pwm = 1;
+ }
+#ifdef CONFIG_MACH_NEO1973_GTA02
+configured:
+#endif
+ spin_lock_init(&neo1973_vib_led.lock);
+
+ return led_classdev_register(&pdev->dev, &neo1973_vib_led.cdev);
+}
+
+static int neo1973_vib_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ if (machine_is_neo1973_gta02()) /* use FIQ to control GPIO */
+ fiq_ipc.vib_pwm = 0; /* off */
+ /* would only need kick if already off so no kick needed */
+#endif
+
+ if (neo1973_vib_led.has_pwm)
+ s3c2410_pwm_disable(&neo1973_vib_led.pwm);
+
+ led_classdev_unregister(&neo1973_vib_led.cdev);
+
+ return 0;
+}
+
+static struct platform_driver neo1973_vib_driver = {
+ .probe = neo1973_vib_probe,
+ .remove = neo1973_vib_remove,
+#ifdef CONFIG_PM
+ .suspend = neo1973_vib_suspend,
+ .resume = neo1973_vib_resume,
+#endif
+ .driver = {
+ .name = "neo1973-vibrator",
+ },
+};
+
+static int __init neo1973_vib_init(void)
+{
+ return platform_driver_register(&neo1973_vib_driver);
+}
+
+static void __exit neo1973_vib_exit(void)
+{
+ platform_driver_unregister(&neo1973_vib_driver);
+}
+
+module_init(neo1973_vib_init);
+module_exit(neo1973_vib_exit);
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("Openmoko GTA01/GTA02 vibrator driver");
+MODULE_LICENSE("GPL");
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -24,6 +24,8 @@
obj-$(CONFIG_LEDS_PCA955X) += leds-pca955x.o
obj-$(CONFIG_LEDS_DA903X) += leds-da903x.o
obj-$(CONFIG_LEDS_HP_DISK) += leds-hp-disk.o
+obj-$(CONFIG_LEDS_NEO1973_VIBRATOR) += leds-neo1973-vibrator.o
+obj-$(CONFIG_LEDS_NEO1973_GTA02) += leds-neo1973-gta02.o
# LED Triggers
obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -86,6 +86,7 @@
obj-y += idle/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_MEMSTICK) += memstick/
+obj-$(CONFIG_AR6000_WLAN) += ar6000/
obj-$(CONFIG_NEW_LEDS) += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_SGI_SN) += sn/
@@ -98,6 +99,7 @@
obj-$(CONFIG_HID) += hid/
obj-$(CONFIG_PPC_PS3) += ps3/
obj-$(CONFIG_OF) += of/
+obj-y += android/
obj-$(CONFIG_SSB) += ssb/
obj-$(CONFIG_VIRTIO) += virtio/
obj-$(CONFIG_REGULATOR) += regulator/
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-core.c
@@ -0,0 +1,1399 @@
+/* Smedia Glamo 336x/337x driver
+ *
+ * (C) 2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/wait.h>
+#include <linux/platform_device.h>
+#include <linux/kernel_stat.h>
+#include <linux/spinlock.h>
+#include <linux/glamofb.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/div64.h>
+
+//#include <mach/regs-irq.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#include "glamo-regs.h"
+#include "glamo-core.h"
+
+#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
+
+#define GLAMO_MEM_REFRESH_COUNT 0x100
+
+struct reg_range {
+ int start;
+ int count;
+ char *name;
+ char dump;
+};
+struct reg_range reg_range[] = {
+ { 0x0000, 0x76, "General", 1 },
+ { 0x0200, 0x16, "Host Bus", 1 },
+ { 0x0300, 0x38, "Memory", 1 },
+/* { 0x0400, 0x100, "Sensor", 0 }, */
+/* { 0x0500, 0x300, "ISP", 0 }, */
+/* { 0x0800, 0x400, "JPEG", 0 }, */
+/* { 0x0c00, 0xcc, "MPEG", 0 }, */
+ { 0x1100, 0xb2, "LCD 1", 1 },
+ { 0x1200, 0x64, "LCD 2", 1 },
+ { 0x1400, 0x40, "MMC", 1 },
+/* { 0x1500, 0x080, "MPU 0", 0 },
+ { 0x1580, 0x080, "MPU 1", 0 },
+ { 0x1600, 0x080, "Cmd Queue", 0 },
+ { 0x1680, 0x080, "RISC CPU", 0 },
+ { 0x1700, 0x400, "2D Unit", 0 },
+ { 0x1b00, 0x900, "3D Unit", 0 }, */
+};
+
+static struct glamo_core *glamo_handle;
+
+static inline void __reg_write(struct glamo_core *glamo,
+ u_int16_t reg, u_int16_t val)
+{
+ writew(val, glamo->base + reg);
+}
+
+static inline u_int16_t __reg_read(struct glamo_core *glamo,
+ u_int16_t reg)
+{
+ return readw(glamo->base + reg);
+}
+
+static void __reg_set_bit_mask(struct glamo_core *glamo,
+ u_int16_t reg, u_int16_t mask,
+ u_int16_t val)
+{
+ u_int16_t tmp;
+
+ val &= mask;
+
+ tmp = __reg_read(glamo, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ __reg_write(glamo, reg, tmp);
+}
+
+static void reg_set_bit_mask(struct glamo_core *glamo,
+ u_int16_t reg, u_int16_t mask,
+ u_int16_t val)
+{
+ spin_lock(&glamo->lock);
+ __reg_set_bit_mask(glamo, reg, mask, val);
+ spin_unlock(&glamo->lock);
+}
+
+static inline void __reg_set_bit(struct glamo_core *glamo,
+ u_int16_t reg, u_int16_t bit)
+{
+ __reg_set_bit_mask(glamo, reg, bit, 0xffff);
+}
+
+static inline void __reg_clear_bit(struct glamo_core *glamo,
+ u_int16_t reg, u_int16_t bit)
+{
+ __reg_set_bit_mask(glamo, reg, bit, 0);
+}
+
+static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
+ u_int16_t *src, int len)
+{
+ if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
+ dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
+ "0x%x)!!\n", addr, src, len);
+ }
+
+}
+
+static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
+ u_int32_t addr, int len)
+{
+ if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
+ dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
+ "0x%x)!!\n", buf, addr, len);
+ }
+
+
+}
+
+/***********************************************************************
+ * resources of sibling devices
+ ***********************************************************************/
+
+#if 0
+static struct resource glamo_core_resources[] = {
+ {
+ .start = GLAMO_REGOFS_GENERIC,
+ .end = GLAMO_REGOFS_GENERIC + 0x400,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device glamo_core_dev = {
+ .name = "glamo-core",
+ .resource = &glamo_core_resources,
+ .num_resources = ARRAY_SIZE(glamo_core_resources),
+};
+#endif
+
+static struct resource glamo_jpeg_resources[] = {
+ {
+ .start = GLAMO_REGOFS_JPEG,
+ .end = GLAMO_REGOFS_MPEG - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_GLAMO_JPEG,
+ .end = IRQ_GLAMO_JPEG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device glamo_jpeg_dev = {
+ .name = "glamo-jpeg",
+ .resource = glamo_jpeg_resources,
+ .num_resources = ARRAY_SIZE(glamo_jpeg_resources),
+};
+
+static struct resource glamo_mpeg_resources[] = {
+ {
+ .start = GLAMO_REGOFS_MPEG,
+ .end = GLAMO_REGOFS_LCD - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_GLAMO_MPEG,
+ .end = IRQ_GLAMO_MPEG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device glamo_mpeg_dev = {
+ .name = "glamo-mpeg",
+ .resource = glamo_mpeg_resources,
+ .num_resources = ARRAY_SIZE(glamo_mpeg_resources),
+};
+
+static struct resource glamo_2d_resources[] = {
+ {
+ .start = GLAMO_REGOFS_2D,
+ .end = GLAMO_REGOFS_3D - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_GLAMO_2D,
+ .end = IRQ_GLAMO_2D,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device glamo_2d_dev = {
+ .name = "glamo-2d",
+ .resource = glamo_2d_resources,
+ .num_resources = ARRAY_SIZE(glamo_2d_resources),
+};
+
+static struct resource glamo_3d_resources[] = {
+ {
+ .start = GLAMO_REGOFS_3D,
+ .end = GLAMO_REGOFS_END - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device glamo_3d_dev = {
+ .name = "glamo-3d",
+ .resource = glamo_3d_resources,
+ .num_resources = ARRAY_SIZE(glamo_3d_resources),
+};
+
+static struct platform_device glamo_spigpio_dev = {
+ .name = "glamo-spi-gpio",
+};
+
+static struct resource glamo_fb_resources[] = {
+ /* FIXME: those need to be incremented by parent base */
+ {
+ .name = "glamo-fb-regs",
+ .start = GLAMO_REGOFS_LCD,
+ .end = GLAMO_REGOFS_MMC - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "glamo-fb-mem",
+ .start = GLAMO_OFFSET_FB,
+ .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device glamo_fb_dev = {
+ .name = "glamo-fb",
+ .resource = glamo_fb_resources,
+ .num_resources = ARRAY_SIZE(glamo_fb_resources),
+};
+
+static struct resource glamo_mmc_resources[] = {
+ {
+ /* FIXME: those need to be incremented by parent base */
+ .start = GLAMO_REGOFS_MMC,
+ .end = GLAMO_REGOFS_MPROC0 - 1,
+ .flags = IORESOURCE_MEM
+ }, {
+ .start = IRQ_GLAMO_MMC,
+ .end = IRQ_GLAMO_MMC,
+ .flags = IORESOURCE_IRQ,
+ }, { /* our data buffer for MMC transfers */
+ .start = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
+ .end = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
+ GLAMO_MMC_BUFFER_SIZE - 1,
+ .flags = IORESOURCE_MEM
+ },
+};
+
+struct glamo_mci_pdata glamo_mci_def_pdata = {
+ .gpio_detect = 0,
+ .glamo_can_set_mci_power = NULL, /* filled in from MFD platform data */
+ .ocr_avail = MMC_VDD_20_21 |
+ MMC_VDD_21_22 |
+ MMC_VDD_22_23 |
+ MMC_VDD_23_24 |
+ MMC_VDD_24_25 |
+ MMC_VDD_25_26 |
+ MMC_VDD_26_27 |
+ MMC_VDD_27_28 |
+ MMC_VDD_28_29 |
+ MMC_VDD_29_30 |
+ MMC_VDD_30_31 |
+ MMC_VDD_32_33,
+ .glamo_irq_is_wired = NULL, /* filled in from MFD platform data */
+ .mci_suspending = NULL, /* filled in from MFD platform data */
+ .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
+};
+EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
+
+
+
+static void mangle_mem_resources(struct resource *res, int num_res,
+ struct resource *parent)
+{
+ int i;
+
+ for (i = 0; i < num_res; i++) {
+ if (res[i].flags != IORESOURCE_MEM)
+ continue;
+ res[i].start += parent->start;
+ res[i].end += parent->start;
+ res[i].parent = parent;
+ }
+}
+
+/***********************************************************************
+ * IRQ demultiplexer
+ ***********************************************************************/
+#define irq2glamo(x) (x - IRQ_GLAMO(0))
+
+static void glamo_ack_irq(unsigned int irq)
+{
+ /* clear interrupt source */
+ __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
+ 1 << irq2glamo(irq));
+}
+
+static void glamo_mask_irq(unsigned int irq)
+{
+ u_int16_t tmp;
+
+ /* clear bit in enable register */
+ tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
+ tmp &= ~(1 << irq2glamo(irq));
+ __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
+}
+
+static void glamo_unmask_irq(unsigned int irq)
+{
+ u_int16_t tmp;
+
+ /* set bit in enable register */
+ tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
+ tmp |= (1 << irq2glamo(irq));
+ __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
+}
+
+static struct irq_chip glamo_irq_chip = {
+ .ack = glamo_ack_irq,
+ .mask = glamo_mask_irq,
+ .unmask = glamo_unmask_irq,
+};
+
+static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+ const unsigned int cpu = smp_processor_id();
+
+ desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
+
+ if (unlikely(desc->status & IRQ_INPROGRESS)) {
+ desc->status |= (IRQ_PENDING | IRQ_MASKED);
+ desc->chip->mask(irq);
+ desc->chip->ack(irq);
+ return;
+ }
+
+ kstat_cpu(cpu).irqs[irq]++;
+ desc->chip->ack(irq);
+ desc->status |= IRQ_INPROGRESS;
+
+ do {
+ u_int16_t irqstatus;
+ int i;
+
+ if (unlikely((desc->status &
+ (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
+ (IRQ_PENDING | IRQ_MASKED))) {
+ /* dealing with pending IRQ, unmasking */
+ desc->chip->unmask(irq);
+ desc->status &= ~IRQ_MASKED;
+ }
+
+ desc->status &= ~IRQ_PENDING;
+
+ /* read IRQ status register */
+ irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
+ for (i = 0; i < 9; i++)
+ if (irqstatus & (1 << i))
+ desc_handle_irq(IRQ_GLAMO(i),
+ irq_desc+IRQ_GLAMO(i));
+
+ } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
+
+ desc->status &= ~IRQ_INPROGRESS;
+}
+
+
+static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long reg = simple_strtoul(buf, NULL, 10);
+ struct glamo_core *glamo = dev_get_drvdata(dev);
+
+ while (*buf && (*buf != ' '))
+ buf++;
+ if (*buf != ' ')
+ return -EINVAL;
+ while (*buf && (*buf == ' '))
+ buf++;
+ if (!*buf)
+ return -EINVAL;
+
+ printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
+ reg, simple_strtoul(buf, NULL, 10));
+
+ __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
+
+ return count;
+}
+
+static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct glamo_core *glamo = dev_get_drvdata(dev);
+ int n, n1 = 0, r;
+ char * end = buf;
+
+ spin_lock(&glamo->lock);
+
+ for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
+ if (!reg_range[r].dump)
+ continue;
+ n1 = 0;
+ end += sprintf(end, "\n%s\n", reg_range[r].name);
+ for (n = reg_range[r].start;
+ n < reg_range[r].start + reg_range[r].count; n += 2) {
+ if (((n1++) & 7) == 0)
+ end += sprintf(end, "\n%04X: ", n);
+ end += sprintf(end, "%04x ", __reg_read(glamo, n));
+ }
+ end += sprintf(end, "\n");
+ if (!attr) {
+ printk("%s", buf);
+ end = buf;
+ }
+ }
+ spin_unlock(&glamo->lock);
+
+ return end - buf;
+}
+
+static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
+static struct attribute *glamo_sysfs_entries[] = {
+ &dev_attr_regs.attr,
+ NULL
+};
+static struct attribute_group glamo_attr_group = {
+ .name = NULL,
+ .attrs = glamo_sysfs_entries,
+};
+
+
+
+/***********************************************************************
+ * 'engine' support
+ ***********************************************************************/
+
+int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ switch (engine) {
+ case GLAMO_ENGINE_LCD:
+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
+ GLAMO_HOSTBUS2_MMIO_EN_LCD,
+ GLAMO_HOSTBUS2_MMIO_EN_LCD);
+ __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
+ GLAMO_CLOCK_LCD_EN_M5CLK |
+ GLAMO_CLOCK_LCD_EN_DHCLK |
+ GLAMO_CLOCK_LCD_EN_DMCLK |
+ GLAMO_CLOCK_LCD_EN_DCLK |
+ GLAMO_CLOCK_LCD_DG_M5CLK |
+ GLAMO_CLOCK_LCD_DG_DMCLK);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
+ GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
+ GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
+ break;
+ case GLAMO_ENGINE_MMC:
+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
+ GLAMO_HOSTBUS2_MMIO_EN_MMC,
+ GLAMO_HOSTBUS2_MMIO_EN_MMC);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
+ GLAMO_CLOCK_MMC_EN_M9CLK |
+ GLAMO_CLOCK_MMC_EN_TCLK |
+ GLAMO_CLOCK_MMC_DG_M9CLK |
+ GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
+ /* enable the TCLK divider clk input */
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
+ GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
+ break;
+ case GLAMO_ENGINE_2D:
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
+ GLAMO_CLOCK_2D_EN_M7CLK |
+ GLAMO_CLOCK_2D_EN_GCLK |
+ GLAMO_CLOCK_2D_DG_M7CLK |
+ GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
+ GLAMO_HOSTBUS2_MMIO_EN_2D,
+ GLAMO_HOSTBUS2_MMIO_EN_2D);
+ break;
+ case GLAMO_ENGINE_CMDQ:
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
+ GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
+ __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
+ GLAMO_HOSTBUS2_MMIO_EN_CQ,
+ GLAMO_HOSTBUS2_MMIO_EN_CQ);
+ break;
+ /* FIXME: Implementation */
+ default:
+ break;
+ }
+
+ glamo->engine_enabled_bitfield |= 1 << engine;
+
+ return 0;
+}
+
+int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ int ret;
+
+ spin_lock(&glamo->lock);
+
+ ret = __glamo_engine_enable(glamo, engine);
+
+ spin_unlock(&glamo->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(glamo_engine_enable);
+
+int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ switch (engine) {
+ case GLAMO_ENGINE_LCD:
+ /* remove pixel clock to LCM */
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
+ GLAMO_CLOCK_LCD_EN_DCLK, 0);
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
+ GLAMO_CLOCK_LCD_EN_DHCLK |
+ GLAMO_CLOCK_LCD_EN_DMCLK, 0);
+ /* kill memory clock */
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
+ GLAMO_CLOCK_LCD_EN_M5CLK, 0);
+ /* stop dividing the clocks */
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+ GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
+ GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
+ GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
+ break;
+
+ case GLAMO_ENGINE_MMC:
+// __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
+// GLAMO_CLOCK_MMC_EN_M9CLK |
+// GLAMO_CLOCK_MMC_EN_TCLK |
+// GLAMO_CLOCK_MMC_DG_M9CLK |
+// GLAMO_CLOCK_MMC_DG_TCLK, 0);
+ /* disable the TCLK divider clk input */
+// __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
+// GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
+
+ default:
+ break;
+ }
+
+ glamo->engine_enabled_bitfield &= ~(1 << engine);
+
+ return 0;
+}
+int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ int ret;
+
+ spin_lock(&glamo->lock);
+
+ ret = __glamo_engine_disable(glamo, engine);
+
+ spin_unlock(&glamo->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(glamo_engine_disable);
+
+static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
+ [GLAMO_ENGINE_LCD] = GLAMO_REG_CLOCK_LCD,
+ [GLAMO_ENGINE_MMC] = GLAMO_REG_CLOCK_MMC,
+ [GLAMO_ENGINE_ISP] = GLAMO_REG_CLOCK_ISP,
+ [GLAMO_ENGINE_JPEG] = GLAMO_REG_CLOCK_JPEG,
+ [GLAMO_ENGINE_3D] = GLAMO_REG_CLOCK_3D,
+ [GLAMO_ENGINE_2D] = GLAMO_REG_CLOCK_2D,
+ [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
+ [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
+};
+
+void glamo_engine_clkreg_set(struct glamo_core *glamo,
+ enum glamo_engine engine,
+ u_int16_t mask, u_int16_t val)
+{
+ reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
+}
+EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
+
+u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
+ enum glamo_engine engine)
+{
+ u_int16_t val;
+
+ spin_lock(&glamo->lock);
+ val = __reg_read(glamo, engine_clock_regs[engine]);
+ spin_unlock(&glamo->lock);
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
+
+struct glamo_script reset_regs[] = {
+ [GLAMO_ENGINE_LCD] = {
+ GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
+ },
+#if 0
+ [GLAMO_ENGINE_HOST] = {
+ GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
+ },
+ [GLAMO_ENGINE_MEM] = {
+ GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
+ },
+#endif
+ [GLAMO_ENGINE_MMC] = {
+ GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
+ },
+ [GLAMO_ENGINE_2D] = {
+ GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
+ },
+ [GLAMO_ENGINE_JPEG] = {
+ GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
+ },
+};
+
+void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
+{
+ struct glamo_script *rst;
+
+ if (engine >= ARRAY_SIZE(reset_regs)) {
+ dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
+ return;
+ }
+
+ rst = &reset_regs[engine];
+
+ spin_lock(&glamo->lock);
+ __reg_set_bit(glamo, rst->reg, rst->val);
+ __reg_clear_bit(glamo, rst->reg, rst->val);
+ spin_unlock(&glamo->lock);
+}
+EXPORT_SYMBOL_GPL(glamo_engine_reset);
+
+void glamo_lcm_reset(int level)
+{
+ if (!glamo_handle)
+ return;
+
+ glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
+ glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
+
+}
+EXPORT_SYMBOL_GPL(glamo_lcm_reset);
+
+enum glamo_pll {
+ GLAMO_PLL1,
+ GLAMO_PLL2,
+};
+
+static int glamo_pll_rate(struct glamo_core *glamo,
+ enum glamo_pll pll)
+{
+ u_int16_t reg;
+ unsigned int div = 512;
+ /* FIXME: move osci into platform_data */
+ unsigned int osci = 32768;
+
+ if (osci == 32768)
+ div = 1;
+
+ switch (pll) {
+ case GLAMO_PLL1:
+ reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
+ break;
+ case GLAMO_PLL2:
+ reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return (osci/div)*reg;
+}
+
+int glamo_engine_reclock(struct glamo_core *glamo,
+ enum glamo_engine engine,
+ int ps)
+{
+ int pll, khz;
+ u_int16_t reg, mask, val = 0;
+
+ if (!ps)
+ return 0;
+
+ switch (engine) {
+ case GLAMO_ENGINE_LCD:
+ pll = GLAMO_PLL1;
+ reg = GLAMO_REG_CLOCK_GEN7;
+ mask = 0xff;
+ break;
+ default:
+ dev_warn(&glamo->pdev->dev,
+ "reclock of engine 0x%x not supported\n", engine);
+ return -EINVAL;
+ break;
+ }
+
+ pll = glamo_pll_rate(glamo, pll);
+ khz = 1000000000UL / ps;
+
+ if (khz)
+ val = (pll / khz) / 1000;
+
+ dev_dbg(&glamo->pdev->dev,
+ "PLL %d, kHZ %d, div %d\n", pll, khz, val);
+
+ if (val) {
+ val--;
+ reg_set_bit_mask(glamo, reg, mask, val);
+ mdelay(5); /* wait some time to stabilize */
+
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+}
+EXPORT_SYMBOL_GPL(glamo_engine_reclock);
+
+/***********************************************************************
+ * script support
+ ***********************************************************************/
+
+int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
+ int len, int may_sleep)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ struct glamo_script *line = &script[i];
+
+ switch (line->reg) {
+ case 0xffff:
+ return 0;
+ case 0xfffe:
+ if (may_sleep)
+ msleep(line->val);
+ else
+ mdelay(line->val * 4);
+ break;
+ case 0xfffd:
+ /* spin until PLLs lock */
+ while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
+ ;
+ break;
+ default:
+ __reg_write(glamo, script[i].reg, script[i].val);
+ break;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(glamo_run_script);
+
+static struct glamo_script glamo_init_script[] = {
+ { GLAMO_REG_CLOCK_HOST, 0x1000 },
+ { 0xfffe, 2 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x1000 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x2000 },
+ { GLAMO_REG_CLOCK_LCD, 0x1000 },
+ { GLAMO_REG_CLOCK_MMC, 0x1000 },
+ { GLAMO_REG_CLOCK_ISP, 0x1000 },
+ { GLAMO_REG_CLOCK_ISP, 0x3000 },
+ { GLAMO_REG_CLOCK_JPEG, 0x1000 },
+ { GLAMO_REG_CLOCK_3D, 0x1000 },
+ { GLAMO_REG_CLOCK_3D, 0x3000 },
+ { GLAMO_REG_CLOCK_2D, 0x1000 },
+ { GLAMO_REG_CLOCK_2D, 0x3000 },
+ { GLAMO_REG_CLOCK_RISC1, 0x1000 },
+ { GLAMO_REG_CLOCK_MPEG, 0x3000 },
+ { GLAMO_REG_CLOCK_MPEG, 0x3000 },
+ { GLAMO_REG_CLOCK_MPROC, 0x1000 /*0x100f*/ },
+ { 0xfffe, 2 },
+ { GLAMO_REG_CLOCK_HOST, 0x0000 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x0000 },
+ { GLAMO_REG_CLOCK_LCD, 0x0000 },
+ { GLAMO_REG_CLOCK_MMC, 0x0000 },
+#if 0
+/* unused engines must be left in reset to stop MMC block read "blackouts" */
+ { GLAMO_REG_CLOCK_ISP, 0x0000 },
+ { GLAMO_REG_CLOCK_ISP, 0x0000 },
+ { GLAMO_REG_CLOCK_JPEG, 0x0000 },
+ { GLAMO_REG_CLOCK_3D, 0x0000 },
+ { GLAMO_REG_CLOCK_3D, 0x0000 },
+ { GLAMO_REG_CLOCK_2D, 0x0000 },
+ { GLAMO_REG_CLOCK_2D, 0x0000 },
+ { GLAMO_REG_CLOCK_RISC1, 0x0000 },
+ { GLAMO_REG_CLOCK_MPEG, 0x0000 },
+ { GLAMO_REG_CLOCK_MPEG, 0x0000 },
+#endif
+ { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
+ { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
+ { 0xfffd, 0 },
+ /*
+ * b9 of this register MUST be zero to get any interrupts on INT#
+ * the other set bits enable all the engine interrupt sources
+ */
+ { GLAMO_REG_IRQ_ENABLE, 0x01ff },
+ { GLAMO_REG_CLOCK_GEN6, 0x2000 },
+ { GLAMO_REG_CLOCK_GEN7, 0x0101 },
+ { GLAMO_REG_CLOCK_GEN8, 0x0100 },
+ { GLAMO_REG_CLOCK_HOST, 0x000d },
+ /*
+ * b7..b4 = 0 = no wait states on read or write
+ * b0 = 1 select PLL2 for Host interface, b1 = enable it
+ */
+ { 0x200, 0x0e03 },
+ { 0x202, 0x07ff },
+ { 0x212, 0x0000 },
+ { 0x214, 0x4000 },
+ { 0x216, 0xf00e },
+
+ /* S-Media recommended "set tiling mode to 512 mode for memory access
+ * more efficiency when 640x480" */
+ { GLAMO_REG_MEM_TYPE, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
+ { GLAMO_REG_MEM_GEN, 0xafaf }, /* 63 grants min + max */
+
+ { GLAMO_REGOFS_HOSTBUS + 2, 0xffff }, /* enable on MMIO*/
+
+ { GLAMO_REG_MEM_TIMING1, 0x0108 },
+ { GLAMO_REG_MEM_TIMING2, 0x0010 }, /* Taa = 3 MCLK */
+ { GLAMO_REG_MEM_TIMING3, 0x0000 },
+ { GLAMO_REG_MEM_TIMING4, 0x0000 }, /* CE1# delay fall/rise */
+ { GLAMO_REG_MEM_TIMING5, 0x0000 }, /* UB# LB# */
+ { GLAMO_REG_MEM_TIMING6, 0x0000 }, /* OE# */
+ { GLAMO_REG_MEM_TIMING7, 0x0000 }, /* WE# */
+ { GLAMO_REG_MEM_TIMING8, 0x1002 }, /* MCLK delay, was 0x1000 */
+ { GLAMO_REG_MEM_TIMING9, 0x6006 },
+ { GLAMO_REG_MEM_TIMING10, 0x00ff },
+ { GLAMO_REG_MEM_TIMING11, 0x0001 },
+ { GLAMO_REG_MEM_POWER1, 0x0020 },
+ { GLAMO_REG_MEM_POWER2, 0x0000 },
+ { GLAMO_REG_MEM_DRAM1, 0x0000 },
+ { 0xfffe, 1 },
+ { GLAMO_REG_MEM_DRAM1, 0xc100 },
+ { 0xfffe, 1 },
+ { GLAMO_REG_MEM_DRAM1, 0xe100 },
+ { GLAMO_REG_MEM_DRAM2, 0x01d6 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x000b },
+ { GLAMO_REG_GPIO_GEN1, 0x000f },
+ { GLAMO_REG_GPIO_GEN2, 0x111e },
+ { GLAMO_REG_GPIO_GEN3, 0xccc3 },
+ { GLAMO_REG_GPIO_GEN4, 0x111e },
+ { GLAMO_REG_GPIO_GEN5, 0x000f },
+};
+#if 0
+static struct glamo_script glamo_resume_script[] = {
+
+ { GLAMO_REG_PLL_GEN1, 0x05db }, /* 48MHz */
+ { GLAMO_REG_PLL_GEN3, 0x0aba }, /* 90MHz */
+ { GLAMO_REG_DFT_GEN6, 1 },
+ { 0xfffe, 100 },
+ { 0xfffd, 0 },
+ { 0x200, 0x0e03 },
+
+ /*
+ * b9 of this register MUST be zero to get any interrupts on INT#
+ * the other set bits enable all the engine interrupt sources
+ */
+ { GLAMO_REG_IRQ_ENABLE, 0x01ff },
+ { GLAMO_REG_CLOCK_HOST, 0x0018 },
+ { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
+
+ { GLAMO_REG_MEM_DRAM1, 0x0000 },
+ { 0xfffe, 1 },
+ { GLAMO_REG_MEM_DRAM1, 0xc100 },
+ { 0xfffe, 1 },
+ { GLAMO_REG_MEM_DRAM1, 0xe100 },
+ { GLAMO_REG_MEM_DRAM2, 0x01d6 },
+ { GLAMO_REG_CLOCK_MEMORY, 0x000b },
+};
+#endif
+
+enum glamo_power {
+ GLAMO_POWER_ON,
+ GLAMO_POWER_SUSPEND,
+};
+
+static void glamo_power(struct glamo_core *glamo,
+ enum glamo_power new_state)
+{
+ int n;
+ unsigned long flags;
+
+ spin_lock_irqsave(&glamo->lock, flags);
+
+ dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
+
+ /*
+Power management
+static const REG_VALUE_MASK_TYPE reg_powerOn[] =
+{
+ { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
+ { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
+ { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
+ { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
+ { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
+};
+
+static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
+{
+ { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
+ { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
+ { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
+ { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
+};
+
+static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
+{
+ { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
+ { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
+ { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
+ { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
+};
+*/
+
+ switch (new_state) {
+ case GLAMO_POWER_ON:
+
+ /*
+ * glamo state on resume is nondeterministic in some
+ * fundamental way, it has also been observed that the
+ * Glamo reset pin can get asserted by, eg, touching it with
+ * a scope probe. So the only answer is to roll with it and
+ * force an external reset on the Glamo during resume.
+ */
+
+ (glamo->pdata->glamo_external_reset)(0);
+ udelay(10);
+ (glamo->pdata->glamo_external_reset)(1);
+ mdelay(5);
+
+ glamo_run_script(glamo, glamo_init_script,
+ ARRAY_SIZE(glamo_init_script), 0);
+
+ break;
+
+ case GLAMO_POWER_SUSPEND:
+
+ /* nuke interrupts */
+ __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
+
+ /* stash a copy of which engines were running */
+ glamo->engine_enabled_bitfield_suspend =
+ glamo->engine_enabled_bitfield;
+
+ /* take down each engine before we kill mem and pll */
+ for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
+ if (glamo->engine_enabled_bitfield & (1 << n))
+ __glamo_engine_disable(glamo, n);
+
+ /* enable self-refresh */
+
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
+ GLAMO_MEM_DRAM1_EN_GATE_CKE |
+ GLAMO_MEM_DRAM1_SELF_REFRESH |
+ GLAMO_MEM_REFRESH_COUNT);
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
+ GLAMO_MEM_DRAM1_EN_MODEREG_SET |
+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
+ GLAMO_MEM_DRAM1_EN_GATE_CKE |
+ GLAMO_MEM_DRAM1_SELF_REFRESH |
+ GLAMO_MEM_REFRESH_COUNT);
+
+ /* force RAM into deep powerdown */
+
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
+ GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
+ (7 << 6) | /* tRC */
+ (1 << 4) | /* tRP */
+ (1 << 2) | /* tRCD */
+ 2); /* CAS latency */
+
+ /* disable clocks to memory */
+ __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
+
+ /* all dividers from OSCI */
+ __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
+
+ /* PLL2 into bypass */
+ __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
+
+ __reg_write(glamo, 0x200, 0x0e00);
+
+
+ /* kill PLLS 1 then 2 */
+ __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
+ __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
+
+ break;
+ }
+
+ spin_unlock_irqrestore(&glamo->lock, flags);
+}
+
+#if 0
+#define MEMDETECT_RETRY 6
+static unsigned int detect_memsize(struct glamo_core *glamo)
+{
+ int i;
+
+ /*static const u_int16_t pattern[] = {
+ 0x1111, 0x8a8a, 0x2222, 0x7a7a,
+ 0x3333, 0x6a6a, 0x4444, 0x5a5a,
+ 0x5555, 0x4a4a, 0x6666, 0x3a3a,
+ 0x7777, 0x2a2a, 0x8888, 0x1a1a
+ }; */
+
+ for (i = 0; i < MEMDETECT_RETRY; i++) {
+ switch (glamo->type) {
+ case 3600:
+ __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
+ break;
+ case 3650:
+ switch (glamo->revision) {
+ case GLAMO_CORE_REV_A0:
+ if (i & 1)
+ __reg_write(glamo, GLAMO_REG_MEM_TYPE,
+ 0x097a);
+ else
+ __reg_write(glamo, GLAMO_REG_MEM_TYPE,
+ 0x0173);
+
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
+ msleep(1);
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
+ break;
+ default:
+ if (i & 1)
+ __reg_write(glamo, GLAMO_REG_MEM_TYPE,
+ 0x0972);
+ else
+ __reg_write(glamo, GLAMO_REG_MEM_TYPE,
+ 0x0872);
+
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
+ msleep(1);
+ __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
+ break;
+ }
+ break;
+ case 3700:
+ /* FIXME */
+ default:
+ break;
+ }
+
+#if 0
+ /* FIXME: finish implementation */
+ for (j = 0; j < 8; j++) {
+ __
+#endif
+ }
+
+ return 0;
+}
+#endif
+
+/* Find out if we can support this version of the Glamo chip */
+static int glamo_supported(struct glamo_core *glamo)
+{
+ u_int16_t dev_id, rev_id; /*, memsize; */
+
+ dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
+ rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
+
+ switch (dev_id) {
+ case 0x3650:
+ switch (rev_id) {
+ case GLAMO_CORE_REV_A2:
+ break;
+ case GLAMO_CORE_REV_A0:
+ case GLAMO_CORE_REV_A1:
+ case GLAMO_CORE_REV_A3:
+ dev_warn(&glamo->pdev->dev, "untested core revision "
+ "%04x, your mileage may vary\n", rev_id);
+ break;
+ default:
+ dev_warn(&glamo->pdev->dev, "unknown glamo revision "
+ "%04x, your mileage may vary\n", rev_id);
+ /* maybe should abort ? */
+ }
+ break;
+ case 0x3600:
+ case 0x3700:
+ default:
+ dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
+ dev_id);
+ return 0;
+ }
+
+ dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
+ "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
+ glamo_pll_rate(glamo, GLAMO_PLL1),
+ glamo_pll_rate(glamo, GLAMO_PLL2));
+
+ return 1;
+}
+
+static int __init glamo_probe(struct platform_device *pdev)
+{
+ int rc = 0, irq;
+ struct glamo_core *glamo;
+ struct platform_device *glamo_mmc_dev;
+
+ if (glamo_handle) {
+ dev_err(&pdev->dev,
+ "This driver supports only one instance\n");
+ return -EBUSY;
+ }
+
+ glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
+ if (!glamo)
+ return -ENOMEM;
+
+ spin_lock_init(&glamo->lock);
+ glamo_handle = glamo;
+ glamo->pdev = pdev;
+ glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ glamo->irq = platform_get_irq(pdev, 0);
+ glamo->pdata = pdev->dev.platform_data;
+ if (!glamo->mem || !glamo->pdata) {
+ dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
+ rc = -ENOENT;
+ goto bail_free;
+ }
+
+ /* register a number of sibling devices whoise IOMEM resources
+ * are siblings of pdev's IOMEM resource */
+#if 0
+ glamo_core_dev.dev.parent = &pdev.dev;
+ mangle_mem_resources(glamo_core_dev.resources,
+ glamo_core_dev.num_resources, glamo->mem);
+ glamo_core_dev.resources[1].start = glamo->irq;
+ glamo_core_dev.resources[1].end = glamo->irq;
+ platform_device_register(&glamo_core_dev);
+#endif
+ /* only remap the generic, hostbus and memory controller registers */
+ glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
+ if (!glamo->base) {
+ dev_err(&pdev->dev, "failed to ioremap() memory region\n");
+ goto bail_free;
+ }
+
+ platform_set_drvdata(pdev, glamo);
+
+ (glamo->pdata->glamo_external_reset)(0);
+ udelay(10);
+ (glamo->pdata->glamo_external_reset)(1);
+ mdelay(10);
+
+ /*
+ * finally set the mfd interrupts up
+ * can't do them earlier or sibling probes blow up
+ */
+
+ for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
+ set_irq_chip(irq, &glamo_irq_chip);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+
+ if (glamo->pdata->glamo_irq_is_wired &&
+ !glamo->pdata->glamo_irq_is_wired()) {
+ set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
+ set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
+ dev_info(&pdev->dev, "Glamo interrupt registered\n");
+ glamo->irq_works = 1;
+ } else {
+ dev_err(&pdev->dev, "Glamo interrupt not used\n");
+ glamo->irq_works = 0;
+ }
+
+
+ /* confirm it isn't insane version */
+ if (!glamo_supported(glamo)) {
+ dev_err(&pdev->dev, "This Glamo is not supported\n");
+ goto bail_irq;
+ }
+
+ /* sysfs */
+ rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "cannot create sysfs group\n");
+ goto bail_irq;
+ }
+
+ /* init the chip with canned register set */
+
+ dev_dbg(&glamo->pdev->dev, "running init script\n");
+ glamo_run_script(glamo, glamo_init_script,
+ ARRAY_SIZE(glamo_init_script), 1);
+
+ dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
+ glamo_pll_rate(glamo, GLAMO_PLL1),
+ glamo_pll_rate(glamo, GLAMO_PLL2));
+
+ /* bring MCI specific stuff over from our MFD platform data */
+ glamo_mci_def_pdata.glamo_can_set_mci_power =
+ glamo->pdata->glamo_can_set_mci_power;
+ glamo_mci_def_pdata.glamo_mci_use_slow =
+ glamo->pdata->glamo_mci_use_slow;
+ glamo_mci_def_pdata.glamo_irq_is_wired =
+ glamo->pdata->glamo_irq_is_wired;
+
+ /* start creating the siblings */
+
+ glamo_2d_dev.dev.parent = &pdev->dev;
+ mangle_mem_resources(glamo_2d_dev.resource,
+ glamo_2d_dev.num_resources, glamo->mem);
+ platform_device_register(&glamo_2d_dev);
+
+ glamo_3d_dev.dev.parent = &pdev->dev;
+ mangle_mem_resources(glamo_3d_dev.resource,
+ glamo_3d_dev.num_resources, glamo->mem);
+ platform_device_register(&glamo_3d_dev);
+
+ glamo_jpeg_dev.dev.parent = &pdev->dev;
+ mangle_mem_resources(glamo_jpeg_dev.resource,
+ glamo_jpeg_dev.num_resources, glamo->mem);
+ platform_device_register(&glamo_jpeg_dev);
+
+ glamo_mpeg_dev.dev.parent = &pdev->dev;
+ mangle_mem_resources(glamo_mpeg_dev.resource,
+ glamo_mpeg_dev.num_resources, glamo->mem);
+ platform_device_register(&glamo_mpeg_dev);
+
+ glamo->pdata->glamo = glamo;
+ glamo_fb_dev.dev.parent = &pdev->dev;
+ glamo_fb_dev.dev.platform_data = glamo->pdata;
+ mangle_mem_resources(glamo_fb_dev.resource,
+ glamo_fb_dev.num_resources, glamo->mem);
+ platform_device_register(&glamo_fb_dev);
+
+ glamo->pdata->spigpio_info->glamo = glamo;
+ glamo_spigpio_dev.dev.parent = &pdev->dev;
+ glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
+ platform_device_register(&glamo_spigpio_dev);
+
+ glamo_mmc_dev = glamo->pdata->mmc_dev;
+ glamo_mmc_dev->name = "glamo-mci";
+ glamo_mmc_dev->dev.parent = &pdev->dev;
+ glamo_mmc_dev->resource = glamo_mmc_resources;
+ glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
+
+ /* we need it later to give to the engine enable and disable */
+ glamo_mci_def_pdata.pglamo = glamo;
+ mangle_mem_resources(glamo_mmc_dev->resource,
+ glamo_mmc_dev->num_resources, glamo->mem);
+ platform_device_register(glamo_mmc_dev);
+
+ /* only request the generic, hostbus and memory controller MMIO */
+ glamo->mem = request_mem_region(glamo->mem->start,
+ GLAMO_REGOFS_VIDCAP, "glamo-core");
+ if (!glamo->mem) {
+ dev_err(&pdev->dev, "failed to request memory region\n");
+ goto bail_irq;
+ }
+
+ return 0;
+
+bail_irq:
+ disable_irq(glamo->irq);
+ set_irq_chained_handler(glamo->irq, NULL);
+
+ for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
+ set_irq_flags(irq, 0);
+ set_irq_chip(irq, NULL);
+ }
+
+ iounmap(glamo->base);
+bail_free:
+ platform_set_drvdata(pdev, NULL);
+ glamo_handle = NULL;
+ kfree(glamo);
+
+ return rc;
+}
+
+static int glamo_remove(struct platform_device *pdev)
+{
+ struct glamo_core *glamo = platform_get_drvdata(pdev);
+ int irq;
+
+ disable_irq(glamo->irq);
+ set_irq_chained_handler(glamo->irq, NULL);
+
+ for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
+ set_irq_flags(irq, 0);
+ set_irq_chip(irq, NULL);
+ }
+
+ platform_set_drvdata(pdev, NULL);
+ platform_device_unregister(&glamo_fb_dev);
+ platform_device_unregister(glamo->pdata->mmc_dev);
+ iounmap(glamo->base);
+ release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
+ glamo_handle = NULL;
+ kfree(glamo);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ glamo_handle->suspending = 1;
+ glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
+
+ return 0;
+}
+
+static int glamo_resume(struct platform_device *pdev)
+{
+ glamo_power(glamo_handle, GLAMO_POWER_ON);
+ glamo_handle->suspending = 0;
+
+ return 0;
+}
+
+#else
+#define glamo_suspend NULL
+#define glamo_resume NULL
+#endif
+
+static struct platform_driver glamo_driver = {
+ .probe = glamo_probe,
+ .remove = glamo_remove,
+ .suspend = glamo_suspend,
+ .resume = glamo_resume,
+ .driver = {
+ .name = "glamo3362",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __devinit glamo_init(void)
+{
+ return platform_driver_register(&glamo_driver);
+}
+
+static void __exit glamo_cleanup(void)
+{
+ platform_driver_unregister(&glamo_driver);
+}
+
+module_init(glamo_init);
+module_exit(glamo_cleanup);
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-core.h
@@ -0,0 +1,92 @@
+#ifndef __GLAMO_CORE_H
+#define __GLAMO_CORE_H
+
+#include <asm/system.h>
+
+/* for the time being, we put the on-screen framebuffer into the lowest
+ * VRAM space. This should make the code easily compatible with the various
+ * 2MB/4MB/8MB variants of the Smedia chips */
+#define GLAMO_OFFSET_VRAM 0x800000
+#define GLAMO_OFFSET_FB (GLAMO_OFFSET_VRAM)
+
+/* we only allocate the minimum possible size for the framebuffer to make
+ * sure we have sufficient memory for other functions of the chip */
+//#define GLAMO_FB_SIZE (640*480*4) /* == 0x12c000 */
+#define GLAMO_INTERNAL_RAM_SIZE 0x800000
+#define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
+#define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
+
+struct glamo_core {
+ int irq;
+ int irq_works; /* 0 means PCB does not support Glamo IRQ */
+ struct resource *mem;
+ struct resource *mem_core;
+ void __iomem *base;
+ struct platform_device *pdev;
+ struct glamofb_platform_data *pdata;
+ u_int16_t type;
+ u_int16_t revision;
+ spinlock_t lock;
+ u32 engine_enabled_bitfield;
+ u32 engine_enabled_bitfield_suspend;
+ int suspending;
+};
+
+struct glamo_script {
+ u_int16_t reg;
+ u_int16_t val;
+};
+
+int glamo_run_script(struct glamo_core *glamo,
+ struct glamo_script *script, int len, int may_sleep);
+
+enum glamo_engine {
+ GLAMO_ENGINE_CAPTURE,
+ GLAMO_ENGINE_ISP,
+ GLAMO_ENGINE_JPEG,
+ GLAMO_ENGINE_MPEG_ENC,
+ GLAMO_ENGINE_MPEG_DEC,
+ GLAMO_ENGINE_LCD,
+ GLAMO_ENGINE_CMDQ,
+ GLAMO_ENGINE_2D,
+ GLAMO_ENGINE_3D,
+ GLAMO_ENGINE_MMC,
+ GLAMO_ENGINE_MICROP0,
+ GLAMO_ENGINE_RISC,
+ GLAMO_ENGINE_MICROP1_MPEG_ENC,
+ GLAMO_ENGINE_MICROP1_MPEG_DEC,
+#if 0
+ GLAMO_ENGINE_H264_DEC,
+ GLAMO_ENGINE_RISC1,
+ GLAMO_ENGINE_SPI,
+#endif
+ __NUM_GLAMO_ENGINES
+};
+
+struct glamo_mci_pdata {
+ struct glamo_core * pglamo;
+ unsigned int gpio_detect;
+ unsigned int gpio_wprotect;
+ unsigned long ocr_avail;
+ int (*glamo_can_set_mci_power)(void);
+ /* glamo-mci asking if it should use the slow clock to card */
+ int (*glamo_mci_use_slow)(void);
+ int (*glamo_irq_is_wired)(void);
+ void (*mci_suspending)(struct platform_device *dev);
+ int (*mci_all_dependencies_resumed)(struct platform_device *dev);
+
+};
+
+int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
+int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
+void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
+int glamo_engine_reclock(struct glamo_core *glamo,
+ enum glamo_engine engine, int ps);
+
+void glamo_engine_clkreg_set(struct glamo_core *glamo,
+ enum glamo_engine engine,
+ u_int16_t mask, u_int16_t val);
+
+u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
+ enum glamo_engine engine);
+#endif /* __GLAMO_CORE_H */
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-fb.c
@@ -0,0 +1,1048 @@
+/* Smedia Glamo 336x/337x driver
+ *
+ * (C) 2007-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/wait.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/div64.h>
+
+#ifdef CONFIG_PM
+#include <linux/pm.h>
+#endif
+
+#include <linux/glamofb.h>
+
+#include "glamo-regs.h"
+#include "glamo-core.h"
+
+#ifndef DEBUG
+#define GLAMO_LOG(...)
+#else
+#define GLAMO_LOG(...) \
+do { \
+ printk(KERN_DEBUG "in %s:%s:%d", __FILE__, __func__, __LINE__); \
+ printk(KERN_DEBUG __VA_ARGS__); \
+} while (0);
+#endif
+
+
+#define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
+
+struct glamofb_handle {
+ struct fb_info *fb;
+ struct device *dev;
+ struct resource *reg;
+ struct resource *fb_res;
+ char __iomem *base;
+ struct glamofb_platform_data *mach_info;
+ char __iomem *cursor_addr;
+ int cursor_on;
+ u_int32_t pseudo_pal[16];
+ spinlock_t lock_cmd;
+};
+
+/* 'sibling' spi device for lcm init */
+static struct platform_device glamo_spi_dev = {
+ .name = "glamo-lcm-spi",
+};
+
+
+static int reg_read(struct glamofb_handle *glamo,
+ u_int16_t reg)
+{
+ return readw(glamo->base + reg);
+}
+
+static void reg_write(struct glamofb_handle *glamo,
+ u_int16_t reg, u_int16_t val)
+{
+ writew(val, glamo->base + reg);
+}
+
+static struct glamo_script glamo_regs[] = {
+ { GLAMO_REG_LCD_MODE1, 0x0020 },
+ /* no display rotation, no hardware cursor, no dither, no gamma,
+ * no retrace flip, vsync low-active, hsync low active,
+ * no TVCLK, no partial display, hw dest color from fb,
+ * no partial display mode, LCD1, software flip, */
+ { GLAMO_REG_LCD_MODE2, 0x9020 },
+ /* video flip, no ptr, no ptr, dhclk off,
+ * normal mode, no cpuif,
+ * res, serial msb first, single fb, no fr ctrl,
+ * cpu if bits all zero, no crc
+ * 0000 0000 0010 0000 */
+ { GLAMO_REG_LCD_MODE3, 0x0b40 },
+ /* src data rgb565, res, 18bit rgb666
+ * 000 01 011 0100 0000 */
+ { GLAMO_REG_LCD_POLARITY, 0x440c },
+ /* DE high active, no cpu/lcd if, cs0 force low, a0 low active,
+ * np cpu if, 9bit serial data, sclk rising edge latch data
+ * 01 00 0 100 0 000 01 0 0 */
+ /* The following values assume 640*480@16bpp */
+ { GLAMO_REG_LCD_A_BASE1, 0x0000 }, /* display A base address 15:0 */
+ { GLAMO_REG_LCD_A_BASE2, 0x0000 }, /* display A base address 22:16 */
+ { GLAMO_REG_LCD_B_BASE1, 0x6000 }, /* display B base address 15:0 */
+ { GLAMO_REG_LCD_B_BASE2, 0x0009 }, /* display B base address 22:16 */
+ { GLAMO_REG_LCD_CURSOR_BASE1, 0xC000 }, /* cursor base address 15:0 */
+ { GLAMO_REG_LCD_CURSOR_BASE2, 0x0012 }, /* cursor base address 22:16 */
+ { GLAMO_REG_LCD_COMMAND2, 0x0000 }, /* display page A */
+};
+
+static int glamofb_run_script(struct glamofb_handle *glamo,
+ struct glamo_script *script, int len)
+{
+ int i;
+
+ if (glamo->mach_info->glamo->suspending) {
+ dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_run_script while "
+ "suspended\n");
+ return -EBUSY;
+ }
+
+ for (i = 0; i < len; i++) {
+ struct glamo_script *line = &script[i];
+
+ if (line->reg == 0xffff)
+ return 0;
+ else if (line->reg == 0xfffe)
+ msleep(line->val);
+ else
+ reg_write(glamo, script[i].reg, script[i].val);
+ }
+
+ return 0;
+}
+
+static int glamofb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct glamofb_handle *glamo = info->par;
+
+ if (glamo->mach_info->glamo->suspending) {
+ dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_check_var while "
+ "suspended\n");
+ return -EBUSY;
+ }
+
+ if (var->yres > glamo->mach_info->yres.max)
+ var->yres = glamo->mach_info->yres.max;
+ else if (var->yres < glamo->mach_info->yres.min)
+ var->yres = glamo->mach_info->yres.min;
+
+ if (var->xres > glamo->mach_info->xres.max)
+ var->xres = glamo->mach_info->xres.max;
+ else if (var->xres < glamo->mach_info->xres.min)
+ var->xres = glamo->mach_info->xres.min;
+
+ if (var->bits_per_pixel > glamo->mach_info->bpp.max)
+ var->bits_per_pixel = glamo->mach_info->bpp.max;
+ else if (var->bits_per_pixel < glamo->mach_info->bpp.min)
+ var->bits_per_pixel = glamo->mach_info->bpp.min;
+
+ /* FIXME: set rgb positions */
+ switch (var->bits_per_pixel) {
+ case 16:
+ switch (reg_read(glamo, GLAMO_REG_LCD_MODE3) & 0xc000) {
+ case GLAMO_LCD_SRC_RGB565:
+ var->red.offset = 11;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->red.length = 5;
+ var->green.length = 6;
+ var->blue.length = 5;
+ var->transp.length = 0;
+ break;
+ case GLAMO_LCD_SRC_ARGB1555:
+ var->transp.offset = 15;
+ var->red.offset = 10;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->transp.length = 1;
+ var->red.length = 5;
+ var->green.length = 5;
+ var->blue.length = 5;
+ break;
+ case GLAMO_LCD_SRC_ARGB4444:
+ var->transp.offset = 12;
+ var->red.offset = 8;
+ var->green.offset = 4;
+ var->blue.offset = 0;
+ var->transp.length = 4;
+ var->red.length = 4;
+ var->green.length = 4;
+ var->blue.length = 4;
+ break;
+ }
+ break;
+ case 24:
+ case 32:
+ default:
+ /* The Smedia Glamo doesn't support anything but 16bit color */
+ printk(KERN_ERR
+ "Smedia driver does not [yet?] support 24/32bpp\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void reg_set_bit_mask(struct glamofb_handle *glamo,
+ u_int16_t reg, u_int16_t mask,
+ u_int16_t val)
+{
+ u_int16_t tmp;
+
+ val &= mask;
+
+ tmp = reg_read(glamo, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ reg_write(glamo, reg, tmp);
+}
+
+#define GLAMO_LCD_WIDTH_MASK 0x03FF
+#define GLAMO_LCD_HEIGHT_MASK 0x03FF
+#define GLAMO_LCD_PITCH_MASK 0x07FE
+#define GLAMO_LCD_HV_TOTAL_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_START_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_END_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_DISP_START_MASK 0x03FF
+#define GLAMO_LCD_HV_RETR_DISP_END_MASK 0x03FF
+
+enum orientation {
+ ORIENTATION_PORTRAIT,
+ ORIENTATION_LANDSCAPE
+};
+
+
+/* the caller has to enxure lock_cmd is held and we are in cmd mode */
+static void __rotate_lcd(struct glamofb_handle *glamo, __u32 rotation)
+{
+ int glamo_rot;
+
+ if (glamo->mach_info->glamo->suspending) {
+ dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING rotate_lcd while "
+ "suspended\n");
+ return;
+ }
+
+ switch (rotation) {
+ case FB_ROTATE_UR:
+ glamo_rot = GLAMO_LCD_ROT_MODE_0;
+ break;
+ case FB_ROTATE_CW:
+ glamo_rot = GLAMO_LCD_ROT_MODE_90;
+ break;
+ case FB_ROTATE_UD:
+ glamo_rot = GLAMO_LCD_ROT_MODE_180;
+ break;
+ case FB_ROTATE_CCW:
+ glamo_rot = GLAMO_LCD_ROT_MODE_270;
+ break;
+ default:
+ glamo_rot = GLAMO_LCD_ROT_MODE_0;
+ break;
+ }
+
+ reg_set_bit_mask(glamo,
+ GLAMO_REG_LCD_WIDTH,
+ GLAMO_LCD_ROT_MODE_MASK,
+ glamo_rot);
+ reg_set_bit_mask(glamo,
+ GLAMO_REG_LCD_MODE1,
+ GLAMO_LCD_MODE1_ROTATE_EN,
+ (glamo_rot != GLAMO_LCD_ROT_MODE_0)?
+ GLAMO_LCD_MODE1_ROTATE_EN : 0);
+}
+
+static enum orientation get_orientation(struct fb_var_screeninfo *var)
+{
+ if (var->xres <= var->yres)
+ return ORIENTATION_PORTRAIT;
+
+ return ORIENTATION_LANDSCAPE;
+}
+
+static int will_orientation_change(struct fb_var_screeninfo *var)
+{
+ enum orientation orient = get_orientation(var);
+
+ switch (orient) {
+ case ORIENTATION_LANDSCAPE:
+ if (var->rotate == FB_ROTATE_UR ||
+ var->rotate == FB_ROTATE_UD)
+ return 1;
+ break;
+ case ORIENTATION_PORTRAIT:
+ if (var->rotate == FB_ROTATE_CW ||
+ var->rotate == FB_ROTATE_CCW)
+ return 1;
+ break;
+ }
+ return 0;
+}
+
+static void glamofb_update_lcd_controller(struct glamofb_handle *glamo,
+ struct fb_var_screeninfo *var)
+{
+ int sync, bp, disp, fp, total, xres, yres, pitch, orientation_changing;
+ unsigned long flags;
+
+ if (!glamo || !var)
+ return;
+
+ if (glamo->mach_info->glamo->suspending) {
+ dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_update_lcd_controller while "
+ "suspended\n");
+ return;
+ }
+
+ dev_dbg(&glamo->mach_info->glamo->pdev->dev,
+ "glamofb_update_lcd_controller spin_lock_irqsave\n");
+ spin_lock_irqsave(&glamo->lock_cmd, flags);
+
+ if (glamofb_cmd_mode(glamo, 1))
+ goto out_unlock;
+
+ if (var->pixclock)
+ glamo_engine_reclock(glamo->mach_info->glamo,
+ GLAMO_ENGINE_LCD,
+ var->pixclock);
+
+ xres = var->xres;
+ yres = var->yres;
+
+ /* figure out if orientation is going to change */
+ orientation_changing = will_orientation_change(var);
+
+ /* adjust the pitch according to new orientation to come */
+
+ if (orientation_changing) {
+ pitch = var->yres * var->bits_per_pixel / 8;
+ } else {
+ pitch = var->xres * var->bits_per_pixel / 8;
+ }
+
+ /*
+ * set the desired LCD geometry
+ */
+ reg_set_bit_mask(glamo,
+ GLAMO_REG_LCD_WIDTH,
+ GLAMO_LCD_WIDTH_MASK,
+ xres);
+ reg_set_bit_mask(glamo,
+ GLAMO_REG_LCD_HEIGHT,
+ GLAMO_LCD_HEIGHT_MASK,
+ yres);
+ reg_set_bit_mask(glamo,
+ GLAMO_REG_LCD_PITCH,
+ GLAMO_LCD_PITCH_MASK,
+ pitch);
+
+ /* honour the rotation request */
+ __rotate_lcd(glamo, var->rotate);
+
+ /* update the reported geometry of the framebuffer. */
+ if (orientation_changing) {
+ var->xres_virtual = var->xres = yres;
+ var->xres_virtual *= 2;
+ var->yres_virtual = var->yres = xres;
+ } else {
+ var->xres_virtual = var->xres = xres;
+ var->yres_virtual = var->yres = yres;
+ var->yres_virtual *= 2;
+ }
+
+ /* update scannout timings */
+ sync = 0;
+ bp = sync + var->hsync_len;
+ disp = bp + var->left_margin;
+ fp = disp + xres;
+ total = fp + var->right_margin;
+
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_TOTAL,
+ GLAMO_LCD_HV_TOTAL_MASK, total);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_RETR_START,
+ GLAMO_LCD_HV_RETR_START_MASK, sync);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_RETR_END,
+ GLAMO_LCD_HV_RETR_END_MASK, bp);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_DISP_START,
+ GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_HORIZ_DISP_END,
+ GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
+
+ sync = 0;
+ bp = sync + var->vsync_len;
+ disp = bp + var->upper_margin;
+ fp = disp + yres;
+ total = fp + var->lower_margin;
+
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_TOTAL,
+ GLAMO_LCD_HV_TOTAL_MASK, total);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_RETR_START,
+ GLAMO_LCD_HV_RETR_START_MASK, sync);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_RETR_END,
+ GLAMO_LCD_HV_RETR_END_MASK, bp);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_DISP_START,
+ GLAMO_LCD_HV_RETR_DISP_START_MASK, disp);
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_VERT_DISP_END,
+ GLAMO_LCD_HV_RETR_DISP_END_MASK, fp);
+
+ glamofb_cmd_mode(glamo, 0);
+
+out_unlock:
+ dev_dbg(&glamo->mach_info->glamo->pdev->dev,
+ "glamofb_update_lcd_controller spin_unlock_irqrestore\n");
+ spin_unlock_irqrestore(&glamo->lock_cmd, flags);
+}
+
+static int glamofb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ struct glamofb_handle *glamo = info->par;
+ u_int16_t page = var->yoffset / glamo->mach_info->yres.defval;
+ reg_write(glamo, GLAMO_REG_LCD_COMMAND2, page);
+
+ return 0;
+}
+
+static int glamofb_set_par(struct fb_info *info)
+{
+ struct glamofb_handle *glamo = info->par;
+ struct fb_var_screeninfo *var = &info->var;
+
+ if (glamo->mach_info->glamo->suspending) {
+ dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_set_par while "
+ "suspended\n");
+ return -EBUSY;
+ }
+
+ switch (var->bits_per_pixel) {
+ case 16:
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ break;
+ default:
+ printk("Smedia driver doesn't support != 16bpp\n");
+ return -EINVAL;
+ }
+
+ info->fix.line_length = (var->xres * var->bits_per_pixel) / 8;
+
+ glamofb_update_lcd_controller(glamo, var);
+
+ return 0;
+}
+
+
+static void notify_blank(struct fb_info *info, int blank_mode)
+{
+ struct fb_event event;
+
+ event.info = info;
+ event.data = &blank_mode;
+ fb_notifier_call_chain(FB_EVENT_CONBLANK, &event);
+}
+
+
+static int glamofb_blank(int blank_mode, struct fb_info *info)
+{
+ struct glamofb_handle *gfb = info->par;
+ struct glamo_core *gcore = gfb->mach_info->glamo;
+
+ dev_dbg(gfb->dev, "glamofb_blank(%u)\n", blank_mode);
+
+ switch (blank_mode) {
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ /* FIXME: add pdata hook/flag to indicate whether
+ * we should already switch off pixel clock here */
+ break;
+ case FB_BLANK_POWERDOWN:
+ /* disable the pixel clock */
+ glamo_engine_clkreg_set(gcore, GLAMO_ENGINE_LCD,
+ GLAMO_CLOCK_LCD_EN_DCLK, 0);
+ break;
+ case FB_BLANK_UNBLANK:
+ case FB_BLANK_NORMAL:
+ /* enable the pixel clock */
+ glamo_engine_clkreg_set(gcore, GLAMO_ENGINE_LCD,
+ GLAMO_CLOCK_LCD_EN_DCLK,
+ GLAMO_CLOCK_LCD_EN_DCLK);
+ notify_blank(info, blank_mode);
+ break;
+ }
+
+ /* FIXME: once we have proper clock management in glamo-core,
+ * we can determine if other units need MCLK1 or the PLL, and
+ * disable it if not used. */
+ return 0;
+}
+
+static inline unsigned int chan_to_field(unsigned int chan,
+ struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int glamofb_setcolreg(unsigned regno,
+ unsigned red, unsigned green, unsigned blue,
+ unsigned transp, struct fb_info *info)
+{
+ struct glamofb_handle *glamo = info->par;
+ unsigned int val;
+
+ if (glamo->mach_info->glamo->suspending) {
+ dev_err(&glamo->mach_info->glamo->pdev->dev, "IGNORING glamofb_set_par while "
+ "suspended\n");
+ return -EBUSY;
+ }
+
+ switch (glamo->fb->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ case FB_VISUAL_DIRECTCOLOR:
+ /* true-colour, use pseuo-palette */
+
+ if (regno < 16) {
+ u32 *pal = glamo->fb->pseudo_palette;
+
+ val = chan_to_field(red, &glamo->fb->var.red);
+ val |= chan_to_field(green, &glamo->fb->var.green);
+ val |= chan_to_field(blue, &glamo->fb->var.blue);
+
+ pal[regno] = val;
+ };
+ break;
+ default:
+ return 1; /* unknown type */
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_MFD_GLAMO_HWACCEL
+static inline void glamofb_vsync_wait(struct glamofb_handle *glamo,
+ int line, int size, int range)
+{
+ int count[2];
+
+ do {
+ count[0] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
+ count[1] = reg_read(glamo, GLAMO_REG_LCD_STATUS2) & 0x3ff;
+ } while (count[0] != count[1] ||
+ (line < count[0] + range &&
+ size > count[0] - range) ||
+ count[0] < range * 2);
+}
+
+/*
+ * Enable/disable the hardware cursor mode altogether
+ * (for blinking and such, use glamofb_cursor()).
+ */
+static void glamofb_cursor_onoff(struct glamofb_handle *glamo, int on)
+{
+ int y, size;
+
+ if (glamo->cursor_on) {
+ y = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_POS);
+ size = reg_read(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE);
+
+ glamofb_vsync_wait(glamo, y, size, 30);
+ }
+
+ reg_set_bit_mask(glamo, GLAMO_REG_LCD_MODE1,
+ GLAMO_LCD_MODE1_CURSOR_EN,
+ on ? GLAMO_LCD_MODE1_CURSOR_EN : 0);
+ glamo->cursor_on = on;
+
+ /* Hide the cursor by default */
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE, 0);
+}
+
+static int glamofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
+{
+ struct glamofb_handle *glamo = info->par;
+ unsigned long flags;
+
+ spin_lock_irqsave(&glamo->lock_cmd, flags);
+
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_SIZE,
+ cursor->enable ? cursor->image.width : 0);
+
+ if (cursor->set & FB_CUR_SETPOS) {
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_X_POS,
+ cursor->image.dx);
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_POS,
+ cursor->image.dy);
+ }
+
+ if (cursor->set & FB_CUR_SETCMAP) {
+ uint16_t fg = glamo->pseudo_pal[cursor->image.fg_color];
+ uint16_t bg = glamo->pseudo_pal[cursor->image.bg_color];
+
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_FG_COLOR, fg);
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_BG_COLOR, bg);
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_DST_COLOR, fg);
+ }
+
+ if (cursor->set & FB_CUR_SETHOT)
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_PRESET,
+ (cursor->hot.x << 8) | cursor->hot.y);
+
+ if ((cursor->set & FB_CUR_SETSIZE) ||
+ (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE))) {
+ int x, y, pitch, op;
+ const uint8_t *pcol = cursor->image.data;
+ const uint8_t *pmsk = cursor->mask;
+ uint8_t __iomem *dst = glamo->cursor_addr;
+ uint8_t dcol = 0;
+ uint8_t dmsk = 0;
+ uint8_t byte = 0;
+
+ if (cursor->image.depth > 1) {
+ spin_unlock_irqrestore(&glamo->lock_cmd, flags);
+ return -EINVAL;
+ }
+
+ pitch = ((cursor->image.width + 7) >> 2) & ~1;
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_PITCH,
+ pitch);
+ reg_write(glamo, GLAMO_REG_LCD_CURSOR_Y_SIZE,
+ cursor->image.height);
+
+ for (y = 0; y < cursor->image.height; y++) {
+ byte = 0;
+ for (x = 0; x < cursor->image.width; x++) {
+ if ((x % 8) == 0) {
+ dcol = *pcol++;
+ dmsk = *pmsk++;
+ } else {
+ dcol >>= 1;
+ dmsk >>= 1;
+ }
+
+ if (cursor->rop == ROP_COPY)
+ op = (dmsk & 1) ?
+ (dcol & 1) ? 1 : 3 : 0;
+ else
+ op = ((dmsk & 1) << 1) |
+ ((dcol & 1) << 0);
+ byte |= op << ((x & 3) << 1);
+
+ if (x % 4 == 3) {
+ writeb(byte, dst + x / 4);
+ byte = 0;
+ }
+ }
+ if (x % 4) {
+ writeb(byte, dst + x / 4);
+ byte = 0;
+ }
+
+ dst += pitch;
+ }
+ }
+
+ spin_unlock_irqrestore(&glamo->lock_cmd, flags);
+
+ return 0;
+}
+#endif
+
+static inline int glamofb_cmdq_empty(struct glamofb_handle *gfb)
+{
+ /* DGCMdQempty -- 1 == command queue is empty */
+ return reg_read(gfb, GLAMO_REG_LCD_STATUS1) & (1 << 15);
+}
+
+/* call holding gfb->lock_cmd when locking, until you unlock */
+int glamofb_cmd_mode(struct glamofb_handle *gfb, int on)
+{
+ int timeout = 2000000;
+
+ if (gfb->mach_info->glamo->suspending) {
+ dev_err(&gfb->mach_info->glamo->pdev->dev, "IGNORING glamofb_cmd_mode while "
+ "suspended\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(gfb->dev, "glamofb_cmd_mode(gfb=%p, on=%d)\n", gfb, on);
+ if (on) {
+ dev_dbg(gfb->dev, "%s: waiting for cmdq empty: ",
+ __FUNCTION__);
+ while ((!glamofb_cmdq_empty(gfb)) && (timeout--))
+ /* yield() */;
+ if (timeout < 0) {
+ printk(KERN_ERR"*************"
+ "glamofb cmd_queue never got empty"
+ "*************\n");
+ return -EIO;
+ }
+ dev_dbg(gfb->dev, "empty!\n");
+
+ /* display the entire frame then switch to command */
+ reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+ GLAMO_LCD_CMD_TYPE_DISP |
+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC);
+
+ /* wait until lcd idle */
+ dev_dbg(gfb->dev, "waiting for lcd idle: ");
+ timeout = 2000000;
+ while ((!reg_read(gfb, GLAMO_REG_LCD_STATUS2) & (1 << 12)) &&
+ (timeout--))
+ /* yield() */;
+ if (timeout < 0) {
+ printk(KERN_ERR"*************"
+ "glamofb lcd never idle"
+ "*************\n");
+ return -EIO;
+ }
+
+ mdelay(100);
+
+ dev_dbg(gfb->dev, "cmd mode entered\n");
+
+ } else {
+ /* RGB interface needs vsync/hsync */
+ if (reg_read(gfb, GLAMO_REG_LCD_MODE3) & GLAMO_LCD_MODE3_RGB)
+ reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+ GLAMO_LCD_CMD_TYPE_DISP |
+ GLAMO_LCD_CMD_DATA_DISP_SYNC);
+
+ reg_write(gfb, GLAMO_REG_LCD_COMMAND1,
+ GLAMO_LCD_CMD_TYPE_DISP |
+ GLAMO_LCD_CMD_DATA_DISP_FIRE);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(glamofb_cmd_mode);
+
+
+int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val)
+{
+ int timeout = 200000;
+
+ if (gfb->mach_info->glamo->suspending) {
+ dev_err(&gfb->mach_info->glamo->pdev->dev, "IGNORING glamofb_cmd_write while "
+ "suspended\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(gfb->dev, "%s: waiting for cmdq empty\n", __FUNCTION__);
+ while ((!glamofb_cmdq_empty(gfb)) && (timeout--))
+ yield();
+ if (timeout < 0) {
+ printk(KERN_ERR"*************"
+ "glamofb cmd_queue never got empty"
+ "*************\n");
+ return 1;
+ }
+ dev_dbg(gfb->dev, "idle, writing 0x%04x\n", val);
+
+ reg_write(gfb, GLAMO_REG_LCD_COMMAND1, val);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(glamofb_cmd_write);
+
+static struct fb_ops glamofb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = glamofb_check_var,
+ .fb_pan_display = glamofb_pan_display,
+ .fb_set_par = glamofb_set_par,
+ .fb_blank = glamofb_blank,
+ .fb_setcolreg = glamofb_setcolreg,
+#ifdef CONFIG_MFD_GLAMO_HWACCEL
+ .fb_cursor = glamofb_cursor,
+#endif
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+static int glamofb_init_regs(struct glamofb_handle *glamo)
+{
+ struct fb_info *info = glamo->fb;
+
+ glamofb_check_var(&info->var, info);
+ glamofb_run_script(glamo, glamo_regs, ARRAY_SIZE(glamo_regs));
+ glamofb_set_par(info);
+
+ return 0;
+}
+
+static int __init glamofb_probe(struct platform_device *pdev)
+{
+ int rc = -EIO;
+ struct fb_info *fbinfo;
+ struct glamofb_handle *glamofb;
+ struct glamofb_platform_data *mach_info = pdev->dev.platform_data;
+
+ printk(KERN_INFO "SMEDIA Glamo frame buffer driver (C) 2007 "
+ "Openmoko, Inc.\n");
+
+ fbinfo = framebuffer_alloc(sizeof(struct glamofb_handle), &pdev->dev);
+ if (!fbinfo)
+ return -ENOMEM;
+
+ glamofb = fbinfo->par;
+ glamofb->fb = fbinfo;
+ glamofb->dev = &pdev->dev;
+
+ strcpy(fbinfo->fix.id, "SMedia Glamo");
+
+ glamofb->reg = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "glamo-fb-regs");
+ if (!glamofb->reg) {
+ dev_err(&pdev->dev, "platform device with no registers?\n");
+ rc = -ENOENT;
+ goto out_free;
+ }
+
+ glamofb->fb_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "glamo-fb-mem");
+ if (!glamofb->fb_res) {
+ dev_err(&pdev->dev, "platform device with no memory ?\n");
+ rc = -ENOENT;
+ goto out_free;
+ }
+
+ glamofb->reg = request_mem_region(glamofb->reg->start,
+ RESSIZE(glamofb->reg), pdev->name);
+ if (!glamofb->reg) {
+ dev_err(&pdev->dev, "failed to request mmio region\n");
+ goto out_free;
+ }
+
+ glamofb->fb_res = request_mem_region(glamofb->fb_res->start,
+ mach_info->fb_mem_size,
+ pdev->name);
+ if (!glamofb->fb_res) {
+ dev_err(&pdev->dev, "failed to request vram region\n");
+ goto out_release_reg;
+ }
+
+ /* we want to remap only the registers required for this core
+ * driver. */
+ glamofb->base = ioremap(glamofb->reg->start, RESSIZE(glamofb->reg));
+ if (!glamofb->base) {
+ dev_err(&pdev->dev, "failed to ioremap() mmio memory\n");
+ goto out_release_fb;
+ }
+ fbinfo->fix.smem_start = (unsigned long) glamofb->fb_res->start;
+ fbinfo->fix.smem_len = mach_info->fb_mem_size;
+
+ fbinfo->screen_base = ioremap(glamofb->fb_res->start,
+ RESSIZE(glamofb->fb_res));
+ if (!fbinfo->screen_base) {
+ dev_err(&pdev->dev, "failed to ioremap() vram memory\n");
+ goto out_release_fb;
+ }
+ glamofb->cursor_addr = fbinfo->screen_base + 0x12C000;
+
+ platform_set_drvdata(pdev, glamofb);
+
+ glamofb->mach_info = pdev->dev.platform_data;
+
+ fbinfo->fix.visual = FB_VISUAL_TRUECOLOR;
+ fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
+ fbinfo->fix.type_aux = 0;
+ fbinfo->fix.xpanstep = 0;
+ fbinfo->fix.ypanstep = mach_info->yres.defval;
+ fbinfo->fix.ywrapstep = 0;
+ fbinfo->fix.accel = FB_ACCEL_GLAMO;
+
+ fbinfo->var.nonstd = 0;
+ fbinfo->var.activate = FB_ACTIVATE_NOW;
+ fbinfo->var.height = mach_info->height;
+ fbinfo->var.width = mach_info->width;
+ fbinfo->var.accel_flags = 0; /* FIXME */
+ fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
+
+ fbinfo->fbops = &glamofb_ops;
+ fbinfo->flags = FBINFO_FLAG_DEFAULT;
+ fbinfo->pseudo_palette = &glamofb->pseudo_pal;
+
+ fbinfo->var.xres = mach_info->xres.defval;
+ fbinfo->var.xres_virtual = mach_info->xres.defval;
+ fbinfo->var.yres = mach_info->yres.defval;
+ fbinfo->var.yres_virtual = mach_info->yres.defval * 2;
+ fbinfo->var.bits_per_pixel = mach_info->bpp.defval;
+
+ fbinfo->var.pixclock = mach_info->pixclock;
+ fbinfo->var.left_margin = mach_info->left_margin;
+ fbinfo->var.right_margin = mach_info->right_margin;
+ fbinfo->var.upper_margin = mach_info->upper_margin;
+ fbinfo->var.lower_margin = mach_info->lower_margin;
+ fbinfo->var.hsync_len = mach_info->hsync_len;
+ fbinfo->var.vsync_len = mach_info->vsync_len;
+
+ memset(fbinfo->screen_base, 0,
+ mach_info->xres.max *
+ mach_info->yres.max *
+ mach_info->bpp.max / 8);
+
+ glamo_engine_enable(mach_info->glamo, GLAMO_ENGINE_LCD);
+ glamo_engine_reset(mach_info->glamo, GLAMO_ENGINE_LCD);
+
+ dev_info(&pdev->dev, "spin_lock_init\n");
+ spin_lock_init(&glamofb->lock_cmd);
+ glamofb_init_regs(glamofb);
+#ifdef CONFIG_MFD_GLAMO_HWACCEL
+ glamofb_cursor_onoff(glamofb, 1);
+#endif
+
+ rc = register_framebuffer(fbinfo);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "failed to register framebuffer\n");
+ goto out_unmap_fb;
+ }
+
+ if (mach_info->spi_info) {
+ /* register the sibling spi device */
+ mach_info->spi_info->glamofb_handle = glamofb;
+ glamo_spi_dev.dev.parent = &pdev->dev;
+ glamo_spi_dev.dev.platform_data = mach_info->spi_info;
+ platform_device_register(&glamo_spi_dev);
+ }
+
+ printk(KERN_INFO "fb%d: %s frame buffer device\n",
+ fbinfo->node, fbinfo->fix.id);
+
+ return 0;
+
+out_unmap_fb:
+ iounmap(fbinfo->screen_base);
+ iounmap(glamofb->base);
+out_release_fb:
+ release_mem_region(glamofb->fb_res->start, RESSIZE(glamofb->fb_res));
+out_release_reg:
+ release_mem_region(glamofb->reg->start, RESSIZE(glamofb->reg));
+out_free:
+ framebuffer_release(fbinfo);
+ return rc;
+}
+
+static int glamofb_remove(struct platform_device *pdev)
+{
+ struct glamofb_handle *glamofb = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ iounmap(glamofb->base);
+ release_mem_region(glamofb->reg->start, RESSIZE(glamofb->reg));
+ kfree(glamofb);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int glamofb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct glamofb_handle *gfb = platform_get_drvdata(pdev);
+
+ /* we need to stop anything touching our framebuffer */
+// fb_blank(gfb->fb, FB_BLANK_NORMAL);
+ fb_set_suspend(gfb->fb, 1);
+
+ /* seriously -- nobody is allowed to touch glamo memory when we
+ * are suspended or we lock on nWAIT
+ */
+// iounmap(gfb->fb->screen_base);
+
+ return 0;
+}
+
+static int glamofb_resume(struct platform_device *pdev)
+{
+ struct glamofb_handle *glamofb = platform_get_drvdata(pdev);
+ struct glamofb_platform_data *mach_info = pdev->dev.platform_data;
+
+ /* OK let's allow framebuffer ops again */
+// gfb->fb->screen_base = ioremap(gfb->fb_res->start,
+// RESSIZE(gfb->fb_res));
+ glamo_engine_enable(mach_info->glamo, GLAMO_ENGINE_LCD);
+ glamo_engine_reset(mach_info->glamo, GLAMO_ENGINE_LCD);
+
+ printk(KERN_ERR"spin_lock_init\n");
+ spin_lock_init(&glamofb->lock_cmd);
+ glamofb_init_regs(glamofb);
+#ifdef CONFIG_MFD_GLAMO_HWACCEL
+ glamofb_cursor_onoff(glamofb, 1);
+#endif
+
+
+ fb_set_suspend(glamofb->fb, 0);
+// fb_blank(gfb->fb, FB_BLANK_UNBLANK);
+
+ return 0;
+}
+#else
+#define glamo_suspend NULL
+#define glamo_resume NULL
+#endif
+
+static struct platform_driver glamofb_driver = {
+ .probe = glamofb_probe,
+ .remove = glamofb_remove,
+ .suspend = glamofb_suspend,
+ .resume = glamofb_resume,
+ .driver = {
+ .name = "glamo-fb",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __devinit glamofb_init(void)
+{
+ return platform_driver_register(&glamofb_driver);
+}
+
+static void __exit glamofb_cleanup(void)
+{
+ platform_driver_unregister(&glamofb_driver);
+}
+
+module_init(glamofb_init);
+module_exit(glamofb_cleanup);
+
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_DESCRIPTION("Smedia Glamo 336x/337x framebuffer driver");
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-gpio.c
@@ -0,0 +1,62 @@
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <linux/glamo-gpio.h>
+
+#include "glamo-core.h"
+#include "glamo-regs.h"
+
+void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin,
+ unsigned int value)
+{
+ unsigned int reg = REG_OF_GPIO(pin);
+ u_int16_t tmp;
+
+ spin_lock(&glamo->lock);
+ tmp = readw(glamo->base + reg);
+ if (value)
+ tmp |= OUTPUT_BIT(pin);
+ else
+ tmp &= ~OUTPUT_BIT(pin);
+ writew(tmp, glamo->base + reg);
+ spin_unlock(&glamo->lock);
+}
+EXPORT_SYMBOL(glamo_gpio_setpin);
+
+int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin)
+{
+ return readw(REG_OF_GPIO(pin)) & INPUT_BIT(pin) ? 1 : 0;
+}
+EXPORT_SYMBOL(glamo_gpio_getpin);
+
+void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc)
+{
+ unsigned int reg = REG_OF_GPIO(pinfunc);
+ u_int16_t tmp;
+
+ spin_lock(&glamo->lock);
+ tmp = readw(glamo->base + reg);
+
+ if ((pinfunc & 0x00f0) == GLAMO_GPIO_F_FUNC) {
+ /* pin is a function pin: clear gpio bit */
+ tmp &= ~FUNC_BIT(pinfunc);
+ } else {
+ /* pin is gpio: set gpio bit */
+ tmp |= FUNC_BIT(pinfunc);
+
+ if (pinfunc & GLAMO_GPIO_F_IN) {
+ /* gpio input: set bit to disable output mode */
+ tmp |= GPIO_OUT_BIT(pinfunc);
+ } else if (pinfunc & GLAMO_GPIO_F_OUT) {
+ /* gpio output: clear bit to enable output mode */
+ tmp &= ~GPIO_OUT_BIT(pinfunc);
+ }
+ }
+ writew(tmp, glamo->base + reg);
+ spin_unlock(&glamo->lock);
+}
+EXPORT_SYMBOL(glamo_gpio_cfgpin);
+
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-lcm-spi.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2007 Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ *
+ * Smedia Glamo GPIO based SPI driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver currently only implements a minimum subset of the hardware
+ * features, esp. those features that are required to drive the jbt6k74
+ * LCM controller asic in the TD028TTEC1 LCM.
+ *
+*/
+
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+#include <linux/spi/glamo.h>
+
+#include <linux/glamofb.h>
+
+#include <mach/hardware.h>
+
+#include "glamo-core.h"
+#include "glamo-regs.h"
+
+struct glamo_spi {
+ struct spi_bitbang bitbang;
+ struct spi_master *master;
+ struct glamo_spi_info *info;
+ struct device *dev;
+};
+
+static inline struct glamo_spi *to_gs(struct spi_device *spi)
+{
+ return spi->controller_data;
+}
+
+static int glamo_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
+{
+ unsigned int bpw;
+
+ bpw = t ? t->bits_per_word : spi->bits_per_word;
+
+ if (bpw != 9 && bpw != 8) {
+ dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void glamo_spi_chipsel(struct spi_device *spi, int value)
+{
+#if 0
+ struct glamo_spi *gs = to_gs(spi);
+
+ dev_dbg(&spi->dev, "chipsel %d: spi=%p, gs=%p, info=%p, handle=%p\n",
+ value, spi, gs, gs->info, gs->info->glamofb_handle);
+
+ glamofb_cmd_mode(gs->info->glamofb_handle, value);
+#endif
+}
+
+static int glamo_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
+{
+ struct glamo_spi *gs = to_gs(spi);
+ const u_int16_t *ui16 = (const u_int16_t *) t->tx_buf;
+ u_int16_t nine_bits;
+ int i;
+
+ dev_dbg(&spi->dev, "txrx: tx %p, rx %p, bpw %d, len %d\n",
+ t->tx_buf, t->rx_buf, t->bits_per_word, t->len);
+
+ if (spi->bits_per_word == 9)
+ nine_bits = (1 << 9);
+ else
+ nine_bits = 0;
+
+ if (t->len > 3 * sizeof(u_int16_t)) {
+ dev_err(&spi->dev, "this driver doesn't support "
+ "%u sized xfers\n", t->len);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < t->len/sizeof(u_int16_t); i++) {
+ /* actually transfer the data */
+#if 1
+ glamofb_cmd_write(gs->info->glamofb_handle,
+ GLAMO_LCD_CMD_TYPE_SERIAL | nine_bits |
+ (1 << 10) | (1 << 11) | (ui16[i] & 0x1ff));
+#endif
+ /* FIXME: fire ?!? */
+ if (i == 0 && (ui16[i] & 0x1ff) == 0x29) {
+ dev_dbg(&spi->dev, "leaving command mode\n");
+ glamofb_cmd_mode(gs->info->glamofb_handle, 0);
+ }
+ }
+
+ return t->len;
+}
+
+static int glamo_spi_setup(struct spi_device *spi)
+{
+ int ret;
+
+ if (!spi->bits_per_word)
+ spi->bits_per_word = 9;
+
+ /* FIXME: hardware can do this */
+ if (spi->mode & SPI_LSB_FIRST)
+ return -EINVAL;
+
+ ret = glamo_spi_setupxfer(spi, NULL);
+ if (ret < 0) {
+ dev_err(&spi->dev, "setupxfer returned %d\n", ret);
+ return ret;
+ }
+
+ dev_dbg(&spi->dev, "%s: mode %d, %u bpw\n",
+ __FUNCTION__, spi->mode, spi->bits_per_word);
+
+ return 0;
+}
+
+static int glamo_spi_probe(struct platform_device *pdev)
+{
+ struct spi_master *master;
+ struct glamo_spi *sp;
+ int ret;
+ int i;
+
+ master = spi_alloc_master(&pdev->dev, sizeof(struct glamo_spi));
+ if (master == NULL) {
+ dev_err(&pdev->dev, "failed to allocate spi master\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ sp = spi_master_get_devdata(master);
+ memset(sp, 0, sizeof(struct glamo_spi));
+
+ sp->master = spi_master_get(master);
+ sp->info = pdev->dev.platform_data;
+ if (!sp->info) {
+ dev_err(&pdev->dev, "can't operate without platform data\n");
+ ret = -EIO;
+ goto err_no_pdev;
+ }
+ dev_dbg(&pdev->dev, "sp->info(pdata) = %p\n", sp->info);
+
+ sp->dev = &pdev->dev;
+
+ platform_set_drvdata(pdev, sp);
+
+ sp->bitbang.master = sp->master;
+ sp->bitbang.setup_transfer = glamo_spi_setupxfer;
+ sp->bitbang.chipselect = glamo_spi_chipsel;
+ sp->bitbang.txrx_bufs = glamo_spi_txrx;
+ sp->bitbang.master->setup = glamo_spi_setup;
+
+ ret = spi_bitbang_start(&sp->bitbang);
+ if (ret)
+ goto err_no_bitbang;
+
+ /* register the chips to go with the board */
+
+ glamofb_cmd_mode(sp->info->glamofb_handle, 1);
+
+ for (i = 0; i < sp->info->board_size; i++) {
+ dev_info(&pdev->dev, "registering %p: %s\n",
+ &sp->info->board_info[i],
+ sp->info->board_info[i].modalias);
+
+ sp->info->board_info[i].controller_data = sp;
+ spi_new_device(master, sp->info->board_info + i);
+ }
+
+ return 0;
+
+err_no_bitbang:
+ platform_set_drvdata(pdev, NULL);
+err_no_pdev:
+ spi_master_put(sp->bitbang.master);
+err:
+ return ret;
+
+}
+
+static int glamo_spi_remove(struct platform_device *pdev)
+{
+ struct glamo_spi *sp = platform_get_drvdata(pdev);
+
+ spi_bitbang_stop(&sp->bitbang);
+ spi_master_put(sp->bitbang.master);
+
+ return 0;
+}
+
+#define glamo_spi_suspend NULL
+#define glamo_spi_resume NULL
+
+static struct platform_driver glamo_spi_drv = {
+ .probe = glamo_spi_probe,
+ .remove = glamo_spi_remove,
+ .suspend = glamo_spi_suspend,
+ .resume = glamo_spi_resume,
+ .driver = {
+ .name = "glamo-lcm-spi",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init glamo_spi_init(void)
+{
+ return platform_driver_register(&glamo_spi_drv);
+}
+
+static void __exit glamo_spi_exit(void)
+{
+ platform_driver_unregister(&glamo_spi_drv);
+}
+
+module_init(glamo_spi_init);
+module_exit(glamo_spi_exit);
+
+MODULE_DESCRIPTION("Smedia Glamo 336x/337x LCM serial command SPI Driver");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>")
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-mci.c
@@ -0,0 +1,1133 @@
+/*
+ * linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
+ *
+ * Copyright (C) 2007 Openmoko, Inc, Andy Green <andy@openmoko.com>
+ * Based on S3C MMC driver that was:
+ * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/pcf50633.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/dma.h>
+#include <asm/dma-mapping.h>
+#include <asm/io.h>
+
+#include "glamo-mci.h"
+#include "glamo-core.h"
+#include "glamo-regs.h"
+
+/* from glamo-core.c */
+extern struct glamo_mci_pdata glamo_mci_def_pdata;
+
+static spinlock_t clock_lock;
+
+#define DRIVER_NAME "glamo-mci"
+#define RESSIZE(ressource) (((ressource)->end - (ressource)->start) + 1)
+
+static void glamo_mci_send_request(struct mmc_host *mmc);
+
+/*
+ * Max SD clock rate
+ *
+ * held at /(3 + 1) due to concerns of 100R recommended series resistor
+ * allows 16MHz @ 4-bit --> 8MBytes/sec raw
+ *
+ * you can override this on kernel commandline using
+ *
+ * glamo_mci.sd_max_clk=10000000
+ *
+ * for example
+ */
+
+static int sd_max_clk = 50000000 / 3;
+module_param(sd_max_clk, int, 0644);
+
+/*
+ * Slow SD clock rate
+ *
+ * you can override this on kernel commandline using
+ *
+ * glamo_mci.sd_slow_ratio=8
+ *
+ * for example
+ *
+ * platform callback is used to decide effective clock rate, if not
+ * defined then max is used, if defined and returns nonzero, rate is
+ * divided by this factor
+ */
+
+static int sd_slow_ratio = 8;
+module_param(sd_slow_ratio, int, 0644);
+
+/*
+ * Post-power SD clock rate
+ *
+ * you can override this on kernel commandline using
+ *
+ * glamo_mci.sd_post_power_clock=1000000
+ *
+ * for example
+ *
+ * After changing power to card, clock is held at this rate until first bulk
+ * transfer completes
+ */
+
+static int sd_post_power_clock = 1000000;
+module_param(sd_post_power_clock, int, 0644);
+
+
+/*
+ * SD Signal drive strength
+ *
+ * you can override this on kernel commandline using
+ *
+ * glamo_mci.sd_drive=0
+ *
+ * for example
+ */
+
+static int sd_drive;
+module_param(sd_drive, int, 0644);
+
+/*
+ * SD allow SD clock to run while idle
+ *
+ * you can override this on kernel commandline using
+ *
+ * glamo_mci.sd_idleclk=0
+ *
+ * for example
+ */
+
+static int sd_idleclk = 0; /* disallow idle clock by default */
+module_param(sd_idleclk, int, 0644);
+
+/* used to stash real idleclk state in suspend: we force it to run in there */
+static int suspend_sd_idleclk;
+
+
+unsigned char CRC7(u8 * pu8, int cnt)
+{
+ u8 crc = 0;
+
+ while (cnt--) {
+ int n;
+ u8 d = *pu8++;
+ for (n = 0; n < 8; n++) {
+ crc <<= 1;
+ if ((d & 0x80) ^ (crc & 0x80))
+ crc ^= 0x09;
+ d <<= 1;
+ }
+ }
+ return (crc << 1) | 1;
+}
+
+static int get_data_buffer(struct glamo_mci_host *host,
+ volatile u32 *words, volatile u16 **pointer)
+{
+ struct scatterlist *sg;
+
+ *words = 0;
+ *pointer = NULL;
+
+ if (host->pio_active == XFER_NONE)
+ return -EINVAL;
+
+ if ((!host->mrq) || (!host->mrq->data))
+ return -EINVAL;
+
+ if (host->pio_sgptr >= host->mrq->data->sg_len) {
+ dev_dbg(&host->pdev->dev, "no more buffers (%i/%i)\n",
+ host->pio_sgptr, host->mrq->data->sg_len);
+ return -EBUSY;
+ }
+ sg = &host->mrq->data->sg[host->pio_sgptr];
+
+ *words = sg->length >> 1; /* we are working with a 16-bit data bus */
+ *pointer = page_address(sg_page(sg)) + sg->offset;
+
+ BUG_ON(((long)(*pointer)) & 1);
+
+ host->pio_sgptr++;
+
+ /* dev_info(&host->pdev->dev, "new buffer (%i/%i)\n",
+ host->pio_sgptr, host->mrq->data->sg_len); */
+ return 0;
+}
+
+static void do_pio_read(struct glamo_mci_host *host)
+{
+ int res;
+ u16 __iomem *from_ptr = host->base_data + (RESSIZE(host->mem_data) /
+ sizeof(u16) / 2);
+#ifdef DEBUG
+ u16 * block;
+#endif
+
+ while (1) {
+ res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
+ if (res) {
+ host->pio_active = XFER_NONE;
+ host->complete_what = COMPLETION_FINALIZE;
+
+ dev_dbg(&host->pdev->dev, "pio_read(): "
+ "complete (no more data).\n");
+ return;
+ }
+
+ dev_dbg(&host->pdev->dev, "pio_read(): host->pio_words: %d\n",
+ host->pio_words);
+
+ host->pio_count += host->pio_words << 1;
+
+#ifdef DEBUG
+ block = (u16 *)host->pio_ptr;
+ res = host->pio_words << 1;
+#endif
+#if 0
+ /* u16-centric memcpy */
+ while (host->pio_words--)
+ *host->pio_ptr++ = *from_ptr++;
+#else
+ /* memcpy can be faster? */
+ memcpy((void *)host->pio_ptr, from_ptr, host->pio_words << 1);
+ host->pio_ptr += host->pio_words;
+#endif
+
+#ifdef DEBUG
+ print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1,
+ (void *)block, res, 1);
+#endif
+ }
+}
+
+static int do_pio_write(struct glamo_mci_host *host)
+{
+ int res = 0;
+ volatile u16 __iomem *to_ptr = host->base_data;
+ int err = 0;
+
+ dev_dbg(&host->pdev->dev, "pio_write():\n");
+ while (!res) {
+ res = get_data_buffer(host, &host->pio_words, &host->pio_ptr);
+ if (res)
+ continue;
+
+ dev_dbg(&host->pdev->dev, "pio_write():new source: [%i]@[%p]\n",
+ host->pio_words, host->pio_ptr);
+
+ host->pio_count += host->pio_words << 1;
+ while (host->pio_words--)
+ writew(*host->pio_ptr++, to_ptr++);
+ }
+
+ dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
+ host->pio_active = XFER_NONE;
+ return err;
+}
+
+static void __glamo_mci_fix_card_div(struct glamo_mci_host *host, int div)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clock_lock, flags);
+
+ if (div < 0) {
+ /* stop clock - remove clock from divider input */
+ writew(readw(glamo_mci_def_pdata.pglamo->base +
+ GLAMO_REG_CLOCK_GEN5_1) & (~GLAMO_CLOCK_GEN51_EN_DIV_TCLK),
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
+
+ goto done;
+ } else {
+ /* set the nearest prescaler factor
+ *
+ * register shared with SCLK divisor -- no chance of race because
+ * we don't use sensor interface
+ */
+ writew((readw(glamo_mci_def_pdata.pglamo->base +
+ GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
+ /* enable clock to divider input */
+ writew(readw(glamo_mci_def_pdata.pglamo->base +
+ GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
+ }
+
+ if (host->force_slow_during_powerup)
+ div = host->clk_rate / sd_post_power_clock;
+ else
+ if (host->pdata->glamo_mci_use_slow)
+ if ((host->pdata->glamo_mci_use_slow)())
+ div = div * sd_slow_ratio;
+
+ if (div > 255)
+ div = 255;
+
+ /*
+ * set the nearest prescaler factor
+ *
+ * register shared with SCLK divisor -- no chance of race because
+ * we don't use sensor interface
+ */
+ writew((readw(glamo_mci_def_pdata.pglamo->base +
+ GLAMO_REG_CLOCK_GEN8) & 0xff00) | div,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN8);
+ /* enable clock to divider input */
+ writew(readw(glamo_mci_def_pdata.pglamo->base +
+ GLAMO_REG_CLOCK_GEN5_1) | GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_GEN5_1);
+
+done:
+ spin_unlock_irqrestore(&clock_lock, flags);
+}
+
+static int __glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq,
+ int *division)
+{
+ int div = 0;
+ int real_rate = 0;
+
+ if (freq) {
+ /* Set clock */
+ for (div = 0; div < 256; div++) {
+ real_rate = host->clk_rate / (div + 1);
+ if (real_rate <= freq)
+ break;
+ }
+ if (div > 255)
+ div = 255;
+
+ if (division)
+ *division = div;
+
+ __glamo_mci_fix_card_div(host, div);
+
+ } else {
+ /* stop clock */
+ if (division)
+ *division = 0xff;
+
+ if (!sd_idleclk && !host->force_slow_during_powerup)
+ /* clock off */
+ __glamo_mci_fix_card_div(host, -1);
+ }
+
+ return real_rate;
+}
+
+static void glamo_mci_irq(unsigned int irq, struct irq_desc *desc)
+{
+ struct glamo_mci_host *host = (struct glamo_mci_host *)
+ desc->handler_data;
+ u16 status;
+ struct mmc_command *cmd;
+ unsigned long iflags;
+
+ if (!host)
+ return;
+
+ if (host->suspending) { /* bad news, dangerous time */
+ dev_err(&host->pdev->dev, "****glamo_mci_irq before resumed\n");
+ return;
+ }
+
+ if (!host->mrq)
+ return;
+ cmd = host->mrq->cmd;
+ if (!cmd)
+ return;
+
+ spin_lock_irqsave(&host->complete_lock, iflags);
+
+ status = readw(host->base + GLAMO_REG_MMC_RB_STAT1);
+
+ /* ack this interrupt source */
+ writew(GLAMO_IRQ_MMC,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_IRQ_CLEAR);
+
+ if (status & (GLAMO_STAT1_MMC_RTOUT |
+ GLAMO_STAT1_MMC_DTOUT))
+ cmd->error = -ETIMEDOUT;
+ if (status & (GLAMO_STAT1_MMC_BWERR |
+ GLAMO_STAT1_MMC_BRERR))
+ cmd->error = -EILSEQ;
+ if (cmd->error) {
+ dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
+ goto done;
+ }
+
+ /* disable the initial slow start after first bulk transfer */
+ if (host->force_slow_during_powerup)
+ host->force_slow_during_powerup--;
+
+ if (host->pio_active == XFER_READ)
+ do_pio_read(host);
+
+ host->mrq->data->bytes_xfered = host->pio_count;
+ dev_dbg(&host->pdev->dev, "status = 0x%04x count=%d\n",
+ status, host->pio_count);
+
+ /* issue STOP if we have been given one to use */
+ if (host->mrq->stop) {
+ host->cmd_is_stop = 1;
+ glamo_mci_send_request(host->mmc);
+ host->cmd_is_stop = 0;
+ }
+
+ if (!sd_idleclk && !host->force_slow_during_powerup)
+ /* clock off */
+ __glamo_mci_fix_card_div(host, -1);
+
+done:
+ host->complete_what = COMPLETION_NONE;
+ host->mrq = NULL;
+ mmc_request_done(host->mmc, cmd->mrq);
+ spin_unlock_irqrestore(&host->complete_lock, iflags);
+}
+
+static int glamo_mci_send_command(struct glamo_mci_host *host,
+ struct mmc_command *cmd)
+{
+ u8 u8a[6];
+ u16 fire = 0;
+
+ /* if we can't do it, reject as busy */
+ if (!readw(host->base + GLAMO_REG_MMC_RB_STAT1) &
+ GLAMO_STAT1_MMC_IDLE) {
+ host->mrq = NULL;
+ cmd->error = -EBUSY;
+ mmc_request_done(host->mmc, host->mrq);
+ return -EBUSY;
+ }
+
+ /* create an array in wire order for CRC computation */
+ u8a[0] = 0x40 | (cmd->opcode & 0x3f);
+ u8a[1] = (u8)(cmd->arg >> 24);
+ u8a[2] = (u8)(cmd->arg >> 16);
+ u8a[3] = (u8)(cmd->arg >> 8);
+ u8a[4] = (u8)cmd->arg;
+ u8a[5] = CRC7(&u8a[0], 5); /* CRC7 on first 5 bytes of packet */
+
+ /* issue the wire-order array including CRC in register order */
+ writew((u8a[4] << 8) | u8a[5], host->base + GLAMO_REG_MMC_CMD_REG1);
+ writew((u8a[2] << 8) | u8a[3], host->base + GLAMO_REG_MMC_CMD_REG2);
+ writew((u8a[0] << 8) | u8a[1], host->base + GLAMO_REG_MMC_CMD_REG3);
+
+ /* command index toggle */
+ fire |= (host->ccnt & 1) << 12;
+
+ /* set type of command */
+ switch (mmc_cmd_type(cmd)) {
+ case MMC_CMD_BC:
+ fire |= GLAMO_FIRE_MMC_CMDT_BNR;
+ break;
+ case MMC_CMD_BCR:
+ fire |= GLAMO_FIRE_MMC_CMDT_BR;
+ break;
+ case MMC_CMD_AC:
+ fire |= GLAMO_FIRE_MMC_CMDT_AND;
+ break;
+ case MMC_CMD_ADTC:
+ fire |= GLAMO_FIRE_MMC_CMDT_AD;
+ break;
+ }
+ /*
+ * if it expects a response, set the type expected
+ *
+ * R1, Length : 48bit, Normal response
+ * R1b, Length : 48bit, same R1, but added card busy status
+ * R2, Length : 136bit (really 128 bits with CRC snipped)
+ * R3, Length : 48bit (OCR register value)
+ * R4, Length : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
+ * R5, Length : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
+ * R6, Length : 48bit (RCA register)
+ * R7, Length : 48bit (interface condition, VHS(voltage supplied),
+ * check pattern, CRC7)
+ */
+ switch (mmc_resp_type(cmd)) {
+ case MMC_RSP_R6: /* same index as R7 and R1 */
+ fire |= GLAMO_FIRE_MMC_RSPT_R1;
+ break;
+ case MMC_RSP_R1B:
+ fire |= GLAMO_FIRE_MMC_RSPT_R1b;
+ break;
+ case MMC_RSP_R2:
+ fire |= GLAMO_FIRE_MMC_RSPT_R2;
+ break;
+ case MMC_RSP_R3:
+ fire |= GLAMO_FIRE_MMC_RSPT_R3;
+ break;
+ /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
+ }
+ /*
+ * From the command index, set up the command class in the host ctrllr
+ *
+ * missing guys present on chip but couldn't figure out how to use yet:
+ * 0x0 "stream read"
+ * 0x9 "cancel running command"
+ */
+ switch (cmd->opcode) {
+ case MMC_READ_SINGLE_BLOCK:
+ fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
+ break;
+ case MMC_SWITCH: /* 64 byte payload */
+ case 0x33: /* observed issued by MCI */
+ case MMC_READ_MULTIPLE_BLOCK:
+ /* we will get an interrupt off this */
+ if (!cmd->mrq->stop)
+ /* multiblock no stop */
+ fire |= GLAMO_FIRE_MMC_CC_MBRNS;
+ else
+ /* multiblock with stop */
+ fire |= GLAMO_FIRE_MMC_CC_MBRS;
+ break;
+ case MMC_WRITE_BLOCK:
+ fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
+ break;
+ case MMC_WRITE_MULTIPLE_BLOCK:
+ if (cmd->mrq->stop)
+ /* multiblock with stop */
+ fire |= GLAMO_FIRE_MMC_CC_MBWS;
+ else
+// /* multiblock NO stop-- 'RESERVED'? */
+ fire |= GLAMO_FIRE_MMC_CC_MBWNS;
+ break;
+ case MMC_STOP_TRANSMISSION:
+ fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
+ break;
+ default:
+ fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
+ break;
+ }
+
+ /* always largest timeout */
+ writew(0xfff, host->base + GLAMO_REG_MMC_TIMEOUT);
+
+ /* Generate interrupt on txfer */
+ writew((readw(host->base + GLAMO_REG_MMC_BASIC) & 0x3e) |
+ 0x0800 | GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
+ GLAMO_BASIC_MMC_EN_COMPL_INT | (sd_drive << 6),
+ host->base + GLAMO_REG_MMC_BASIC);
+
+ /* send the command out on the wire */
+ /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
+ writew(fire, host->base + GLAMO_REG_MMC_CMD_FIRE);
+ cmd->error = 0;
+ return 0;
+}
+
+static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
+ struct mmc_data *data)
+{
+ /*
+ * the S-Media-internal RAM offset for our MMC buffer
+ * Read is halfway up the buffer and write is at the start
+ */
+ if (data->flags & MMC_DATA_READ) {
+ writew((u16)(GLAMO_FB_SIZE + (RESSIZE(host->mem_data) / 2)),
+ host->base + GLAMO_REG_MMC_WDATADS1);
+ writew((u16)((GLAMO_FB_SIZE +
+ (RESSIZE(host->mem_data) / 2)) >> 16),
+ host->base + GLAMO_REG_MMC_WDATADS2);
+ } else {
+ writew((u16)GLAMO_FB_SIZE, host->base +
+ GLAMO_REG_MMC_RDATADS1);
+ writew((u16)(GLAMO_FB_SIZE >> 16), host->base +
+ GLAMO_REG_MMC_RDATADS2);
+ }
+
+ /* set up the block info */
+ writew(data->blksz, host->base + GLAMO_REG_MMC_DATBLKLEN);
+ writew(data->blocks, host->base + GLAMO_REG_MMC_DATBLKCNT);
+ dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
+ data->blksz, data->blocks);
+ host->pio_sgptr = 0;
+ host->pio_words = 0;
+ host->pio_count = 0;
+ host->pio_active = 0;
+ /* if write, prep the write into the shared RAM before the command */
+ if (data->flags & MMC_DATA_WRITE) {
+ host->pio_active = XFER_WRITE;
+ return do_pio_write(host);
+ }
+ host->pio_active = XFER_READ;
+ return 0;
+}
+
+static void glamo_mci_send_request(struct mmc_host *mmc)
+{
+ struct glamo_mci_host *host = mmc_priv(mmc);
+ struct mmc_request *mrq = host->mrq;
+ struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
+ u16 * pu16 = (u16 *)&cmd->resp[0];
+ u16 * reg_resp = (u16 *)(host->base + GLAMO_REG_MMC_CMD_RSP1);
+ u16 status;
+ int n;
+ int timeout = 1000000;
+ int insanity_timeout = 1000000;
+
+ if (host->suspending) {
+ dev_err(&host->pdev->dev, "IGNORING glamo_mci_send_request while "
+ "suspended\n");
+ cmd->error = -EIO;
+ if (cmd->data)
+ cmd->data->error = -EIO;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+
+ host->ccnt++;
+ /*
+ * somehow 2.6.24 MCI manages to issue MMC_WRITE_BLOCK *without* the
+ * MMC_DATA_WRITE flag, WTF? Work around the madness.
+ */
+ if (cmd->opcode == MMC_WRITE_BLOCK)
+ if (mrq->data)
+ mrq->data->flags |= MMC_DATA_WRITE;
+
+ /* this guy has data to read/write? */
+ if ((!host->cmd_is_stop) && cmd->data) {
+ int res;
+ host->dcnt++;
+ res = glamo_mci_prepare_pio(host, cmd->data);
+ if (res) {
+ cmd->error = -EIO;
+ cmd->data->error = -EIO;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+ }
+
+ dev_dbg(&host->pdev->dev,"cmd 0x%x, "
+ "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
+ cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
+ cmd->flags);
+
+ /* resume requested clock rate
+ * scale it down by sd_slow_ratio if platform requests it
+ */
+ __glamo_mci_fix_card_div(host, host->clk_div);
+
+ if (glamo_mci_send_command(host, cmd))
+ goto bail;
+
+ /* we are deselecting card? because it isn't going to ack then... */
+ if ((cmd->opcode == 7) && (cmd->arg == 0))
+ goto done;
+
+ /*
+ * we must spin until response is ready or timed out
+ * -- we don't get interrupts unless there is a bulk rx
+ */
+ do
+ status = readw(host->base + GLAMO_REG_MMC_RB_STAT1);
+ while (((((status >> 15) & 1) != (host->ccnt & 1)) ||
+ (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
+ GLAMO_STAT1_MMC_RTOUT |
+ GLAMO_STAT1_MMC_DTOUT |
+ GLAMO_STAT1_MMC_BWERR |
+ GLAMO_STAT1_MMC_BRERR)))) && (insanity_timeout--));
+
+ if (insanity_timeout < 0)
+ dev_info(&host->pdev->dev, "command timeout, continuing\n");
+
+ if (status & (GLAMO_STAT1_MMC_RTOUT |
+ GLAMO_STAT1_MMC_DTOUT))
+ cmd->error = -ETIMEDOUT;
+ if (status & (GLAMO_STAT1_MMC_BWERR |
+ GLAMO_STAT1_MMC_BRERR))
+ cmd->error = -EILSEQ;
+
+ if (host->cmd_is_stop)
+ goto bail;
+
+ if (cmd->error) {
+ dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
+ goto done;
+ }
+ /*
+ * mangle the response registers in two different exciting
+ * undocumented ways discovered by trial and error
+ */
+ if (mmc_resp_type(cmd) == MMC_RSP_R2)
+ /* grab the response */
+ for (n = 0; n < 8; n++) /* super mangle power 1 */
+ pu16[n ^ 6] = readw(&reg_resp[n]);
+ else
+ for (n = 0; n < 3; n++) /* super mangle power 2 */
+ pu16[n] = (readw(&reg_resp[n]) >> 8) |
+ (readw(&reg_resp[n + 1]) << 8);
+ /*
+ * if we don't have bulk data to take care of, we're done
+ */
+ if (!cmd->data)
+ goto done;
+ if (!(cmd->data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)))
+ goto done;
+
+ /*
+ * Otherwise can can use the interrupt as async completion --
+ * if there is read data coming, or we wait for write data to complete,
+ * exit without mmc_request_done() as the payload interrupt
+ * will service it
+ */
+ dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
+ /*
+ * if the glamo INT# line isn't wired (*cough* it can happen)
+ * I'm afraid we have to spin on the IRQ status bit and "be
+ * our own INT# line"
+ */
+ if (!glamo_mci_def_pdata.pglamo->irq_works) {
+ /*
+ * we have faith we will get an "interrupt"...
+ * but something insane like suspend problems can mean
+ * we spin here forever, so we timeout after a LONG time
+ */
+ while ((!(readw(glamo_mci_def_pdata.pglamo->base +
+ GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
+ (timeout--))
+ ;
+
+ if (timeout < 0) {
+ if (cmd->data->error)
+ cmd->data->error = -ETIMEDOUT;
+ dev_err(&host->pdev->dev, "Payload timeout\n");
+ goto bail;
+ }
+
+ /* yay we are an interrupt controller! -- call the ISR
+ * it will stop clock to card
+ */
+ glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC),
+ irq_desc + IRQ_GLAMO(GLAMO_IRQIDX_MMC));
+ }
+ return;
+
+done:
+ host->complete_what = COMPLETION_NONE;
+ host->mrq = NULL;
+ mmc_request_done(host->mmc, cmd->mrq);
+bail:
+ if (!sd_idleclk && !host->force_slow_during_powerup)
+ /* stop the clock to card */
+ __glamo_mci_fix_card_div(host, -1);
+}
+
+static void glamo_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct glamo_mci_host *host = mmc_priv(mmc);
+
+ host->cmd_is_stop = 0;
+ host->mrq = mrq;
+ glamo_mci_send_request(mmc);
+}
+
+#if 1
+static void glamo_mci_reset(struct glamo_mci_host *host)
+{
+ if (host->suspending) {
+ dev_err(&host->pdev->dev, "IGNORING glamo_mci_reset while "
+ "suspended\n");
+ return;
+ }
+ dev_dbg(&host->pdev->dev, "******* glamo_mci_reset\n");
+ /* reset MMC controller */
+ writew(GLAMO_CLOCK_MMC_RESET | GLAMO_CLOCK_MMC_DG_TCLK |
+ GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
+ GLAMO_CLOCK_MMC_EN_M9CLK,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
+ udelay(10);
+ /* and disable reset */
+ writew(GLAMO_CLOCK_MMC_DG_TCLK |
+ GLAMO_CLOCK_MMC_EN_TCLK | GLAMO_CLOCK_MMC_DG_M9CLK |
+ GLAMO_CLOCK_MMC_EN_M9CLK,
+ glamo_mci_def_pdata.pglamo->base + GLAMO_REG_CLOCK_MMC);
+}
+#endif
+static inline int glamo_mci_get_mv(int vdd)
+{
+ int mv = 1650;
+
+ if (vdd > 7)
+ mv += 350 + 100 * (vdd - 8);
+
+ return mv;
+}
+
+static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct glamo_mci_host *host = mmc_priv(mmc);
+ struct regulator *regulator;
+ int n = 0;
+ int div;
+ int powering = 0;
+ int mv;
+
+ if (host->suspending) {
+ dev_err(&host->pdev->dev, "IGNORING glamo_mci_set_ios while "
+ "suspended\n");
+ return;
+ }
+
+ regulator = host->regulator;
+
+ /* Set power */
+ switch(ios->power_mode) {
+ case MMC_POWER_UP:
+ if (host->pdata->glamo_can_set_mci_power()) {
+ mv = glamo_mci_get_mv(ios->vdd);
+ regulator_set_voltage(regulator, mv * 1000, mv * 1000);
+ regulator_enable(regulator);
+ }
+ break;
+ case MMC_POWER_ON:
+ /*
+ * we should use very slow clock until first bulk
+ * transfer completes OK
+ */
+ host->force_slow_during_powerup = 1;
+
+ if (host->vdd_current != ios->vdd) {
+ if (host->pdata->glamo_can_set_mci_power()) {
+ mv = glamo_mci_get_mv(ios->vdd);
+ regulator_set_voltage(regulator, mv * 1000, mv * 1000);
+ printk(KERN_INFO "SD power -> %dmV\n", mv);
+ }
+ host->vdd_current = ios->vdd;
+ }
+ if (host->power_mode_current == MMC_POWER_OFF) {
+ glamo_engine_enable(glamo_mci_def_pdata.pglamo,
+ GLAMO_ENGINE_MMC);
+ powering = 1;
+ }
+ break;
+
+ case MMC_POWER_OFF:
+ default:
+ if (host->power_mode_current == MMC_POWER_OFF)
+ break;
+ /* never want clocking with dead card */
+ __glamo_mci_fix_card_div(host, -1);
+
+ glamo_engine_disable(glamo_mci_def_pdata.pglamo,
+ GLAMO_ENGINE_MMC);
+ regulator_disable(regulator);
+ host->vdd_current = -1;
+ break;
+ }
+ host->power_mode_current = ios->power_mode;
+
+ host->real_rate = __glamo_mci_set_card_clock(host, ios->clock, &div);
+ host->clk_div = div;
+
+ /* after power-up, we are meant to give it >= 74 clocks so it can
+ * initialize itself. Doubt any modern cards need it but anyway...
+ */
+ if (powering)
+ mdelay(1);
+
+ if (!sd_idleclk && !host->force_slow_during_powerup)
+ /* stop the clock to card, because we are idle until transfer */
+ __glamo_mci_fix_card_div(host, -1);
+
+ if ((ios->power_mode == MMC_POWER_ON) ||
+ (ios->power_mode == MMC_POWER_UP)) {
+ dev_info(&host->pdev->dev,
+ "powered (vdd = %d) clk: %lukHz div=%d (req: %ukHz). "
+ "Bus width=%d\n",(int)ios->vdd,
+ host->real_rate / 1000, (int)host->clk_div,
+ ios->clock / 1000, (int)ios->bus_width);
+ } else
+ dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
+
+ /* set bus width */
+ host->bus_width = ios->bus_width;
+ if (host->bus_width == MMC_BUS_WIDTH_4)
+ n = GLAMO_BASIC_MMC_EN_4BIT_DATA;
+ writew((readw(host->base + GLAMO_REG_MMC_BASIC) &
+ (~(GLAMO_BASIC_MMC_EN_4BIT_DATA |
+ GLAMO_BASIC_MMC_EN_DR_STR0 |
+ GLAMO_BASIC_MMC_EN_DR_STR1))) | n |
+ sd_drive << 6, host->base + GLAMO_REG_MMC_BASIC);
+}
+
+
+/*
+ * no physical write protect supported by us
+ */
+static int glamo_mci_get_ro(struct mmc_host *mmc)
+{
+ return 0;
+}
+
+static struct mmc_host_ops glamo_mci_ops = {
+ .request = glamo_mci_request,
+ .set_ios = glamo_mci_set_ios,
+ .get_ro = glamo_mci_get_ro,
+};
+
+static int glamo_mci_probe(struct platform_device *pdev)
+{
+ struct mmc_host *mmc;
+ struct glamo_mci_host *host;
+ int ret;
+
+ dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
+
+ mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
+ if (!mmc) {
+ ret = -ENOMEM;
+ goto probe_out;
+ }
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+ host->pdev = pdev;
+ host->pdata = &glamo_mci_def_pdata;
+ host->power_mode_current = MMC_POWER_OFF;
+
+ host->complete_what = COMPLETION_NONE;
+ host->pio_active = XFER_NONE;
+
+ spin_lock_init(&host->complete_lock);
+
+ host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!host->mem) {
+ dev_err(&pdev->dev,
+ "failed to get io memory region resouce.\n");
+
+ ret = -ENOENT;
+ goto probe_free_host;
+ }
+
+ host->mem = request_mem_region(host->mem->start,
+ RESSIZE(host->mem), pdev->name);
+
+ if (!host->mem) {
+ dev_err(&pdev->dev, "failed to request io memory region.\n");
+ ret = -ENOENT;
+ goto probe_free_host;
+ }
+
+ host->base = ioremap(host->mem->start, RESSIZE(host->mem));
+ if (!host->base) {
+ dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
+ ret = -EINVAL;
+ goto probe_free_mem_region;
+ }
+
+ host->regulator = regulator_get(&pdev->dev, "SD_3V3");
+ if (!host->regulator) {
+ dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
+ return -ENODEV;
+ }
+
+ /* set the handler for our bit of the shared chip irq register */
+ set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq);
+ /* stash host as our handler's private data */
+ set_irq_data(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
+
+ /* Get ahold of our data buffer we use for data in and out on MMC */
+ host->mem_data = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!host->mem_data) {
+ dev_err(&pdev->dev,
+ "failed to get io memory region resource.\n");
+ ret = -ENOENT;
+ goto probe_iounmap;
+ }
+
+ host->mem_data = request_mem_region(host->mem_data->start,
+ RESSIZE(host->mem_data), pdev->name);
+
+ if (!host->mem_data) {
+ dev_err(&pdev->dev, "failed to request io memory region.\n");
+ ret = -ENOENT;
+ goto probe_iounmap;
+ }
+ host->base_data = ioremap(host->mem_data->start,
+ RESSIZE(host->mem_data));
+ host->data_max_size = RESSIZE(host->mem_data);
+
+ if (host->base_data == 0) {
+ dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
+ ret = -EINVAL;
+ goto probe_free_mem_region_data;
+ }
+
+ host->vdd_current = 0;
+ host->clk_rate = 50000000; /* really it's 49152000 */
+ host->clk_div = 16;
+
+ /* explain our host controller capabilities */
+ mmc->ops = &glamo_mci_ops;
+ mmc->ocr_avail = host->pdata->ocr_avail;
+ mmc->caps = MMC_CAP_4_BIT_DATA |
+ MMC_CAP_MMC_HIGHSPEED |
+ MMC_CAP_SD_HIGHSPEED;
+ mmc->f_min = host->clk_rate / 256;
+ mmc->f_max = sd_max_clk;
+
+ mmc->max_blk_count = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
+ mmc->max_blk_size = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
+ mmc->max_req_size = RESSIZE(host->mem_data) / 2;
+ mmc->max_seg_size = mmc->max_req_size;
+ mmc->max_phys_segs = 1; /* hw doesn't talk about segs??? */
+ mmc->max_hw_segs = 1;
+
+ dev_info(&host->pdev->dev, "probe: mapped mci_base:%p irq:%u.\n",
+ host->base, host->irq);
+
+ platform_set_drvdata(pdev, mmc);
+
+ glamo_engine_enable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
+ glamo_mci_reset(host);
+
+ if ((ret = mmc_add_host(mmc))) {
+ dev_err(&pdev->dev, "failed to add mmc host.\n");
+ goto probe_free_mem_region_data;
+ }
+
+ dev_info(&pdev->dev,"initialisation done.\n");
+ return 0;
+
+ probe_free_mem_region_data:
+ release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
+
+ probe_iounmap:
+ iounmap(host->base);
+
+ probe_free_mem_region:
+ release_mem_region(host->mem->start, RESSIZE(host->mem));
+
+ probe_free_host:
+ mmc_free_host(mmc);
+ probe_out:
+ return ret;
+}
+
+static int glamo_mci_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct glamo_mci_host *host = mmc_priv(mmc);
+ struct regulator *regulator;
+
+ mmc_remove_host(mmc);
+ /* stop using our handler, revert it to default */
+ set_irq_handler(IRQ_GLAMO(GLAMO_IRQIDX_MMC), handle_level_irq);
+ iounmap(host->base);
+ iounmap(host->base_data);
+ release_mem_region(host->mem->start, RESSIZE(host->mem));
+ release_mem_region(host->mem_data->start, RESSIZE(host->mem_data));
+
+ regulator = host->regulator;
+ regulator_put(regulator);
+
+ mmc_free_host(mmc);
+
+ glamo_engine_disable(glamo_mci_def_pdata.pglamo, GLAMO_ENGINE_MMC);
+ return 0;
+}
+
+
+#ifdef CONFIG_PM
+
+static int glamo_mci_suspend(struct platform_device *dev, pm_message_t state)
+{
+ struct mmc_host *mmc = platform_get_drvdata(dev);
+ struct glamo_mci_host *host = mmc_priv(mmc);
+ int ret;
+
+ /*
+ * possible workaround for SD corruption during suspend - resume
+ * make sure the clock was running during suspend and consequently
+ * resume
+ */
+ __glamo_mci_fix_card_div(host, host->clk_div);
+
+ /* we are going to do more commands to override this in
+ * mmc_suspend_host(), so we need to change sd_idleclk for the
+ * duration as well
+ */
+ suspend_sd_idleclk = sd_idleclk;
+ sd_idleclk = 1;
+
+ ret = mmc_suspend_host(mmc, state);
+
+ host->suspending++;
+ /* so that when we resume, we use any modified max rate */
+ mmc->f_max = sd_max_clk;
+
+ return ret;
+}
+
+int glamo_mci_resume(struct platform_device *dev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(dev);
+ struct glamo_mci_host *host = mmc_priv(mmc);
+ int ret;
+
+ sd_idleclk = 1;
+
+ glamo_engine_enable(host->pdata->pglamo, GLAMO_ENGINE_MMC);
+ glamo_mci_reset(host);
+
+ host->suspending--;
+
+ ret = mmc_resume_host(mmc);
+
+ /* put sd_idleclk back to pre-suspend state */
+ sd_idleclk = suspend_sd_idleclk;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(glamo_mci_resume);
+
+#else /* CONFIG_PM */
+#define glamo_mci_suspend NULL
+#define glamo_mci_resume NULL
+#endif /* CONFIG_PM */
+
+
+static struct platform_driver glamo_mci_driver =
+{
+ .driver.name = "glamo-mci",
+ .probe = glamo_mci_probe,
+ .remove = glamo_mci_remove,
+ .suspend = glamo_mci_suspend,
+ .resume = glamo_mci_resume,
+};
+
+static int __init glamo_mci_init(void)
+{
+ spin_lock_init(&clock_lock);
+ platform_driver_register(&glamo_mci_driver);
+ return 0;
+}
+
+static void __exit glamo_mci_exit(void)
+{
+ platform_driver_unregister(&glamo_mci_driver);
+}
+
+module_init(glamo_mci_init);
+module_exit(glamo_mci_exit);
+
+MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-mci.h
@@ -0,0 +1,83 @@
+/*
+ * linux/drivers/mmc/host/glamo-mmc.h - GLAMO MCI driver
+ *
+ * Copyright (C) 2007-2008 Openmoko, Inc, Andy Green <andy@openmoko.com>
+ * based on S3C MMC driver -->
+ * Copyright (C) 2004-2006 Thomas Kleffel, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/regulator/consumer.h>
+
+enum glamo_mci_waitfor {
+ COMPLETION_NONE,
+ COMPLETION_FINALIZE,
+ COMPLETION_CMDSENT,
+ COMPLETION_RSPFIN,
+ COMPLETION_XFERFINISH,
+ COMPLETION_XFERFINISH_RSPFIN,
+};
+
+struct glamo_mci_host {
+ struct platform_device *pdev;
+ struct glamo_mci_pdata *pdata;
+ struct mmc_host *mmc;
+ struct resource *mem;
+ struct resource *mem_data;
+ struct clk *clk;
+ void __iomem *base;
+ u16 __iomem *base_data;
+ int irq;
+ int irq_cd;
+ int dma;
+ int data_max_size;
+
+ int suspending;
+
+ int power_mode_current;
+ unsigned int vdd_current;
+
+ unsigned long clk_rate;
+ unsigned long clk_div;
+ unsigned long real_rate;
+ u8 prescaler;
+
+ int force_slow_during_powerup;
+
+ unsigned sdiimsk;
+ int dodma;
+
+ volatile int dmatogo;
+
+ struct mmc_request *mrq;
+ int cmd_is_stop;
+
+ spinlock_t complete_lock;
+ volatile enum glamo_mci_waitfor
+ complete_what;
+
+ volatile int dma_complete;
+
+ volatile u32 pio_sgptr;
+ volatile u32 pio_words;
+ volatile u32 pio_count;
+ volatile u16 *pio_ptr;
+#define XFER_NONE 0
+#define XFER_READ 1
+#define XFER_WRITE 2
+ volatile u32 pio_active;
+
+ int bus_width;
+
+ char dbgmsg_cmd[301];
+ char dbgmsg_dat[301];
+ volatile char *status;
+
+ unsigned int ccnt, dcnt;
+ struct tasklet_struct pio_tasklet;
+
+ struct regulator *regulator;
+};
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-regs.h
@@ -0,0 +1,632 @@
+#ifndef _GLAMO_REGS_H
+#define _GLAMO_REGS_H
+
+/* Smedia Glamo 336x/337x driver
+ *
+ * (C) 2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+enum glamo_regster_offsets {
+ GLAMO_REGOFS_GENERIC = 0x0000,
+ GLAMO_REGOFS_HOSTBUS = 0x0200,
+ GLAMO_REGOFS_MEMORY = 0x0300,
+ GLAMO_REGOFS_VIDCAP = 0x0400,
+ GLAMO_REGOFS_ISP = 0x0500,
+ GLAMO_REGOFS_JPEG = 0x0800,
+ GLAMO_REGOFS_MPEG = 0x0c00,
+ GLAMO_REGOFS_LCD = 0x1100,
+ GLAMO_REGOFS_MMC = 0x1400,
+ GLAMO_REGOFS_MPROC0 = 0x1500,
+ GLAMO_REGOFS_MPROC1 = 0x1580,
+ GLAMO_REGOFS_CMDQUEUE = 0x1600,
+ GLAMO_REGOFS_RISC = 0x1680,
+ GLAMO_REGOFS_2D = 0x1700,
+ GLAMO_REGOFS_3D = 0x1b00,
+ GLAMO_REGOFS_END = 0x2400,
+};
+
+
+enum glamo_register_generic {
+ GLAMO_REG_GCONF1 = 0x0000,
+ GLAMO_REG_GCONF2 = 0x0002,
+#define GLAMO_REG_DEVICE_ID GLAMO_REG_GCONF2
+ GLAMO_REG_GCONF3 = 0x0004,
+#define GLAMO_REG_REVISION_ID GLAMO_REG_GCONF3
+ GLAMO_REG_IRQ_GEN1 = 0x0006,
+#define GLAMO_REG_IRQ_ENABLE GLAMO_REG_IRQ_GEN1
+ GLAMO_REG_IRQ_GEN2 = 0x0008,
+#define GLAMO_REG_IRQ_SET GLAMO_REG_IRQ_GEN2
+ GLAMO_REG_IRQ_GEN3 = 0x000a,
+#define GLAMO_REG_IRQ_CLEAR GLAMO_REG_IRQ_GEN3
+ GLAMO_REG_IRQ_GEN4 = 0x000c,
+#define GLAMO_REG_IRQ_STATUS GLAMO_REG_IRQ_GEN4
+ GLAMO_REG_CLOCK_HOST = 0x0010,
+ GLAMO_REG_CLOCK_MEMORY = 0x0012,
+ GLAMO_REG_CLOCK_LCD = 0x0014,
+ GLAMO_REG_CLOCK_MMC = 0x0016,
+ GLAMO_REG_CLOCK_ISP = 0x0018,
+ GLAMO_REG_CLOCK_JPEG = 0x001a,
+ GLAMO_REG_CLOCK_3D = 0x001c,
+ GLAMO_REG_CLOCK_2D = 0x001e,
+ GLAMO_REG_CLOCK_RISC1 = 0x0020, /* 3365 only? */
+ GLAMO_REG_CLOCK_RISC2 = 0x0022, /* 3365 only? */
+ GLAMO_REG_CLOCK_MPEG = 0x0024,
+ GLAMO_REG_CLOCK_MPROC = 0x0026,
+
+ GLAMO_REG_CLOCK_GEN5_1 = 0x0030,
+ GLAMO_REG_CLOCK_GEN5_2 = 0x0032,
+ GLAMO_REG_CLOCK_GEN6 = 0x0034,
+ GLAMO_REG_CLOCK_GEN7 = 0x0036,
+ GLAMO_REG_CLOCK_GEN8 = 0x0038,
+ GLAMO_REG_CLOCK_GEN9 = 0x003a,
+ GLAMO_REG_CLOCK_GEN10 = 0x003c,
+ GLAMO_REG_CLOCK_GEN11 = 0x003e,
+ GLAMO_REG_PLL_GEN1 = 0x0040,
+ GLAMO_REG_PLL_GEN2 = 0x0042,
+ GLAMO_REG_PLL_GEN3 = 0x0044,
+ GLAMO_REG_PLL_GEN4 = 0x0046,
+ GLAMO_REG_PLL_GEN5 = 0x0048,
+ GLAMO_REG_GPIO_GEN1 = 0x0050,
+ GLAMO_REG_GPIO_GEN2 = 0x0052,
+ GLAMO_REG_GPIO_GEN3 = 0x0054,
+ GLAMO_REG_GPIO_GEN4 = 0x0056,
+ GLAMO_REG_GPIO_GEN5 = 0x0058,
+ GLAMO_REG_GPIO_GEN6 = 0x005a,
+ GLAMO_REG_GPIO_GEN7 = 0x005c,
+ GLAMO_REG_GPIO_GEN8 = 0x005e,
+ GLAMO_REG_GPIO_GEN9 = 0x0060,
+ GLAMO_REG_GPIO_GEN10 = 0x0062,
+ GLAMO_REG_DFT_GEN1 = 0x0070,
+ GLAMO_REG_DFT_GEN2 = 0x0072,
+ GLAMO_REG_DFT_GEN3 = 0x0074,
+ GLAMO_REG_DFT_GEN4 = 0x0076,
+
+ GLAMO_REG_DFT_GEN5 = 0x01e0,
+ GLAMO_REG_DFT_GEN6 = 0x01f0,
+};
+
+#define GLAMO_REG_HOSTBUS(x) (GLAMO_REGOFS_HOSTBUS-2+(x*2))
+
+#define REG_MEM(x) (GLAMO_REGOFS_MEMORY+(x))
+#define GLAMO_REG_MEM_TIMING(x) (GLAMO_REG_MEM_TIMING1-2+(x*2))
+
+enum glamo_register_mem {
+ GLAMO_REG_MEM_TYPE = REG_MEM(0x00),
+ GLAMO_REG_MEM_GEN = REG_MEM(0x02),
+ GLAMO_REG_MEM_TIMING1 = REG_MEM(0x04),
+ GLAMO_REG_MEM_TIMING2 = REG_MEM(0x06),
+ GLAMO_REG_MEM_TIMING3 = REG_MEM(0x08),
+ GLAMO_REG_MEM_TIMING4 = REG_MEM(0x0a),
+ GLAMO_REG_MEM_TIMING5 = REG_MEM(0x0c),
+ GLAMO_REG_MEM_TIMING6 = REG_MEM(0x0e),
+ GLAMO_REG_MEM_TIMING7 = REG_MEM(0x10),
+ GLAMO_REG_MEM_TIMING8 = REG_MEM(0x12),
+ GLAMO_REG_MEM_TIMING9 = REG_MEM(0x14),
+ GLAMO_REG_MEM_TIMING10 = REG_MEM(0x16),
+ GLAMO_REG_MEM_TIMING11 = REG_MEM(0x18),
+ GLAMO_REG_MEM_POWER1 = REG_MEM(0x1a),
+ GLAMO_REG_MEM_POWER2 = REG_MEM(0x1c),
+ GLAMO_REG_MEM_LCD_BUF1 = REG_MEM(0x1e),
+ GLAMO_REG_MEM_LCD_BUF2 = REG_MEM(0x20),
+ GLAMO_REG_MEM_LCD_BUF3 = REG_MEM(0x22),
+ GLAMO_REG_MEM_LCD_BUF4 = REG_MEM(0x24),
+ GLAMO_REG_MEM_BIST1 = REG_MEM(0x26),
+ GLAMO_REG_MEM_BIST2 = REG_MEM(0x28),
+ GLAMO_REG_MEM_BIST3 = REG_MEM(0x2a),
+ GLAMO_REG_MEM_BIST4 = REG_MEM(0x2c),
+ GLAMO_REG_MEM_BIST5 = REG_MEM(0x2e),
+ GLAMO_REG_MEM_MAH1 = REG_MEM(0x30),
+ GLAMO_REG_MEM_MAH2 = REG_MEM(0x32),
+ GLAMO_REG_MEM_DRAM1 = REG_MEM(0x34),
+ GLAMO_REG_MEM_DRAM2 = REG_MEM(0x36),
+ GLAMO_REG_MEM_CRC = REG_MEM(0x38),
+};
+
+#define GLAMO_MEM_TYPE_MASK 0x03
+
+enum glamo_reg_mem_dram1 {
+ /* b0 - b10 == refresh period, 1 -> 2048 clocks */
+ GLAMO_MEM_DRAM1_EN_GATE_CLK = (1 << 11),
+ GLAMO_MEM_DRAM1_SELF_REFRESH = (1 << 12),
+ GLAMO_MEM_DRAM1_EN_GATE_CKE = (1 << 13),
+ GLAMO_MEM_DRAM1_EN_DRAM_REFRESH = (1 << 14),
+ GLAMO_MEM_DRAM1_EN_MODEREG_SET = (1 << 15),
+};
+
+enum glamo_reg_mem_dram2 {
+ GLAMO_MEM_DRAM2_DEEP_PWRDOWN = (1 << 12),
+};
+
+enum glamo_irq_index {
+ GLAMO_IRQIDX_HOSTBUS = 0,
+ GLAMO_IRQIDX_JPEG = 1,
+ GLAMO_IRQIDX_MPEG = 2,
+ GLAMO_IRQIDX_MPROC1 = 3,
+ GLAMO_IRQIDX_MPROC0 = 4,
+ GLAMO_IRQIDX_CMDQUEUE = 5,
+ GLAMO_IRQIDX_2D = 6,
+ GLAMO_IRQIDX_MMC = 7,
+ GLAMO_IRQIDX_RISC = 8,
+};
+
+enum glamo_irq {
+ GLAMO_IRQ_HOSTBUS = (1 << GLAMO_IRQIDX_HOSTBUS),
+ GLAMO_IRQ_JPEG = (1 << GLAMO_IRQIDX_JPEG),
+ GLAMO_IRQ_MPEG = (1 << GLAMO_IRQIDX_MPEG),
+ GLAMO_IRQ_MPROC1 = (1 << GLAMO_IRQIDX_MPROC1),
+ GLAMO_IRQ_MPROC0 = (1 << GLAMO_IRQIDX_MPROC0),
+ GLAMO_IRQ_CMDQUEUE = (1 << GLAMO_IRQIDX_CMDQUEUE),
+ GLAMO_IRQ_2D = (1 << GLAMO_IRQIDX_2D),
+ GLAMO_IRQ_MMC = (1 << GLAMO_IRQIDX_MMC),
+ GLAMO_IRQ_RISC = (1 << GLAMO_IRQIDX_RISC),
+};
+
+enum glamo_reg_clock_host {
+ GLAMO_CLOCK_HOST_DG_BCLK = 0x0001,
+ GLAMO_CLOCK_HOST_DG_M0CLK = 0x0004,
+ GLAMO_CLOCK_HOST_RESET = 0x1000,
+};
+
+enum glamo_reg_clock_mem {
+ GLAMO_CLOCK_MEM_DG_M1CLK = 0x0001,
+ GLAMO_CLOCK_MEM_EN_M1CLK = 0x0002,
+ GLAMO_CLOCK_MEM_DG_MOCACLK = 0x0004,
+ GLAMO_CLOCK_MEM_EN_MOCACLK = 0x0008,
+ GLAMO_CLOCK_MEM_RESET = 0x1000,
+ GLAMO_CLOCK_MOCA_RESET = 0x2000,
+};
+
+enum glamo_reg_clock_lcd {
+ GLAMO_CLOCK_LCD_DG_DCLK = 0x0001,
+ GLAMO_CLOCK_LCD_EN_DCLK = 0x0002,
+ GLAMO_CLOCK_LCD_DG_DMCLK = 0x0004,
+ GLAMO_CLOCK_LCD_EN_DMCLK = 0x0008,
+ //
+ GLAMO_CLOCK_LCD_EN_DHCLK = 0x0020,
+ GLAMO_CLOCK_LCD_DG_M5CLK = 0x0040,
+ GLAMO_CLOCK_LCD_EN_M5CLK = 0x0080,
+ GLAMO_CLOCK_LCD_RESET = 0x1000,
+};
+
+enum glamo_reg_clock_mmc {
+ GLAMO_CLOCK_MMC_DG_TCLK = 0x0001,
+ GLAMO_CLOCK_MMC_EN_TCLK = 0x0002,
+ GLAMO_CLOCK_MMC_DG_M9CLK = 0x0004,
+ GLAMO_CLOCK_MMC_EN_M9CLK = 0x0008,
+ GLAMO_CLOCK_MMC_RESET = 0x1000,
+};
+
+enum glamo_reg_basic_mmc {
+ /* set to disable CRC error rejection */
+ GLAMO_BASIC_MMC_DISABLE_CRC = 0x0001,
+ /* enable completion interrupt */
+ GLAMO_BASIC_MMC_EN_COMPL_INT = 0x0002,
+ /* stop MMC clock while enforced idle waiting for data from card */
+ GLAMO_BASIC_MMC_NO_CLK_RD_WAIT = 0x0004,
+ /* 0 = 1-bit bus to card, 1 = use 4-bit bus (has to be negotiated) */
+ GLAMO_BASIC_MMC_EN_4BIT_DATA = 0x0008,
+ /* enable 75K pullups on D3..D0 */
+ GLAMO_BASIC_MMC_EN_DATA_PUPS = 0x0010,
+ /* enable 75K pullup on CMD */
+ GLAMO_BASIC_MMC_EN_CMD_PUP = 0x0020,
+ /* IO drive strength 00=weak -> 11=strongest */
+ GLAMO_BASIC_MMC_EN_DR_STR0 = 0x0040,
+ GLAMO_BASIC_MMC_EN_DR_STR1 = 0x0080,
+ /* TCLK delay stage A, 0000 = 500ps --> 1111 = 8ns */
+ GLAMO_BASIC_MMC_EN_TCLK_DLYA0 = 0x0100,
+ GLAMO_BASIC_MMC_EN_TCLK_DLYA1 = 0x0200,
+ GLAMO_BASIC_MMC_EN_TCLK_DLYA2 = 0x0400,
+ GLAMO_BASIC_MMC_EN_TCLK_DLYA3 = 0x0800,
+ /* TCLK delay stage B (cumulative), 0000 = 500ps --> 1111 = 8ns */
+ GLAMO_BASIC_MMC_EN_TCLK_DLYB0 = 0x1000,
+ GLAMO_BASIC_MMC_EN_TCLK_DLYB1 = 0x2000,
+ GLAMO_BASIC_MMC_EN_TCLK_DLYB2 = 0x4000,
+ GLAMO_BASIC_MMC_EN_TCLK_DLYB3 = 0x8000,
+};
+
+enum glamo_reg_stat1_mmc {
+ /* command "counter" (really: toggle) */
+ GLAMO_STAT1_MMC_CMD_CTR = 0x8000,
+ /* engine is idle */
+ GLAMO_STAT1_MMC_IDLE = 0x4000,
+ /* readback response is ready */
+ GLAMO_STAT1_MMC_RB_RRDY = 0x0200,
+ /* readback data is ready */
+ GLAMO_STAT1_MMC_RB_DRDY = 0x0100,
+ /* no response timeout */
+ GLAMO_STAT1_MMC_RTOUT = 0x0020,
+ /* no data timeout */
+ GLAMO_STAT1_MMC_DTOUT = 0x0010,
+ /* CRC error on block write */
+ GLAMO_STAT1_MMC_BWERR = 0x0004,
+ /* CRC error on block read */
+ GLAMO_STAT1_MMC_BRERR = 0x0002
+};
+
+enum glamo_reg_fire_mmc {
+ /* command "counter" (really: toggle)
+ * the STAT1 register reflects this so you can ensure you don't look
+ * at status for previous command
+ */
+ GLAMO_FIRE_MMC_CMD_CTR = 0x8000,
+ /* sets kind of response expected */
+ GLAMO_FIRE_MMC_RES_MASK = 0x0700,
+ /* sets command type */
+ GLAMO_FIRE_MMC_TYP_MASK = 0x00C0,
+ /* sets command class */
+ GLAMO_FIRE_MMC_CLS_MASK = 0x000F,
+};
+
+enum glamo_fire_mmc_response_types {
+ GLAMO_FIRE_MMC_RSPT_R1 = 0x0000,
+ GLAMO_FIRE_MMC_RSPT_R1b = 0x0100,
+ GLAMO_FIRE_MMC_RSPT_R2 = 0x0200,
+ GLAMO_FIRE_MMC_RSPT_R3 = 0x0300,
+ GLAMO_FIRE_MMC_RSPT_R4 = 0x0400,
+ GLAMO_FIRE_MMC_RSPT_R5 = 0x0500,
+};
+
+enum glamo_fire_mmc_command_types {
+ /* broadcast, no response */
+ GLAMO_FIRE_MMC_CMDT_BNR = 0x0000,
+ /* broadcast, with response */
+ GLAMO_FIRE_MMC_CMDT_BR = 0x0040,
+ /* addressed, no data */
+ GLAMO_FIRE_MMC_CMDT_AND = 0x0080,
+ /* addressed, with data */
+ GLAMO_FIRE_MMC_CMDT_AD = 0x00C0,
+};
+
+enum glamo_fire_mmc_command_class {
+ /* "Stream Read" */
+ GLAMO_FIRE_MMC_CC_STRR = 0x0000,
+ /* Single Block Read */
+ GLAMO_FIRE_MMC_CC_SBR = 0x0001,
+ /* Multiple Block Read With Stop */
+ GLAMO_FIRE_MMC_CC_MBRS = 0x0002,
+ /* Multiple Block Read No Stop */
+ GLAMO_FIRE_MMC_CC_MBRNS = 0x0003,
+ /* RESERVED for "Stream Write" */
+ GLAMO_FIRE_MMC_CC_STRW = 0x0004,
+ /* "Stream Write" */
+ GLAMO_FIRE_MMC_CC_SBW = 0x0005,
+ /* RESERVED for Multiple Block Write With Stop */
+ GLAMO_FIRE_MMC_CC_MBWS = 0x0006,
+ /* Multiple Block Write No Stop */
+ GLAMO_FIRE_MMC_CC_MBWNS = 0x0007,
+ /* STOP command */
+ GLAMO_FIRE_MMC_CC_STOP = 0x0008,
+ /* Cancel on Running Command */
+ GLAMO_FIRE_MMC_CC_CANCL = 0x0009,
+ /* "Basic Command" */
+ GLAMO_FIRE_MMC_CC_BASIC = 0x000a,
+};
+
+/* these are offsets from the start of the MMC register region */
+enum glamo_register_mmc {
+ /* MMC command, b15..8 = cmd arg b7..0; b7..1 = CRC; b0 = end bit */
+ GLAMO_REG_MMC_CMD_REG1 = 0x00,
+ /* MMC command, b15..0 = cmd arg b23 .. 8 */
+ GLAMO_REG_MMC_CMD_REG2 = 0x02,
+ /* MMC command, b15=start, b14=transmission,
+ * b13..8=cmd idx, b7..0=cmd arg b31..24
+ */
+ GLAMO_REG_MMC_CMD_REG3 = 0x04,
+ GLAMO_REG_MMC_CMD_FIRE = 0x06,
+ GLAMO_REG_MMC_CMD_RSP1 = 0x10,
+ GLAMO_REG_MMC_CMD_RSP2 = 0x12,
+ GLAMO_REG_MMC_CMD_RSP3 = 0x14,
+ GLAMO_REG_MMC_CMD_RSP4 = 0x16,
+ GLAMO_REG_MMC_CMD_RSP5 = 0x18,
+ GLAMO_REG_MMC_CMD_RSP6 = 0x1a,
+ GLAMO_REG_MMC_CMD_RSP7 = 0x1c,
+ GLAMO_REG_MMC_CMD_RSP8 = 0x1e,
+ GLAMO_REG_MMC_RB_STAT1 = 0x20,
+ GLAMO_REG_MMC_RB_BLKCNT = 0x22,
+ GLAMO_REG_MMC_RB_BLKLEN = 0x24,
+ GLAMO_REG_MMC_BASIC = 0x30,
+ GLAMO_REG_MMC_RDATADS1 = 0x34,
+ GLAMO_REG_MMC_RDATADS2 = 0x36,
+ GLAMO_REG_MMC_WDATADS1 = 0x38,
+ GLAMO_REG_MMC_WDATADS2 = 0x3a,
+ GLAMO_REG_MMC_DATBLKCNT = 0x3c,
+ GLAMO_REG_MMC_DATBLKLEN = 0x3e,
+ GLAMO_REG_MMC_TIMEOUT = 0x40,
+
+};
+
+enum glamo_reg_clock_isp {
+ GLAMO_CLOCK_ISP_DG_I1CLK = 0x0001,
+ GLAMO_CLOCK_ISP_EN_I1CLK = 0x0002,
+ GLAMO_CLOCK_ISP_DG_CCLK = 0x0004,
+ GLAMO_CLOCK_ISP_EN_CCLK = 0x0008,
+ //
+ GLAMO_CLOCK_ISP_EN_SCLK = 0x0020,
+ GLAMO_CLOCK_ISP_DG_M2CLK = 0x0040,
+ GLAMO_CLOCK_ISP_EN_M2CLK = 0x0080,
+ GLAMO_CLOCK_ISP_DG_M15CLK = 0x0100,
+ GLAMO_CLOCK_ISP_EN_M15CLK = 0x0200,
+ GLAMO_CLOCK_ISP1_RESET = 0x1000,
+ GLAMO_CLOCK_ISP2_RESET = 0x2000,
+};
+
+enum glamo_reg_clock_jpeg {
+ GLAMO_CLOCK_JPEG_DG_JCLK = 0x0001,
+ GLAMO_CLOCK_JPEG_EN_JCLK = 0x0002,
+ GLAMO_CLOCK_JPEG_DG_M3CLK = 0x0004,
+ GLAMO_CLOCK_JPEG_EN_M3CLK = 0x0008,
+ GLAMO_CLOCK_JPEG_RESET = 0x1000,
+};
+
+enum glamo_reg_clock_2d {
+ GLAMO_CLOCK_2D_DG_GCLK = 0x0001,
+ GLAMO_CLOCK_2D_EN_GCLK = 0x0002,
+ GLAMO_CLOCK_2D_DG_M7CLK = 0x0004,
+ GLAMO_CLOCK_2D_EN_M7CLK = 0x0008,
+ GLAMO_CLOCK_2D_DG_M6CLK = 0x0010,
+ GLAMO_CLOCK_2D_EN_M6CLK = 0x0020,
+ GLAMO_CLOCK_2D_RESET = 0x1000,
+ GLAMO_CLOCK_2D_CQ_RESET = 0x2000,
+};
+
+enum glamo_reg_clock_3d {
+ GLAMO_CLOCK_3D_DG_ECLK = 0x0001,
+ GLAMO_CLOCK_3D_EN_ECLK = 0x0002,
+ GLAMO_CLOCK_3D_DG_RCLK = 0x0004,
+ GLAMO_CLOCK_3D_EN_RCLK = 0x0008,
+ GLAMO_CLOCK_3D_DG_M8CLK = 0x0010,
+ GLAMO_CLOCK_3D_EN_M8CLK = 0x0020,
+ GLAMO_CLOCK_3D_BACK_RESET = 0x1000,
+ GLAMO_CLOCK_3D_FRONT_RESET = 0x2000,
+};
+
+enum glamo_reg_clock_mpeg {
+ GLAMO_CLOCK_MPEG_DG_X0CLK = 0x0001,
+ GLAMO_CLOCK_MPEG_EN_X0CLK = 0x0002,
+ GLAMO_CLOCK_MPEG_DG_X1CLK = 0x0004,
+ GLAMO_CLOCK_MPEG_EN_X1CLK = 0x0008,
+ GLAMO_CLOCK_MPEG_DG_X2CLK = 0x0010,
+ GLAMO_CLOCK_MPEG_EN_X2CLK = 0x0020,
+ GLAMO_CLOCK_MPEG_DG_X3CLK = 0x0040,
+ GLAMO_CLOCK_MPEG_EN_X3CLK = 0x0080,
+ GLAMO_CLOCK_MPEG_DG_X4CLK = 0x0100,
+ GLAMO_CLOCK_MPEG_EN_X4CLK = 0x0200,
+ GLAMO_CLOCK_MPEG_DG_X6CLK = 0x0400,
+ GLAMO_CLOCK_MPEG_EN_X6CLK = 0x0800,
+ GLAMO_CLOCK_MPEG_ENC_RESET = 0x1000,
+ GLAMO_CLOCK_MPEG_DEC_RESET = 0x2000,
+};
+
+enum glamo_reg_clock51 {
+ GLAMO_CLOCK_GEN51_EN_DIV_MCLK = 0x0001,
+ GLAMO_CLOCK_GEN51_EN_DIV_SCLK = 0x0002,
+ GLAMO_CLOCK_GEN51_EN_DIV_JCLK = 0x0004,
+ GLAMO_CLOCK_GEN51_EN_DIV_DCLK = 0x0008,
+ GLAMO_CLOCK_GEN51_EN_DIV_DMCLK = 0x0010,
+ GLAMO_CLOCK_GEN51_EN_DIV_DHCLK = 0x0020,
+ GLAMO_CLOCK_GEN51_EN_DIV_GCLK = 0x0040,
+ GLAMO_CLOCK_GEN51_EN_DIV_TCLK = 0x0080,
+ /* FIXME: higher bits */
+};
+
+enum glamo_reg_hostbus2 {
+ GLAMO_HOSTBUS2_MMIO_EN_ISP = 0x0001,
+ GLAMO_HOSTBUS2_MMIO_EN_JPEG = 0x0002,
+ GLAMO_HOSTBUS2_MMIO_EN_MPEG = 0x0004,
+ GLAMO_HOSTBUS2_MMIO_EN_LCD = 0x0008,
+ GLAMO_HOSTBUS2_MMIO_EN_MMC = 0x0010,
+ GLAMO_HOSTBUS2_MMIO_EN_MICROP0 = 0x0020,
+ GLAMO_HOSTBUS2_MMIO_EN_MICROP1 = 0x0040,
+ GLAMO_HOSTBUS2_MMIO_EN_CQ = 0x0080,
+ GLAMO_HOSTBUS2_MMIO_EN_RISC = 0x0100,
+ GLAMO_HOSTBUS2_MMIO_EN_2D = 0x0200,
+ GLAMO_HOSTBUS2_MMIO_EN_3D = 0x0400,
+};
+
+/* LCD Controller */
+
+#define REG_LCD(x) (x)
+enum glamo_reg_lcd {
+ GLAMO_REG_LCD_MODE1 = REG_LCD(0x00),
+ GLAMO_REG_LCD_MODE2 = REG_LCD(0x02),
+ GLAMO_REG_LCD_MODE3 = REG_LCD(0x04),
+ GLAMO_REG_LCD_WIDTH = REG_LCD(0x06),
+ GLAMO_REG_LCD_HEIGHT = REG_LCD(0x08),
+ GLAMO_REG_LCD_POLARITY = REG_LCD(0x0a),
+ GLAMO_REG_LCD_A_BASE1 = REG_LCD(0x0c),
+ GLAMO_REG_LCD_A_BASE2 = REG_LCD(0x0e),
+ GLAMO_REG_LCD_B_BASE1 = REG_LCD(0x10),
+ GLAMO_REG_LCD_B_BASE2 = REG_LCD(0x12),
+ GLAMO_REG_LCD_C_BASE1 = REG_LCD(0x14),
+ GLAMO_REG_LCD_C_BASE2 = REG_LCD(0x16),
+ GLAMO_REG_LCD_PITCH = REG_LCD(0x18),
+ /* RES */
+ GLAMO_REG_LCD_HORIZ_TOTAL = REG_LCD(0x1c),
+ /* RES */
+ GLAMO_REG_LCD_HORIZ_RETR_START = REG_LCD(0x20),
+ /* RES */
+ GLAMO_REG_LCD_HORIZ_RETR_END = REG_LCD(0x24),
+ /* RES */
+ GLAMO_REG_LCD_HORIZ_DISP_START = REG_LCD(0x28),
+ /* RES */
+ GLAMO_REG_LCD_HORIZ_DISP_END = REG_LCD(0x2c),
+ /* RES */
+ GLAMO_REG_LCD_VERT_TOTAL = REG_LCD(0x30),
+ /* RES */
+ GLAMO_REG_LCD_VERT_RETR_START = REG_LCD(0x34),
+ /* RES */
+ GLAMO_REG_LCD_VERT_RETR_END = REG_LCD(0x38),
+ /* RES */
+ GLAMO_REG_LCD_VERT_DISP_START = REG_LCD(0x3c),
+ /* RES */
+ GLAMO_REG_LCD_VERT_DISP_END = REG_LCD(0x40),
+ /* RES */
+ GLAMO_REG_LCD_POL = REG_LCD(0x44),
+ GLAMO_REG_LCD_DATA_START = REG_LCD(0x46),
+ GLAMO_REG_LCD_FRATE_CONTRO = REG_LCD(0x48),
+ GLAMO_REG_LCD_DATA_CMD_HDR = REG_LCD(0x4a),
+ GLAMO_REG_LCD_SP_START = REG_LCD(0x4c),
+ GLAMO_REG_LCD_SP_END = REG_LCD(0x4e),
+ GLAMO_REG_LCD_CURSOR_BASE1 = REG_LCD(0x50),
+ GLAMO_REG_LCD_CURSOR_BASE2 = REG_LCD(0x52),
+ GLAMO_REG_LCD_CURSOR_PITCH = REG_LCD(0x54),
+ GLAMO_REG_LCD_CURSOR_X_SIZE = REG_LCD(0x56),
+ GLAMO_REG_LCD_CURSOR_Y_SIZE = REG_LCD(0x58),
+ GLAMO_REG_LCD_CURSOR_X_POS = REG_LCD(0x5a),
+ GLAMO_REG_LCD_CURSOR_Y_POS = REG_LCD(0x5c),
+ GLAMO_REG_LCD_CURSOR_PRESET = REG_LCD(0x5e),
+ GLAMO_REG_LCD_CURSOR_FG_COLOR = REG_LCD(0x60),
+ /* RES */
+ GLAMO_REG_LCD_CURSOR_BG_COLOR = REG_LCD(0x64),
+ /* RES */
+ GLAMO_REG_LCD_CURSOR_DST_COLOR = REG_LCD(0x68),
+ /* RES */
+ GLAMO_REG_LCD_STATUS1 = REG_LCD(0x80),
+ GLAMO_REG_LCD_STATUS2 = REG_LCD(0x82),
+ GLAMO_REG_LCD_STATUS3 = REG_LCD(0x84),
+ GLAMO_REG_LCD_STATUS4 = REG_LCD(0x86),
+ /* RES */
+ GLAMO_REG_LCD_COMMAND1 = REG_LCD(0xa0),
+ GLAMO_REG_LCD_COMMAND2 = REG_LCD(0xa2),
+ /* RES */
+ GLAMO_REG_LCD_WFORM_DELAY1 = REG_LCD(0xb0),
+ GLAMO_REG_LCD_WFORM_DELAY2 = REG_LCD(0xb2),
+ /* RES */
+ GLAMO_REG_LCD_GAMMA_CORR = REG_LCD(0x100),
+ /* RES */
+ GLAMO_REG_LCD_GAMMA_R_ENTRY01 = REG_LCD(0x110),
+ GLAMO_REG_LCD_GAMMA_R_ENTRY23 = REG_LCD(0x112),
+ GLAMO_REG_LCD_GAMMA_R_ENTRY45 = REG_LCD(0x114),
+ GLAMO_REG_LCD_GAMMA_R_ENTRY67 = REG_LCD(0x116),
+ GLAMO_REG_LCD_GAMMA_R_ENTRY8 = REG_LCD(0x118),
+ /* RES */
+ GLAMO_REG_LCD_GAMMA_G_ENTRY01 = REG_LCD(0x130),
+ GLAMO_REG_LCD_GAMMA_G_ENTRY23 = REG_LCD(0x132),
+ GLAMO_REG_LCD_GAMMA_G_ENTRY45 = REG_LCD(0x134),
+ GLAMO_REG_LCD_GAMMA_G_ENTRY67 = REG_LCD(0x136),
+ GLAMO_REG_LCD_GAMMA_G_ENTRY8 = REG_LCD(0x138),
+ /* RES */
+ GLAMO_REG_LCD_GAMMA_B_ENTRY01 = REG_LCD(0x150),
+ GLAMO_REG_LCD_GAMMA_B_ENTRY23 = REG_LCD(0x152),
+ GLAMO_REG_LCD_GAMMA_B_ENTRY45 = REG_LCD(0x154),
+ GLAMO_REG_LCD_GAMMA_B_ENTRY67 = REG_LCD(0x156),
+ GLAMO_REG_LCD_GAMMA_B_ENTRY8 = REG_LCD(0x158),
+ /* RES */
+ GLAMO_REG_LCD_SRAM_DRIVING1 = REG_LCD(0x160),
+ GLAMO_REG_LCD_SRAM_DRIVING2 = REG_LCD(0x162),
+ GLAMO_REG_LCD_SRAM_DRIVING3 = REG_LCD(0x164),
+};
+
+enum glamo_reg_lcd_mode1 {
+ GLAMO_LCD_MODE1_PWRSAVE = 0x0001,
+ GLAMO_LCD_MODE1_PARTIAL_PRT = 0x0002,
+ GLAMO_LCD_MODE1_HWFLIP = 0x0004,
+ GLAMO_LCD_MODE1_LCD2 = 0x0008,
+ /* RES */
+ GLAMO_LCD_MODE1_PARTIAL_MODE = 0x0020,
+ GLAMO_LCD_MODE1_CURSOR_DSTCOLOR = 0x0040,
+ GLAMO_LCD_MODE1_PARTIAL_ENABLE = 0x0080,
+ GLAMO_LCD_MODE1_TVCLK_IN_ENABLE = 0x0100,
+ GLAMO_LCD_MODE1_HSYNC_HIGH_ACT = 0x0200,
+ GLAMO_LCD_MODE1_VSYNC_HIGH_ACT = 0x0400,
+ GLAMO_LCD_MODE1_HSYNC_FLIP = 0x0800,
+ GLAMO_LCD_MODE1_GAMMA_COR_EN = 0x1000,
+ GLAMO_LCD_MODE1_DITHER_EN = 0x2000,
+ GLAMO_LCD_MODE1_CURSOR_EN = 0x4000,
+ GLAMO_LCD_MODE1_ROTATE_EN = 0x8000,
+};
+
+enum glamo_reg_lcd_mode2 {
+ GLAMO_LCD_MODE2_CRC_CHECK_EN = 0x0001,
+ GLAMO_LCD_MODE2_DCMD_PER_LINE = 0x0002,
+ GLAMO_LCD_MODE2_NOUSE_BDEF = 0x0004,
+ GLAMO_LCD_MODE2_OUT_POS_MODE = 0x0008,
+ GLAMO_LCD_MODE2_FRATE_CTRL_EN = 0x0010,
+ GLAMO_LCD_MODE2_SINGLE_BUFFER = 0x0020,
+ GLAMO_LCD_MODE2_SER_LSB_TO_MSB = 0x0040,
+ /* FIXME */
+};
+
+enum glamo_reg_lcd_mode3 {
+ /* LCD color source data format */
+ GLAMO_LCD_SRC_RGB565 = 0x0000,
+ GLAMO_LCD_SRC_ARGB1555 = 0x4000,
+ GLAMO_LCD_SRC_ARGB4444 = 0x8000,
+ /* interface type */
+ GLAMO_LCD_MODE3_LCD = 0x1000,
+ GLAMO_LCD_MODE3_RGB = 0x0800,
+ GLAMO_LCD_MODE3_CPU = 0x0000,
+ /* mode */
+ GLAMO_LCD_MODE3_RGB332 = 0x0000,
+ GLAMO_LCD_MODE3_RGB444 = 0x0100,
+ GLAMO_LCD_MODE3_RGB565 = 0x0200,
+ GLAMO_LCD_MODE3_RGB666 = 0x0300,
+ /* depth */
+ GLAMO_LCD_MODE3_6BITS = 0x0000,
+ GLAMO_LCD_MODE3_8BITS = 0x0010,
+ GLAMO_LCD_MODE3_9BITS = 0x0020,
+ GLAMO_LCD_MODE3_16BITS = 0x0030,
+ GLAMO_LCD_MODE3_18BITS = 0x0040,
+};
+
+enum glamo_lcd_rot_mode {
+ GLAMO_LCD_ROT_MODE_0 = 0x0000,
+ GLAMO_LCD_ROT_MODE_180 = 0x2000,
+ GLAMO_LCD_ROT_MODE_MIRROR = 0x4000,
+ GLAMO_LCD_ROT_MODE_FLIP = 0x6000,
+ GLAMO_LCD_ROT_MODE_90 = 0x8000,
+ GLAMO_LCD_ROT_MODE_270 = 0xa000,
+};
+#define GLAMO_LCD_ROT_MODE_MASK 0xe000
+
+enum glamo_lcd_cmd_type {
+ GLAMO_LCD_CMD_TYPE_DISP = 0x0000,
+ GLAMO_LCD_CMD_TYPE_PARALLEL = 0x4000,
+ GLAMO_LCD_CMD_TYPE_SERIAL = 0x8000,
+ GLAMO_LCD_CMD_TYPE_SERIAL_DIRECT= 0xc000,
+};
+#define GLAMO_LCD_CMD_TYPE_MASK 0xc000
+
+enum glamo_lcd_cmds {
+ GLAMO_LCD_CMD_DATA_DISP_FIRE = 0x00,
+ GLAMO_LCD_CMD_DATA_DISP_SYNC = 0x01, /* RGB only */
+ /* switch to command mode, no display */
+ GLAMO_LCD_CMD_DATA_FIRE_NO_DISP = 0x02,
+ /* display until VSYNC, switch to command */
+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC = 0x11,
+ /* display until HSYNC, switch to command */
+ GLAMO_LCD_CMD_DATA_FIRE_HSYNC = 0x12,
+ /* display until VSYNC, 1 black frame, VSYNC, switch to command */
+ GLAMO_LCD_CMD_DATA_FIRE_VSYNC_B = 0x13,
+ /* don't care about display and switch to command */
+ GLAMO_LCD_CMD_DATA_FIRE_FREE = 0x14, /* RGB only */
+ /* don't care about display, keep data display but disable data,
+ * and switch to command */
+ GLAMO_LCD_CMD_DATA_FIRE_FREE_D = 0x15, /* RGB only */
+};
+
+enum glamo_core_revisions {
+ GLAMO_CORE_REV_A0 = 0x0000,
+ GLAMO_CORE_REV_A1 = 0x0001,
+ GLAMO_CORE_REV_A2 = 0x0002,
+ GLAMO_CORE_REV_A3 = 0x0003,
+};
+
+#endif /* _GLAMO_REGS_H */
--- /dev/null
+++ b/drivers/mfd/glamo/glamo-spi-gpio.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2007 Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ *
+ * Smedia Glamo GPIO based SPI driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver currently only implements a minimum subset of the hardware
+ * features, esp. those features that are required to drive the jbt6k74
+ * LCM controller asic in the TD028TTEC1 LCM.
+ *
+*/
+
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_bitbang.h>
+#include <linux/spi/glamo.h>
+
+#include <linux/glamofb.h>
+
+#include <mach/hardware.h>
+
+#include "glamo-core.h"
+#include "glamo-regs.h"
+
+struct glamo_spigpio {
+ struct spi_bitbang bitbang;
+ struct spi_master *master;
+ struct glamo_spigpio_info *info;
+ struct glamo_core *glamo;
+};
+
+static inline struct glamo_spigpio *to_sg(struct spi_device *spi)
+{
+ return spi->controller_data;
+}
+
+static inline void setsck(struct spi_device *dev, int on)
+{
+ struct glamo_spigpio *sg = to_sg(dev);
+ glamo_gpio_setpin(sg->glamo, sg->info->pin_clk, on ? 1 : 0);
+}
+
+static inline void setmosi(struct spi_device *dev, int on)
+{
+ struct glamo_spigpio *sg = to_sg(dev);
+ glamo_gpio_setpin(sg->glamo, sg->info->pin_mosi, on ? 1 : 0);
+}
+
+static inline u32 getmiso(struct spi_device *dev)
+{
+ struct glamo_spigpio *sg = to_sg(dev);
+ if (sg->info->pin_miso)
+ return glamo_gpio_getpin(sg->glamo, sg->info->pin_miso) ? 1 : 0;
+ else
+ return 0;
+}
+
+#define spidelay(x) ndelay(x)
+
+#define EXPAND_BITBANG_TXRX
+#include <linux/spi/spi_bitbang.h>
+
+static u32 glamo_spigpio_txrx_mode0(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits);
+}
+
+static u32 glamo_spigpio_txrx_mode1(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits);
+}
+
+static u32 glamo_spigpio_txrx_mode2(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits);
+}
+
+static u32 glamo_spigpio_txrx_mode3(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
+{
+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits);
+}
+
+
+#if 0
+static int glamo_spigpio_setupxfer(struct spi_device *spi,
+ struct spi_transfer *t)
+{
+ struct glamo_spi *gs = to_sg(spi);
+ unsigned int bpw;
+
+ bpw = t ? t->bits_per_word : spi->bits_per_word;
+
+ if (bpw != 9 && bpw != 8) {
+ dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+static void glamo_spigpio_chipsel(struct spi_device *spi, int value)
+{
+ struct glamo_spigpio *gs = to_sg(spi);
+#if 0
+ dev_dbg(&spi->dev, "chipsel %d: spi=%p, gs=%p, info=%p, handle=%p\n",
+ value, spi, gs, gs->info, gs->info->glamo);
+#endif
+ glamo_gpio_setpin(gs->glamo, gs->info->pin_cs, value ? 0 : 1);
+}
+
+
+static int glamo_spigpio_probe(struct platform_device *pdev)
+{
+ struct spi_master *master;
+ struct glamo_spigpio *sp;
+ int ret;
+ int i;
+
+ master = spi_alloc_master(&pdev->dev, sizeof(struct glamo_spigpio));
+ if (master == NULL) {
+ dev_err(&pdev->dev, "failed to allocate spi master\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ sp = spi_master_get_devdata(master);
+ platform_set_drvdata(pdev, sp);
+ sp->info = pdev->dev.platform_data;
+ if (!sp->info) {
+ dev_err(&pdev->dev, "can't operate without platform data\n");
+ ret = -EIO;
+ goto err_no_pdev;
+ }
+
+ master->num_chipselect = 1;
+ master->bus_num = 2; /* FIXME: use dynamic number */
+
+ sp->master = spi_master_get(master);
+ sp->glamo = sp->info->glamo;
+
+ sp->bitbang.master = sp->master;
+ sp->bitbang.chipselect = glamo_spigpio_chipsel;
+ sp->bitbang.txrx_word[SPI_MODE_0] = glamo_spigpio_txrx_mode0;
+ sp->bitbang.txrx_word[SPI_MODE_1] = glamo_spigpio_txrx_mode1;
+ sp->bitbang.txrx_word[SPI_MODE_2] = glamo_spigpio_txrx_mode2;
+ sp->bitbang.txrx_word[SPI_MODE_3] = glamo_spigpio_txrx_mode3;
+
+ /* set state of spi pins */
+ glamo_gpio_setpin(sp->glamo, sp->info->pin_clk, 0);
+ glamo_gpio_setpin(sp->glamo, sp->info->pin_mosi, 0);
+ glamo_gpio_setpin(sp->glamo, sp->info->pin_cs, 1);
+
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_clk);
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_mosi);
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_cs);
+ if (sp->info->pin_miso)
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_miso);
+
+ /* bring the LCM panel out of reset if it isn't already */
+
+ glamo_gpio_setpin(sp->glamo, GLAMO_GPIO4, 1);
+ glamo_gpio_cfgpin(sp->glamo, GLAMO_GPIO4_OUTPUT);
+ msleep(90);
+
+#if 0
+ sp->dev = &pdev->dev;
+
+ sp->bitbang.setup_transfer = glamo_spi_setupxfer;
+ sp->bitbang.txrx_bufs = glamo_spi_txrx;
+ sp->bitbang.master->setup = glamo_spi_setup;
+#endif
+
+ ret = spi_bitbang_start(&sp->bitbang);
+ if (ret)
+ goto err_no_bitbang;
+
+ /* register the chips to go with the board */
+
+ for (i = 0; i < sp->info->board_size; i++) {
+ dev_info(&pdev->dev, "registering %p: %s\n",
+ &sp->info->board_info[i],
+ sp->info->board_info[i].modalias);
+
+ sp->info->board_info[i].controller_data = sp;
+ spi_new_device(master, sp->info->board_info + i);
+ }
+
+ return 0;
+
+err_no_bitbang:
+ platform_set_drvdata(pdev, NULL);
+err_no_pdev:
+ spi_master_put(sp->bitbang.master);
+err:
+ return ret;
+
+}
+
+static int glamo_spigpio_remove(struct platform_device *pdev)
+{
+ struct glamo_spigpio *sp = platform_get_drvdata(pdev);
+
+ spi_bitbang_stop(&sp->bitbang);
+ spi_master_put(sp->bitbang.master);
+
+ return 0;
+}
+
+/*#define glamo_spigpio_suspend NULL
+#define glamo_spigpio_resume NULL
+*/
+
+
+#ifdef CONFIG_PM
+static int glamo_spigpio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ return 0;
+}
+
+static int glamo_spigpio_resume(struct platform_device *pdev)
+{
+ struct glamo_spigpio *sp = platform_get_drvdata(pdev);
+
+ if (!sp)
+ return 0;
+
+ /* set state of spi pins */
+ glamo_gpio_setpin(sp->glamo, sp->info->pin_clk, 0);
+ glamo_gpio_setpin(sp->glamo, sp->info->pin_mosi, 0);
+ glamo_gpio_setpin(sp->glamo, sp->info->pin_cs, 1);
+
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_clk);
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_mosi);
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_cs);
+ if (sp->info->pin_miso)
+ glamo_gpio_cfgpin(sp->glamo, sp->info->pin_miso);
+
+ return 0;
+}
+#endif
+
+static struct platform_driver glamo_spi_drv = {
+ .probe = glamo_spigpio_probe,
+ .remove = glamo_spigpio_remove,
+#ifdef CONFIG_PM
+ .suspend_late = glamo_spigpio_suspend,
+ .resume_early = glamo_spigpio_resume,
+#endif
+ .driver = {
+ .name = "glamo-spi-gpio",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init glamo_spi_init(void)
+{
+ return platform_driver_register(&glamo_spi_drv);
+}
+
+static void __exit glamo_spi_exit(void)
+{
+ platform_driver_unregister(&glamo_spi_drv);
+}
+
+module_init(glamo_spi_init);
+module_exit(glamo_spi_exit);
+
+MODULE_DESCRIPTION("Smedia Glamo 336x/337x LCM serial command SPI Driver");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>")
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/mfd/glamo/Kconfig
@@ -0,0 +1,44 @@
+config MFD_GLAMO
+ bool "Smedia Glamo 336x/337x support"
+ help
+ This enables the core driver for the Smedia Glamo 336x/337x
+ multi-function device. It includes irq_chip demultiplex as
+ well as clock / power management and GPIO support.
+
+config MFD_GLAMO_FB
+ tristate "Smedia Glamo 336x/337x framebuffer support"
+ depends on FB && MFD_GLAMO
+ help
+ Frame buffer driver for the LCD controller in the Smedia Glamo
+ 336x/337x.
+
+ This driver is also available as a module ( = code which can be
+ inserted and removed from the running kernel whenever you want). The
+ module will be called glamofb. If you want to compile it as a module,
+ say M here and read <file:Documentation/modules.txt>.
+
+ If unsure, say N.
+
+config MFD_GLAMO_SPI_GPIO
+ tristate "Glamo GPIO SPI bitbang support"
+ depends on MFD_GLAMO
+ help
+ Enable a bitbanging SPI adapter driver for the Smedia Glamo.
+
+config MFD_GLAMO_SPI_FB
+ tristate "Glamo LCM control channel SPI support"
+ depends on MFD_GLAMO_FB
+ help
+ Enable a bitbanging SPI adapter driver for the Smedia Glamo LCM
+ control channel. This SPI interface is frequently used to
+ interconnect the LCM control interface.
+
+config MFD_GLAMO_MCI
+ tristate "Glamo S3C SD/MMC Card Interface support"
+ depends on MFD_GLAMO && MMC
+ help
+ This selects a driver for the MCI interface found in
+ the S-Media GLAMO chip, as used in Openmoko
+ neo1973 GTA-02.
+
+ If unsure, say N.
\ No newline at end of file
--- /dev/null
+++ b/drivers/mfd/glamo/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for the Smedia Glamo framebuffer driver
+#
+
+obj-$(CONFIG_MFD_GLAMO) += glamo-core.o glamo-gpio.o
+obj-$(CONFIG_MFD_GLAMO_SPI) += glamo-spi.o
+obj-$(CONFIG_MFD_GLAMO_SPI_GPIO) += glamo-spi-gpio.o
+
+obj-$(CONFIG_MFD_GLAMO_FB) += glamo-fb.o
+obj-$(CONFIG_MFD_GLAMO_SPI_FB) += glamo-lcm-spi.o
+obj-$(CONFIG_MFD_GLAMO_MCI) += glamo-mci.o
+
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -153,6 +153,55 @@
I2C as the control interface. Additional options must be
selected to enable support for the functionality of the chip.
+config MFD_PCF50633
+ tristate "Support for NXP PCF50633"
+ depends on I2C
+ help
+ Say yes here if you have NXP PCF50633 chip on your board.
+ This core driver provides register access and IRQ handling
+ facilities, and registers devices for the various functions
+ so that function-specific drivers can bind to them.
+
+
+config PCF50633_ADC
+ tristate "Support for NXP PCF50633 ADC"
+ depends on MFD_PCF50633
+ help
+ Say yes here if you want to include support for ADC in the
+ NXP PCF50633 chip.
+
+config PCF50633_GPIO
+ tristate "Support for NXP PCF50633 GPIO"
+ depends on MFD_PCF50633
+ help
+ Say yes here if you want to include support GPIO for pins on
+ the PCF50633 chip.
+
+config MFD_PCF50606
+ tristate "Support for NXP PCF50606"
+ depends on I2C
+ help
+ Say yes here if you have NXP PCF50606 chip on your board.
+ This core driver provides register access and IRQ handling
+ facilities, and registers devices for the various functions
+ so that function-specific drivers can bind to them.
+
+config PCF50606_ADC
+ tristate "Support for NXP PCF50606 ADC"
+ depends on MFD_PCF50606
+ help
+ Say yes here if you want to include support for ADC in the
+ NXP PCF50606 chip.
+
+config PCF50606_GPO
+ tristate "Support for NXP PCF50606 GPO"
+ depends on MFD_PCF50606
+ help
+ Say yes here if you want to include support GPO for pins on
+ the PCF50606 chip.
+
+source "drivers/mfd/glamo/Kconfig"
+
endmenu
menu "Multimedia Capabilities Port drivers"
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_MFD_SM501) += sm501.o
obj-$(CONFIG_MFD_ASIC3) += asic3.o
+obj-$(CONFIG_MFD_GLAMO) += glamo/
obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o
@@ -31,4 +32,13 @@
endif
obj-$(CONFIG_UCB1400_CORE) += ucb1400_core.o
-obj-$(CONFIG_PMIC_DA903X) += da903x.o
\ No newline at end of file
+obj-$(CONFIG_PMIC_DA903X) += da903x.o
+
+obj-$(CONFIG_MFD_PCF50633) += pcf50633-core.o
+obj-$(CONFIG_PCF50633_ADC) += pcf50633-adc.o
+obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
+
+obj-$(CONFIG_MFD_PCF50606) += pcf50606-core.o
+obj-$(CONFIG_PCF50606_ADC) += pcf50606-adc.o
+obj-$(CONFIG_PCF50606_GPO) += pcf50606-gpo.o
+
--- /dev/null
+++ b/drivers/mfd/pcf50606-adc.c
@@ -0,0 +1,239 @@
+/* Philips PCF50606 ADC Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50606 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/mfd/pcf50606/core.h>
+#include <linux/mfd/pcf50606/adc.h>
+
+struct pcf50606_adc_request {
+ int mux;
+ int avg;
+ int result;
+ void (*callback)(struct pcf50606 *, void *, int);
+ void *callback_param;
+
+ /* Used in case of sync requests */
+ struct completion completion;
+
+};
+
+static void adc_read_setup(struct pcf50606 *pcf,
+ int channel, int avg)
+{
+ channel &= PCF50606_ADCC2_ADCMUX_MASK;
+
+ /* start ADC conversion of selected channel */
+ pcf50606_reg_write(pcf, PCF50606_REG_ADCC2, channel |
+ PCF50606_ADCC2_ADCSTART | PCF50606_ADCC2_RES_10BIT);
+
+}
+
+static void trigger_next_adc_job_if_any(struct pcf50606 *pcf)
+{
+ int head, tail;
+
+ mutex_lock(&pcf->adc.queue_mutex);
+
+ head = pcf->adc.queue_head;
+ tail = pcf->adc.queue_tail;
+
+ if (!pcf->adc.queue[head])
+ goto out;
+
+ adc_read_setup(pcf, pcf->adc.queue[head]->mux,
+ pcf->adc.queue[head]->avg);
+out:
+ mutex_unlock(&pcf->adc.queue_mutex);
+}
+
+static int
+adc_enqueue_request(struct pcf50606 *pcf, struct pcf50606_adc_request *req)
+{
+ int head, tail;
+
+ mutex_lock(&pcf->adc.queue_mutex);
+ head = pcf->adc.queue_head;
+ tail = pcf->adc.queue_tail;
+
+ if (pcf->adc.queue[tail]) {
+ mutex_unlock(&pcf->adc.queue_mutex);
+ return -EBUSY;
+ }
+
+ pcf->adc.queue[tail] = req;
+
+ pcf->adc.queue_tail =
+ (tail + 1) & (PCF50606_MAX_ADC_FIFO_DEPTH - 1);
+
+ mutex_unlock(&pcf->adc.queue_mutex);
+
+ trigger_next_adc_job_if_any(pcf);
+
+ return 0;
+}
+
+static void
+pcf50606_adc_sync_read_callback(struct pcf50606 *pcf, void *param, int result)
+{
+ struct pcf50606_adc_request *req;
+
+ /*We know here that the passed param is an adc_request object */
+ req = (struct pcf50606_adc_request *)param;
+
+ req->result = result;
+ complete(&req->completion);
+}
+
+int pcf50606_adc_sync_read(struct pcf50606 *pcf, int mux, int avg)
+{
+
+ struct pcf50606_adc_request *req;
+ int result;
+
+ /* req is freed when the result is ready, in pcf50606_work*/
+ req = kzalloc(sizeof(*req), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->mux = mux;
+ req->avg = avg;
+ req->callback = pcf50606_adc_sync_read_callback;
+ req->callback_param = req;
+ init_completion(&req->completion);
+
+ adc_enqueue_request(pcf, req);
+
+ wait_for_completion(&req->completion);
+ result = req->result;
+
+ return result;
+}
+EXPORT_SYMBOL_GPL(pcf50606_adc_sync_read);
+
+int pcf50606_adc_async_read(struct pcf50606 *pcf, int mux, int avg,
+ void (*callback)(struct pcf50606 *, void *, int),
+ void *callback_param)
+{
+ struct pcf50606_adc_request *req;
+
+ /* req is freed when the result is ready, in pcf50606_work*/
+ req = kmalloc(sizeof(*req), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->mux = mux;
+ req->avg = avg;
+ req->callback = callback;
+ req->callback_param = callback_param;
+
+ adc_enqueue_request(pcf, req);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50606_adc_async_read);
+
+static int adc_result(struct pcf50606 *pcf)
+{
+ u16 ret = (pcf50606_reg_read(pcf, PCF50606_REG_ADCS1) << 2) |
+ (pcf50606_reg_read(pcf, PCF50606_REG_ADCS2) & 0x03);
+
+ dev_info(pcf->dev, "adc result = %d\n", ret);
+
+ return ret;
+}
+
+static void pcf50606_adc_irq(struct pcf50606 *pcf, int irq, void *unused)
+{
+ struct pcf50606_adc_request *req;
+ int head;
+
+ mutex_lock(&pcf->adc.queue_mutex);
+ head = pcf->adc.queue_head;
+
+ req = pcf->adc.queue[head];
+ if (!req) {
+ dev_err(pcf->dev, "ADC queue empty\n");
+ mutex_unlock(&pcf->adc.queue_mutex);
+ return;
+ }
+ pcf->adc.queue[head] = NULL;
+ pcf->adc.queue_head = (head + 1) &
+ (PCF50606_MAX_ADC_FIFO_DEPTH - 1);
+
+ mutex_unlock(&pcf->adc.queue_mutex);
+ req->callback(pcf, req->callback_param, adc_result(pcf));
+
+ kfree(req);
+
+ trigger_next_adc_job_if_any(pcf);
+}
+
+int __init pcf50606_adc_probe(struct platform_device *pdev)
+{
+ struct pcf50606 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+
+ /* Set up IRQ handlers */
+ pcf->irq_handler[PCF50606_IRQ_ADCRDY].handler = pcf50606_adc_irq;
+
+ mutex_init(&pcf->adc.queue_mutex);
+ return 0;
+}
+
+static int __devexit pcf50606_adc_remove(struct platform_device *pdev)
+{
+ struct pcf50606 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+ pcf->irq_handler[PCF50606_IRQ_ADCRDY].handler = NULL;
+
+ return 0;
+}
+
+struct platform_driver pcf50606_adc_driver = {
+ .driver = {
+ .name = "pcf50606-adc",
+ },
+ .probe = pcf50606_adc_probe,
+ .remove = __devexit_p(pcf50606_adc_remove),
+};
+
+static int __init pcf50606_adc_init(void)
+{
+ return platform_driver_register(&pcf50606_adc_driver);
+}
+module_init(pcf50606_adc_init);
+
+static void __exit pcf50606_adc_exit(void)
+{
+ platform_driver_unregister(&pcf50606_adc_driver);
+}
+module_exit(pcf50606_adc_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50606 adc driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50606-adc");
+
--- /dev/null
+++ b/drivers/mfd/pcf50606-core.c
@@ -0,0 +1,580 @@
+/* Philips PCF50606 Power Management Unit (PMU) driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * Matt Hsu <matt@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+#include <linux/mfd/pcf50606/core.h>
+
+/* Read a block of upto 32 regs */
+int pcf50606_read_block(struct pcf50606 *pcf , u8 reg,
+ int nr_regs, u8 *data)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
+ nr_regs, data);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50606_read_block);
+
+/* Write a block of upto 32 regs */
+int pcf50606_write_block(struct pcf50606 *pcf , u8 reg,
+ int nr_regs, u8 *data)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
+ nr_regs, data);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50606_write_block);
+
+u8 pcf50606_reg_read(struct pcf50606 *pcf, u8 reg)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50606_reg_read);
+
+int pcf50606_reg_write(struct pcf50606 *pcf, u8 reg, u8 val)
+{
+ int ret;
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, val);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50606_reg_write);
+
+int pcf50606_reg_set_bit_mask(struct pcf50606 *pcf, u8 reg, u8 mask, u8 val)
+{
+ int ret;
+ u8 tmp;
+
+ val &= mask;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50606_reg_set_bit_mask);
+
+int pcf50606_reg_clear_bits(struct pcf50606 *pcf, u8 reg, u8 val)
+{
+ int ret;
+ u8 tmp;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp &= ~val;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50606_reg_clear_bits);
+
+static ssize_t show_resume_reason(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pcf50606 *pcf = dev_get_drvdata(dev);
+ int n;
+
+ n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
+ pcf->resume_reason[0],
+ pcf->resume_reason[1],
+ pcf->resume_reason[2],
+ pcf->resume_reason[3],
+ pcf->resume_reason[4]);
+
+ return n;
+}
+static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
+
+static struct attribute *pcf_sysfs_entries[] = {
+ &dev_attr_resume_reason.attr,
+ NULL,
+};
+
+static struct attribute_group pcf_attr_group = {
+ .name = NULL, /* put in device directory */
+ .attrs = pcf_sysfs_entries,
+};
+
+
+static int pcf50606_irq_mask_set(struct pcf50606 *pcf, int irq, int mask)
+{
+ u8 reg, bits, tmp;
+ int ret = 0, idx;
+
+ idx = irq / 8;
+ reg = PCF50606_REG_INT1M + idx;
+ bits = 1 << (irq % 8);
+
+ mutex_lock(&pcf->lock);
+
+ if (mask) {
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp |= bits;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ pcf->mask_regs[idx] &= ~bits;
+ pcf->mask_regs[idx] |= bits;
+ } else {
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp &= ~bits;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ pcf->mask_regs[idx] &= ~bits;
+ }
+
+ mutex_unlock(&pcf->lock);
+
+ return 0;
+}
+
+int pcf50606_irq_mask(struct pcf50606 *pcf, int irq)
+{
+ dev_info(pcf->dev, "Masking IRQ %d\n", irq);
+
+ return pcf50606_irq_mask_set(pcf, irq, 1);
+}
+EXPORT_SYMBOL_GPL(pcf50606_irq_mask);
+
+int pcf50606_irq_unmask(struct pcf50606 *pcf, int irq)
+{
+ dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
+
+ return pcf50606_irq_mask_set(pcf, irq, 0);
+}
+EXPORT_SYMBOL_GPL(pcf50606_irq_unmask);
+
+int pcf50606_irq_mask_get(struct pcf50606 *pcf, int irq)
+{
+ u8 reg, bits;
+
+ reg = (irq / 8);
+ bits = (1 << (irq % 8));
+
+ return pcf->mask_regs[reg] & bits;
+}
+EXPORT_SYMBOL_GPL(pcf50606_irq_mask_get);
+
+static void pcf50606_irq_call_handler(struct pcf50606 *pcf,
+ int irq)
+{
+ if (pcf->irq_handler[irq].handler)
+ pcf->irq_handler[irq].handler(pcf, irq,
+ pcf->irq_handler[irq].data);
+}
+
+#define PCF50606_ONKEY1S_TIMEOUT 8
+
+static void pcf50606_irq_worker(struct work_struct *work)
+{
+ struct pcf50606 *pcf;
+ int ret, i, j;
+ u8 pcf_int[3], chgstat;
+
+ pcf = container_of(work, struct pcf50606, irq_work);
+
+ /* Read the 3 INT regs in one transaction */
+ ret = pcf50606_read_block(pcf, PCF50606_REG_INT1,
+ sizeof(pcf_int), pcf_int);
+ if (ret != sizeof(pcf_int)) {
+ dev_info(pcf->dev, "Error reading INT registers\n");
+
+ /* We don't have an option but to retry. Because if
+ * we don't, there won't be another interrupt edge.
+ */
+ goto reschedule;
+ }
+
+ /* We immediately read the usb and adapter status. We thus make sure
+ * only of CHGINS/CHGRM handlers are called */
+ if (pcf_int[1] & (PCF50606_INT2_CHGINS | PCF50606_INT2_CHGRM)) {
+ chgstat = pcf50606_reg_read(pcf, PCF50606_REG_MBCS1);
+ if (chgstat & (0x1 << 4))
+ pcf_int[1] &= ~(1 << PCF50606_INT2_CHGRM);
+ else
+ pcf_int[1] &= ~(1 << PCF50606_INT2_CHGINS);
+ }
+
+ dev_info(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x",
+ pcf_int[0], pcf_int[1], pcf_int[2]);
+
+ /* Some revisions of the chip don't have a 8s standby mode on
+ * ONKEY1S press. We try to manually do it in such cases. */
+
+ if (pcf_int[0] & PCF50606_INT1_SECOND && pcf->onkey1s_held) {
+ dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
+ pcf->onkey1s_held);
+ if (pcf->onkey1s_held++ == PCF50606_ONKEY1S_TIMEOUT)
+ if (pcf->pdata->force_shutdown)
+ pcf->pdata->force_shutdown(pcf);
+ }
+
+ if (pcf_int[0] & PCF50606_INT1_ONKEY1S) {
+ dev_info(pcf->dev, "ONKEY1S held\n");
+ pcf->onkey1s_held = 1 ;
+
+ /* Unmask IRQ_SECOND */
+ pcf50606_reg_clear_bits(pcf, PCF50606_REG_INT1M,
+ PCF50606_INT1_SECOND);
+
+ /* Unmask IRQ_ONKEYF */
+ pcf50606_reg_clear_bits(pcf, PCF50606_REG_INT1M,
+ PCF50606_INT1_ONKEYF);
+ }
+
+ if ((pcf_int[0] & PCF50606_INT1_ONKEYR) && pcf->onkey1s_held) {
+ pcf->onkey1s_held = 0;
+
+ /* Mask SECOND and ONKEYF interrupts */
+ if (pcf->mask_regs[0] & PCF50606_INT1_SECOND)
+ pcf50606_reg_set_bit_mask(pcf,
+ PCF50606_REG_INT1M,
+ PCF50606_INT1_SECOND,
+ PCF50606_INT1_SECOND);
+
+ if (pcf->mask_regs[0] & PCF50606_INT1_ONKEYF)
+ pcf50606_reg_set_bit_mask(pcf,
+ PCF50606_REG_INT1M,
+ PCF50606_INT1_ONKEYF,
+ PCF50606_INT1_ONKEYF);
+ }
+
+ /* Have we just resumed ? */
+ if (pcf->is_suspended) {
+
+ pcf->is_suspended = 0;
+
+ /* Set the resume reason filtering out non resumers */
+ for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
+ pcf->resume_reason[i] = pcf_int[i] &
+ pcf->pdata->resumers[i];
+
+ /* Make sure we don't pass on any input events to
+ * userspace now */
+ pcf_int[0] &= ~(PCF50606_INT1_SECOND | PCF50606_INT1_ALARM);
+ }
+
+ /* Unset masked interrupts */
+ for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
+ pcf_int[i] &= ~pcf->mask_regs[i];
+
+ for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
+ for (j = 0; j < 8 ; j++)
+ if (pcf_int[i] & (1 << j))
+ pcf50606_irq_call_handler(pcf, (i * 8) + j);
+
+ put_device(pcf->dev);
+
+ return;
+reschedule:
+ schedule_work(&pcf->irq_work);
+
+ /* Don't put_device here. Will be used when we are rescheduled */
+
+ return;
+}
+
+static irqreturn_t pcf50606_irq(int irq, void *data)
+{
+ struct pcf50606 *pcf = data;
+
+ get_device(pcf->dev);
+ schedule_work(&pcf->irq_work);
+
+ return IRQ_HANDLED;
+}
+
+static void
+pcf50606_client_dev_register(struct pcf50606 *pcf, const char *name,
+ struct platform_device **pdev)
+{
+ int ret;
+
+ *pdev = platform_device_alloc(name, -1);
+
+ if (!pdev) {
+ dev_err(pcf->dev, "Falied to allocate %s\n", name);
+ return;
+ }
+
+ (*pdev)->dev.parent = pcf->dev;
+ platform_set_drvdata(*pdev, pcf);
+
+ ret = platform_device_add(*pdev);
+ if (ret != 0) {
+ dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
+ platform_device_put(*pdev);
+ *pdev = NULL;
+ }
+}
+
+#ifdef CONFIG_PM
+static int pcf50606_suspend(struct device *dev, pm_message_t state)
+{
+ struct pcf50606 *pcf;
+ int ret, i;
+ u8 res[3];
+
+ pcf = dev_get_drvdata(dev);
+
+ /* Make sure our interrupt handlers are not called
+ * henceforth */
+ disable_irq(pcf->irq);
+
+ /* Make sure that an IRQ worker has quit */
+ cancel_work_sync(&pcf->irq_work);
+
+ /* Save the masks */
+ ret = pcf50606_read_block(pcf, PCF50606_REG_INT1M,
+ ARRAY_SIZE(pcf->suspend_irq_masks),
+ pcf->suspend_irq_masks);
+ if (ret < 0)
+ dev_err(pcf->dev, "error saving irq masks\n");
+
+ /* Set interrupt masks. So that only those sources we want to wake
+ * us up can
+ */
+ for (i = 0; i < ARRAY_SIZE(res); i++)
+ res[i] = ~pcf->pdata->resumers[i];
+
+ pcf50606_write_block(pcf, PCF50606_REG_INT1M,
+ ARRAY_SIZE(res), &res[0]);
+
+ pcf->is_suspended = 1;
+
+ return 0;
+}
+
+static int pcf50606_resume(struct device *dev)
+{
+ struct pcf50606 *pcf;
+
+ pcf = dev_get_drvdata(dev);
+
+ /* Write the saved mask registers */
+ pcf50606_write_block(pcf, PCF50606_REG_INT1M,
+ ARRAY_SIZE(pcf->suspend_irq_masks),
+ pcf->suspend_irq_masks);
+
+ /* Clear any pending interrupts and set resume reason if any */
+ pcf50606_irq_worker(&pcf->irq_work);
+
+ enable_irq(pcf->irq);
+
+ return 0;
+}
+#else
+#define pcf50606_suspend NULL
+#define pcf50606_resume NULL
+#endif
+
+static int pcf50606_probe(struct i2c_client *client,
+ const struct i2c_device_id *ids)
+{
+ struct pcf50606 *pcf;
+ struct pcf50606_platform_data *pdata;
+ int i, ret = 0;
+ int version, variant;
+ u8 mbcs1;
+
+ pdata = client->dev.platform_data;
+
+ pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
+ if (!pcf)
+ return -ENOMEM;
+
+ pcf->pdata = pdata;
+ pdata->pcf = pcf;
+
+ mutex_init(&pcf->lock);
+
+ i2c_set_clientdata(client, pcf);
+ pcf->dev = &client->dev;
+ pcf->i2c_client = client;
+
+ INIT_WORK(&pcf->irq_work, pcf50606_irq_worker);
+
+ version = pcf50606_reg_read(pcf, 0);
+ if (version < 0) {
+ dev_err(pcf->dev, "Unable to probe pcf50606\n");
+ kfree(pcf);
+ return -ENODEV;
+ }
+
+ variant = pcf50606_reg_read(pcf, 1);
+ if (version < 0) {
+ dev_err(pcf->dev, "Unable to probe pcf50606\n");
+ kfree(pcf);
+ return -ENODEV;
+ }
+
+ dev_info(pcf->dev, "Probed device version %d variant %d\n",
+ version, variant);
+
+ /* Enable all inteerupts except RTC SECOND */
+ pcf->mask_regs[0] = 0x80;
+ pcf50606_reg_write(pcf, PCF50606_REG_INT1M, 0x80);
+
+ pcf50606_reg_write(pcf, PCF50606_REG_INT2M, 0x00);
+ pcf50606_reg_write(pcf, PCF50606_REG_INT3M, 0x00);
+
+ pcf50606_client_dev_register(pcf, "pcf50606-input",
+ &pcf->input.pdev);
+ pcf50606_client_dev_register(pcf, "pcf50606-rtc",
+ &pcf->rtc.pdev);
+ pcf50606_client_dev_register(pcf, "pcf50606-mbc",
+ &pcf->mbc.pdev);
+ pcf50606_client_dev_register(pcf, "pcf50606-adc",
+ &pcf->adc.pdev);
+ pcf50606_client_dev_register(pcf, "pcf50606-wdt",
+ &pcf->wdt.pdev);
+ for (i = 0; i < PCF50606_NUM_REGULATORS; i++) {
+ struct platform_device *pdev;
+
+ pdev = platform_device_alloc("pcf50606-regltr", i);
+ if (!pdev) {
+ dev_err(pcf->dev, "Cannot create regulator\n");
+ continue;
+ }
+
+ pdev->dev.parent = pcf->dev;
+ pdev->dev.platform_data = &pdata->reg_init_data[i];
+ pdev->dev.driver_data = pcf;
+ pcf->pmic.pdev[i] = pdev;
+
+ platform_device_add(pdev);
+ }
+
+ pcf->irq = client->irq;
+
+ if (client->irq) {
+ ret = request_irq(client->irq, pcf50606_irq,
+ IRQF_TRIGGER_FALLING, "pcf50606", pcf);
+
+ if (ret) {
+ dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
+ goto err;
+ }
+ } else {
+ dev_err(pcf->dev, "No IRQ configured\n");
+ goto err;
+ }
+
+ if (enable_irq_wake(client->irq) < 0)
+ dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source"
+ "in this hardware revision", client->irq);
+
+ /* Cold Intialization */
+ mbcs1 = pcf50606_reg_read(pcf, PCF50606_REG_MBCS1);
+
+ if (mbcs1 & (0x01 << 4)) /* Charger present ? */
+ pcf50606_irq_call_handler(pcf, PCF50606_IRQ_CHGINS);
+
+ ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
+ if (ret)
+ dev_err(pcf->dev, "error creating sysfs entries\n");
+
+ if (pdata->probe_done)
+ pdata->probe_done(pcf);
+
+ return 0;
+
+err:
+ kfree(pcf);
+ return ret;
+}
+
+static int pcf50606_remove(struct i2c_client *client)
+{
+ struct pcf50606 *pcf = i2c_get_clientdata(client);
+
+ free_irq(pcf->irq, pcf);
+ kfree(pcf);
+
+ return 0;
+}
+
+static struct i2c_device_id pcf50606_id_table[] = {
+ {"pcf50606", 0x73},
+};
+
+static struct i2c_driver pcf50606_driver = {
+ .driver = {
+ .name = "pcf50606",
+ .suspend = pcf50606_suspend,
+ .resume = pcf50606_resume,
+ },
+ .id_table = pcf50606_id_table,
+ .probe = pcf50606_probe,
+ .remove = pcf50606_remove,
+};
+
+static int __init pcf50606_init(void)
+{
+ return i2c_add_driver(&pcf50606_driver);
+}
+
+static void pcf50606_exit(void)
+{
+ i2c_del_driver(&pcf50606_driver);
+}
+
+MODULE_DESCRIPTION("I2C chip driver for NXP PCF50606 PMU");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
+
+module_init(pcf50606_init);
+module_exit(pcf50606_exit);
--- /dev/null
+++ b/drivers/mfd/pcf50606-gpo.c
@@ -0,0 +1,128 @@
+/* Philips PCF50606 GPO Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50606 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/mfd/pcf50606/core.h>
+#include <linux/mfd/pcf50606/gpo.h>
+#include <linux/mfd/pcf50606/pmic.h>
+
+void pcf50606_gpo_set_active(struct pcf50606 *pcf, int gpo, int val)
+{
+ u8 reg, value, mask;
+
+ reg = gpo;
+ value = val;
+ mask = 0x07;
+
+ if (gpo == PCF50606_GPO2) {
+ value = val << 4;
+ mask = 0x07 << 4;
+ }
+ pcf50606_reg_set_bit_mask(pcf, reg, mask, value);
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo_set_active);
+
+int pcf50606_gpo_get_active(struct pcf50606 *pcf, int gpo)
+{
+ u8 reg, value, shift = 0;
+
+ reg = gpo;
+ if (gpo == PCF50606_GPO2)
+ shift = 4;
+
+ value = pcf50606_reg_read(pcf, reg);
+
+ return (value >> shift) & 0x07;
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo_get_active);
+
+void pcf50606_gpo_set_standby(struct pcf50606 *pcf, int gpo, int val)
+{
+ u8 reg;
+
+ if (gpo == PCF50606_GPO1 || gpo == PCF50606_GPO2) {
+ dev_err(pcf->dev, "Can't set standby settings for GPO[12]n");
+ return;
+ }
+
+ reg = gpo;
+
+ pcf50606_reg_set_bit_mask(pcf, gpo, 0x07 << 3, val);
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo_set_standby);
+
+int pcf50606_gpo_get_standby(struct pcf50606 *pcf, int gpo)
+{
+ u8 reg, value;
+
+ if (gpo == PCF50606_GPO1 || gpo == PCF50606_GPO2) {
+ dev_err(pcf->dev, "Can't get standby settings for GPO[12]n");
+ return -EINVAL;
+ }
+
+ reg = gpo;
+ value = pcf50606_reg_read(pcf, reg);
+
+ return (value >> 3) & 0x07;
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo_get_standby);
+
+void pcf50606_gpo_invert_set(struct pcf50606 *pcf, int gpo, int invert)
+{
+ u8 reg, value, mask;
+
+ reg = gpo;
+ value = !!invert << 6;
+ mask = 0x01 << 6;
+
+ if (gpo == PCF50606_GPO1) {
+ mask = 0x01 << 4;
+ value = !!invert << 4;
+ }
+ else if (gpo == PCF50606_GPO2) {
+ mask = 0x01 << 7;
+ value = !!invert << 7;
+ }
+
+ pcf50606_reg_set_bit_mask(pcf, reg, mask, value);
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo_invert_set);
+
+int pcf50606_gpo_invert_get(struct pcf50606 *pcf, int gpo)
+{
+ u8 reg, value, shift;
+
+ reg = gpo;
+ shift = 6;
+
+ if (gpo == PCF50606_GPO1)
+ shift = 4;
+ else if (gpo == PCF50606_GPO2)
+ shift = 7;
+
+ value = pcf50606_reg_read(pcf, reg);
+
+ return (value >> shift) & 0x01;
+}
+EXPORT_SYMBOL_GPL(pcf50606_gpo_invert_get);
--- /dev/null
+++ b/drivers/mfd/pcf50633-adc.c
@@ -0,0 +1,252 @@
+/* Philips PCF50633 ADC Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50633 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * NOTE: This driver does not yet support subtractive ADC mode, which means
+ * you can do only one measurement per read request.
+ */
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/adc.h>
+
+struct pcf50633_adc_request {
+ int mux;
+ int avg;
+ int result;
+ void (*callback)(struct pcf50633 *, void *, int);
+ void *callback_param;
+
+ /* Used in case of sync requests */
+ struct completion completion;
+
+};
+
+static void adc_read_setup(struct pcf50633 *pcf,
+ int channel, int avg)
+{
+ channel &= PCF50633_ADCC1_ADCMUX_MASK;
+
+ /* kill ratiometric, but enable ACCSW biasing */
+ pcf50633_reg_write(pcf, PCF50633_REG_ADCC2, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_ADCC3, 0x01);
+
+ /* start ADC conversion on selected channel */
+ pcf50633_reg_write(pcf, PCF50633_REG_ADCC1, channel | avg |
+ PCF50633_ADCC1_ADCSTART | PCF50633_ADCC1_RES_10BIT);
+
+}
+
+static void trigger_next_adc_job_if_any(struct pcf50633 *pcf)
+{
+ int head, tail;
+
+ mutex_lock(&pcf->adc.queue_mutex);
+
+ head = pcf->adc.queue_head;
+ tail = pcf->adc.queue_tail;
+
+ if (!pcf->adc.queue[head])
+ goto out;
+
+ adc_read_setup(pcf, pcf->adc.queue[head]->mux,
+ pcf->adc.queue[head]->avg);
+out:
+ mutex_unlock(&pcf->adc.queue_mutex);
+}
+
+static int
+adc_enqueue_request(struct pcf50633 *pcf, struct pcf50633_adc_request *req)
+{
+ int head, tail;
+
+ mutex_lock(&pcf->adc.queue_mutex);
+ head = pcf->adc.queue_head;
+ tail = pcf->adc.queue_tail;
+
+ if (pcf->adc.queue[tail]) {
+ mutex_unlock(&pcf->adc.queue_mutex);
+ return -EBUSY;
+ }
+
+ pcf->adc.queue[tail] = req;
+
+ pcf->adc.queue_tail =
+ (tail + 1) & (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
+
+ mutex_unlock(&pcf->adc.queue_mutex);
+
+ trigger_next_adc_job_if_any(pcf);
+
+ return 0;
+}
+
+static void
+pcf50633_adc_sync_read_callback(struct pcf50633 *pcf, void *param, int result)
+{
+ struct pcf50633_adc_request *req;
+
+ /*We know here that the passed param is an adc_request object */
+ req = (struct pcf50633_adc_request *)param;
+
+ req->result = result;
+ complete(&req->completion);
+}
+
+int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg)
+{
+
+ struct pcf50633_adc_request *req;
+ int result;
+
+ /* req is freed when the result is ready, in interrupt handler */
+ req = kzalloc(sizeof(*req), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->mux = mux;
+ req->avg = avg;
+ req->callback = pcf50633_adc_sync_read_callback;
+ req->callback_param = req;
+ init_completion(&req->completion);
+
+ adc_enqueue_request(pcf, req);
+
+ wait_for_completion(&req->completion);
+ result = req->result;
+
+ return result;
+}
+EXPORT_SYMBOL_GPL(pcf50633_adc_sync_read);
+
+int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
+ void (*callback)(struct pcf50633 *, void *, int),
+ void *callback_param)
+{
+ struct pcf50633_adc_request *req;
+
+ /* req is freed when the result is ready, in interrupt handler */
+ req = kmalloc(sizeof(*req), GFP_KERNEL);
+ if (!req)
+ return -ENOMEM;
+
+ req->mux = mux;
+ req->avg = avg;
+ req->callback = callback;
+ req->callback_param = callback_param;
+
+ adc_enqueue_request(pcf, req);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pcf50633_adc_async_read);
+
+static int adc_result(struct pcf50633 *pcf)
+{
+ u8 adcs1, adcs3;
+ u16 result;
+
+ adcs1 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS1);
+ adcs3 = pcf50633_reg_read(pcf, PCF50633_REG_ADCS3);
+ result = (adcs1 << 2) | (adcs3 & PCF50633_ADCS3_ADCDAT1L_MASK);
+
+ dev_info(pcf->dev, "adc result = %d\n", result);
+
+ return result;
+}
+
+static void pcf50633_adc_irq(struct pcf50633 *pcf, int irq, void *unused)
+{
+ struct pcf50633_adc_request *req;
+ int head;
+
+ mutex_lock(&pcf->adc.queue_mutex);
+ head = pcf->adc.queue_head;
+
+ req = pcf->adc.queue[head];
+ if (!req) {
+ dev_err(pcf->dev, "ADC queue empty\n");
+ mutex_unlock(&pcf->adc.queue_mutex);
+ return;
+ }
+ pcf->adc.queue[head] = NULL;
+ pcf->adc.queue_head = (head + 1) &
+ (PCF50633_MAX_ADC_FIFO_DEPTH - 1);
+
+ mutex_unlock(&pcf->adc.queue_mutex);
+ req->callback(pcf, req->callback_param, adc_result(pcf));
+
+ kfree(req);
+
+ trigger_next_adc_job_if_any(pcf);
+}
+
+int __init pcf50633_adc_probe(struct platform_device *pdev)
+{
+ struct pcf50633 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+
+ /* Set up IRQ handlers */
+ pcf->irq_handler[PCF50633_IRQ_ADCRDY].handler = pcf50633_adc_irq;
+
+ mutex_init(&pcf->adc.queue_mutex);
+ return 0;
+}
+
+static int __devexit pcf50633_adc_remove(struct platform_device *pdev)
+{
+ struct pcf50633 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+ pcf->irq_handler[PCF50633_IRQ_ADCRDY].handler = NULL;
+
+ return 0;
+}
+
+struct platform_driver pcf50633_adc_driver = {
+ .driver = {
+ .name = "pcf50633-adc",
+ },
+ .probe = pcf50633_adc_probe,
+ .remove = __devexit_p(pcf50633_adc_remove),
+};
+
+static int __init pcf50633_adc_init(void)
+{
+ return platform_driver_register(&pcf50633_adc_driver);
+}
+module_init(pcf50633_adc_init);
+
+static void __exit pcf50633_adc_exit(void)
+{
+ platform_driver_unregister(&pcf50633_adc_driver);
+}
+module_exit(pcf50633_adc_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50633 adc driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50633-adc");
+
--- /dev/null
+++ b/drivers/mfd/pcf50633-core.c
@@ -0,0 +1,627 @@
+/* Philips PCF50633 Power Management Unit (PMU) driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+
+#include <linux/mfd/pcf50633/core.h>
+
+/* Read a block of upto 32 regs */
+int pcf50633_read_block(struct pcf50633 *pcf , u8 reg,
+ int nr_regs, u8 *data)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg,
+ nr_regs, data);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50633_read_block);
+
+/* Write a block of upto 32 regs */
+int pcf50633_write_block(struct pcf50633 *pcf , u8 reg,
+ int nr_regs, u8 *data)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg,
+ nr_regs, data);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50633_write_block);
+
+u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg)
+{
+ int ret;
+
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50633_reg_read);
+
+int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val)
+{
+ int ret;
+ mutex_lock(&pcf->lock);
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, val);
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50633_reg_write);
+
+int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val)
+{
+ int ret;
+ u8 tmp;
+
+ val &= mask;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp &= ~mask;
+ tmp |= val;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask);
+
+int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val)
+{
+ int ret;
+ u8 tmp;
+
+ mutex_lock(&pcf->lock);
+
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp &= ~val;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ mutex_unlock(&pcf->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits);
+
+/* sysfs attributes */
+static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct pcf50633 *pcf = dev_get_drvdata(dev);
+ u8 dump[16];
+ int n, n1, idx = 0;
+ char *buf1 = buf;
+ static u8 address_no_read[] = { /* must be ascending */
+ PCF50633_REG_INT1,
+ PCF50633_REG_INT2,
+ PCF50633_REG_INT3,
+ PCF50633_REG_INT4,
+ PCF50633_REG_INT5,
+ 0 /* terminator */
+ };
+
+ for (n = 0; n < 256; n += sizeof(dump)) {
+ for (n1 = 0; n1 < sizeof(dump); n1++)
+ if (n == address_no_read[idx]) {
+ idx++;
+ dump[n1] = 0x00;
+ } else
+ dump[n1] = pcf50633_reg_read(pcf, n + n1);
+
+ hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0);
+ buf1 += strlen(buf1);
+ *buf1++ = '\n';
+ *buf1 = '\0';
+ }
+
+ return buf1 - buf;
+}
+static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL);
+
+static ssize_t show_resume_reason(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pcf50633 *pcf = dev_get_drvdata(dev);
+ int n;
+
+ n = sprintf(buf, "%02x%02x%02x%02x%02x\n",
+ pcf->resume_reason[0],
+ pcf->resume_reason[1],
+ pcf->resume_reason[2],
+ pcf->resume_reason[3],
+ pcf->resume_reason[4]);
+
+ return n;
+}
+static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL);
+
+static struct attribute *pcf_sysfs_entries[] = {
+ &dev_attr_dump_regs.attr,
+ &dev_attr_resume_reason.attr,
+ NULL,
+};
+
+static struct attribute_group pcf_attr_group = {
+ .name = NULL, /* put in device directory */
+ .attrs = pcf_sysfs_entries,
+};
+
+
+static int pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, int mask)
+{
+ u8 reg, bits, tmp;
+ int ret = 0, idx;
+
+ idx = irq / 8;
+ reg = PCF50633_REG_INT1M + idx;
+ bits = 1 << (irq % 8);
+
+ mutex_lock(&pcf->lock);
+
+ if (mask) {
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp |= bits;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ pcf->mask_regs[idx] &= ~bits;
+ pcf->mask_regs[idx] |= bits;
+ } else {
+ tmp = i2c_smbus_read_byte_data(pcf->i2c_client, reg);
+ tmp &= ~bits;
+ ret = i2c_smbus_write_byte_data(pcf->i2c_client, reg, tmp);
+
+ pcf->mask_regs[idx] &= ~bits;
+ }
+
+ mutex_unlock(&pcf->lock);
+
+ return 0;
+}
+
+int pcf50633_irq_mask(struct pcf50633 *pcf, int irq)
+{
+ dev_info(pcf->dev, "Masking IRQ %d\n", irq);
+
+ return pcf50633_irq_mask_set(pcf, irq, 1);
+}
+EXPORT_SYMBOL_GPL(pcf50633_irq_mask);
+
+int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq)
+{
+ dev_info(pcf->dev, "Unmasking IRQ %d\n", irq);
+
+ return pcf50633_irq_mask_set(pcf, irq, 0);
+}
+EXPORT_SYMBOL_GPL(pcf50633_irq_unmask);
+
+int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq)
+{
+ u8 reg, bits;
+
+ reg = (irq / 8);
+ bits = (1 << (irq % 8));
+
+ return pcf->mask_regs[reg] & bits;
+}
+EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get);
+
+static void pcf50633_irq_call_handler(struct pcf50633 *pcf,
+ int irq)
+{
+ if (pcf->irq_handler[irq].handler) {
+ pcf->irq_handler[irq].handler(pcf, irq,
+ pcf->irq_handler[irq].data);
+ }
+}
+
+#define PCF50633_ONKEY1S_TIMEOUT 8
+
+static void pcf50633_irq_worker(struct work_struct *work)
+{
+ struct pcf50633 *pcf;
+ int ret, i, j;
+ u8 pcf_int[5], chgstat;
+
+ pcf = container_of(work, struct pcf50633, irq_work);
+
+ /* Read the 5 INT regs in one transaction */
+ ret = pcf50633_read_block(pcf, PCF50633_REG_INT1,
+ sizeof(pcf_int), pcf_int);
+ if (ret != sizeof(pcf_int)) {
+ dev_info(pcf->dev, "Error reading INT registers\n");
+
+ /* We don't have an option but to retry. Because if
+ * we don't, there won't be another interrupt edge.
+ */
+ goto reschedule;
+ }
+
+ pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04 ); /* defeat 8s death from lowsys on A5 */
+
+ /* We immediately read the usb and adapter status. We thus make sure
+ * only of USBINS/USBREM and ADAPINS/ADPREM IRQ handlers are called */
+ if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) {
+ chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
+ if (chgstat & (0x3 << 4))
+ pcf_int[0] &= ~(1 << PCF50633_INT1_USBREM);
+ else
+ pcf_int[0] &= ~(1 << PCF50633_INT1_USBINS);
+ }
+
+ if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) {
+ chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
+ if (chgstat & (0x3 << 4))
+ pcf_int[0] &= ~(1 << PCF50633_INT1_ADPREM);
+ else
+ pcf_int[0] &= ~(1 << PCF50633_INT1_ADPINS);
+ }
+
+ dev_info(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x "
+ "INT4=0x%02x INT5=0x%02x\n", pcf_int[0],
+ pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]);
+
+ /* Some revisions of the chip don't have a 8s standby mode on
+ * ONKEY1S press. We try to manually do it in such cases. */
+
+ if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) {
+ dev_info(pcf->dev, "ONKEY1S held for %d secs\n",
+ pcf->onkey1s_held);
+ if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT)
+ if (pcf->pdata->force_shutdown)
+ pcf->pdata->force_shutdown(pcf);
+ }
+
+ if (pcf_int[2] & PCF50633_INT3_ONKEY1S) {
+ dev_info(pcf->dev, "ONKEY1S held\n");
+ pcf->onkey1s_held = 1 ;
+
+ /* Unmask IRQ_SECOND */
+ pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M,
+ PCF50633_INT1_SECOND);
+
+ /* Unmask IRQ_ONKEYR */
+ pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M,
+ PCF50633_INT2_ONKEYR);
+ }
+
+ if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) {
+ pcf->onkey1s_held = 0;
+
+ /* Mask SECOND and ONKEYR interrupts */
+ if (pcf->mask_regs[0] & PCF50633_INT1_SECOND)
+ pcf50633_reg_set_bit_mask(pcf,
+ PCF50633_REG_INT1M,
+ PCF50633_INT1_SECOND,
+ PCF50633_INT1_SECOND);
+
+ if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR)
+ pcf50633_reg_set_bit_mask(pcf,
+ PCF50633_REG_INT2M,
+ PCF50633_INT2_ONKEYR,
+ PCF50633_INT2_ONKEYR);
+ }
+
+ /* Have we just resumed ? */
+ if (pcf->is_suspended) {
+
+ pcf->is_suspended = 0;
+
+ /* Set the resume reason filtering out non resumers */
+ for (i = 0; i < ARRAY_SIZE(pcf_int); i++)
+ pcf->resume_reason[i] = pcf_int[i] &
+ pcf->pdata->resumers[i];
+
+ /* Make sure we don't pass on any ONKEY events to
+ * userspace now */
+ pcf_int[1] &= ~ (PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF);
+ }
+
+ /* Unset masked interrupts */
+ for (i = 0; i < ARRAY_SIZE(pcf_int); i++) {
+ pcf_int[i] &= ~pcf->mask_regs[i];
+ for (j = 0; j < 8 ; j++)
+ if (pcf_int[i] & (1 << j))
+ pcf50633_irq_call_handler(pcf, (i * 8) + j);
+ }
+
+ put_device(pcf->dev);
+
+ enable_irq(pcf->irq);
+
+ return;
+reschedule:
+ schedule_work(&pcf->irq_work);
+
+ /* Don't put_device here. Will be used when we are rescheduled */
+
+ return;
+}
+
+static irqreturn_t pcf50633_irq(int irq, void *data)
+{
+ struct pcf50633 *pcf = data;
+
+ get_device(pcf->dev);
+
+ disable_irq(pcf->irq);
+
+ schedule_work(&pcf->irq_work);
+
+ return IRQ_HANDLED;
+}
+
+static void
+pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name,
+ struct platform_device **pdev)
+{
+ int ret;
+
+ *pdev = platform_device_alloc(name, -1);
+
+ if (!pdev) {
+ dev_err(pcf->dev, "Falied to allocate %s\n", name);
+ return;
+ }
+
+ (*pdev)->dev.parent = pcf->dev;
+ platform_set_drvdata(*pdev, pcf);
+
+ ret = platform_device_add(*pdev);
+ if (ret != 0) {
+ dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret);
+ platform_device_put(*pdev);
+ *pdev = NULL;
+ }
+}
+
+#ifdef CONFIG_PM
+static int pcf50633_suspend(struct device *dev, pm_message_t state)
+{
+ struct pcf50633 *pcf;
+ int ret, i;
+ u8 res[5];
+
+ pcf = dev_get_drvdata(dev);
+
+ /* Make sure our interrupt handlers are not called
+ * henceforth */
+ disable_irq(pcf->irq);
+
+ /* Make sure that an IRQ worker has quit */
+ cancel_work_sync(&pcf->irq_work);
+
+ /* Save the masks */
+ ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M,
+ ARRAY_SIZE(pcf->suspend_irq_masks),
+ pcf->suspend_irq_masks);
+ if (ret < 0)
+ dev_err(pcf->dev, "error saving irq masks\n");
+
+ /* Set interrupt masks. So that only those sources we want to wake
+ * us up can
+ */
+ for (i = 0; i < ARRAY_SIZE(res); i++)
+ res[i] = ~pcf->pdata->resumers[i];
+
+ pcf50633_write_block(pcf, PCF50633_REG_INT1M, ARRAY_SIZE(res), &res[0]);
+
+ pcf->is_suspended = 1;
+
+ return 0;
+}
+
+static int pcf50633_resume(struct device *dev)
+{
+ struct pcf50633 *pcf;
+
+ pcf = dev_get_drvdata(dev);
+
+ /* Write the saved mask registers */
+ pcf50633_write_block(pcf, PCF50633_REG_INT1M,
+ ARRAY_SIZE(pcf->suspend_irq_masks),
+ pcf->suspend_irq_masks);
+
+ get_device(pcf->dev);
+
+ /*
+ * Clear any pending interrupts and set resume reason if any.
+ * This will leave with enable_irq()
+ */
+ pcf50633_irq_worker(&pcf->irq_work);
+
+ return 0;
+}
+#else
+#define pcf50633_suspend NULL
+#define pcf50633_resume NULL
+#endif
+
+static int pcf50633_probe(struct i2c_client *client,
+ const struct i2c_device_id *ids)
+{
+ struct pcf50633 *pcf;
+ struct pcf50633_platform_data *pdata;
+ int i, ret = 0;
+ int version;
+ int variant;
+
+ pdata = client->dev.platform_data;
+
+ pcf = kzalloc(sizeof(*pcf), GFP_KERNEL);
+ if (!pcf)
+ return -ENOMEM;
+
+ pcf->pdata = pdata;
+ pdata->pcf = pcf;
+
+ mutex_init(&pcf->lock);
+
+ i2c_set_clientdata(client, pcf);
+ pcf->dev = &client->dev;
+ pcf->i2c_client = client;
+
+ INIT_WORK(&pcf->irq_work, pcf50633_irq_worker);
+
+ version = pcf50633_reg_read(pcf, 0);
+ if (version < 0) {
+ dev_err(pcf->dev, "Unable to probe pcf50633\n");
+ kfree(pcf);
+ return -ENODEV;
+ }
+
+ variant = pcf50633_reg_read(pcf, 1);
+ if (variant < 0) {
+ dev_err(pcf->dev, "Unable to probe pcf50633\n");
+ kfree(pcf);
+ return -ENODEV;
+ }
+
+ dev_info(pcf->dev, "Probed device version %d variant %d\n",
+ version, variant);
+
+ /* Enable all inteerupts except RTC SECOND */
+ pcf->mask_regs[0] = 0x80;
+ pcf50633_reg_write(pcf, PCF50633_REG_INT1M, 0x80);
+
+ pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00);
+ pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00);
+
+ pcf50633_client_dev_register(pcf, "pcf50633-input",
+ &pcf->input.pdev);
+ pcf50633_client_dev_register(pcf, "pcf50633-rtc",
+ &pcf->rtc.pdev);
+ pcf50633_client_dev_register(pcf, "pcf50633-mbc",
+ &pcf->mbc.pdev);
+ pcf50633_client_dev_register(pcf, "pcf50633-adc",
+ &pcf->adc.pdev);
+ for (i = 0; i < PCF50633_NUM_REGULATORS; i++) {
+ struct platform_device *pdev;
+
+ pdev = platform_device_alloc("pcf50633-regltr", i);
+ if (!pdev) {
+ dev_err(pcf->dev, "Cannot create regulator\n");
+ continue;
+ }
+
+ pdev->dev.parent = pcf->dev;
+ pdev->dev.platform_data = &pdata->reg_init_data[i];
+ pdev->dev.driver_data = pcf;
+ pcf->pmic.pdev[i] = pdev;
+
+ platform_device_add(pdev);
+ }
+
+ pcf->irq = client->irq;
+
+ if (client->irq) {
+ ret = request_irq(client->irq, pcf50633_irq,
+ IRQF_TRIGGER_LOW, "pcf50633", pcf);
+
+ if (ret) {
+ dev_err(pcf->dev, "Failed to request IRQ %d\n", ret);
+ goto err;
+ }
+ } else {
+ dev_err(pcf->dev, "No IRQ configured\n");
+ goto err;
+ }
+
+ if (enable_irq_wake(client->irq) < 0)
+ dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up "
+ "source in this hardware revision\n", client->irq);
+
+ ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group);
+ if (ret)
+ dev_err(pcf->dev, "error creating sysfs entries\n");
+
+ if (pdata->probe_done)
+ pdata->probe_done(pcf);
+
+ return 0;
+
+err:
+ kfree(pcf);
+ return ret;
+}
+
+static int pcf50633_remove(struct i2c_client *client)
+{
+ struct pcf50633 *pcf = i2c_get_clientdata(client);
+
+ free_irq(pcf->irq, pcf);
+ kfree(pcf);
+
+ return 0;
+}
+
+static struct i2c_device_id pcf50633_id_table[] = {
+ {"pcf50633", 0x73},
+};
+
+static struct i2c_driver pcf50633_driver = {
+ .driver = {
+ .name = "pcf50633",
+ .suspend = pcf50633_suspend,
+ .resume = pcf50633_resume,
+ },
+ .id_table = pcf50633_id_table,
+ .probe = pcf50633_probe,
+ .remove = pcf50633_remove,
+};
+
+static int __init pcf50633_init(void)
+{
+ return i2c_add_driver(&pcf50633_driver);
+}
+
+static void pcf50633_exit(void)
+{
+ i2c_del_driver(&pcf50633_driver);
+}
+
+MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
+
+module_init(pcf50633_init);
+module_exit(pcf50633_exit);
--- /dev/null
+++ b/drivers/mfd/pcf50633-gpio.c
@@ -0,0 +1,100 @@
+/* Philips PCF50633 GPIO Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50633 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/gpio.h>
+#include <linux/mfd/pcf50633/pmic.h>
+
+void pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, int val)
+{
+ u8 reg;
+
+ reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
+
+ pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_set);
+
+int pcf50633_gpio_get(struct pcf50633 *pcf, int gpio)
+{
+ u8 reg, val;
+
+ reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
+ val = pcf50633_reg_read(pcf, reg) & 0x07;
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_get);
+
+void pcf50633_gpio_invert_set(struct pcf50633 *pcf, int gpio, int invert)
+{
+ u8 val, reg;
+
+ reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
+ val = !!invert << 3;
+
+ pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_set);
+
+int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio)
+{
+ u8 reg, val;
+
+ reg = gpio - PCF50633_GPIO1 + PCF50633_REG_GPIO1CFG;
+ val = pcf50633_reg_read(pcf, reg);
+
+ return val & (1 << 3);
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_invert_get);
+
+static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
+ [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT,
+ [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT,
+ [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT,
+ [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT,
+ [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT,
+ [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT,
+ [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT,
+ [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT,
+ [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT,
+ [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT,
+ [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT,
+};
+
+void pcf50633_gpio_power_supply_set(struct pcf50633 *pcf,
+ int gpio, int regulator, int on)
+{
+ u8 reg, val, mask;
+
+ /* the *ENA register is always one after the *OUT register */
+ reg = pcf50633_regulator_registers[regulator] + 1;
+
+ val = (!!on << (gpio - PCF50633_GPIO1));
+ mask = (1 << (gpio - PCF50633_GPIO1));
+
+ pcf50633_reg_set_bit_mask(pcf, reg, mask, val);
+}
+EXPORT_SYMBOL_GPL(pcf50633_gpio_power_supply_set);
--- /dev/null
+++ b/drivers/mfd/pcf50633-i2c.c
@@ -0,0 +1,3 @@
+
+};
+
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -401,6 +401,11 @@
If you are not sure, say Y here. The driver enables polling only if
it is strictly necessary to do so.
+config LOW_MEMORY_KILLER
+ tristate "Low Memory Killer"
+ ---help---
+ Register processes to be killed when memory is low.
+
config ATMEL_SSC
tristate "Device driver for Atmel SSC peripheral"
depends on AVR32 || ARCH_AT91
@@ -500,4 +505,9 @@
source "drivers/misc/c2port/Kconfig"
+config MACH_NEO1973
+ bool
+ help
+ Common machine code for Openmoko GTAxx hardware
+
endif # MISC_DEVICES
--- /dev/null
+++ b/drivers/misc/lowmemorykiller.c
@@ -0,0 +1,119 @@
+/* drivers/misc/lowmemorykiller.c
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/oom.h>
+#include <linux/sched.h>
+
+static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask);
+
+static struct shrinker lowmem_shrinker = {
+ .shrink = lowmem_shrink,
+ .seeks = DEFAULT_SEEKS * 16
+};
+static uint32_t lowmem_debug_level = 2;
+static int lowmem_adj[6] = {
+ 0,
+ 1,
+ 6,
+ 12,
+};
+static int lowmem_adj_size = 4;
+static size_t lowmem_minfree[6] = {
+ 3*512, // 6MB
+ 2*1024, // 8MB
+ 4*1024, // 16MB
+ 16*1024, // 64MB
+};
+static int lowmem_minfree_size = 4;
+
+#define lowmem_print(level, x...) do { if(lowmem_debug_level >= (level)) printk(x); } while(0)
+
+module_param_named(cost, lowmem_shrinker.seeks, int, S_IRUGO | S_IWUSR);
+module_param_array_named(adj, lowmem_adj, int, &lowmem_adj_size, S_IRUGO | S_IWUSR);
+module_param_array_named(minfree, lowmem_minfree, uint, &lowmem_minfree_size, S_IRUGO | S_IWUSR);
+module_param_named(debug_level, lowmem_debug_level, uint, S_IRUGO | S_IWUSR);
+
+static int lowmem_shrink(int nr_to_scan, gfp_t gfp_mask)
+{
+ struct task_struct *p;
+ struct task_struct *selected = NULL;
+ int rem = 0;
+ int tasksize;
+ int i;
+ int min_adj = OOM_ADJUST_MAX + 1;
+ int selected_tasksize = 0;
+ int array_size = ARRAY_SIZE(lowmem_adj);
+ int other_free = global_page_state(NR_FREE_PAGES) + global_page_state(NR_FILE_PAGES);
+ if(lowmem_adj_size < array_size)
+ array_size = lowmem_adj_size;
+ if(lowmem_minfree_size < array_size)
+ array_size = lowmem_minfree_size;
+ for(i = 0; i < array_size; i++) {
+ if(other_free < lowmem_minfree[i]) {
+ min_adj = lowmem_adj[i];
+ break;
+ }
+ }
+ if(nr_to_scan > 0)
+ lowmem_print(3, "lowmem_shrink %d, %x, ofree %d, ma %d\n", nr_to_scan, gfp_mask, other_free, min_adj);
+ read_lock(&tasklist_lock);
+ for_each_process(p) {
+ if(p->oomkilladj >= 0 && p->mm) {
+ tasksize = get_mm_rss(p->mm);
+ if(nr_to_scan > 0 && tasksize > 0 && p->oomkilladj >= min_adj) {
+ if(selected == NULL ||
+ p->oomkilladj > selected->oomkilladj ||
+ (p->oomkilladj == selected->oomkilladj &&
+ tasksize > selected_tasksize)) {
+ selected = p;
+ selected_tasksize = tasksize;
+ lowmem_print(2, "select %d (%s), adj %d, size %d, to kill\n",
+ p->pid, p->comm, p->oomkilladj, tasksize);
+ }
+ }
+ rem += tasksize;
+ }
+ }
+ if(selected != NULL) {
+ lowmem_print(1, "send sigkill to %d (%s), adj %d, size %d\n",
+ selected->pid, selected->comm,
+ selected->oomkilladj, selected_tasksize);
+ force_sig(SIGKILL, selected);
+ rem -= selected_tasksize;
+ }
+ lowmem_print(4, "lowmem_shrink %d, %x, return %d\n", nr_to_scan, gfp_mask, rem);
+ read_unlock(&tasklist_lock);
+ return rem;
+}
+
+static int __init lowmem_init(void)
+{
+ register_shrinker(&lowmem_shrinker);
+ return 0;
+}
+
+static void __exit lowmem_exit(void)
+{
+ unregister_shrinker(&lowmem_shrinker);
+}
+
+module_init(lowmem_init);
+module_exit(lowmem_exit);
+
+MODULE_LICENSE("GPL");
+
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -33,3 +33,8 @@
obj-$(CONFIG_SGI_GRU) += sgi-gru/
obj-$(CONFIG_HP_ILO) += hpilo.o
obj-$(CONFIG_C2PORT) += c2port/
+obj-$(CONFIG_MACH_SMDK6410) += smdk6410-sleeptest.o
+obj-$(CONFIG_LOW_MEMORY_KILLER) += lowmemorykiller.o
+obj-$(CONFIG_MACH_NEO1973) += neo1973_version.o \
+ neo1973_pm_host.o \
+ neo1973_pm_resume_reason.o
--- /dev/null
+++ b/drivers/misc/neo1973_pm_charging_led.c
@@ -0,0 +1,106 @@
+/*
+ * Charging LED sysfs for the FIC Neo1973 GSM Phone
+ * (currently only implemented in GTA02 but ready for GTA01 implementation)
+ *
+ * (C) 2008 by Openmoko Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License charging_led 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+#include <asm/arch/gta02.h>
+
+static enum neo1973_charging_led_modes charging_mode;
+
+static char *charging_led_mode_names[] = {
+ "Disabled",
+ "Aux LED",
+ "Power LED"
+};
+
+static ssize_t charging_led_read(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
+}
+
+static ssize_t charging_led_read(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
+}
+
+
+static DEVICE_ATTR(pcb, 0644, charging_led_read, charging_led_write);
+
+static struct attribute *neo1973_charging_led_sysfs_entries[] = {
+ &dev_attr_pcb.attr,
+ NULL
+};
+
+static struct attribute_group neo1973_charging_led_attr_group = {
+ .name = NULL,
+ .attrs = neo1973_charging_led_sysfs_entries,
+};
+
+static int __init neo1973_charging_led_probe(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "starting\n");
+
+ switch (machine_arch_type) {
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ case MACH_TYPE_NEO1973_GTA01:
+ return -EINVAL;
+#endif /* CONFIG_MACH_NEO1973_GTA01 */
+ default:
+ break;
+ }
+
+ return sysfs_create_group(&pdev->dev.kobj,
+ &neo1973_charging_led_attr_group);
+}
+
+static int neo1973_charging_led_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &neo1973_charging_led_attr_group);
+ return 0;
+}
+
+static struct platform_driver neo1973_charging_led_driver = {
+ .probe = neo1973_charging_led_probe,
+ .remove = neo1973_charging_led_remove,
+ .driver = {
+ .name = "neo1973-charging-led",
+ },
+};
+
+static int __devinit neo1973_charging_led_init(void)
+{
+ return platform_driver_register(&neo1973_charging_led_driver);
+}
+
+static void neo1973_charging_led_exit(void)
+{
+ platform_driver_unregister(&neo1973_charging_led_driver);
+}
+
+module_init(neo1973_charging_led_init);
+module_exit(neo1973_charging_led_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Neo1973 PCB charging_led");
+#endif
--- /dev/null
+++ b/drivers/misc/neo1973_pm_host.c
@@ -0,0 +1,109 @@
+/*
+ * Bluetooth PM code for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2007 by Openmoko Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+#include <mach/gta02.h>
+#include <linux/mfd/pcf50633/gpio.h>
+
+static ssize_t pm_host_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%d\n",
+ pcf50633_gpio_get(gta02_pcf_pdata.pcf, PCF50633_GPO)
+ == PCF50633_GPOCFG_GPOSEL_1);
+}
+
+static ssize_t pm_host_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long on = simple_strtoul(buf, NULL, 10);
+ u8 val;
+
+ if (on)
+ val = PCF50633_GPOCFG_GPOSEL_1;
+ else
+ val = PCF50633_GPOCFG_GPOSEL_0;
+
+
+ pcf50633_gpio_set(gta02_pcf_pdata.pcf, PCF50633_GPO, val);
+
+ return count;
+}
+
+static DEVICE_ATTR(hostmode, 0644, pm_host_read, pm_host_write);
+
+static struct attribute *neo1973_pm_host_sysfs_entries[] = {
+ &dev_attr_hostmode.attr,
+ NULL
+};
+
+static struct attribute_group neo1973_pm_host_attr_group = {
+ .name = NULL,
+ .attrs = neo1973_pm_host_sysfs_entries,
+};
+
+static int __init neo1973_pm_host_probe(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "starting\n");
+
+ switch (machine_arch_type) {
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ case MACH_TYPE_NEO1973_GTA01:
+ return -EINVAL;
+#endif /* CONFIG_MACH_NEO1973_GTA01 */
+ default:
+ break;
+ }
+
+ return sysfs_create_group(&pdev->dev.kobj, &neo1973_pm_host_attr_group);
+}
+
+static int neo1973_pm_host_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &neo1973_pm_host_attr_group);
+ return 0;
+}
+
+static struct platform_driver neo1973_pm_host_driver = {
+ .probe = neo1973_pm_host_probe,
+ .remove = neo1973_pm_host_remove,
+ .driver = {
+ .name = "neo1973-pm-host",
+ },
+};
+
+static int __devinit neo1973_pm_host_init(void)
+{
+ return platform_driver_register(&neo1973_pm_host_driver);
+}
+
+static void neo1973_pm_host_exit(void)
+{
+ platform_driver_unregister(&neo1973_pm_host_driver);
+}
+
+module_init(neo1973_pm_host_init);
+module_exit(neo1973_pm_host_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Neo1973 USB Host Power Management");
+#endif
--- /dev/null
+++ b/drivers/misc/neo1973_pm_resume_reason.c
@@ -0,0 +1,147 @@
+/*
+ * Resume reason sysfs for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2008 by Openmoko Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License resume_reason 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+#include <mach/gta02.h>
+#include <linux/mfd/pcf50633/core.h>
+#endif
+
+static unsigned int *gstatus4_mapped;
+static char *resume_reasons[][17] = { { /* GTA01 */
+ "EINT00_NULL",
+ "EINT01_GSM",
+ "EINT02_NULL",
+ "EINT03_NULL",
+ "EINT04_JACK",
+ "EINT05_SDCARD",
+ "EINT06_AUXKEY",
+ "EINT07_HOLDKEY",
+ "EINT08_NULL",
+ "EINT09_NULL",
+ "EINT10_NULL",
+ "EINT11_NULL",
+ "EINT12_NULL",
+ "EINT13_NULL",
+ "EINT14_NULL",
+ "EINT15_NULL",
+ NULL
+}, { /* GTA02 */
+ "EINT00_ACCEL1",
+ "EINT01_GSM",
+ "EINT02_BLUETOOTH",
+ "EINT03_DEBUGBRD",
+ "EINT04_JACK",
+ "EINT05_WLAN",
+ "EINT06_AUXKEY",
+ "EINT07_HOLDKEY",
+ "EINT08_ACCEL2",
+ "EINT09_PMU",
+ "EINT10_NULL",
+ "EINT11_NULL",
+ "EINT12_GLAMO",
+ "EINT13_NULL",
+ "EINT14_NULL",
+ "EINT15_NULL",
+ NULL
+} };
+
+static ssize_t resume_reason_read(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int bit = 0;
+ char *end = buf;
+ int gta = !!machine_is_neo1973_gta02();
+
+ for (bit = 0; resume_reasons[gta][bit]; bit++) {
+ if ((*gstatus4_mapped) & (1 << bit))
+ end += sprintf(end, "* %s\n", resume_reasons[gta][bit]);
+ else
+ end += sprintf(end, " %s\n", resume_reasons[gta][bit]);
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ if ((gta) && (bit == 9)); /* PMU */
+// end += pcf50633_report_resumers(gta02_pcf_pdata.pcf, end);
+#endif
+ }
+
+ return end - buf;
+}
+
+
+static DEVICE_ATTR(resume_reason, 0644, resume_reason_read, NULL);
+
+static struct attribute *neo1973_resume_reason_sysfs_entries[] = {
+ &dev_attr_resume_reason.attr,
+ NULL
+};
+
+static struct attribute_group neo1973_resume_reason_attr_group = {
+ .name = NULL,
+ .attrs = neo1973_resume_reason_sysfs_entries,
+};
+
+static int __init neo1973_resume_reason_probe(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "starting\n");
+
+ gstatus4_mapped = ioremap(0x560000BC /* GSTATUS4 */, 0x4);
+ if (!gstatus4_mapped) {
+ dev_err(&pdev->dev, "failed to ioremap() memory region\n");
+ return -EINVAL;
+ }
+
+ return sysfs_create_group(&pdev->dev.kobj,
+ &neo1973_resume_reason_attr_group);
+}
+
+static int neo1973_resume_reason_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &neo1973_resume_reason_attr_group);
+ iounmap(gstatus4_mapped);
+ return 0;
+}
+
+static struct platform_driver neo1973_resume_reason_driver = {
+ .probe = neo1973_resume_reason_probe,
+ .remove = neo1973_resume_reason_remove,
+ .driver = {
+ .name = "neo1973-resume",
+ },
+};
+
+static int __devinit neo1973_resume_reason_init(void)
+{
+ return platform_driver_register(&neo1973_resume_reason_driver);
+}
+
+static void neo1973_resume_reason_exit(void)
+{
+ platform_driver_unregister(&neo1973_resume_reason_driver);
+}
+
+module_init(neo1973_resume_reason_init);
+module_exit(neo1973_resume_reason_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Neo1973 resume_reason");
--- /dev/null
+++ b/drivers/misc/neo1973_pm_usbhost.c
@@ -0,0 +1,132 @@
+/*
+ * Bluetooth PM code for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2007 by OpenMoko Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+#include <asm/arch/gta02.h>
+#include <linux/pcf50633.h>
+#endif
+
+static ssize_t pm_usbhost_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%d\n",
+ pcf50633_gpio_get(pcf50633_global, PCF50633_GPO));
+}
+
+static ssize_t pm_usbhost_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long on = simple_strtoul(buf, NULL, 10);
+
+ pcf50633_gpio_set(pcf50633_global, PCF50633_GPO, on);
+
+ return count;
+}
+
+static DEVICE_ATTR(hostmode, 0644, pm_usbhost_read, pm_usbhost_write);
+
+#ifdef CONFIG_PM
+static int neo1973_usbhost_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ dev_dbg(&pdev->dev, "suspending\n");
+ /* FIXME: The PMU should save the PMU status, and the GPIO code should
+ * preserve the GPIO level, so there shouldn't be anything left to do
+ * for us, should there? */
+
+ return 0;
+}
+
+static int neo1973_usbhost_resume(struct platform_device *pdev)
+{
+ dev_dbg(&pdev->dev, "resuming\n");
+
+ return 0;
+}
+#else
+#define neo1973_usbhost_suspend NULL
+#define neo1973_usbhost_resume NULL
+#endif
+
+static struct attribute *neo1973_usbhost_sysfs_entries[] = {
+ &dev_attr_hostmode.attr,
+ NULL
+};
+
+static struct attribute_group neo1973_usbhost_attr_group = {
+ .name = NULL,
+ .attrs = neo1973_usbhost_sysfs_entries,
+};
+
+static int __init neo1973_usbhost_probe(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "starting\n");
+
+ switch (machine_arch_type) {
+
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ case MACH_TYPE_NEO1973_GTA01:
+ return -EINVAL;
+#endif /* CONFIG_MACH_NEO1973_GTA01 */
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ case MACH_TYPE_NEO1973_GTA02:
+/* race */
+/* pcf50633_gpio_set(pcf50633_global, PCF50633_GPO, 0); */
+ break;
+#endif /* CONFIG_MACH_NEO1973_GTA02 */
+ }
+
+ return sysfs_create_group(&pdev->dev.kobj, &neo1973_usbhost_attr_group);
+}
+
+static int neo1973_usbhost_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &neo1973_usbhost_attr_group);
+
+ return 0;
+}
+
+static struct platform_driver neo1973_usbhost_driver = {
+ .probe = neo1973_usbhost_probe,
+ .remove = neo1973_usbhost_remove,
+ .suspend = neo1973_usbhost_suspend,
+ .resume = neo1973_usbhost_resume,
+ .driver = {
+ .name = "neo1973-pm-host",
+ },
+};
+
+static int __devinit neo1973_usbhost_init(void)
+{
+ return platform_driver_register(&neo1973_usbhost_driver);
+}
+
+static void neo1973_usbhost_exit(void)
+{
+ platform_driver_unregister(&neo1973_usbhost_driver);
+}
+
+module_init(neo1973_usbhost_init);
+module_exit(neo1973_usbhost_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Neo1973 USB Host Power Management");
--- /dev/null
+++ b/drivers/misc/neo1973_version.c
@@ -0,0 +1,90 @@
+/*
+ * PCB version sysfs for the FIC Neo1973 GSM Phone
+ *
+ * (C) 2007 by Openmoko Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#ifdef CONFIG_MACH_NEO1973_GTA02
+#include <mach/gta02.h>
+
+static ssize_t version_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "0x%03X\n", gta02_get_pcb_revision());
+}
+
+
+static DEVICE_ATTR(pcb, 0644, version_read, NULL);
+
+static struct attribute *neo1973_version_sysfs_entries[] = {
+ &dev_attr_pcb.attr,
+ NULL
+};
+
+static struct attribute_group neo1973_version_attr_group = {
+ .name = NULL,
+ .attrs = neo1973_version_sysfs_entries,
+};
+
+static int __init neo1973_version_probe(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "starting\n");
+
+ switch (machine_arch_type) {
+#ifdef CONFIG_MACH_NEO1973_GTA01
+ case MACH_TYPE_NEO1973_GTA01:
+ return -EINVAL;
+#endif /* CONFIG_MACH_NEO1973_GTA01 */
+ default:
+ break;
+ }
+
+ return sysfs_create_group(&pdev->dev.kobj, &neo1973_version_attr_group);
+}
+
+static int neo1973_version_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &neo1973_version_attr_group);
+ return 0;
+}
+
+static struct platform_driver neo1973_version_driver = {
+ .probe = neo1973_version_probe,
+ .remove = neo1973_version_remove,
+ .driver = {
+ .name = "neo1973-version",
+ },
+};
+
+static int __devinit neo1973_version_init(void)
+{
+ return platform_driver_register(&neo1973_version_driver);
+}
+
+static void neo1973_version_exit(void)
+{
+ platform_driver_unregister(&neo1973_version_driver);
+}
+
+module_init(neo1973_version_init);
+module_exit(neo1973_version_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("Neo1973 PCB version");
+#endif
--- /dev/null
+++ b/drivers/misc/smdk6410-sleeptest.c
@@ -0,0 +1,65 @@
+/* linux/drivers/misc/smdk6410-sleeptest.c
+ *
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+
+#include <plat/gpio-cfg.h>
+
+static irqreturn_t sleep_action(int irq, void *pw)
+{
+ printk(KERN_INFO "%s: irq %d\n", __func__, irq);
+ return IRQ_HANDLED;
+}
+
+static void sleep_setup(unsigned int irq, unsigned int gpio)
+{
+ int ret;
+
+ WARN_ON(s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)) < 0);
+ WARN_ON(s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP) < 0);
+
+ ret = request_irq(irq, sleep_action, IRQF_TRIGGER_FALLING,
+ "sleep", NULL);
+ if (ret < 0)
+ printk(KERN_ERR "%s: request_irq() failed\n", __func__);
+
+ ret = set_irq_wake(irq, 1);
+ if (ret < 0)
+ printk(KERN_ERR "%s: set_irq_wake() failed\n", __func__);
+}
+
+static void sleep_led(unsigned int gpio)
+{
+ gpio_request(gpio, "sleep led");
+ gpio_direction_output(gpio, 0);
+}
+
+static __init int smdk6410_sleeptest_init(void)
+{
+ sleep_setup(IRQ_EINT(10), S3C64XX_GPN(10));
+ sleep_led(S3C64XX_GPN(15));
+ sleep_led(S3C64XX_GPN(14));
+ sleep_led(S3C64XX_GPN(13));
+ sleep_led(S3C64XX_GPN(12));
+
+ return 0;
+}
+
+module_init(smdk6410_sleeptest_init);
+
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -57,10 +57,11 @@
/*
* Internal function. Flush all scheduled work from the MMC work queue.
*/
-static void mmc_flush_scheduled_work(void)
+void mmc_flush_scheduled_work(void)
{
flush_workqueue(workqueue);
}
+EXPORT_SYMBOL_GPL(mmc_flush_scheduled_work);
/**
* mmc_request_done - finish processing an MMC request
@@ -495,7 +496,13 @@
*/
static void mmc_power_up(struct mmc_host *host)
{
- int bit = fls(host->ocr_avail) - 1;
+ int bit;
+
+ /* If ocr is set, we use it */
+ if (host->ocr)
+ bit = ffs(host->ocr) - 1;
+ else
+ bit = fls(host->ocr_avail) - 1;
host->ios.vdd = bit;
if (mmc_host_is_spi(host)) {
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -48,6 +48,18 @@
If unsure, say N.
+config MMC_SDHCI_S3C
+ tristate "SDHCI support on Samsung S3C SoC"
+ depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ often referrered to as the HSMMC block in some of the Samsung S3C
+ range of SoC.
+
+ If you have a controller with this interface, say Y or M here.
+
+ If unsure, say N.
+
config MMC_RICOH_MMC
tristate "Ricoh MMC Controller Disabler (EXPERIMENTAL)"
depends on MMC_SDHCI_PCI
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_MMC_IMX) += imxmmc.o
obj-$(CONFIG_MMC_SDHCI) += sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
+obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -2,6 +2,7 @@
* linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
*
* Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
+ * Copyright (C) 2007 Harald Welte <laforge@gnumonks.org>
*
* Current driver maintained by Ben Dooks and Simtec Electronics
* Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
@@ -25,7 +26,15 @@
#include <mach/regs-sdi.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c24xx/mci.h>
+#include <plat/mci.h>
+
+#include <asm/dma.h>
+#include <asm/dma-mapping.h>
+
+#include <asm/io.h>
+#include <mach/regs-gpio.h>
+#include <mach/mci.h>
+#include <mach/dma.h>
#include "s3cmci.h"
@@ -47,6 +56,9 @@
static const int dbgmap_info = dbg_info | dbg_conf;
static const int dbgmap_debug = dbg_err | dbg_debug;
+static int f_max = -1; /* override maximum frequency limit */
+static int persist; /* keep interface alive across suspend/resume */
+
#define dbg(host, channels, args...) \
do { \
if (dbgmap_err & channels) \
@@ -280,8 +292,11 @@
* an even multiple of 4. */
if (fifo >= host->pio_bytes)
fifo = host->pio_bytes;
- else
+ else {
fifo -= fifo & 3;
+ if (!fifo)
+ break;
+ }
host->pio_bytes -= fifo;
host->pio_count += fifo;
@@ -353,8 +368,11 @@
* words, so round down to an even multiple of 4. */
if (fifo >= host->pio_bytes)
fifo = host->pio_bytes;
- else
+ else {
fifo -= fifo & 3;
+ if (!fifo)
+ break;
+ }
host->pio_bytes -= fifo;
host->pio_count += fifo;
@@ -373,7 +391,6 @@
{
struct s3cmci_host *host = (struct s3cmci_host *) data;
-
disable_irq(host->irq);
if (host->pio_active == XFER_WRITE)
@@ -614,7 +631,6 @@
spin_unlock_irqrestore(&host->complete_lock, iflags);
return IRQ_HANDLED;
-
}
/*
@@ -1026,6 +1042,7 @@
dbg(host, dbg_err, "data prepare error %d\n", res);
cmd->error = res;
cmd->data->error = res;
+ cmd->data->error = -EIO;
mmc_request_done(mmc, mrq);
return;
@@ -1263,10 +1280,8 @@
host->is2440 = is2440;
host->pdata = pdev->dev.platform_data;
- if (!host->pdata) {
- pdev->dev.platform_data = &s3cmci_def_pdata;
+ if (!host->pdata)
host->pdata = &s3cmci_def_pdata;
- }
spin_lock_init(&host->complete_lock);
tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
@@ -1379,6 +1394,18 @@
mmc->f_min = host->clk_rate / (host->clk_div * 256);
mmc->f_max = host->clk_rate / host->clk_div;
+ if (f_max >= 0) {
+ unsigned f = f_max;
+
+ if (f < mmc->f_min)
+ f = mmc->f_min;
+ if (mmc->f_max > f) {
+ dev_info(&pdev->dev, "f_max lowered from %u to %u Hz\n",
+ mmc->f_max, f);
+ mmc->f_max = f;
+ }
+ }
+
if (host->pdata->ocr_avail)
mmc->ocr_avail = host->pdata->ocr_avail;
@@ -1491,18 +1518,60 @@
#ifdef CONFIG_PM
+static int save_regs(struct mmc_host *mmc)
+{
+ struct s3cmci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+ unsigned from;
+ u32 *to = host->saved;
+
+ mmc_flush_scheduled_work();
+
+ local_irq_save(flags);
+ for (from = S3C2410_SDICON; from != S3C2410_SDIIMSK+4; from += 4)
+ if (from != host->sdidata)
+ *to++ = readl(host->base + from);
+ BUG_ON(to-host->saved != ARRAY_SIZE(host->saved));
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+static int restore_regs(struct mmc_host *mmc)
+{
+ struct s3cmci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+ unsigned to;
+ u32 *from = host->saved;
+
+ /*
+ * Before we begin with the necromancy, make sure we don't
+ * inadvertently start something we'll regret microseconds later.
+ */
+ from[S3C2410_SDICMDCON - S3C2410_SDICON] = 0;
+
+ local_irq_save(flags);
+ for (to = S3C2410_SDICON; to != S3C2410_SDIIMSK+4; to += 4)
+ if (to != host->sdidata)
+ writel(*from++, host->base + to);
+ BUG_ON(from-host->saved != ARRAY_SIZE(host->saved));
+ local_irq_restore(flags);
+
+ return 0;
+}
+
static int s3cmci_suspend(struct platform_device *dev, pm_message_t state)
{
struct mmc_host *mmc = platform_get_drvdata(dev);
- return mmc_suspend_host(mmc, state);
+ return persist ? save_regs(mmc) : mmc_suspend_host(mmc, state);
}
static int s3cmci_resume(struct platform_device *dev)
{
struct mmc_host *mmc = platform_get_drvdata(dev);
- return mmc_resume_host(mmc);
+ return persist ? restore_regs(mmc) : mmc_resume_host(mmc);
}
#else /* CONFIG_PM */
@@ -1560,9 +1629,13 @@
module_init(s3cmci_init);
module_exit(s3cmci_exit);
+module_param(f_max, int, 0644);
+module_param(persist, int, 0644);
+
MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
MODULE_ALIAS("platform:s3c2410-sdi");
MODULE_ALIAS("platform:s3c2412-sdi");
MODULE_ALIAS("platform:s3c2440-sdi");
+
--- a/drivers/mmc/host/s3cmci.h
+++ b/drivers/mmc/host/s3cmci.h
@@ -8,6 +8,9 @@
* published by the Free Software Foundation.
*/
+
+#include <mach/regs-sdi.h>
+
/* FIXME: DMA Resource management ?! */
#define S3CMCI_DMA 0
@@ -68,6 +71,13 @@
unsigned int ccnt, dcnt;
struct tasklet_struct pio_tasklet;
+ /*
+ * Here's where we save the registers during suspend. Note that we skip
+ * SDIDATA, which is at different positions on 2410 and 2440, so
+ * there's no "+1" in the array size.
+ */
+ u32 saved[(S3C2410_SDIIMSK-S3C2410_SDICON)/4];
+
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -73,6 +73,11 @@
readl(host->ioaddr + SDHCI_CAPABILITIES),
readl(host->ioaddr + SDHCI_MAX_CURRENT));
+ if (host->flags & SDHCI_USE_ADMA)
+ printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
+ readl(host->ioaddr + SDHCI_ADMA_ERROR),
+ readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
+
printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
}
@@ -731,6 +736,23 @@
writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
}
+static void shdci_check_dma_overrun(struct sdhci_host *host, struct mmc_data *data)
+{
+ u32 dma_pos = readl(host->ioaddr + SDHCI_DMA_ADDRESS);
+ u32 dma_start = sg_dma_address(data->sg);
+ u32 dma_end = dma_start + data->sg->length;
+
+ /* Test whether we ended up moving more data than
+ * was originally requested. */
+
+ if (dma_pos <= dma_end)
+ return;
+
+ printk(KERN_ERR "%s: dma overrun, dma %08x, req %08x..%08x\n",
+ mmc_hostname(host->mmc), dma_pos,
+ dma_start, dma_end);
+}
+
static void sdhci_finish_data(struct sdhci_host *host)
{
struct mmc_data *data;
@@ -744,6 +766,8 @@
if (host->flags & SDHCI_USE_ADMA)
sdhci_adma_table_post(host, data);
else {
+ shdci_check_dma_overrun(host, data);
+
dma_unmap_sg(mmc_dev(host->mmc), data->sg,
data->sg_len, (data->flags & MMC_DATA_READ) ?
DMA_FROM_DEVICE : DMA_TO_DEVICE);
@@ -883,13 +907,18 @@
static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
+ if (clock == host->clock)
+ return;
+
+ host->ops->change_clock(host, clock);
+}
+
+void sdhci_change_clock(struct sdhci_host *host, unsigned int clock)
+{
int div;
u16 clk;
unsigned long timeout;
- if (clock == host->clock)
- return;
-
writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
if (clock == 0)
@@ -926,6 +955,8 @@
host->clock = clock;
}
+EXPORT_SYMBOL_GPL(sdhci_set_clock);
+
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
u8 pwr;
@@ -999,12 +1030,13 @@
#endif
host->mrq = mrq;
-
+/*
if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
|| (host->flags & SDHCI_DEVICE_DEAD)) {
host->mrq->cmd->error = -ENOMEDIUM;
tasklet_schedule(&host->finish_tasklet);
} else
+*/
sdhci_send_command(host, mrq->cmd);
mmiowb();
@@ -1033,6 +1065,9 @@
sdhci_init(host);
}
+ if (host->ops->set_ios)
+ host->ops->set_ios(host, ios);
+
sdhci_set_clock(host, ios->clock);
if (ios->power_mode == MMC_POWER_OFF)
@@ -1136,7 +1171,7 @@
host = (struct sdhci_host*)param;
spin_lock_irqsave(&host->lock, flags);
-
+/*
if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
if (host->mrq) {
printk(KERN_ERR "%s: Card removed during transfer!\n",
@@ -1151,7 +1186,7 @@
tasklet_schedule(&host->finish_tasklet);
}
}
-
+*/
spin_unlock_irqrestore(&host->lock, flags);
mmc_detect_change(host->mmc, msecs_to_jiffies(200));
@@ -1607,17 +1642,23 @@
mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
}
- host->max_clk =
- (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ if (host->ops->get_max_clock)
+ host->max_clk = host->ops->get_max_clock(host);
+ else {
+ host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ host->max_clk *= 1000000;
+ }
if (host->max_clk == 0) {
printk(KERN_ERR "%s: Hardware doesn't specify base clock "
"frequency.\n", mmc_hostname(mmc));
return -ENODEV;
}
- host->max_clk *= 1000000;
- host->timeout_clk =
- (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
+ if (host->ops->get_timeout_clock)
+ host->timeout_clk = host->ops->get_timeout_clock(host);
+ else
+ host->timeout_clk =
+ (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
if (host->timeout_clk == 0) {
printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
"frequency.\n", mmc_hostname(mmc));
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -57,6 +57,7 @@
#define SDHCI_DATA_AVAILABLE 0x00000800
#define SDHCI_CARD_PRESENT 0x00010000
#define SDHCI_WRITE_PROTECT 0x00080000
+#define SDHCI_DATA_BIT(x) (1 << ((x) + 20))
#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_LED 0x01
@@ -270,6 +271,14 @@
struct sdhci_ops {
int (*enable_dma)(struct sdhci_host *host);
+ unsigned int (*get_max_clock)(struct sdhci_host *host);
+ unsigned int (*get_timeout_clock)(struct sdhci_host *host);
+
+ void (*change_clock)(struct sdhci_host *host,
+ unsigned int clock);
+
+ void (*set_ios)(struct sdhci_host *host,
+ struct mmc_ios *ios);
};
@@ -277,6 +286,8 @@
size_t priv_size);
extern void sdhci_free_host(struct sdhci_host *host);
+extern void sdhci_change_clock(struct sdhci_host *host, unsigned int clock);
+
static inline void *sdhci_priv(struct sdhci_host *host)
{
return (void *)host->private;
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -392,6 +392,7 @@
static struct sdhci_ops sdhci_pci_ops = {
.enable_dma = sdhci_pci_enable_dma,
+ .change_clock = sdhci_change_clock,
};
/*****************************************************************************\
--- /dev/null
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -0,0 +1,419 @@
+/* linux/drivers/mmc/host/sdhci-s3c.c
+ *
+ * Copyright 2008 Openmoko Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * SDHCI (HSMMC) support for Samsung SoC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+#include "sdhci.h"
+
+#define MAX_BUS_CLK (4)
+
+struct sdhci_s3c {
+ struct sdhci_host *host;
+ struct platform_device *pdev;
+ struct resource *ioarea;
+ struct s3c_sdhci_platdata *pdata;
+ unsigned int cur_clk;
+
+ struct clk *clk_io; /* clock for io bus */
+ struct clk *clk_bus[MAX_BUS_CLK];
+};
+
+static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
+{
+ return sdhci_priv(host);
+}
+
+static u32 get_curclk(u32 ctrl2)
+{
+ ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+ ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
+
+ return ctrl2;
+}
+
+static void sdhci_s3c_check_sclk(struct sdhci_host *host)
+{
+ struct sdhci_s3c *ourhost = to_s3c(host);
+ u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+
+ if (get_curclk(tmp) != ourhost->cur_clk) {
+ dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
+
+ tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+ tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
+ writel(tmp, host->ioaddr + 0x80);
+ }
+}
+
+static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
+{
+ struct sdhci_s3c *ourhost = to_s3c(host);
+ struct clk *busclk;
+ unsigned int rate, max;
+ int clk;
+
+ /* note, a reset will reset the clock source */
+
+ sdhci_s3c_check_sclk(host);
+
+ for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
+ busclk = ourhost->clk_bus[clk];
+ if (!busclk)
+ continue;
+
+ rate = clk_get_rate(busclk);
+ if (rate > max)
+ max = rate;
+ }
+
+ return max;
+}
+
+static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
+{
+ return sdhci_s3c_get_max_clk(host) / 1000000;
+}
+
+static void sdhci_s3c_set_ios(struct sdhci_host *host,
+ struct mmc_ios *ios)
+{
+ struct sdhci_s3c *ourhost = to_s3c(host);
+ struct s3c_sdhci_platdata *pdata = ourhost->pdata;
+ int width;
+
+ sdhci_s3c_check_sclk(host);
+
+ if (ios->power_mode != MMC_POWER_OFF) {
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_4:
+ width = 4;
+ break;
+ case MMC_BUS_WIDTH_1:
+ width = 1;
+ break;
+ default:
+ BUG();
+ }
+
+ if (pdata->cfg_gpio)
+ pdata->cfg_gpio(ourhost->pdev, width);
+ }
+
+ if (pdata->cfg_card)
+ pdata->cfg_card(ourhost->pdev, host->ioaddr,
+ ios, host->mmc->card);
+}
+
+static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
+ unsigned int src,
+ unsigned int wanted)
+{
+ unsigned long rate;
+ struct clk *clksrc = ourhost->clk_bus[src];
+ int div;
+
+ if (!clksrc)
+ return UINT_MAX;
+
+ rate = clk_get_rate(clksrc);
+
+ for (div = 1; div < 256; div *= 2) {
+ if ((rate / div) <= wanted)
+ break;
+ }
+
+ dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
+ src, rate, wanted, rate / div);
+
+ return (wanted - (rate / div));
+}
+
+static void sdhci_s3c_change_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_s3c *ourhost = to_s3c(host);
+ unsigned int best = UINT_MAX;
+ unsigned int delta;
+ int best_src = 0;
+ int src;
+ u32 ctrl;
+
+ for (src = 0; src < MAX_BUS_CLK; src++) {
+ delta = sdhci_s3c_consider_clock(ourhost, src, clock);
+ if (delta < best) {
+ best = delta;
+ best_src = src;
+ }
+ }
+
+ dev_dbg(&ourhost->pdev->dev,
+ "selected source %d, clock %d, delta %d\n",
+ best_src, clock, best);
+
+ /* turn clock off to card before changing clock source */
+ writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+ /* select the new clock source */
+
+ if (ourhost->cur_clk != best_src) {
+ struct clk *clk = ourhost->clk_bus[best_src];
+
+ ourhost->cur_clk = best_src;
+ host->max_clk = clk_get_rate(clk);
+ host->timeout_clk = host->max_clk / 1000000;
+
+ ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+ ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+ ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
+ writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
+ }
+
+ sdhci_change_clock(host, clock);
+}
+
+static struct sdhci_ops sdhci_s3c_ops = {
+ .get_max_clock = sdhci_s3c_get_max_clk,
+ .get_timeout_clock = sdhci_s3c_get_timeout_clk,
+ .change_clock = sdhci_s3c_change_clock,
+ .set_ios = sdhci_s3c_set_ios,
+};
+
+/*
+ * call this when you need sd stack to recognize insertion or removal of card
+ * that can't be told by SDHCI regs
+ */
+
+void sdhci_s3c_force_presence_change(struct platform_device *pdev)
+{
+ struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
+
+ dev_info(&pdev->dev, "sdhci_s3c_force_presence_change called\n");
+ mmc_detect_change(pdata->sdhci_host->mmc, msecs_to_jiffies(200));
+}
+EXPORT_SYMBOL_GPL(sdhci_s3c_force_presence_change);
+
+
+static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
+{
+ struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
+ struct device *dev = &pdev->dev;
+ struct sdhci_host *host;
+ struct sdhci_s3c *sc;
+ struct resource *res;
+ int ret, irq, ptr, clks;
+
+ if (!pdata) {
+ dev_err(dev, "no device data specified\n");
+ return -ENOENT;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "no irq specified\n");
+ return irq;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "no memory specified\n");
+ return -ENOENT;
+ }
+
+ host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
+ if (IS_ERR(host)) {
+ dev_err(dev, "sdhci_alloc_host() failed\n");
+ return PTR_ERR(host);
+ }
+
+ pdata->sdhci_host = host;
+
+ sc = sdhci_priv(host);
+
+ sc->host = host;
+ sc->pdev = pdev;
+ sc->pdata = pdata;
+
+ platform_set_drvdata(pdev, host);
+
+ sc->clk_io = clk_get(dev, "hsmmc");
+ if (IS_ERR(sc->clk_io)) {
+ dev_err(dev, "failed to get io clock\n");
+ ret = PTR_ERR(sc->clk_io);
+ goto err_io_clk;
+ }
+
+ /* enable the local io clock and keep it running for the moment. */
+ clk_enable(sc->clk_io);
+
+ for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
+ struct clk *clk;
+ char *name = pdata->clocks[ptr];
+
+ if (name == NULL)
+ continue;
+
+ clk = clk_get(dev, name);
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock %s\n", name);
+ continue;
+ }
+
+ clks++;
+ sc->clk_bus[ptr] = clk;
+ clk_enable(clk);
+
+ dev_info(dev, "clock source %d: %s (%ld Hz)\n",
+ ptr, name, clk_get_rate(clk));
+ }
+
+ if (clks == 0) {
+ dev_err(dev, "failed to find any bus clocks\n");
+ ret = -ENOENT;
+ goto err_no_busclks;
+ }
+
+ sc->ioarea = request_mem_region(res->start, resource_size(res),
+ mmc_hostname(host->mmc));
+ if (!sc->ioarea) {
+ dev_err(dev, "failed to reserve register area\n");
+ ret = -ENXIO;
+ goto err_req_regs;
+ }
+
+ host->ioaddr = ioremap_nocache(res->start, resource_size(res));
+ if (!host->ioaddr) {
+ dev_err(dev, "failed to map registers\n");
+ ret = -ENXIO;
+ goto err_req_regs;
+ }
+
+ /* Ensure we have minimal gpio selected CMD/CLK/Detect */
+ if (pdata->cfg_gpio)
+ pdata->cfg_gpio(pdev, 0);
+
+ sdhci_s3c_check_sclk(host);
+
+ host->hw_name = "samsung-hsmmc";
+ host->ops = &sdhci_s3c_ops;
+ host->quirks = 0;
+ host->irq = irq;
+
+ /* Setup quirks for the controller */
+
+ /* Currently with ADMA enabled we are getting some length
+ * interrupts that are not being dealt with, do disable
+ * ADMA until this is sorted out. */
+ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+ host->quirks |= SDHCI_QUIRK_32BIT_ADMA_SIZE;
+
+ /* It seems we do not get an DATA transfer complete on non-busy
+ * transfers, not sure if this is a problem with this specific
+ * SDHCI block, or a missing configuration that needs to be set. */
+ host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
+
+ host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_32BIT_DMA_SIZE);
+
+ ret = sdhci_add_host(host);
+ if (ret) {
+ dev_err(dev, "sdhci_add_host() failed\n");
+ goto err_add_host;
+ }
+
+ return 0;
+
+ err_add_host:
+ release_resource(sc->ioarea);
+ kfree(sc->ioarea);
+
+ err_req_regs:
+ for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
+ clk_disable(sc->clk_bus[ptr]);
+ clk_put(sc->clk_bus[ptr]);
+ }
+
+ err_no_busclks:
+ clk_disable(sc->clk_io);
+ clk_put(sc->clk_io);
+
+ err_io_clk:
+ sdhci_free_host(host);
+
+ return ret;
+}
+
+static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int sdhci_s3c_suspend(struct platform_device *dev, pm_message_t pm)
+{
+ struct sdhci_host *host = platform_get_drvdata(dev);
+
+ sdhci_suspend_host(host, pm);
+ return 0;
+}
+
+static int sdhci_s3c_resume(struct platform_device *dev)
+{
+ struct sdhci_host *host = platform_get_drvdata(dev);
+
+ sdhci_resume_host(host);
+ return 0;
+}
+
+#else
+#define sdhci_s3c_suspend NULL
+#define sdhci_s3c_resume NULL
+#endif
+
+static struct platform_driver sdhci_s3c_driver = {
+ .probe = sdhci_s3c_probe,
+ .remove = __devexit_p(sdhci_s3c_remove),
+ .suspend = sdhci_s3c_suspend,
+ .resume = sdhci_s3c_resume,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "s3c-sdhci",
+ },
+};
+
+static int __init sdhci_s3c_init(void)
+{
+ return platform_driver_register(&sdhci_s3c_driver);
+}
+
+static void __exit sdhci_s3c_exit(void)
+{
+ platform_driver_unregister(&sdhci_s3c_driver);
+}
+
+module_init(sdhci_s3c_init);
+module_exit(sdhci_s3c_exit);
+
+MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
+MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c-sdhci");
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -45,8 +45,8 @@
#include <asm/io.h>
-#include <asm/plat-s3c/regs-nand.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/regs-nand.h>
+#include <plat/nand.h>
#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
static int hardware_ecc = 1;
@@ -231,8 +231,6 @@
BUG();
}
- dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
-
local_irq_save(flags);
cfg = readl(info->regs + S3C2410_NFCONF);
@@ -240,6 +238,8 @@
cfg |= set;
writel(cfg, info->regs + S3C2410_NFCONF);
+ dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
+
local_irq_restore(flags);
return 0;
@@ -438,7 +438,7 @@
if ((diff0 & ~(1<<fls(diff0))) == 0)
return 1;
- return -1;
+ return -EBADMSG;
}
/* ECC functions
@@ -530,7 +530,12 @@
static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
+ u8 *ptr = buf + (len & ~3);
+ int i;
+
readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
+ for (i = 0; i != (len & 3); i++)
+ ptr[i] = readb(info->regs + S3C2440_NFDATA);
}
static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
@@ -645,17 +650,31 @@
}
#ifdef CONFIG_MTD_PARTITIONS
+const char *part_probes[] = { "cmdlinepart", NULL };
static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
struct s3c2410_nand_mtd *mtd,
struct s3c2410_nand_set *set)
{
+ struct mtd_partition *part_info;
+ int nr_part = 0;
+
if (set == NULL)
return add_mtd_device(&mtd->mtd);
- if (set->nr_partitions > 0 && set->partitions != NULL) {
- return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
+ if (set->nr_partitions == 0) {
+ mtd->mtd.name = set->name;
+ nr_part = parse_mtd_partitions(&mtd->mtd, part_probes,
+ &part_info, 0);
+ } else {
+ if (set->nr_partitions > 0 && set->partitions != NULL) {
+ nr_part = set->nr_partitions;
+ part_info = set->partitions;
+ }
}
+ if (nr_part > 0 && part_info)
+ return add_mtd_partitions(&mtd->mtd, part_info, nr_part);
+
return add_mtd_device(&mtd->mtd);
}
#else
@@ -684,9 +703,13 @@
chip->select_chip = s3c2410_nand_select_chip;
chip->chip_delay = 50;
chip->priv = nmtd;
- chip->options = 0;
chip->controller = &info->controller;
+ if (set->flags & S3C2410_NAND_BBT)
+ chip->options = NAND_USE_FLASH_BBT;
+ else
+ chip->options = 0;
+
switch (info->cpu_type) {
case TYPE_S3C2410:
chip->IO_ADDR_W = regs + S3C2410_NFDATA;
@@ -726,7 +749,7 @@
nmtd->mtd.owner = THIS_MODULE;
nmtd->set = set;
- if (hardware_ecc) {
+ if (!info->platform->software_ecc && hardware_ecc) {
chip->ecc.calculate = s3c2410_nand_calculate_ecc;
chip->ecc.correct = s3c2410_nand_correct_data;
chip->ecc.mode = NAND_ECC_HW;
--- a/drivers/net/wireless/libertas/if_sdio.c
+++ b/drivers/net/wireless/libertas/if_sdio.c
@@ -48,6 +48,7 @@
static const struct sdio_device_id if_sdio_ids[] = {
{ SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_LIBERTAS) },
+ { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, SDIO_DEVICE_ID_MARVELL_88W8688) },
{ /* end: all zeroes */ },
};
@@ -72,7 +73,12 @@
.helper = "sd8686_helper.bin",
.firmware = "sd8686.bin",
},
-};
+ {
+ /* 8688 */
+ .model = 0x10,
+ .helper = "sd8688_helper.bin",
+ .firmware = "sd8688.bin",
+ },};
struct if_sdio_packet {
struct if_sdio_packet *next;
--- a/drivers/pnp/Kconfig
+++ b/drivers/pnp/Kconfig
@@ -5,7 +5,7 @@
menuconfig PNP
bool "Plug and Play support"
depends on HAS_IOMEM
- depends on ISA || ACPI
+ depends on ISA || ACPI || SDIO
---help---
Plug and Play (PnP) is a standard for peripherals which allows those
peripherals to be configured by software, e.g. assign IRQ's or other
--- a/drivers/pnp/resource.c
+++ b/drivers/pnp/resource.c
@@ -436,6 +436,7 @@
}
}
+#if 0
/* check if the resource is already in use, skip if the
* device is active because it itself may be in use */
if (!dev->active) {
@@ -443,6 +444,7 @@
return 0;
free_dma(*dma);
}
+#endif
/* check for conflicts with other pnp devices */
pnp_for_each_dev(tdev) {
--- /dev/null
+++ b/drivers/power/bq27000_battery.c
@@ -0,0 +1,463 @@
+/*
+ * Driver for batteries with bq27000 chips inside via HDQ
+ *
+ * Copyright 2008 Openmoko, Inc
+ * Andy Green <andy@openmoko.com>
+ *
+ * based on ds2760 driver, original copyright notice for that --->
+ *
+ * Copyright © 2007 Anton Vorontsov
+ * 2004-2007 Matt Reimer
+ * 2004 Szabolcs Gyurko
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * Author: Anton Vorontsov <cbou@mail.ru>
+ * February 2007
+ *
+ * Matt Reimer <mreimer@vpop.net>
+ * April 2004, 2005, 2007
+ *
+ * Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
+ * September 2004
+ */
+
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/jiffies.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include <linux/power_supply.h>
+#include <linux/bq27000_battery.h>
+
+enum bq27000_regs {
+ /* RAM regs */
+ /* read-write after this */
+ BQ27000_CTRL = 0, /* Device Control Register */
+ BQ27000_MODE, /* Device Mode Register */
+ BQ27000_AR_L, /* At-Rate H L */
+ BQ27000_AR_H,
+ /* read-only after this */
+ BQ27000_ARTTE_L, /* At-Rate Time To Empty H L */
+ BQ27000_ARTTE_H,
+ BQ27000_TEMP_L, /* Reported Temperature H L */
+ BQ27000_TEMP_H,
+ BQ27000_VOLT_L, /* Reported Voltage H L */
+ BQ27000_VOLT_H,
+ BQ27000_FLAGS, /* Status Flags */
+ BQ27000_RSOC, /* Relative State of Charge */
+ BQ27000_NAC_L, /* Nominal Available Capacity H L */
+ BQ27000_NAC_H,
+ BQ27000_CACD_L, /* Discharge Compensated H L */
+ BQ27000_CACD_H,
+ BQ27000_CACT_L, /* Temperature Compensated H L */
+ BQ27000_CACT_H,
+ BQ27000_LMD_L, /* Last measured discharge H L */
+ BQ27000_LMD_H,
+ BQ27000_AI_L, /* Average Current H L */
+ BQ27000_AI_H,
+ BQ27000_TTE_L, /* Time to Empty H L */
+ BQ27000_TTE_H,
+ BQ27000_TTF_L, /* Time to Full H L */
+ BQ27000_TTF_H,
+ BQ27000_SI_L, /* Standby Current H L */
+ BQ27000_SI_H,
+ BQ27000_STTE_L, /* Standby Time To Empty H L */
+ BQ27000_STTE_H,
+ BQ27000_MLI_L, /* Max Load Current H L */
+ BQ27000_MLI_H,
+ BQ27000_MLTTE_L, /* Max Load Time To Empty H L */
+ BQ27000_MLTTE_H,
+ BQ27000_SAE_L, /* Available Energy H L */
+ BQ27000_SAE_H,
+ BQ27000_AP_L, /* Available Power H L */
+ BQ27000_AP_H,
+ BQ27000_TTECP_L, /* Time to Empty at Constant Power H L */
+ BQ27000_TTECP_H,
+ BQ27000_CYCL_L, /* Cycle count since learning cycle H L */
+ BQ27000_CYCL_H,
+ BQ27000_CYCT_L, /* Cycle Count Total H L */
+ BQ27000_CYCT_H,
+ BQ27000_CSOC, /* Compensated State Of Charge */
+ /* EEPROM regs */
+ /* read-write after this */
+ BQ27000_EE_EE_EN = 0x6e, /* EEPROM Program Enable */
+ BQ27000_EE_ILMD = 0x76, /* Initial Last Measured Discharge High Byte */
+ BQ27000_EE_SEDVF, /* Scaled EDVF Threshold */
+ BQ27000_EE_SEDV1, /* Scaled EDV1 Threshold */
+ BQ27000_EE_ISLC, /* Initial Standby Load Current */
+ BQ27000_EE_DMFSD, /* Digital Magnitude Filter and Self Discharge */
+ BQ27000_EE_TAPER, /* Aging Estimate Enable, Charge Termination Taper */
+ BQ27000_EE_PKCFG, /* Pack Configuration Values */
+ BQ27000_EE_IMLC, /* Initial Max Load Current or ID #3 */
+ BQ27000_EE_DCOMP, /* Discharge rate compensation constants or ID #2 */
+ BQ27000_EE_TCOMP, /* Temperature Compensation constants or ID #1 */
+};
+
+enum bq27000_status_flags {
+ BQ27000_STATUS_CHGS = 0x80, /* 1 = being charged */
+ BQ27000_STATUS_NOACT = 0x40, /* 1 = no activity */
+ BQ27000_STATUS_IMIN = 0x20, /* 1 = Lion taper current mode */
+ BQ27000_STATUS_CI = 0x10, /* 1 = capacity likely innacurate */
+ BQ27000_STATUS_CALIP = 0x08, /* 1 = calibration in progress */
+ BQ27000_STATUS_VDQ = 0x04, /* 1 = capacity should be accurate */
+ BQ27000_STATUS_EDV1 = 0x02, /* 1 = end of discharge.. <6% left */
+ BQ27000_STATUS_EDVF = 0x01, /* 1 = no, it's really empty now */
+};
+
+#define NANOVOLTS_UNIT 3750
+
+struct bq27000_bat_regs {
+ int ai;
+ int flags;
+ int lmd;
+ int rsoc;
+ int temp;
+ int tte;
+ int ttf;
+ int volt;
+};
+
+struct bq27000_device_info {
+ struct device *dev;
+ struct power_supply bat;
+ struct delayed_work work;
+ struct bq27000_platform_data *pdata;
+
+ struct bq27000_bat_regs regs;
+};
+
+static unsigned int cache_time = 10000;
+module_param(cache_time, uint, 0644);
+MODULE_PARM_DESC(cache_time, "cache time in milliseconds");
+
+/*
+ * reading 16 bit values over HDQ has a special hazard where the
+ * hdq device firmware can update the 16-bit register during the time we
+ * read the two halves. TI document SLUS556D recommends the algorithm here
+ * to avoid trouble
+ */
+
+static int hdq_read16(struct bq27000_device_info *di, int address)
+{
+ int acc;
+ int high;
+ int retries = 3;
+
+ while (retries--) {
+
+ high = (di->pdata->hdq_read)(address + 1); /* high part */
+
+ if (high < 0)
+ return high;
+ acc = (di->pdata->hdq_read)(address);
+ if (acc < 0)
+ return acc;
+
+ /* confirm high didn't change between reading it and low */
+ if (high == (di->pdata->hdq_read)(address + 1))
+ return (high << 8) | acc;
+ }
+
+ return -ETIME;
+}
+
+static void bq27000_battery_external_power_changed(struct power_supply *psy)
+{
+ struct bq27000_device_info *di = container_of(psy, struct bq27000_device_info, bat);
+
+ power_supply_changed(&di->bat);
+ dev_dbg(di->dev, "%s\n", __FUNCTION__);
+}
+
+static int bq27000_battery_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ int n;
+ struct bq27000_device_info *di = container_of(psy, struct bq27000_device_info, bat);
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_STATUS:
+ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+
+ if (!di->pdata->get_charger_online_status)
+ goto use_bat;
+ if ((di->pdata->get_charger_online_status)()) {
+ /*
+ * charger is definitively present
+ * we report our state in terms of what it says it
+ * is doing
+ */
+ if (!di->pdata->get_charger_active_status)
+ goto use_bat;
+
+ if ((di->pdata->get_charger_active_status)()) {
+ val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ break;
+ }
+ val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+ break;
+ }
+
+ /*
+ * platform provided definite indication of charger presence,
+ * and it is telling us it isn't there... but we are on so we
+ * must be running from battery --->
+ */
+
+ val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+ break;
+
+use_bat:
+ /*
+ * either the charger is not connected, or the
+ * platform doesn't give info about charger, use battery state
+ * but... battery state can be out of date by 4 seconds or
+ * so... use the platform callbacks if possible.
+ */
+
+ /* no real activity on the battery */
+ if (di->regs.ai < 2) {
+ if (!di->regs.ttf)
+ val->intval = POWER_SUPPLY_STATUS_FULL;
+ else
+ val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING;
+ break;
+ }
+ /* power is actually going in or out... */
+ if (di->regs.flags < 0)
+ return di->regs.flags;
+ if (di->regs.flags & BQ27000_STATUS_CHGS)
+ val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ else
+ val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+ break;
+ case POWER_SUPPLY_PROP_HEALTH:
+ val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
+ /* Do we have accurate readings... */
+ if (di->regs.flags < 0)
+ return di->regs.flags;
+ if (di->regs.flags & BQ27000_STATUS_VDQ)
+ val->intval = POWER_SUPPLY_HEALTH_GOOD;
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+ if (di->regs.volt < 0)
+ return di->regs.volt;
+ /* mV -> uV */
+ val->intval = di->regs.volt * 1000;
+ break;
+ case POWER_SUPPLY_PROP_CURRENT_NOW:
+ if (di->regs.flags < 0)
+ return di->regs.flags;
+ if (di->regs.flags & BQ27000_STATUS_CHGS)
+ n = -NANOVOLTS_UNIT;
+ else
+ n = NANOVOLTS_UNIT;
+ if (di->regs.ai < 0)
+ return di->regs.ai;
+ val->intval = (di->regs.ai * n) / di->pdata->rsense_mohms;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_FULL:
+ if (di->regs.lmd < 0)
+ return di->regs.lmd;
+ val->intval = (di->regs.lmd * 3570) / di->pdata->rsense_mohms;
+ break;
+ case POWER_SUPPLY_PROP_TEMP:
+ if (di->regs.temp < 0)
+ return di->regs.temp;
+ /* K (in 0.25K units) is 273.15 up from C (in 0.1C)*/
+ /* 10926 = 27315 * 4 / 10 */
+ val->intval = (((long)di->regs.temp * 10l) - 10926) / 4;
+ break;
+ case POWER_SUPPLY_PROP_TECHNOLOGY:
+ val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+ break;
+ case POWER_SUPPLY_PROP_CAPACITY:
+ val->intval = di->regs.rsoc;
+ if (val->intval < 0)
+ return val->intval;
+ break;
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = !(di->regs.rsoc < 0);
+ break;
+ case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
+ if (di->regs.tte < 0)
+ return di->regs.tte;
+ val->intval = 60 * di->regs.tte;
+ break;
+ case POWER_SUPPLY_PROP_TIME_TO_FULL_NOW:
+ if (di->regs.ttf < 0)
+ return di->regs.ttf;
+ val->intval = 60 * di->regs.ttf;
+ break;
+ case POWER_SUPPLY_PROP_ONLINE:
+ if (di->pdata->get_charger_online_status)
+ val->intval = (di->pdata->get_charger_online_status)();
+ else
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void bq27000_battery_work(struct work_struct *work)
+{
+ struct bq27000_device_info *di =
+ container_of(work, struct bq27000_device_info, work.work);
+
+ if ((di->pdata->hdq_initialized)()) {
+ struct bq27000_bat_regs regs;
+
+ regs.ai = hdq_read16(di, BQ27000_AI_L);
+ regs.flags = (di->pdata->hdq_read)(BQ27000_FLAGS);
+ regs.lmd = hdq_read16(di, BQ27000_LMD_L);
+ regs.rsoc = (di->pdata->hdq_read)(BQ27000_RSOC);
+ regs.temp = hdq_read16(di, BQ27000_TEMP_L);
+ regs.tte = hdq_read16(di, BQ27000_TTE_L);
+ regs.ttf = hdq_read16(di, BQ27000_TTF_L);
+ regs.volt = hdq_read16(di, BQ27000_VOLT_L);
+
+ if (memcmp (&regs, &di->regs, sizeof(regs)) != 0) {
+ di->regs = regs;
+ power_supply_changed(&di->bat);
+ }
+ }
+
+ if (!schedule_delayed_work(&di->work, cache_time))
+ dev_err(di->dev, "battery service reschedule failed\n");
+}
+
+static enum power_supply_property bq27000_battery_props[] = {
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_HEALTH,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ POWER_SUPPLY_PROP_CURRENT_NOW,
+ POWER_SUPPLY_PROP_CHARGE_FULL,
+ POWER_SUPPLY_PROP_TEMP,
+ POWER_SUPPLY_PROP_TECHNOLOGY,
+ POWER_SUPPLY_PROP_PRESENT,
+ POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
+ POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
+ POWER_SUPPLY_PROP_CAPACITY,
+ POWER_SUPPLY_PROP_ONLINE
+};
+
+static int bq27000_battery_probe(struct platform_device *pdev)
+{
+ int retval = 0;
+ struct bq27000_device_info *di;
+ struct bq27000_platform_data *pdata;
+
+ dev_info(&pdev->dev, "BQ27000 Battery Driver (C) 2008 Openmoko, Inc\n");
+
+ di = kzalloc(sizeof(*di), GFP_KERNEL);
+ if (!di) {
+ retval = -ENOMEM;
+ goto di_alloc_failed;
+ }
+
+ platform_set_drvdata(pdev, di);
+
+ pdata = pdev->dev.platform_data;
+ di->dev = &pdev->dev;
+ /* di->w1_dev = pdev->dev.parent; */
+ di->bat.name = pdata->name;
+ di->bat.type = POWER_SUPPLY_TYPE_BATTERY;
+ di->bat.properties = bq27000_battery_props;
+ di->bat.num_properties = ARRAY_SIZE(bq27000_battery_props);
+ di->bat.get_property = bq27000_battery_get_property;
+ di->bat.external_power_changed =
+ bq27000_battery_external_power_changed;
+ di->bat.use_for_apm = 1;
+ di->pdata = pdata;
+
+ retval = power_supply_register(&pdev->dev, &di->bat);
+ if (retval) {
+ dev_err(di->dev, "failed to register battery\n");
+ goto batt_failed;
+ }
+
+ INIT_DELAYED_WORK(&di->work, bq27000_battery_work);
+
+ if (!schedule_delayed_work(&di->work, 0))
+ dev_err(di->dev, "failed to schedule bq27000_battery_work\n");
+
+ return 0;
+
+batt_failed:
+ kfree(di);
+di_alloc_failed:
+ return retval;
+}
+
+static int bq27000_battery_remove(struct platform_device *pdev)
+{
+ struct bq27000_device_info *di = platform_get_drvdata(pdev);
+
+ cancel_delayed_work(&di->work);
+
+ power_supply_unregister(&di->bat);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int bq27000_battery_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ struct bq27000_device_info *di = platform_get_drvdata(pdev);
+
+ cancel_delayed_work(&di->work);
+ return 0;
+}
+
+static int bq27000_battery_resume(struct platform_device *pdev)
+{
+ struct bq27000_device_info *di = platform_get_drvdata(pdev);
+
+ schedule_delayed_work(&di->work, 0);
+ return 0;
+}
+
+#else
+
+#define bq27000_battery_suspend NULL
+#define bq27000_battery_resume NULL
+
+#endif /* CONFIG_PM */
+
+static struct platform_driver bq27000_battery_driver = {
+ .driver = {
+ .name = "bq27000-battery",
+ },
+ .probe = bq27000_battery_probe,
+ .remove = bq27000_battery_remove,
+ .suspend = bq27000_battery_suspend,
+ .resume = bq27000_battery_resume,
+};
+
+static int __init bq27000_battery_init(void)
+{
+ return platform_driver_register(&bq27000_battery_driver);
+}
+
+static void __exit bq27000_battery_exit(void)
+{
+ platform_driver_unregister(&bq27000_battery_driver);
+}
+
+module_init(bq27000_battery_init);
+module_exit(bq27000_battery_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("bq27000 battery driver");
--- /dev/null
+++ b/drivers/power/gta02_hdq.c
@@ -0,0 +1,292 @@
+/*
+ * HDQ driver for the FIC Neo1973 GTA02 GSM phone
+ *
+ * (C) 2006-2007 by Openmoko, Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <mach/hardware.h>
+#include <linux/gta02_hdq.h>
+#include <asm/mach-types.h>
+#include <mach/gta02.h>
+#include <mach/fiq_ipc_gta02.h>
+
+
+
+#define HDQ_READ 0
+#define HDQ_WRITE 0x80
+
+static int fiq_busy(void)
+{
+ int request = (volatile u8)fiq_ipc.hdq_request_ctr;
+ int transact = (volatile u8)fiq_ipc.hdq_transaction_ctr;
+
+ return (request != transact);
+}
+
+int gta02hdq_initialized(void)
+{
+ return fiq_ipc.hdq_probed;
+}
+EXPORT_SYMBOL_GPL(gta02hdq_initialized);
+
+int gta02hdq_read(int address)
+{
+ int count_sleeps = 5;
+ int ret = -ETIME;
+
+ if (!fiq_ipc.hdq_probed)
+ return -EINVAL;
+
+ mutex_lock(&fiq_ipc.hdq_lock);
+
+ fiq_ipc.hdq_error = 0;
+ fiq_ipc.hdq_ads = address | HDQ_READ;
+ fiq_ipc.hdq_request_ctr++;
+ fiq_kick();
+ /*
+ * FIQ takes care of it while we block our calling process
+ * But we're not spinning -- other processes run normally while
+ * we wait for the result
+ */
+ while (count_sleeps--) {
+ msleep(10); /* valid transaction always completes in < 10ms */
+
+ if (fiq_busy())
+ continue;
+
+ if (fiq_ipc.hdq_error)
+ goto done; /* didn't see a response in good time */
+
+ ret = fiq_ipc.hdq_rx_data;
+ goto done;
+ }
+
+done:
+ mutex_unlock(&fiq_ipc.hdq_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(gta02hdq_read);
+
+int gta02hdq_write(int address, u8 data)
+{
+ int count_sleeps = 5;
+ int ret = -ETIME;
+
+ if (!fiq_ipc.hdq_probed)
+ return -EINVAL;
+
+ mutex_lock(&fiq_ipc.hdq_lock);
+
+ fiq_ipc.hdq_error = 0;
+ fiq_ipc.hdq_ads = address | HDQ_WRITE;
+ fiq_ipc.hdq_tx_data = data;
+ fiq_ipc.hdq_request_ctr++;
+ fiq_kick();
+ /*
+ * FIQ takes care of it while we block our calling process
+ * But we're not spinning -- other processes run normally while
+ * we wait for the result
+ */
+ while (count_sleeps--) {
+ msleep(10); /* valid transaction always completes in < 10ms */
+
+ if (fiq_busy())
+ continue; /* something bad with FIQ */
+
+ if (fiq_ipc.hdq_error)
+ goto done; /* didn't see a response in good time */
+
+ ret = 0;
+ goto done;
+ }
+
+done:
+ mutex_unlock(&fiq_ipc.hdq_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(gta02hdq_write);
+
+/* sysfs */
+
+static ssize_t hdq_sysfs_dump(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int n;
+ int v;
+ u8 u8a[128]; /* whole address space for HDQ */
+ char *end = buf;
+
+ if (!fiq_ipc.hdq_probed)
+ return -EINVAL;
+
+ /* the dump does not take care about 16 bit regs, because at this
+ * bus level we don't know about the chip details
+ */
+ for (n = 0; n < sizeof(u8a); n++) {
+ v = gta02hdq_read(n);
+ if (v < 0)
+ goto bail;
+ u8a[n] = v;
+ }
+
+ for (n = 0; n < sizeof(u8a); n += 16) {
+ hex_dump_to_buffer(u8a + n, sizeof(u8a), 16, 1, end, 4096, 0);
+ end += strlen(end);
+ *end++ = '\n';
+ *end = '\0';
+ }
+ return (end - buf);
+
+bail:
+ return sprintf(buf, "ERROR %d\n", v);
+}
+
+/* you write by <address> <data>, eg, "34 128" */
+
+#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
+
+static ssize_t hdq_sysfs_write(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ const char *end = buf + count;
+ int address = atoi(buf);
+
+ if (!fiq_ipc.hdq_probed)
+ return -EINVAL;
+
+ while ((buf != end) && (*buf != ' '))
+ buf++;
+ if (buf >= end)
+ return 0;
+ while ((buf < end) && (*buf == ' '))
+ buf++;
+ if (buf >= end)
+ return 0;
+
+ gta02hdq_write(address, atoi(buf));
+
+ return count;
+}
+
+static DEVICE_ATTR(dump, 0400, hdq_sysfs_dump, NULL);
+static DEVICE_ATTR(write, 0600, NULL, hdq_sysfs_write);
+
+static struct attribute *gta02hdq_sysfs_entries[] = {
+ &dev_attr_dump.attr,
+ &dev_attr_write.attr,
+ NULL
+};
+
+static struct attribute_group gta02hdq_attr_group = {
+ .name = "hdq",
+ .attrs = gta02hdq_sysfs_entries,
+};
+
+
+#ifdef CONFIG_PM
+static int gta02hdq_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ /* after 18s of this, the battery monitor will also go to sleep */
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 0);
+ s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
+ return 0;
+}
+
+static int gta02hdq_resume(struct platform_device *pdev)
+{
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
+ s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
+ return 0;
+}
+#endif
+
+static int __init gta02hdq_probe(struct platform_device *pdev)
+{
+ struct resource *r = platform_get_resource(pdev, 0, 0);
+ int ret;
+ struct gta02_hdq_platform_data *pdata = pdev->dev.platform_data;
+
+ if (!machine_is_neo1973_gta02())
+ return -EIO;
+
+ if (!r)
+ return -EINVAL;
+
+ if (!fiq_ready) {
+ printk(KERN_ERR "hdq probe fails on fiq not ready\n");
+ return -EINVAL;
+ }
+
+ platform_set_drvdata(pdev, NULL);
+
+ mutex_init(&fiq_ipc.hdq_lock);
+
+ /* set our HDQ comms pin from the platform data */
+ fiq_ipc.hdq_gpio_pin = r->start;
+
+ s3c2410_gpio_setpin(fiq_ipc.hdq_gpio_pin, 1);
+ s3c2410_gpio_cfgpin(fiq_ipc.hdq_gpio_pin, S3C2410_GPIO_OUTPUT);
+
+ ret = sysfs_create_group(&pdev->dev.kobj, &gta02hdq_attr_group);
+ if (ret)
+ return ret;
+
+ fiq_ipc.hdq_probed = 1; /* we are ready to do stuff now */
+
+ /*
+ * if wanted, users can defer registration of devices
+ * that depend on HDQ until after we register, and can use our
+ * device as parent so suspend-resume ordering is correct
+ */
+ if (pdata->attach_child_devices)
+ (pdata->attach_child_devices)(&pdev->dev);
+
+ return 0;
+}
+
+static int gta02hdq_remove(struct platform_device *pdev)
+{
+ sysfs_remove_group(&pdev->dev.kobj, &gta02hdq_attr_group);
+ return 0;
+}
+
+static struct platform_driver gta02hdq_driver = {
+ .probe = gta02hdq_probe,
+ .remove = gta02hdq_remove,
+#ifdef CONFIG_PM
+ .suspend = gta02hdq_suspend,
+ .resume = gta02hdq_resume,
+#endif
+ .driver = {
+ .name = "gta02-hdq",
+ },
+};
+
+static int __init gta02hdq_init(void)
+{
+ return platform_driver_register(&gta02hdq_driver);
+}
+
+static void __exit gta02hdq_exit(void)
+{
+ platform_driver_unregister(&gta02hdq_driver);
+}
+
+module_init(gta02hdq_init);
+module_exit(gta02hdq_exit);
+
+MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
+MODULE_DESCRIPTION("GTA02 HDQ driver");
+MODULE_LICENSE("GPL");
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -68,4 +68,24 @@
help
Say Y here to enable support for batteries with BQ27200(I2C) chip.
+config BATTERY_BQ27000_HDQ
+ tristate "BQ27000 HDQ battery monitor driver"
+ help
+ Say Y to enable support for the battery on the Neo Freerunner
+
+config GTA02_HDQ
+ tristate "Neo Freerunner HDQ"
+ depends on MACH_NEO1973_GTA02 && FIQ && S3C2440_C_FIQ
+ help
+ Say Y to enable support for communicating with an HDQ battery
+ on the Neo Freerunner. You probably want to select
+ at least BATTERY_BQ27000_HDQ as well
+
+config CHARGER_PCF50633
+ tristate "Support for NXP PCF50633 MBC"
+ depends on MFD_PCF50633
+ help
+ Say Y to include support for NXP PCF50633 Main Battery Charger.
+
endif # POWER_SUPPLY
+
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -23,3 +23,9 @@
obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o
obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o
obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o
+obj-$(CONFIG_BATTERY_PALMTX) += palmtx_battery.o
+obj-$(CONFIG_BATTERY_BQ27000_HDQ) += bq27000_battery.o
+
+obj-$(CONFIG_GTA02_HDQ) += gta02_hdq.o
+
+obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o
--- /dev/null
+++ b/drivers/power/pcf50633-charger.c
@@ -0,0 +1,415 @@
+/* Philips PCF50633 Main Battery Charger Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50633 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/mbc.h>
+
+void pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma)
+{
+ int ret;
+ u8 bits;
+ int charging_start = 1;
+ u8 mbcs2, chgmod;
+
+ if (ma >= 1000)
+ bits = PCF50633_MBCC7_USB_1000mA;
+ else if (ma >= 500)
+ bits = PCF50633_MBCC7_USB_500mA;
+ else if (ma >= 100)
+ bits = PCF50633_MBCC7_USB_100mA;
+ else {
+ bits = PCF50633_MBCC7_USB_SUSPEND;
+ charging_start = 0;
+ }
+
+ ret = pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC7,
+ PCF50633_MBCC7_USB_MASK, bits);
+ if (ret)
+ dev_err(pcf->dev, "error setting usb curlim to %d mA\n", ma);
+ else
+ dev_info(pcf->dev, "usb curlim to %d mA\n", ma);
+
+ mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
+ chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
+
+ /* If chgmod == BATFULL, setting chgena has no effect.
+ * We need to set resume instead.
+ */
+ if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_CHGENA, PCF50633_MBCC1_CHGENA);
+ else
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_RESUME, PCF50633_MBCC1_RESUME);
+
+ pcf->mbc.usb_active = charging_start;
+ power_supply_changed(&pcf->mbc.usb);
+}
+EXPORT_SYMBOL_GPL(pcf50633_mbc_usb_curlim_set);
+
+static const char *chgmode_names[] = {
+ [PCF50633_MBCS2_MBC_PLAY] = "play-only",
+ [PCF50633_MBCS2_MBC_USB_PRE] = "pre",
+ [PCF50633_MBCS2_MBC_ADP_PRE] = "pre",
+ [PCF50633_MBCS2_MBC_USB_PRE_WAIT] = "pre-wait",
+ [PCF50633_MBCS2_MBC_ADP_PRE_WAIT] = "pre-wait",
+ [PCF50633_MBCS2_MBC_USB_FAST] = "fast",
+ [PCF50633_MBCS2_MBC_ADP_FAST] = "fast",
+ [PCF50633_MBCS2_MBC_USB_FAST_WAIT] = "fast-wait",
+ [PCF50633_MBCS2_MBC_ADP_FAST_WAIT] = "fast-wait",
+ [PCF50633_MBCS2_MBC_BAT_FULL] = "bat-full",
+};
+
+static ssize_t show_chgmode(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct pcf50633 *pcf = dev_get_drvdata(dev);
+
+ u8 mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
+ u8 chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
+
+ return sprintf(buf, "%s %d\n", chgmode_names[chgmod], chgmod);
+}
+static DEVICE_ATTR(chgmode, S_IRUGO | S_IWUSR, show_chgmode, NULL);
+
+static ssize_t show_usblim(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct pcf50633 *pcf = dev_get_drvdata(dev);
+ u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
+ PCF50633_MBCC7_USB_MASK;
+ unsigned int ma;
+
+ if (usblim == PCF50633_MBCC7_USB_1000mA)
+ ma = 1000;
+ else if (usblim == PCF50633_MBCC7_USB_500mA)
+ ma = 500;
+ else if (usblim == PCF50633_MBCC7_USB_100mA)
+ ma = 100;
+ else
+ ma = 0;
+
+ return sprintf(buf, "%u\n", ma);
+}
+static DEVICE_ATTR(usb_curlim, S_IRUGO | S_IWUSR, show_usblim, NULL);
+
+static ssize_t force_usb_limit_dangerous(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct pcf50633 *pcf = dev_get_drvdata(dev);
+ unsigned long ma;
+
+ strict_strtoul(buf, 10, &ma);
+
+ pcf50633_mbc_usb_curlim_set(pcf, ma);
+
+ return count;
+}
+
+static DEVICE_ATTR(force_usb_limit_dangerous, 0600,
+ NULL, force_usb_limit_dangerous);
+
+static struct attribute *mbc_sysfs_entries[] = {
+ &dev_attr_chgmode.attr,
+ &dev_attr_usb_curlim.attr,
+ &dev_attr_force_usb_limit_dangerous.attr,
+ NULL,
+};
+
+static struct attribute_group mbc_attr_group = {
+ .name = NULL, /* put in device directory */
+ .attrs = mbc_sysfs_entries,
+};
+
+/* MBC state machine switches into charging mode when the battery voltage
+ * falls below 96% of a battery float voltage. But the voltage drop in Li-ion
+ * batteries is marginal(1~2 %) till about 80% of its capacity - which means,
+ * after a BATFULL, charging won't be restarted until 80%.
+ *
+ * This work_struct function restarts charging every
+ * CHARGING_RESTART_TIMEOUT seconds and makes sure we don't discharge too much
+ */
+
+#define CHARGING_RESTART_TIMEOUT (900 * HZ) /* 15 minutes */
+
+static void pcf50633_mbc_charging_restart(struct work_struct *work)
+{
+ struct pcf50633_mbc *mbc;
+ struct pcf50633 *pcf;
+ u8 mbcs2, chgmod;
+
+ mbc = container_of(work, struct pcf50633_mbc,
+ charging_restart_work.work);
+ pcf = container_of(mbc, struct pcf50633, mbc);
+
+ mbcs2 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2);
+ chgmod = (mbcs2 & PCF50633_MBCS2_MBC_MASK);
+
+ if (chgmod != PCF50633_MBCS2_MBC_BAT_FULL)
+ return;
+
+ /* Restart charging */
+ pcf50633_reg_set_bit_mask(pcf, PCF50633_REG_MBCC1, PCF50633_MBCC1_RESUME,
+ PCF50633_MBCC1_RESUME);
+ mbc->usb_active = 1;
+ power_supply_changed(&mbc->usb);
+
+ dev_info(pcf->dev, "Charging restarted..\n");
+}
+
+static void pcf50633_mbc_irq_handler(struct pcf50633 *pcf, int irq, void *data)
+{
+ struct pcf50633_mbc *mbc;
+
+ mbc = &pcf->mbc;
+
+ /* USB */
+ if (irq == PCF50633_IRQ_USBINS)
+ mbc->usb_online = 1;
+ else if (irq == PCF50633_IRQ_USBREM) {
+ mbc->usb_online = 0;
+ mbc->usb_active = 0;
+ pcf50633_mbc_usb_curlim_set(pcf, 0);
+ cancel_delayed_work_sync(&mbc->charging_restart_work);
+ }
+
+ /* Adapter */
+ if (irq == PCF50633_IRQ_ADPINS) {
+ pcf->mbc.adapter_online = 1;
+ pcf->mbc.adapter_active = 1;
+ } else if (irq == PCF50633_IRQ_ADPREM) {
+ mbc->adapter_online = 0;
+ mbc->adapter_active = 0;
+ }
+
+ if (irq == PCF50633_IRQ_BATFULL) {
+ mbc->usb_active = 0;
+ mbc->adapter_active = 0;
+ schedule_delayed_work(&mbc->charging_restart_work,
+ CHARGING_RESTART_TIMEOUT);
+ } else if (irq == PCF50633_IRQ_USBLIMON)
+ mbc->usb_active = 0;
+ else if (irq == PCF50633_IRQ_USBLIMOFF)
+ mbc->usb_active = 1;
+
+ power_supply_changed(&mbc->ac);
+ power_supply_changed(&mbc->usb);
+ power_supply_changed(&mbc->adapter);
+
+ if (pcf->pdata->mbc_event_callback)
+ pcf->pdata->mbc_event_callback(pcf, irq);
+}
+
+static int adapter_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ int ret = 0;
+ struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb);
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_ONLINE:
+ val->intval = mbc->adapter_online;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int usb_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ int ret = 0;
+ struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, usb);
+ struct pcf50633 *pcf = container_of(mbc, struct pcf50633, mbc);
+
+ u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
+ PCF50633_MBCC7_USB_MASK;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_ONLINE:
+ val->intval = mbc->usb_online && (usblim == PCF50633_MBCC7_USB_500mA);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int ac_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ int ret = 0;
+ struct pcf50633_mbc *mbc = container_of(psy, struct pcf50633_mbc, ac);
+ struct pcf50633 *pcf = container_of(mbc, struct pcf50633, mbc);
+
+ u8 usblim = pcf50633_reg_read(pcf, PCF50633_REG_MBCC7) &
+ PCF50633_MBCC7_USB_MASK;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_ONLINE:
+ val->intval = mbc->usb_online && (usblim == PCF50633_MBCC7_USB_1000mA);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static enum power_supply_property power_props[] = {
+ POWER_SUPPLY_PROP_ONLINE,
+};
+
+int __init pcf50633_mbc_probe(struct platform_device *pdev)
+{
+ struct pcf50633 *pcf;
+ struct pcf50633_mbc *mbc;
+ int ret;
+ u8 mbcs1;
+
+ pcf = platform_get_drvdata(pdev);
+ mbc = &pcf->mbc;
+
+ /* Set up IRQ handlers */
+ pcf->irq_handler[PCF50633_IRQ_ADPINS].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_ADPREM].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_USBINS].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_USBREM].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_BATFULL].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_CHGHALT].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_THLIMON].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_THLIMOFF].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_USBLIMON].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_USBLIMOFF].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_LOWSYS].handler =
+ pcf50633_mbc_irq_handler;
+ pcf->irq_handler[PCF50633_IRQ_LOWBAT].handler =
+ pcf50633_mbc_irq_handler;
+
+ /* Create power supplies */
+
+ mbc->adapter.name = "adapter";
+ mbc->adapter.type = POWER_SUPPLY_TYPE_MAINS;
+ mbc->adapter.properties = power_props;
+ mbc->adapter.num_properties = ARRAY_SIZE(power_props);
+ mbc->adapter.get_property = &adapter_get_property;
+ mbc->adapter.supplied_to = pcf->pdata->batteries;
+ mbc->adapter.num_supplicants = pcf->pdata->num_batteries;
+
+ mbc->usb.name = "usb";
+ mbc->usb.type = POWER_SUPPLY_TYPE_USB;
+ mbc->usb.properties = power_props;
+ mbc->usb.num_properties = ARRAY_SIZE(power_props);
+ mbc->usb.get_property = usb_get_property;
+ mbc->usb.supplied_to = pcf->pdata->batteries;
+ mbc->usb.num_supplicants = pcf->pdata->num_batteries;
+
+ mbc->ac.name = "ac";
+ mbc->ac.type = POWER_SUPPLY_TYPE_MAINS;
+ mbc->ac.properties = power_props;
+ mbc->ac.num_properties = ARRAY_SIZE(power_props);
+ mbc->ac.get_property = ac_get_property;
+ mbc->ac.supplied_to = pcf->pdata->batteries;
+ mbc->ac.num_supplicants = pcf->pdata->num_batteries;
+
+ INIT_DELAYED_WORK(&mbc->charging_restart_work,
+ pcf50633_mbc_charging_restart);
+
+ ret = power_supply_register(&pdev->dev, &mbc->adapter);
+ if (ret)
+ dev_err(pcf->dev, "failed to register adapter\n");
+
+ ret = power_supply_register(&pdev->dev, &mbc->usb);
+ if (ret)
+ dev_err(pcf->dev, "failed to register usb\n");
+
+ ret = power_supply_register(&pdev->dev, &mbc->ac);
+ if (ret)
+ dev_err(pcf->dev, "failed to register ac\n");
+
+ mbcs1 = pcf50633_reg_read(pcf, PCF50633_REG_MBCS1);
+ if (mbcs1 & 0x01)
+ pcf50633_mbc_irq_handler(pcf, PCF50633_IRQ_USBINS, NULL);
+ if (mbcs1 & 0x04)
+ pcf50633_mbc_irq_handler(pcf, PCF50633_IRQ_ADPINS, NULL);
+
+ /* Disable automatic charging restart. Manually setting RESUME
+ * won't have effect otherwise
+ */
+ pcf50633_reg_clear_bits(pcf, PCF50633_REG_MBCC1,
+ PCF50633_MBCC1_AUTORES);
+
+ return sysfs_create_group(&pdev->dev.kobj, &mbc_attr_group);
+}
+
+static int __devexit pcf50633_mbc_remove(struct platform_device *pdev)
+{
+ struct pcf50633 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+
+ return 0;
+}
+
+struct platform_driver pcf50633_mbc_driver = {
+ .driver = {
+ .name = "pcf50633-mbc",
+ },
+ .probe = pcf50633_mbc_probe,
+ .remove = __devexit_p(pcf50633_mbc_remove),
+};
+
+static int __init pcf50633_mbc_init(void)
+{
+ return platform_driver_register(&pcf50633_mbc_driver);
+}
+module_init(pcf50633_mbc_init);
+
+static void __exit pcf50633_mbc_exit(void)
+{
+ platform_driver_unregister(&pcf50633_mbc_driver);
+}
+module_exit(pcf50633_mbc_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50633 mbc driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50633-mbc");
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1113,6 +1113,7 @@
if (!regulator->enabled) {
printk(KERN_ERR "%s: not in use by this consumer\n",
__func__);
+ WARN_ON(1);
return 0;
}
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -73,4 +73,10 @@
Say y here to support the BUCKs and LDOs regulators found on
Dialog Semiconductor DA9030/DA9034 PMIC.
+config REGULATOR_PCF50633
+ bool "PCF50633 regulator driver"
+ depends on MFD_PCF50633
+ help
+ Say Y here to support the voltage regulators and convertors
+ on PCF50633
endif
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -11,5 +11,6 @@
obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
obj-$(CONFIG_REGULATOR_DA903X) += da903x.o
+obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
--- /dev/null
+++ b/drivers/regulator/pcf50633-regulator.c
@@ -0,0 +1,330 @@
+/* Philips PCF50633 PMIC Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50633 driver mainly by
+ * Harald Welte and Andy Green
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/regulator/driver.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/pmic.h>
+
+#define PCF50633_REGULATOR(_name, _id) \
+ { \
+ .name = _name, \
+ .id = _id, \
+ .ops = &pcf50633_regulator_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }
+static const u8 pcf50633_regulator_registers[PCF50633_NUM_REGULATORS] = {
+ [PCF50633_REGULATOR_AUTO] = PCF50633_REG_AUTOOUT,
+ [PCF50633_REGULATOR_DOWN1] = PCF50633_REG_DOWN1OUT,
+ [PCF50633_REGULATOR_DOWN2] = PCF50633_REG_DOWN2OUT,
+ [PCF50633_REGULATOR_MEMLDO] = PCF50633_REG_MEMLDOOUT,
+ [PCF50633_REGULATOR_LDO1] = PCF50633_REG_LDO1OUT,
+ [PCF50633_REGULATOR_LDO2] = PCF50633_REG_LDO2OUT,
+ [PCF50633_REGULATOR_LDO3] = PCF50633_REG_LDO3OUT,
+ [PCF50633_REGULATOR_LDO4] = PCF50633_REG_LDO4OUT,
+ [PCF50633_REGULATOR_LDO5] = PCF50633_REG_LDO5OUT,
+ [PCF50633_REGULATOR_LDO6] = PCF50633_REG_LDO6OUT,
+ [PCF50633_REGULATOR_HCLDO] = PCF50633_REG_HCLDOOUT,
+};
+
+/* Bits from voltage value */
+static u_int8_t auto_voltage_bits(unsigned int millivolts)
+{
+ if (millivolts < 1800)
+ return 0;
+ if (millivolts > 3800)
+ return 0xff;
+
+ millivolts -= 625;
+ return millivolts/25;
+}
+
+static u_int8_t down_voltage_bits(unsigned int millivolts)
+{
+ if (millivolts < 625)
+ return 0;
+ else if (millivolts > 3000)
+ return 0xff;
+
+ millivolts -= 625;
+ return millivolts/25;
+}
+
+static u_int8_t ldo_voltage_bits(unsigned int millivolts)
+{
+ if (millivolts < 900)
+ return 0;
+ else if (millivolts > 3600)
+ return 0x1f;
+
+ millivolts -= 900;
+ return millivolts/100;
+}
+
+/* Obtain voltage value from bits */
+
+static unsigned int auto_voltage_value(uint8_t bits)
+{
+ if (bits < 0x2f)
+ return 0;
+ return 625 + (bits * 25);
+}
+
+
+static unsigned int down_voltage_value(uint8_t bits)
+{
+ return 625 + (bits*25);
+}
+
+
+static unsigned int ldo_voltage_value(uint8_t bits)
+{
+ bits &= 0x1f;
+ return 900 + (bits * 100);
+}
+
+static int pcf50633_regulator_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV)
+{
+ uint8_t volt_bits;
+ uint8_t regnr;
+ int regulator_id;
+ int millivolts;
+ struct pcf50633 *pcf = rdev_get_drvdata(rdev);;
+
+ regulator_id = rdev_get_id(rdev);
+
+ if (regulator_id >= PCF50633_NUM_REGULATORS)
+ return -EINVAL;
+
+ millivolts = min_uV / 1000;
+
+ regnr = pcf50633_regulator_registers[regulator_id];
+
+ switch (regulator_id) {
+ case PCF50633_REGULATOR_AUTO:
+ volt_bits = auto_voltage_bits(millivolts);
+ break;
+ case PCF50633_REGULATOR_DOWN1:
+ volt_bits = down_voltage_bits(millivolts);
+ break;
+ case PCF50633_REGULATOR_DOWN2:
+ volt_bits = down_voltage_bits(millivolts);
+ break;
+ case PCF50633_REGULATOR_LDO1:
+ case PCF50633_REGULATOR_LDO2:
+ case PCF50633_REGULATOR_LDO3:
+ case PCF50633_REGULATOR_LDO4:
+ case PCF50633_REGULATOR_LDO5:
+ case PCF50633_REGULATOR_LDO6:
+ case PCF50633_REGULATOR_HCLDO:
+ volt_bits = ldo_voltage_bits(millivolts);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return pcf50633_reg_write(pcf, regnr, volt_bits);
+}
+
+static int pcf50633_regulator_get_voltage(struct regulator_dev *rdev)
+{
+ uint8_t volt_bits;
+ uint8_t regnr;
+ unsigned int rc = 0;
+ int regulator_id = rdev_get_id(rdev);
+ struct pcf50633 *pcf = rdev_get_drvdata(rdev);
+
+ if (regulator_id >= PCF50633_NUM_REGULATORS)
+ return -EINVAL;
+
+ regnr = pcf50633_regulator_registers[regulator_id];
+ volt_bits = pcf50633_reg_read(pcf, regnr);
+
+ switch (regulator_id) {
+ case PCF50633_REGULATOR_AUTO:
+ rc = auto_voltage_value(volt_bits);
+ break;
+ case PCF50633_REGULATOR_DOWN1:
+ rc = down_voltage_value(volt_bits);
+ break;
+ case PCF50633_REGULATOR_DOWN2:
+ rc = down_voltage_value(volt_bits);
+ break;
+ case PCF50633_REGULATOR_LDO1:
+ case PCF50633_REGULATOR_LDO2:
+ case PCF50633_REGULATOR_LDO3:
+ case PCF50633_REGULATOR_LDO4:
+ case PCF50633_REGULATOR_LDO5:
+ case PCF50633_REGULATOR_LDO6:
+ case PCF50633_REGULATOR_HCLDO:
+ rc = ldo_voltage_value(volt_bits);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rc * 1000;
+}
+
+static int pcf50633_regulator_enable(struct regulator_dev *rdev)
+{
+ uint8_t regnr;
+ int regulator_id = rdev_get_id(rdev);
+ struct pcf50633 *pcf = rdev_get_drvdata(rdev);
+
+ if (regulator_id >= PCF50633_NUM_REGULATORS)
+ return -EINVAL;
+
+ /* the *ENA register is always one after the *OUT register */
+ regnr = pcf50633_regulator_registers[regulator_id] + 1;
+
+ pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON,
+ PCF50633_REGULATOR_ON);
+
+ return 0;
+}
+
+static int pcf50633_regulator_disable(struct regulator_dev *rdev)
+{
+ uint8_t regnr;
+ int regulator_id = rdev_get_id(rdev);
+ struct pcf50633 *pcf = rdev_get_drvdata(rdev);
+
+ if (regulator_id >= PCF50633_NUM_REGULATORS)
+ return -EINVAL;
+
+ /* the *ENA register is always one after the *OUT register */
+ regnr = pcf50633_regulator_registers[regulator_id] + 1;
+
+ pcf50633_reg_set_bit_mask(pcf, regnr, PCF50633_REGULATOR_ON, 0);
+
+ return 0;
+}
+
+static int pcf50633_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ uint8_t val, regnr;
+ int regulator_id = rdev_get_id(rdev);
+ struct pcf50633 *pcf = rdev_get_drvdata(rdev);
+
+ if (regulator_id >= PCF50633_NUM_REGULATORS)
+ return -EINVAL;
+
+ /* the *ENA register is always one after the *OUT register */
+ regnr = pcf50633_regulator_registers[regulator_id] + 1;
+ val = pcf50633_reg_read(pcf, regnr) & PCF50633_REGULATOR_ON;
+
+ return val;
+}
+
+struct regulator_ops pcf50633_regulator_ops = {
+ .set_voltage = pcf50633_regulator_set_voltage,
+ .get_voltage = pcf50633_regulator_get_voltage,
+ .enable = pcf50633_regulator_enable,
+ .disable = pcf50633_regulator_disable,
+ .is_enabled = pcf50633_regulator_is_enabled,
+ .set_suspend_enable = pcf50633_regulator_enable,
+ .set_suspend_disable = pcf50633_regulator_disable,
+};
+
+static struct regulator_desc regulators[] = {
+ [PCF50633_REGULATOR_AUTO] =
+ PCF50633_REGULATOR("auto", PCF50633_REGULATOR_AUTO),
+ [PCF50633_REGULATOR_DOWN1] =
+ PCF50633_REGULATOR("down1", PCF50633_REGULATOR_DOWN1),
+ [PCF50633_REGULATOR_DOWN2] =
+ PCF50633_REGULATOR("down2", PCF50633_REGULATOR_DOWN2),
+ [PCF50633_REGULATOR_LDO1] =
+ PCF50633_REGULATOR("ldo1", PCF50633_REGULATOR_LDO1),
+ [PCF50633_REGULATOR_LDO2] =
+ PCF50633_REGULATOR("ldo2", PCF50633_REGULATOR_LDO2),
+ [PCF50633_REGULATOR_LDO3] =
+ PCF50633_REGULATOR("ldo3", PCF50633_REGULATOR_LDO3),
+ [PCF50633_REGULATOR_LDO4] =
+ PCF50633_REGULATOR("ldo4", PCF50633_REGULATOR_LDO4),
+ [PCF50633_REGULATOR_LDO5] =
+ PCF50633_REGULATOR("ldo5", PCF50633_REGULATOR_LDO5),
+ [PCF50633_REGULATOR_LDO6] =
+ PCF50633_REGULATOR("ldo6", PCF50633_REGULATOR_LDO6),
+ [PCF50633_REGULATOR_HCLDO] =
+ PCF50633_REGULATOR("hcldo", PCF50633_REGULATOR_HCLDO),
+ [PCF50633_REGULATOR_MEMLDO] =
+ PCF50633_REGULATOR("memldo", PCF50633_REGULATOR_MEMLDO),
+};
+
+int __init pcf50633_regulator_probe(struct platform_device *pdev)
+{
+ struct regulator_dev *rdev;
+ struct pcf50633 *pcf;
+
+ pcf = pdev->dev.driver_data;
+
+ rdev = regulator_register(&regulators[pdev->id], &pdev->dev, pcf);
+ if (IS_ERR(rdev))
+ return PTR_ERR(rdev);
+
+ if (pcf->pdata->regulator_registered)
+ pcf->pdata->regulator_registered(pcf, pdev->id);
+
+ return 0;
+}
+
+static int __devexit pcf50633_regulator_remove(struct platform_device *pdev)
+{
+ struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+ regulator_unregister(rdev);
+
+ return 0;
+}
+
+struct platform_driver pcf50633_regulator_driver = {
+ .driver = {
+ .name = "pcf50633-regltr",
+ },
+ .probe = pcf50633_regulator_probe,
+ .remove = __devexit_p(pcf50633_regulator_remove),
+};
+
+static int __init pcf50633_regulator_init(void)
+{
+ return platform_driver_register(&pcf50633_regulator_driver);
+}
+module_init(pcf50633_regulator_init);
+
+static void __exit pcf50633_regulator_exit(void)
+{
+ platform_driver_unregister(&pcf50633_regulator_driver);
+}
+module_exit(pcf50633_regulator_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50633 regulator driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50633-regulator");
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -219,6 +219,18 @@
This driver can also be built as a module. If so, the module
will be called rtc-pcf8583.
+config RTC_DRV_PCF50633
+ tristate "Philips PCF50633"
+ help
+ If you say yes here you get support for the Philips PCF50633
+ PMU's RTC.
+
+config RTC_DRV_PCF50606
+ tristate "Philips PCF50606"
+ help
+ If you say yes here you get support for the Philips PCF50606
+ PMU's RTC.
+
config RTC_DRV_M41T80
tristate "ST M41T65/M41T80/81/82/83/84/85/87"
help
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -50,6 +50,8 @@
obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o
obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o
obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o
+obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
+obj-$(CONFIG_RTC_DRV_PCF50606) += rtc-pcf50606.o
obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o
obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
obj-$(CONFIG_RTC_DRV_PARISC) += rtc-parisc.o
--- /dev/null
+++ b/drivers/rtc/rtc-pcf50606.c
@@ -0,0 +1,300 @@
+/* Philips PCF50606 RTC Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50606 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 060, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+#include <linux/bcd.h>
+
+#include <linux/mfd/pcf50606/core.h>
+#include <linux/mfd/pcf50606/rtc.h>
+
+enum pcf50606_time_indexes {
+ PCF50606_TI_SEC = 0,
+ PCF50606_TI_MIN,
+ PCF50606_TI_HOUR,
+ PCF50606_TI_WKDAY,
+ PCF50606_TI_DAY,
+ PCF50606_TI_MONTH,
+ PCF50606_TI_YEAR,
+ PCF50606_TI_EXTENT /* always last */
+};
+
+
+struct pcf50606_time {
+ u_int8_t time[PCF50606_TI_EXTENT];
+};
+
+static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50606_time *pcf)
+{
+ rtc->tm_sec = bcd2bin(pcf->time[PCF50606_TI_SEC]);
+ rtc->tm_min = bcd2bin(pcf->time[PCF50606_TI_MIN]);
+ rtc->tm_hour = bcd2bin(pcf->time[PCF50606_TI_HOUR]);
+ rtc->tm_wday = bcd2bin(pcf->time[PCF50606_TI_WKDAY]);
+ rtc->tm_mday = bcd2bin(pcf->time[PCF50606_TI_DAY]);
+ rtc->tm_mon = bcd2bin(pcf->time[PCF50606_TI_MONTH]);
+ rtc->tm_year = bcd2bin(pcf->time[PCF50606_TI_YEAR]) + 100;
+}
+
+static void rtc2pcf_time(struct pcf50606_time *pcf, struct rtc_time *rtc)
+{
+ pcf->time[PCF50606_TI_SEC] = bin2bcd(rtc->tm_sec);
+ pcf->time[PCF50606_TI_MIN] = bin2bcd(rtc->tm_min);
+ pcf->time[PCF50606_TI_HOUR] = bin2bcd(rtc->tm_hour);
+ pcf->time[PCF50606_TI_WKDAY] = bin2bcd(rtc->tm_wday);
+ pcf->time[PCF50606_TI_DAY] = bin2bcd(rtc->tm_mday);
+ pcf->time[PCF50606_TI_MONTH] = bin2bcd(rtc->tm_mon);
+ pcf->time[PCF50606_TI_YEAR] = bin2bcd(rtc->tm_year - 100);
+}
+
+static int pcf50606_rtc_ioctl(struct device *dev, unsigned int cmd,
+ unsigned long arg)
+{
+ struct pcf50606 *pcf;
+
+ pcf = dev_get_drvdata(dev);
+
+ switch (cmd) {
+ case RTC_AIE_OFF:
+ /* disable the alarm interrupt */
+ pcf->rtc.alarm_enabled = 0;
+ pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
+ return 0;
+ case RTC_AIE_ON:
+ /* enable the alarm interrupt */
+ pcf->rtc.alarm_enabled = 1;
+ pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
+ return 0;
+ case RTC_PIE_OFF:
+ /* disable periodic interrupt (hz tick) */
+ pcf->rtc.second_enabled = 0;
+ pcf50606_irq_mask(pcf, PCF50606_IRQ_SECOND);
+ return 0;
+ case RTC_PIE_ON:
+ /* ensable periodic interrupt (hz tick) */
+ pcf->rtc.second_enabled = 1;
+ pcf50606_irq_unmask(pcf, PCF50606_IRQ_SECOND);
+ return 0;
+ }
+ return -ENOIOCTLCMD;
+}
+
+static int pcf50606_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct pcf50606 *pcf;
+ struct pcf50606_time pcf_tm;
+ int ret;
+
+ pcf = dev_get_drvdata(dev);
+
+ ret = pcf50606_read_block(pcf, PCF50606_REG_RTCSC,
+ PCF50606_TI_EXTENT,
+ &pcf_tm.time[0]);
+ if (ret != PCF50606_TI_EXTENT)
+ dev_err(dev, "Failed to read time\n");
+
+ dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
+ pcf_tm.time[PCF50606_TI_DAY],
+ pcf_tm.time[PCF50606_TI_MONTH],
+ pcf_tm.time[PCF50606_TI_YEAR],
+ pcf_tm.time[PCF50606_TI_HOUR],
+ pcf_tm.time[PCF50606_TI_MIN],
+ pcf_tm.time[PCF50606_TI_SEC]);
+
+ pcf2rtc_time(tm, &pcf_tm);
+
+ dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
+ tm->tm_mday, tm->tm_mon, tm->tm_year,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
+
+static int pcf50606_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct pcf50606 *pcf;
+ struct pcf50606_time pcf_tm;
+ int ret;
+ int second_masked, alarm_masked;
+
+ pcf = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
+ tm->tm_mday, tm->tm_mon, tm->tm_year,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+ rtc2pcf_time(&pcf_tm, tm);
+ dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
+ pcf_tm.time[PCF50606_TI_DAY],
+ pcf_tm.time[PCF50606_TI_MONTH],
+ pcf_tm.time[PCF50606_TI_YEAR],
+ pcf_tm.time[PCF50606_TI_HOUR],
+ pcf_tm.time[PCF50606_TI_MIN],
+ pcf_tm.time[PCF50606_TI_SEC]);
+
+
+ second_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_SECOND);
+ alarm_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_ALARM);
+
+ if (!second_masked)
+ pcf50606_irq_mask(pcf, PCF50606_IRQ_SECOND);
+ if (!alarm_masked)
+ pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
+
+ ret = pcf50606_write_block(pcf, PCF50606_REG_RTCSC,
+ PCF50606_TI_EXTENT,
+ &pcf_tm.time[0]);
+ if (ret)
+ dev_err(dev, "Failed to set time %d\n", ret);
+
+ if (!second_masked)
+ pcf50606_irq_unmask(pcf, PCF50606_IRQ_SECOND);
+ if (!alarm_masked)
+ pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
+
+
+ return 0;
+}
+
+static int pcf50606_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct pcf50606 *pcf;
+ struct pcf50606_time pcf_tm;
+ int ret;
+
+ pcf = dev_get_drvdata(dev);
+
+ alrm->enabled = pcf->rtc.alarm_enabled;
+
+ ret = pcf50606_read_block(pcf, PCF50606_REG_RTCSCA,
+ PCF50606_TI_EXTENT, &pcf_tm.time[0]);
+
+ if (ret != PCF50606_TI_EXTENT)
+ dev_err(dev, "Failed to read Alarm time :-(\n");
+
+ pcf2rtc_time(&alrm->time, &pcf_tm);
+
+ return 0;
+}
+
+static int pcf50606_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct pcf50606 *pcf;
+ struct pcf50606_time pcf_tm;
+ int ret, alarm_masked;
+
+ pcf = dev_get_drvdata(dev);
+
+ rtc2pcf_time(&pcf_tm, &alrm->time);
+
+ /* do like mktime does and ignore tm_wday */
+ pcf_tm.time[PCF50606_TI_WKDAY] = 7;
+
+ alarm_masked = pcf50606_irq_mask_get(pcf, PCF50606_IRQ_ALARM);
+
+ /* disable alarm interrupt */
+ if (!alarm_masked)
+ pcf50606_irq_mask(pcf, PCF50606_IRQ_ALARM);
+
+ ret = pcf50606_write_block(pcf, PCF50606_REG_RTCSCA,
+ PCF50606_TI_EXTENT, &pcf_tm.time[0]);
+ if (ret)
+ dev_err(dev, "Failed to write alarm time %d\n", ret);
+
+ if (!alarm_masked)
+ pcf50606_irq_unmask(pcf, PCF50606_IRQ_ALARM);
+
+ return 0;
+}
+static struct rtc_class_ops pcf50606_rtc_ops = {
+ .ioctl = pcf50606_rtc_ioctl,
+ .read_time = pcf50606_rtc_read_time,
+ .set_time = pcf50606_rtc_set_time,
+ .read_alarm = pcf50606_rtc_read_alarm,
+ .set_alarm = pcf50606_rtc_set_alarm,
+};
+
+static void pcf50606_rtc_irq(struct pcf50606 *pcf, int irq, void *unused)
+{
+ switch (irq) {
+ case PCF50606_IRQ_ALARM:
+ rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_AF | RTC_IRQF);
+ break;
+ case PCF50606_IRQ_SECOND:
+ rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_PF | RTC_IRQF);
+ break;
+ }
+}
+
+static int pcf50606_rtc_probe(struct platform_device *pdev)
+{
+ struct rtc_device *rtc;
+ struct pcf50606 *pcf;
+
+ rtc = rtc_device_register("pcf50606", &pdev->dev,
+ &pcf50606_rtc_ops, THIS_MODULE);
+ if (IS_ERR(rtc))
+ return -ENODEV;
+
+ pcf = platform_get_drvdata(pdev);
+
+ /* Set up IRQ handlers */
+ pcf->irq_handler[PCF50606_IRQ_ALARM].handler = pcf50606_rtc_irq;
+ pcf->irq_handler[PCF50606_IRQ_SECOND].handler = pcf50606_rtc_irq;
+
+ pcf->rtc.rtc_dev = rtc;
+
+ return 0;
+}
+
+static int pcf50606_rtc_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+
+static struct platform_driver pcf50606_rtc_driver = {
+ .driver = {
+ .name = "pcf50606-rtc",
+ },
+ .probe = pcf50606_rtc_probe,
+ .remove = __devexit_p(pcf50606_rtc_remove),
+};
+
+static int __init pcf50606_rtc_init(void)
+{
+ return platform_driver_register(&pcf50606_rtc_driver);
+}
+module_init(pcf50606_rtc_init);
+
+static void __exit pcf50606_rtc_exit(void)
+{
+ platform_driver_unregister(&pcf50606_rtc_driver);
+}
+module_exit(pcf50606_rtc_exit);
+
+
+MODULE_DESCRIPTION("RTC driver for NXP PCF50606 power management unit");
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_LICENSE("GPL");
+
--- /dev/null
+++ b/drivers/rtc/rtc-pcf50633.c
@@ -0,0 +1,300 @@
+/* Philips PCF50633 RTC Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50633 driver mainly by
+ * Harald Welte, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+#include <linux/bcd.h>
+
+#include <linux/mfd/pcf50633/core.h>
+#include <linux/mfd/pcf50633/rtc.h>
+
+enum pcf50633_time_indexes {
+ PCF50633_TI_SEC = 0,
+ PCF50633_TI_MIN,
+ PCF50633_TI_HOUR,
+ PCF50633_TI_WKDAY,
+ PCF50633_TI_DAY,
+ PCF50633_TI_MONTH,
+ PCF50633_TI_YEAR,
+ PCF50633_TI_EXTENT /* always last */
+};
+
+
+struct pcf50633_time {
+ u_int8_t time[PCF50633_TI_EXTENT];
+};
+
+static void pcf2rtc_time(struct rtc_time *rtc, struct pcf50633_time *pcf)
+{
+ rtc->tm_sec = bcd2bin(pcf->time[PCF50633_TI_SEC]);
+ rtc->tm_min = bcd2bin(pcf->time[PCF50633_TI_MIN]);
+ rtc->tm_hour = bcd2bin(pcf->time[PCF50633_TI_HOUR]);
+ rtc->tm_wday = bcd2bin(pcf->time[PCF50633_TI_WKDAY]);
+ rtc->tm_mday = bcd2bin(pcf->time[PCF50633_TI_DAY]);
+ rtc->tm_mon = bcd2bin(pcf->time[PCF50633_TI_MONTH]);
+ rtc->tm_year = bcd2bin(pcf->time[PCF50633_TI_YEAR]) + 100;
+}
+
+static void rtc2pcf_time(struct pcf50633_time *pcf, struct rtc_time *rtc)
+{
+ pcf->time[PCF50633_TI_SEC] = bin2bcd(rtc->tm_sec);
+ pcf->time[PCF50633_TI_MIN] = bin2bcd(rtc->tm_min);
+ pcf->time[PCF50633_TI_HOUR] = bin2bcd(rtc->tm_hour);
+ pcf->time[PCF50633_TI_WKDAY] = bin2bcd(rtc->tm_wday);
+ pcf->time[PCF50633_TI_DAY] = bin2bcd(rtc->tm_mday);
+ pcf->time[PCF50633_TI_MONTH] = bin2bcd(rtc->tm_mon);
+ pcf->time[PCF50633_TI_YEAR] = bin2bcd(rtc->tm_year - 100);
+}
+
+static int pcf50633_rtc_ioctl(struct device *dev, unsigned int cmd,
+ unsigned long arg)
+{
+ struct pcf50633 *pcf;
+
+ pcf = dev_get_drvdata(dev);
+
+ switch (cmd) {
+ case RTC_AIE_OFF:
+ /* disable the alarm interrupt */
+ pcf->rtc.alarm_enabled = 0;
+ pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
+ return 0;
+ case RTC_AIE_ON:
+ /* enable the alarm interrupt */
+ pcf->rtc.alarm_enabled = 1;
+ pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
+ return 0;
+ case RTC_PIE_OFF:
+ /* disable periodic interrupt (hz tick) */
+ pcf->rtc.second_enabled = 0;
+ pcf50633_irq_mask(pcf, PCF50633_IRQ_SECOND);
+ return 0;
+ case RTC_PIE_ON:
+ /* ensable periodic interrupt (hz tick) */
+ pcf->rtc.second_enabled = 1;
+ pcf50633_irq_unmask(pcf, PCF50633_IRQ_SECOND);
+ return 0;
+ }
+ return -ENOIOCTLCMD;
+}
+
+static int pcf50633_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct pcf50633 *pcf;
+ struct pcf50633_time pcf_tm;
+ int ret;
+
+ pcf = dev_get_drvdata(dev);
+
+ ret = pcf50633_read_block(pcf, PCF50633_REG_RTCSC,
+ PCF50633_TI_EXTENT,
+ &pcf_tm.time[0]);
+ if (ret != PCF50633_TI_EXTENT)
+ dev_err(dev, "Failed to read time\n");
+
+ dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
+ pcf_tm.time[PCF50633_TI_DAY],
+ pcf_tm.time[PCF50633_TI_MONTH],
+ pcf_tm.time[PCF50633_TI_YEAR],
+ pcf_tm.time[PCF50633_TI_HOUR],
+ pcf_tm.time[PCF50633_TI_MIN],
+ pcf_tm.time[PCF50633_TI_SEC]);
+
+ pcf2rtc_time(tm, &pcf_tm);
+
+ dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
+ tm->tm_mday, tm->tm_mon, tm->tm_year,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
+
+static int pcf50633_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct pcf50633 *pcf;
+ struct pcf50633_time pcf_tm;
+ int ret;
+ int second_masked, alarm_masked;
+
+ pcf = dev_get_drvdata(dev);
+
+ dev_dbg(dev, "RTC_TIME: %u.%u.%u %u:%u:%u\n",
+ tm->tm_mday, tm->tm_mon, tm->tm_year,
+ tm->tm_hour, tm->tm_min, tm->tm_sec);
+ rtc2pcf_time(&pcf_tm, tm);
+ dev_dbg(dev, "PCF_TIME: %02x.%02x.%02x %02x:%02x:%02x\n",
+ pcf_tm.time[PCF50633_TI_DAY],
+ pcf_tm.time[PCF50633_TI_MONTH],
+ pcf_tm.time[PCF50633_TI_YEAR],
+ pcf_tm.time[PCF50633_TI_HOUR],
+ pcf_tm.time[PCF50633_TI_MIN],
+ pcf_tm.time[PCF50633_TI_SEC]);
+
+
+ second_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_SECOND);
+ alarm_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_ALARM);
+
+ if (!second_masked)
+ pcf50633_irq_mask(pcf, PCF50633_IRQ_SECOND);
+ if (!alarm_masked)
+ pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
+
+ ret = pcf50633_write_block(pcf, PCF50633_REG_RTCSC,
+ PCF50633_TI_EXTENT,
+ &pcf_tm.time[0]);
+ if (ret)
+ dev_err(dev, "Failed to set time %d\n", ret);
+
+ if (!second_masked)
+ pcf50633_irq_unmask(pcf, PCF50633_IRQ_SECOND);
+ if (!alarm_masked)
+ pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
+
+
+ return 0;
+}
+
+static int pcf50633_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct pcf50633 *pcf;
+ struct pcf50633_time pcf_tm;
+ int ret;
+
+ pcf = dev_get_drvdata(dev);
+
+ alrm->enabled = pcf->rtc.alarm_enabled;
+
+ ret = pcf50633_read_block(pcf, PCF50633_REG_RTCSCA,
+ PCF50633_TI_EXTENT, &pcf_tm.time[0]);
+
+ if (ret != PCF50633_TI_EXTENT)
+ dev_err(dev, "Failed to read Alarm time :-(\n");
+
+ pcf2rtc_time(&alrm->time, &pcf_tm);
+
+ return 0;
+}
+
+static int pcf50633_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct pcf50633 *pcf;
+ struct pcf50633_time pcf_tm;
+ int ret, alarm_masked;
+
+ pcf = dev_get_drvdata(dev);
+
+ rtc2pcf_time(&pcf_tm, &alrm->time);
+
+ /* do like mktime does and ignore tm_wday */
+ pcf_tm.time[PCF50633_TI_WKDAY] = 7;
+
+ alarm_masked = pcf50633_irq_mask_get(pcf, PCF50633_IRQ_ALARM);
+
+ /* disable alarm interrupt */
+ if (!alarm_masked)
+ pcf50633_irq_mask(pcf, PCF50633_IRQ_ALARM);
+
+ ret = pcf50633_write_block(pcf, PCF50633_REG_RTCSCA,
+ PCF50633_TI_EXTENT, &pcf_tm.time[0]);
+ if (ret)
+ dev_err(dev, "Failed to write alarm time %d\n", ret);
+
+ if (!alarm_masked)
+ pcf50633_irq_unmask(pcf, PCF50633_IRQ_ALARM);
+
+ return 0;
+}
+static struct rtc_class_ops pcf50633_rtc_ops = {
+ .ioctl = pcf50633_rtc_ioctl,
+ .read_time = pcf50633_rtc_read_time,
+ .set_time = pcf50633_rtc_set_time,
+ .read_alarm = pcf50633_rtc_read_alarm,
+ .set_alarm = pcf50633_rtc_set_alarm,
+};
+
+static void pcf50633_rtc_irq(struct pcf50633 *pcf, int irq, void *unused)
+{
+ switch (irq) {
+ case PCF50633_IRQ_ALARM:
+ rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_AF | RTC_IRQF);
+ break;
+ case PCF50633_IRQ_SECOND:
+ rtc_update_irq(pcf->rtc.rtc_dev, 1, RTC_PF | RTC_IRQF);
+ break;
+ }
+}
+
+static int pcf50633_rtc_probe(struct platform_device *pdev)
+{
+ struct rtc_device *rtc;
+ struct pcf50633 *pcf;
+
+ rtc = rtc_device_register("pcf50633", &pdev->dev,
+ &pcf50633_rtc_ops, THIS_MODULE);
+ if (IS_ERR(rtc))
+ return -ENODEV;
+
+ pcf = platform_get_drvdata(pdev);
+
+ /* Set up IRQ handlers */
+ pcf->irq_handler[PCF50633_IRQ_ALARM].handler = pcf50633_rtc_irq;
+ pcf->irq_handler[PCF50633_IRQ_SECOND].handler = pcf50633_rtc_irq;
+
+ pcf->rtc.rtc_dev = rtc;
+
+ return 0;
+}
+
+static int pcf50633_rtc_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+
+static struct platform_driver pcf50633_rtc_driver = {
+ .driver = {
+ .name = "pcf50633-rtc",
+ },
+ .probe = pcf50633_rtc_probe,
+ .remove = __devexit_p(pcf50633_rtc_remove),
+};
+
+static int __init pcf50633_rtc_init(void)
+{
+ return platform_driver_register(&pcf50633_rtc_driver);
+}
+module_init(pcf50633_rtc_init);
+
+static void __exit pcf50633_rtc_exit(void)
+{
+ platform_driver_unregister(&pcf50633_rtc_driver);
+}
+module_exit(pcf50633_rtc_exit);
+
+
+MODULE_DESCRIPTION("RTC driver for NXP PCF50633 power management unit");
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_LICENSE("GPL");
+
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -26,7 +26,7 @@
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/plat-s3c/regs-rtc.h>
+#include <plat/regs-rtc.h>
/* I have yet to find an S3C implementation with more than one
* of these rtc blocks in */
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -447,7 +447,7 @@
config SERIAL_SAMSUNG
tristate "Samsung SoC serial support"
- depends on ARM && PLAT_S3C24XX
+ depends on ARM && PLAT_S3C
select SERIAL_CORE
help
Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
@@ -455,6 +455,16 @@
provide all of these ports, depending on how the serial port
pins are configured.
+config SERIAL_SAMSUNG_UARTS
+ int
+ depends on SERIAL_SAMSUNG
+ default 2 if ARCH_S3C2400
+ default 4 if ARCH_S3C64XX || CPU_S3C2443
+ default 3
+ help
+ Select the number of available UART ports for the Samsung S3C
+ serial driver
+
config SERIAL_SAMSUNG_DEBUG
bool "Samsung SoC serial debug"
depends on SERIAL_SAMSUNG && DEBUG_LL
@@ -508,7 +518,20 @@
help
Serial port support for the Samsung S3C2440 and S3C2442 SoC
-
+config SERIAL_S3C24A0
+ tristate "Samsung S3C24A0 Serial port support"
+ depends on SERIAL_SAMSUNG && CPU_S3C24A0
+ default y if CPU_S3C24A0
+ help
+ Serial port support for the Samsung S3C24A0 SoC
+
+config SERIAL_S3C6400
+ tristate "Samsung S3C6400/S3C6410 Serial port support"
+ depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410)
+ default y
+ help
+ Serial port support for the Samsung S3C6400 and S3C6410
+ SoCs
config SERIAL_DZ
bool "DECstation DZ serial driver"
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,6 +41,8 @@
obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
+obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
+obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
obj-$(CONFIG_SERIAL_MUX) += mux.o
obj-$(CONFIG_SERIAL_68328) += 68328serial.o
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -19,6 +19,7 @@
#include <linux/serial.h>
#include <asm/irq.h>
+
#include <mach/hardware.h>
#include <plat/regs-serial.h>
--- /dev/null
+++ b/drivers/serial/s3c24a0.c
@@ -0,0 +1,118 @@
+/* linux/drivers/serial/s3c24a0.c
+ *
+ * Driver for Samsung S3C24A0 SoC onboard UARTs.
+ *
+ * Based on drivers/serial/s3c2410.c
+ *
+ * Author: Sandeep Patil <sandeep.patil@azingo.com>
+ *
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+
+#include "samsung.h"
+
+static int s3c24a0_serial_setsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ if (strcmp(clk->name, "uclk") == 0)
+ ucon |= S3C2410_UCON_UCLK;
+ else
+ ucon &= ~S3C2410_UCON_UCLK;
+
+ wr_regl(port, S3C2410_UCON, ucon);
+ return 0;
+}
+
+static int s3c24a0_serial_getsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ clk->divisor = 1;
+ clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
+
+ return 0;
+}
+
+static int s3c24a0_serial_resetport(struct uart_port *port,
+ struct s3c2410_uartcfg *cfg)
+{
+ dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
+ port, port->mapbase, cfg);
+
+ wr_regl(port, S3C2410_UCON, cfg->ucon);
+ wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+ /* reset both fifos */
+
+ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+ wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+ return 0;
+}
+
+static struct s3c24xx_uart_info s3c24a0_uart_inf = {
+ .name = "Samsung S3C24A0 UART",
+ .type = PORT_S3C2410,
+ .fifosize = 16,
+ .rx_fifomask = S3C24A0_UFSTAT_RXMASK,
+ .rx_fifoshift = S3C24A0_UFSTAT_RXSHIFT,
+ .rx_fifofull = S3C24A0_UFSTAT_RXFULL,
+ .tx_fifofull = S3C24A0_UFSTAT_TXFULL,
+ .tx_fifomask = S3C24A0_UFSTAT_TXMASK,
+ .tx_fifoshift = S3C24A0_UFSTAT_TXSHIFT,
+ .get_clksrc = s3c24a0_serial_getsource,
+ .set_clksrc = s3c24a0_serial_setsource,
+ .reset_port = s3c24a0_serial_resetport,
+};
+
+static int s3c24a0_serial_probe(struct platform_device *dev)
+{
+ return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
+}
+
+static struct platform_driver s3c24a0_serial_drv = {
+ .probe = s3c24a0_serial_probe,
+ .remove = s3c24xx_serial_remove,
+ .driver = {
+ .name = "s3c24a0-uart",
+ .owner = THIS_MODULE,
+ },
+};
+
+s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
+
+static int __init s3c24a0_serial_init(void)
+{
+ return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
+}
+
+static void __exit s3c24a0_serial_exit(void)
+{
+ platform_driver_unregister(&s3c24a0_serial_drv);
+}
+
+module_init(s3c24a0_serial_init);
+module_exit(s3c24a0_serial_exit);
+
--- /dev/null
+++ b/drivers/serial/s3c6400.c
@@ -0,0 +1,152 @@
+/* linux/drivers/serial/s3c6400.c
+ *
+ * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+
+#include "samsung.h"
+
+static int s3c6400_serial_setsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ if (strcmp(clk->name, "uclk0") == 0) {
+ ucon &= ~S3C6400_UCON_CLKMASK;
+ ucon |= S3C6400_UCON_UCLK0;
+ } else if (strcmp(clk->name, "uclk1") == 0)
+ ucon |= S3C6400_UCON_UCLK1;
+ else if (strcmp(clk->name, "pclk") == 0) {
+ /* See notes about transitioning from UCLK to PCLK */
+ ucon &= ~S3C6400_UCON_UCLK0;
+ } else {
+ printk(KERN_ERR "unknown clock source %s\n", clk->name);
+ return -EINVAL;
+ }
+
+ wr_regl(port, S3C2410_UCON, ucon);
+ return 0;
+}
+
+
+static int s3c6400_serial_getsource(struct uart_port *port,
+ struct s3c24xx_uart_clksrc *clk)
+{
+ u32 ucon = rd_regl(port, S3C2410_UCON);
+
+ clk->divisor = 1;
+
+ switch (ucon & S3C6400_UCON_CLKMASK) {
+ case S3C6400_UCON_UCLK0:
+ clk->name = "uclk0";
+ break;
+
+ case S3C6400_UCON_UCLK1:
+ clk->name = "uclk1";
+ break;
+
+ case S3C6400_UCON_PCLK:
+ case S3C6400_UCON_PCLK2:
+ clk->name = "pclk";
+ break;
+ }
+
+ return 0;
+}
+
+static int s3c6400_serial_resetport(struct uart_port *port,
+ struct s3c2410_uartcfg *cfg)
+{
+ unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+ dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
+ port, port->mapbase, cfg);
+
+ /* ensure we don't change the clock settings... */
+
+ ucon &= S3C6400_UCON_CLKMASK;
+
+ wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
+ wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+ /* reset both fifos */
+
+ wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+ wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+ return 0;
+}
+
+static struct s3c24xx_uart_info s3c6400_uart_inf = {
+ .name = "Samsung S3C6400 UART",
+ .type = PORT_S3C6400,
+ .fifosize = 64,
+ .has_divslot = 1,
+ .rx_fifomask = S3C2440_UFSTAT_RXMASK,
+ .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
+ .rx_fifofull = S3C2440_UFSTAT_RXFULL,
+ .tx_fifofull = S3C2440_UFSTAT_TXFULL,
+ .tx_fifomask = S3C2440_UFSTAT_TXMASK,
+ .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
+ .get_clksrc = s3c6400_serial_getsource,
+ .set_clksrc = s3c6400_serial_setsource,
+ .reset_port = s3c6400_serial_resetport,
+};
+
+/* device management */
+
+static int s3c6400_serial_probe(struct platform_device *dev)
+{
+ dbg("s3c6400_serial_probe: dev=%p\n", dev);
+ return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
+}
+
+static struct platform_driver s3c6400_serial_drv = {
+ .probe = s3c6400_serial_probe,
+ .remove = s3c24xx_serial_remove,
+ .driver = {
+ .name = "s3c6400-uart",
+ .owner = THIS_MODULE,
+ },
+};
+
+s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
+
+static int __init s3c6400_serial_init(void)
+{
+ return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
+}
+
+static void __exit s3c6400_serial_exit(void)
+{
+ platform_driver_unregister(&s3c6400_serial_drv);
+}
+
+module_init(s3c6400_serial_init);
+module_exit(s3c6400_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c6400-uart");
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -42,13 +42,18 @@
#include <linux/serial.h>
#include <linux/delay.h>
#include <linux/clk.h>
+#include <linux/cpufreq.h>
#include <asm/irq.h>
#include <mach/hardware.h>
+#include <mach/map.h>
#include <plat/regs-serial.h>
+#if defined(CONFIG_MACH_NEO1973) && !defined(CONFIG_CPU_S3C6410)
#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#endif
#include "samsung.h"
@@ -58,19 +63,6 @@
#define S3C24XX_SERIAL_MAJOR 204
#define S3C24XX_SERIAL_MINOR 64
-/* we can support 3 uarts, but not always use them */
-
-#ifdef CONFIG_CPU_S3C2400
-#define NR_PORTS (2)
-#else
-#define NR_PORTS (3)
-#endif
-
-/* port irq numbers */
-
-#define TX_IRQ(port) ((port)->irq + 1)
-#define RX_IRQ(port) ((port)->irq)
-
/* macros to change one thing to another */
#define tx_enabled(port) ((port)->unused[0])
@@ -136,8 +128,10 @@
static void s3c24xx_serial_stop_tx(struct uart_port *port)
{
+ struct s3c24xx_uart_port *ourport = to_ourport(port);
+
if (tx_enabled(port)) {
- disable_irq(TX_IRQ(port));
+ disable_irq(ourport->tx_irq);
tx_enabled(port) = 0;
if (port->flags & UPF_CONS_FLOW)
s3c24xx_serial_rx_enable(port);
@@ -146,11 +140,13 @@
static void s3c24xx_serial_start_tx(struct uart_port *port)
{
+ struct s3c24xx_uart_port *ourport = to_ourport(port);
+
if (!tx_enabled(port)) {
if (port->flags & UPF_CONS_FLOW)
s3c24xx_serial_rx_disable(port);
- enable_irq(TX_IRQ(port));
+ enable_irq(ourport->tx_irq);
tx_enabled(port) = 1;
}
}
@@ -158,9 +154,11 @@
static void s3c24xx_serial_stop_rx(struct uart_port *port)
{
+ struct s3c24xx_uart_port *ourport = to_ourport(port);
+
if (rx_enabled(port)) {
dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
- disable_irq(RX_IRQ(port));
+ disable_irq(ourport->rx_irq);
rx_enabled(port) = 0;
}
}
@@ -241,7 +239,7 @@
port->icount.rx++;
if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
- dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
+ printk(KERN_DEBUG "rxerr: port ch=0x%02x, rxs=0x%08x\n",
ch, uerstat);
/* check for break */
@@ -384,13 +382,13 @@
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (ourport->tx_claimed) {
- free_irq(TX_IRQ(port), ourport);
+ free_irq(ourport->tx_irq, ourport);
tx_enabled(port) = 0;
ourport->tx_claimed = 0;
}
if (ourport->rx_claimed) {
- free_irq(RX_IRQ(port), ourport);
+ free_irq(ourport->rx_irq, ourport);
ourport->rx_claimed = 0;
rx_enabled(port) = 0;
}
@@ -407,12 +405,11 @@
rx_enabled(port) = 1;
- ret = request_irq(RX_IRQ(port),
- s3c24xx_serial_rx_chars, 0,
+ ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
s3c24xx_serial_portname(port), ourport);
if (ret != 0) {
- printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
+ printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
return ret;
}
@@ -422,12 +419,11 @@
tx_enabled(port) = 1;
- ret = request_irq(TX_IRQ(port),
- s3c24xx_serial_tx_chars, 0,
+ ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
s3c24xx_serial_portname(port), ourport);
if (ret) {
- printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
+ printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
goto err;
}
@@ -452,6 +448,8 @@
{
struct s3c24xx_uart_port *ourport = to_ourport(port);
+ ourport->pm_level = level;
+
switch (level) {
case 3:
if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
@@ -514,6 +512,7 @@
struct baud_calc {
struct s3c24xx_uart_clksrc *clksrc;
unsigned int calc;
+ unsigned int divslot;
unsigned int quot;
struct clk *src;
};
@@ -523,6 +522,7 @@
struct s3c24xx_uart_clksrc *clksrc,
unsigned int baud)
{
+ struct s3c24xx_uart_port *ourport = to_ourport(port);
unsigned long rate;
calc->src = clk_get(port->dev, clksrc->name);
@@ -533,8 +533,24 @@
rate /= clksrc->divisor;
calc->clksrc = clksrc;
- calc->quot = (rate + (8 * baud)) / (16 * baud);
- calc->calc = (rate / (calc->quot * 16));
+
+ if (ourport->info->has_divslot) {
+ unsigned long div = rate / baud;
+
+ /* The UDIVSLOT register on the newer UARTs allows us to
+ * get a divisor adjustment of 1/16th on the baud clock.
+ *
+ * We don't keep the UDIVSLOT value (the 16ths we calculated
+ * by not multiplying the baud by 16) as it is easy enough
+ * to recalculate.
+ */
+
+ calc->quot = div / 16;
+ calc->calc = rate / div;
+ } else {
+ calc->quot = (rate + (8 * baud)) / (16 * baud);
+ calc->calc = (rate / (calc->quot * 16));
+ }
calc->quot--;
return 1;
@@ -617,6 +633,30 @@
return best->quot;
}
+/* udivslot_table[]
+ *
+ * This table takes the fractional value of the baud divisor and gives
+ * the recommended setting for the UDIVSLOT register.
+ */
+static u16 udivslot_table[16] = {
+ [0] = 0x0000,
+ [1] = 0x0080,
+ [2] = 0x0808,
+ [3] = 0x0888,
+ [4] = 0x2222,
+ [5] = 0x4924,
+ [6] = 0x4A52,
+ [7] = 0x54AA,
+ [8] = 0x5555,
+ [9] = 0xD555,
+ [10] = 0xD5D5,
+ [11] = 0xDDD5,
+ [12] = 0xDDDD,
+ [13] = 0xDFDD,
+ [14] = 0xDFDF,
+ [15] = 0xFFDF,
+};
+
static void s3c24xx_serial_set_termios(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
@@ -629,6 +669,7 @@
unsigned int baud, quot;
unsigned int ulcon;
unsigned int umcon;
+ unsigned int udivslot = 0;
/*
* We don't support modem control lines.
@@ -650,6 +691,7 @@
/* check to see if we need to change clock source */
if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
+ dbg("selecting clock %p\n", clk);
s3c24xx_serial_setsource(port, clksrc);
if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
@@ -661,6 +703,14 @@
ourport->clksrc = clksrc;
ourport->baudclk = clk;
+ ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
+ }
+
+ if (ourport->info->has_divslot) {
+ unsigned int div = ourport->baudclk_rate / baud;
+
+ udivslot = udivslot_table[div & 15];
+ dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
}
switch (termios->c_cflag & CSIZE) {
@@ -702,12 +752,16 @@
spin_lock_irqsave(&port->lock, flags);
- dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
+ dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
+ ulcon, quot, udivslot);
wr_regl(port, S3C2410_ULCON, ulcon);
wr_regl(port, S3C2410_UBRDIV, quot);
wr_regl(port, S3C2410_UMCON, umcon);
+ if (ourport->info->has_divslot)
+ wr_regl(port, S3C2443_DIVSLOT, udivslot);
+
dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
rd_regl(port, S3C2410_ULCON),
rd_regl(port, S3C2410_UCON),
@@ -752,6 +806,8 @@
return "S3C2440";
case PORT_S3C2412:
return "S3C2412";
+ case PORT_S3C6400:
+ return "S3C6400/10";
default:
return NULL;
}
@@ -827,14 +883,14 @@
static struct uart_driver s3c24xx_uart_drv = {
.owner = THIS_MODULE,
.dev_name = "s3c2410_serial",
- .nr = 3,
+ .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
.cons = S3C24XX_SERIAL_CONSOLE,
.driver_name = S3C24XX_SERIAL_NAME,
.major = S3C24XX_SERIAL_MAJOR,
.minor = S3C24XX_SERIAL_MINOR,
};
-static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
+static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
[0] = {
.port = {
.lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
@@ -859,7 +915,7 @@
.line = 1,
}
},
-#if NR_PORTS > 2
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
[2] = {
.port = {
@@ -872,10 +928,88 @@
.flags = UPF_BOOT_AUTOCONF,
.line = 2,
}
+ },
+#endif
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
+ [3] = {
+ .port = {
+ .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
+ .iotype = UPIO_MEM,
+ .irq = IRQ_S3CUART_RX3,
+ .uartclk = 0,
+ .fifosize = 16,
+ .ops = &s3c24xx_serial_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 3,
+ }
}
#endif
};
+#ifdef CONFIG_MACH_NEO1973_GTA02
+static void s3c24xx_serial_force_debug_port_up(void)
+{
+ struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[
+ CONFIG_DEBUG_S3C_UART];
+ struct s3c24xx_uart_clksrc *clksrc = NULL;
+ struct clk *clk = NULL;
+ unsigned long tmp;
+
+ s3c24xx_serial_getclk(&ourport->port, &clksrc, &clk, 115200);
+
+ tmp = __raw_readl(S3C2410_CLKCON);
+
+ /* re-start uart clocks */
+ tmp |= S3C2410_CLKCON_UART0;
+ tmp |= S3C2410_CLKCON_UART1;
+ tmp |= S3C2410_CLKCON_UART2;
+
+ __raw_writel(tmp, S3C2410_CLKCON);
+ udelay(10);
+
+ s3c24xx_serial_setsource(&ourport->port, clksrc);
+
+ if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
+ clk_disable(ourport->baudclk);
+ ourport->baudclk = NULL;
+ }
+
+ clk_enable(clk);
+
+ ourport->clksrc = clksrc;
+ ourport->baudclk = clk;
+}
+
+static void s3c2410_printascii(const char *sz)
+{
+ struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[
+ CONFIG_DEBUG_S3C_UART];
+ struct uart_port *port = &ourport->port;
+
+ /* 8 N 1 */
+ wr_regl(port, S3C2410_ULCON, (rd_regl(port, S3C2410_ULCON)) | 3);
+ /* polling mode */
+ wr_regl(port, S3C2410_UCON, (rd_regl(port, S3C2410_UCON) & ~0xc0f) | 5);
+ /* disable FIFO */
+ wr_regl(port, S3C2410_UFCON, (rd_regl(port, S3C2410_UFCON) & ~0x01));
+ /* fix baud rate */
+ wr_regl(port, S3C2410_UBRDIV, 26);
+
+ while (*sz) {
+ int timeout = 10000000;
+
+ /* spin on it being busy */
+ while ((!(rd_regl(port, S3C2410_UTRSTAT) & 2)) && timeout--)
+ ;
+
+ /* transmit register */
+ wr_regl(port, S3C2410_UTXH, *sz);
+
+ sz++;
+ }
+}
+#endif
+
/* s3c24xx_serial_resetport
*
* wrapper to call the specific reset for this port (reset the fifos
@@ -890,6 +1024,93 @@
return (info->reset_port)(port, cfg);
}
+
+#ifdef CONFIG_CPU_FREQ
+
+static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
+ unsigned long val, void *data)
+{
+ struct s3c24xx_uart_port *port;
+ struct uart_port *uport;
+
+ port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
+ uport = &port->port;
+
+ /* check to see if port is enabled */
+
+ if (port->pm_level != 0)
+ return 0;
+
+ /* try and work out if the baudrate is changing, we can detect
+ * a change in rate, but we do not have support for detecting
+ * a disturbance in the clock-rate over the change.
+ */
+
+ if (IS_ERR(port->clk))
+ goto exit;
+
+ if (port->baudclk_rate == clk_get_rate(port->clk))
+ goto exit;
+
+ if (val == CPUFREQ_PRECHANGE) {
+ /* we should really shut the port down whilst the
+ * frequency change is in progress. */
+
+ } else if (val == CPUFREQ_POSTCHANGE) {
+ struct ktermios *termios;
+ struct tty_struct *tty;
+
+ if (uport->info == NULL) {
+ printk(KERN_WARNING "%s: info NULL\n", __func__);
+ goto exit;
+ }
+
+ tty = uport->info->port.tty;
+
+ if (tty == NULL) {
+ printk(KERN_WARNING "%s: tty is NULL\n", __func__);
+ goto exit;
+ }
+
+ termios = tty->termios;
+
+ if (termios == NULL) {
+ printk(KERN_WARNING "%s: no termios?\n", __func__);
+ goto exit;
+ }
+
+ s3c24xx_serial_set_termios(uport, termios, NULL);
+ }
+
+ exit:
+ return 0;
+}
+
+static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
+{
+ port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
+
+ return cpufreq_register_notifier(&port->freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
+{
+ cpufreq_unregister_notifier(&port->freq_transition,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
+{
+ return 0;
+}
+
+static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
+{
+}
+#endif
+
/* s3c24xx_serial_init_port
*
* initialise a single serial port from the platform device given
@@ -914,8 +1135,11 @@
if (port->mapbase != 0)
return 0;
- if (cfg->hwport > 3)
- return -EINVAL;
+ if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
+ printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
+ cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
+ return -ERANGE;
+ }
/* setup info for port */
port->dev = &platdev->dev;
@@ -943,18 +1167,26 @@
dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
- port->mapbase = res->start;
- port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
+ port->mapbase = res->start;
+ port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
ret = platform_get_irq(platdev, 0);
if (ret < 0)
port->irq = 0;
- else
+ else {
port->irq = ret;
+ ourport->rx_irq = ret;
+ ourport->tx_irq = ret + 1;
+ }
+
+ ret = platform_get_irq(platdev, 1);
+ if (ret > 0)
+ ourport->tx_irq = ret;
ourport->clk = clk_get(&platdev->dev, "uart");
- dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
- port->mapbase, port->membase, port->irq, port->uartclk);
+ dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
+ port->mapbase, port->membase, port->irq,
+ ourport->rx_irq, ourport->tx_irq, port->uartclk);
/* reset the fifos (and setup the uart) */
s3c24xx_serial_resetport(port, cfg);
@@ -987,6 +1219,7 @@
ourport = &s3c24xx_serial_ports[probe_index];
probe_index++;
+ init_resume_dependency_list(&ourport->resume_dependency);
dbg("%s: initialising port %p...\n", __func__, ourport);
@@ -1002,6 +1235,10 @@
if (ret < 0)
printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
+ ret = s3c24xx_serial_cpufreq_register(ourport);
+ if (ret < 0)
+ dev_err(&dev->dev, "failed to add cpufreq notifier\n");
+
return 0;
probe_err:
@@ -1015,6 +1252,7 @@
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
if (port) {
+ s3c24xx_serial_cpufreq_deregister(to_ourport(port));
device_remove_file(&dev->dev, &dev_attr_clock_source);
uart_remove_one_port(&s3c24xx_uart_drv, port);
}
@@ -1038,6 +1276,16 @@
return 0;
}
+void s3c24xx_serial_register_resume_dependency(struct resume_dependency *
+ resume_dependency, int uart_index)
+{
+ struct s3c24xx_uart_port *ourport = &s3c24xx_serial_ports[uart_index];
+
+ register_resume_dependency(&ourport->resume_dependency,
+ resume_dependency);
+}
+EXPORT_SYMBOL(s3c24xx_serial_register_resume_dependency);
+
static int s3c24xx_serial_resume(struct platform_device *dev)
{
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
@@ -1049,6 +1297,9 @@
clk_disable(ourport->clk);
uart_resume_port(&s3c24xx_uart_drv, port);
+
+ callback_all_resume_dependencies(&ourport->resume_dependency);
+
}
return 0;
@@ -1059,6 +1310,12 @@
struct s3c24xx_uart_info *info)
{
dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ /* set up the emergency debug UART functions */
+
+ printk_emergency_debug_spew_init = s3c24xx_serial_force_debug_port_up;
+ printk_emergency_debug_spew_send_string = s3c2410_printascii;
+#endif
#ifdef CONFIG_PM
drv->suspend = s3c24xx_serial_suspend;
@@ -1098,6 +1355,13 @@
#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
static struct uart_port *cons_uart;
+static int cons_silenced;
+
+void s3c24xx_serial_console_set_silence(int silenced)
+{
+ cons_silenced = silenced;
+}
+EXPORT_SYMBOL(s3c24xx_serial_console_set_silence);
static int
s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
@@ -1122,9 +1386,21 @@
s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
{
unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
+ unsigned int umcon = rd_regl(cons_uart, S3C2410_UMCON);
+
+ if (cons_silenced)
+ return;
+
+ /* If auto HW flow control enabled, temporarily turn it off */
+ if (umcon & S3C2410_UMCOM_AFC)
+ wr_regl(port, S3C2410_UMCON, (umcon & !S3C2410_UMCOM_AFC));
+
while (!s3c24xx_serial_console_txrdy(port, ufcon))
barrier();
wr_regb(cons_uart, S3C2410_UTXH, ch);
+
+ if (umcon & S3C2410_UMCOM_AFC)
+ wr_regl(port, S3C2410_UMCON, umcon);
}
static void
@@ -1219,7 +1495,7 @@
platdev_ptr = s3c24xx_uart_devs;
- for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
+ for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
}
@@ -1240,7 +1516,7 @@
/* is this a valid port */
- if (co->index == -1 || co->index >= NR_PORTS)
+ if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
co->index = 0;
port = &s3c24xx_serial_ports[co->index].port;
--- a/drivers/serial/samsung.h
+++ b/drivers/serial/samsung.h
@@ -10,6 +10,8 @@
* published by the Free Software Foundation.
*/
+#include <linux/resume-dependency.h>
+
struct s3c24xx_uart_info {
char *name;
unsigned int type;
@@ -21,6 +23,10 @@
unsigned long tx_fifoshift;
unsigned long tx_fifofull;
+ /* uart port features */
+
+ unsigned int has_divslot:1;
+
/* clock source control */
int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
@@ -33,12 +39,23 @@
struct s3c24xx_uart_port {
unsigned char rx_claimed;
unsigned char tx_claimed;
+ unsigned int pm_level;
+ unsigned long baudclk_rate;
+
+ unsigned int rx_irq;
+ unsigned int tx_irq;
struct s3c24xx_uart_info *info;
struct s3c24xx_uart_clksrc *clksrc;
struct clk *clk;
struct clk *baudclk;
struct uart_port port;
+
+#ifdef CONFIG_CPU_FREQ
+ struct notifier_block freq_transition;
+#endif
+
+ struct resume_dependency resume_dependency;
};
/* conversion functions */
--- a/drivers/spi/spi_s3c24xx.c
+++ b/drivers/spi/spi_s3c24xx.c
@@ -28,7 +28,7 @@
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
#include <mach/spi.h>
struct s3c24xx_spi {
--- a/drivers/spi/spi_s3c24xx_gpio.c
+++ b/drivers/spi/spi_s3c24xx_gpio.c
@@ -91,7 +91,7 @@
struct s3c2410_spigpio *sg = spidev_to_sg(dev);
if (sg->info && sg->info->chip_select)
- (sg->info->chip_select)(sg->info, value);
+ (sg->info->chip_select)(sg->info, dev->chip_select, value);
}
static int s3c2410_spigpio_probe(struct platform_device *dev)
@@ -100,6 +100,7 @@
struct spi_master *master;
struct s3c2410_spigpio *sp;
int ret;
+ int i;
master = spi_alloc_master(&dev->dev, sizeof(struct s3c2410_spigpio));
if (master == NULL) {
@@ -112,9 +113,11 @@
platform_set_drvdata(dev, sp);
- /* copy in the plkatform data */
+ /* copy in the platform data */
info = sp->info = dev->dev.platform_data;
+ master->num_chipselect = info->num_chipselect;
+
/* setup spi bitbang adaptor */
sp->bitbang.master = spi_master_get(master);
sp->bitbang.master->bus_num = info->bus_num;
@@ -143,6 +146,22 @@
if (ret)
goto err_no_bitbang;
+ /* register the chips to go with the board */
+
+ for (i = 0; i < sp->info->board_size; i++) {
+ struct spi_device *spidev;
+
+ dev_info(&dev->dev, "registering %p: %s\n",
+ &sp->info->board_info[i],
+ sp->info->board_info[i].modalias);
+
+ sp->info->board_info[i].controller_data = sp;
+ spidev = spi_new_device(master, sp->info->board_info + i);
+ if (spidev)
+ spidev->max_speed_hz =
+ sp->info->board_info[i].max_speed_hz;
+ }
+
return 0;
err_no_bitbang:
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -1045,7 +1045,11 @@
/*-------------------------------------------------------------------------*/
static struct usb_gadget_driver composite_driver = {
+#ifdef CONFIG_USB_GADGET_DUALSPEED
.speed = USB_SPEED_HIGH,
+#else
+ .speed = USB_SPEED_FULL,
+#endif
.bind = composite_bind,
.unbind = __exit_p(composite_unbind),
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -122,11 +122,16 @@
* Instead: allocate your own, using normal USB-IF procedures.
*/
+#if 0
/* Thanks to NetChip Technologies for donating this product ID.
* It's for devices with only CDC Ethernet configurations.
*/
#define CDC_VENDOR_NUM 0x0525 /* NetChip */
#define CDC_PRODUCT_NUM 0xa4a1 /* Linux-USB Ethernet Gadget */
+#else
+#define CDC_VENDOR_NUM 0x1457 /* First International Computer */
+#define CDC_PRODUCT_NUM 0x5117 /* Linux-USB Ethernet Gadget */
+#endif
/* For hardware that can't talk CDC, we use the same vendor ID that
* ARM Linux has used for ethernet-over-usb, both with sa1100 and
@@ -147,8 +152,8 @@
* used with CDC Ethernet, Linux 2.4 hosts will need updates to choose
* the non-RNDIS configuration.
*/
-#define RNDIS_VENDOR_NUM 0x0525 /* NetChip */
-#define RNDIS_PRODUCT_NUM 0xa4a2 /* Ethernet/RNDIS Gadget */
+#define RNDIS_VENDOR_NUM 0x1457 /* NetChip */
+#define RNDIS_PRODUCT_NUM 0x5122 /* Ethernet/RNDIS Gadget */
/*-------------------------------------------------------------------------*/
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -53,8 +53,8 @@
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
-#include <asm/plat-s3c24xx/regs-udc.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/regs-udc.h>
+#include <plat/udc.h>
#include "s3c2410_udc.h"
@@ -134,6 +134,8 @@
return 0;
}
#endif
+
+#ifdef CONFIG_USB_GADGET_DEBUG_FS
static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
{
u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
@@ -197,6 +199,7 @@
.release = single_release,
.owner = THIS_MODULE,
};
+#endif
/* io macros */
@@ -843,6 +846,7 @@
u32 ep_csr1;
u32 idx;
+handle_ep_again:
if (likely (!list_empty(&ep->queue)))
req = list_entry(ep->queue.next,
struct s3c2410_request, queue);
@@ -882,6 +886,8 @@
if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
s3c2410_udc_read_fifo(ep,req);
+ if (s3c2410_udc_fifo_count_out())
+ goto handle_ep_again;
}
}
}
@@ -1890,6 +1896,7 @@
udc->vbus = 1;
}
+#ifdef CONFIG_USB_GADGET_DEBUG_FS
if (s3c2410_udc_debugfs_root) {
udc->regs_info = debugfs_create_file("registers", S_IRUGO,
s3c2410_udc_debugfs_root,
@@ -1897,6 +1904,7 @@
if (!udc->regs_info)
dev_warn(dev, "debugfs file creation failed\n");
}
+#endif
dev_dbg(dev, "probe ok\n");
@@ -2003,12 +2011,14 @@
dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
+#ifdef CONFIG_USB_GADGET_DEBUG_FS
s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
if (IS_ERR(s3c2410_udc_debugfs_root)) {
printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
s3c2410_udc_debugfs_root = NULL;
}
+#endif
retval = platform_driver_register(&udc_driver_2410);
if (retval)
--- a/drivers/usb/host/ohci-s3c2410.c
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -24,6 +24,7 @@
#include <mach/hardware.h>
#include <mach/usb-control.h>
+#include <mach/regs-gpio.h>
#define valid_port(idx) ((idx) == 1 || (idx) == 2)
@@ -308,6 +309,42 @@
local_irq_restore(flags);
}
+/* switching of USB pads */
+static ssize_t show_usb_mode(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ if (__raw_readl(S3C24XX_MISCCR) & S3C2410_MISCCR_USBHOST)
+ return sprintf(buf, "host\n");
+
+ return sprintf(buf, "device\n");
+}
+
+static ssize_t set_usb_mode(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ if (!strncmp(buf, "host", 4)) {
+ printk("s3c2410: changing usb to host\n");
+ s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST,
+ S3C2410_MISCCR_USBHOST);
+ /* FIXME:
+ * - call machine-specific disable-pullup function i
+ * - enable +Vbus (if hardware supports it)
+ */
+ s3c2410_gpio_setpin(S3C2410_GPB9, 0);
+ } else if (!strncmp(buf, "device", 6)) {
+ printk("s3c2410: changing usb to device\n");
+ s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST, 0);
+ s3c2410_gpio_setpin(S3C2410_GPB9, 1);
+ } else {
+ printk("s3c2410: unknown mode\n");
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR(usb_mode, S_IRUGO | S_IWUSR, show_usb_mode, set_usb_mode);
+
/* may be called without controller electrically present */
/* may be called with controller, bus, and devices active */
@@ -325,6 +362,7 @@
static void
usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev)
{
+ device_remove_file(&dev->dev, &dev_attr_usb_mode);
usb_remove_hcd(hcd);
s3c2410_stop_hc(dev);
iounmap(hcd->regs);
@@ -392,8 +430,15 @@
if (retval != 0)
goto err_ioremap;
+ retval = device_create_file(&dev->dev, &dev_attr_usb_mode);
+ if (retval != 0)
+ goto err_hcd;
+
return 0;
+ err_hcd:
+ usb_remove_hcd(hcd);
+
err_ioremap:
s3c2410_stop_hc(dev);
iounmap(hcd->regs);
--- /dev/null
+++ b/drivers/video/backlight/gta01_bl.c
@@ -0,0 +1,269 @@
+/*
+ * Backlight Driver for FIC GTA01 (Neo1973) GSM Phone
+ *
+ * Copyright (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * based on corgi_cl.c, Copyright (c) 2004-2006 Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Javi Roman <javiroman@kernel-labs.org>:
+ * implement PWM, instead of simple on/off switching
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/fb.h>
+#include <linux/backlight.h>
+#include <linux/clk.h>
+
+#include <mach/hardware.h>
+#include <mach/gta01.h>
+#include <mach/pwm.h>
+
+#include <plat/regs-timer.h>
+#include <asm/plat-s3c24xx/neo1973.h>
+
+static struct backlight_properties gta01bl_prop;
+static struct backlight_device *gta01_backlight_device;
+static struct gta01bl_machinfo *bl_machinfo;
+
+static unsigned long gta01bl_flags;
+
+struct gta01bl_data {
+ int intensity;
+ struct mutex mutex;
+ struct clk *clk;
+ struct s3c2410_pwm pwm;
+};
+
+static struct gta01bl_data gta01bl;
+
+static int gta01bl_defer_resume_backlight;
+
+#define GTA01BL_SUSPENDED 0x01
+#define GTA01BL_BATTLOW 0x02
+
+/* On the GTA01 / Neo1973, we use a 50 or 66MHz PCLK, which gives
+ * us a 6.25..8.25MHz DIV8 clock, which is further divided by a
+ * prescaler of 4, resulting in a 1.56..2.06MHz tick. This results in a
+ * minimum frequency of 24..31Hz. At 400Hz, we need to set the count
+ * to something like 3906..5156, providing us a way sufficient resolution
+ * for display brightness adjustment. */
+#define GTA01BL_COUNTER 5156
+
+static int gta01bl_send_intensity(struct backlight_device *bd)
+{
+ int intensity = bd->props.brightness;
+
+ if (bd->props.power != FB_BLANK_UNBLANK)
+ intensity = 0;
+ if (bd->props.fb_blank != FB_BLANK_UNBLANK)
+ intensity = 0;
+ if (gta01bl_flags & GTA01BL_SUSPENDED)
+ intensity = 0;
+ if (gta01bl_flags & GTA01BL_BATTLOW)
+ intensity &= bl_machinfo->limit_mask;
+
+ mutex_lock(&gta01bl.mutex);
+#ifdef GTA01_BACKLIGHT_ONOFF_ONLY
+ if (intensity)
+ neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
+ else
+ neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 0);
+#else
+ if (intensity == bd->props.max_brightness) {
+ neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
+ s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
+ } else {
+ s3c2410_pwm_duty_cycle(intensity & 0xffff, &gta01bl.pwm);
+ s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPB0_TOUT0);
+ }
+#endif
+ mutex_unlock(&gta01bl.mutex);
+
+ gta01bl.intensity = intensity;
+ return 0;
+}
+
+static int gta01bl_init_hw(void)
+{
+ int rc;
+
+ rc = s3c2410_pwm_init(&gta01bl.pwm);
+ if (rc)
+ return rc;
+
+ gta01bl.pwm.timerid = PWM0;
+ gta01bl.pwm.prescaler = (4 - 1);
+ gta01bl.pwm.divider = S3C2410_TCFG1_MUX0_DIV8;
+ gta01bl.pwm.counter = GTA01BL_COUNTER;
+ gta01bl.pwm.comparer = gta01bl.pwm.counter;
+
+ rc = s3c2410_pwm_enable(&gta01bl.pwm);
+ if (rc)
+ return rc;
+
+ s3c2410_pwm_start(&gta01bl.pwm);
+
+ gta01bl_prop.max_brightness = gta01bl.pwm.counter;
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int gta01bl_suspend(struct platform_device *dev, pm_message_t state)
+{
+ gta01bl_flags |= GTA01BL_SUSPENDED;
+ gta01bl_send_intensity(gta01_backlight_device);
+ neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 0);
+ s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
+ return 0;
+}
+
+void gta01bl_deferred_resume(void)
+{
+ mutex_lock(&gta01bl.mutex);
+ gta01bl_init_hw();
+ mutex_unlock(&gta01bl.mutex);
+
+ gta01bl_flags &= ~GTA01BL_SUSPENDED;
+ gta01bl_send_intensity(gta01_backlight_device);
+}
+EXPORT_SYMBOL_GPL(gta01bl_deferred_resume);
+
+static int gta01bl_resume(struct platform_device *dev)
+{
+ if (!gta01bl_defer_resume_backlight)
+ gta01bl_deferred_resume();
+ return 0;
+}
+#else
+#define gta01bl_suspend NULL
+#define gta01bl_resume NULL
+#endif
+
+static int gta01bl_get_intensity(struct backlight_device *bd)
+{
+ return gta01bl.intensity;
+}
+
+static int gta01bl_set_intensity(struct backlight_device *bd)
+{
+ gta01bl_send_intensity(gta01_backlight_device);
+ return 0;
+}
+
+/*
+ * Called when the battery is low to limit the backlight intensity.
+ * If limit==0 clear any limit, otherwise limit the intensity
+ */
+void gta01bl_limit_intensity(int limit)
+{
+ if (limit)
+ gta01bl_flags |= GTA01BL_BATTLOW;
+ else
+ gta01bl_flags &= ~GTA01BL_BATTLOW;
+ gta01bl_send_intensity(gta01_backlight_device);
+}
+EXPORT_SYMBOL_GPL(gta01bl_limit_intensity);
+
+
+static struct backlight_ops gta01bl_ops = {
+ .get_brightness = gta01bl_get_intensity,
+ .update_status = gta01bl_set_intensity,
+};
+
+static int __init gta01bl_probe(struct platform_device *pdev)
+{
+ struct gta01bl_machinfo *machinfo = pdev->dev.platform_data;
+ int rc;
+
+#ifdef GTA01_BACKLIGHT_ONOFF_ONLY
+ s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
+ gta01bl_prop.max_brightness = 1;
+#else
+ rc = gta01bl_init_hw();
+ if (rc < 0)
+ return rc;
+#endif
+ mutex_init(&gta01bl.mutex);
+
+ if (!machinfo->limit_mask)
+ machinfo->limit_mask = -1;
+
+ gta01bl_defer_resume_backlight = machinfo->defer_resume_backlight;
+
+ gta01_backlight_device = backlight_device_register("gta01-bl",
+ &pdev->dev, NULL,
+ &gta01bl_ops);
+ if (IS_ERR(gta01_backlight_device))
+ return PTR_ERR(gta01_backlight_device);
+
+ gta01bl_prop.power = FB_BLANK_UNBLANK;
+ gta01bl_prop.brightness = gta01bl_prop.max_brightness;
+ memcpy(&gta01_backlight_device->props,
+ &gta01bl_prop, sizeof(gta01bl_prop));
+ gta01bl_send_intensity(gta01_backlight_device);
+
+ return 0;
+}
+
+static int gta01bl_remove(struct platform_device *dev)
+{
+#ifndef GTA01_BACKLIGHT_ONOFF_ONLY
+ s3c2410_pwm_disable(&gta01bl.pwm);
+#endif
+ backlight_device_unregister(gta01_backlight_device);
+ mutex_destroy(&gta01bl.mutex);
+
+ s3c2410_gpio_cfgpin(GTA01_GPIO_BACKLIGHT, S3C2410_GPIO_OUTPUT);
+ neo1973_gpb_setpin(GTA01_GPIO_BACKLIGHT, 1);
+
+ return 0;
+}
+
+static struct platform_driver gta01bl_driver = {
+ .probe = gta01bl_probe,
+ .remove = gta01bl_remove,
+ .suspend = gta01bl_suspend,
+ .resume = gta01bl_resume,
+ .driver = {
+ .name = "gta01-bl",
+ },
+};
+
+static int __init gta01bl_init(void)
+{
+ return platform_driver_register(&gta01bl_driver);
+}
+
+static void __exit gta01bl_exit(void)
+{
+ platform_driver_unregister(&gta01bl_driver);
+}
+
+module_init(gta01bl_init);
+module_exit(gta01bl_exit);
+
+MODULE_DESCRIPTION("FIC GTA01 (Neo1973) Backlight Driver");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -152,6 +152,13 @@
the PWL module of OMAP1 processors. Say Y if your board
uses this hardware.
+config BACKLIGHT_GTA01
+ tristate "FIC Neo1973 GTA01 Backlight Driver"
+ depends on BACKLIGHT_CLASS_DEVICE && MACH_NEO1973_GTA01
+ default y
+ help
+ If you have a FIC Neo1973 GTA01, say y to enable the backlight driver.
+
config BACKLIGHT_HP680
tristate "HP Jornada 680 Backlight Driver"
depends on BACKLIGHT_CLASS_DEVICE && SH_HP6XX
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
obj-$(CONFIG_BACKLIGHT_ATMEL_PWM) += atmel-pwm-bl.o
obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o
+obj-$(CONFIG_BACKLIGHT_GTA01) += gta01_bl.o
obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -401,6 +401,9 @@
int c;
int mode;
+ if (info->state != FBINFO_STATE_RUNNING)
+ return;
+
acquire_console_sem();
if (ops && ops->currcon != -1)
vc = vc_cons[ops->currcon].d;
@@ -3225,13 +3228,17 @@
static int fbcon_event_notify(struct notifier_block *self,
unsigned long action, void *data)
{
- struct fb_event *event = data;
- struct fb_info *info = event->info;
+ struct fb_event *event;
+ struct fb_info *info;
struct fb_videomode *mode;
struct fb_con2fbmap *con2fb;
struct fb_blit_caps *caps;
int ret = 0;
+ printk(KERN_INFO "fbcon_event_notify action=%ld, data=%p\n", action, data);
+
+ event = data;
+ info = event->info;
/*
* ignore all events except driver registration and deregistration
* if fbcon is not active
--- /dev/null
+++ b/drivers/video/display/jbt6k74.c
@@ -0,0 +1,809 @@
+/* Linux kernel driver for the tpo JBT6K74-AS LCM ASIC
+ *
+ * Copyright (C) 2006-2007 by Openmoko, Inc.
+ * Author: Harald Welte <laforge@openmoko.org>,
+ * Stefan Schmidt <stefan@openmoko.org>
+ * Copyright (C) 2008 by Harald Welte <laforge@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/jbt6k74.h>
+#include <linux/fb.h>
+
+enum jbt_register {
+ JBT_REG_SLEEP_IN = 0x10,
+ JBT_REG_SLEEP_OUT = 0x11,
+
+ JBT_REG_DISPLAY_OFF = 0x28,
+ JBT_REG_DISPLAY_ON = 0x29,
+
+ JBT_REG_RGB_FORMAT = 0x3a,
+ JBT_REG_QUAD_RATE = 0x3b,
+
+ JBT_REG_POWER_ON_OFF = 0xb0,
+ JBT_REG_BOOSTER_OP = 0xb1,
+ JBT_REG_BOOSTER_MODE = 0xb2,
+ JBT_REG_BOOSTER_FREQ = 0xb3,
+ JBT_REG_OPAMP_SYSCLK = 0xb4,
+ JBT_REG_VSC_VOLTAGE = 0xb5,
+ JBT_REG_VCOM_VOLTAGE = 0xb6,
+ JBT_REG_EXT_DISPL = 0xb7,
+ JBT_REG_OUTPUT_CONTROL = 0xb8,
+ JBT_REG_DCCLK_DCEV = 0xb9,
+ JBT_REG_DISPLAY_MODE1 = 0xba,
+ JBT_REG_DISPLAY_MODE2 = 0xbb,
+ JBT_REG_DISPLAY_MODE = 0xbc,
+ JBT_REG_ASW_SLEW = 0xbd,
+ JBT_REG_DUMMY_DISPLAY = 0xbe,
+ JBT_REG_DRIVE_SYSTEM = 0xbf,
+
+ JBT_REG_SLEEP_OUT_FR_A = 0xc0,
+ JBT_REG_SLEEP_OUT_FR_B = 0xc1,
+ JBT_REG_SLEEP_OUT_FR_C = 0xc2,
+ JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
+ JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
+ JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
+ JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
+
+ JBT_REG_GAMMA1_FINE_1 = 0xc7,
+ JBT_REG_GAMMA1_FINE_2 = 0xc8,
+ JBT_REG_GAMMA1_INCLINATION = 0xc9,
+ JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
+
+ /* VGA */
+ JBT_REG_BLANK_CONTROL = 0xcf,
+ JBT_REG_BLANK_TH_TV = 0xd0,
+ JBT_REG_CKV_ON_OFF = 0xd1,
+ JBT_REG_CKV_1_2 = 0xd2,
+ JBT_REG_OEV_TIMING = 0xd3,
+ JBT_REG_ASW_TIMING_1 = 0xd4,
+ JBT_REG_ASW_TIMING_2 = 0xd5,
+
+ /* QVGA */
+ JBT_REG_BLANK_CONTROL_QVGA = 0xd6,
+ JBT_REG_BLANK_TH_TV_QVGA = 0xd7,
+ JBT_REG_CKV_ON_OFF_QVGA = 0xd8,
+ JBT_REG_CKV_1_2_QVGA = 0xd9,
+ JBT_REG_OEV_TIMING_QVGA = 0xde,
+ JBT_REG_ASW_TIMING_1_QVGA = 0xdf,
+ JBT_REG_ASW_TIMING_2_QVGA = 0xe0,
+
+
+ JBT_REG_HCLOCK_VGA = 0xec,
+ JBT_REG_HCLOCK_QVGA = 0xed,
+
+};
+
+enum jbt_state {
+ JBT_STATE_DEEP_STANDBY,
+ JBT_STATE_SLEEP,
+ JBT_STATE_NORMAL,
+ JBT_STATE_QVGA_NORMAL,
+};
+
+static const char *jbt_state_names[] = {
+ [JBT_STATE_DEEP_STANDBY] = "deep-standby",
+ [JBT_STATE_SLEEP] = "sleep",
+ [JBT_STATE_NORMAL] = "normal",
+ [JBT_STATE_QVGA_NORMAL] = "qvga-normal",
+};
+
+struct jbt_info {
+ enum jbt_state state, last_state;
+ struct spi_device *spi_dev;
+ struct mutex lock; /* protects tx_buf and reg_cache */
+ struct notifier_block fb_notif;
+ u16 tx_buf[8];
+ u16 reg_cache[0xEE];
+ int have_resumed;
+};
+
+#define JBT_COMMAND 0x000
+#define JBT_DATA 0x100
+
+
+static int jbt_reg_write_nodata(struct jbt_info *jbt, u8 reg)
+{
+ int rc;
+
+ mutex_lock(&jbt->lock);
+
+ jbt->tx_buf[0] = JBT_COMMAND | reg;
+ rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
+ 1*sizeof(u16));
+ if (rc == 0)
+ jbt->reg_cache[reg] = 0;
+ else
+ printk(KERN_ERR"jbt_reg_write_nodata spi_write ret %d\n",
+ rc);
+
+ mutex_unlock(&jbt->lock);
+
+ return rc;
+}
+
+
+static int jbt_reg_write(struct jbt_info *jbt, u8 reg, u8 data)
+{
+ int rc;
+
+ mutex_lock(&jbt->lock);
+
+ jbt->tx_buf[0] = JBT_COMMAND | reg;
+ jbt->tx_buf[1] = JBT_DATA | data;
+ rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
+ 2*sizeof(u16));
+ if (rc == 0)
+ jbt->reg_cache[reg] = data;
+ else
+ printk(KERN_ERR"jbt_reg_write spi_write ret %d\n", rc);
+
+ mutex_unlock(&jbt->lock);
+
+ return rc;
+}
+
+static int jbt_reg_write16(struct jbt_info *jbt, u8 reg, u16 data)
+{
+ int rc;
+
+ mutex_lock(&jbt->lock);
+
+ jbt->tx_buf[0] = JBT_COMMAND | reg;
+ jbt->tx_buf[1] = JBT_DATA | (data >> 8);
+ jbt->tx_buf[2] = JBT_DATA | (data & 0xff);
+
+ rc = spi_write(jbt->spi_dev, (u8 *)jbt->tx_buf,
+ 3*sizeof(u16));
+ if (rc == 0)
+ jbt->reg_cache[reg] = data;
+ else
+ printk(KERN_ERR"jbt_reg_write16 spi_write ret %d\n", rc);
+
+ mutex_unlock(&jbt->lock);
+
+ return rc;
+}
+
+static int jbt_init_regs(struct jbt_info *jbt, int qvga)
+{
+ int rc;
+
+ dev_dbg(&jbt->spi_dev->dev, "entering %cVGA mode\n", qvga ? 'Q' : ' ');
+
+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE1, 0x01);
+ rc |= jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE2, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_RGB_FORMAT, 0x60);
+ rc |= jbt_reg_write(jbt, JBT_REG_DRIVE_SYSTEM, 0x10);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_OP, 0x56);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_MODE, 0x33);
+ rc |= jbt_reg_write(jbt, JBT_REG_BOOSTER_FREQ, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_OPAMP_SYSCLK, 0x02);
+ rc |= jbt_reg_write(jbt, JBT_REG_VSC_VOLTAGE, 0x2b);
+ rc |= jbt_reg_write(jbt, JBT_REG_VCOM_VOLTAGE, 0x40);
+ rc |= jbt_reg_write(jbt, JBT_REG_EXT_DISPL, 0x03);
+ rc |= jbt_reg_write(jbt, JBT_REG_DCCLK_DCEV, 0x04);
+ /*
+ * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
+ * to avoid red / blue flicker
+ */
+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_SLEW, 0x04);
+ rc |= jbt_reg_write(jbt, JBT_REG_DUMMY_DISPLAY, 0x00);
+
+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_A, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_B, 0x11);
+ rc |= jbt_reg_write(jbt, JBT_REG_SLEEP_OUT_FR_C, 0x11);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
+ rc |= jbt_reg_write16(jbt, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
+
+ rc |= jbt_reg_write16(jbt, JBT_REG_GAMMA1_FINE_1, 0x5533);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_FINE_2, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_INCLINATION, 0x00);
+ rc |= jbt_reg_write(jbt, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
+
+ if (!qvga) {
+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_VGA, 0x1f0);
+ rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL, 0x02);
+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV, 0x0804);
+
+ rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF, 0x01);
+ rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2, 0x0000);
+
+ rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING, 0x0d0e);
+ rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1, 0x11a4);
+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2, 0x0e);
+ } else {
+ rc |= jbt_reg_write16(jbt, JBT_REG_HCLOCK_QVGA, 0x00ff);
+ rc |= jbt_reg_write(jbt, JBT_REG_BLANK_CONTROL_QVGA, 0x02);
+ rc |= jbt_reg_write16(jbt, JBT_REG_BLANK_TH_TV_QVGA, 0x0804);
+
+ rc |= jbt_reg_write(jbt, JBT_REG_CKV_ON_OFF_QVGA, 0x01);
+ rc |= jbt_reg_write16(jbt, JBT_REG_CKV_1_2_QVGA, 0x0008);
+
+ rc |= jbt_reg_write16(jbt, JBT_REG_OEV_TIMING_QVGA, 0x050a);
+ rc |= jbt_reg_write16(jbt, JBT_REG_ASW_TIMING_1_QVGA, 0x0a19);
+ rc |= jbt_reg_write(jbt, JBT_REG_ASW_TIMING_2_QVGA, 0x0a);
+ }
+
+ return rc ? -EIO : 0;
+}
+
+static int standby_to_sleep(struct jbt_info *jbt)
+{
+ int rc;
+
+ /* three times command zero */
+ rc = jbt_reg_write_nodata(jbt, 0x00);
+ mdelay(1);
+ rc |= jbt_reg_write_nodata(jbt, 0x00);
+ mdelay(1);
+ rc |= jbt_reg_write_nodata(jbt, 0x00);
+ mdelay(1);
+
+ /* deep standby out */
+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x17);
+
+ return rc ? -EIO : 0;
+}
+
+static int sleep_to_normal(struct jbt_info *jbt)
+{
+ int rc;
+
+ /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x80);
+
+ /* Quad mode off */
+ rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x00);
+
+ /* AVDD on, XVDD on */
+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
+
+ /* Output control */
+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
+
+ /* Sleep mode off */
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
+
+ /* initialize register set */
+ rc |= jbt_init_regs(jbt, 0);
+
+ /* Turn on display */
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
+
+ return rc ? -EIO : 0;
+}
+
+static int sleep_to_qvga_normal(struct jbt_info *jbt)
+{
+ int rc;
+
+ /* RGB I/F on, RAM wirte off, QVGA through, SIGCON enable */
+ rc = jbt_reg_write(jbt, JBT_REG_DISPLAY_MODE, 0x81);
+
+ /* Quad mode on */
+ rc |= jbt_reg_write(jbt, JBT_REG_QUAD_RATE, 0x22);
+
+ /* AVDD on, XVDD on */
+ rc |= jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x16);
+
+ /* Output control */
+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0xfff9);
+
+ /* Sleep mode off */
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_OUT);
+
+ /* initialize register set for qvga*/
+ rc |= jbt_init_regs(jbt, 1);
+
+ /* Turn on display */
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_ON);
+
+ return rc ? -EIO : 0;
+}
+
+static int normal_to_sleep(struct jbt_info *jbt)
+{
+ int rc;
+
+ rc = jbt_reg_write_nodata(jbt, JBT_REG_DISPLAY_OFF);
+ rc |= jbt_reg_write16(jbt, JBT_REG_OUTPUT_CONTROL, 0x8002);
+ rc |= jbt_reg_write_nodata(jbt, JBT_REG_SLEEP_IN);
+
+ return rc ? -EIO : 0;
+}
+
+static int sleep_to_standby(struct jbt_info *jbt)
+{
+ return jbt_reg_write(jbt, JBT_REG_POWER_ON_OFF, 0x00);
+}
+
+/* frontend function */
+int jbt6k74_enter_state(struct jbt_info *jbt, enum jbt_state new_state)
+{
+ int rc = -EINVAL;
+
+ dev_dbg(&jbt->spi_dev->dev, "entering (old_state=%u, "
+ "new_state=%u)\n", jbt->state, new_state);
+
+ switch (jbt->state) {
+ case JBT_STATE_DEEP_STANDBY:
+ switch (new_state) {
+ case JBT_STATE_DEEP_STANDBY:
+ rc = 0;
+ break;
+ case JBT_STATE_SLEEP:
+ rc = standby_to_sleep(jbt);
+ break;
+ case JBT_STATE_NORMAL:
+ /* first transition into sleep */
+ rc = standby_to_sleep(jbt);
+ /* then transition into normal */
+ rc |= sleep_to_normal(jbt);
+ break;
+ case JBT_STATE_QVGA_NORMAL:
+ /* first transition into sleep */
+ rc = standby_to_sleep(jbt);
+ /* then transition into normal */
+ rc |= sleep_to_qvga_normal(jbt);
+ break;
+ }
+ break;
+ case JBT_STATE_SLEEP:
+ switch (new_state) {
+ case JBT_STATE_SLEEP:
+ rc = 0;
+ break;
+ case JBT_STATE_DEEP_STANDBY:
+ rc = sleep_to_standby(jbt);
+ break;
+ case JBT_STATE_NORMAL:
+ rc = sleep_to_normal(jbt);
+ break;
+ case JBT_STATE_QVGA_NORMAL:
+ rc = sleep_to_qvga_normal(jbt);
+ break;
+ }
+ break;
+ case JBT_STATE_NORMAL:
+ switch (new_state) {
+ case JBT_STATE_NORMAL:
+ rc = 0;
+ break;
+ case JBT_STATE_DEEP_STANDBY:
+ /* first transition into sleep */
+ rc = normal_to_sleep(jbt);
+ /* then transition into deep standby */
+ rc |= sleep_to_standby(jbt);
+ break;
+ case JBT_STATE_SLEEP:
+ rc = normal_to_sleep(jbt);
+ break;
+ case JBT_STATE_QVGA_NORMAL:
+ /* first transition into sleep */
+ rc = normal_to_sleep(jbt);
+ /* second transition into deep standby */
+ rc |= sleep_to_standby(jbt);
+ /* third transition into sleep */
+ rc |= standby_to_sleep(jbt);
+ /* fourth transition into normal */
+ rc |= sleep_to_qvga_normal(jbt);
+ break;
+ }
+ break;
+ case JBT_STATE_QVGA_NORMAL:
+ switch (new_state) {
+ case JBT_STATE_QVGA_NORMAL:
+ rc = 0;
+ break;
+ case JBT_STATE_DEEP_STANDBY:
+ /* first transition into sleep */
+ rc = normal_to_sleep(jbt);
+ /* then transition into deep standby */
+ rc |= sleep_to_standby(jbt);
+ break;
+ case JBT_STATE_SLEEP:
+ rc = normal_to_sleep(jbt);
+ break;
+ case JBT_STATE_NORMAL:
+ /* first transition into sleep */
+ rc = normal_to_sleep(jbt);
+ /* second transition into deep standby */
+ rc |= sleep_to_standby(jbt);
+ /* third transition into sleep */
+ rc |= standby_to_sleep(jbt);
+ /* fourth transition into normal */
+ rc |= sleep_to_normal(jbt);
+ break;
+ }
+ break;
+ }
+
+ if (rc == 0)
+ jbt->state = new_state;
+
+ return rc;
+}
+EXPORT_SYMBOL_GPL(jbt6k74_enter_state);
+
+static ssize_t state_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct jbt_info *jbt = dev_get_drvdata(dev);
+
+ if (jbt->state >= ARRAY_SIZE(jbt_state_names))
+ return -EIO;
+
+ return sprintf(buf, "%s\n", jbt_state_names[jbt->state]);
+}
+
+static ssize_t state_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct jbt_info *jbt = dev_get_drvdata(dev);
+ int i, rc;
+
+ for (i = 0; i < ARRAY_SIZE(jbt_state_names); i++) {
+ if (!strncmp(buf, jbt_state_names[i],
+ strlen(jbt_state_names[i]))) {
+ rc = jbt6k74_enter_state(jbt, i);
+ if (rc)
+ return rc;
+ return count;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static DEVICE_ATTR(state, 0644, state_read, state_write);
+
+static int reg_by_string(const char *name)
+{
+ if (!strcmp(name, "gamma_fine1"))
+ return JBT_REG_GAMMA1_FINE_1;
+ else if (!strcmp(name, "gamma_fine2"))
+ return JBT_REG_GAMMA1_FINE_2;
+ else if (!strcmp(name, "gamma_inclination"))
+ return JBT_REG_GAMMA1_INCLINATION;
+ else
+ return JBT_REG_GAMMA1_BLUE_OFFSET;
+}
+
+static ssize_t gamma_read(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct jbt_info *jbt = dev_get_drvdata(dev);
+ int reg = reg_by_string(attr->attr.name);
+ u16 val;
+
+ mutex_lock(&jbt->lock);
+ val = jbt->reg_cache[reg];
+ mutex_unlock(&jbt->lock);
+
+ return sprintf(buf, "0x%04x\n", val);
+}
+
+static ssize_t gamma_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct jbt_info *jbt = dev_get_drvdata(dev);
+ int reg = reg_by_string(attr->attr.name);
+ unsigned long val = simple_strtoul(buf, NULL, 10);
+
+ dev_info(dev, "**** jbt6k74 writing gama %lu\n", val & 0xff);
+
+ jbt_reg_write(jbt, reg, val & 0xff);
+
+ return count;
+}
+
+static ssize_t reset_write(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct jbt_info *jbt = dev_get_drvdata(dev);
+ struct jbt6k74_platform_data *jbt6k74_pdata = jbt->spi_dev->dev.platform_data;
+ int rc;
+
+ dev_info(dev, "**** jbt6k74 reset\n");
+
+ /* hard reset the jbt6k74 */
+
+ (jbt6k74_pdata->reset)(0, 0);
+ mdelay(1);
+ (jbt6k74_pdata->reset)(0, 1);
+ mdelay(120);
+
+ rc = jbt_reg_write_nodata(jbt, 0x01);
+ if (rc < 0)
+ dev_err(dev, "cannot soft reset\n");
+
+ mdelay(120);
+
+ jbt->state = JBT_STATE_DEEP_STANDBY;
+
+ switch (jbt->last_state) {
+ case JBT_STATE_QVGA_NORMAL:
+ jbt6k74_enter_state(jbt, JBT_STATE_QVGA_NORMAL);
+ break;
+ default:
+ jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
+ break;
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR(gamma_fine1, 0644, gamma_read, gamma_write);
+static DEVICE_ATTR(gamma_fine2, 0644, gamma_read, gamma_write);
+static DEVICE_ATTR(gamma_inclination, 0644, gamma_read, gamma_write);
+static DEVICE_ATTR(gamma_blue_offset, 0644, gamma_read, gamma_write);
+static DEVICE_ATTR(reset, 0600, NULL, reset_write);
+
+static struct attribute *jbt_sysfs_entries[] = {
+ &dev_attr_state.attr,
+ &dev_attr_gamma_fine1.attr,
+ &dev_attr_gamma_fine2.attr,
+ &dev_attr_gamma_inclination.attr,
+ &dev_attr_gamma_blue_offset.attr,
+ &dev_attr_reset.attr,
+ NULL,
+};
+
+static struct attribute_group jbt_attr_group = {
+ .name = NULL,
+ .attrs = jbt_sysfs_entries,
+};
+
+static int fb_notifier_callback(struct notifier_block *self,
+ unsigned long event, void *data)
+{
+ struct jbt_info *jbt;
+ struct fb_event *evdata = data;
+ int fb_blank;
+
+ if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
+ return 0;
+
+ fb_blank = *(int *)evdata->data;
+ jbt = container_of(self, struct jbt_info, fb_notif);
+
+ switch (fb_blank) {
+ case FB_BLANK_UNBLANK:
+ dev_info(&jbt->spi_dev->dev, "**** jbt6k74 unblank\n");
+ jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
+ break;
+ case FB_BLANK_NORMAL:
+ dev_info(&jbt->spi_dev->dev, "**** jbt6k74 normal\n");
+ break;
+ case FB_BLANK_VSYNC_SUSPEND:
+ dev_info(&jbt->spi_dev->dev, "**** jbt6k74 vsync suspend\n");
+ break;
+ case FB_BLANK_HSYNC_SUSPEND:
+ dev_info(&jbt->spi_dev->dev, "**** jbt6k74 hsync suspend\n");
+ /* FIXME: we disable SLEEP since it would result in
+ * a visible artefact (white screen) before the backlight
+ * is dimmed to a dark enough level */
+ /* jbt6k74_enter_state(jbt, JBT_STATE_SLEEP); */
+ break;
+ case FB_BLANK_POWERDOWN:
+ dev_info(&jbt->spi_dev->dev, "**** jbt6k74 powerdown\n");
+ /* FIXME: deep standby causes WSOD on certain devices. We use
+ * sleep as workaround */
+ jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
+ break;
+ }
+
+ return 0;
+}
+
+/* linux device model infrastructure */
+
+static int __devinit jbt_probe(struct spi_device *spi)
+{
+ int rc;
+ struct jbt_info *jbt;
+ struct jbt6k74_platform_data *jbt6k74_pdata = spi->dev.platform_data;
+
+ /* the controller doesn't have a MISO pin; we can't do detection */
+
+ spi->mode = SPI_CPOL | SPI_CPHA;
+ spi->bits_per_word = 9;
+
+ rc = spi_setup(spi);
+ if (rc < 0) {
+ dev_err(&spi->dev,
+ "error during spi_setup of jbt6k74 driver\n");
+ return rc;
+ }
+
+ jbt = kzalloc(sizeof(*jbt), GFP_KERNEL);
+ if (!jbt)
+ return -ENOMEM;
+
+ jbt->spi_dev = spi;
+ jbt->state = JBT_STATE_DEEP_STANDBY;
+ mutex_init(&jbt->lock);
+
+ dev_set_drvdata(&spi->dev, jbt);
+
+ /* hard reset the jbt6k74 */
+
+ (jbt6k74_pdata->reset)(0, 0);
+ mdelay(1);
+ (jbt6k74_pdata->reset)(0, 1);
+ mdelay(120);
+
+ rc = jbt_reg_write_nodata(jbt, 0x01);
+ if (rc < 0)
+ dev_err(&spi->dev, "cannot soft reset\n");
+
+ mdelay(120);
+
+
+ rc = jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
+ if (rc < 0) {
+ dev_err(&spi->dev, "cannot enter NORMAL state\n");
+ goto err_free_drvdata;
+ }
+
+ rc = sysfs_create_group(&spi->dev.kobj, &jbt_attr_group);
+ if (rc < 0) {
+ dev_err(&spi->dev, "cannot create sysfs group\n");
+ goto err_standby;
+ }
+
+ jbt->fb_notif.notifier_call = fb_notifier_callback;
+ rc = fb_register_client(&jbt->fb_notif);
+ if (rc < 0) {
+ dev_err(&spi->dev, "cannot register notifier\n");
+ goto err_sysfs;
+ }
+
+ if (jbt6k74_pdata->probe_completed)
+ jbt6k74_pdata->probe_completed(&spi->dev);
+
+ return 0;
+
+err_sysfs:
+ sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
+err_standby:
+ jbt6k74_enter_state(jbt, JBT_STATE_DEEP_STANDBY);
+err_free_drvdata:
+ dev_set_drvdata(&spi->dev, NULL);
+ kfree(jbt);
+
+ return rc;
+}
+
+static int __devexit jbt_remove(struct spi_device *spi)
+{
+ struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
+
+ /* We don't want to switch off the display in case the user
+ * accidentially onloads the module (whose use count normally is 0) */
+
+ fb_unregister_client(&jbt->fb_notif);
+ sysfs_remove_group(&spi->dev.kobj, &jbt_attr_group);
+ dev_set_drvdata(&spi->dev, NULL);
+ kfree(jbt);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int jbt_suspend(struct spi_device *spi, pm_message_t state)
+{
+ struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
+
+ /* Save mode for resume */
+ jbt->last_state = jbt->state;
+ /* FIXME: deep standby causes WSOD on certain devices. We use
+ * sleep as workaround */
+ jbt6k74_enter_state(jbt, JBT_STATE_SLEEP);
+
+ jbt->have_resumed = 0;
+
+ dev_info(&spi->dev, "**** jbt6k74 suspend end\n");
+
+ return 0;
+}
+
+int jbt6k74_resume(struct spi_device *spi)
+{
+ struct jbt_info *jbt = dev_get_drvdata(&spi->dev);
+ struct jbt6k74_platform_data *jbt6k74_pdata = spi->dev.platform_data;
+ int rc;
+
+ dev_info(&spi->dev, "**** jbt6k74 resume start\n");
+
+ /* hard reset the jbt6k74 */
+
+ (jbt6k74_pdata->reset)(0, 0);
+ mdelay(1);
+ (jbt6k74_pdata->reset)(0, 1);
+ mdelay(120);
+
+ rc = jbt_reg_write_nodata(jbt, 0x01);
+ if (rc < 0)
+ dev_err(&spi->dev, "cannot soft reset\n");
+
+ mdelay(120);
+
+ jbt->state = JBT_STATE_DEEP_STANDBY;
+
+ switch (jbt->last_state) {
+ case JBT_STATE_QVGA_NORMAL:
+ jbt6k74_enter_state(jbt, JBT_STATE_QVGA_NORMAL);
+ break;
+ default:
+ jbt6k74_enter_state(jbt, JBT_STATE_NORMAL);
+ break;
+ }
+
+ if (jbt6k74_pdata->resuming)
+ (jbt6k74_pdata->resuming)(0);
+
+ dev_info(&spi->dev, "**** jbt6k74 resume end\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(jbt6k74_resume);
+
+#else
+#define jbt_suspend NULL
+#define jbt_resume NULL
+#endif
+
+static struct spi_driver jbt6k74_driver = {
+ .driver = {
+ .name = "jbt6k74",
+ .owner = THIS_MODULE,
+ },
+
+ .probe = jbt_probe,
+ .remove = __devexit_p(jbt_remove),
+ .suspend = jbt_suspend,
+ .resume = jbt6k74_resume,
+};
+
+static int __init jbt_init(void)
+{
+ return spi_register_driver(&jbt6k74_driver);
+}
+
+static void __exit jbt_exit(void)
+{
+ spi_unregister_driver(&jbt6k74_driver);
+}
+
+MODULE_DESCRIPTION("SPI driver for tpo JBT6K74-AS LCM control interface");
+MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
+MODULE_LICENSE("GPL");
+
+module_init(jbt_init);
+module_exit(jbt_exit);
--- a/drivers/video/display/Kconfig
+++ b/drivers/video/display/Kconfig
@@ -21,4 +21,15 @@
comment "Display hardware drivers"
depends on DISPLAY_SUPPORT
+config DISPLAY_JBT6K74
+ tristate "TPO JBT6K74-AS TFT display ASIC control interface"
+ depends on SPI_MASTER && SYSFS
+ help
+ SPI driver for the control interface of TFT panels containing
+ the TPO JBT6K74-AS controller ASIC, such as the TPO TD028TTEC1
+ TFT diplay module used in the FIC/Openmoko Neo1973 GSM phones.
+
+ The control interface is required for display operation, as it
+ controls power management, display timing and gamma calibration.
+
endmenu
--- a/drivers/video/display/Makefile
+++ b/drivers/video/display/Makefile
@@ -3,4 +3,5 @@
display-objs := display-sysfs.o
obj-$(CONFIG_DISPLAY_SUPPORT) += display.o
+obj-$(CONFIG_DISPLAY_JBT6K74) += jbt6k74.o
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1918,6 +1918,30 @@
depends on FB_TMIO
default y
+config FB_S3C
+ tristate "Samsung S3C framebuffer support"
+ depends on FB && ARCH_S3C64XX
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ ---help---
+ Frame buffer driver for the built-in FB controller in the Samsung
+ SoC line from the S3C2443 onwards, including the S3C2416, S3C2450,
+ and the S3C64XX series such as the S3C6400 and S3C6410.
+
+ These chips all have the same basic framebuffer design with the
+ actual capabilities depending on the chip. For instance the S3C6400
+ and S3C6410 support 4 hardware windows whereas the S3C24XX series
+ currently only have two.
+
+ Currently the support is only for the S3C6400 and S3C6410 SoCs.
+
+config FB_S3C_DEBUG_REGWRITE
+ bool "Debug register writes"
+ depends on FB_S3C
+ ---help---
+ Show all register writes via printk(KERN_DEBUG)
+
config FB_S3C2410
tristate "S3C2410 LCD framebuffer support"
depends on FB && ARCH_S3C2410
--- a/drivers/video/logo/Kconfig
+++ b/drivers/video/logo/Kconfig
@@ -77,6 +77,11 @@
depends on SUPERH
default y
+config LOGO_OPENMOKO_CLUT224
+ bool "224-color Openmoko Linux logo"
+ depends on MACH_NEO1973_GTA01 || MACH_NEO1973_GTA02
+ default y
+
config LOGO_M32R_CLUT224
bool "224-color M32R Linux logo"
depends on M32R
--- a/drivers/video/logo/logo.c
+++ b/drivers/video/logo/logo.c
@@ -35,6 +35,7 @@
extern const struct linux_logo logo_superh_vga16;
extern const struct linux_logo logo_superh_clut224;
extern const struct linux_logo logo_m32r_clut224;
+extern const struct linux_logo logo_openmoko_clut224;
static int nologo;
module_param(nologo, bool, 0);
@@ -115,6 +116,10 @@
/* M32R Linux logo */
logo = &logo_m32r_clut224;
#endif
+#ifdef CONFIG_LOGO_OPENMOKO_CLUT224
+ /* Openmoko Linux logo */
+ logo = &logo_openmoko_clut224;
+#endif
}
return logo;
}
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+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
--- a/drivers/video/logo/Makefile
+++ b/drivers/video/logo/Makefile
@@ -15,6 +15,7 @@
obj-$(CONFIG_LOGO_SUPERH_VGA16) += logo_superh_vga16.o
obj-$(CONFIG_LOGO_SUPERH_CLUT224) += logo_superh_clut224.o
obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o
+obj-$(CONFIG_LOGO_OPENMOKO_CLUT224) += logo_openmoko_clut224.o
obj-$(CONFIG_SPU_BASE) += logo_spe_clut224.o
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -109,6 +109,7 @@
obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
obj-$(CONFIG_FB_SH7760) += sh7760fb.o
obj-$(CONFIG_FB_IMX) += imxfb.o
+obj-$(CONFIG_FB_S3C) += s3c-fb.o
obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
obj-$(CONFIG_FB_COBALT) += cobalt_lcdfb.o
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -1017,6 +1017,8 @@
s3c2410fb_init_registers(fbinfo);
+ s3c2410fb_set_par(fbinfo);
+
return 0;
}
--- /dev/null
+++ b/drivers/video/s3c-fb.c
@@ -0,0 +1,1036 @@
+/* linux/drivers/video/s3c-fb.c
+ *
+ * Copyright 2008 Openmoko Inc.
+ * Copyright 2008 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ * http://armlinux.simtec.co.uk/
+ *
+ * Samsung SoC Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/gfp.h>
+#include <linux/clk.h>
+#include <linux/fb.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <plat/fb.h>
+
+/* This driver will export a number of framebuffer interfaces depending
+ * on the configuration passed in via the platform data. Each fb instance
+ * maps to a hardware window. Currently there is no support for runtime
+ * setting of the alpha-blending functions that each window has, so only
+ * window 0 is actually useful.
+ *
+ * Window 0 is treated specially, it is used for the basis of the LCD
+ * output timings and as the control for the output power-down state.
+*/
+
+/* note, some of the functions that get called are derived from including
+ * <mach/regs-fb.h> as they are specific to the architecture that the code
+ * is being built for.
+*/
+
+#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
+#undef writel
+#define writel(v, r) do { \
+ printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
+ __raw_writel(v, r); } while(0)
+#endif /* FB_S3C_DEBUG_REGWRITE */
+
+struct s3c_fb;
+
+/**
+ * struct s3c_fb_win - per window private data for each framebuffer.
+ * @windata: The platform data supplied for the window configuration.
+ * @parent: The hardware that this window is part of.
+ * @fbinfo: Pointer pack to the framebuffer info for this window.
+ * @palette_buffer: Buffer/cache to hold palette entries.
+ * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
+ * @index: The window number of this window.
+ * @palette: The bitfields for changing r/g/b into a hardware palette entry.
+ */
+struct s3c_fb_win {
+ struct s3c_fb_pd_win *windata;
+ struct s3c_fb *parent;
+ struct fb_info *fbinfo;
+ struct s3c_fb_palette palette;
+
+ u32 *palette_buffer;
+ u32 pseudo_palette[16];
+ unsigned int index;
+};
+
+/**
+ * struct s3c_fb - overall hardware state of the hardware
+ * @dev: The device that we bound to, for printing, etc.
+ * @regs_res: The resource we claimed for the IO registers.
+ * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
+ * @regs: The mapped hardware registers.
+ * @enabled: A bitmask of enabled hardware windows.
+ * @pdata: The platform configuration data passed with the device.
+ * @windows: The hardware windows that have been claimed.
+ */
+struct s3c_fb {
+ struct device *dev;
+ struct resource *regs_res;
+ struct clk *bus_clk;
+ void __iomem *regs;
+
+ unsigned char enabled;
+
+ struct s3c_fb_platdata *pdata;
+ struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
+};
+
+/**
+ * s3c_fb_win_has_palette() - determine if a mode has a palette
+ * @win: The window number being queried.
+ * @bpp: The number of bits per pixel to test.
+ *
+ * Work out if the given window supports palletised data at the specified bpp.
+ */
+static int s3c_fb_win_has_palette(unsigned int win, unsigned int bpp)
+{
+ return s3c_fb_win_pal_size(win) <= (1 << bpp);
+}
+
+/**
+ * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
+ * @var: The screen information to verify.
+ * @info: The framebuffer device.
+ *
+ * Framebuffer layer call to verify the given information and allow us to
+ * update various information depending on the hardware capabilities.
+ */
+static int s3c_fb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb_pd_win *windata = win->windata;
+ struct s3c_fb *sfb = win->parent;
+
+ dev_dbg(sfb->dev, "checking parameters\n");
+
+ var->xres_virtual = max((unsigned int)windata->virtual_x, var->xres);
+ var->yres_virtual = max((unsigned int)windata->virtual_y, var->yres);
+
+ if (!s3c_fb_validate_win_bpp(win->index, var->bits_per_pixel)) {
+ dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
+ win->index, var->bits_per_pixel);
+ return -EINVAL;
+ }
+
+ /* always ensure these are zero, for drop through cases below */
+ var->transp.offset = 0;
+ var->transp.length = 0;
+
+ switch (var->bits_per_pixel) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ if (!s3c_fb_win_has_palette(win->index, var->bits_per_pixel)) {
+ /* non palletised, A:1,R:2,G:3,B:2 mode */
+ var->red.offset = 4;
+ var->green.offset = 2;
+ var->blue.offset = 0;
+ var->red.length = 5;
+ var->green.length = 3;
+ var->blue.length = 2;
+ var->transp.offset = 7;
+ var->transp.length = 1;
+ } else {
+ var->red.offset = 0;
+ var->red.length = var->bits_per_pixel;
+ var->green = var->red;
+ var->blue = var->red;
+ }
+ break;
+
+ case 19:
+ /* 666 with one bit alpha/transparency */
+ var->transp.offset = 18;
+ var->transp.length = 1;
+ case 18:
+ var->bits_per_pixel = 32;
+
+ /* 666 format */
+ var->red.offset = 12;
+ var->green.offset = 6;
+ var->blue.offset = 0;
+ var->red.length = 6;
+ var->green.length = 6;
+ var->blue.length = 6;
+ break;
+
+ case 16:
+ /* 16 bpp, 565 format */
+ var->red.offset = 11;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->red.length = 5;
+ var->green.length = 6;
+ var->blue.length = 5;
+ break;
+
+ case 28:
+ case 25:
+ var->transp.length = var->bits_per_pixel - 24;
+ var->transp.offset = 24;
+ /* drop through */
+ case 24:
+ /* our 24bpp is unpacked, so 32bpp */
+ var->bits_per_pixel = 32;
+ case 32:
+ var->red.offset = 16;
+ var->red.length = 8;
+ var->green.offset = 8;
+ var->green.length = 8;
+ var->blue.offset = 0;
+ var->blue.length = 8;
+ break;
+
+ default:
+ dev_err(sfb->dev, "invalid bpp\n");
+ }
+
+ dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
+ return 0;
+}
+
+/**
+ * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
+ * @sfb: The hardware state.
+ * @pixclock: The pixel clock wanted, in picoseconds.
+ *
+ * Given the specified pixel clock, work out the necessary divider to get
+ * close to the output frequency.
+ */
+static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
+{
+ unsigned long clk = clk_get_rate(sfb->bus_clk);
+ unsigned long long tmp;
+ unsigned int result;
+
+ tmp = (unsigned long long)clk;
+ tmp *= pixclk;
+
+ do_div(tmp, 1000000000UL);
+ result = (unsigned int)tmp / 1000;
+
+ dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
+ pixclk, clk, result, clk / result);
+
+ return result;
+}
+
+/**
+ * s3c_fb_align_word() - align pixel count to word boundary
+ * @bpp: The number of bits per pixel
+ * @pix: The value to be aligned.
+ *
+ * Align the given pixel count so that it will start on an 32bit word
+ * boundary.
+ */
+static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
+{
+ int pix_per_word;
+
+ if (bpp > 16)
+ return pix;
+
+ pix_per_word = (8 * 32) / bpp;
+ return ALIGN(pix, pix_per_word);
+}
+
+/**
+ * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
+ * @info: The framebuffer to change.
+ *
+ * Framebuffer layer request to set a new mode for the specified framebuffer
+ */
+static int s3c_fb_set_par(struct fb_info *info)
+{
+ struct fb_var_screeninfo *var = &info->var;
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+ void __iomem *regs = sfb->regs;
+ int win_no = win->index;
+ u32 data;
+ u32 pagewidth;
+ int clkdiv;
+
+ dev_dbg(sfb->dev, "setting framebuffer parameters\n");
+
+ switch (var->bits_per_pixel) {
+ case 32:
+ case 24:
+ case 16:
+ case 12:
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ break;
+ case 8:
+ if (s3c_fb_win_has_palette(win_no, 8))
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ else
+ info->fix.visual = FB_VISUAL_TRUECOLOR;
+ break;
+ case 1:
+ info->fix.visual = FB_VISUAL_MONO01;
+ break;
+ default:
+ info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+ break;
+ }
+
+ info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
+
+ /* disable the window whilst we update it */
+ writel(0, regs + WINCON(win_no));
+
+ /* use window 0 as the basis for the lcd output timings */
+
+ if (win_no == 0) {
+ clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
+
+ data = sfb->pdata->vidcon0;
+ data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
+
+ if (clkdiv > 1)
+ data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
+ else
+ data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
+
+ /* write the timing data to the panel */
+
+ data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
+ writel(data, regs + VIDCON0);
+
+ data = VIDTCON0_VBPD(var->upper_margin - 1) |
+ VIDTCON0_VFPD(var->lower_margin - 1) |
+ VIDTCON0_VSPW(var->vsync_len - 1);
+
+ writel(data, regs + VIDTCON0);
+
+ data = VIDTCON1_HBPD(var->left_margin - 1) |
+ VIDTCON1_HFPD(var->right_margin - 1) |
+ VIDTCON1_HSPW(var->hsync_len - 1);
+
+ writel(data, regs + VIDTCON1);
+
+ data = VIDTCON2_LINEVAL(var->yres - 1) |
+ VIDTCON2_HOZVAL(var->xres - 1);
+ writel(data, regs + VIDTCON2);
+ }
+
+ /* write the buffer address */
+
+ writel(info->fix.smem_start, regs + VIDW_BUF_START(win_no));
+
+ data = info->fix.smem_start + info->fix.line_length * var->yres;
+ writel(data, regs + VIDW_BUF_END(win_no));
+
+ pagewidth = (var->xres * var->bits_per_pixel) >> 3;
+ data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
+ VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
+ writel(data, regs + VIDW_BUF_SIZE(win_no));
+
+ /* write 'OSD' registers to control position of framebuffer */
+
+ data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
+ writel(data, regs + VIDOSD_A(win_no));
+
+ data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
+ var->xres - 1)) |
+ VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
+
+ writel(data, regs + VIDOSD_B(win_no));
+
+ data = var->xres * var->yres;
+ if (s3c_fb_has_osd_d(win_no)) {
+ writel(data, regs + VIDOSD_D(win_no));
+ writel(0, regs + VIDOSD_C(win_no));
+ } else
+ writel(data, regs + VIDOSD_C(win_no));
+
+ data = WINCONx_ENWIN;
+
+ /* note, since we have to round up the bits-per-pixel, we end up
+ * relying on the bitfield information for r/g/b/a to work out
+ * exactly which mode of operation is intended. */
+
+ switch (var->bits_per_pixel) {
+ case 1:
+ data |= WINCON0_BPPMODE_1BPP;
+ data |= WINCONx_BITSWP;
+ data |= WINCONx_BURSTLEN_4WORD;
+ break;
+ case 2:
+ data |= WINCON0_BPPMODE_2BPP;
+ data |= WINCONx_BITSWP;
+ data |= WINCONx_BURSTLEN_8WORD;
+ break;
+ case 4:
+ data |= WINCON0_BPPMODE_4BPP;
+ data |= WINCONx_BITSWP;
+ data |= WINCONx_BURSTLEN_8WORD;
+ break;
+ case 8:
+ if (var->transp.length != 0)
+ data |= WINCON1_BPPMODE_8BPP_1232;
+ else
+ data |= WINCON0_BPPMODE_8BPP_PALETTE;
+ data |= WINCONx_BURSTLEN_8WORD;
+ data |= WINCONx_BYTSWP;
+ break;
+ case 16:
+ if (var->transp.length != 0)
+ data |= WINCON1_BPPMODE_16BPP_A1555;
+ else
+ data |= WINCON0_BPPMODE_16BPP_565;
+ data |= WINCONx_HAWSWP;
+ data |= WINCONx_BURSTLEN_16WORD;
+ break;
+ case 24:
+ case 32:
+ if (var->red.length == 6) {
+ if (var->transp.length != 0)
+ data |= WINCON1_BPPMODE_19BPP_A1666;
+ else
+ data |= WINCON1_BPPMODE_18BPP_666;
+ } else if (var->transp.length != 0)
+ data |= WINCON1_BPPMODE_25BPP_A1888;
+ else
+ data |= WINCON0_BPPMODE_24BPP_888;
+
+ data |= WINCONx_BURSTLEN_16WORD;
+ break;
+ }
+
+ writel(data, regs + WINCON(win_no));
+ writel(0x0, regs + WINxMAP(win_no));
+
+ return 0;
+}
+
+/**
+ * s3c_fb_update_palette() - set or schedule a palette update.
+ * @sfb: The hardware information.
+ * @win: The window being updated.
+ * @reg: The palette index being changed.
+ * @value: The computed palette value.
+ *
+ * Change the value of a palette register, either by directly writing to
+ * the palette (this requires the palette RAM to be disconnected from the
+ * hardware whilst this is in progress) or schedule the update for later.
+ *
+ * At the moment, since we have no VSYNC interrupt support, we simply set
+ * the palette entry directly.
+ */
+static void s3c_fb_update_palette(struct s3c_fb *sfb,
+ struct s3c_fb_win *win,
+ unsigned int reg,
+ u32 value)
+{
+ void __iomem *palreg;
+ u32 palcon;
+
+ palreg = sfb->regs + s3c_fb_pal_reg(win->index, reg);
+
+ dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
+ __func__, win->index, reg, palreg, value);
+
+ win->palette_buffer[reg] = value;
+
+ palcon = readl(sfb->regs + WPALCON);
+ writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
+
+ if (s3c_fb_pal_is16(win->index))
+ writew(value, palreg);
+ else
+ writel(value, palreg);
+
+ writel(palcon, sfb->regs + WPALCON);
+}
+
+static inline unsigned int chan_to_field(unsigned int chan,
+ struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+/**
+ * s3c_fb_setcolreg() - framebuffer layer request to change palette.
+ * @regno: The palette index to change.
+ * @red: The red field for the palette data.
+ * @green: The green field for the palette data.
+ * @blue: The blue field for the palette data.
+ * @trans: The transparency (alpha) field for the palette data.
+ * @info: The framebuffer being changed.
+ */
+static int s3c_fb_setcolreg(unsigned regno,
+ unsigned red, unsigned green, unsigned blue,
+ unsigned transp, struct fb_info *info)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+ unsigned int val;
+
+ dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
+ __func__, win->index, regno, red, green, blue);
+
+ switch (info->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ /* true-colour, use pseudo-palette */
+
+ if (regno < 16) {
+ u32 *pal = info->pseudo_palette;
+
+ val = chan_to_field(red, &info->var.red);
+ val |= chan_to_field(green, &info->var.green);
+ val |= chan_to_field(blue, &info->var.blue);
+
+ pal[regno] = val;
+ }
+ break;
+
+ case FB_VISUAL_PSEUDOCOLOR:
+ if (regno < s3c_fb_win_pal_size(win->index)) {
+ val = chan_to_field(red, &win->palette.r);
+ val |= chan_to_field(green, &win->palette.g);
+ val |= chan_to_field(blue, &win->palette.b);
+
+ s3c_fb_update_palette(sfb, win, regno, val);
+ }
+
+ break;
+
+ default:
+ return 1; /* unknown type */
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_fb_enable() - Set the state of the main LCD output
+ * @sfb: The main framebuffer state.
+ * @enable: The state to set.
+ */
+static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
+{
+ u32 vidcon0 = readl(sfb->regs + VIDCON0);
+
+ if (enable)
+ vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
+ else {
+ /* see the note in the framebuffer datasheet about
+ * why you cannot take both of these bits down at the
+ * same time. */
+
+ if (!(vidcon0 & VIDCON0_ENVID))
+ return;
+
+ vidcon0 |= VIDCON0_ENVID;
+ vidcon0 &= ~VIDCON0_ENVID_F;
+ }
+
+ writel(vidcon0, sfb->regs + VIDCON0);
+}
+
+/**
+ * s3c_fb_blank() - blank or unblank the given window
+ * @blank_mode: The blank state from FB_BLANK_*
+ * @info: The framebuffer to blank.
+ *
+ * Framebuffer layer request to change the power state.
+ */
+static int s3c_fb_blank(int blank_mode, struct fb_info *info)
+{
+ struct s3c_fb_win *win = info->par;
+ struct s3c_fb *sfb = win->parent;
+ unsigned int index = win->index;
+ u32 wincon;
+
+ dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
+
+ wincon = readl(sfb->regs + WINCON(index));
+
+ switch (blank_mode) {
+ case FB_BLANK_POWERDOWN:
+ wincon &= ~WINCONx_ENWIN;
+ sfb->enabled &= ~(1 << index);
+ /* fall through to FB_BLANK_NORMAL */
+
+ case FB_BLANK_NORMAL:
+ /* disable the DMA and display 0x0 (black) */
+ writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
+ sfb->regs + WINxMAP(index));
+ break;
+
+ case FB_BLANK_UNBLANK:
+ writel(0x0, sfb->regs + WINxMAP(index));
+ wincon |= WINCONx_ENWIN;
+ sfb->enabled |= (1 << index);
+ break;
+
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ default:
+ return 1;
+ }
+
+ writel(wincon, sfb->regs + WINCON(index));
+
+ /* Check the enabled state to see if we need to be running the
+ * main LCD interface, as if there are no active windows then
+ * it is highly likely that we also do not need to output
+ * anything.
+ */
+
+ /* We could do something like the following code, but the current
+ * system of using framebuffer events means that we cannot make
+ * the distinction between just window 0 being inactive and all
+ * the windows being down.
+ *
+ * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
+ */
+
+ /* we're stuck with this until we can do something about overriding
+ * the power control using the blanking event for a single fb.
+ */
+ if (index == 0)
+ s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
+
+ return 0;
+}
+
+static struct fb_ops s3c_fb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = s3c_fb_check_var,
+ .fb_set_par = s3c_fb_set_par,
+ .fb_blank = s3c_fb_blank,
+ .fb_setcolreg = s3c_fb_setcolreg,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+};
+
+/**
+ * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
+ * @sfb: The base resources for the hardware.
+ * @win: The window to initialise memory for.
+ *
+ * Allocate memory for the given framebuffer.
+ */
+static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
+ struct s3c_fb_win *win)
+{
+ struct s3c_fb_pd_win *windata = win->windata;
+ unsigned int real_size, virt_size, size;
+ struct fb_info *fbi = win->fbinfo;
+ dma_addr_t map_dma;
+
+ dev_dbg(sfb->dev, "allocating memory for display\n");
+
+ real_size = windata->win_mode.xres * windata->win_mode.yres;
+ virt_size = windata->virtual_x * windata->virtual_y;
+
+ dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
+ real_size, windata->win_mode.xres, windata->win_mode.yres,
+ virt_size, windata->virtual_x, windata->virtual_y);
+
+ size = (real_size > virt_size) ? real_size : virt_size;
+ size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
+ size /= 8;
+
+ fbi->fix.smem_len = size;
+ size = PAGE_ALIGN(size);
+
+ dev_dbg(sfb->dev, "want %u bytes for window\n", size);
+
+ fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
+ &map_dma, GFP_KERNEL);
+ if (!fbi->screen_base)
+ return -ENOMEM;
+
+ dev_dbg(sfb->dev, "mapped %x to %p\n",
+ (unsigned int)map_dma, fbi->screen_base);
+
+ memset(fbi->screen_base, 0x0, size);
+ fbi->fix.smem_start = map_dma;
+
+ return 0;
+}
+
+/**
+ * s3c_fb_free_memory() - free the display memory for the given window
+ * @sfb: The base resources for the hardware.
+ * @win: The window to free the display memory for.
+ *
+ * Free the display memory allocated by s3c_fb_alloc_memory().
+ */
+static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
+{
+ struct fb_info *fbi = win->fbinfo;
+
+ dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
+ fbi->screen_base, fbi->fix.smem_start);
+}
+
+/**
+ * s3c_fb_release_win() - release resources for a framebuffer window.
+ * @win: The window to cleanup the resources for.
+ *
+ * Release the resources that where claimed for the hardware window,
+ * such as the framebuffer instance and any memory claimed for it.
+ */
+static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
+{
+ fb_dealloc_cmap(&win->fbinfo->cmap);
+ unregister_framebuffer(win->fbinfo);
+ s3c_fb_free_memory(sfb, win);
+}
+
+/**
+ * s3c_fb_probe_win() - register an hardware window
+ * @sfb: The base resources for the hardware
+ * @res: Pointer to where to place the resultant window.
+ *
+ * Allocate and do the basic initialisation for one of the hardware's graphics
+ * windows.
+ */
+static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
+ struct s3c_fb_win **res)
+{
+ struct fb_var_screeninfo *var;
+ struct fb_videomode *initmode;
+ struct s3c_fb_pd_win *windata;
+ struct s3c_fb_win *win;
+ struct fb_info *fbinfo;
+ int palette_size;
+ int ret;
+
+ dev_dbg(sfb->dev, "probing window %d\n", win_no);
+
+ palette_size = s3c_fb_win_pal_size(win_no);
+
+ fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
+ palette_size * sizeof(u32), sfb->dev);
+ if (!fbinfo) {
+ dev_err(sfb->dev, "failed to allocate framebuffer\n");
+ return -ENOENT;
+ }
+
+ windata = sfb->pdata->win[win_no];
+ initmode = &windata->win_mode;
+
+ WARN_ON(windata->max_bpp == 0);
+ WARN_ON(windata->win_mode.xres == 0);
+ WARN_ON(windata->win_mode.yres == 0);
+
+ win = fbinfo->par;
+ var = &fbinfo->var;
+ win->fbinfo = fbinfo;
+ win->parent = sfb;
+ win->windata = windata;
+ win->index = win_no;
+ win->palette_buffer = (u32 *)(win + 1);
+
+ ret = s3c_fb_alloc_memory(sfb, win);
+ if (ret) {
+ dev_err(sfb->dev, "failed to allocate display memory\n");
+ goto err_framebuffer;
+ }
+
+ /* setup the r/b/g positions for the window's palette */
+ s3c_fb_init_palette(win_no, &win->palette);
+
+ /* setup the initial video mode from the window */
+ fb_videomode_to_var(&fbinfo->var, initmode);
+
+ fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
+ fbinfo->fix.accel = FB_ACCEL_NONE;
+ fbinfo->var.activate = FB_ACTIVATE_NOW;
+ fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
+ fbinfo->var.bits_per_pixel = windata->default_bpp;
+ fbinfo->fbops = &s3c_fb_ops;
+ fbinfo->flags = FBINFO_FLAG_DEFAULT;
+ fbinfo->pseudo_palette = &win->pseudo_palette;
+
+ /* prepare to actually start the framebuffer */
+
+ ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
+ if (ret < 0) {
+ dev_err(sfb->dev, "check_var failed on initial video params\n");
+ goto err_alloc_mem;
+ }
+
+ /* create initial colour map */
+
+ ret = fb_alloc_cmap(&fbinfo->cmap, s3c_fb_win_pal_size(win_no), 1);
+ if (ret == 0)
+ fb_set_cmap(&fbinfo->cmap, fbinfo);
+ else
+ dev_err(sfb->dev, "failed to allocate fb cmap\n");
+
+ s3c_fb_set_par(fbinfo);
+
+ dev_dbg(sfb->dev, "about to register framebuffer\n");
+
+ /* run the check_var and set_par on our configuration. */
+
+ ret = register_framebuffer(fbinfo);
+ if (ret < 0) {
+ dev_err(sfb->dev, "failed to register framebuffer\n");
+ goto err_alloc_mem;
+ }
+
+ *res = win;
+ dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
+
+ return 0;
+
+err_alloc_mem:
+ s3c_fb_free_memory(sfb, win);
+
+err_framebuffer:
+ unregister_framebuffer(fbinfo);
+ return ret;
+}
+
+/**
+ * s3c_fb_clear_win() - clear hardware window registers.
+ * @sfb: The base resources for the hardware.
+ * @win: The window to process.
+ *
+ * Reset the specific window registers to a known state.
+ */
+static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
+{
+ void __iomem *regs = sfb->regs;
+
+ writel(0, regs + WINCON(win));
+ writel(0xffffff, regs + WxKEYCONy(win, 0));
+ writel(0xffffff, regs + WxKEYCONy(win, 1));
+
+ writel(0, regs + VIDOSD_A(win));
+ writel(0, regs + VIDOSD_B(win));
+ writel(0, regs + VIDOSD_C(win));
+}
+
+static int __devinit s3c_fb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct s3c_fb_platdata *pd;
+ struct s3c_fb *sfb;
+ struct resource *res;
+ int win;
+ int ret = 0;
+
+ pd = pdev->dev.platform_data;
+ if (!pd) {
+ dev_err(dev, "no platform data specified\n");
+ return -EINVAL;
+ }
+
+ sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
+ if (!sfb) {
+ dev_err(dev, "no memory for framebuffers\n");
+ return -ENOMEM;
+ }
+
+ sfb->dev = dev;
+ sfb->pdata = pd;
+
+ sfb->bus_clk = clk_get(dev, "lcd");
+ if (IS_ERR(sfb->bus_clk)) {
+ dev_err(dev, "failed to get bus clock\n");
+ goto err_sfb;
+ }
+
+ clk_enable(sfb->bus_clk);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "failed to find registers\n");
+ ret = -ENOENT;
+ goto err_clk;
+ }
+
+ sfb->regs_res = request_mem_region(res->start, resource_size(res),
+ dev_name(dev));
+ if (!sfb->regs_res) {
+ dev_err(dev, "failed to claim register region\n");
+ ret = -ENOENT;
+ goto err_clk;
+ }
+
+ sfb->regs = ioremap(res->start, resource_size(res));
+ if (!sfb->regs) {
+ dev_err(dev, "failed to map registers\n");
+ ret = -ENXIO;
+ goto err_req_region;
+ }
+
+ dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
+
+ /* setup gpio and output polarity controls */
+
+ pd->setup_gpio();
+
+ writel(pd->vidcon1, sfb->regs + VIDCON1);
+
+ /* zero all windows before we do anything */
+
+ for (win = 0; win < S3C_FB_MAX_WIN; win++)
+ s3c_fb_clear_win(sfb, win);
+
+ /* we have the register setup, start allocating framebuffers */
+
+ for (win = 0; win < S3C_FB_MAX_WIN; win++) {
+ if (!pd->win[win])
+ continue;
+
+ ret = s3c_fb_probe_win(sfb, win, &sfb->windows[win]);
+ if (ret < 0) {
+ dev_err(dev, "failed to create window %d\n", win);
+ for (; win >= 0; win--)
+ s3c_fb_release_win(sfb, sfb->windows[win]);
+ goto err_ioremap;
+ }
+ }
+
+ platform_set_drvdata(pdev, sfb);
+
+ return 0;
+
+err_ioremap:
+ iounmap(sfb->regs);
+
+err_req_region:
+ release_resource(sfb->regs_res);
+ kfree(sfb->regs_res);
+
+err_clk:
+ clk_disable(sfb->bus_clk);
+ clk_put(sfb->bus_clk);
+
+err_sfb:
+ kfree(sfb);
+ return ret;
+}
+
+/**
+ * s3c_fb_remove() - Cleanup on module finalisation
+ * @pdev: The platform device we are bound to.
+ *
+ * Shutdown and then release all the resources that the driver allocated
+ * on initialisation.
+ */
+static int __devexit s3c_fb_remove(struct platform_device *pdev)
+{
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ int win;
+
+ for (win = 0; win <= S3C_FB_MAX_WIN; win++)
+ s3c_fb_release_win(sfb, sfb->windows[win]);
+
+ iounmap(sfb->regs);
+
+ clk_disable(sfb->bus_clk);
+ clk_put(sfb->bus_clk);
+
+ release_resource(sfb->regs_res);
+ kfree(sfb->regs_res);
+
+ kfree(sfb);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ struct s3c_fb_win *win;
+ int win_no;
+
+ for (win_no = S3C_FB_MAX_WIN; win_no >= 0; win_no--) {
+ win = sfb->windows[win_no];
+ if (!win)
+ continue;
+
+ /* use the blank function to push into power-down */
+ s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
+ }
+
+ clk_disable(sfb->bus_clk);
+ return 0;
+}
+
+static int s3c_fb_resume(struct platform_device *pdev)
+{
+ struct s3c_fb *sfb = platform_get_drvdata(pdev);
+ struct s3c_fb_win *win;
+ int win_no;
+
+ clk_enable(sfb->bus_clk);
+
+ for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
+ win = sfb->windows[win_no];
+ if (!win)
+ continue;
+
+ dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
+ s3c_fb_set_par(win->fbinfo);
+ }
+
+ return 0;
+}
+#else
+#define s3c_fb_suspend NULL
+#define s3c_fb_resume NULL
+#endif
+
+static struct platform_driver s3c_fb_driver = {
+ .probe = s3c_fb_probe,
+ .remove = s3c_fb_remove,
+ .suspend = s3c_fb_suspend,
+ .resume = s3c_fb_resume,
+ .driver = {
+ .name = "s3c-fb",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init s3c_fb_init(void)
+{
+ return platform_driver_register(&s3c_fb_driver);
+}
+
+static void __exit s3c_fb_cleanup(void)
+{
+ platform_driver_unregister(&s3c_fb_driver);
+}
+
+module_init(s3c_fb_init);
+module_exit(s3c_fb_cleanup);
+
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:s3c-fb");
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -233,6 +233,12 @@
To compile this driver as a module, choose M here: the
module will be called orion5x_wdt.
+config PCF50606_WATCHDOG
+ tristate "NXP PCF50606 Watchdog"
+ depends on MFD_PCF50606
+ help
+ Say Y here to include support for NXP PCF50606 watchdog timer.
+
# ARM26 Architecture
# AVR32 Architecture
@@ -784,7 +790,7 @@
tristate "RTAS watchdog"
depends on PPC_RTAS
help
- This driver adds watchdog support for the RTAS watchdog.
+ his driver adds watchdog support for the RTAS watchdog.
To compile this driver as a module, choose M here. The module
will be called wdrtas.
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -41,6 +41,7 @@
obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
obj-$(CONFIG_ORION5X_WATCHDOG) += orion5x_wdt.o
+obj-$(CONFIG_PCF50606_WATCHDOG) += pcf50606_wdt.o
# ARM26 Architecture
--- /dev/null
+++ b/drivers/watchdog/pcf50606_wdt.c
@@ -0,0 +1,213 @@
+/* Philips PCF50606 Watchdog Timer Driver
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * Author: Balaji Rao <balajirrao@openmoko.org>
+ * All rights reserved.
+ *
+ * Broken down from monstrous PCF50606 driver mainly by
+ * Harald Welte, Matt Hsu, Andy Green and Werner Almesberger
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/miscdevice.h>
+#include <linux/watchdog.h>
+
+#include <linux/mfd/pcf50606/core.h>
+#include <linux/mfd/pcf50606/wdt.h>
+
+static struct pcf50606 *pcf;
+static unsigned long wdt_status;
+#define WDT_IN_USE 0
+#define WDT_OK_TO_CLOSE 1
+#define WDT_REGION_INITED 2
+#define WDT_DEVICE_INITED 3
+
+static int allow_close;
+#define CLOSE_STATE_NOT 0x0000
+#define CLOSE_STATE_ALLOW 0x2342
+
+static void pcf50606_wdt_start(void)
+{
+ pcf50606_reg_set_bit_mask(pcf, PCF50606_REG_OOCC1, PCF50606_OOCC1_WDTRST,
+ PCF50606_OOCC1_WDTRST);
+}
+
+static void pcf50606_wdt_stop(void)
+{
+ pcf50606_reg_clear_bits(pcf, PCF50606_REG_OOCS, PCF50606_OOCS_WDTEXP);
+}
+
+static void pcf50606_wdt_keepalive(void)
+{
+ pcf50606_wdt_start();
+}
+
+static int pcf50606_wdt_open(struct inode *inode, struct file *file)
+{
+ if (test_and_set_bit(WDT_IN_USE, &wdt_status))
+ return -EBUSY;
+
+ pcf50606_wdt_start();
+
+ return nonseekable_open(inode, file);
+}
+
+static int pcf50606_wdt_release(struct inode *inode, struct file *file)
+{
+ if (allow_close == CLOSE_STATE_ALLOW)
+ pcf50606_wdt_stop();
+ else {
+ printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n");
+ pcf50606_wdt_keepalive();
+ }
+
+ allow_close = CLOSE_STATE_NOT;
+ clear_bit(WDT_IN_USE, &wdt_status);
+
+ return 0;
+}
+
+static ssize_t pcf50606_wdt_write(struct file *file, const char __user *data,
+ size_t len, loff_t *ppos)
+{
+ if (len) {
+ size_t i;
+
+ for (i = 0; i != len; i++) {
+ char c;
+ if (get_user(c, data + i))
+ return -EFAULT;
+ if (c == 'V')
+ allow_close = CLOSE_STATE_ALLOW;
+ }
+ pcf50606_wdt_keepalive();
+ }
+
+ return len;
+}
+
+static struct watchdog_info pcf50606_wdt_ident = {
+ .options = WDIOF_MAGICCLOSE,
+ .firmware_version = 0,
+ .identity = "PCF50606 Watchdog",
+};
+
+static int pcf50606_wdt_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ void __user *argp = (void __user *)arg;
+ int __user *p = argp;
+
+ switch (cmd) {
+ case WDIOC_GETSUPPORT:
+ return copy_to_user(argp, &pcf50606_wdt_ident,
+ sizeof(pcf50606_wdt_ident)) ? -EFAULT : 0;
+ break;
+ case WDIOC_GETSTATUS:
+ case WDIOC_GETBOOTSTATUS:
+ return put_user(0, p);
+ case WDIOC_KEEPALIVE:
+ pcf50606_wdt_keepalive();
+ return 0;
+ case WDIOC_GETTIMEOUT:
+ return put_user(8, p);
+ default:
+ return -ENOIOCTLCMD;
+ }
+}
+
+static struct file_operations pcf50606_wdt_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .write = &pcf50606_wdt_write,
+ .ioctl = &pcf50606_wdt_ioctl,
+ .open = &pcf50606_wdt_open,
+ .release = &pcf50606_wdt_release,
+};
+
+static struct miscdevice pcf50606_wdt_miscdev = {
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &pcf50606_wdt_fops,
+};
+
+static void pcf50606_wdt_irq(struct pcf50606 *pcf, int irq, void *unused)
+{
+ pcf50606_reg_set_bit_mask(pcf, PCF50606_REG_OOCC1,
+ PCF50606_OOCC1_WDTRST,
+ PCF50606_OOCC1_WDTRST);
+}
+
+int __init pcf50606_wdt_probe(struct platform_device *pdev)
+{
+ struct pcf50606 *pcf;
+ int err;
+
+ pcf = platform_get_drvdata(pdev);
+
+ err = misc_register(&pcf50606_wdt_miscdev);
+ if (err) {
+ dev_err(&pdev->dev, "cannot register miscdev on "
+ "minor=%d (%d)\n", WATCHDOG_MINOR, err);
+ return err;
+ }
+ set_bit(WDT_DEVICE_INITED, &wdt_status);
+
+ /* Set up IRQ handlers */
+ pcf->irq_handler[PCF50606_IRQ_CHGWD10S].handler = pcf50606_wdt_irq;
+
+ return 0;
+}
+
+static int __devexit pcf50606_wdt_remove(struct platform_device *pdev)
+{
+ struct pcf50606 *pcf;
+
+ pcf = platform_get_drvdata(pdev);
+
+ misc_deregister(&pcf50606_wdt_miscdev);
+
+ pcf->irq_handler[PCF50606_IRQ_CHGWD10S].handler = NULL;
+
+ return 0;
+}
+
+struct platform_driver pcf50606_wdt_driver = {
+ .driver = {
+ .name = "pcf50606-wdt",
+ },
+ .probe = pcf50606_wdt_probe,
+ .remove = __devexit_p(pcf50606_wdt_remove),
+};
+
+static int __init pcf50606_wdt_init(void)
+{
+ return platform_driver_register(&pcf50606_wdt_driver);
+}
+module_init(pcf50606_wdt_init);
+
+static void __exit pcf50606_wdt_exit(void)
+{
+ platform_driver_unregister(&pcf50606_wdt_driver);
+}
+module_exit(pcf50606_wdt_exit);
+
+MODULE_AUTHOR("Balaji Rao <balajirrao@openmoko.org>");
+MODULE_DESCRIPTION("PCF50606 wdt driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pcf50606-wdt");
+
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -42,7 +42,7 @@
#undef S3C_VA_WATCHDOG
#define S3C_VA_WATCHDOG (0)
-#include <asm/plat-s3c/regs-watchdog.h>
+#include <plat/regs-watchdog.h>
#define PFX "s3c2410-wdt: "
--- a/fs/jffs2/background.c
+++ b/fs/jffs2/background.c
@@ -95,13 +95,17 @@
spin_unlock(&c->erase_completion_lock);
- /* This thread is purely an optimisation. But if it runs when
- other things could be running, it actually makes things a
- lot worse. Use yield() and put it at the back of the runqueue
- every time. Especially during boot, pulling an inode in
- with read_inode() is much preferable to having the GC thread
- get there first. */
- yield();
+ /* Problem - immediately after bootup, the GCD spends a lot
+ * of time in places like jffs2_kill_fragtree(); so much so
+ * that userspace processes (like gdm and X) are starved
+ * despite plenty of cond_resched()s and renicing. Yield()
+ * doesn't help, either (presumably because userspace and GCD
+ * are generally competing for a higher latency resource -
+ * disk).
+ * This forces the GCD to slow the hell down. Pulling an
+ * inode in with read_inode() is much preferable to having
+ * the GC thread get there first. */
+ schedule_timeout_interruptible(msecs_to_jiffies(50));
/* Put_super will send a SIGKILL and then wait on the sem.
*/
--- a/include/asm-arm/plat-s3c/iic.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/iic.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - I2C Controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IIC_H
-#define __ASM_ARCH_IIC_H __FILE__
-
-#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
-
-/* Notes:
- * 1) All frequencies are expressed in Hz
- * 2) A value of zero is `do not care`
-*/
-
-struct s3c2410_platform_i2c {
- int bus_num; /* bus number to use */
- unsigned int flags;
- unsigned int slave_addr; /* slave address for controller */
- unsigned long bus_freq; /* standard bus frequency */
- unsigned long max_freq; /* max frequency for the bus */
- unsigned long min_freq; /* min frequency for the bus */
- unsigned int sda_delay; /* pclks (s3c2440 only) */
-};
-
-#endif /* __ASM_ARCH_IIC_H */
--- a/include/asm-arm/plat-s3c/nand.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/nand.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - NAND device controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* struct s3c2410_nand_set
- *
- * define an set of one or more nand chips registered with an unique mtd
- *
- * nr_chips = number of chips in this set
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * name = name of set (optional)
- * nr_map = map for low-layer logical to physical chip numbers (option)
- * partitions = mtd partition list
-*/
-
-struct s3c2410_nand_set {
- unsigned int disable_ecc : 1;
-
- int nr_chips;
- int nr_partitions;
- char *name;
- int *nr_map;
- struct mtd_partition *partitions;
- struct nand_ecclayout *ecc_layout;
-};
-
-struct s3c2410_platform_nand {
- /* timing information for controller, all times in nanoseconds */
-
- int tacls; /* time for active CLE/ALE to nWE/nOE */
- int twrph0; /* active time for nWE/nOE */
- int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
-
- unsigned int ignore_unset_ecc : 1;
-
- int nr_sets;
- struct s3c2410_nand_set *sets;
-
- void (*select_chip)(struct s3c2410_nand_set *,
- int chip);
-};
-
--- a/include/asm-arm/plat-s3c/regs-ac97.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
- *
- * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 AC97 Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_AC97_H
-#define __ASM_ARCH_REGS_AC97_H __FILE__
-
-#define S3C_AC97_GLBCTRL (0x00)
-
-#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
-#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
-#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
-#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
-#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
-#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
-#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
-#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
-#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
-#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
-#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
-#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
-#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
-
-#define S3C_AC97_GLBSTAT (0x04)
-
-#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
-#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
-#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
-#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
-#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
-#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
-#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
-#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
-
-#define S3C_AC97_CODEC_CMD (0x08)
-
-#define S3C_AC97_CODEC_CMD_READ (1<<23)
-
-#define S3C_AC97_STAT (0x0c)
-#define S3C_AC97_PCM_ADDR (0x10)
-#define S3C_AC97_PCM_DATA (0x18)
-#define S3C_AC97_MIC_DATA (0x1C)
-
-#endif /* __ASM_ARCH_REGS_AC97_H */
--- a/include/asm-arm/plat-s3c/regs-iic.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 I2C Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_IIC_H
-#define __ASM_ARCH_REGS_IIC_H __FILE__
-
-/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
-
-#define S3C2410_IICREG(x) (x)
-
-#define S3C2410_IICCON S3C2410_IICREG(0x00)
-#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
-#define S3C2410_IICADD S3C2410_IICREG(0x08)
-#define S3C2410_IICDS S3C2410_IICREG(0x0C)
-#define S3C2440_IICLC S3C2410_IICREG(0x10)
-
-#define S3C2410_IICCON_ACKEN (1<<7)
-#define S3C2410_IICCON_TXDIV_16 (0<<6)
-#define S3C2410_IICCON_TXDIV_512 (1<<6)
-#define S3C2410_IICCON_IRQEN (1<<5)
-#define S3C2410_IICCON_IRQPEND (1<<4)
-#define S3C2410_IICCON_SCALE(x) ((x)&15)
-#define S3C2410_IICCON_SCALEMASK (0xf)
-
-#define S3C2410_IICSTAT_MASTER_RX (2<<6)
-#define S3C2410_IICSTAT_MASTER_TX (3<<6)
-#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
-#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
-#define S3C2410_IICSTAT_MODEMASK (3<<6)
-
-#define S3C2410_IICSTAT_START (1<<5)
-#define S3C2410_IICSTAT_BUSBUSY (1<<5)
-#define S3C2410_IICSTAT_TXRXEN (1<<4)
-#define S3C2410_IICSTAT_ARBITR (1<<3)
-#define S3C2410_IICSTAT_ASSLAVE (1<<2)
-#define S3C2410_IICSTAT_ADDR0 (1<<1)
-#define S3C2410_IICSTAT_LASTBIT (1<<0)
-
-#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
-#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
-#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
-#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
-#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
-
-#define S3C2410_IICLC_FILTER_ON (1<<2)
-
-#endif /* __ASM_ARCH_REGS_IIC_H */
--- a/include/asm-arm/plat-s3c/regs-nand.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
- *
- * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 NAND register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_NAND
-#define __ASM_ARM_REGS_NAND
-
-
-#define S3C2410_NFREG(x) (x)
-
-#define S3C2410_NFCONF S3C2410_NFREG(0x00)
-#define S3C2410_NFCMD S3C2410_NFREG(0x04)
-#define S3C2410_NFADDR S3C2410_NFREG(0x08)
-#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
-#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
-#define S3C2410_NFECC S3C2410_NFREG(0x14)
-
-#define S3C2440_NFCONT S3C2410_NFREG(0x04)
-#define S3C2440_NFCMD S3C2410_NFREG(0x08)
-#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
-#define S3C2440_NFDATA S3C2410_NFREG(0x10)
-#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
-#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
-#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
-#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
-#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
-#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
-#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
-#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
-#define S3C2440_NFSECC S3C2410_NFREG(0x34)
-#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
-#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
-
-#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
-#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
-#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
-#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
-#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
-#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
-#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
-#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
-
-#define S3C2410_NFCONF_EN (1<<15)
-#define S3C2410_NFCONF_512BYTE (1<<14)
-#define S3C2410_NFCONF_4STEP (1<<13)
-#define S3C2410_NFCONF_INITECC (1<<12)
-#define S3C2410_NFCONF_nFCE (1<<11)
-#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
-#define S3C2440_NFCONF_ADVFLASH (1<<3)
-#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
-#define S3C2440_NFCONT_SOFTLOCK (1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
-#define S3C2440_NFCONT_RNBINT_EN (1<<9)
-#define S3C2440_NFCONT_RN_FALLING (1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
-#define S3C2440_NFCONT_INITECC (1<<4)
-#define S3C2440_NFCONT_nFCE (1<<1)
-#define S3C2440_NFCONT_ENABLE (1<<0)
-
-#define S3C2440_NFSTAT_READY (1<<0)
-#define S3C2440_NFSTAT_nCE (1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT (1<<31)
-#define S3C2412_NFCONF_ECCCLKCON (1<<30)
-#define S3C2412_NFCONF_ECC_MLC (1<<24)
-#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
-#define S3C2412_NFCONT_SOFTLOCK (1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
-#define S3C2412_NFCONT_nFCE1 (1<<2)
-#define S3C2412_NFCONT_nFCE0 (1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
-#define S3C2412_NFSTAT_nFCE1 (1<<3)
-#define S3C2412_NFSTAT_nFCE0 (1<<2)
-#define S3C2412_NFSTAT_Res1 (1<<1)
-#define S3C2412_NFSTAT_READY (1<<0)
-
-#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
-#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
-#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
-#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
-#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_NONE (0)
-#define S3C2412_NFECCERR_1BIT (1)
-#define S3C2412_NFECCERR_MULTIBIT (2)
-#define S3C2412_NFECCERR_ECCAREA (3)
-
-
-
-#endif /* __ASM_ARM_REGS_NAND */
-
--- a/include/asm-arm/plat-s3c/regs-rtc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Internal RTC register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_RTC_H
-#define __ASM_ARCH_REGS_RTC_H __FILE__
-
-#define S3C2410_RTCREG(x) (x)
-
-#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN (1<<0)
-#define S3C2410_RTCCON_CLKSEL (1<<1)
-#define S3C2410_RTCCON_CNTSEL (1<<2)
-#define S3C2410_RTCCON_CLKRST (1<<3)
-
-#define S3C2410_TICNT S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE (1<<7)
-
-#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN (1<<6)
-#define S3C2410_RTCALM_YEAREN (1<<5)
-#define S3C2410_RTCALM_MONEN (1<<4)
-#define S3C2410_RTCALM_DAYEN (1<<3)
-#define S3C2410_RTCALM_HOUREN (1<<2)
-#define S3C2410_RTCALM_MINEN (1<<1)
-#define S3C2410_RTCALM_SECEN (1<<0)
-
-#define S3C2410_RTCALM_ALL \
- S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
- S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
- S3C2410_RTCALM_SECEN
-
-
-#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
-
-#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
-#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
-
-
-#endif /* __ASM_ARCH_REGS_RTC_H */
--- a/include/asm-arm/plat-s3c/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H
-
-#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-
-#define S3C2410_WTCON S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT S3C_WDOGREG(0x08)
-
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-
-#define S3C2410_WTCON_RSTEN (0x01)
-#define S3C2410_WTCON_INTEN (1<<2)
-#define S3C2410_WTCON_ENABLE (1<<5)
-
-#define S3C2410_WTCON_DIV16 (0<<3)
-#define S3C2410_WTCON_DIV32 (1<<3)
-#define S3C2410_WTCON_DIV64 (2<<3)
-#define S3C2410_WTCON_DIV128 (3<<3)
-
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
-
-
--- a/include/asm-arm/plat-s3c24xx/mci.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ARCH_MCI_H
-#define _ARCH_MCI_H
-
-struct s3c24xx_mci_pdata {
- unsigned int wprotect_invert : 1;
- unsigned int detect_invert : 1; /* set => detect active high. */
-
- unsigned int gpio_detect;
- unsigned int gpio_wprotect;
- unsigned long ocr_avail;
- void (*set_power)(unsigned char power_mode,
- unsigned short vdd);
-};
-
-#endif /* _ARCH_NCI_H */
--- /dev/null
+++ b/include/asm-arm/plat-s3c24xx/neo1973.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/plat-s3c24xx/neo1973.h
+ *
+ * Common utility code for GTA01 and GTA02
+ *
+ * Copyright (C) 2008 by Openmoko, Inc.
+ * Author: Holger Hans Peter Freyther <freyther@openmoko.org>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef NEO1973_H
+#define NEO1973_H
+
+void neo1973_gpb_add_shadow_gpio(unsigned int gpio);
+void neo1973_gpb_setpin(unsigned int pin, unsigned to);
+
+#endif
--- a/include/asm-arm/plat-s3c24xx/regs-spi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
- *
- * Copyright (c) 2004 Fetron GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 SPI register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_SPI_H
-#define __ASM_ARCH_REGS_SPI_H
-
-#define S3C2410_SPI1 (0x20)
-#define S3C2412_SPI1 (0x100)
-
-#define S3C2410_SPCON (0x00)
-
-#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
-#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
-#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
-#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
-#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
-#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
-#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
-#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
-#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
-#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
-#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
-#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
-
-#define S3C2412_SPCON_DIRC_RX (1<<7)
-
-#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
-#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
-#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
-#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
-#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
- 0: slave, 1: master */
-#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
-#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
-
-#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
-#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
-
-#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
-
-
-#define S3C2410_SPSTA (0x04)
-
-#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
-#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
-#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
-#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
-#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
-#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
-#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
-#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
-
-#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
-#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
-#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
-#define S3C2412_SPSTA_READY_ORG (1<<3)
-
-#define S3C2410_SPPIN (0x08)
-
-#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
-#define S3C2410_SPPIN_RESERVED (1<<1)
-#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
-#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
-
-#define S3C2410_SPPRE (0x0C)
-#define S3C2410_SPTDAT (0x10)
-#define S3C2410_SPRDAT (0x14)
-
-#define S3C2412_TXFIFO (0x18)
-#define S3C2412_RXFIFO (0x18)
-#define S3C2412_SPFIC (0x24)
-
-
-#endif /* __ASM_ARCH_REGS_SPI_H */
--- a/include/asm-arm/plat-s3c24xx/regs-udc.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
- *
- * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
- *
- * This include file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
-*/
-
-#ifndef __ASM_ARCH_REGS_UDC_H
-#define __ASM_ARCH_REGS_UDC_H
-
-#define S3C2410_USBDREG(x) (x)
-
-#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140)
-#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144)
-#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148)
-
-#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158)
-#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c)
-
-#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c)
-
-#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170)
-#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174)
-
-#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0)
-#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4)
-#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8)
-#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc)
-#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0)
-
-#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200)
-#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204)
-#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208)
-#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c)
-#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210)
-#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214)
-
-#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218)
-#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c)
-#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220)
-#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224)
-#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228)
-#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c)
-
-#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240)
-#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244)
-#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248)
-#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c)
-#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250)
-#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254)
-
-#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258)
-#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c)
-#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260)
-#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264)
-#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268)
-#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c)
-
-#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178)
-
-/* indexed registers */
-
-#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180)
-
-#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184)
-
-#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184)
-#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188)
-
-#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190)
-#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194)
-#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
-#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
-
-#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
-
-#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
-#define S3C2410_UDC_PWR_RESET (1<<3) // R
-#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W
-#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R
-#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W
-
-#define S3C2410_UDC_PWR_DEFAULT 0x00
-
-#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only)
-#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only)
-#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only)
-#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only)
-#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only)
-#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only)
-#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W
-#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W
-#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W
-#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W
-#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W
-
-#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
-#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
-
-
-#define S3C2410_UDC_INDEX_EP0 (0x00)
-#define S3C2410_UDC_INDEX_EP1 (0x01) // ??
-#define S3C2410_UDC_INDEX_EP2 (0x02) // ??
-#define S3C2410_UDC_INDEX_EP3 (0x03) // ??
-#define S3C2410_UDC_INDEX_EP4 (0x04) // ??
-
-#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W
-#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W
-#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only)
-#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only)
-
-#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W
-#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W
-#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W
-#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W
-
-#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W
-#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W
-#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W
-#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R
-#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W
-#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
-#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
-
-#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
-#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
-#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
-#define S3C2410_UDC_EP0_CSR_DE (1<<3)
-#define S3C2410_UDC_EP0_CSR_SE (1<<4)
-#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5)
-#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6)
-#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
-
-#define S3C2410_UDC_MAXP_8 (1<<0)
-#define S3C2410_UDC_MAXP_16 (1<<1)
-#define S3C2410_UDC_MAXP_32 (1<<2)
-#define S3C2410_UDC_MAXP_64 (1<<3)
-
-
-#endif
--- a/include/asm-arm/plat-s3c24xx/udc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/udc.h
- *
- * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
- * Changelog:
- * 14-Mar-2005 RTP Created file
- * 02-Aug-2005 RTP File rename
- * 07-Sep-2005 BJD Minor cleanups, changed cmd to enum
- * 18-Jan-2007 HMW Add per-platform vbus_draw function
-*/
-
-#ifndef __ASM_ARM_ARCH_UDC_H
-#define __ASM_ARM_ARCH_UDC_H
-
-enum s3c2410_udc_cmd_e {
- S3C2410_UDC_P_ENABLE = 1, /* Pull-up enable */
- S3C2410_UDC_P_DISABLE = 2, /* Pull-up disable */
- S3C2410_UDC_P_RESET = 3, /* UDC reset, in case of */
-};
-
-struct s3c2410_udc_mach_info {
- void (*udc_command)(enum s3c2410_udc_cmd_e);
- void (*vbus_draw)(unsigned int ma);
- unsigned int vbus_pin;
- unsigned char vbus_pin_inverted;
-};
-
-extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
-
-#endif /* __ASM_ARM_ARCH_UDC_H */
--- /dev/null
+++ b/include/linux/android_aid.h
@@ -0,0 +1,25 @@
+/* include/linux/android_aid.h
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_ANDROID_AID_H
+#define _LINUX_ANDROID_AID_H
+
+/* AIDs that the kernel treats differently */
+#define AID_NET_BT_ADMIN 3001
+#define AID_NET_BT 3002
+#define AID_INET 3003
+#define AID_NET_RAW 3004
+
+#endif
--- /dev/null
+++ b/include/linux/android_alarm.h
@@ -0,0 +1,59 @@
+/* include/linux/android_alarm.h
+ *
+ * Copyright (C) 2006-2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_ANDROID_ALARM_H
+#define _LINUX_ANDROID_ALARM_H
+
+#include <asm/ioctl.h>
+#include <linux/time.h>
+
+typedef enum {
+ /* return code bit numbers or set alarm arg */
+ ANDROID_ALARM_RTC_WAKEUP,
+ ANDROID_ALARM_RTC,
+ ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
+ ANDROID_ALARM_ELAPSED_REALTIME,
+ ANDROID_ALARM_SYSTEMTIME,
+
+ ANDROID_ALARM_TYPE_COUNT,
+
+ /* return code bit numbers */
+ /* ANDROID_ALARM_TIME_CHANGE = 16 */
+} android_alarm_type_t;
+
+typedef enum {
+ ANDROID_ALARM_RTC_WAKEUP_MASK = 1U << ANDROID_ALARM_RTC_WAKEUP,
+ ANDROID_ALARM_RTC_MASK = 1U << ANDROID_ALARM_RTC,
+ ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP_MASK = 1U << ANDROID_ALARM_ELAPSED_REALTIME_WAKEUP,
+ ANDROID_ALARM_ELAPSED_REALTIME_MASK = 1U << ANDROID_ALARM_ELAPSED_REALTIME,
+ ANDROID_ALARM_SYSTEMTIME_MASK = 1U << ANDROID_ALARM_SYSTEMTIME,
+ ANDROID_ALARM_TIME_CHANGE_MASK = 1U << 16
+} android_alarm_return_flags_t;
+
+/* Disable alarm */
+#define ANDROID_ALARM_CLEAR(type) _IO('a', 0 | ((type) << 4))
+
+/* Ack last alarm and wait for next */
+#define ANDROID_ALARM_WAIT _IO('a', 1)
+
+/* Set alarm */
+#define ANDROID_ALARM_SET(type) _IOW('a', 2 | ((type) << 4), struct timespec)
+#define ANDROID_ALARM_SET_AND_WAIT(type) _IOW('a', 3 | ((type) << 4), struct timespec)
+#define ANDROID_ALARM_GET_TIME(type) _IOW('a', 4 | ((type) << 4), struct timespec)
+#define ANDROID_ALARM_SET_RTC _IOW('a', 5, struct timespec)
+#define ANDROID_ALARM_BASE_CMD(cmd) (cmd & ~(_IOC(0, 0, 0xf0, 0)))
+#define ANDROID_ALARM_IOCTL_TO_TYPE(cmd) (_IOC_NR(cmd) >> 4)
+
+#endif
--- /dev/null
+++ b/include/linux/android_power.h
@@ -0,0 +1,98 @@
+/* include/linux/android_power.h
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_ANDROID_POWER_H
+#define _LINUX_ANDROID_POWER_H
+
+#include <linux/list.h>
+#include <linux/ktime.h>
+
+typedef struct
+{
+ struct list_head link;
+ int flags;
+ const char *name;
+ int expires;
+#ifdef CONFIG_ANDROID_POWER_STAT
+ struct {
+ int count;
+ int expire_count;
+ ktime_t total_time;
+ ktime_t max_time;
+ ktime_t last_time;
+ } stat;
+#endif
+} android_suspend_lock_t;
+
+#if 0 /* none of these flags are implemented */
+#define ANDROID_SUSPEND_LOCK_FLAG_COUNTED (1U << 0)
+#define ANDROID_SUSPEND_LOCK_FLAG_USER_READABLE (1U << 1)
+#define ANDROID_SUSPEND_LOCK_FLAG_USER_SET (1U << 2)
+#define ANDROID_SUSPEND_LOCK_FLAG_USER_CLEAR (1U << 3)
+#define ANDROID_SUSPEND_LOCK_FLAG_USER_INC (1U << 4)
+#define ANDROID_SUSPEND_LOCK_FLAG_USER_DEC (1U << 5)
+#define ANDROID_SUSPEND_LOCK_FLAG_USER_VISIBLE_MASK (0x1fU << 1)
+#endif
+#define ANDROID_SUSPEND_LOCK_AUTO_EXPIRE (1U << 6)
+#define ANDROID_SUSPEND_LOCK_ACTIVE (1U << 7)
+
+enum {
+ ANDROID_STOPPED_DRAWING,
+ ANDROID_REQUEST_STOP_DRAWING,
+ ANDROID_DRAWING_OK,
+};
+
+enum {
+ ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN = 50,
+ ANDROID_EARLY_SUSPEND_LEVEL_CONSOLE_SWITCH = 100,
+ ANDROID_EARLY_SUSPEND_LEVEL_DISABLE_FB = 150,
+};
+typedef struct android_early_suspend android_early_suspend_t;
+struct android_early_suspend
+{
+ struct list_head link;
+ int level;
+ void (*suspend)(android_early_suspend_t *h);
+ void (*resume)(android_early_suspend_t *h);
+};
+
+typedef enum {
+ ANDROID_CHARGING_STATE_UNKNOWN,
+ ANDROID_CHARGING_STATE_DISCHARGE,
+ ANDROID_CHARGING_STATE_MAINTAIN, /* or trickle */
+ ANDROID_CHARGING_STATE_SLOW,
+ ANDROID_CHARGING_STATE_NORMAL,
+ ANDROID_CHARGING_STATE_FAST,
+ ANDROID_CHARGING_STATE_OVERHEAT
+} android_charging_state_t;
+
+/* android_suspend_lock_t *android_allocate_suspend_lock(const char *debug_name); */
+/* void android_free_suspend_lock(android_suspend_lock_t *lock); */
+int android_init_suspend_lock(android_suspend_lock_t *lock);
+void android_uninit_suspend_lock(android_suspend_lock_t *lock);
+void android_lock_idle(android_suspend_lock_t *lock);
+void android_lock_idle_auto_expire(android_suspend_lock_t *lock, int timeout);
+void android_lock_suspend(android_suspend_lock_t *lock);
+void android_lock_suspend_auto_expire(android_suspend_lock_t *lock, int timeout);
+void android_unlock_suspend(android_suspend_lock_t *lock);
+
+int android_power_is_driver_suspended(void);
+int android_power_is_low_power_idle_ok(void);
+
+void android_register_early_suspend(android_early_suspend_t *handler);
+void android_unregister_early_suspend(android_early_suspend_t *handler);
+
+#endif
+
--- /dev/null
+++ b/include/linux/android_timed_gpio.h
@@ -0,0 +1,31 @@
+/* include/linux/android_timed_gpio.h
+ *
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+*/
+
+#ifndef _LINUX_ANDROID_TIMED_GPIO_H
+#define _LINUX_ANDROID_TIMED_GPIO_H
+
+struct timed_gpio {
+ const char *name;
+ unsigned gpio;
+ int max_timeout;
+ u8 active_low;
+};
+
+struct timed_gpio_platform_data {
+ int num_gpios;
+ struct timed_gpio *gpios;
+};
+
+#endif
--- /dev/null
+++ b/include/linux/ashmem.h
@@ -0,0 +1,48 @@
+/*
+ * include/linux/ashmem.h
+ *
+ * Copyright 2008 Google Inc.
+ * Author: Robert Love
+ *
+ * This file is dual licensed. It may be redistributed and/or modified
+ * under the terms of the Apache 2.0 License OR version 2 of the GNU
+ * General Public License.
+ */
+
+#ifndef _LINUX_ASHMEM_H
+#define _LINUX_ASHMEM_H
+
+#include <linux/limits.h>
+#include <linux/ioctl.h>
+
+#define ASHMEM_NAME_LEN 256
+
+#define ASHMEM_NAME_DEF "dev/ashmem"
+
+/* Return values from ASHMEM_PIN: Was the mapping purged while unpinned? */
+#define ASHMEM_NOT_PURGED 0
+#define ASHMEM_WAS_PURGED 1
+
+/* Return values from ASHMEM_GET_PIN_STATUS: Is the mapping pinned? */
+#define ASHMEM_IS_UNPINNED 0
+#define ASHMEM_IS_PINNED 1
+
+struct ashmem_pin {
+ __u32 offset; /* offset into region, in bytes, page-aligned */
+ __u32 len; /* length forward from offset, in bytes, page-aligned */
+};
+
+#define __ASHMEMIOC 0x77
+
+#define ASHMEM_SET_NAME _IOW(__ASHMEMIOC, 1, char[ASHMEM_NAME_LEN])
+#define ASHMEM_GET_NAME _IOR(__ASHMEMIOC, 2, char[ASHMEM_NAME_LEN])
+#define ASHMEM_SET_SIZE _IOW(__ASHMEMIOC, 3, size_t)
+#define ASHMEM_GET_SIZE _IO(__ASHMEMIOC, 4)
+#define ASHMEM_SET_PROT_MASK _IOW(__ASHMEMIOC, 5, unsigned long)
+#define ASHMEM_GET_PROT_MASK _IO(__ASHMEMIOC, 6)
+#define ASHMEM_PIN _IOW(__ASHMEMIOC, 7, struct ashmem_pin)
+#define ASHMEM_UNPIN _IOW(__ASHMEMIOC, 8, struct ashmem_pin)
+#define ASHMEM_GET_PIN_STATUS _IO(__ASHMEMIOC, 9)
+#define ASHMEM_PURGE_ALL_CACHES _IO(__ASHMEMIOC, 10)
+
+#endif /* _LINUX_ASHMEM_H */
--- /dev/null
+++ b/include/linux/binder.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2008 Google, Inc.
+ *
+ * Based on, but no longer compatible with, the original
+ * OpenBinder.org binder driver interface, which is:
+ *
+ * Copyright (c) 2005 Palmsource, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_BINDER_H
+#define _LINUX_BINDER_H
+
+#include <linux/ioctl.h>
+
+#define B_PACK_CHARS(c1, c2, c3, c4) \
+ ((((c1)<<24)) | (((c2)<<16)) | (((c3)<<8)) | (c4))
+#define B_TYPE_LARGE 0x85
+
+enum {
+ BINDER_TYPE_BINDER = B_PACK_CHARS('s', 'b', '*', B_TYPE_LARGE),
+ BINDER_TYPE_WEAK_BINDER = B_PACK_CHARS('w', 'b', '*', B_TYPE_LARGE),
+ BINDER_TYPE_HANDLE = B_PACK_CHARS('s', 'h', '*', B_TYPE_LARGE),
+ BINDER_TYPE_WEAK_HANDLE = B_PACK_CHARS('w', 'h', '*', B_TYPE_LARGE),
+ BINDER_TYPE_FD = B_PACK_CHARS('f', 'd', '*', B_TYPE_LARGE),
+};
+
+enum {
+ FLAT_BINDER_FLAG_PRIORITY_MASK = 0xff,
+ FLAT_BINDER_FLAG_ACCEPTS_FDS = 0x100,
+};
+
+/*
+ * This is the flattened representation of a Binder object for transfer
+ * between processes. The 'offsets' supplied as part of a binder transaction
+ * contains offsets into the data where these structures occur. The Binder
+ * driver takes care of re-writing the structure type and data as it moves
+ * between processes.
+ */
+struct flat_binder_object {
+ /* 8 bytes for large_flat_header. */
+ unsigned long type;
+ unsigned long flags;
+
+ /* 8 bytes of data. */
+ union {
+ void *binder; /* local object */
+ signed long handle; /* remote object */
+ };
+
+ /* extra data associated with local object */
+ void *cookie;
+};
+
+/*
+ * On 64-bit platforms where user code may run in 32-bits the driver must
+ * translate the buffer (and local binder) addresses apropriately.
+ */
+
+struct binder_write_read {
+ signed long write_size; /* bytes to write */
+ signed long write_consumed; /* bytes consumed by driver */
+ unsigned long write_buffer;
+ signed long read_size; /* bytes to read */
+ signed long read_consumed; /* bytes consumed by driver */
+ unsigned long read_buffer;
+};
+
+/* Use with BINDER_VERSION, driver fills in fields. */
+struct binder_version {
+ /* driver protocol version -- increment with incompatible change */
+ signed long protocol_version;
+};
+
+/* This is the current protocol version. */
+#define BINDER_CURRENT_PROTOCOL_VERSION 7
+
+#define BINDER_WRITE_READ _IOWR('b', 1, struct binder_write_read)
+#define BINDER_SET_IDLE_TIMEOUT _IOW('b', 3, int64_t)
+#define BINDER_SET_MAX_THREADS _IOW('b', 5, size_t)
+#define BINDER_SET_IDLE_PRIORITY _IOW('b', 6, int)
+#define BINDER_SET_CONTEXT_MGR _IOW('b', 7, int)
+#define BINDER_THREAD_EXIT _IOW('b', 8, int)
+#define BINDER_VERSION _IOWR('b', 9, struct binder_version)
+
+/*
+ * NOTE: Two special error codes you should check for when calling
+ * in to the driver are:
+ *
+ * EINTR -- The operation has been interupted. This should be
+ * handled by retrying the ioctl() until a different error code
+ * is returned.
+ *
+ * ECONNREFUSED -- The driver is no longer accepting operations
+ * from your process. That is, the process is being destroyed.
+ * You should handle this by exiting from your process. Note
+ * that once this error code is returned, all further calls to
+ * the driver from any thread will return this same code.
+ */
+
+enum transaction_flags {
+ TF_ONE_WAY = 0x01, /* this is a one-way call: async, no return */
+ TF_ROOT_OBJECT = 0x04, /* contents are the component's root object */
+ TF_STATUS_CODE = 0x08, /* contents are a 32-bit status code */
+ TF_ACCEPT_FDS = 0x10, /* allow replies with file descriptors */
+};
+
+struct binder_transaction_data {
+ /* The first two are only used for bcTRANSACTION and brTRANSACTION,
+ * identifying the target and contents of the transaction.
+ */
+ union {
+ size_t handle; /* target descriptor of command transaction */
+ void *ptr; /* target descriptor of return transaction */
+ } target;
+ void *cookie; /* target object cookie */
+ unsigned int code; /* transaction command */
+
+ /* General information about the transaction. */
+ unsigned int flags;
+ pid_t sender_pid;
+ uid_t sender_euid;
+ size_t data_size; /* number of bytes of data */
+ size_t offsets_size; /* number of bytes of offsets */
+
+ /* If this transaction is inline, the data immediately
+ * follows here; otherwise, it ends with a pointer to
+ * the data buffer.
+ */
+ union {
+ struct {
+ /* transaction data */
+ const void *buffer;
+ /* offsets from buffer to flat_binder_object structs */
+ const void *offsets;
+ } ptr;
+ uint8_t buf[8];
+ } data;
+};
+
+struct binder_ptr_cookie {
+ void *ptr;
+ void *cookie;
+};
+
+struct binder_pri_desc {
+ int priority;
+ int desc;
+};
+
+struct binder_pri_ptr_cookie {
+ int priority;
+ void *ptr;
+ void *cookie;
+};
+
+enum BinderDriverReturnProtocol {
+ BR_ERROR = _IOR('r', 0, int),
+ /*
+ * int: error code
+ */
+
+ BR_OK = _IO('r', 1),
+ /* No parameters! */
+
+ BR_TRANSACTION = _IOR('r', 2, struct binder_transaction_data),
+ BR_REPLY = _IOR('r', 3, struct binder_transaction_data),
+ /*
+ * binder_transaction_data: the received command.
+ */
+
+ BR_ACQUIRE_RESULT = _IOR('r', 4, int),
+ /*
+ * not currently supported
+ * int: 0 if the last bcATTEMPT_ACQUIRE was not successful.
+ * Else the remote object has acquired a primary reference.
+ */
+
+ BR_DEAD_REPLY = _IO('r', 5),
+ /*
+ * The target of the last transaction (either a bcTRANSACTION or
+ * a bcATTEMPT_ACQUIRE) is no longer with us. No parameters.
+ */
+
+ BR_TRANSACTION_COMPLETE = _IO('r', 6),
+ /*
+ * No parameters... always refers to the last transaction requested
+ * (including replies). Note that this will be sent even for
+ * asynchronous transactions.
+ */
+
+ BR_INCREFS = _IOR('r', 7, struct binder_ptr_cookie),
+ BR_ACQUIRE = _IOR('r', 8, struct binder_ptr_cookie),
+ BR_RELEASE = _IOR('r', 9, struct binder_ptr_cookie),
+ BR_DECREFS = _IOR('r', 10, struct binder_ptr_cookie),
+ /*
+ * void *: ptr to binder
+ * void *: cookie for binder
+ */
+
+ BR_ATTEMPT_ACQUIRE = _IOR('r', 11, struct binder_pri_ptr_cookie),
+ /*
+ * not currently supported
+ * int: priority
+ * void *: ptr to binder
+ * void *: cookie for binder
+ */
+
+ BR_NOOP = _IO('r', 12),
+ /*
+ * No parameters. Do nothing and examine the next command. It exists
+ * primarily so that we can replace it with a BR_SPAWN_LOOPER command.
+ */
+
+ BR_SPAWN_LOOPER = _IO('r', 13),
+ /*
+ * No parameters. The driver has determined that a process has no
+ * threads waiting to service incomming transactions. When a process
+ * receives this command, it must spawn a new service thread and
+ * register it via bcENTER_LOOPER.
+ */
+
+ BR_FINISHED = _IO('r', 14),
+ /*
+ * not currently supported
+ * stop threadpool thread
+ */
+
+ BR_DEAD_BINDER = _IOR('r', 15, void *),
+ /*
+ * void *: cookie
+ */
+ BR_CLEAR_DEATH_NOTIFICATION_DONE = _IOR('r', 16, void *),
+ /*
+ * void *: cookie
+ */
+
+ BR_FAILED_REPLY = _IO('r', 17),
+ /*
+ * The the last transaction (either a bcTRANSACTION or
+ * a bcATTEMPT_ACQUIRE) failed (e.g. out of memory). No parameters.
+ */
+};
+
+enum BinderDriverCommandProtocol {
+ BC_TRANSACTION = _IOW('c', 0, struct binder_transaction_data),
+ BC_REPLY = _IOW('c', 1, struct binder_transaction_data),
+ /*
+ * binder_transaction_data: the sent command.
+ */
+
+ BC_ACQUIRE_RESULT = _IOW('c', 2, int),
+ /*
+ * not currently supported
+ * int: 0 if the last BR_ATTEMPT_ACQUIRE was not successful.
+ * Else you have acquired a primary reference on the object.
+ */
+
+ BC_FREE_BUFFER = _IOW('c', 3, int),
+ /*
+ * void *: ptr to transaction data received on a read
+ */
+
+ BC_INCREFS = _IOW('c', 4, int),
+ BC_ACQUIRE = _IOW('c', 5, int),
+ BC_RELEASE = _IOW('c', 6, int),
+ BC_DECREFS = _IOW('c', 7, int),
+ /*
+ * int: descriptor
+ */
+
+ BC_INCREFS_DONE = _IOW('c', 8, struct binder_ptr_cookie),
+ BC_ACQUIRE_DONE = _IOW('c', 9, struct binder_ptr_cookie),
+ /*
+ * void *: ptr to binder
+ * void *: cookie for binder
+ */
+
+ BC_ATTEMPT_ACQUIRE = _IOW('c', 10, struct binder_pri_desc),
+ /*
+ * not currently supported
+ * int: priority
+ * int: descriptor
+ */
+
+ BC_REGISTER_LOOPER = _IO('c', 11),
+ /*
+ * No parameters.
+ * Register a spawned looper thread with the device.
+ */
+
+ BC_ENTER_LOOPER = _IO('c', 12),
+ BC_EXIT_LOOPER = _IO('c', 13),
+ /*
+ * No parameters.
+ * These two commands are sent as an application-level thread
+ * enters and exits the binder loop, respectively. They are
+ * used so the binder can have an accurate count of the number
+ * of looping threads it has available.
+ */
+
+ BC_REQUEST_DEATH_NOTIFICATION = _IOW('c', 14, struct binder_ptr_cookie),
+ /*
+ * void *: ptr to binder
+ * void *: cookie
+ */
+
+ BC_CLEAR_DEATH_NOTIFICATION = _IOW('c', 15, struct binder_ptr_cookie),
+ /*
+ * void *: ptr to binder
+ * void *: cookie
+ */
+
+ BC_DEAD_BINDER_DONE = _IOW('c', 16, void *),
+ /*
+ * void *: cookie
+ */
+};
+
+#endif /* _LINUX_BINDER_H */
+
--- /dev/null
+++ b/include/linux/bq27000_battery.h
@@ -0,0 +1,14 @@
+#ifndef __BQ27000_BATTERY_H__
+#define __BQ27000_BATTERY_H__
+
+struct bq27000_platform_data {
+ const char *name;
+ int rsense_mohms;
+ int (*hdq_read)(int);
+ int (*hdq_write)(int, u8);
+ int (*hdq_initialized)(void);
+ int (*get_charger_online_status)(void);
+ int (*get_charger_active_status)(void);
+};
+
+#endif
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -48,6 +48,11 @@
struct bus_attribute *);
extern void bus_remove_file(struct bus_type *, struct bus_attribute *);
+extern int __must_check bus_create_device_link(struct bus_type *bus,
+ struct kobject *target,
+ const char *name);
+extern void bus_remove_device_link(struct bus_type *bus, const char *name);
+
struct bus_type {
const char *name;
struct bus_attribute *bus_attrs;
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -123,6 +123,7 @@
#define FB_ACCEL_TRIDENT_3DIMAGE 51 /* Trident 3DImage */
#define FB_ACCEL_TRIDENT_BLADE3D 52 /* Trident Blade3D */
#define FB_ACCEL_TRIDENT_BLADEXP 53 /* Trident BladeXP */
+#define FB_ACCEL_GLAMO 50 /* SMedia Glamo */
#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
--- /dev/null
+++ b/include/linux/glamofb.h
@@ -0,0 +1,45 @@
+#ifndef _LINUX_GLAMOFB_H
+#define _LINUX_GLAMOFB_H
+
+#include <linux/spi/glamo.h>
+
+struct glamofb_val {
+ unsigned int defval;
+ unsigned int min;
+ unsigned int max;
+};
+
+struct glamo_core;
+
+struct glamofb_platform_data {
+ int width, height;
+ int pixclock;
+ int left_margin, right_margin;
+ int upper_margin, lower_margin;
+ int hsync_len, vsync_len;
+ int fb_mem_size;
+
+ struct glamofb_val xres;
+ struct glamofb_val yres;
+ struct glamofb_val bpp;
+
+ struct glamo_spi_info *spi_info;
+ struct glamo_spigpio_info *spigpio_info;
+ struct glamo_core *glamo;
+
+ struct platform_device *mmc_dev;
+
+ /* glamo mmc platform specific info */
+ int (*glamo_can_set_mci_power)(void);
+
+ /* glamo-mci asking if it should use the slow clock to card */
+ int (*glamo_mci_use_slow)(void);
+ int (*glamo_irq_is_wired)(void);
+ void (*glamo_external_reset)(int);
+};
+
+int glamofb_cmd_mode(struct glamofb_handle *gfb, int on);
+int glamofb_cmd_write(struct glamofb_handle *gfb, u_int16_t val);
+void glamo_lcm_reset(int level);
+
+#endif
--- /dev/null
+++ b/include/linux/glamo-gpio.h
@@ -0,0 +1,99 @@
+#ifndef __GLAMO_GPIO_H
+#define __GLAMO_GPIO_H
+
+struct glamo_core;
+
+#define GLAMO_GPIO_BANKA 0x0000
+#define GLAMO_GPIO_BANKB 0x1000
+#define GLAMO_GPIO_BANKC 0x2000
+#define GLAMO_GPIO_BANKD 0x3000
+
+#define GLAMO_GPIONO(bank, pin) ((bank & 0xf000) | ((pin & 0xf) << 8))
+
+#define GLAMO_GPIO_F_IN 0x0010
+#define GLAMO_GPIO_F_OUT 0x0020
+#define GLAMO_GPIO_F_FUNC 0x0030
+
+#define GLAMO_GPIO0 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 0)
+#define GLAMO_GPIO0_INPUT (GLAMO_GPIO0 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO0_OUTPUT (GLAMO_GPIO0 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO0_HA20 (GLAMO_GPIO0 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO1 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 1)
+#define GLAMO_GPIO1_INPUT (GLAMO_GPIO1 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO1_OUTPUT (GLAMO_GPIO1 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO1_HA21 (GLAMO_GPIO1 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO2 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 2)
+#define GLAMO_GPIO2_INPUT (GLAMO_GPIO2 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO2_OUTPUT (GLAMO_GPIO2 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO2_HA22 (GLAMO_GPIO2 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO3 GLAMO_GPIONO(GLAMO_GPIO_BANKA, 3)
+#define GLAMO_GPIO3_INPUT (GLAMO_GPIO3 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO3_OUTPUT (GLAMO_GPIO3 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO3_HA23 (GLAMO_GPIO3 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO4 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 0)
+#define GLAMO_GPIO4_INPUT (GLAMO_GPIO4 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO4_OUTPUT (GLAMO_GPIO4 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO4_nLCS0 (GLAMO_GPIO4 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO5 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 1)
+#define GLAMO_GPIO5_INPUT (GLAMO_GPIO5 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO5_OUTPUT (GLAMO_GPIO5 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO5_nLCS1 (GLAMO_GPIO5 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO6 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 2)
+#define GLAMO_GPIO6_INPUT (GLAMO_GPIO6 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO6_OUTPUT (GLAMO_GPIO6 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO6_LDCLK (GLAMO_GPIO6 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO7 GLAMO_GPIONO(GLAMO_GPIO_BANKB, 3)
+#define GLAMO_GPIO7_INPUT (GLAMO_GPIO7 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO7_OUTPUT (GLAMO_GPIO7 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO7_nLDE (GLAMO_GPIO7 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO8 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 0)
+#define GLAMO_GPIO8_INPUT (GLAMO_GPIO8 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO8_OUTPUT (GLAMO_GPIO8 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO8_LD16 (GLAMO_GPIO8 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO9 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 1)
+#define GLAMO_GPIO9_INPUT (GLAMO_GPIO9 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO9_OUTPUT (GLAMO_GPIO9 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO9_LD17 (GLAMO_GPIO9 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO10 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 2)
+#define GLAMO_GPIO10_INPUT (GLAMO_GPIO10 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO10_OUTPUT (GLAMO_GPIO10 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO10_LSCK (GLAMO_GPIO10 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO11 GLAMO_GPIONO(GLAMO_GPIO_BANKC, 3)
+#define GLAMO_GPIO11_INPUT (GLAMO_GPIO11 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO11_OUTPUT (GLAMO_GPIO11 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO11_LSDA (GLAMO_GPIO11 | GLAMO_GPIO_F_FUNC)
+
+#define GLAMO_GPIO12 GLAMO_GPIONO(GLAMO_GPIO_BANKD, 0)
+#define GLAMO_GPIO12_INPUT (GLAMO_GPIO12 | GLAMO_GPIO_F_IN)
+#define GLAMO_GPIO12_OUTPUT (GLAMO_GPIO12 | GLAMO_GPIO_F_OUT)
+#define GLAMO_GPIO12_LSA0 (GLAMO_GPIO12 | GLAMO_GPIO_F_FUNC)
+
+
+#define REG_OF_GPIO(gpio) (((gpio & 0xf000) >> 12)*2 \
+ + GLAMO_REG_GPIO_GEN1)
+#define NUM_OF_GPIO(gpio) ((gpio & 0x0f00) >> 8)
+#define GPIO_OUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 0))
+#define OUTPUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 4))
+#define INPUT_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 8))
+#define FUNC_BIT(gpio) (1 << (NUM_OF_GPIO(gpio) + 12))
+
+void glamo_gpio_setpin(struct glamo_core *glamo, unsigned int pin,
+ unsigned int value);
+
+int glamo_gpio_getpin(struct glamo_core *glamo, unsigned int pin);
+
+void glamo_gpio_cfgpin(struct glamo_core *glamo, unsigned int pinfunc);
+
+
+#endif /* _GLAMO_GPIO */
--- /dev/null
+++ b/include/linux/gta02_hdq.h
@@ -0,0 +1,18 @@
+#ifndef __GTA02HDQ_H__
+#define __GTA02HDQ_H__
+
+/* platform data */
+
+struct gta02_hdq_platform_data {
+ /*
+ * give an opportunity to use us as parent for
+ * devices that depend on us
+ */
+ void (*attach_child_devices)(struct device *parent_device);
+};
+
+int gta02hdq_read(int address);
+int gta02hdq_write(int address, u8 data);
+int gta02hdq_initialized(void);
+
+#endif
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -83,6 +83,9 @@
#define I2C_DRIVERID_CS5345 96 /* cs5345 audio processor */
#define I2C_DRIVERID_OV7670 1048 /* Omnivision 7670 camera */
+#define I2C_DRIVERID_PCF50606 1049
+#define I2C_DRIVERID_PCF50633 1051
+#define I2C_DRIVERID_PCA9632 1052
/*
* ---- Adapter types ----------------------------------------------------
--- /dev/null
+++ b/include/linux/jbt6k74.h
@@ -0,0 +1,14 @@
+#ifndef __JBT6K74_H__
+#define __JBT6K74_H__
+
+#include <linux/spi/spi.h>
+#include <linux/device.h>
+
+
+struct jbt6k74_platform_data {
+ void (*reset)(int devindex, int level);
+ void (*resuming)(int devindex); /* called when LCM is resumed */
+ void (*probe_completed)(struct device *dev);
+};
+
+#endif
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -225,6 +225,8 @@
extern int printk_ratelimit(void);
extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
unsigned int interval_msec);
+extern void (*printk_emergency_debug_spew_init)(void);
+extern void (*printk_emergency_debug_spew_send_string)(const char *);
#else
static inline int vprintk(const char *s, va_list args)
__attribute__ ((format (printf, 1, 0)));
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -1,7 +1,6 @@
#ifndef LINUX_KEXEC_H
#define LINUX_KEXEC_H
-#ifdef CONFIG_KEXEC
#include <linux/types.h>
#include <linux/list.h>
#include <linux/linkage.h>
@@ -11,6 +10,8 @@
#include <linux/elf.h>
#include <asm/kexec.h>
+#ifdef CONFIG_KEXEC
+
/* Verify architecture specific macros are defined */
#ifndef KEXEC_SOURCE_MEMORY_LIMIT
--- /dev/null
+++ b/include/linux/lis302dl.h
@@ -0,0 +1,154 @@
+#ifndef _LINUX_LIS302DL_H
+#define _LINUX_LIS302DL_H
+
+#include <linux/types.h>
+#include <linux/spi/spi.h>
+#include <linux/input.h>
+
+
+struct lis302dl_info;
+
+struct lis302dl_platform_data {
+ char *name;
+ unsigned long pin_chip_select;
+ unsigned long pin_clk;
+ unsigned long pin_mosi;
+ unsigned long pin_miso;
+ int open_drain;
+ int interrupt;
+ void (*lis302dl_bitbang)(struct lis302dl_info *lis, u8 *tx,
+ int tx_bytes, u8 *rx, int rx_bytes);
+ void (*lis302dl_suspend_io)(struct lis302dl_info *, int resuming);
+ int (*lis302dl_bitbang_reg_read)(struct lis302dl_info *, u8 reg);
+ void (*lis302dl_bitbang_reg_write)(struct lis302dl_info *, u8 reg,
+ u8 val);
+};
+
+struct lis302dl_info {
+ struct lis302dl_platform_data *pdata;
+ struct device *dev;
+ struct input_dev *input_dev;
+ unsigned int flags;
+ unsigned int threshold;
+ unsigned int duration;
+ struct {
+ unsigned int threshold; /* mg */
+ unsigned int duration; /* ms */
+ } wakeup;
+ u_int8_t regs[0x40];
+};
+
+enum lis302dl_reg {
+ LIS302DL_REG_WHO_AM_I = 0x0f,
+ LIS302DL_REG_CTRL1 = 0x20,
+ LIS302DL_REG_CTRL2 = 0x21,
+ LIS302DL_REG_CTRL3 = 0x22,
+ LIS302DL_REG_HP_FILTER_RESET = 0x23,
+ LIS302DL_REG_STATUS = 0x27,
+ LIS302DL_REG_OUT_X = 0x29,
+ LIS302DL_REG_OUT_Y = 0x2b,
+ LIS302DL_REG_OUT_Z = 0x2d,
+ LIS302DL_REG_FF_WU_CFG_1 = 0x30,
+ LIS302DL_REG_FF_WU_SRC_1 = 0x31,
+ LIS302DL_REG_FF_WU_THS_1 = 0x32,
+ LIS302DL_REG_FF_WU_DURATION_1 = 0x33,
+ LIS302DL_REG_FF_WU_CFG_2 = 0x34,
+ LIS302DL_REG_FF_WU_SRC_2 = 0x35,
+ LIS302DL_REG_FF_WU_THS_2 = 0x36,
+ LIS302DL_REG_FF_WU_DURATION_2 = 0x37,
+ LIS302DL_REG_CLICK_CFG = 0x38,
+ LIS302DL_REG_CLICK_SRC = 0x39,
+ LIS302DL_REG_CLICK_THSY_X = 0x3b,
+ LIS302DL_REG_CLICK_THSZ = 0x3c,
+ LIS302DL_REG_CLICK_TIME_LIMIT = 0x3d,
+ LIS302DL_REG_CLICK_LATENCY = 0x3e,
+ LIS302DL_REG_CLICK_WINDOW = 0x3f,
+};
+
+enum lis302dl_reg_ctrl1 {
+ LIS302DL_CTRL1_Xen = 0x01,
+ LIS302DL_CTRL1_Yen = 0x02,
+ LIS302DL_CTRL1_Zen = 0x04,
+ LIS302DL_CTRL1_STM = 0x08,
+ LIS302DL_CTRL1_STP = 0x10,
+ LIS302DL_CTRL1_FS = 0x20,
+ LIS302DL_CTRL1_PD = 0x40,
+ LIS302DL_CTRL1_DR = 0x80,
+};
+
+enum lis302dl_reg_ctrl2 {
+ LIS302DL_CTRL2_HPC1 = 0x01,
+ LIS302DL_CTRL2_HPC2 = 0x02,
+ LIS302DL_CTRL2_HPFF1 = 0x04,
+ LIS302DL_CTRL2_HPFF2 = 0x08,
+ LIS302DL_CTRL2_FDS = 0x10,
+ LIS302DL_CTRL2_BOOT = 0x40,
+ LIS302DL_CTRL2_SIM = 0x80,
+};
+enum lis302dl_reg_ctrl3 {
+ LIS302DL_CTRL3_PP_OD = 0x40,
+ LIS302DL_CTRL3_IHL = 0x80,
+};
+
+enum lis302dl_reg_status {
+ LIS302DL_STATUS_XDA = 0x01,
+ LIS302DL_STATUS_YDA = 0x02,
+ LIS302DL_STATUS_ZDA = 0x04,
+ LIS302DL_STATUS_XYZDA = 0x08,
+ LIS302DL_STATUS_XOR = 0x10,
+ LIS302DL_STATUS_YOR = 0x20,
+ LIS302DL_STATUS_ZOR = 0x40,
+ LIS302DL_STATUS_XYZOR = 0x80,
+};
+
+/* Wakeup/freefall interrupt defs */
+enum lis302dl_reg_ffwucfg {
+ LIS302DL_FFWUCFG_XLIE = 0x01,
+ LIS302DL_FFWUCFG_XHIE = 0x02,
+ LIS302DL_FFWUCFG_YLIE = 0x04,
+ LIS302DL_FFWUCFG_YHIE = 0x08,
+ LIS302DL_FFWUCFG_ZLIE = 0x10,
+ LIS302DL_FFWUCFG_ZHIE = 0x20,
+ LIS302DL_FFWUCFG_LIR = 0x40,
+ LIS302DL_FFWUCFG_AOI = 0x80,
+};
+
+enum lis302dl_reg_ffwuths {
+ LIS302DL_FFWUTHS_DCRM = 0x80,
+};
+
+enum lis302dl_reg_ffwusrc {
+ LIS302DL_FFWUSRC_XL = 0x01,
+ LIS302DL_FFWUSRC_XH = 0x02,
+ LIS302DL_FFWUSRC_YL = 0x04,
+ LIS302DL_FFWUSRC_YH = 0x08,
+ LIS302DL_FFWUSRC_ZL = 0x10,
+ LIS302DL_FFWUSRC_ZH = 0x20,
+ LIS302DL_FFWUSRC_IA = 0x40,
+};
+
+enum lis302dl_reg_cloik_src {
+ LIS302DL_CLICKSRC_SINGLE_X = 0x01,
+ LIS302DL_CLICKSRC_DOUBLE_X = 0x02,
+ LIS302DL_CLICKSRC_SINGLE_Y = 0x04,
+ LIS302DL_CLICKSRC_DOUBLE_Y = 0x08,
+ LIS302DL_CLICKSRC_SINGLE_Z = 0x10,
+ LIS302DL_CLICKSRC_DOUBLE_Z = 0x20,
+ LIS302DL_CLICKSRC_IA = 0x40,
+};
+
+#define LIS302DL_WHO_AM_I_MAGIC 0x3b
+
+#define LIS302DL_F_WUP_FF_1 0x0001 /* wake up from free fall */
+#define LIS302DL_F_WUP_FF_2 0x0002
+#define LIS302DL_F_WUP_FF 0x0003
+#define LIS302DL_F_WUP_CLICK 0x0004
+#define LIS302DL_F_POWER 0x0010
+#define LIS302DL_F_FS 0x0020 /* ADC full scale */
+#define LIS302DL_F_INPUT_OPEN 0x0040 /* Set if input device is opened */
+#define LIS302DL_F_IRQ_WAKE 0x0080 /* IRQ is setup in wake mode */
+#define LIS302DL_F_DR 0x0100 /* Data rate, 400Hz/100Hz */
+
+
+#endif /* _LINUX_LIS302DL_H */
+
--- /dev/null
+++ b/include/linux/logger.h
@@ -0,0 +1,48 @@
+/* include/linux/logger.h
+ *
+ * Copyright (C) 2007-2008 Google, Inc.
+ * Author: Robert Love <rlove@android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_LOGGER_H
+#define _LINUX_LOGGER_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+struct logger_entry {
+ __u16 len; /* length of the payload */
+ __u16 __pad; /* no matter what, we get 2 bytes of padding */
+ __s32 pid; /* generating process's pid */
+ __s32 tid; /* generating process's tid */
+ __s32 sec; /* seconds since Epoch */
+ __s32 nsec; /* nanoseconds */
+ char msg[0]; /* the entry's payload */
+};
+
+#define LOGGER_LOG_RADIO "log_radio" /* radio-related messages */
+#define LOGGER_LOG_EVENTS "log_events" /* system/hardware events */
+#define LOGGER_LOG_MAIN "log_main" /* everything else */
+
+#define LOGGER_ENTRY_MAX_LEN (4*1024)
+#define LOGGER_ENTRY_MAX_PAYLOAD \
+ (LOGGER_ENTRY_MAX_LEN - sizeof(struct logger_entry))
+
+#define __LOGGERIO 0xAE
+
+#define LOGGER_GET_LOG_BUF_SIZE _IO(__LOGGERIO, 1) /* size of log */
+#define LOGGER_GET_LOG_LEN _IO(__LOGGERIO, 2) /* used log len */
+#define LOGGER_GET_NEXT_ENTRY_LEN _IO(__LOGGERIO, 3) /* next entry len */
+#define LOGGER_FLUSH_LOG _IO(__LOGGERIO, 4) /* flush log */
+
+#endif /* _LINUX_LOGGER_H */
--- /dev/null
+++ b/include/linux/mfd/pcf50606/adc.h
@@ -0,0 +1,87 @@
+/*
+ * adc.h -- Driver for NXP PCF50606 ADC
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_ADC_H
+#define __LINUX_MFD_PCF50606_ADC_H
+
+#include <linux/platform_device.h>
+
+/* ADC Registers */
+#define PCF50606_REG_ADCC1 0x2e
+#define PCF50606_REG_ADCC2 0x2f
+#define PCF50606_REG_ADCS1 0x30
+#define PCF50606_REG_ADCS2 0x31
+#define PCF50606_REG_ADCS3 0x32
+
+#define PCF50606_ADCC1_TSCMODACT 0x01
+#define PCF50606_ADCC1_TSCMODSTB 0x02
+#define PCF50606_ADCC1_TRATSET 0x04
+#define PCF50606_ADCC1_NTCSWAPE 0x08
+#define PCF50606_ADCC1_NTCSWAOFF 0x10
+#define PCF50606_ADCC1_EXTSYNCBREAK 0x20
+ /* reserved */
+#define PCF50606_ADCC1_TSCINT 0x80
+
+#define PCF50606_ADCC2_ADCSTART 0x01
+ /* see enum pcf50606_adcc2_adcmux */
+#define PCF50606_ADCC2_SYNC_NONE 0x00
+#define PCF50606_ADCC2_SYNC_TXON 0x20
+#define PCF50606_ADCC2_SYNC_PWREN1 0x40
+#define PCF50606_ADCC2_SYNC_PWREN2 0x60
+#define PCF50606_ADCC2_RES_10BIT 0x00
+#define PCF50606_ADCC2_RES_8BIT 0x80
+
+#define PCF50606_ADCC2_ADCMUX_MASK (0xf << 1)
+
+#define ADCMUX_SHIFT 1
+#define PCF50606_ADCMUX_BATVOLT_RES (0x0 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_BATVOLT_SUBTR (0x1 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_ADCIN1_RES (0x2 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_ADCIN1_SUBTR (0x3 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_BATTEMP (0x4 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_ADCIN2 (0x5 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_ADCIN3 (0x6 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_ADCIN3_RATIO (0x7 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_XPOS (0x8 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_YPOS (0x9 << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_P1 (0xa << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_P2 (0xb << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_BATVOLT_ADCIN1 (0xc << ADCMUX_SHIFT)
+#define PCF50606_ADCMUX_XY_SEQUENCE (0xe << ADCMUX_SHIFT)
+#define PCF50606_P1_P2_RESISTANCE (0xf << ADCMUX_SHIFT)
+
+#define PCF50606_ADCS2_ADCRDY 0x80
+
+struct pcf50606;
+
+#define PCF50606_MAX_ADC_FIFO_DEPTH 8
+
+struct pcf50606_adc_request;
+
+struct pcf50606_adc {
+ struct platform_device *pdev;
+
+ /* Private stuff */
+ struct pcf50606_adc_request *queue[PCF50606_MAX_ADC_FIFO_DEPTH];
+ int queue_head;
+ int queue_tail;
+ struct mutex queue_mutex;
+};
+
+extern int
+pcf50606_adc_async_read(struct pcf50606 *pcf, int mux, int avg,
+ void (*callback)(struct pcf50606 *, void *, int),
+ void *callback_param);
+extern int
+pcf50606_adc_sync_read(struct pcf50606 *pcf, int mux, int avg);
+
+#endif /* __LINUX_PCF50606_ADC_H */
--- /dev/null
+++ b/include/linux/mfd/pcf50606/core.h
@@ -0,0 +1,163 @@
+/*
+ * core.h -- Core driver for NXP PCF50606
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_CORE_H
+#define __LINUX_MFD_PCF50606_CORE_H
+
+#include <linux/i2c.h>
+#include <linux/workqueue.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/power_supply.h>
+
+#include <linux/mfd/pcf50606/pmic.h>
+#include <linux/mfd/pcf50606/input.h>
+#include <linux/mfd/pcf50606/mbc.h>
+#include <linux/mfd/pcf50606/rtc.h>
+#include <linux/mfd/pcf50606/adc.h>
+#include <linux/mfd/pcf50606/wdt.h>
+
+struct pcf50606;
+
+struct pcf50606_platform_data {
+ struct regulator_init_data reg_init_data[PCF50606_NUM_REGULATORS];
+
+ char **batteries;
+ int num_batteries;
+
+ /* Callbacks */
+ void (*probe_done)(struct pcf50606 *);
+ void (*mbc_event_callback)(struct pcf50606 *, int);
+ void (*regulator_registered)(struct pcf50606 *, int);
+ void (*force_shutdown)(struct pcf50606 *);
+
+ u8 resumers[3];
+
+ /* Runtime data - filled by driver afer probe */
+ struct pcf50606 *pcf;
+};
+
+struct pcf50606_irq {
+ void (*handler)(struct pcf50606 *, int, void *);
+ void *data;
+};
+
+int pcf50606_irq_mask(struct pcf50606 *pcf, int irq);
+int pcf50606_irq_unmask(struct pcf50606 *pcf, int irq);
+int pcf50606_irq_mask_get(struct pcf50606 *pcf, int irq);
+
+int pcf50606_read_block(struct pcf50606 *, u8 reg,
+ int nr_regs, u8 *data);
+int pcf50606_write_block(struct pcf50606 *pcf, u8 reg,
+ int nr_regs, u8 *data);
+u8 pcf50606_reg_read(struct pcf50606 *, u8 reg);
+int pcf50606_reg_write(struct pcf50606 *pcf, u8 reg, u8 val);
+
+int pcf50606_reg_set_bit_mask(struct pcf50606 *pcf, u8 reg, u8 mask, u8 val);
+int pcf50606_reg_clear_bits(struct pcf50606 *pcf, u8 reg, u8 bits);
+
+/* Interrupt registers */
+
+#define PCF50606_REG_INT1 0x02
+#define PCF50606_REG_INT2 0x03
+#define PCF50606_REG_INT3 0x04
+
+#define PCF50606_REG_INT1M 0x05
+#define PCF50606_REG_INT2M 0x06
+#define PCF50606_REG_INT3M 0x07
+
+enum {
+ /* Chip IRQs */
+ PCF50606_IRQ_ONKEYR,
+ PCF50606_IRQ_ONKEYF,
+ PCF50606_IRQ_ONKEY1S,
+ PCF50606_IRQ_EXTONR,
+ PCF50606_IRQ_EXTONF,
+ PCF50606_IRQ_SECOND,
+ PCF50606_IRQ_ALARM,
+ PCF50606_IRQ_CHGINS,
+ PCF50606_IRQ_CHGRM,
+ PCF50606_IRQ_CHGFOK,
+ PCF50606_IRQ_CHGERR,
+ PCF50606_IRQ_CHGFRDY,
+ PCF50606_IRQ_CHGPROT,
+ PCF50606_IRQ_CHGWD10S,
+ PCF50606_IRQ_CHGWDEXP,
+ PCF50606_IRQ_ADCRDY,
+ PCF50606_IRQ_ACDINS,
+ PCF50606_IRQ_ACDREM,
+ PCF50606_IRQ_TSCPRES,
+ PCF50606_IRQ_LOWBAT,
+ PCF50606_IRQ_HIGHTMP,
+
+ /* Always last */
+ PCF50606_NUM_IRQ,
+};
+
+struct pcf50606 {
+ struct device *dev;
+ struct i2c_client *i2c_client;
+
+ struct pcf50606_platform_data *pdata;
+ int irq;
+ struct pcf50606_irq irq_handler[PCF50606_NUM_IRQ];
+ struct work_struct irq_work;
+ struct mutex lock;
+
+ u8 mask_regs[3];
+
+ u8 suspend_irq_masks[3];
+ u8 resume_reason[3];
+ int is_suspended;
+
+ int onkey1s_held;
+
+ struct pcf50606_pmic pmic;
+ struct pcf50606_input input;
+ struct pcf50606_mbc mbc;
+ struct pcf50606_rtc rtc;
+ struct pcf50606_adc adc;
+ struct pcf50606_wdt wdt;
+};
+
+enum pcf50606_reg_int1 {
+ PCF50606_INT1_ONKEYR = 0x01, /* ONKEY rising edge */
+ PCF50606_INT1_ONKEYF = 0x02, /* ONKEY falling edge */
+ PCF50606_INT1_ONKEY1S = 0x04, /* OMKEY at least 1sec low */
+ PCF50606_INT1_EXTONR = 0x08, /* EXTON rising edge */
+ PCF50606_INT1_EXTONF = 0x10, /* EXTON falling edge */
+ PCF50606_INT1_SECOND = 0x40, /* RTC periodic second interrupt */
+ PCF50606_INT1_ALARM = 0x80, /* RTC alarm time is reached */
+};
+
+enum pcf50606_reg_int2 {
+ PCF50606_INT2_CHGINS = 0x01, /* Charger inserted */
+ PCF50606_INT2_CHGRM = 0x02, /* Charger removed */
+ PCF50606_INT2_CHGFOK = 0x04, /* Fast charging OK */
+ PCF50606_INT2_CHGERR = 0x08, /* Error in charging mode */
+ PCF50606_INT2_CHGFRDY = 0x10, /* Fast charge completed */
+ PCF50606_INT2_CHGPROT = 0x20, /* Charging protection interrupt */
+ PCF50606_INT2_CHGWD10S = 0x40, /* Charger watchdig expires in 10s */
+ PCF50606_INT2_CHGWDEXP = 0x80, /* Charger watchdog expires */
+};
+
+enum pcf50606_reg_int3 {
+ PCF50606_INT3_ADCRDY = 0x01, /* ADC conversion finished */
+ PCF50606_INT3_ACDINS = 0x02, /* Accessory inserted */
+ PCF50606_INT3_ACDREM = 0x04, /* Accessory removed */
+ PCF50606_INT3_TSCPRES = 0x08, /* Touch screen pressed */
+ PCF50606_INT3_LOWBAT = 0x40, /* Low battery voltage */
+ PCF50606_INT3_HIGHTMP = 0x80, /* High temperature */
+};
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/gpo.h
@@ -0,0 +1,43 @@
+/*
+ * gpo.h -- GPO driver for NXP PCF50606
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_GPO_H
+#define __LINUX_MFD_PCF50606_GPO_H
+
+#define PCF50606_REG_GPOC1 0x38
+#define PCF50606_REG_GPOC2 0x39
+#define PCF50606_REG_GPOC3 0x3a
+#define PCF50606_REG_GPOC4 0x3b
+#define PCF50606_REG_GPOC5 0x3c
+
+#define PCF50606_GPO1 PCF50606_REG_GPOC1
+#define PCF50606_GPO2 PCF50606_REG_GPOC1
+#define PCF50606_GPOOD1 PCF50606_REG_GPOC2
+#define PCF50606_GPOOD2 PCF50606_REG_GPOC3
+#define PCF50606_GPOOD3 PCF50606_REG_GPOC4
+#define PCF50606_GPOOD4 PCF50606_REG_GPOC5
+
+#define PCF50606_GPOCFG_GPOSEL_MASK 0x07
+
+struct pcf50606;
+
+void pcf50606_gpo_set_active(struct pcf50606 *pcf, int gpo, int value);
+int pcf50606_gpo_get_active(struct pcf50606 *pcf, int gpo);
+void pcf50606_gpo_set_standby(struct pcf50606 *pcf, int gpo, int value);
+int pcf50606_gpo_get_standby(struct pcf50606 *pcf, int gpo);
+
+void pcf50606_gpo_invert_set(struct pcf50606 *, int gpo, int invert);
+int pcf50606_gpo_invert_get(struct pcf50606 *pcf, int gpo);
+
+#endif /* __LINUX_MFD_PCF50606_GPIO_H */
+
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/input.h
@@ -0,0 +1,37 @@
+/*
+ * input.h -- Input driver for NXP PCF50606
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_INPUT_H
+#define __LINUX_MFD_PCF50606_INPUT_H
+
+#include <linux/platform_device.h>
+#include <linux/input.h>
+
+#define PFC50606_OOCS_ONKEY 0x01
+#define PCF50606_OOCS_EXTON 0x02
+
+#define PCF50606_OOCC2_ONKEYDB_NONE 0x00
+#define PCF50606_OOCC2_ONKEYDB_14ms 0x01
+#define PCF50606_OOCC2_ONKEYDB_62ms 0x02
+#define PCF50606_OOCC2_ONKEYDB_500ms 0x03
+#define PCF50606_OOCC2_EXTONDB_NONE 0x00
+#define PCF50606_OOCC2_EXTONDB_14ms 0x04
+#define PCF50606_OOCC2_EXTONDB_62ms 0x08
+#define PCF50606_OOCC2_EXTONDB_500ms 0x0c
+
+struct pcf50606_input {
+ struct input_dev *input_dev;
+ struct platform_device *pdev;
+};
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/led.h
@@ -0,0 +1,22 @@
+/*
+ * led.h -- LED driver for NXP PCF50606
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_LED_H
+#define __LINUX_MFD_PCF50606_LED_H
+
+#define PCF50606_REG_LEDC1 0x36
+#define PCF50606_REG_LEDC2 0x37
+
+#include <linux/platform_device.h>
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/mbc.h
@@ -0,0 +1,53 @@
+/*
+ * mbc.h -- Driver for NXP PCF50606 Main Battery Charger
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_MBC_H
+#define __LINUX_MFD_PCF50606_MBC_H
+
+#include <linux/platform_device.h>
+
+#define PCF50606_REG_MBCC1 0x29
+#define PCF50606_REG_MBCC2 0x2a
+#define PCF50606_REG_MBCC3 0x2b
+#define PCF50606_REG_MBCS1 0x2c
+
+enum pcf50606_reg_mbcc1 {
+ PCF50606_MBCC1_CHGAPE = 0x01,
+ PCF50606_MBCC1_AUTOFST = 0x02,
+#define PCF50606_MBCC1_CHGMOD_MASK 0x1c
+#define PCF50606_MBCC1_CHGMOD_SHIFT 2
+ PCF50606_MBCC1_CHGMOD_QUAL = 0x00,
+ PCF50606_MBCC1_CHGMOD_PRE = 0x04,
+ PCF50606_MBCC1_CHGMOD_TRICKLE = 0x08,
+ PCF50606_MBCC1_CHGMOD_FAST_CCCV = 0x0c,
+ PCF50606_MBCC1_CHGMOD_FAST_NOCC = 0x10,
+ PCF50606_MBCC1_CHGMOD_FAST_NOCV = 0x14,
+ PCF50606_MBCC1_CHGMOD_FAST_SW = 0x18,
+ PCF50606_MBCC1_CHGMOD_IDLE = 0x1c,
+ PCF50606_MBCC1_DETMOD_LOWCHG = 0x20,
+ PCF50606_MBCC1_DETMOD_WDRST = 0x40,
+};
+
+struct pcf50606;
+
+void pcf50606_mbc_usb_curlim_set(struct pcf50606 *pcf, int ma);
+
+struct pcf50606_mbc {
+ int charger_online;
+ int charger_active;
+
+ struct power_supply charger;
+
+ struct platform_device *pdev;
+};
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/pmic.h
@@ -0,0 +1,82 @@
+#ifndef __LINUX_MFD_PCF50606_PMIC_H
+#define __LINUX_MFD_PCF50606_PMIC_H
+
+#include <linux/platform_device.h>
+
+#define PCF50606_REG_DCDC1 0x1b
+#define PCF50606_REG_DCDC2 0x1c
+#define PCF50606_REG_DCDC3 0x1d
+#define PCF50606_REG_DCDC4 0x1e
+#define PCF50606_REG_DCDEC1 0x1f
+#define PCF50606_REG_DCDEC2 0x20
+#define PCF50606_REG_DCUDC1 0x21
+#define PCF50606_REG_DCUDC2 0x22
+#define PCF50606_REG_IOREGC 0x23
+#define PCF50606_REG_D1REGC1 0x24
+#define PCF50606_REG_D2REGC1 0x25
+#define PCF50606_REG_D3REGC1 0x26
+#define PCF50606_REG_LPREGC1 0x27
+#define PCF50606_REG_LPREGC2 0x28
+
+/* used by PSSC, PWROKM, PWROKS, */
+enum pcf50606_regu {
+ PCF50606_REGU_DCD = 0x01, /* DCD in phase 2 */
+ PCF50606_REGU_DCDE = 0x02, /* DCDE in phase 2 */
+ PCF50606_REGU_DCUD = 0x04, /* DCDU in phase 2 */
+ PCF50606_REGU_IO = 0x08, /* IO in phase 2 */
+ PCF50606_REGU_D1 = 0x10, /* D1 in phase 2 */
+ PCF50606_REGU_D2 = 0x20, /* D2 in phase 2 */
+ PCF50606_REGU_D3 = 0x40, /* D3 in phase 2 */
+ PCF50606_REGU_LP = 0x80, /* LP in phase 2 */
+};
+
+enum pcf50606_reg_dcdc4 {
+ PCF50606_DCDC4_MODE_AUTO = 0x00,
+ PCF50606_DCDC4_MODE_PWM = 0x01,
+ PCF50606_DCDC4_MODE_PCF = 0x02,
+ PCF50606_DCDC4_OFF_FLOAT = 0x00,
+ PCF50606_DCDC4_OFF_BYPASS = 0x04,
+ PCF50606_DCDC4_OFF_PULLDOWN = 0x08,
+ PCF50606_DCDC4_CURLIM_500mA = 0x00,
+ PCF50606_DCDC4_CURLIM_750mA = 0x10,
+ PCF50606_DCDC4_CURLIM_1000mA = 0x20,
+ PCF50606_DCDC4_CURLIM_1250mA = 0x30,
+ PCF50606_DCDC4_TOGGLE = 0x40,
+ PCF50606_DCDC4_REGSEL_DCDC2 = 0x80,
+};
+
+enum pcf50606_reg_dcdec2 {
+ PCF50606_DCDEC2_MODE_AUTO = 0x00,
+ PCF50606_DCDEC2_MODE_PWM = 0x01,
+ PCF50606_DCDEC2_MODE_PCF = 0x02,
+ PCF50606_DCDEC2_OFF_FLOAT = 0x00,
+ PCF50606_DCDEC2_OFF_BYPASS = 0x04,
+};
+
+enum pcf50606_reg_dcudc2 {
+ PCF50606_DCUDC2_MODE_AUTO = 0x00,
+ PCF50606_DCUDC2_MODE_PWM = 0x01,
+ PCF50606_DCUDC2_MODE_PCF = 0x02,
+ PCF50606_DCUDC2_OFF_FLOAT = 0x00,
+ PCF50606_DCUDC2_OFF_BYPASS = 0x04,
+};
+
+enum pcf50606_regulator_id {
+ PCF50606_REGULATOR_DCD,
+ PCF50606_REGULATOR_DCDE,
+ PCF50606_REGULATOR_DCUD,
+ PCF50606_REGULATOR_D1REG,
+ PCF50606_REGULATOR_D2REG,
+ PCF50606_REGULATOR_D3REG,
+ PCF50606_REGULATOR_LPREG,
+ PCF50606_REGULATOR_IOREG,
+
+ /* Always last */
+ PCF50606_NUM_REGULATORS
+};
+
+struct pcf50606_pmic {
+ struct platform_device *pdev[PCF50606_NUM_REGULATORS];
+};
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/rtc.h
@@ -0,0 +1,43 @@
+/*
+ * rtc.h -- RTC driver for NXP PCF50606
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_RTC_H
+#define __LINUX_MFD_PCF50606_RTC_H
+
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+
+#define PCF50606_REG_RTCSC 0x0a /* Second */
+#define PCF50606_REG_RTCMN 0x0b /* Minute */
+#define PCF50606_REG_RTCHR 0x0c /* Hour */
+#define PCF50606_REG_RTCWD 0x0d /* Weekday */
+#define PCF50606_REG_RTCDT 0x0e /* Day */
+#define PCF50606_REG_RTCMT 0x0f /* Month */
+#define PCF50606_REG_RTCYR 0x10 /* Year */
+#define PCF50606_REG_RTCSCA 0x11 /* Alarm Second */
+#define PCF50606_REG_RTCMNA 0x12 /* Alarm Minute */
+#define PCF50606_REG_RTCHRA 0x13 /* Alarm Hour */
+#define PCF50606_REG_RTCWDA 0x14 /* Alarm Weekday */
+#define PCF50606_REG_RTCDTA 0x15 /* Alarm Day */
+#define PCF50606_REG_RTCMTA 0x16 /* Alarm Month */
+#define PCF50606_REG_RTCYRA 0x17 /* Alarm Year */
+
+struct pcf50606_rtc {
+ int alarm_enabled;
+ int second_enabled;
+
+ struct rtc_device *rtc_dev;
+ struct platform_device *pdev;
+};
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50606/wdt.h
@@ -0,0 +1,32 @@
+/*
+ * wdt.h -- WDT driver for NXP PCF50606
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50606_WDT_H
+#define __LINUX_MFD_PCF50606_WDT_H
+
+#define PCF50606_REG_OOCC1 0x08
+#define PCF50606_REG_OOCS 0x01
+
+#define PCF50606_OOCS_WDTEXP 0x80
+#define PCF50606_OOCC1_WDTRST 0x08
+
+#define CLOSE_STATE_NOT 0x0000
+#define CLOSE_STATE_ALLOW 0x2342
+
+struct pcf50606;
+
+struct pcf50606_wdt {
+ struct platform_device *pdev;
+};
+#endif /* __LINUX_MFD_PCF50606_WDT_H */
+
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/adc.h
@@ -0,0 +1,88 @@
+/*
+ * adc.h -- Driver for NXP PCF50633 ADC
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_ADC_H
+#define __LINUX_MFD_PCF50633_ADC_H
+
+#include <linux/platform_device.h>
+
+/* ADC Registers */
+#define PCF50633_REG_ADCC3 0x52
+#define PCF50633_REG_ADCC2 0x53
+#define PCF50633_REG_ADCC1 0x54
+#define PCF50633_REG_ADCS1 0x55
+#define PCF50633_REG_ADCS2 0x56
+#define PCF50633_REG_ADCS3 0x57
+
+#define PCF50633_ADCC1_ADCSTART 0x01
+#define PCF50633_ADCC1_RES_10BIT 0x02
+#define PCF50633_ADCC1_AVERAGE_NO 0x00
+#define PCF50633_ADCC1_AVERAGE_4 0x04
+#define PCF50633_ADCC1_AVERAGE_8 0x08
+#define PCF50633_ADCC1_AVERAGE_16 0x0c
+#define PCF50633_ADCC1_MUX_BATSNS_RES 0x00
+#define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10
+#define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20
+#define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30
+#define PCF50633_ADCC1_MUX_BATTEMP 0x60
+#define PCF50633_ADCC1_MUX_ADCIN1 0x70
+#define PCF50633_ADCC1_AVERAGE_MASK 0x0c
+#define PCF50633_ADCC1_ADCMUX_MASK 0xf0
+
+#define PCF50633_ADCC2_RATIO_NONE 0x00
+#define PCF50633_ADCC2_RATIO_BATTEMP 0x01
+#define PCF50633_ADCC2_RATIO_ADCIN1 0x02
+#define PCF50633_ADCC2_RATIO_BOTH 0x03
+#define PCF50633_ADCC2_RATIOSETTL_100US 0x04
+
+#define PCF50633_ADCC3_ACCSW_EN 0x01
+#define PCF50633_ADCC3_NTCSW_EN 0x04
+#define PCF50633_ADCC3_RES_DIV_TWO 0x10
+#define PCF50633_ADCC3_RES_DIV_THREE 0x00
+
+#define PCF50633_ADCS3_REF_NTCSW 0x00
+#define PCF50633_ADCS3_REF_ACCSW 0x10
+#define PCF50633_ADCS3_REF_2V0 0x20
+#define PCF50633_ADCS3_REF_VISA 0x30
+#define PCF50633_ADCS3_REF_2V0_2 0x70
+#define PCF50633_ADCS3_ADCRDY 0x80
+
+#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03
+#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c
+#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2
+#define PCF50633_ASCS3_REF_MASK 0x70
+
+
+struct pcf50633;
+
+#define PCF50633_MAX_ADC_FIFO_DEPTH 8
+
+struct pcf50633_adc_request;
+
+struct pcf50633_adc {
+ struct platform_device *pdev;
+
+ /* Private stuff */
+ struct pcf50633_adc_request *queue[PCF50633_MAX_ADC_FIFO_DEPTH];
+ int queue_head;
+ int queue_tail;
+ struct mutex queue_mutex;
+};
+
+extern int
+pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
+ void (*callback)(struct pcf50633 *, void *, int),
+ void *callback_param);
+extern int
+pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
+
+#endif /* __LINUX_PCF50633_ADC_H */
--- /dev/null
+++ b/include/linux/mfd/pcf50633/core.h
@@ -0,0 +1,212 @@
+/*
+ * core.h -- Core driver for NXP PCF50633
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_CORE_H
+#define __LINUX_MFD_PCF50633_CORE_H
+
+#include <linux/i2c.h>
+#include <linux/workqueue.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/power_supply.h>
+
+#include <linux/mfd/pcf50633/pmic.h>
+#include <linux/mfd/pcf50633/input.h>
+#include <linux/mfd/pcf50633/mbc.h>
+#include <linux/mfd/pcf50633/rtc.h>
+#include <linux/mfd/pcf50633/adc.h>
+#include <linux/mfd/pcf50633/gpio.h>
+
+struct pcf50633;
+
+struct pcf50633_platform_data {
+ struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
+
+ char **batteries;
+ int num_batteries;
+
+ /* Callbacks */
+ void (*probe_done)(struct pcf50633 *);
+ void (*mbc_event_callback)(struct pcf50633 *, int);
+ void (*regulator_registered)(struct pcf50633 *, int);
+ void (*force_shutdown)(struct pcf50633 *);
+
+ u8 resumers[5];
+
+ /* Runtime data - filled by driver afer probe */
+ struct pcf50633 *pcf;
+};
+
+struct pcf50633_irq {
+ void (*handler)(struct pcf50633 *, int, void *);
+ void *data;
+};
+
+int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
+int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
+int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
+
+int pcf50633_read_block(struct pcf50633 *, u8 reg,
+ int nr_regs, u8 *data);
+int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
+ int nr_regs, u8 *data);
+u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
+int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
+
+int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
+int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
+
+/* Interrupt registers */
+
+#define PCF50633_REG_INT1 0x02
+#define PCF50633_REG_INT2 0x03
+#define PCF50633_REG_INT3 0x04
+#define PCF50633_REG_INT4 0x05
+#define PCF50633_REG_INT5 0x06
+
+#define PCF50633_REG_INT1M 0x07
+#define PCF50633_REG_INT2M 0x08
+#define PCF50633_REG_INT3M 0x09
+#define PCF50633_REG_INT4M 0x0a
+#define PCF50633_REG_INT5M 0x0b
+
+enum {
+ /* Chip IRQs */
+ PCF50633_IRQ_ADPINS = 0,
+ PCF50633_IRQ_ADPREM,
+ PCF50633_IRQ_USBINS,
+ PCF50633_IRQ_USBREM,
+ PCF50633_IRQ_RESERVED1,
+ PCF50633_IRQ_RESERVED2,
+ PCF50633_IRQ_ALARM,
+ PCF50633_IRQ_SECOND,
+ PCF50633_IRQ_ONKEYR,
+ PCF50633_IRQ_ONKEYF,
+ PCF50633_IRQ_EXTON1R,
+ PCF50633_IRQ_EXTON1F,
+ PCF50633_IRQ_EXTON2R,
+ PCF50633_IRQ_EXTON2F,
+ PCF50633_IRQ_EXTON3R,
+ PCF50633_IRQ_EXTON3F,
+ PCF50633_IRQ_BATFULL,
+ PCF50633_IRQ_CHGHALT,
+ PCF50633_IRQ_THLIMON,
+ PCF50633_IRQ_THLIMOFF,
+ PCF50633_IRQ_USBLIMON,
+ PCF50633_IRQ_USBLIMOFF,
+ PCF50633_IRQ_ADCRDY,
+ PCF50633_IRQ_ONKEY1S,
+ PCF50633_IRQ_LOWSYS,
+ PCF50633_IRQ_LOWBAT,
+ PCF50633_IRQ_HIGHTMP,
+ PCF50633_IRQ_AUTOPWRFAIL,
+ PCF50633_IRQ_DWN1PWRFAIL,
+ PCF50633_IRQ_DWN2PWRFAIL,
+ PCF50633_IRQ_LEDPWRFAIL,
+ PCF50633_IRQ_LEDOVP,
+ PCF50633_IRQ_LDO1PWRFAIL,
+ PCF50633_IRQ_LDO2PWRFAIL,
+ PCF50633_IRQ_LDO3PWRFAIL,
+ PCF50633_IRQ_LDO4PWRFAIL,
+ PCF50633_IRQ_LDO5PWRFAIL,
+ PCF50633_IRQ_LDO6PWRFAIL,
+ PCF50633_IRQ_HCLDOPWRFAIL,
+ PCF50633_IRQ_HCLDOOVL,
+
+ /* Always last */
+ PCF50633_NUM_IRQ,
+};
+
+struct pcf50633 {
+ struct device *dev;
+ struct i2c_client *i2c_client;
+
+ struct pcf50633_platform_data *pdata;
+ int irq;
+ struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
+ struct work_struct irq_work;
+ struct mutex lock;
+
+ u8 mask_regs[5];
+
+ u8 suspend_irq_masks[5];
+ u8 resume_reason[5];
+ int is_suspended;
+
+ int onkey1s_held;
+
+ struct pcf50633_pmic pmic;
+ struct pcf50633_input input;
+ struct pcf50633_mbc mbc;
+ struct pcf50633_rtc rtc;
+ struct pcf50633_adc adc;
+};
+
+enum pcf50633_reg_int1 {
+ PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
+ PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
+ PCF50633_INT1_USBINS = 0x04, /* USB inserted */
+ PCF50633_INT1_USBREM = 0x08, /* USB removed */
+ /* reserved */
+ PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
+ PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
+};
+
+enum pcf50633_reg_int2 {
+ PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
+ PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
+ PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
+ PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
+ PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
+ PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
+ PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
+ PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
+};
+
+enum pcf50633_reg_int3 {
+ PCF50633_INT3_BATFULL = 0x01, /* Battery full */
+ PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
+ PCF50633_INT3_THLIMON = 0x04,
+ PCF50633_INT3_THLIMOFF = 0x08,
+ PCF50633_INT3_USBLIMON = 0x10,
+ PCF50633_INT3_USBLIMOFF = 0x20,
+ PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */
+ PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
+};
+
+enum pcf50633_reg_int4 {
+ PCF50633_INT4_LOWSYS = 0x01,
+ PCF50633_INT4_LOWBAT = 0x02,
+ PCF50633_INT4_HIGHTMP = 0x04,
+ PCF50633_INT4_AUTOPWRFAIL = 0x08,
+ PCF50633_INT4_DWN1PWRFAIL = 0x10,
+ PCF50633_INT4_DWN2PWRFAIL = 0x20,
+ PCF50633_INT4_LEDPWRFAIL = 0x40,
+ PCF50633_INT4_LEDOVP = 0x80,
+};
+
+enum pcf50633_reg_int5 {
+ PCF50633_INT5_LDO1PWRFAIL = 0x01,
+ PCF50633_INT5_LDO2PWRFAIL = 0x02,
+ PCF50633_INT5_LDO3PWRFAIL = 0x04,
+ PCF50633_INT5_LDO4PWRFAIL = 0x08,
+ PCF50633_INT5_LDO5PWRFAIL = 0x10,
+ PCF50633_INT5_LDO6PWRFAIL = 0x20,
+ PCF50633_INT5_HCLDOPWRFAIL = 0x40,
+ PCF50633_INT5_HCLDOOVL = 0x80,
+};
+
+/* misc. registers */
+#define PCF50633_REG_OOCSHDWN 0x0c
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/gpio.h
@@ -0,0 +1,51 @@
+/*
+ * gpio.h -- GPIO driver for NXP PCF50633
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_GPIO_H
+#define __LINUX_MFD_PCF50633_GPIO_H
+
+#define PCF50633_GPIO1 1
+#define PCF50633_GPIO2 2
+#define PCF50633_GPIO3 3
+#define PCF50633_GPO 4
+
+#define PCF50633_REG_GPIO1CFG 0x14
+#define PCF50633_REG_GPIO2CFG 0x15
+#define PCF50633_REG_GPIO3CFG 0x16
+#define PCF50633_REG_GPOCFG 0x17
+
+enum pcf50633_reg_gpocfg {
+ PCF50633_GPOCFG_GPOSEL_0 = 0x00,
+ PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
+ PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02,
+ PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03,
+ PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04,
+ PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05,
+ PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06,
+ PCF50633_GPOCFG_GPOSEL_1 = 0x07,
+ PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08,
+};
+#define PCF50633_GPOCFG_GPOSEL_MASK 0x07
+
+struct pcf50633;
+
+void pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, int on);
+int pcf50633_gpio_get(struct pcf50633 *pcf, int gpio);
+
+void pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert);
+int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio);
+
+void pcf50633_gpio_power_supply_set(struct pcf50633 *,
+ int gpio, int regulator, int on);
+#endif /* __LINUX_MFD_PCF50633_GPIO_H */
+
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/input.h
@@ -0,0 +1,29 @@
+/*
+ * input.h -- Input driver for NXP PCF50633
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_INPUT_H
+#define __LINUX_MFD_PCF50633_INPUT_H
+
+#include <linux/platform_device.h>
+#include <linux/input.h>
+
+#define PCF50633_OOCSTAT_ONKEY 0x01
+#define PCF50633_REG_OOCSTAT 0x12
+#define PCF50633_REG_OOCMODE 0x10
+
+struct pcf50633_input {
+ struct input_dev *input_dev;
+ struct platform_device *pdev;
+};
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/led.h
@@ -0,0 +1,24 @@
+/*
+ * led.h -- LED driver for NXP PCF50633
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_LED_H
+#define __LINUX_MFD_PCF50633_LED_H
+
+#include <linux/platform_device.h>
+
+#define PCF50633_REG_LEDOUT 0x28
+#define PCF50633_REG_LEDENA 0x29
+#define PCF50633_REG_LEDCTL 0x2a
+#define PCF50633_REG_LEDDIM 0x2b
+
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/mbc.h
@@ -0,0 +1,140 @@
+/*
+ * mbc.h -- Driver for NXP PCF50633 Main Battery Charger
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_MBC_H
+#define __LINUX_MFD_PCF50633_MBC_H
+
+#include <linux/platform_device.h>
+
+#define PCF50633_REG_MBCC1 0x43
+#define PCF50633_REG_MBCC2 0x44
+#define PCF50633_REG_MBCC3 0x45
+#define PCF50633_REG_MBCC4 0x46
+#define PCF50633_REG_MBCC5 0x47
+#define PCF50633_REG_MBCC6 0x48
+#define PCF50633_REG_MBCC7 0x49
+#define PCF50633_REG_MBCC8 0x4a
+#define PCF50633_REG_MBCS1 0x4b
+#define PCF50633_REG_MBCS2 0x4c
+#define PCF50633_REG_MBCS3 0x4d
+
+enum pcf50633_reg_mbcc1 {
+ PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
+ PCF50633_MBCC1_AUTOSTOP = 0x02,
+ PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
+ PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
+ PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
+ PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
+ PCF50633_MBCC1_WDTIME_1H = 0x00,
+ PCF50633_MBCC1_WDTIME_2H = 0x40,
+ PCF50633_MBCC1_WDTIME_4H = 0x80,
+ PCF50633_MBCC1_WDTIME_6H = 0xc0,
+};
+#define PCF50633_MBCC1_WDTIME_MASK 0xc0
+
+enum pcf50633_reg_mbcc2 {
+ PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
+ PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
+ PCF50633_MBCC2_VBATCOND_3V0 = 0x02,
+ PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
+ PCF50633_MBCC2_VMAX_4V = 0x00,
+ PCF50633_MBCC2_VMAX_4V20 = 0x28,
+ PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
+};
+
+enum pcf50633_reg_mbcc7 {
+ PCF50633_MBCC7_USB_100mA = 0x00,
+ PCF50633_MBCC7_USB_500mA = 0x01,
+ PCF50633_MBCC7_USB_1000mA = 0x02,
+ PCF50633_MBCC7_USB_SUSPEND = 0x03,
+ PCF50633_MBCC7_BATTEMP_EN = 0x04,
+ PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00,
+ PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40,
+ PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80,
+ PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0,
+};
+#define PCF50633_MBCC7_USB_MASK 0x03
+
+enum pcf50633_reg_mbcc8 {
+ PCF50633_MBCC8_USBENASUS = 0x10,
+};
+
+enum pcf50633_reg_mbcs1 {
+ PCF50633_MBCS1_USBPRES = 0x01,
+ PCF50633_MBCS1_USBOK = 0x02,
+ PCF50633_MBCS1_ADAPTPRES = 0x04,
+ PCF50633_MBCS1_ADAPTOK = 0x08,
+ PCF50633_MBCS1_TBAT_OK = 0x00,
+ PCF50633_MBCS1_TBAT_ABOVE = 0x10,
+ PCF50633_MBCS1_TBAT_BELOW = 0x20,
+ PCF50633_MBCS1_TBAT_UNDEF = 0x30,
+ PCF50633_MBCS1_PREWDTEXP = 0x40,
+ PCF50633_MBCS1_WDTEXP = 0x80,
+};
+
+enum pcf50633_reg_mbcs2_mbcmod {
+ PCF50633_MBCS2_MBC_PLAY = 0x00,
+ PCF50633_MBCS2_MBC_USB_PRE = 0x01,
+ PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
+ PCF50633_MBCS2_MBC_USB_FAST = 0x03,
+ PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04,
+ PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05,
+ PCF50633_MBCS2_MBC_ADP_PRE = 0x06,
+ PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
+ PCF50633_MBCS2_MBC_ADP_FAST = 0x08,
+ PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09,
+ PCF50633_MBCS2_MBC_BAT_FULL = 0x0a,
+ PCF50633_MBCS2_MBC_HALT = 0x0b,
+};
+#define PCF50633_MBCS2_MBC_MASK 0x0f
+enum pcf50633_reg_mbcs2_chgstat {
+ PCF50633_MBCS2_CHGS_NONE = 0x00,
+ PCF50633_MBCS2_CHGS_ADAPTER = 0x10,
+ PCF50633_MBCS2_CHGS_USB = 0x20,
+ PCF50633_MBCS2_CHGS_BOTH = 0x30,
+};
+#define PCF50633_MBCS2_RESSTAT_AUTO 0x40
+
+enum pcf50633_reg_mbcs3 {
+ PCF50633_MBCS3_USBLIM_PLAY = 0x01,
+ PCF50633_MBCS3_USBLIM_CGH = 0x02,
+ PCF50633_MBCS3_TLIM_PLAY = 0x04,
+ PCF50633_MBCS3_TLIM_CHG = 0x08,
+ PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */
+ PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */
+ PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */
+ PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */
+};
+
+#define PCF50633_MBCC2_VBATCOND_MASK 0x03
+#define PCF50633_MBCC2_VMAX_MASK 0x3c
+
+struct pcf50633;
+
+void pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma);
+
+struct pcf50633_mbc {
+ int adapter_active;
+ int adapter_online;
+ int usb_active;
+ int usb_online;
+
+ struct power_supply ac;
+ struct power_supply usb;
+ struct power_supply adapter;
+
+ struct delayed_work charging_restart_work;
+
+ struct platform_device *pdev;
+};
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/pmic.h
@@ -0,0 +1,73 @@
+#ifndef __LINUX_MFD_PCF50633_PMIC_H
+#define __LINUX_MFD_PCF50633_PMIC_H
+
+#include <linux/platform_device.h>
+
+#define PCF50633_REG_AUTOOUT 0x1a
+#define PCF50633_REG_AUTOENA 0x1b
+#define PCF50633_REG_AUTOCTL 0x1c
+#define PCF50633_REG_AUTOMXC 0x1d
+#define PCF50633_REG_DOWN1OUT 0x1e
+#define PCF50633_REG_DOWN1ENA 0x1f
+#define PCF50633_REG_DOWN1CTL 0x20
+#define PCF50633_REG_DOWN1MXC 0x21
+#define PCF50633_REG_DOWN2OUT 0x22
+#define PCF50633_REG_DOWN2ENA 0x23
+#define PCF50633_REG_DOWN2CTL 0x24
+#define PCF50633_REG_DOWN2MXC 0x25
+#define PCF50633_REG_MEMLDOOUT 0x26
+#define PCF50633_REG_MEMLDOENA 0x27
+#define PCF50633_REG_LDO1OUT 0x2d
+#define PCF50633_REG_LDO1ENA 0x2e
+#define PCF50633_REG_LDO2OUT 0x2f
+#define PCF50633_REG_LDO2ENA 0x30
+#define PCF50633_REG_LDO3OUT 0x31
+#define PCF50633_REG_LDO3ENA 0x32
+#define PCF50633_REG_LDO4OUT 0x33
+#define PCF50633_REG_LDO4ENA 0x34
+#define PCF50633_REG_LDO5OUT 0x35
+#define PCF50633_REG_LDO5ENA 0x36
+#define PCF50633_REG_LDO6OUT 0x37
+#define PCF50633_REG_LDO6ENA 0x38
+#define PCF50633_REG_HCLDOOUT 0x39
+#define PCF50633_REG_HCLDOENA 0x3a
+#define PCF50633_REG_HCLDOOVL 0x40
+
+enum pcf50633_regulator_enable {
+ PCF50633_REGULATOR_ON = 0x01,
+ PCF50633_REGULATOR_ON_GPIO1 = 0x02,
+ PCF50633_REGULATOR_ON_GPIO2 = 0x04,
+ PCF50633_REGULATOR_ON_GPIO3 = 0x08,
+};
+#define PCF50633_REGULATOR_ON_MASK 0x0f
+
+enum pcf50633_regulator_phase {
+ PCF50633_REGULATOR_ACTPH1 = 0x00,
+ PCF50633_REGULATOR_ACTPH2 = 0x10,
+ PCF50633_REGULATOR_ACTPH3 = 0x20,
+ PCF50633_REGULATOR_ACTPH4 = 0x30,
+};
+#define PCF50633_REGULATOR_ACTPH_MASK 0x30
+
+
+enum pcf50633_regulator_id {
+ PCF50633_REGULATOR_AUTO,
+ PCF50633_REGULATOR_DOWN1,
+ PCF50633_REGULATOR_DOWN2,
+ PCF50633_REGULATOR_LDO1,
+ PCF50633_REGULATOR_LDO2,
+ PCF50633_REGULATOR_LDO3,
+ PCF50633_REGULATOR_LDO4,
+ PCF50633_REGULATOR_LDO5,
+ PCF50633_REGULATOR_LDO6,
+ PCF50633_REGULATOR_HCLDO,
+ PCF50633_REGULATOR_MEMLDO,
+
+ PCF50633_NUM_REGULATORS
+};
+
+struct pcf50633_pmic {
+ struct platform_device *pdev[PCF50633_NUM_REGULATORS];
+};
+#endif
+
--- /dev/null
+++ b/include/linux/mfd/pcf50633/rtc.h
@@ -0,0 +1,43 @@
+/*
+ * rtc.h -- RTC driver for NXP PCF50633
+ *
+ * (C) 2006-2008 by Openmoko, Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __LINUX_MFD_PCF50633_RTC_H
+#define __LINUX_MFD_PCF50633_RTC_H
+
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+
+#define PCF50633_REG_RTCSC 0x59 /* Second */
+#define PCF50633_REG_RTCMN 0x5a /* Minute */
+#define PCF50633_REG_RTCHR 0x5b /* Hour */
+#define PCF50633_REG_RTCWD 0x5c /* Weekday */
+#define PCF50633_REG_RTCDT 0x5d /* Day */
+#define PCF50633_REG_RTCMT 0x5e /* Month */
+#define PCF50633_REG_RTCYR 0x5f /* Year */
+#define PCF50633_REG_RTCSCA 0x60 /* Alarm Second */
+#define PCF50633_REG_RTCMNA 0x61 /* Alarm Minute */
+#define PCF50633_REG_RTCHRA 0x62 /* Alarm Hour */
+#define PCF50633_REG_RTCWDA 0x63 /* Alarm Weekday */
+#define PCF50633_REG_RTCDTA 0x64 /* Alarm Day */
+#define PCF50633_REG_RTCMTA 0x65 /* Alarm Month */
+#define PCF50633_REG_RTCYRA 0x66 /* Alarm Year */
+
+struct pcf50633_rtc {
+ int alarm_enabled;
+ int second_enabled;
+
+ struct rtc_device *rtc_dev;
+ struct platform_device *pdev;
+};
+
+#endif
+
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -129,6 +129,8 @@
struct mmc_host;
struct mmc_card;
+extern void mmc_flush_scheduled_work(void);
+
extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
--- a/include/linux/mmc/sdio_ids.h
+++ b/include/linux/mmc/sdio_ids.h
@@ -25,5 +25,8 @@
#define SDIO_VENDOR_ID_MARVELL 0x02df
#define SDIO_DEVICE_ID_MARVELL_LIBERTAS 0x9103
+#define SDIO_DEVICE_ID_MARVELL_88W8688 0x9104
+#define SDIO_VENDOR_ID_ATHEROS 0x0271
+#define SDIO_DEVICE_ID_ATHEROS_AR6000 0x0100
#endif
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -713,7 +713,7 @@
}
#endif
struct file *shmem_file_setup(char *name, loff_t size, unsigned long flags);
-
+void shmem_set_file(struct vm_area_struct *, struct file *);
int shmem_zero_setup(struct vm_area_struct *);
#ifndef CONFIG_MMU
--- /dev/null
+++ b/include/linux/pcf50606.h
@@ -0,0 +1,91 @@
+#ifndef _LINUX_PCF50606_H
+#define _LINUX_PCF50606_H
+
+#include <linux/pcf506xx.h>
+
+
+/* public in-kernel pcf50606 api */
+enum pcf50606_regulator_id {
+ PCF50606_REGULATOR_DCD,
+ PCF50606_REGULATOR_DCDE,
+ PCF50606_REGULATOR_DCUD,
+ PCF50606_REGULATOR_D1REG,
+ PCF50606_REGULATOR_D2REG,
+ PCF50606_REGULATOR_D3REG,
+ PCF50606_REGULATOR_LPREG,
+ PCF50606_REGULATOR_IOREG,
+ __NUM_PCF50606_REGULATORS
+};
+
+struct pcf50606_data;
+
+/* This is an ugly construct on how to access the (currently single/global)
+ * pcf50606 handle from other code in the kernel. I didn't really come up with
+ * a more decent method of dynamically resolving this */
+extern struct pcf50606_data *pcf50606_global;
+
+extern void
+pcf50606_go_standby(void);
+
+extern void
+pcf50606_gpo0_set(struct pcf50606_data *pcf, int on);
+
+extern int
+pcf50606_gpo0_get(struct pcf50606_data *pcf);
+
+extern int
+pcf50606_voltage_set(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg,
+ unsigned int millivolts);
+extern unsigned int
+pcf50606_voltage_get(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg);
+extern int
+pcf50606_onoff_get(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg);
+
+extern int
+pcf50606_onoff_set(struct pcf50606_data *pcf,
+ enum pcf50606_regulator_id reg, int on);
+
+extern void
+pcf50606_charge_fast(struct pcf50606_data *pcf, int on);
+
+
+#define PCF50606_FEAT_EXTON 0x00000001 /* not yet supported */
+#define PCF50606_FEAT_MBC 0x00000002
+#define PCF50606_FEAT_BBC 0x00000004 /* not yet supported */
+#define PCF50606_FEAT_TSC 0x00000008 /* not yet supported */
+#define PCF50606_FEAT_WDT 0x00000010
+#define PCF50606_FEAT_ACD 0x00000020
+#define PCF50606_FEAT_RTC 0x00000040
+#define PCF50606_FEAT_PWM 0x00000080
+#define PCF50606_FEAT_CHGCUR 0x00000100
+#define PCF50606_FEAT_BATVOLT 0x00000200
+#define PCF50606_FEAT_BATTEMP 0x00000400
+#define PCF50606_FEAT_PWM_BL 0x00000800
+
+struct pcf50606_platform_data {
+ /* general */
+ unsigned int used_features;
+ unsigned int onkey_seconds_required;
+
+ /* voltage regulator related */
+ struct pmu_voltage_rail rails[__NUM_PCF50606_REGULATORS];
+ unsigned int used_regulators;
+
+ /* charger related */
+ unsigned int r_fix_batt;
+ unsigned int r_fix_batt_par;
+ unsigned int r_sense_milli;
+
+ /* backlight related */
+ unsigned int init_brightness;
+
+ struct {
+ u_int8_t mbcc3; /* charger voltage / current */
+ } charger;
+ pmu_cb cb;
+};
+
+#endif
--- /dev/null
+++ b/include/linux/pcf50633.h
@@ -0,0 +1,618 @@
+#ifndef _LINUX_PCF50633_H
+#define _LINUX_PCF50633_H
+
+#include <linux/pcf506xx.h>
+#include <linux/regulator/machine.h>
+
+#define PCF50633_FIDX_CHG_ENABLED 0 /* Charger enabled */
+#define PCF50633_FIDX_CHG_PRESENT 1 /* Charger present */
+#define PCF50633_FIDX_CHG_ERR 3 /* Charger Error */
+#define PCF50633_FIDX_CHG_PROT 4 /* Charger Protection */
+#define PCF50633_FIDX_CHG_READY 5 /* Charging completed */
+#define PCF50633_FIDX_PWR_PRESSED 8
+#define PCF50633_FIDX_RTC_SECOND 9
+#define PCF50633_FIDX_USB_PRESENT 10
+
+#define PCF50633_F_CHG_ENABLED (1 << PCF50633_FIDX_CHG_ENABLED)
+#define PCF50633_F_CHG_PRESENT (1 << PCF50633_FIDX_CHG_PRESENT)
+#define PCF50633_F_CHG_ERR (1 << PCF50633_FIDX_CHG_ERR)
+#define PCF50633_F_CHG_PROT (1 << PCF50633_FIDX_CHG_PROT)
+#define PCF50633_F_CHG_READY (1 << PCF50633_FIDX_CHG_READY)
+
+#define PCF50633_F_CHG_MASK 0x000000fc
+
+#define PCF50633_F_PWR_PRESSED (1 << PCF50633_FIDX_PWR_PRESSED)
+
+#define PCF50633_F_RTC_SECOND (1 << PCF50633_FIDX_RTC_SECOND)
+#define PCF50633_F_USB_PRESENT (1 << PCF50633_FIDX_USB_PRESENT)
+
+/* public in-kernel pcf50633 api */
+enum pcf50633_regulator_id {
+ PCF50633_REGULATOR_AUTO,
+ PCF50633_REGULATOR_DOWN1,
+ PCF50633_REGULATOR_DOWN2,
+ PCF50633_REGULATOR_LDO1,
+ PCF50633_REGULATOR_LDO2,
+ PCF50633_REGULATOR_LDO3,
+ PCF50633_REGULATOR_LDO4,
+ PCF50633_REGULATOR_LDO5,
+ PCF50633_REGULATOR_LDO6,
+ PCF50633_REGULATOR_HCLDO,
+ PCF50633_REGULATOR_MEMLDO,
+ __NUM_PCF50633_REGULATORS
+};
+
+enum pcf50633_reg_int1 {
+ PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
+ PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
+ PCF50633_INT1_USBINS = 0x04, /* USB inserted */
+ PCF50633_INT1_USBREM = 0x08, /* USB removed */
+ /* reserved */
+ PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
+ PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
+};
+
+enum pcf50633_reg_int2 {
+ PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
+ PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
+ PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
+ PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
+ PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
+ PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
+ PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
+ PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
+};
+
+enum pcf50633_reg_int3 {
+ PCF50633_INT3_BATFULL = 0x01, /* Battery full */
+ PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
+ PCF50633_INT3_THLIMON = 0x04,
+ PCF50633_INT3_THLIMOFF = 0x08,
+ PCF50633_INT3_USBLIMON = 0x10,
+ PCF50633_INT3_USBLIMOFF = 0x20,
+ PCF50633_INT3_ADCRDY = 0x40, /* ADC conversion finished */
+ PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
+};
+
+enum pcf50633_reg_int4 {
+ PCF50633_INT4_LOWSYS = 0x01,
+ PCF50633_INT4_LOWBAT = 0x02,
+ PCF50633_INT4_HIGHTMP = 0x04,
+ PCF50633_INT4_AUTOPWRFAIL = 0x08,
+ PCF50633_INT4_DWN1PWRFAIL = 0x10,
+ PCF50633_INT4_DWN2PWRFAIL = 0x20,
+ PCF50633_INT4_LEDPWRFAIL = 0x40,
+ PCF50633_INT4_LEDOVP = 0x80,
+};
+
+enum pcf50633_reg_int5 {
+ PCF50633_INT5_LDO1PWRFAIL = 0x01,
+ PCF50633_INT5_LDO2PWRFAIL = 0x02,
+ PCF50633_INT5_LDO3PWRFAIL = 0x04,
+ PCF50633_INT5_LDO4PWRFAIL = 0x08,
+ PCF50633_INT5_LDO5PWRFAIL = 0x10,
+ PCF50633_INT5_LDO6PWRFAIL = 0x20,
+ PCF50633_INT5_HCLDOPWRFAIL = 0x40,
+ PCF50633_INT5_HCLDOOVL = 0x80,
+};
+
+struct pcf50633_data;
+
+extern void
+pcf50633_go_standby(struct pcf50633_data *pcf);
+
+enum pcf50633_gpio {
+ PCF50633_GPIO1 = 1,
+ PCF50633_GPIO2 = 2,
+ PCF50633_GPIO3 = 3,
+ PCF50633_GPO = 4,
+};
+
+extern void
+pcf50633_gpio_set(struct pcf50633_data *pcf, enum pcf50633_gpio gpio, int on);
+
+extern int
+pcf50633_gpio_get(struct pcf50633_data *pcf, enum pcf50633_gpio gpio);
+
+extern int
+pcf50633_adc_async_read(struct pcf50633_data *pcf, int mux, int avg,
+ void (*callback)(struct pcf50633_data *, void *, int),
+ void *callback_param);
+
+extern int
+pcf50633_adc_sync_read(struct pcf50633_data *pcf, int mux, int avg);
+
+extern void
+pcf50633_backlight_resume(struct pcf50633_data *pcf);
+
+extern u_int16_t
+pcf50633_battvolt(struct pcf50633_data *pcf);
+
+extern int
+pcf50633_report_resumers(struct pcf50633_data *pcf, char *buf);
+
+extern int
+pcf50633_notify_usb_current_limit_change(struct pcf50633_data *pcf,
+ unsigned int ma);
+extern int
+pcf50633_wait_for_ready(struct pcf50633_data *pcf, int timeout_ms,
+ char *name);
+
+/* 0 = initialized and resumed and ready to roll, !=0 = either not
+ * initialized or not resumed yet
+ */
+extern int
+pcf50633_ready(struct pcf50633_data *pcf);
+
+#define PCF50633_FEAT_EXTON 0x00000001 /* not yet supported */
+#define PCF50633_FEAT_MBC 0x00000002
+#define PCF50633_FEAT_BBC 0x00000004 /* not yet supported */
+#define PCF50633_FEAT_RTC 0x00000040
+#define PCF50633_FEAT_CHGCUR 0x00000100
+#define PCF50633_FEAT_BATVOLT 0x00000200
+#define PCF50633_FEAT_BATTEMP 0x00000400
+#define PCF50633_FEAT_PWM_BL 0x00000800
+
+enum charger_type {
+ CHARGER_TYPE_NONE = 0,
+ CHARGER_TYPE_HOSTUSB,
+ CHARGER_TYPE_1A
+};
+
+#define ADC_NOM_CHG_DETECT_1A 6
+#define ADC_NOM_CHG_DETECT_NONE 43
+
+#define MAX_ADC_FIFO_DEPTH 8
+
+enum pcf50633_suspend_states {
+ PCF50633_SS_RUNNING,
+ PCF50633_SS_STARTING_SUSPEND,
+ PCF50633_SS_COMPLETED_SUSPEND,
+ PCF50633_SS_RESUMING_BUT_NOT_US_YET,
+ PCF50633_SS_STARTING_RESUME,
+ PCF50633_SS_COMPLETED_RESUME,
+};
+
+struct pcf50633_data;
+
+struct pcf50633_platform_data {
+ /* general */
+ unsigned int used_features;
+ unsigned int onkey_seconds_sig_init;
+ unsigned int onkey_seconds_shutdown;
+
+ /* callback to attach platform children (to enforce suspend / resume
+ * ordering */
+ void (*attach_child_devices)(struct device *parent_device);
+
+ /* charger related */
+ unsigned int r_fix_batt;
+ unsigned int r_fix_batt_par;
+ unsigned int r_sense_milli;
+ int flag_use_apm_emulation;
+
+ unsigned char resumers[5];
+
+ struct {
+ u_int8_t mbcc3; /* charger voltage / current */
+ } charger;
+ pmu_cb cb;
+
+ struct regulator_init_data reg_init_data[__NUM_PCF50633_REGULATORS];
+
+ /* Called when a regulator has been registered */
+ void (*regulator_registered)(struct pcf50633_data *pcf, int id);
+
+ /* Runtime data */
+ struct pcf50633_data *pcf;
+};
+
+enum pfc50633_regs {
+ PCF50633_REG_VERSION = 0x00,
+ PCF50633_REG_VARIANT = 0x01,
+ PCF50633_REG_INT1 = 0x02, /* Interrupt Status */
+ PCF50633_REG_INT2 = 0x03, /* Interrupt Status */
+ PCF50633_REG_INT3 = 0x04, /* Interrupt Status */
+ PCF50633_REG_INT4 = 0x05, /* Interrupt Status */
+ PCF50633_REG_INT5 = 0x06, /* Interrupt Status */
+ PCF50633_REG_INT1M = 0x07, /* Interrupt Mask */
+ PCF50633_REG_INT2M = 0x08, /* Interrupt Mask */
+ PCF50633_REG_INT3M = 0x09, /* Interrupt Mask */
+ PCF50633_REG_INT4M = 0x0a, /* Interrupt Mask */
+ PCF50633_REG_INT5M = 0x0b, /* Interrupt Mask */
+ PCF50633_REG_OOCSHDWN = 0x0c,
+ PCF50633_REG_OOCWAKE = 0x0d,
+ PCF50633_REG_OOCTIM1 = 0x0e,
+ PCF50633_REG_OOCTIM2 = 0x0f,
+ PCF50633_REG_OOCMODE = 0x10,
+ PCF50633_REG_OOCCTL = 0x11,
+ PCF50633_REG_OOCSTAT = 0x12,
+ PCF50633_REG_GPIOCTL = 0x13,
+ PCF50633_REG_GPIO1CFG = 0x14,
+ PCF50633_REG_GPIO2CFG = 0x15,
+ PCF50633_REG_GPIO3CFG = 0x16,
+ PCF50633_REG_GPOCFG = 0x17,
+ PCF50633_REG_BVMCTL = 0x18,
+ PCF50633_REG_SVMCTL = 0x19,
+ PCF50633_REG_AUTOOUT = 0x1a,
+ PCF50633_REG_AUTOENA = 0x1b,
+ PCF50633_REG_AUTOCTL = 0x1c,
+ PCF50633_REG_AUTOMXC = 0x1d,
+ PCF50633_REG_DOWN1OUT = 0x1e,
+ PCF50633_REG_DOWN1ENA = 0x1f,
+ PCF50633_REG_DOWN1CTL = 0x20,
+ PCF50633_REG_DOWN1MXC = 0x21,
+ PCF50633_REG_DOWN2OUT = 0x22,
+ PCF50633_REG_DOWN2ENA = 0x23,
+ PCF50633_REG_DOWN2CTL = 0x24,
+ PCF50633_REG_DOWN2MXC = 0x25,
+ PCF50633_REG_MEMLDOOUT = 0x26,
+ PCF50633_REG_MEMLDOENA = 0x27,
+ PCF50633_REG_LEDOUT = 0x28,
+ PCF50633_REG_LEDENA = 0x29,
+ PCF50633_REG_LEDCTL = 0x2a,
+ PCF50633_REG_LEDDIM = 0x2b,
+ /* reserved */
+ PCF50633_REG_LDO1OUT = 0x2d,
+ PCF50633_REG_LDO1ENA = 0x2e,
+ PCF50633_REG_LDO2OUT = 0x2f,
+ PCF50633_REG_LDO2ENA = 0x30,
+ PCF50633_REG_LDO3OUT = 0x31,
+ PCF50633_REG_LDO3ENA = 0x32,
+ PCF50633_REG_LDO4OUT = 0x33,
+ PCF50633_REG_LDO4ENA = 0x34,
+ PCF50633_REG_LDO5OUT = 0x35,
+ PCF50633_REG_LDO5ENA = 0x36,
+ PCF50633_REG_LDO6OUT = 0x37,
+ PCF50633_REG_LDO6ENA = 0x38,
+ PCF50633_REG_HCLDOOUT = 0x39,
+ PCF50633_REG_HCLDOENA = 0x3a,
+ PCF50633_REG_STBYCTL1 = 0x3b,
+ PCF50633_REG_STBYCTL2 = 0x3c,
+ PCF50633_REG_DEBPF1 = 0x3d,
+ PCF50633_REG_DEBPF2 = 0x3e,
+ PCF50633_REG_DEBPF3 = 0x3f,
+ PCF50633_REG_HCLDOOVL = 0x40,
+ PCF50633_REG_DCDCSTAT = 0x41,
+ PCF50633_REG_LDOSTAT = 0x42,
+ PCF50633_REG_MBCC1 = 0x43,
+ PCF50633_REG_MBCC2 = 0x44,
+ PCF50633_REG_MBCC3 = 0x45,
+ PCF50633_REG_MBCC4 = 0x46,
+ PCF50633_REG_MBCC5 = 0x47,
+ PCF50633_REG_MBCC6 = 0x48,
+ PCF50633_REG_MBCC7 = 0x49,
+ PCF50633_REG_MBCC8 = 0x4a,
+ PCF50633_REG_MBCS1 = 0x4b,
+ PCF50633_REG_MBCS2 = 0x4c,
+ PCF50633_REG_MBCS3 = 0x4d,
+ PCF50633_REG_BBCCTL = 0x4e,
+ PCF50633_REG_ALMGAIN = 0x4f,
+ PCF50633_REG_ALMDATA = 0x50,
+ /* reserved */
+ PCF50633_REG_ADCC3 = 0x52,
+ PCF50633_REG_ADCC2 = 0x53,
+ PCF50633_REG_ADCC1 = 0x54,
+ PCF50633_REG_ADCS1 = 0x55,
+ PCF50633_REG_ADCS2 = 0x56,
+ PCF50633_REG_ADCS3 = 0x57,
+ /* reserved */
+ PCF50633_REG_RTCSC = 0x59, /* Second */
+ PCF50633_REG_RTCMN = 0x5a, /* Minute */
+ PCF50633_REG_RTCHR = 0x5b, /* Hour */
+ PCF50633_REG_RTCWD = 0x5c, /* Weekday */
+ PCF50633_REG_RTCDT = 0x5d, /* Day */
+ PCF50633_REG_RTCMT = 0x5e, /* Month */
+ PCF50633_REG_RTCYR = 0x5f, /* Year */
+ PCF50633_REG_RTCSCA = 0x60, /* Alarm Second */
+ PCF50633_REG_RTCMNA = 0x61, /* Alarm Minute */
+ PCF50633_REG_RTCHRA = 0x62, /* Alarm Hour */
+ PCF50633_REG_RTCWDA = 0x63, /* Alarm Weekday */
+ PCF50633_REG_RTCDTA = 0x64, /* Alarm Day */
+ PCF50633_REG_RTCMTA = 0x65, /* Alarm Month */
+ PCF50633_REG_RTCYRA = 0x66, /* Alarm Year */
+
+ PCF50633_REG_MEMBYTE0 = 0x67,
+ PCF50633_REG_MEMBYTE1 = 0x68,
+ PCF50633_REG_MEMBYTE2 = 0x69,
+ PCF50633_REG_MEMBYTE3 = 0x6a,
+ PCF50633_REG_MEMBYTE4 = 0x6b,
+ PCF50633_REG_MEMBYTE5 = 0x6c,
+ PCF50633_REG_MEMBYTE6 = 0x6d,
+ PCF50633_REG_MEMBYTE7 = 0x6e,
+ /* reserved */
+ PCF50633_REG_DCDCPFM = 0x84,
+ __NUM_PCF50633_REGS
+};
+
+
+enum pcf50633_reg_oocshdwn {
+ PCF50633_OOCSHDWN_GOSTDBY = 0x01,
+ PCF50633_OOCSHDWN_TOTRST = 0x04,
+ PCF50633_OOCSHDWN_COLDBOOT = 0x08,
+};
+
+enum pcf50633_reg_oocwake {
+ PCF50633_OOCWAKE_ONKEY = 0x01,
+ PCF50633_OOCWAKE_EXTON1 = 0x02,
+ PCF50633_OOCWAKE_EXTON2 = 0x04,
+ PCF50633_OOCWAKE_EXTON3 = 0x08,
+ PCF50633_OOCWAKE_RTC = 0x10,
+ /* reserved */
+ PCF50633_OOCWAKE_USB = 0x40,
+ PCF50633_OOCWAKE_ADP = 0x80,
+};
+
+enum pcf50633_reg_mbcc1 {
+ PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
+ PCF50633_MBCC1_AUTOSTOP = 0x02,
+ PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
+ PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
+ PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
+ PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
+ PCF50633_MBCC1_WDTIME_1H = 0x00,
+ PCF50633_MBCC1_WDTIME_2H = 0x40,
+ PCF50633_MBCC1_WDTIME_4H = 0x80,
+ PCF50633_MBCC1_WDTIME_6H = 0xc0,
+};
+#define PCF50633_MBCC1_WDTIME_MASK 0xc0
+
+enum pcf50633_reg_mbcc2 {
+ PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
+ PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
+ PCF50633_MBCC2_VBATCOND_3V0 = 0x02,
+ PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
+ PCF50633_MBCC2_VMAX_4V = 0x00,
+ PCF50633_MBCC2_VMAX_4V20 = 0x28,
+ PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
+};
+#define PCF50633_MBCC2_VBATCOND_MASK 0x03
+#define PCF50633_MBCC2_VMAX_MASK 0x3c
+
+enum pcf50633_reg_adcc1 {
+ PCF50633_ADCC1_ADCSTART = 0x01,
+ PCF50633_ADCC1_RES_10BIT = 0x02,
+ PCF50633_ADCC1_AVERAGE_NO = 0x00,
+ PCF50633_ADCC1_AVERAGE_4 = 0x04,
+ PCF50633_ADCC1_AVERAGE_8 = 0x08,
+ PCF50633_ADCC1_AVERAGE_16 = 0x0c,
+
+ PCF50633_ADCC1_MUX_BATSNS_RES = 0x00,
+ PCF50633_ADCC1_MUX_BATSNS_SUBTR = 0x10,
+ PCF50633_ADCC1_MUX_ADCIN2_RES = 0x20,
+ PCF50633_ADCC1_MUX_ADCIN2_SUBTR = 0x30,
+ PCF50633_ADCC1_MUX_BATTEMP = 0x60,
+ PCF50633_ADCC1_MUX_ADCIN1 = 0x70,
+};
+#define PCF50633_ADCC1_AVERAGE_MASK 0x0c
+#define PCF50633_ADCC1_ADCMUX_MASK 0xf0
+
+enum pcf50633_reg_adcc2 {
+ PCF50633_ADCC2_RATIO_NONE = 0x00,
+ PCF50633_ADCC2_RATIO_BATTEMP = 0x01,
+ PCF50633_ADCC2_RATIO_ADCIN1 = 0x02,
+ PCF50633_ADCC2_RATIO_BOTH = 0x03,
+ PCF50633_ADCC2_RATIOSETTL_100US = 0x04,
+};
+#define PCF50633_ADCC2_RATIO_MASK 0x03
+
+enum pcf50633_reg_adcc3 {
+ PCF50633_ADCC3_ACCSW_EN = 0x01,
+ PCF50633_ADCC3_NTCSW_EN = 0x04,
+ PCF50633_ADCC3_RES_DIV_TWO = 0x10,
+ PCF50633_ADCC3_RES_DIV_THREE = 0x00,
+};
+
+enum pcf50633_reg_adcs3 {
+ PCF50633_ADCS3_REF_NTCSW = 0x00,
+ PCF50633_ADCS3_REF_ACCSW = 0x10,
+ PCF50633_ADCS3_REF_2V0 = 0x20,
+ PCF50633_ADCS3_REF_VISA = 0x30,
+ PCF50633_ADCS3_REF_2V0_2 = 0x70,
+ PCF50633_ADCS3_ADCRDY = 0x80,
+};
+#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03
+#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c
+#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2
+#define PCF50633_ASCS3_REF_MASK 0x70
+
+enum pcf50633_regulator_enable {
+ PCF50633_REGULATOR_ON = 0x01,
+ PCF50633_REGULATOR_ON_GPIO1 = 0x02,
+ PCF50633_REGULATOR_ON_GPIO2 = 0x04,
+ PCF50633_REGULATOR_ON_GPIO3 = 0x08,
+};
+#define PCF50633_REGULATOR_ON_MASK 0x0f
+
+enum pcf50633_regulator_phase {
+ PCF50633_REGULATOR_ACTPH1 = 0x00,
+ PCF50633_REGULATOR_ACTPH2 = 0x10,
+ PCF50633_REGULATOR_ACTPH3 = 0x20,
+ PCF50633_REGULATOR_ACTPH4 = 0x30,
+};
+#define PCF50633_REGULATOR_ACTPH_MASK 0x30
+
+enum pcf50633_reg_gpocfg {
+ PCF50633_GPOCFG_GPOSEL_0 = 0x00,
+ PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
+ PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02,
+ PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03,
+ PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04,
+ PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05,
+ PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06,
+ PCF50633_GPOCFG_GPOSEL_1 = 0x07,
+ PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08,
+};
+#define PCF50633_GPOCFG_GPOSEL_MASK 0x07
+
+#if 0
+enum pcf50633_reg_mbcc1 {
+ PCF50633_MBCC1_CHGENA = 0x01,
+ PCF50633_MBCC1_AUTOSTOP = 0x02,
+ PCF50633_MBCC1_AUTORES = 0x04,
+ PCF50633_MBCC1_RESUME = 0x08,
+ PCF50633_MBCC1_RESTART = 0x10,
+ PCF50633_MBCC1_PREWDTIME_30MIN = 0x00,
+ PCF50633_MBCC1_PREWDTIME_60MIN = 0x20,
+ PCF50633_MBCC1_WDTIME_2HRS = 0x40,
+ PCF50633_MBCC1_WDTIME_4HRS = 0x80,
+ PCF50633_MBCC1_WDTIME_6HRS = 0xc0,
+};
+
+enum pcf50633_reg_mbcc2 {
+ PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
+ PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
+ PCF50633_MBCC2_VBATCOND_3V0 = 0x02,
+ PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
+ PCF50633_MBCC2_VRESDEBTIME_64S = 0x80,
+};
+#define PCF50633_MBCC2_VMAX_MASK 0x3c
+#endif
+
+enum pcf50633_reg_mbcc7 {
+ PCF50633_MBCC7_USB_100mA = 0x00,
+ PCF50633_MBCC7_USB_500mA = 0x01,
+ PCF50633_MBCC7_USB_1000mA = 0x02,
+ PCF50633_MBCC7_USB_SUSPEND = 0x03,
+ PCF50633_MBCC7_BATTEMP_EN = 0x04,
+ PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00,
+ PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40,
+ PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80,
+ PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0,
+};
+#define PCF56033_MBCC7_USB_MASK 0x03
+
+enum pcf50633_reg_mbcc8 {
+ PCF50633_MBCC8_USBENASUS = 0x10,
+};
+
+enum pcf50633_reg_mbcs1 {
+ PCF50633_MBCS1_USBPRES = 0x01,
+ PCF50633_MBCS1_USBOK = 0x02,
+ PCF50633_MBCS1_ADAPTPRES = 0x04,
+ PCF50633_MBCS1_ADAPTOK = 0x08,
+ PCF50633_MBCS1_TBAT_OK = 0x00,
+ PCF50633_MBCS1_TBAT_ABOVE = 0x10,
+ PCF50633_MBCS1_TBAT_BELOW = 0x20,
+ PCF50633_MBCS1_TBAT_UNDEF = 0x30,
+ PCF50633_MBCS1_PREWDTEXP = 0x40,
+ PCF50633_MBCS1_WDTEXP = 0x80,
+};
+
+enum pcf50633_reg_mbcs2_mbcmod {
+ PCF50633_MBCS2_MBC_PLAY = 0x00,
+ PCF50633_MBCS2_MBC_USB_PRE = 0x01,
+ PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
+ PCF50633_MBCS2_MBC_USB_FAST = 0x03,
+ PCF50633_MBCS2_MBC_USB_FAST_WAIT= 0x04,
+ PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05,
+ PCF50633_MBCS2_MBC_ADP_PRE = 0x06,
+ PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
+ PCF50633_MBCS2_MBC_ADP_FAST = 0x08,
+ PCF50633_MBCS2_MBC_ADP_FAST_WAIT= 0x09,
+ PCF50633_MBCS2_MBC_BAT_FULL = 0x0a,
+ PCF50633_MBCS2_MBC_HALT = 0x0b,
+};
+#define PCF50633_MBCS2_MBC_MASK 0x0f
+enum pcf50633_reg_mbcs2_chgstat {
+ PCF50633_MBCS2_CHGS_NONE = 0x00,
+ PCF50633_MBCS2_CHGS_ADAPTER = 0x10,
+ PCF50633_MBCS2_CHGS_USB = 0x20,
+ PCF50633_MBCS2_CHGS_BOTH = 0x30,
+};
+#define PCF50633_MBCS2_RESSTAT_AUTO 0x40
+
+enum pcf50633_reg_mbcs3 {
+ PCF50633_MBCS3_USBLIM_PLAY = 0x01,
+ PCF50633_MBCS3_USBLIM_CGH = 0x02,
+ PCF50633_MBCS3_TLIM_PLAY = 0x04,
+ PCF50633_MBCS3_TLIM_CHG = 0x08,
+ PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */
+ PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */
+ PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */
+ PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */
+};
+
+struct adc_request {
+ int mux;
+ int avg;
+ int result;
+ void (*callback)(struct pcf50633_data *, void *, int);
+ void *callback_param;
+
+ /* Used in case of sync requests */
+ struct completion completion;
+};
+
+struct pcf50633_data {
+ struct i2c_client *client;
+ struct pcf50633_platform_data *pdata;
+ struct backlight_device *backlight;
+ struct mutex lock;
+ unsigned int flags;
+ unsigned int working;
+ struct mutex working_lock;
+ struct work_struct work;
+ struct rtc_device *rtc;
+ struct input_dev *input_dev;
+ int allow_close;
+ int onkey_seconds;
+ int irq;
+ enum pcf50633_suspend_states suspend_state;
+ int usb_removal_count;
+ u8 pcfirq_resume[5];
+ int probe_completed;
+ int suppress_onkey_events;
+
+ /* if he pulls battery while charging, we notice that and correctly
+ * report that the charger is idle. But there is no interrupt that
+ * fires if he puts a battery back in and charging resumes. So when
+ * the battery is pulled, we run this work function looking for
+ * either charger resumption or USB cable pull
+ */
+ struct mutex working_lock_nobat;
+ struct work_struct work_nobat;
+ int working_nobat;
+ int usb_removal_count_nobat;
+ int jiffies_last_bat_ins;
+
+ /* current limit notification handler stuff */
+ struct mutex working_lock_usb_curlimit;
+ struct work_struct work_usb_curlimit;
+ int pending_curlimit;
+ int usb_removal_count_usb_curlimit;
+
+ int last_curlim_set;
+
+ int coldplug_done; /* cleared by probe, set by first work service */
+ int flag_bat_voltage_read; /* ipc to /sys batt voltage read func */
+
+ /* we have a FIFO of ADC measurement requests that are used only by
+ * the workqueue service code after the ADC completion interrupt
+ */
+ struct adc_request *adc_queue[MAX_ADC_FIFO_DEPTH]; /* amount of averaging */
+ int adc_queue_head; /* head owned by foreground code */
+ int adc_queue_tail; /* tail owned by service code */
+
+ struct platform_device *regulator_pdev[__NUM_PCF50633_REGULATORS];
+};
+
+/* this is to be provided by the board implementation */
+extern const u_int8_t pcf50633_initial_regs[__NUM_PCF50633_REGS];
+
+int pcf50633_read(struct pcf50633_data *pcf, u_int8_t reg,
+ int nr_regs, u_int8_t *data);
+
+int pcf50633_write(struct pcf50633_data *pcf, u_int8_t reg,
+ int nr_regs, u_int8_t *data);
+
+int pcf50633_reg_write(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t val);
+
+u_int8_t pcf50633_reg_read(struct pcf50633_data *pcf, u_int8_t reg);
+
+int pcf50633_reg_set_bit_mask(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t mask, u_int8_t val);
+int pcf50633_reg_clear_bits(struct pcf50633_data *pcf, u_int8_t reg, u_int8_t bits);
+
+void pcf50633_charge_autofast(int on);
+#endif /* _PCF50633_H */
+
--- /dev/null
+++ b/include/linux/pcf506xx.h
@@ -0,0 +1,34 @@
+#ifndef _LINUX_PCF506XX_H
+#define _LINUX_PCF506XX_H
+
+
+#define PMU_VRAIL_F_SUSPEND_ON 0x00000001 /* Remains on during suspend */
+#define PMU_VRAIL_F_UNUSED 0x00000002 /* This rail is not used */
+struct pmu_voltage_rail {
+ char *name;
+ unsigned int flags;
+ struct {
+ unsigned int init;
+ unsigned int max;
+ } voltage;
+};
+
+enum pmu_event {
+ PMU_EVT_NONE,
+ PMU_EVT_INSERT,
+ PMU_EVT_REMOVE,
+#ifdef CONFIG_SENSORS_PCF50633
+ PMU_EVT_USB_INSERT,
+ PMU_EVT_USB_REMOVE,
+#endif
+ PMU_EVT_CHARGER_ACTIVE,
+ PMU_EVT_CHARGER_IDLE,
+ PMU_EVT_CHARGER_CHANGE,
+ __NUM_PMU_EVTS
+};
+
+typedef int (*pmu_cb)(struct device *dev, unsigned int feature,
+ enum pmu_event event);
+
+
+#endif /* !_LINUX_PCF506XX_H */
--- /dev/null
+++ b/include/linux/regulator/pcf50633.h
@@ -0,0 +1,3 @@
+#include <linux/pcf50633.h>
+
+int pcf50633_regulator_init(struct pcf50633_data *, int);
--- /dev/null
+++ b/include/linux/resume-dependency.h
@@ -0,0 +1,114 @@
+#ifndef __RESUME_DEPENDENCY_H__
+#define __RESUME_DEPENDENCY_H__
+
+/* Resume dependency framework
+ *
+ * (C) 2008 Openmoko, Inc.
+ * Author: Andy Green <andy@openmoko.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2.1.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <linux/list.h>
+
+struct resume_dependency {
+ struct list_head list;
+
+ void (*callback)(void *); /* called with context as arg */
+ void * context;
+ int called_flag; /* set to 1 after called, use for multi dep */
+};
+
+/* if you are a driver accept to have other drivers as dependencies, you need to
+ * instantiate a struct resume_dependency above, then initialize it by invoking
+ * init_resume_dependency_list() on it
+ */
+
+#define init_resume_dependency_list(_head) \
+ printk(KERN_INFO "##### init_resume_dependency_list(head=%p)\n", (_head)); \
+ INIT_LIST_HEAD(&(_head)->list);
+
+
+/* if your resume function depends on something else being resumed first, you
+ * can register the dependency by calling this in your suspend function with
+ * head being the list held by the thing you are dependent on, and dep being
+ * your struct resume_dependency
+ */
+
+#define register_resume_dependency(_head, _dep) { \
+ struct list_head *_pos, *_q; \
+ struct resume_dependency *_d; \
+\
+ printk(KERN_ERR "##### register_resume_dependency(head=%p, dep=%p)\n", (_head), (_dep)); \
+ (_dep)->called_flag = 1; \
+ list_for_each_safe(_pos, _q, &((_head)->list)) { \
+ _d = list_entry(_pos, struct resume_dependency, list); \
+ if (_d == (_dep)) { \
+ list_del(_pos); \
+ printk(KERN_ERR "##### duplicate dependency removed first\n"); \
+ } \
+ } \
+ list_add(&(_dep)->list, &(_head)->list); \
+}
+
+/* In the resume function that things can be dependent on, at the end you
+ * invoke this macro. This calls back the dependent resumes now it is safe to
+ * use the resumed thing they were dependent on.
+ */
+
+#define callback_all_resume_dependencies(_head) { \
+ struct list_head *_pos, *_q; \
+ struct resume_dependency *_dep; \
+\
+ printk(KERN_ERR "##### callback_all_resume_dependencies(head=%p)\n", (_head)); \
+ list_for_each_safe(_pos, _q, &((_head)->list)) { \
+ _dep = list_entry(_pos, struct resume_dependency, list); \
+ printk(KERN_ERR "##### callback list entry (head=%p, dep=%p)\n", (_head), (_dep)); \
+ _dep->called_flag = 1; \
+ printk(KERN_ERR "##### callback=%p(context=%p))\n", (_dep->callback),(_dep->context)); \
+ (_dep->callback)(_dep->context); \
+ list_del(_pos); \
+ } \
+}
+
+/* When a dependency is added, it is not actually active; the dependent resume
+ * handler will function as normal. The dependency is activated by the suspend
+ * handler for the driver that will be doing the callbacks. This ensures that
+ * if the suspend is aborted for any reason (error, driver busy, etc), that all
+ * suspended drivers will resume, even if the driver upon which they are dependent
+ * did not suspend, and hence will not resume, and thus would be unable to perform
+ * the callbacks.
+ */
+
+#define activate_all_resume_dependencies(_head) { \
+ struct list_head *_pos, *_q; \
+ struct resume_dependency *_dep; \
+\
+ printk(KERN_ERR "##### activate_all_resume_dependencies(head=%p)\n", (_head)); \
+ list_for_each_safe(_pos, _q, &((_head)->list)) { \
+ _dep = list_entry(_pos, struct resume_dependency, list); \
+ printk(KERN_ERR "##### activating callback list entry (head=%p, dep=%p)\n", (_head), (_dep)); \
+ _dep->called_flag = 0; \
+ } \
+}
+
+/* if your resume action is dependent on multiple drivers being resumed already,
+ * register the same callback with each driver you are dependent on, and check
+ * .called_flag for all of the struct resume_dependency. When they are all 1
+ * you know it is the last callback and you can resume, otherwise just return
+ */
+
+#endif
--- /dev/null
+++ b/include/linux/rtc/pcf50633.h
@@ -0,0 +1,9 @@
+enum pcf50633_rtc_event {
+ PCF50633_RTC_EVENT_ALARM,
+ PCF50633_RTC_EVENT_SECOND,
+};
+
+extern void pcf50633_rtc_handle_event(struct pcf50633_data *pcf,
+ enum pcf50633_rtc_event evt);
+
+
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -158,6 +158,8 @@
/* SH-SCI */
#define PORT_SCIFA 83
+#define PORT_S3C6400 83
+
#ifdef __KERNEL__
#include <linux/compiler.h>
--- /dev/null
+++ b/include/linux/spi/glamo.h
@@ -0,0 +1,28 @@
+#ifndef __GLAMO_SPI_H
+#define __GLAMO_SPI_H
+
+#include <linux/glamo-gpio.h>
+
+struct spi_board_info;
+struct glamofb_handle;
+struct glamo_core;
+
+struct glamo_spi_info {
+ unsigned long board_size;
+ struct spi_board_info *board_info;
+ struct glamofb_handle *glamofb_handle;
+};
+
+struct glamo_spigpio_info {
+ unsigned int pin_clk;
+ unsigned int pin_mosi;
+ unsigned int pin_miso;
+ unsigned int pin_cs;
+
+ unsigned int board_size;
+ struct spi_board_info *board_info;
+ struct glamo_core *glamo;
+};
+
+
+#endif
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -146,6 +146,12 @@
struct pbe *next;
};
+/**
+ * global indication we are somewhere between start of suspend and end of
+ * resume, nonzero is true
+ */
+extern int global_inside_suspend;
+
/* mm/page_alloc.c */
extern void mark_free_pages(struct zone *zone);
--- /dev/null
+++ b/include/linux/ts_filter_group.h
@@ -0,0 +1,39 @@
+#ifndef __TS_FILTER_GROUP_H__
+#define __TS_FILTER_GROUP_H__
+
+#include <linux/ts_filter.h>
+
+/*
+ * Touchscreen group filter.
+ *
+ * Copyright (C) 2008 by Openmoko, Inc.
+ * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
+ *
+ */
+
+struct ts_filter_group_configuration {
+ int extent;
+ int close_enough;
+ int threshold;
+ int attempts;
+};
+
+struct ts_filter_group {
+ struct ts_filter tsf;
+ struct ts_filter_group_configuration *config;
+
+ int N; /* How many samples we have */
+ int *samples[MAX_TS_FILTER_COORDS]; /* the samples, our input */
+
+ int *group_size; /* used for temporal computations */
+ int *sorted_samples; /* used for temporal computations */
+
+ int range_max[MAX_TS_FILTER_COORDS]; /* max computed ranges */
+ int range_min[MAX_TS_FILTER_COORDS]; /* min computed ranges */
+
+ int tries_left; /* We finish if we don't get enough samples */
+};
+
+extern struct ts_filter_api ts_filter_group_api;
+
+#endif
--- /dev/null
+++ b/include/linux/ts_filter.h
@@ -0,0 +1,56 @@
+#ifndef __TS_FILTER_H__
+#define __TS_FILTER_H__
+
+/*
+ * touchscreen filter
+ *
+ * (c) 2008 Andy Green <andy@openmoko.com>
+ */
+
+#include <linux/platform_device.h>
+
+#define MAX_TS_FILTER_CHAIN 4 /* max filters you can chain up */
+#define MAX_TS_FILTER_COORDS 3 /* X, Y and Z (pressure) */
+
+struct ts_filter;
+
+/* operations that a filter can perform
+ */
+struct ts_filter_api {
+ struct ts_filter * (*create)(struct platform_device *pdev, void *config,
+ int count_coords);
+ void (*destroy)(struct platform_device *pdev, struct ts_filter *filter);
+ void (*clear)(struct ts_filter *filter);
+ int (*process)(struct ts_filter *filter, int *coords);
+ void (*scale)(struct ts_filter *filter, int *coords);
+};
+
+/* this is the common part of all filters, the result
+ * we use this type as an otherwise opaque handle on to
+ * the actual filter. Therefore you need one of these
+ * at the start of your actual filter struct
+ */
+
+struct ts_filter {
+ struct ts_filter *next; /* next in chain */
+ struct ts_filter_api *api; /* operations to use for this object */
+ int count_coords;
+ int coords[MAX_TS_FILTER_COORDS];
+};
+
+/*
+ * helper to create a filter chain from array of API pointers and
+ * array of config ints... leaves pointers to created filters in list
+ * array and fills in ->next pointers to create the chain
+ */
+
+extern int ts_filter_create_chain(struct platform_device *pdev,
+ struct ts_filter_api **api, void **config,
+ struct ts_filter **list, int count_coords);
+
+/* helper to destroy a whole chain from the list of filter pointers */
+
+extern void ts_filter_destroy_chain(struct platform_device *pdev,
+ struct ts_filter **list);
+
+#endif
--- /dev/null
+++ b/include/linux/ts_filter_linear.h
@@ -0,0 +1,64 @@
+#ifndef __TS_FILTER_LINEAR_H__
+#define __TS_FILTER_LINEAR_H__
+
+#include <linux/ts_filter.h>
+#include <linux/kobject.h>
+
+/*
+ * touchscreen linear filter.
+ *
+ * Copyright (C) 2008 by Openmoko, Inc.
+ * Author: Nelson Castillo <arhuaco@freaks-unidos.net>
+ *
+ */
+
+#define TS_FILTER_LINEAR_NCONSTANTS 7
+
+/* sysfs */
+
+struct ts_filter_linear;
+
+struct const_obj {
+ struct ts_filter_linear *tsfl;
+ struct kobject kobj;
+};
+
+#define to_const_obj(x) container_of(x, struct const_obj, kobj)
+
+struct const_attribute {
+ struct attribute attr;
+ ssize_t (*show)(struct const_obj *const, struct const_attribute *attr,
+ char *buf);
+ ssize_t (*store)(struct const_obj *const, struct const_attribute *attr,
+ const char *buf, size_t count);
+};
+
+#define to_const_attr(x) container_of(x, struct const_attribute, attr)
+
+/* filter configuration */
+
+struct ts_filter_linear_configuration {
+ int constants[TS_FILTER_LINEAR_NCONSTANTS];
+ int coord0;
+ int coord1;
+};
+
+/* the filter */
+
+struct ts_filter_linear {
+ struct ts_filter tsf;
+ struct ts_filter_linear_configuration *config;
+
+ int constants[TS_FILTER_LINEAR_NCONSTANTS];
+
+ /* sysfs */
+ struct const_obj c_obj;
+ struct kobj_type const_ktype;
+ struct const_attribute kattrs[TS_FILTER_LINEAR_NCONSTANTS];
+ struct attribute *attrs[TS_FILTER_LINEAR_NCONSTANTS + 1];
+ char attr_names[TS_FILTER_LINEAR_NCONSTANTS][2];
+};
+
+extern struct ts_filter_api ts_filter_linear_api;
+
+#endif
--- /dev/null
+++ b/include/linux/ts_filter_mean.h
@@ -0,0 +1,34 @@
+#ifndef __TS_FILTER_MEAN_H__
+#define __TS_FILTER_MEAN_H__
+
+#include <linux/ts_filter.h>
+
+/*
+ * touchscreen filter
+ *
+ * mean
+ *
+ * (c) 2008 Andy Green <andy@openmoko.com>
+ */
+
+struct ts_filter_mean_configuration {
+ int bits_filter_length;
+ int averaging_threshold;
+
+ int extent;
+};
+
+struct ts_filter_mean {
+ struct ts_filter tsf;
+ struct ts_filter_mean_configuration *config;
+
+ int reported[MAX_TS_FILTER_COORDS];
+ int lowpass[MAX_TS_FILTER_COORDS];
+ int *fifo[MAX_TS_FILTER_COORDS];
+ int fhead[MAX_TS_FILTER_COORDS];
+ int ftail[MAX_TS_FILTER_COORDS];
+};
+
+extern struct ts_filter_api ts_filter_mean_api;
+
+#endif
--- /dev/null
+++ b/include/linux/ts_filter_median.h
@@ -0,0 +1,36 @@
+#ifndef __TS_FILTER_MEDIAN_H__
+#define __TS_FILTER_MEDIAN_H__
+
+#include <linux/ts_filter.h>
+
+/*
+ * touchscreen filter
+ *
+ * median
+ *
+ * (c) 2008 Andy Green <andy@openmoko.com>
+ */
+
+struct ts_filter_median_configuration {
+ int extent;
+ int midpoint;
+ int decimation_threshold;
+ int decimation_above;
+ int decimation_below;
+};
+
+struct ts_filter_median {
+ struct ts_filter tsf;
+ struct ts_filter_median_configuration *config;
+
+ int decimation_count;
+ int last_issued[MAX_TS_FILTER_COORDS];
+ int valid; /* how many samples in the sort buffer are valid */
+ int *sort[MAX_TS_FILTER_COORDS]; /* samples taken for median */
+ int *fifo[MAX_TS_FILTER_COORDS]; /* samples taken for median */
+ int pos; /* where we are in the fifo sample memory */
+};
+
+extern struct ts_filter_api ts_filter_median_api;
+
+#endif
--- a/include/linux/vt.h
+++ b/include/linux/vt.h
@@ -18,8 +18,19 @@
* resizing).
*/
#define MIN_NR_CONSOLES 1 /* must be at least 1 */
+#if (CONFIG_NR_TTY_DEVICES < 4)
+/* Lower Limit */
+#define MAX_NR_CONSOLES 4 /* serial lines start at 64 */
+#define MAX_NR_USER_CONSOLES 4 /* must be root to allocate above this */
+#elif (CONFIG_NR_TTY_DEVICES > 63)
+/* Upper Limit */
#define MAX_NR_CONSOLES 63 /* serial lines start at 64 */
#define MAX_NR_USER_CONSOLES 63 /* must be root to allocate above this */
+#else
+/* They chose a sensible number */
+#define MAX_NR_CONSOLES CONFIG_NR_TTY_DEVICES
+#define MAX_NR_USER_CONSOLES CONFIG_NR_TTY_DEVICES
+#endif
/* Note: the ioctl VT_GETSTATE does not work for
consoles 16 and higher (since it returns a short) */
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -244,6 +244,13 @@
int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin);
int snd_soc_dapm_sync(struct snd_soc_codec *codec);
+/* dapm audio endpoint control */
+int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
+ char *pin, int status);
+int snd_soc_dapm_get_endpoint(struct snd_soc_codec *codec,
+ char *pin);
+int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec);
+
/* dapm widget types */
enum snd_soc_dapm_type {
snd_soc_dapm_input = 0, /* input pin */
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -732,6 +732,15 @@
by some high performance threaded applications. Disabling
this option saves about 7k.
+config ASHMEM
+ bool "Enable Android's Shared Memory Subsystem"
+ default n
+ depends on SHMEM || TINY_SHMEM
+ help
+ The ashmem subsystem is a new shared memory allocator, similar to
+ POSIX SHM but with different behavior and sporting a simpler
+ file-based API.
+
config VM_EVENT_COUNTERS
default y
bool "Enable VM event counters for /proc/vmstat" if EMBEDDED
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -380,6 +380,7 @@
out_unlock:
spin_unlock(&desc->lock);
}
+EXPORT_SYMBOL(handle_level_irq);
/**
* handle_fasteoi_irq - irq handler for transparent controllers
@@ -583,6 +584,7 @@
}
spin_unlock_irqrestore(&desc->lock, flags);
}
+EXPORT_SYMBOL(__set_irq_handler);
void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
--- a/kernel/power/main.c
+++ b/kernel/power/main.c
@@ -132,6 +132,9 @@
#endif /* CONFIG_PM_SLEEP */
+int global_inside_suspend;
+EXPORT_SYMBOL(global_inside_suspend);
+
#ifdef CONFIG_SUSPEND
#ifdef CONFIG_PM_TEST_SUSPEND
@@ -322,6 +325,8 @@
if (!suspend_ops)
return -ENOSYS;
+ global_inside_suspend = 1;
+
if (suspend_ops->begin) {
error = suspend_ops->begin(state);
if (error)
@@ -365,6 +370,8 @@
Close:
if (suspend_ops->end)
suspend_ops->end();
+ global_inside_suspend = 0;
+
return error;
Recover_platform:
@@ -427,6 +434,8 @@
return -EBUSY;
printk(KERN_INFO "PM: Syncing filesystems ... ");
+ global_inside_suspend = 1;
+
sys_sync();
printk("done.\n");
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -32,8 +32,11 @@
#include <linux/security.h>
#include <linux/bootmem.h>
#include <linux/syscalls.h>
+#include <linux/jiffies.h>
+#include <linux/suspend.h>
#include <asm/uaccess.h>
+#include <asm/plat-s3c24xx/neo1973.h>
/*
* Architectures can override it:
@@ -67,6 +70,12 @@
int oops_in_progress;
EXPORT_SYMBOL(oops_in_progress);
+void (*printk_emergency_debug_spew_init)(void) = NULL;
+EXPORT_SYMBOL(printk_emergency_debug_spew_init);
+
+void (*printk_emergency_debug_spew_send_string)(const char *) = NULL;
+EXPORT_SYMBOL(printk_emergency_debug_spew_send_string);
+
/*
* console_sem protects the console_drivers list, and also
* provides serialisation for access to the entire console
@@ -667,8 +676,39 @@
/* Emit the output into the temporary buffer */
printed_len += vscnprintf(printk_buf + printed_len,
sizeof(printk_buf) - printed_len, fmt, args);
-
-
+#ifdef CONFIG_MACH_NEO1973_GTA02
+ /* if you're debugging resume, the normal methods can change resume
+ * ordering behaviours because their debugging output is synchronous
+ * (ie, CONFIG_DEBUG_LL). If your problem is an OOPS, this code
+ * will not affect the speed and duration and ordering of resume
+ * actions, but will give you a chance to read the full undumped
+ * syslog AND the OOPS data when it happens
+ *
+ * if you support it, your debug device init can override the exported
+ * emergency_debug_spew_init and emergency_debug_spew_send_string to
+ * usually force polling or bitbanging on your debug console device
+ */
+ if (oops_in_progress && global_inside_suspend &&
+ printk_emergency_debug_spew_init &&
+ printk_emergency_debug_spew_send_string) {
+ unsigned long cur_index;
+ char ch[2];
+
+ if (global_inside_suspend == 1) {
+ (printk_emergency_debug_spew_init)();
+
+ ch[1] = '\0';
+ cur_index = con_start;
+ while (cur_index != log_end) {
+ ch[0] = LOG_BUF(cur_index);
+ (printk_emergency_debug_spew_send_string)(ch);
+ cur_index++;
+ }
+ global_inside_suspend++; /* only once */
+ }
+ (printk_emergency_debug_spew_send_string)(printk_buf);
+ }
+#endif
/*
* Copy the output into log_buf. If the caller didn't provide
* appropriate log level tags, we insert them here
--- a/kernel/timer.c
+++ b/kernel/timer.c
@@ -813,7 +813,11 @@
* don't have to detach them individually.
*/
list_for_each_entry_safe(timer, tmp, &tv_list, entry) {
- BUG_ON(tbase_get_base(timer->base) != base);
+ if (tbase_get_base(timer->base) != base) {
+ printk(KERN_ERR "cascade: timer %p: tbase_get_base(timer->base) 0x%x "
+ "!= base 0x%x\n", timer, tbase_get_base(timer->base), base);
+ BUG_ON(1);
+ }
internal_add_timer(base, timer);
}
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1705,6 +1705,20 @@
P: Matthew Wilcox
M: matthew@wil.cx
L: linux-fsdevel@vger.kernel.org
+
+FIC/OPENMOKO NEO1973 GSM PHONE
+P: Harald Welte
+M: laforge@openmoko.org
+L: openmoko-kernel@lists.openmoko.org
+W: http://wiki.openmoko.org/wiki/Kernel
+W: http://wiki.openmoko.org/wiki/Neo1973
+S: Maintained
+
+FRAMEBUFFER LAYER
+P: Antonino Daplas
+M: adaplas@gmail.com
+L: linux-fbdev-devel@lists.sourceforge.net (moderated for non-subscribers)
+W: http://linux-fbdev.sourceforge.net/
S: Maintained
FILESYSTEMS (VFS and infrastructure)
--- /dev/null
+++ b/makerecovery
@@ -0,0 +1,17 @@
+#!/bin/sh
+#
+# make 6MB recovery image from two moredrivers type kernels
+# placed at start and at +4MBytes
+
+if [ -z "$1" ] ; then
+ echo "Usage: $0 uImage-moredrivers-..."
+ exit 1
+fi
+cat $1 > recovery-$1
+SIZE=`ls -l $1 | tr -s ' ' ' ' | cut -d' ' -f5`
+SPACE=$(( 4 * 1024 * 1024 - $SIZE ))
+dd if=/dev/zero of=_spacer bs=1 count=$SPACE
+cat _spacer >> recovery-$1
+rm -f _spacer
+cat $1 >> recovery-$1
+
--- /dev/null
+++ b/mm/ashmem.c
@@ -0,0 +1,657 @@
+/* drivers/android/ashmem.c
+**
+** Android / Anonymous Shared Memory Subsystem, ashmem
+**
+** Copyright (C) 2008 Google, Inc.
+**
+** Robert Love <rlove@google.com>
+**
+** This software is licensed under the terms of the GNU General Public
+** License version 2, as published by the Free Software Foundation, and
+** may be copied, distributed, and modified under those terms.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+** GNU General Public License for more details.
+*/
+
+#include <linux/module.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/security.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/uaccess.h>
+#include <linux/personality.h>
+#include <linux/bitops.h>
+#include <linux/mutex.h>
+#include <linux/shmem_fs.h>
+#include <linux/ashmem.h>
+
+/*
+ * ashmem_area - android shared memory area
+ * Lifecycle: From our parent file's open() until its release()
+ * Locking: Protected by `ashmem_mutex'
+ * Big Note: Mappings do NOT pin this structure; it dies on close()
+ */
+struct ashmem_area {
+ char name[ASHMEM_NAME_LEN]; /* optional name for /proc/pid/maps */
+ struct list_head unpinned_list; /* list of all ashmem areas */
+ struct file *file; /* the shmem-based backing file */
+ size_t size; /* size of the mapping, in bytes */
+ unsigned long prot_mask; /* allowed prot bits, as vm_flags */
+};
+
+/*
+ * ashmem_range - represents an interval of unpinned (evictable) pages
+ * Lifecycle: From unpin to pin
+ * Locking: Protected by `ashmem_mutex'
+ */
+struct ashmem_range {
+ struct list_head lru; /* entry in LRU list */
+ struct list_head unpinned; /* entry in its area's unpinned list */
+ struct ashmem_area *asma; /* associated area */
+ size_t pgstart; /* starting page, inclusive */
+ size_t pgend; /* ending page, inclusive */
+ unsigned int purged; /* ASHMEM_NOT or ASHMEM_WAS_PURGED */
+};
+
+/* LRU list of unpinned pages, protected by ashmem_mutex */
+static LIST_HEAD(ashmem_lru_list);
+
+/* Count of pages on our LRU list, protected by ashmem_mutex */
+static unsigned long lru_count;
+
+/*
+ * ashmem_mutex - protects the list of and each individual ashmem_area
+ *
+ * Lock Ordering: ashmex_mutex -> i_mutex -> i_alloc_sem
+ */
+static DEFINE_MUTEX(ashmem_mutex);
+
+static struct kmem_cache *ashmem_area_cachep __read_mostly;
+static struct kmem_cache *ashmem_range_cachep __read_mostly;
+
+#define range_size(range) \
+ ((range)->pgend - (range)->pgstart + 1)
+
+#define range_on_lru(range) \
+ ((range)->purged == ASHMEM_NOT_PURGED)
+
+#define page_range_subsumes_range(range, start, end) \
+ (((range)->pgstart >= (start)) && ((range)->pgend <= (end)))
+
+#define page_range_subsumed_by_range(range, start, end) \
+ (((range)->pgstart <= (start)) && ((range)->pgend >= (end)))
+
+#define page_in_range(range, page) \
+ (((range)->pgstart <= (page)) && ((range)->pgend >= (page)))
+
+#define page_range_in_range(range, start, end) \
+ (page_in_range(range, start) || page_in_range(range, end) || \
+ page_range_subsumes_range(range, start, end))
+
+#define range_before_page(range, page) \
+ ((range)->pgend < (page))
+
+#define PROT_MASK (PROT_EXEC | PROT_READ | PROT_WRITE)
+
+static inline void lru_add(struct ashmem_range *range)
+{
+ list_add_tail(&range->lru, &ashmem_lru_list);
+ lru_count += range_size(range);
+}
+
+static inline void lru_del(struct ashmem_range *range)
+{
+ list_del(&range->lru);
+ lru_count -= range_size(range);
+}
+
+/*
+ * range_alloc - allocate and initialize a new ashmem_range structure
+ *
+ * 'asma' - associated ashmem_area
+ * 'prev_range' - the previous ashmem_range in the sorted asma->unpinned list
+ * 'purged' - initial purge value (ASMEM_NOT_PURGED or ASHMEM_WAS_PURGED)
+ * 'start' - starting page, inclusive
+ * 'end' - ending page, inclusive
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int range_alloc(struct ashmem_area *asma,
+ struct ashmem_range *prev_range, unsigned int purged,
+ size_t start, size_t end)
+{
+ struct ashmem_range *range;
+
+ range = kmem_cache_zalloc(ashmem_range_cachep, GFP_KERNEL);
+ if (unlikely(!range))
+ return -ENOMEM;
+
+ range->asma = asma;
+ range->pgstart = start;
+ range->pgend = end;
+ range->purged = purged;
+
+ list_add_tail(&range->unpinned, &prev_range->unpinned);
+
+ if (range_on_lru(range))
+ lru_add(range);
+
+ return 0;
+}
+
+static void range_del(struct ashmem_range *range)
+{
+ list_del(&range->unpinned);
+ if (range_on_lru(range))
+ lru_del(range);
+ kmem_cache_free(ashmem_range_cachep, range);
+}
+
+/*
+ * range_shrink - shrinks a range
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static inline void range_shrink(struct ashmem_range *range,
+ size_t start, size_t end)
+{
+ size_t pre = range_size(range);
+
+ range->pgstart = start;
+ range->pgend = end;
+
+ if (range_on_lru(range))
+ lru_count -= pre - range_size(range);
+}
+
+static int ashmem_open(struct inode *inode, struct file *file)
+{
+ struct ashmem_area *asma;
+ int ret;
+
+ ret = nonseekable_open(inode, file);
+ if (unlikely(ret))
+ return ret;
+
+ asma = kmem_cache_zalloc(ashmem_area_cachep, GFP_KERNEL);
+ if (unlikely(!asma))
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&asma->unpinned_list);
+ asma->prot_mask = PROT_MASK;
+ file->private_data = asma;
+
+ return 0;
+}
+
+static int ashmem_release(struct inode *ignored, struct file *file)
+{
+ struct ashmem_area *asma = file->private_data;
+ struct ashmem_range *range, *next;
+
+ mutex_lock(&ashmem_mutex);
+ list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned)
+ range_del(range);
+ mutex_unlock(&ashmem_mutex);
+
+ if (asma->file)
+ fput(asma->file);
+ kmem_cache_free(ashmem_area_cachep, asma);
+
+ return 0;
+}
+
+static int ashmem_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ struct ashmem_area *asma = file->private_data;
+ int ret = 0;
+
+ mutex_lock(&ashmem_mutex);
+
+ /* user needs to SET_SIZE before mapping */
+ if (unlikely(!asma->size)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* requested protection bits must match our allowed protection mask */
+ if (unlikely((vma->vm_flags & ~asma->prot_mask) & PROT_MASK)) {
+ ret = -EPERM;
+ goto out;
+ }
+
+ if (!asma->file) {
+ char *name = ASHMEM_NAME_DEF;
+ struct file *vmfile;
+
+ if (asma->name[0] != '\0')
+ name = asma->name;
+
+ /* ... and allocate the backing shmem file */
+ vmfile = shmem_file_setup(name, asma->size, vma->vm_flags);
+ if (unlikely(IS_ERR(vmfile))) {
+ ret = PTR_ERR(vmfile);
+ goto out;
+ }
+ asma->file = vmfile;
+ }
+ get_file(asma->file);
+
+ shmem_set_file(vma, asma->file);
+ vma->vm_flags |= VM_CAN_NONLINEAR;
+
+out:
+ mutex_unlock(&ashmem_mutex);
+ return ret;
+}
+
+/*
+ * ashmem_shrink - our cache shrinker, called from mm/vmscan.c :: shrink_slab
+ *
+ * 'nr_to_scan' is the number of objects (pages) to prune, or 0 to query how
+ * many objects (pages) we have in total.
+ *
+ * 'gfp_mask' is the mask of the allocation that got us into this mess.
+ *
+ * Return value is the number of objects (pages) remaining, or -1 if we cannot
+ * proceed without risk of deadlock (due to gfp_mask).
+ *
+ * We approximate LRU via least-recently-unpinned, jettisoning unpinned partial
+ * chunks of ashmem regions LRU-wise one-at-a-time until we hit 'nr_to_scan'
+ * pages freed.
+ */
+static int ashmem_shrink(int nr_to_scan, gfp_t gfp_mask)
+{
+ struct ashmem_range *range, *next;
+
+ /* We might recurse into filesystem code, so bail out if necessary */
+ if (nr_to_scan && !(gfp_mask & __GFP_FS))
+ return -1;
+ if (!nr_to_scan)
+ return lru_count;
+
+ mutex_lock(&ashmem_mutex);
+ list_for_each_entry_safe(range, next, &ashmem_lru_list, lru) {
+ struct inode *inode = range->asma->file->f_dentry->d_inode;
+ loff_t start = range->pgstart * PAGE_SIZE;
+ loff_t end = (range->pgend + 1) * PAGE_SIZE - 1;
+
+ vmtruncate_range(inode, start, end);
+ range->purged = ASHMEM_WAS_PURGED;
+ lru_del(range);
+
+ nr_to_scan -= range_size(range);
+ if (nr_to_scan <= 0)
+ break;
+ }
+ mutex_unlock(&ashmem_mutex);
+
+ return lru_count;
+}
+
+static struct shrinker ashmem_shrinker = {
+ .shrink = ashmem_shrink,
+ .seeks = DEFAULT_SEEKS * 4,
+};
+
+static int set_prot_mask(struct ashmem_area *asma, unsigned long prot)
+{
+ int ret = 0;
+
+ mutex_lock(&ashmem_mutex);
+
+ /* the user can only remove, not add, protection bits */
+ if (unlikely((asma->prot_mask & prot) != prot)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* does the application expect PROT_READ to imply PROT_EXEC? */
+ if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC))
+ prot |= PROT_EXEC;
+
+ asma->prot_mask = prot;
+
+out:
+ mutex_unlock(&ashmem_mutex);
+ return ret;
+}
+
+static int set_name(struct ashmem_area *asma, void __user *name)
+{
+ int ret = 0;
+
+ mutex_lock(&ashmem_mutex);
+
+ /* cannot change an existing mapping's name */
+ if (unlikely(asma->file)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (unlikely(copy_from_user(asma->name, name, ASHMEM_NAME_LEN)))
+ ret = -EFAULT;
+ asma->name[ASHMEM_NAME_LEN-1] = '\0';
+
+out:
+ mutex_unlock(&ashmem_mutex);
+
+ return ret;
+}
+
+static int get_name(struct ashmem_area *asma, void __user *name)
+{
+ int ret = 0;
+
+ mutex_lock(&ashmem_mutex);
+ if (asma->name[0] != '\0') {
+ size_t len;
+
+ /*
+ * Copying only `len', instead of ASHMEM_NAME_LEN, bytes
+ * prevents us from revealing one user's stack to another.
+ */
+ len = strlen(asma->name) + 1;
+ if (unlikely(copy_to_user(name, asma->name, len)))
+ ret = -EFAULT;
+ } else {
+ if (unlikely(copy_to_user(name, ASHMEM_NAME_DEF,
+ sizeof(ASHMEM_NAME_DEF))))
+ ret = -EFAULT;
+ }
+ mutex_unlock(&ashmem_mutex);
+
+ return ret;
+}
+
+/*
+ * ashmem_pin - pin the given ashmem region, returning whether it was
+ * previously purged (ASHMEM_WAS_PURGED) or not (ASHMEM_NOT_PURGED).
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int ashmem_pin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
+{
+ struct ashmem_range *range, *next;
+ int ret = ASHMEM_NOT_PURGED;
+
+ list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
+ /* moved past last applicable page; we can short circuit */
+ if (range_before_page(range, pgstart))
+ break;
+
+ /*
+ * The user can ask us to pin pages that span multiple ranges,
+ * or to pin pages that aren't even unpinned, so this is messy.
+ *
+ * Four cases:
+ * 1. The requested range subsumes an existing range, so we
+ * just remove the entire matching range.
+ * 2. The requested range overlaps the start of an existing
+ * range, so we just update that range.
+ * 3. The requested range overlaps the end of an existing
+ * range, so we just update that range.
+ * 4. The requested range punches a hole in an existing range,
+ * so we have to update one side of the range and then
+ * create a new range for the other side.
+ */
+ if (page_range_in_range(range, pgstart, pgend)) {
+ ret |= range->purged;
+
+ /* Case #1: Easy. Just nuke the whole thing. */
+ if (page_range_subsumes_range(range, pgstart, pgend)) {
+ range_del(range);
+ continue;
+ }
+
+ /* Case #2: We overlap from the start, so adjust it */
+ if (range->pgstart >= pgstart) {
+ range_shrink(range, pgend + 1, range->pgend);
+ continue;
+ }
+
+ /* Case #3: We overlap from the rear, so adjust it */
+ if (range->pgend <= pgend) {
+ range_shrink(range, range->pgstart, pgstart-1);
+ continue;
+ }
+
+ /*
+ * Case #4: We eat a chunk out of the middle. A bit
+ * more complicated, we allocate a new range for the
+ * second half and adjust the first chunk's endpoint.
+ */
+ range_alloc(asma, range, range->purged,
+ pgend + 1, range->pgend);
+ range_shrink(range, range->pgstart, pgstart - 1);
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * ashmem_unpin - unpin the given range of pages. Returns zero on success.
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int ashmem_unpin(struct ashmem_area *asma, size_t pgstart, size_t pgend)
+{
+ struct ashmem_range *range, *next;
+ unsigned int purged = ASHMEM_NOT_PURGED;
+
+restart:
+ list_for_each_entry_safe(range, next, &asma->unpinned_list, unpinned) {
+ /* short circuit: this is our insertion point */
+ if (range_before_page(range, pgstart))
+ break;
+
+ /*
+ * The user can ask us to unpin pages that are already entirely
+ * or partially pinned. We handle those two cases here.
+ */
+ if (page_range_subsumed_by_range(range, pgstart, pgend))
+ return 0;
+ if (page_range_in_range(range, pgstart, pgend)) {
+ pgstart = min_t(size_t, range->pgstart, pgstart),
+ pgend = max_t(size_t, range->pgend, pgend);
+ purged |= range->purged;
+ range_del(range);
+ goto restart;
+ }
+ }
+
+ return range_alloc(asma, range, purged, pgstart, pgend);
+}
+
+/*
+ * ashmem_get_pin_status - Returns ASHMEM_IS_UNPINNED if _any_ pages in the
+ * given interval are unpinned and ASHMEM_IS_PINNED otherwise.
+ *
+ * Caller must hold ashmem_mutex.
+ */
+static int ashmem_get_pin_status(struct ashmem_area *asma, size_t pgstart,
+ size_t pgend)
+{
+ struct ashmem_range *range;
+ int ret = ASHMEM_IS_PINNED;
+
+ list_for_each_entry(range, &asma->unpinned_list, unpinned) {
+ if (range_before_page(range, pgstart))
+ break;
+ if (page_range_in_range(range, pgstart, pgend)) {
+ ret = ASHMEM_IS_UNPINNED;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd,
+ void __user *p)
+{
+ struct ashmem_pin pin;
+ size_t pgstart, pgend;
+ int ret = -EINVAL;
+
+ if (unlikely(!asma->file))
+ return -EINVAL;
+
+ if (unlikely(copy_from_user(&pin, p, sizeof(pin))))
+ return -EFAULT;
+
+ /* per custom, you can pass zero for len to mean "everything onward" */
+ if (!pin.len)
+ pin.len = asma->size - pin.offset;
+
+ if (unlikely((pin.offset | pin.len) & ~PAGE_MASK))
+ return -EINVAL;
+
+ if (unlikely(((__u32) -1) - pin.offset < pin.len))
+ return -EINVAL;
+
+ if (unlikely(asma->size < pin.offset + pin.len))
+ return -EINVAL;
+
+ pgstart = pin.offset / PAGE_SIZE;
+ pgend = pgstart + (pin.len / PAGE_SIZE) - 1;
+
+ mutex_lock(&ashmem_mutex);
+
+ switch (cmd) {
+ case ASHMEM_PIN:
+ ret = ashmem_pin(asma, pgstart, pgend);
+ break;
+ case ASHMEM_UNPIN:
+ ret = ashmem_unpin(asma, pgstart, pgend);
+ break;
+ case ASHMEM_GET_PIN_STATUS:
+ ret = ashmem_get_pin_status(asma, pgstart, pgend);
+ break;
+ }
+
+ mutex_unlock(&ashmem_mutex);
+
+ return ret;
+}
+
+static long ashmem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct ashmem_area *asma = file->private_data;
+ long ret = -ENOTTY;
+
+ switch (cmd) {
+ case ASHMEM_SET_NAME:
+ ret = set_name(asma, (void __user *) arg);
+ break;
+ case ASHMEM_GET_NAME:
+ ret = get_name(asma, (void __user *) arg);
+ break;
+ case ASHMEM_SET_SIZE:
+ ret = -EINVAL;
+ if (!asma->file && !(arg & ~PAGE_MASK)) {
+ ret = 0;
+ asma->size = (size_t) arg;
+ }
+ break;
+ case ASHMEM_GET_SIZE:
+ ret = asma->size;
+ break;
+ case ASHMEM_SET_PROT_MASK:
+ ret = set_prot_mask(asma, arg);
+ break;
+ case ASHMEM_GET_PROT_MASK:
+ ret = asma->prot_mask;
+ break;
+ case ASHMEM_PIN:
+ case ASHMEM_UNPIN:
+ case ASHMEM_GET_PIN_STATUS:
+ ret = ashmem_pin_unpin(asma, cmd, (void __user *) arg);
+ break;
+ case ASHMEM_PURGE_ALL_CACHES:
+ ret = -EPERM;
+ if (capable(CAP_SYS_ADMIN)) {
+ ret = ashmem_shrink(0, GFP_KERNEL);
+ ashmem_shrink(ret, GFP_KERNEL);
+ }
+ break;
+ }
+
+ return ret;
+}
+
+static struct file_operations ashmem_fops = {
+ .owner = THIS_MODULE,
+ .open = ashmem_open,
+ .release = ashmem_release,
+ .mmap = ashmem_mmap,
+ .unlocked_ioctl = ashmem_ioctl,
+ .compat_ioctl = ashmem_ioctl,
+};
+
+static struct miscdevice ashmem_misc = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = "ashmem",
+ .fops = &ashmem_fops,
+};
+
+static int __init ashmem_init(void)
+{
+ int ret;
+
+ ashmem_area_cachep = kmem_cache_create("ashmem_area_cache",
+ sizeof(struct ashmem_area),
+ 0, 0, NULL);
+ if (unlikely(!ashmem_area_cachep)) {
+ printk(KERN_ERR "ashmem: failed to create slab cache\n");
+ return -ENOMEM;
+ }
+
+ ashmem_range_cachep = kmem_cache_create("ashmem_range_cache",
+ sizeof(struct ashmem_range),
+ 0, 0, NULL);
+ if (unlikely(!ashmem_range_cachep)) {
+ printk(KERN_ERR "ashmem: failed to create slab cache\n");
+ return -ENOMEM;
+ }
+
+ ret = misc_register(&ashmem_misc);
+ if (unlikely(ret)) {
+ printk(KERN_ERR "ashmem: failed to register misc device!\n");
+ return ret;
+ }
+
+ register_shrinker(&ashmem_shrinker);
+
+ printk(KERN_INFO "ashmem: initialized\n");
+
+ return 0;
+}
+
+static void __exit ashmem_exit(void)
+{
+ int ret;
+
+ unregister_shrinker(&ashmem_shrinker);
+
+ ret = misc_deregister(&ashmem_misc);
+ if (unlikely(ret))
+ printk(KERN_ERR "ashmem: failed to unregister misc device!\n");
+
+ kmem_cache_destroy(ashmem_range_cachep);
+ kmem_cache_destroy(ashmem_area_cachep);
+
+ printk(KERN_INFO "ashmem: unloaded\n");
+}
+
+module_init(ashmem_init);
+module_exit(ashmem_exit);
+
+MODULE_LICENSE("GPL");
--- a/mm/Makefile
+++ b/mm/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_SPARSEMEM) += sparse.o
obj-$(CONFIG_SPARSEMEM_VMEMMAP) += sparse-vmemmap.o
obj-$(CONFIG_SHMEM) += shmem.o
+obj-$(CONFIG_ASHMEM) += ashmem.o
obj-$(CONFIG_TMPFS_POSIX_ACL) += shmem_acl.o
obj-$(CONFIG_TINY_SHMEM) += tiny-shmem.o
obj-$(CONFIG_SLOB) += slob.o
--- a/mm/tiny-shmem.c
+++ b/mm/tiny-shmem.c
@@ -97,6 +97,22 @@
}
EXPORT_SYMBOL_GPL(shmem_file_setup);
+void shmem_set_file(struct vm_area_struct *vma, struct file *file)
+{
+ if (vma->vm_file)
+ fput(vma->vm_file);
+ vma->vm_file = file;
+ vma->vm_ops = &generic_file_vm_ops;
+}
+
+void shmem_set_file(struct vm_area_struct *vma, struct file *file)
+{
+ if (vma->vm_file)
+ fput(vma->vm_file);
+ vma->vm_file = file;
+ vma->vm_ops = &generic_file_vm_ops;
+}
+
/**
* shmem_zero_setup - setup a shared anonymous mapping
* @vma: the vma to be mmapped is prepared by do_mmap_pgoff
@@ -110,10 +126,8 @@
if (IS_ERR(file))
return PTR_ERR(file);
- if (vma->vm_file)
- fput(vma->vm_file);
- vma->vm_file = file;
- vma->vm_ops = &generic_file_vm_ops;
+ shmem_set_file(vma, file);
+
return 0;
}
--- /dev/null
+++ b/remote_install_sdcard
@@ -0,0 +1,18 @@
+#!/bin/sh
+
+# automatic kernel updater and reboot - Andy Green <andy@openmoko.com>
+
+GTA_DEVICE_IP=192.168.0.202
+
+# you should set up key-based auth on dropbear if you want
+# to play this game.
+#
+# 1) mkdir /home/root/.ssh
+# 2) chown root:root / /home /home/root
+# 3) chmod 700 /home/root /home/root/.ssh
+# 4) copy your id_*.pub into /home/root/.ssh/authorized_keys
+# 5) chmod 600 /home/root/.ssh/*
+
+scp uImage.bin root@$GTA_DEVICE_IP:/boot
+ssh root@$GTA_DEVICE_IP "mount /dev/mmcblk0p1 / -oremount,ro ; reboot -if &"
+
--- a/scripts/mkuboot.sh
+++ b/scripts/mkuboot.sh
@@ -11,7 +11,7 @@
if [ -z "${MKIMAGE}" ]; then
# Doesn't exist
echo '"mkimage" command not found - U-Boot images will not be built' >&2
- exit 0;
+ exit 1;
fi
fi
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -1584,6 +1584,9 @@
schedule_delayed_work(&codec->delayed_work,
msecs_to_jiffies(caps_charge));
+ /* Fix reg WM8753_ADCTL2 */
+ wm8753_write(codec, WM8753_ADCTL2, 0x0000);
+
/* set the update bits */
reg = wm8753_read_reg_cache(codec, WM8753_LDAC);
wm8753_write(codec, WM8753_LDAC, reg | 0x0100);
@@ -1644,17 +1647,20 @@
struct snd_soc_codec *codec = socdev->codec;
int ret;
+ /* codec->control_data must be set before call to wm8753_init */
i2c_set_clientdata(i2c, codec);
codec->control_data = i2c;
ret = wm8753_init(socdev);
- if (ret < 0)
+ if (ret < 0) {
pr_err("failed to initialise WM8753\n");
+ codec->control_data = NULL;
+ }
return ret;
}
-static int wm8753_i2c_remove(struct i2c_client *client)
+static int __devexit wm8753_i2c_remove(struct i2c_client *client)
{
struct snd_soc_codec *codec = i2c_get_clientdata(client);
kfree(codec->reg_cache);
@@ -1675,6 +1681,7 @@
.probe = wm8753_i2c_probe,
.remove = wm8753_i2c_remove,
.id_table = wm8753_i2c_id,
+ .class = I2C_CLASS_SOUND
};
static int wm8753_add_i2c_device(struct platform_device *pdev,
@@ -1716,6 +1723,8 @@
i2c_del_driver(&wm8753_i2c_driver);
return -ENODEV;
}
+
+
#endif
#if defined(CONFIG_SPI_MASTER)
@@ -1783,7 +1792,7 @@
struct wm8753_priv *wm8753;
int ret = 0;
- pr_info("WM8753 Audio Codec %s", WM8753_VERSION);
+ pr_info("WM8753 Audio Codec %s\n", WM8753_VERSION);
setup = socdev->codec_data;
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
@@ -1820,6 +1829,7 @@
#endif
if (ret != 0) {
+ printk(KERN_ERR "can't add codec bus driver\n");
kfree(codec->private_data);
kfree(codec);
}
@@ -1857,7 +1867,6 @@
snd_soc_free_pcms(socdev);
snd_soc_dapm_free(socdev);
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
- i2c_unregister_device(codec->control_data);
i2c_del_driver(&wm8753_i2c_driver);
#endif
#if defined(CONFIG_SPI_MASTER)
--- a/sound/soc/s3c24xx/Kconfig
+++ b/sound/soc/s3c24xx/Kconfig
@@ -26,6 +26,15 @@
Say Y if you want to add support for SoC audio on smdk2440
with the WM8753.
+config SND_S3C24XX_SOC_NEO1973_GTA02_WM8753
+ tristate "SoC I2S Audio support for NEO1973 GTA02 - WM8753"
+ depends on SND_S3C24XX_SOC && MACH_NEO1973_GTA02
+ select SND_S3C24XX_SOC_I2S
+ select SND_SOC_WM8753
+ help
+ Say Y if you want to add support for SoC audio on neo1973 gta02
+ with the WM8753 codec
+
config SND_S3C24XX_SOC_SMDK2443_WM9710
tristate "SoC AC97 Audio support for SMDK2443 - WM9710"
depends on SND_S3C24XX_SOC && MACH_SMDK2443
--- a/sound/soc/s3c24xx/Makefile
+++ b/sound/soc/s3c24xx/Makefile
@@ -13,7 +13,10 @@
snd-soc-neo1973-wm8753-objs := neo1973_wm8753.o
snd-soc-smdk2443-wm9710-objs := smdk2443_wm9710.o
snd-soc-ln2440sbc-alc650-objs := ln2440sbc_alc650.o
+snd-soc-neo1973-gta02-wm8753-objs := neo1973_gta02_wm8753.o
obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_WM8753) += snd-soc-neo1973-wm8753.o
obj-$(CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710) += snd-soc-smdk2443-wm9710.o
obj-$(CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650) += snd-soc-ln2440sbc-alc650.o
+obj-$(CONFIG_SND_S3C24XX_SOC_NEO1973_GTA02_WM8753) += snd-soc-neo1973-gta02-wm8753.o
+
--- /dev/null
+++ b/sound/soc/s3c24xx/neo1973_gta02_wm8753.c
@@ -0,0 +1,673 @@
+/*
+ * neo1973_gta02_wm8753.c -- SoC audio for Neo1973
+ *
+ * Copyright 2007 Openmoko Inc
+ * Author: Graeme Gregory <graeme@openmoko.org>
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory <linux@wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Revision history
+ * 06th Nov 2007 Changed from GTA01 to GTA02
+ * 20th Jan 2007 Initial version.
+ * 05th Feb 2007 Rename all to Neo1973
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#include <asm/mach-types.h>
+#include <asm/hardware/scoop.h>
+#include <asm/plat-s3c24xx/regs-iis.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/hardware.h>
+#include <mach/audio.h>
+#include <asm/io.h>
+#include <mach/spi-gpio.h>
+#include <mach/regs-gpioj.h>
+#include <mach/gta02.h>
+#include "../codecs/wm8753.h"
+#include "s3c24xx-pcm.h"
+#include "s3c24xx-i2s.h"
+
+/* define the scenarios */
+#define NEO_AUDIO_OFF 0
+#define NEO_GSM_CALL_AUDIO_HANDSET 1
+#define NEO_GSM_CALL_AUDIO_HEADSET 2
+#define NEO_GSM_CALL_AUDIO_BLUETOOTH 3
+#define NEO_STEREO_TO_SPEAKERS 4
+#define NEO_STEREO_TO_HEADPHONES 5
+#define NEO_CAPTURE_HANDSET 6
+#define NEO_CAPTURE_HEADSET 7
+#define NEO_CAPTURE_BLUETOOTH 8
+#define NEO_STEREO_TO_HANDSET_SPK 9
+
+static struct snd_soc_machine neo1973_gta02;
+
+static int neo1973_gta02_hifi_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+ struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+ unsigned int pll_out = 0, bclk = 0;
+ int ret = 0;
+ unsigned long iis_clkrate;
+
+ iis_clkrate = s3c24xx_i2s_get_clockrate();
+
+ switch (params_rate(params)) {
+ case 8000:
+ case 16000:
+ pll_out = 12288000;
+ break;
+ case 48000:
+ bclk = WM8753_BCLK_DIV_4;
+ pll_out = 12288000;
+ break;
+ case 96000:
+ bclk = WM8753_BCLK_DIV_2;
+ pll_out = 12288000;
+ break;
+ case 11025:
+ bclk = WM8753_BCLK_DIV_16;
+ pll_out = 11289600;
+ break;
+ case 22050:
+ bclk = WM8753_BCLK_DIV_8;
+ pll_out = 11289600;
+ break;
+ case 44100:
+ bclk = WM8753_BCLK_DIV_4;
+ pll_out = 11289600;
+ break;
+ case 88200:
+ bclk = WM8753_BCLK_DIV_2;
+ pll_out = 11289600;
+ break;
+ }
+
+ /* set codec DAI configuration */
+ ret = codec_dai->dai_ops.set_fmt(codec_dai,
+ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0)
+ return ret;
+
+ /* set cpu DAI configuration */
+ ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
+ SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM);
+ if (ret < 0)
+ return ret;
+
+ /* set the codec system clock for DAC and ADC */
+ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_MCLK, pll_out,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ /* set MCLK division for sample rate */
+ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK,
+ S3C2410_IISMOD_32FS );
+ if (ret < 0)
+ return ret;
+
+ /* set codec BCLK division for sample rate */
+ ret = codec_dai->dai_ops.set_clkdiv(codec_dai,
+ WM8753_BCLKDIV, bclk);
+ if (ret < 0)
+ return ret;
+
+ /* set prescaler division for sample rate */
+ ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER,
+ S3C24XX_PRESCALE(4,4));
+ if (ret < 0)
+ return ret;
+
+ /* codec PLL input is PCLK/4 */
+ ret = codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1,
+ iis_clkrate / 4, pll_out);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int neo1973_gta02_hifi_hw_free(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+
+ /* disable the PLL */
+ return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL1, 0, 0);
+}
+
+/*
+ * Neo1973 WM8753 HiFi DAI opserations.
+ */
+static struct snd_soc_ops neo1973_gta02_hifi_ops = {
+ .hw_params = neo1973_gta02_hifi_hw_params,
+ .hw_free = neo1973_gta02_hifi_hw_free,
+};
+
+static int neo1973_gta02_voice_hw_params(
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+ unsigned int pcmdiv = 0;
+ int ret = 0;
+ unsigned long iis_clkrate;
+
+ iis_clkrate = s3c24xx_i2s_get_clockrate();
+
+ if (params_rate(params) != 8000)
+ return -EINVAL;
+ if (params_channels(params) != 1)
+ return -EINVAL;
+
+ pcmdiv = WM8753_PCM_DIV_6; /* 2.048 MHz */
+
+ /* todo: gg check mode (DSP_B) against CSR datasheet */
+ /* set codec DAI configuration */
+ ret = codec_dai->dai_ops.set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ return ret;
+
+ /* set the codec system clock for DAC and ADC */
+ ret = codec_dai->dai_ops.set_sysclk(codec_dai, WM8753_PCMCLK,
+ 12288000, SND_SOC_CLOCK_IN);
+ if (ret < 0)
+ return ret;
+
+ /* set codec PCM division for sample rate */
+ ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8753_PCMDIV,
+ pcmdiv);
+ if (ret < 0)
+ return ret;
+
+ /* configue and enable PLL for 12.288MHz output */
+ ret = codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL2,
+ iis_clkrate / 4, 12288000);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int neo1973_gta02_voice_hw_free(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+
+ /* disable the PLL */
+ return codec_dai->dai_ops.set_pll(codec_dai, WM8753_PLL2, 0, 0);
+}
+
+static struct snd_soc_ops neo1973_gta02_voice_ops = {
+ .hw_params = neo1973_gta02_voice_hw_params,
+ .hw_free = neo1973_gta02_voice_hw_free,
+};
+
+#define LM4853_AMP 1
+#define LM4853_SPK 2
+
+static u8 lm4853_state=0;
+
+static int lm4853_set_state(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int val = ucontrol->value.integer.value[0];
+
+ if(val) {
+ lm4853_state |= LM4853_AMP;
+ s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT,0);
+ } else {
+ lm4853_state &= ~LM4853_AMP;
+ s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT,1);
+ }
+
+ return 0;
+}
+
+static int lm4853_get_state(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = lm4853_state & LM4853_AMP;
+
+ return 0;
+}
+
+static int lm4853_set_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ int val = ucontrol->value.integer.value[0];
+
+ if(val) {
+ lm4853_state |= LM4853_SPK;
+ s3c2410_gpio_setpin(GTA02_GPIO_HP_IN,0);
+ } else {
+ lm4853_state &= ~LM4853_SPK;
+ s3c2410_gpio_setpin(GTA02_GPIO_HP_IN,1);
+ }
+
+ return 0;
+}
+
+static int lm4853_get_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = (lm4853_state & LM4853_SPK) >> 1;
+
+ return 0;
+}
+
+static int neo1973_gta02_set_stereo_out(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int val = ucontrol->value.integer.value[0];
+
+ snd_soc_dapm_set_endpoint(codec, "Stereo Out", val);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static int neo1973_gta02_get_stereo_out(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_dapm_get_endpoint(codec, "Stereo Out");
+
+ return 0;
+}
+
+
+static int neo1973_gta02_set_gsm_out(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int val = ucontrol->value.integer.value[0];
+
+ snd_soc_dapm_set_endpoint(codec, "GSM Line Out", val);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static int neo1973_gta02_get_gsm_out(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_dapm_get_endpoint(codec, "GSM Line Out");
+
+ return 0;
+}
+
+static int neo1973_gta02_set_gsm_in(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int val = ucontrol->value.integer.value[0];
+
+ snd_soc_dapm_set_endpoint(codec, "GSM Line In", val);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static int neo1973_gta02_get_gsm_in(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_dapm_get_endpoint(codec, "GSM Line In");
+
+ return 0;
+}
+
+static int neo1973_gta02_set_headset_mic(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int val = ucontrol->value.integer.value[0];
+
+ snd_soc_dapm_set_endpoint(codec, "Headset Mic", val);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static int neo1973_gta02_get_headset_mic(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_dapm_get_endpoint(codec, "Headset Mic");
+
+ return 0;
+}
+
+static int neo1973_gta02_set_handset_mic(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int val = ucontrol->value.integer.value[0];
+
+ snd_soc_dapm_set_endpoint(codec, "Handset Mic", val);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static int neo1973_gta02_get_handset_mic(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_dapm_get_endpoint(codec, "Handset Mic");
+
+ return 0;
+}
+
+static int neo1973_gta02_set_handset_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ int val = ucontrol->value.integer.value[0];
+
+ snd_soc_dapm_set_endpoint(codec, "Handset Spk", val);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+static int neo1973_gta02_get_handset_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+ ucontrol->value.integer.value[0] =
+ snd_soc_dapm_get_endpoint(codec, "Handset Spk");
+
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
+ SND_SOC_DAPM_LINE("Stereo Out", NULL),
+ SND_SOC_DAPM_LINE("GSM Line Out", NULL),
+ SND_SOC_DAPM_LINE("GSM Line In", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("Handset Mic", NULL),
+ SND_SOC_DAPM_SPK("Handset Spk", NULL),
+};
+
+
+/* example machine audio_mapnections */
+static const char* audio_map[][3] = {
+
+ /* Connections to the lm4853 amp */
+ {"Stereo Out", NULL, "LOUT1"},
+ {"Stereo Out", NULL, "ROUT1"},
+
+ /* Connections to the GSM Module */
+ {"GSM Line Out", NULL, "MONO1"},
+ {"GSM Line Out", NULL, "MONO2"},
+ {"RXP", NULL, "GSM Line In"},
+ {"RXN", NULL, "GSM Line In"},
+
+ /* Connections to Headset */
+ {"MIC1", NULL, "Mic Bias"},
+ {"Mic Bias", NULL, "Headset Mic"},
+
+ /* Call Mic */
+ {"MIC2", NULL, "Mic Bias"},
+ {"MIC2N", NULL, "Mic Bias"},
+ {"Mic Bias", NULL, "Handset Mic"},
+
+ /* Call Speaker */
+ {"Handset Spk", NULL, "LOUT2"},
+ {"Handset Spk", NULL, "ROUT2"},
+
+ /* Connect the ALC pins */
+ {"ACIN", NULL, "ACOP"},
+
+ {NULL, NULL, NULL},
+};
+
+static const struct snd_kcontrol_new wm8753_neo1973_gta02_controls[] = {
+ SOC_SINGLE_EXT("DAPM Stereo Out Switch", 0, 0, 1, 0,
+ neo1973_gta02_get_stereo_out,
+ neo1973_gta02_set_stereo_out),
+ SOC_SINGLE_EXT("DAPM GSM Line Out Switch", 1, 0, 1, 0,
+ neo1973_gta02_get_gsm_out,
+ neo1973_gta02_set_gsm_out),
+ SOC_SINGLE_EXT("DAPM GSM Line In Switch", 2, 0, 1, 0,
+ neo1973_gta02_get_gsm_in,
+ neo1973_gta02_set_gsm_in),
+ SOC_SINGLE_EXT("DAPM Headset Mic Switch", 3, 0, 1, 0,
+ neo1973_gta02_get_headset_mic,
+ neo1973_gta02_set_headset_mic),
+ SOC_SINGLE_EXT("DAPM Handset Mic Switch", 4, 0, 1, 0,
+ neo1973_gta02_get_handset_mic,
+ neo1973_gta02_set_handset_mic),
+ SOC_SINGLE_EXT("DAPM Handset Spk Switch", 5, 0, 1, 0,
+ neo1973_gta02_get_handset_spk,
+ neo1973_gta02_set_handset_spk),
+ SOC_SINGLE_EXT("Amp State Switch", 6, 0, 1, 0,
+ lm4853_get_state,
+ lm4853_set_state),
+ SOC_SINGLE_EXT("Amp Spk Switch", 7, 0, 1, 0,
+ lm4853_get_spk,
+ lm4853_set_spk),
+};
+
+/*
+ * This is an example machine initialisation for a wm8753 connected to a
+ * neo1973 GTA02.
+ */
+static int neo1973_gta02_wm8753_init(struct snd_soc_codec *codec)
+{
+ int i, err;
+
+ /* set up NC codec pins */
+ snd_soc_dapm_set_endpoint(codec, "OUT3", 0);
+ snd_soc_dapm_set_endpoint(codec, "OUT4", 0);
+ snd_soc_dapm_set_endpoint(codec, "LINE1", 0);
+ snd_soc_dapm_set_endpoint(codec, "LINE2", 0);
+
+ /* Add neo1973 gta02 specific widgets */
+ for (i = 0; i < ARRAY_SIZE(wm8753_dapm_widgets); i++)
+ snd_soc_dapm_new_control(codec, &wm8753_dapm_widgets[i]);
+
+ /* add neo1973 gta02 specific controls */
+ for (i = 0; i < ARRAY_SIZE(wm8753_neo1973_gta02_controls); i++) {
+ err = snd_ctl_add(codec->card,
+ snd_soc_cnew(&wm8753_neo1973_gta02_controls[i],
+ codec, NULL));
+ if (err < 0)
+ return err;
+ }
+
+ /* set up neo1973 gta02 specific audio path audio_mapnects */
+ for (i = 0; audio_map[i][0] != NULL; i++) {
+ snd_soc_dapm_connect_input(codec, audio_map[i][0],
+ audio_map[i][1], audio_map[i][2]);
+ }
+
+ /* set endpoints to default off mode */
+ snd_soc_dapm_set_endpoint(codec, "Stereo Out", 0);
+ snd_soc_dapm_set_endpoint(codec, "GSM Line Out",0);
+ snd_soc_dapm_set_endpoint(codec, "GSM Line In", 0);
+ snd_soc_dapm_set_endpoint(codec, "Headset Mic", 0);
+ snd_soc_dapm_set_endpoint(codec, "Handset Mic", 0);
+ snd_soc_dapm_set_endpoint(codec, "Handset Spk", 0);
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
+}
+
+/*
+ * BT Codec DAI
+ */
+static struct snd_soc_dai bt_dai =
+{ .name = "Bluetooth",
+ .id = 0,
+ .type = SND_SOC_DAI_PCM,
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = SNDRV_PCM_RATE_8000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 1,
+ .rates = SNDRV_PCM_RATE_8000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,},
+};
+
+static struct snd_soc_dai_link neo1973_gta02_dai[] = {
+{ /* Hifi Playback - for similatious use with voice below */
+ .name = "WM8753",
+ .stream_name = "WM8753 HiFi",
+ .cpu_dai = &s3c24xx_i2s_dai,
+ .codec_dai = &wm8753_dai[WM8753_DAI_HIFI],
+ .init = neo1973_gta02_wm8753_init,
+ .ops = &neo1973_gta02_hifi_ops,
+},
+{ /* Voice via BT */
+ .name = "Bluetooth",
+ .stream_name = "Voice",
+ .cpu_dai = &bt_dai,
+ .codec_dai = &wm8753_dai[WM8753_DAI_VOICE],
+ .ops = &neo1973_gta02_voice_ops,
+},
+};
+
+#ifdef CONFIG_PM
+int neo1973_gta02_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 1);
+
+ return 0;
+}
+
+int neo1973_gta02_resume(struct platform_device *pdev)
+{
+ if(lm4853_state & LM4853_AMP)
+ s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 0);
+
+ return 0;
+}
+#else
+#define neo1973_gta02_suspend NULL
+#define neo1973_gta02_resume NULL
+#endif
+
+static struct snd_soc_machine neo1973_gta02 = {
+ .name = "neo1973-gta02",
+ .suspend_pre = neo1973_gta02_suspend,
+ .resume_post = neo1973_gta02_resume,
+ .dai_link = neo1973_gta02_dai,
+ .num_links = ARRAY_SIZE(neo1973_gta02_dai),
+};
+
+/* Audio private data */
+static struct wm8753_setup_data soc_codec_data_wm8753_gta02 = {
+ .i2c_bus = 0,
+ .i2c_address = 0x1a,
+// .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
+// .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
+};
+
+static struct snd_soc_device neo1973_gta02_snd_devdata = {
+ .machine = &neo1973_gta02,
+ .platform = &s3c24xx_soc_platform,
+ .codec_dev = &soc_codec_dev_wm8753,
+ .codec_data = &soc_codec_data_wm8753_gta02,
+};
+
+
+
+static struct platform_device *neo1973_gta02_snd_device;
+
+static int __init neo1973_gta02_init(void)
+{
+ int ret;
+
+ if (!machine_is_neo1973_gta02()) {
+ printk(KERN_INFO
+ "Only GTA02 hardware supported by ASoc driver\n");
+ return -ENODEV;
+ }
+
+ neo1973_gta02_snd_device = platform_device_alloc("soc-audio", -1);
+ if (!neo1973_gta02_snd_device)
+ return -ENOMEM;
+
+ platform_set_drvdata(neo1973_gta02_snd_device,
+ &neo1973_gta02_snd_devdata);
+ neo1973_gta02_snd_devdata.dev = &neo1973_gta02_snd_device->dev;
+ ret = platform_device_add(neo1973_gta02_snd_device);
+
+ if (ret)
+ platform_device_put(neo1973_gta02_snd_device);
+
+ /* Initialise GPIOs used by amp */
+ s3c2410_gpio_cfgpin(GTA02_GPIO_HP_IN, S3C2410_GPIO_OUTPUT);
+ s3c2410_gpio_cfgpin(GTA02_GPIO_AMP_SHUT, S3C2410_GPIO_OUTPUT);
+
+ /* Amp off by default */
+ s3c2410_gpio_setpin(GTA02_GPIO_AMP_SHUT, 1);
+
+ /* Speaker off by default */
+ s3c2410_gpio_setpin(GTA02_GPIO_HP_IN, 1);
+
+ return ret;
+}
+
+static void __exit neo1973_gta02_exit(void)
+{
+ platform_device_unregister(neo1973_gta02_snd_device);
+}
+
+module_init(neo1973_gta02_init);
+module_exit(neo1973_gta02_exit);
+
+/* Module information */
+MODULE_AUTHOR("Graeme Gregory, graeme@openmoko.org");
+MODULE_DESCRIPTION("ALSA SoC WM8753 Neo1973 GTA02");
+MODULE_LICENSE("GPL");
+
--- a/sound/soc/s3c24xx/neo1973_wm8753.c
+++ b/sound/soc/s3c24xx/neo1973_wm8753.c
@@ -32,7 +32,7 @@
#include <mach/audio.h>
#include <linux/io.h>
#include <mach/spi-gpio.h>
-
+#include <asm/mach-types.h>
#include <asm/plat-s3c24xx/regs-iis.h>
#include "../codecs/wm8753.h"
@@ -585,7 +585,7 @@
.num_links = ARRAY_SIZE(neo1973_dai),
};
-static struct wm8753_setup_data neo1973_wm8753_setup = {
+static struct wm8753_setup_data soc_codec_data_wm8753_gta01 = {
.i2c_bus = 0,
.i2c_address = 0x1a,
};
@@ -594,7 +594,7 @@
.machine = &neo1973,
.platform = &s3c24xx_soc_platform,
.codec_dev = &soc_codec_dev_wm8753,
- .codec_data = &neo1973_wm8753_setup,
+ .codec_data = &soc_codec_data_wm8753_gta01
};
static int lm4857_i2c_probe(struct i2c_client *client,
@@ -676,7 +676,7 @@
{
int ret;
- DBG("Entered %s\n", __func__);
+ printk(KERN_DEBUG "Entered %s\n", __func__);
if (!machine_is_neo1973_gta01()) {
printk(KERN_INFO
--- a/sound/soc/s3c24xx/s3c2443-ac97.c
+++ b/sound/soc/s3c24xx/s3c2443-ac97.c
@@ -28,7 +28,7 @@
#include <sound/soc.h>
#include <mach/hardware.h>
-#include <asm/plat-s3c/regs-ac97.h>
+#include <plat/regs-ac97.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/audio.h>
--- a/sound/soc/s3c24xx/s3c24xx-i2s.c
+++ b/sound/soc/s3c24xx/s3c24xx-i2s.c
@@ -175,7 +175,7 @@
static int s3c24xx_snd_lrsync(void)
{
u32 iiscon;
- int timeout = 50; /* 5ms */
+ int timeout = 5; /* 500us, 125 should be enough at 8kHz */
DBG("Entered %s\n", __func__);
@@ -282,11 +282,14 @@
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
- if (!s3c24xx_snd_is_clkmaster()) {
- ret = s3c24xx_snd_lrsync();
- if (ret)
- goto exit_err;
- }
+ if (!s3c24xx_snd_is_clkmaster())
+ /* we ignore the return code, if it sync'd then fine,
+ * if it didn't sync, which happens after resume the
+ * first time when there was a live stream at suspend,
+ * just let it timeout, the stream picks up OK after
+ * that and LRCK is evidently working again.
+ */
+ s3c24xx_snd_lrsync();
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
s3c24xx_snd_rxctrl(1);
@@ -306,7 +309,6 @@
break;
}
-exit_err:
return ret;
}
--- a/sound/soc/s3c24xx/s3c24xx-pcm.c
+++ b/sound/soc/s3c24xx/s3c24xx-pcm.c
@@ -168,7 +168,7 @@
prtd->params->client, NULL);
if (ret < 0) {
- DBG(KERN_ERR "failed to get dma channel\n");
+ DBG(KERN_ERR "failed to get dma channel: %d\n", ret);
return ret;
}
}
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -1003,6 +1003,38 @@
}
static DEVICE_ATTR(codec_reg, 0444, codec_reg_show, NULL);
+
+static ssize_t codec_reg_write(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 address;
+ u32 data;
+ char * end;
+ size_t left = count;
+ struct snd_soc_device *devdata = dev_get_drvdata(dev);
+ struct snd_soc_codec *codec = devdata->codec;
+
+ address = simple_strtoul(buf, &end, 16);
+ left -= (int)(end - buf);
+ while ((*end == ' ') && (left)) {
+ end++;
+ left--;
+ }
+ if (!left)
+ return count;
+ data = simple_strtoul(end, &end, 16);
+
+ printk(KERN_INFO"user writes Codec reg 0x%02X with Data 0x%04X\n",
+ address, data);
+
+ codec->write(codec, address, data);
+
+ return count;
+}
+
+static DEVICE_ATTR(codec_reg_write, 0644, NULL, codec_reg_write);
+
/**
* snd_soc_new_ac97_codec - initailise AC97 device
* @codec: audio codec
@@ -1218,6 +1250,9 @@
mutex_unlock(&codec->mutex);
+ err = device_create_file(socdev->dev, &dev_attr_codec_reg_write);
+ if (err < 0)
+ printk(KERN_WARNING "asoc: failed to add codec sysfs entries\n");
out:
return ret;
}
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -1525,6 +1525,56 @@
EXPORT_SYMBOL_GPL(snd_soc_dapm_get_pin_status);
/**
+ * snd_soc_dapm_get_endpoint - get audio endpoint status
+ * @codec: audio codec
+ * @endpoint: audio signal endpoint (or start point)
+ *
+ * Get audio endpoint status - connected or disconnected.
+ *
+ * Returns status
+ */
+int snd_soc_dapm_get_endpoint(struct snd_soc_codec *codec,
+ char *endpoint)
+{
+ struct snd_soc_dapm_widget *w;
+
+ list_for_each_entry(w, &codec->dapm_widgets, list) {
+ if (!strcmp(w->name, endpoint)) {
+ return w->connected;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(snd_soc_dapm_get_endpoint);
+
+/**
+ * snd_soc_dapm_set_endpoint - set audio endpoint status
+ * @codec: audio codec
+ * @endpoint: audio signal endpoint (or start point)
+ * @status: point status
+ *
+ * Set audio endpoint status - connected or disconnected.
+ *
+ * Returns 0 for success else error.
+ */
+int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec,
+ char *endpoint, int status)
+{
+ struct snd_soc_dapm_widget *w;
+
+ list_for_each_entry(w, &codec->dapm_widgets, list) {
+ if (!strcmp(w->name, endpoint)) {
+ w->connected = status;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(snd_soc_dapm_set_endpoint);
+
+/**
* snd_soc_dapm_free - free dapm resources
* @socdev: SoC device
*
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