mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 15:25:20 +02:00
f61f0b7178
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26127 3c298f89-4303-0410-b956-a3cf2f4a3e73
105 lines
3.4 KiB
Diff
105 lines
3.4 KiB
Diff
--- a/drivers/ssb/scan.c
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+++ b/drivers/ssb/scan.c
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@@ -90,6 +90,14 @@ const char *ssb_core_name(u16 coreid)
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return "ARM 1176";
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case SSB_DEV_ARM_7TDMI:
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return "ARM 7TDMI";
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+ case SSB_DEV_ETHERNET_GBIT2:
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+ return "Gigabit MAC";
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+ case SSB_DEV_MIPS_74K:
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+ return "MIPS 74k";
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+ case SSB_DEV_DDR_CTRLR:
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+ return "DDR1/2 memory controller";
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+ case SSB_DEV_I2S:
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+ return "I2S";
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}
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return "UNKNOWN";
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}
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@@ -148,6 +156,7 @@ static u8 chipid_to_nrcores(u16 chipid)
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case 0x4710:
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case 0x4610:
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case 0x4704:
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+ case 0x4716:
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return 9;
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default:
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ssb_printk(KERN_ERR PFX
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--- a/include/linux/ssb/ssb.h
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+++ b/include/linux/ssb/ssb.h
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@@ -155,9 +155,16 @@ struct ssb_bus_ops {
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#define SSB_DEV_MINI_MACPHY 0x823
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#define SSB_DEV_ARM_1176 0x824
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#define SSB_DEV_ARM_7TDMI 0x825
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+#define SSB_DEV_ETHERNET_GBIT2 0x82d
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+#define SSB_DEV_MIPS_74K 0x82c
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+#define SSB_DEV_DDR_CTRLR 0x82e
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+#define SSB_DEV_I2S 0x834
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+#define SSB_DEV_DEFAULT 0xfff
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/* Vendor-ID values */
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#define SSB_VENDOR_BROADCOM 0x4243
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+#define SSB_VENDOR_BROADCOM2 0x04BF
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+#define SSB_VENDOR_ARM 0x43b
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/* Some kernel subsystems poke with dev->drvdata, so we must use the
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* following ugly workaround to get from struct device to struct ssb_device */
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -11,6 +11,7 @@
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#define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
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#define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
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#define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
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+#define SSB_AI_BASE 0x18100000 /* base for AI registers */
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#define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
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#define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
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@@ -26,6 +27,7 @@
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#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
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#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
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+#define SSB_EROM_ASD_SZ_BASE 0x00001000
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/* Enumeration space constants */
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#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
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@@ -499,5 +501,41 @@ enum {
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#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
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#define SSB_ADM_BASE2_SHIFT 16
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+/***** EROM defines for AI type busses *****/
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+#define SSB_EROM_VALID 1
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+#define SSB_EROM_END 0xe
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+#define SSB_EROM_TAG 0xe
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+/* Adress Space Descriptor */
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+#define SSB_EROM_ASD 0x4
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+#define SSB_EROM_ASD_SP_MASK 0x00000f00
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+#define SSB_EROM_ASD_SP_SHIFT 8
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+#define SSB_EROM_ASD_ST_MASK 0x000000c0
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+#define SSB_EROM_ASD_ST_SLAVE 0x00000000
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+#define SSB_EROM_ASD_ST_BRIDGE 0x00000040
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+#define SSB_EROM_ASD_ST_MWRAP 0x000000c0
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+#define SSB_EROM_ASD_ST_SWRAP 0x00000080
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+#define SSB_EROM_ASD_ADDR_MASK 0xfffff000
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+#define SSB_EROM_ASD_AG32 0x00000008
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+#define SSB_EROM_ASD_SZ_MASK 0x00000030
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+#define SSB_EROM_ASD_SZ_SZD 0x00000030
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+#define SSB_EROM_ASD_SZ_SHIFT 4
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+#define SSB_EROM_CI 0
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+#define SSB_EROM_CIA_CID_MASK 0x000fff00
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+#define SSB_EROM_CIA_CID_SHIFT 8
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+#define SSB_EROM_CIA_MFG_MASK 0xfff00000
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+#define SSB_EROM_CIA_MFG_SHIFT 20
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+#define SSB_EROM_CIB_REV_MASK 0xff000000
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+#define SSB_EROM_CIB_REV_SHIFT 24
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+#define SSB_EROM_CIB_NMW_MASK 0x0007c000
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+#define SSB_EROM_CIB_NSW_MASK 0x00f80000
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+#define SSB_EROM_CIB_NSP_MASK 0x00003e00
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+
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+/***** Registers of AI config space *****/
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+#define SSB_AI_RESETCTRL 0x800 /* maybe 0x804 for big endian */
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+#define SSB_AI_RESETCTRL_RESET 1
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+#define SSB_AI_IOCTRL 0x408 /* maybe 0x40c for big endian */
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+#define SSB_CF_FGC 0x0002
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+#define SSB_CF_CLOCK_EN 0x001
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+#define SSB_AI_oobselouta30 0x100
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#endif /* LINUX_SSB_REGS_H_ */
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