mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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a7c087dc66
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9815 3c298f89-4303-0410-b956-a3cf2f4a3e73
259 lines
8.7 KiB
C
259 lines
8.7 KiB
C
/*
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* ifx_ssc.h defines some data sructures used in ifx_ssc.c
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*
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* Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
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*
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*
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*/
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#ifndef __IFX_SSC_H
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#define __IFX_SSC_H
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#ifdef __KERNEL__
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#include <asm/danube/ifx_ssc_defines.h>
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#endif //__KERNEL__
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#define PORT_CNT 1 // assume default value
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/* symbolic constants to be used in SSC routines */
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// ### TO DO: bad performance
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#define IFX_SSC_TXFIFO_ITL 1
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#define IFX_SSC_RXFIFO_ITL 1
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struct ifx_ssc_statistics {
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unsigned int abortErr; /* abort error */
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unsigned int modeErr; /* master/slave mode error */
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unsigned int txOvErr; /* TX Overflow error */
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unsigned int txUnErr; /* TX Underrun error */
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unsigned int rxOvErr; /* RX Overflow error */
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unsigned int rxUnErr; /* RX Underrun error */
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unsigned int rxBytes;
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unsigned int txBytes;
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};
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struct ifx_ssc_hwopts {
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unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
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unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
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unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
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unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
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unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
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unsigned int echoMode:1; /* Echo mode */
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unsigned int loopBack:1; /* Loopback mode */
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unsigned int idleValue:1; /* Idle value */
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unsigned int clockPolarity:1; /* Idle clock is high or low */
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unsigned int clockPhase:1; /* Tx on trailing or leading edge */
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unsigned int headingControl:1; /* LSB first or MSB first */
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unsigned int dataWidth:6; /* from 2 up to 32 bits */
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unsigned int masterSelect:1; /* Master or Slave mode */
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unsigned int modeRxTx:2; /* rx/tx mode */
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unsigned int gpoCs:8; /* choose outputs to use for chip select */
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unsigned int gpoInv:8; /* invert GPO outputs */
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};
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struct ifx_ssc_frm_opts {
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bool FrameEnable; // SFCON.SFEN
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unsigned int DataLength; // SFCON.DLEN
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unsigned int PauseLength; // SFCON.PLEN
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unsigned int IdleData; // SFCON.IDAT
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unsigned int IdleClock; // SFCON.ICLK
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bool StopAfterPause; // SFCON.STOP
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};
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struct ifx_ssc_frm_status {
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bool DataBusy; // SFSTAT.DBSY
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bool PauseBusy; // SFSTAT.PBSY
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unsigned int DataCount; // SFSTAT.DCNT
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unsigned int PauseCount; // SFSTAT.PCNT
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bool EnIntAfterData; // SFCON.IBEN
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bool EnIntAfterPause; // SFCON.IAEN
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};
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typedef struct {
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char *buf;
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size_t len;
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} ifx_ssc_buf_item_t;
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// data structures for batch execution
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typedef union {
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struct {
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bool save_options;
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} init;
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ifx_ssc_buf_item_t read;
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ifx_ssc_buf_item_t write;
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ifx_ssc_buf_item_t rd_wr;
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unsigned int set_baudrate;
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struct ifx_ssc_frm_opts set_frm;
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unsigned int set_gpo;
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struct ifx_ssc_hwopts set_hwopts;
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} ifx_ssc_batch_cmd_param;
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struct ifx_ssc_batch_list {
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unsigned int cmd;
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ifx_ssc_batch_cmd_param cmd_param;
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struct ifx_ssc_batch_list *next;
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};
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#ifdef __KERNEL__
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#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
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struct ifx_ssc_port {
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unsigned long mapbase;
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struct ifx_ssc_hwopts opts;
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struct ifx_ssc_statistics stats;
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struct ifx_ssc_frm_status frm_status;
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struct ifx_ssc_frm_opts frm_opts;
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/* wait queue for ifx_ssc_read() */
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wait_queue_head_t rwait, pwait;
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int port_nr;
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char port_is_open; /* exclusive open - boolean */
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// int no_of_bits; /* number of _valid_ bits */
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// int elem_size; /* shift for element (no of bytes)*/
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/* buffer and pointers to the read/write position */
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char *rxbuf; /* buffer for RX */
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char *rxbuf_end; /* buffer end pointer for RX */
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volatile char *rxbuf_ptr; /* buffer write pointer for RX */
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char *txbuf; /* buffer for TX */
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char *txbuf_end; /* buffer end pointer for TX */
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volatile char *txbuf_ptr; /* buffer read pointer for TX */
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unsigned int baud;
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/* each channel has its own interrupts */
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/* (transmit/receive/error/frame) */
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unsigned int txirq, rxirq, errirq, frmirq;
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};
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/* default values for SSC configuration */
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// values of CON
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#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
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#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
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#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
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#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
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#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
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#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
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#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
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#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
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#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
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#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
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#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
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// other values
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#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
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#ifdef CONFIG_USE_EMULATOR
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#define IFX_SSC_DEF_BAUDRATE 10000
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#else
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#define IFX_SSC_DEF_BAUDRATE 2000000
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#endif
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#define IFX_SSC_DEF_RMC 0x10
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#define IFX_SSC_DEF_TXFIFO_FL 8
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#define IFX_SSC_DEF_RXFIFO_FL 1
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#if 1 //TODO
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#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
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#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
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#else
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#error "what is ur Chip Select???"
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#endif
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#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
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#if 0
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#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
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IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
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#endif
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#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
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IFX_SSC_R_BIT | IFX_SSC_E_BIT
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#endif /* __KERNEL__ */
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// batch execution commands
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#define IFX_SSC_BATCH_CMD_INIT 1
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#define IFX_SSC_BATCH_CMD_READ 2
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#define IFX_SSC_BATCH_CMD_WRITE 3
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#define IFX_SSC_BATCH_CMD_RD_WR 4
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#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
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#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
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#define IFX_SSC_BATCH_CMD_SET_FRM 7
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#define IFX_SSC_BATCH_CMD_SET_GPO 8
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#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
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//#define IFX_SSC_BATCH_CMD_
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//#define IFX_SSC_BATCH_CMD_
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#define IFX_SSC_BATCH_CMD_END_EXEC 0
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/* Macros to configure SSC hardware */
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/* headingControl: */
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#define IFX_SSC_LSB_FIRST 0
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#define IFX_SSC_MSB_FIRST 1
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/* dataWidth: */
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#define IFX_SSC_MIN_DATA_WIDTH 2
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#define IFX_SSC_MAX_DATA_WIDTH 32
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/* master/slave mode select */
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#define IFX_SSC_MASTER_MODE 1
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#define IFX_SSC_SLAVE_MODE 0
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/* rx/tx mode */
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// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
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#define IFX_SSC_MODE_RXTX 0
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#define IFX_SSC_MODE_RX 1
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#define IFX_SSC_MODE_TX 2
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#define IFX_SSC_MODE_OFF 3
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#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
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/* GPO values */
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#define IFX_SSC_MAX_GPO_OUT 7
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#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
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/***********************/
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/* defines for ioctl's */
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/***********************/
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#define IFX_SSC_IOCTL_MAGIC 'S'
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/* read out the statistics */
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#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
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/* clear the statistics */
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#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
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/* set the baudrate */
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#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
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/* get the current baudrate */
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#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
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/* set hardware options */
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#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
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/* get the current hardware options */
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#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
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/* set transmission mode */
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#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
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/* get the current transmission mode */
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#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
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/* abort transmission */
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#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
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#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
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/* set general purpose outputs */
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#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
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/* clear general purpose outputs */
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#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
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/* get general purpose outputs */
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#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
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/*** serial framing ***/
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/* get status of serial framing */
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#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
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/* get counter reload values and control bits */
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#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
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/* set counter reload values and control bits */
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#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
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/*** batch execution ***/
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/* do batch execution */
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#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
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#ifdef __KERNEL__
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// routines from ifx_ssc.c
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// ### TO DO
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/* kernel interface for read and write */
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ssize_t ifx_ssc_kread (int, char *, size_t);
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ssize_t ifx_ssc_kwrite (int, const char *, size_t);
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#ifdef CONFIG_IFX_VP_KERNEL_TEST
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void ifx_ssc_tc (void);
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#endif // CONFIG_IFX_VP_KERNEL_TEST
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#endif //__KERNEL__
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#endif // __IFX_SSC_H
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