mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-05 03:50:36 +02:00
796a9d1091
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15242 3c298f89-4303-0410-b956-a3cf2f4a3e73
415 lines
10 KiB
C
415 lines
10 KiB
C
/*
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* Low-Level PCI and SB support for BCM47xx (Linux support code)
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/paccess.h>
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#include <typedefs.h>
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#include <osl.h>
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#include <sbconfig.h>
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#include <sbutils.h>
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#include <hndpci.h>
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#include <pcicfg.h>
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#include <bcmdevs.h>
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#include <bcmnvram.h>
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/* Global SB handle */
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extern sb_t *bcm947xx_sbh;
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extern spinlock_t bcm947xx_sbh_lock;
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/* Convenience */
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#define sbh bcm947xx_sbh
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#define sbh_lock bcm947xx_sbh_lock
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static int
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sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&sbh_lock, flags);
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ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), where, value, sizeof(*value));
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spin_unlock_irqrestore(&sbh_lock, flags);
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return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int
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sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&sbh_lock, flags);
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ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), where, value, sizeof(*value));
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spin_unlock_irqrestore(&sbh_lock, flags);
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return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int
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sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&sbh_lock, flags);
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ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), where, value, sizeof(*value));
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spin_unlock_irqrestore(&sbh_lock, flags);
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return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int
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sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&sbh_lock, flags);
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ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), where, &value, sizeof(value));
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spin_unlock_irqrestore(&sbh_lock, flags);
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return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int
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sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&sbh_lock, flags);
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ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), where, &value, sizeof(value));
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spin_unlock_irqrestore(&sbh_lock, flags);
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return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static int
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sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&sbh_lock, flags);
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ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), where, &value, sizeof(value));
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spin_unlock_irqrestore(&sbh_lock, flags);
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return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pcibios_ops = {
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sbpci_read_config_byte,
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sbpci_read_config_word,
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sbpci_read_config_dword,
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sbpci_write_config_byte,
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sbpci_write_config_word,
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sbpci_write_config_dword
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};
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void __init
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pcibios_init(void)
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{
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ulong flags;
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if (!(sbh = sb_kattach(SB_OSH)))
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panic("sb_kattach failed");
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spin_lock_init(&sbh_lock);
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spin_lock_irqsave(&sbh_lock, flags);
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sbpci_init(sbh);
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spin_unlock_irqrestore(&sbh_lock, flags);
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set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
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mdelay(300); /* workaround for atheros cards */
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/* Scan the SB bus */
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pci_scan_bus(0, &pcibios_ops, NULL);
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}
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char * __init
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pcibios_setup(char *str)
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{
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if (!strncmp(str, "ban=", 4)) {
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sbpci_ban(simple_strtoul(str + 4, NULL, 0));
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return NULL;
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}
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return (str);
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}
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static u32 pci_iobase = 0x100;
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static u32 pci_membase = SB_PCI_DMA;
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static u32 pcmcia_membase = 0x40004000;
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void __init
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pcibios_fixup_bus(struct pci_bus *b)
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{
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struct list_head *ln;
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struct pci_dev *d;
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struct resource *res;
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int pos, size;
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u32 *base;
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u8 irq;
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printk("PCI: Fixing up bus %d\n", b->number);
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/* Fix up SB */
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if (b->number == 0) {
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for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
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d = pci_dev_b(ln);
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/* Fix up interrupt lines */
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pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
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d->irq = irq + 2;
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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}
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}
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/* Fix up external PCI */
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else {
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for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
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d = pci_dev_b(ln);
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/* Fix up resource bases */
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for (pos = 0; pos < 6; pos++) {
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res = &d->resource[pos];
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base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
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if (res->end) {
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size = res->end - res->start + 1;
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if (*base & (size - 1))
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*base = (*base + size) & ~(size - 1);
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res->start = *base;
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res->end = res->start + size - 1;
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*base += size;
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pci_write_config_dword(d,
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PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
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}
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/* Fix up PCI bridge BAR0 only */
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if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
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break;
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}
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/* Fix up interrupt lines */
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if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
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d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
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pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
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}
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}
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}
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unsigned int
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pcibios_assign_all_busses(void)
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{
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return 1;
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}
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void
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pcibios_align_resource(void *data, struct resource *res,
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unsigned long size, unsigned long align)
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{
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}
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int
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pcibios_enable_resources(struct pci_dev *dev)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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/* External PCI only */
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if (dev->bus->number == 0)
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return 0;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx = 0; idx < 6; idx++) {
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r = &dev->resource[idx];
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (dev->resource[PCI_ROM_RESOURCE].start)
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cmd |= PCI_COMMAND_MEMORY;
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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int
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pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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ulong flags;
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uint coreidx;
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void *regs;
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/* External PCI device enable */
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if (dev->bus->number != 0)
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return pcibios_enable_resources(dev);
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/* These cores come out of reset enabled */
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if (dev->device == SB_MIPS ||
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dev->device == SB_MIPS33 ||
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dev->device == SB_EXTIF ||
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dev->device == SB_CC)
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return 0;
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spin_lock_irqsave(&sbh_lock, flags);
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coreidx = sb_coreidx(sbh);
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regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
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if (!regs)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* The USB core requires a special bit to be set during core
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* reset to enable host (OHCI) mode. Resetting the SB core in
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* pcibios_enable_device() is a hack for compatibility with
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* vanilla usb-ohci so that it does not have to know about
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* SB. A driver that wants to use the USB core in device mode
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* should know about SB and should reset the bit back to 0
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* after calling pcibios_enable_device().
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*/
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if (sb_coreid(sbh) == SB_USB) {
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printk(KERN_INFO "SB USB 1.1 init\n");
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sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
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sb_core_reset(sbh, 1 << 29, 0);
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}
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/*
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* USB 2.0 special considerations:
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*
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* 1. Since the core supports both OHCI and EHCI functions, it must
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* only be reset once.
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*
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* 2. In addition to the standard SB reset sequence, the Host Control
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* Register must be programmed to bring the USB core and various
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* phy components out of reset.
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*/
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else if (sb_coreid(sbh) == SB_USB20H) {
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uint corerev = sb_corerev(sbh);
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printk(KERN_INFO "SB USB20H init\n");
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printk(KERN_INFO "SB COREREV: %d\n", corerev);
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if (!sb_iscoreup(sbh)) {
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printk(KERN_INFO "SB USB20H resetting\n");
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sb_core_reset(sbh, 0, 0);
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writel(0x7FF, (ulong)regs + 0x200);
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udelay(1);
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}
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/* PRxxxx: War for 5354 failures. */
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if (corerev == 1 || corerev == 2) {
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uint32 tmp;
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/* Change Flush control reg */
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tmp = readl((uintptr)regs + 0x400);
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tmp &= ~8;
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writel(tmp, (uintptr)regs + 0x400);
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tmp = readl((uintptr)regs + 0x400);
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printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
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/* Change Shim control reg */
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tmp = readl((uintptr)regs + 0x304);
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tmp &= ~0x100;
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writel(tmp, (uintptr)regs + 0x304);
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tmp = readl((uintptr)regs + 0x304);
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printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
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}
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} else
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sb_core_reset(sbh, 0, 0);
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sb_setcoreidx(sbh, coreidx);
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spin_unlock_irqrestore(&sbh_lock, flags);
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return 0;
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}
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void
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pcibios_update_resource(struct pci_dev *dev, struct resource *root,
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struct resource *res, int resource)
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{
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unsigned long where, size;
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u32 reg;
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/* External PCI only */
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if (dev->bus->number == 0)
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return;
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where = PCI_BASE_ADDRESS_0 + (resource * 4);
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size = res->end - res->start;
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pci_read_config_dword(dev, where, ®);
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if (dev->bus->number == 1)
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reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
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else
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reg = res->start;
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pci_write_config_dword(dev, where, reg);
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}
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static void __init
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quirk_sbpci_bridge(struct pci_dev *dev)
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{
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if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
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return;
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printk("PCI: Fixing up bridge\n");
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/* Enable PCI bridge bus mastering and memory space */
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pci_set_master(dev);
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pcibios_enable_resources(dev);
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/* Enable PCI bridge BAR1 prefetch and burst */
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pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
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}
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struct pci_fixup pcibios_fixups[] = {
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{ PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
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{ 0 }
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};
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain crappy BIOSes forget to set it properly.
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*/
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unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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