mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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769a390d81
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31130 3c298f89-4303-0410-b956-a3cf2f4a3e73
84 lines
3.4 KiB
Diff
84 lines
3.4 KiB
Diff
From 32511e7dfab9b9cabe2772e3f5430559294a8d1c Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 25 Jan 2012 17:40:01 +0100
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Subject: [PATCH 09/63] MIPS: BCM63XX: remove SPI2 register
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This register was introduced with the support of the BCM6368 CPU in the idea
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that its internal layout was different from the other CPUs SPI controller.
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The controller is actually the same as the one present on BCM6358 so we can
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remove this register and use the usual SPI register instead.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +---------
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1 files changed, 1 insertions(+), 9 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -102,7 +102,6 @@ enum bcm63xx_regs_set {
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RSET_UART1,
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RSET_GPIO,
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RSET_SPI,
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- RSET_SPI2,
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RSET_UDC0,
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RSET_OHCI0,
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RSET_OHCI_PRIV,
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@@ -166,7 +165,6 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UART1_BASE (0xdeadbeef)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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#define BCM_6338_SPI_BASE (0xfffe0c00)
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-#define BCM_6338_SPI2_BASE (0xdeadbeef)
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#define BCM_6338_UDC0_BASE (0xdeadbeef)
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#define BCM_6338_USBDMA_BASE (0xfffe2400)
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#define BCM_6338_OHCI0_BASE (0xdeadbeef)
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@@ -210,7 +208,6 @@ enum bcm63xx_regs_set {
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#define BCM_6345_UART1_BASE (0xdeadbeef)
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#define BCM_6345_GPIO_BASE (0xfffe0400)
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#define BCM_6345_SPI_BASE (0xdeadbeef)
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-#define BCM_6345_SPI2_BASE (0xdeadbeef)
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#define BCM_6345_UDC0_BASE (0xdeadbeef)
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#define BCM_6345_USBDMA_BASE (0xfffe2800)
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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@@ -253,7 +250,6 @@ enum bcm63xx_regs_set {
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#define BCM_6348_UART1_BASE (0xdeadbeef)
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#define BCM_6348_GPIO_BASE (0xfffe0400)
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#define BCM_6348_SPI_BASE (0xfffe0c00)
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-#define BCM_6348_SPI2_BASE (0xdeadbeef)
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#define BCM_6348_UDC0_BASE (0xfffe1000)
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#define BCM_6348_OHCI0_BASE (0xfffe1b00)
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#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
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@@ -294,7 +290,6 @@ enum bcm63xx_regs_set {
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#define BCM_6358_UART1_BASE (0xfffe0120)
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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#define BCM_6358_SPI_BASE (0xfffe0800)
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-#define BCM_6358_SPI2_BASE (0xfffe0800)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
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@@ -335,8 +330,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_UART0_BASE (0xb0000100)
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#define BCM_6368_UART1_BASE (0xb0000120)
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#define BCM_6368_GPIO_BASE (0xb0000080)
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-#define BCM_6368_SPI_BASE (0xdeadbeef)
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-#define BCM_6368_SPI2_BASE (0xb0000800)
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+#define BCM_6368_SPI_BASE (0xb0000800)
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#define BCM_6368_UDC0_BASE (0xdeadbeef)
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#define BCM_6368_OHCI0_BASE (0xb0001600)
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#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
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@@ -383,7 +377,6 @@ extern const unsigned long *bcm63xx_regs
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__GEN_RSET_BASE(__cpu, UART1) \
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__GEN_RSET_BASE(__cpu, GPIO) \
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__GEN_RSET_BASE(__cpu, SPI) \
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- __GEN_RSET_BASE(__cpu, SPI2) \
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__GEN_RSET_BASE(__cpu, UDC0) \
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__GEN_RSET_BASE(__cpu, OHCI0) \
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__GEN_RSET_BASE(__cpu, OHCI_PRIV) \
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@@ -422,7 +415,6 @@ extern const unsigned long *bcm63xx_regs
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[RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
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[RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
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[RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
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- [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
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[RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
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[RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
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[RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
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