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4666e9b56d
BCM6338 and BCM6338 have their MSG_CONTROL register width of 8-bits instead of 16-bits. We were previously using a 16-bits write which corrupted the first byte of the TX FIFO. Also the message type was always set to Full-duplex even in the case of half-duplex messages. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32409 3c298f89-4303-0410-b956-a3cf2f4a3e73
108 lines
3.7 KiB
Diff
108 lines
3.7 KiB
Diff
From 48d3ed67982d2d1cecb5b33bf396d21f6fd7b088 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Tue, 14 Jun 2011 21:14:39 +0200
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Subject: [PATCH 39/79] MIPS: BCM63XX: add MISC register set definition
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 10 +++++++++-
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 ++
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 10 ++++++++++
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3 files changed, 21 insertions(+), 1 deletion(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -129,7 +129,8 @@ enum bcm63xx_regs_set {
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RSET_PCMDMA,
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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- RSET_TRNG
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+ RSET_TRNG,
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+ RSET_MISC
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@@ -198,6 +199,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6338_TRNG_BASE (0xdeadbeef)
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+#define BCM_6338_MISC_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@@ -242,6 +244,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6345_TRNG_BASE (0xdeadbeef)
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+#define BCM_6345_MISC_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@@ -283,6 +286,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6348_TRNG_BASE (0xdeadbeef)
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+#define BCM_6348_MISC_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@@ -324,6 +328,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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#define BCM_6358_TRNG_BASE (0xdeadbeef)
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+#define BCM_6358_MISC_BASE (0xdeadbeef)
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/*
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@@ -366,6 +371,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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#define BCM_6368_TRNG_BASE (0xb0004180)
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+#define BCM_6368_MISC_BASE (0xdeadbeef)
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extern const unsigned long *bcm63xx_regs_base;
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@@ -412,6 +418,7 @@ extern const unsigned long *bcm63xx_regs
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__GEN_RSET_BASE(__cpu, PCMDMAC) \
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__GEN_RSET_BASE(__cpu, PCMDMAS) \
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__GEN_RSET_BASE(__cpu, TRNG) \
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+ __GEN_RSET_BASE(__cpu, MISC) \
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}
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#define __GEN_CPU_REGS_TABLE(__cpu) \
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@@ -451,6 +458,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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[RSET_TRNG] = BCM_## __cpu ##_TRNG_BASE, \
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+ [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -91,5 +91,7 @@
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#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
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#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
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#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
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+#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
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+#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
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#endif /* ! BCM63XX_IO_H_ */
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1123,4 +1123,14 @@
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#define TRNG_THRES 0x0c
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#define TRNG_MASK 0x10
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+/*************************************************************************
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+ * _REG relative to RSET_MISC
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+ *************************************************************************/
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+
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+#define MISC_STRAPBUS_6328_REG 0x240
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+#define STRAPBUS_6328_FCVO_SHIFT 7
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+#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
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+#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
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+#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
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+
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#endif /* BCM63XX_REGS_H_ */
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