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38 lines
1.1 KiB
Plaintext
38 lines
1.1 KiB
Plaintext
--- linux-mips-cvs/arch/mips/mm/c-r4k.c 2004-11-03 17:43:07.000000000 +0100
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+++ linux-cache/arch/mips/mm/c-r4k.c 2005-03-06 23:39:53.000000000 +0100
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@@ -1031,9 +1031,34 @@
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c->options |= MIPS_CPU_SUBSET_CACHES;
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}
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+#if defined(CONFIG_BCM4310)
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+static void __init _change_cachability(u32 cm)
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+{
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+ struct cpuinfo_mips *c = ¤t_cpu_data;
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+
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+ change_c0_config(CONF_CM_CMASK, cm);
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+ if ((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) ==
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+ (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) {
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+ cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+}
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+
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+static void (*change_cachability)(u32);
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+#endif
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+
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static inline void coherency_setup(void)
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{
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+#if defined(CONFIG_BCM4310)
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+ change_cachability = (void (*)(u32)) KSEG1ADDR((unsigned long)(_change_cachability));
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+ change_cachability(CONF_CM_DEFAULT);
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+#else
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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+#endif
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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