mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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fd8ccf9c65
* backport 2.6.8 patches to .39 / .32.33 * remove lqtapi * bump tapi/dsl to .39 * migrate to new ltq_ style api * add amazon_se support git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27026 3c298f89-4303-0410-b956-a3cf2f4a3e73
77 lines
1.9 KiB
Diff
77 lines
1.9 KiB
Diff
--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -179,6 +179,16 @@
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#
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#
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+# Lantiq
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+#
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+
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+core-$(CONFIG_LANTIQ) += arch/mips/lantiq/
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+cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
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+load-$(CONFIG_LANTIQ) = 0xffffffff80002000
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+cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
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+cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
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+
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+#
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# Texas Instruments AR7
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#
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core-$(CONFIG_AR7) += arch/mips/ar7/
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--- a/include/linux/compiler.h
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+++ b/include/linux/compiler.h
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@@ -144,6 +144,11 @@
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# define barrier() __memory_barrier()
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#endif
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+/* Unreachable code */
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+#ifndef unreachable
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+# define unreachable() do { } while (1)
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+#endif
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+
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#ifndef RELOC_HIDE
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# define RELOC_HIDE(ptr, off) \
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({ unsigned long __ptr; \
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
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@@ -0,0 +1,40 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef _LTQ_FALCON_H__
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+#define _LTQ_FALCON_H__
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+
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+#ifdef CONFIG_SOC_FALCON
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+
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+#include <lantiq.h>
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+
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+/* Chip IDs */
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+#define SOC_ID_FALCON 0x01B8
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+
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+/* SoC Types */
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+#define SOC_TYPE_FALCON 0x01
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+
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+/* ASC0/1 - serial port */
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+#define LTQ_ASC0_BASE_ADDR 0x1E100C00
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+#define LTQ_ASC1_BASE_ADDR 0x1E100B00
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+#define LTQ_ASC_SIZE 0x100
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+
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+#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
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+#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
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+#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
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+
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+/* ICU - interrupt control unit */
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+#define LTQ_ICU_BASE_ADDR 0x1F880200
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+#define LTQ_ICU_SIZE 0x100
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+
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+/* WDT */
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+#define LTQ_WDT_BASE_ADDR 0x1F8803F0
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+#define LTQ_WDT_SIZE 0x10
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+
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+#endif /* CONFIG_SOC_FALCON */
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+#endif /* _LTQ_XWAY_H__ */
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