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2048e10433
This adds u-boot for nbg460n ar71xx target, as it is required as second stage bootloader. Signed-off-by: Michael Kurz <michi.kurz@googlemail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24418 3c298f89-4303-0410-b956-a3cf2f4a3e73
189 lines
5.9 KiB
C
189 lines
5.9 KiB
C
/*
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* (C) Copyright 2010
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* Michael Kurz <michi.kurz@googlemail.com>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef RTL8366_MII_H
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#define RTL8366_MII_H
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#define MII_CONTROL_REG 0
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#define MII_STATUS_REG 1
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#define MII_PHY_ID0 2
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#define MII_PHY_ID1 3
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#define MII_LOCAL_CAP 4
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#define MII_REMOTE_CAP 5
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#define MII_EXT_AUTONEG 6
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#define MII_LOCAL_NEXT_PAGE 7
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#define MII_REMOTE_NEXT_PAGE 8
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#define MII_GIGA_CONTROL 9
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#define MII_GIGA_STATUS 10
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#define MII_EXT_STATUS_REG 15
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/* Control register */
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#define MII_CONTROL_1000MBPS 6
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#define MII_CONTROL_COLL_TEST 7
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#define MII_CONTROL_FULLDUPLEX 8
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#define MII_CONTROL_RENEG 9
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#define MII_CONTROL_ISOLATE 10
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#define MII_CONTROL_POWERDOWN 11
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#define MII_CONTROL_AUTONEG 12
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#define MII_CONTROL_100MBPS 13
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#define MII_CONTROL_LOOPBACK 14
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#define MII_CONTROL_RESET 15
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/* Status/Extended status register */
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/* Basic status */
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#define MII_STATUS_CAPABILITY 0
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#define MII_STATUS_JABBER 1
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#define MII_STATUS_LINK_UP 2
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#define MII_STATUS_AUTONEG_ABLE 3
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#define MII_STATUS_REMOTE_FAULT 4
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#define MII_STATUS_AUTONEG_DONE 5
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#define MII_STATUS_NO_PREAMBLE 6
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#define MII_STATUS_RESERVED 7
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#define MII_STATUS_EXTENDED 8
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#define MII_STATUS_100_T2_HALF 9
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#define MII_STATUS_100_T2_FULL 10
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#define MII_STATUS_10_TX_HALF 11
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#define MII_STATUS_10_TX_FULL 12
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#define MII_STATUS_100_TX_HALF 13
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#define MII_STATUS_100_TX_FULL 14
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#define MII_STATUS_100_T4 15
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#define MII_GIGA_CONTROL_HALF 8
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#define MII_GIGA_CONTROL_FULL 9
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#define MII_GIGA_STATUS_HALF 10
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#define MII_GIGA_STATUS_FULL 11
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/* Extended status */
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#define MII_STATUS_1000_T_HALF 12
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#define MII_STATUS_1000_T_FULL 13
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#define MII_STATUS_1000_X_HALF 14
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#define MII_STATUS_1000_X_FULL 15
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/* Local/Remmote capability register */
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#define MII_CAP_10BASE_TX 5
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#define MII_CAP_10BASE_TX_FULL 6
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#define MII_CAP_100BASE_TX 7
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#define MII_CAP_100BASE_TX_FULL 8
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#define MII_CAP_100BASE_T4 9
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#define MII_CAP_SYMM_PAUSE 10
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#define MII_CAP_ASYMM_PAUSE 11
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#define MII_CAP_RESERVED 12
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#define MII_CAP_REMOTE_FAULT 13
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#define MII_CAP_ACKNOWLEDGE 14
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#define MII_CAP_NEXT_PAGE 15
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#define MII_CAP_IEEE_802_3 0x0001
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#define MII_LINK_MODE_MASK 0x1f
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#define REALTEK_RTL8366_CHIP_ID0 0x001C
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#define REALTEK_RTL8366_CHIP_ID1 0xC940
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#define REALTEK_RTL8366_CHIP_ID1_MP 0xC960
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#define REALTEK_MIN_PORT_ID 0
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#define REALTEK_MAX_PORT_ID 5
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#define REALTEK_MIN_PHY_ID REALTEK_MIN_PORT_ID
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#define REALTEK_MAX_PHY_ID 4
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#define REALTEK_CPU_PORT_ID REALTEK_MAX_PORT_ID
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#define REALTEK_PHY_PORT_MASK ((1<<(REALTEK_MAX_PHY_ID+1)) - (1<<REALTEK_MIN_PHY_ID))
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#define REALTEK_CPU_PORT_MASK (1<<REALTEK_CPU_PORT_ID)
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#define REALTEK_ALL_PORT_MASK (REALTEK_PHY_PORT_MASK | REALTEK_CPU_PORT_MASK)
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/* port ability */
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#define RTL8366S_PORT_ABILITY_BASE 0x0011
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/* port vlan control register */
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#define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
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/* port linking status */
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#define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
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#define RTL8366S_PORT_STATUS_SPEED_BIT 0
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#define RTL8366S_PORT_STATUS_SPEED_MSK 0x0003
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#define RTL8366S_PORT_STATUS_DUPLEX_BIT 2
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#define RTL8366S_PORT_STATUS_DUPLEX_MSK 0x0004
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#define RTL8366S_PORT_STATUS_LINK_BIT 4
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#define RTL8366S_PORT_STATUS_LINK_MSK 0x0010
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#define RTL8366S_PORT_STATUS_TXPAUSE_BIT 5
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#define RTL8366S_PORT_STATUS_TXPAUSE_MSK 0x0020
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#define RTL8366S_PORT_STATUS_RXPAUSE_BIT 6
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#define RTL8366S_PORT_STATUS_RXPAUSE_MSK 0x0040
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#define RTL8366S_PORT_STATUS_AN_BIT 7
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#define RTL8366S_PORT_STATUS_AN_MSK 0x0080
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/* internal control */
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#define RTL8366S_RESET_CONTROL_REG 0x0100
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#define RTL8366S_RESET_QUEUE_BIT 2
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#define RTL8366S_CHIP_ID_REG 0x0105
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/* MAC control */
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#define RTL8366S_MAC_FORCE_CTRL0_REG 0x0F04
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#define RTL8366S_MAC_FORCE_CTRL1_REG 0x0F05
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/* PHY registers control */
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#define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
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#define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
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#define RTL8366S_PHY_CTRL_READ 1
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#define RTL8366S_PHY_CTRL_WRITE 0
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#define RTL8366S_PHY_REG_MASK 0x1F
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#define RTL8366S_PHY_PAGE_OFFSET 5
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#define RTL8366S_PHY_PAGE_MASK (0x7<<5)
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#define RTL8366S_PHY_NO_OFFSET 9
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#define RTL8366S_PHY_NO_MASK (0x1F<<9)
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#define RTL8366S_PHY_NO_MAX 4
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#define RTL8366S_PHY_PAGE_MAX 7
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#define RTL8366S_PHY_ADDR_MAX 31
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/* cpu port control reg */
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#define RTL8366S_CPU_CTRL_REG 0x004F
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#define RTL8366S_CPU_DRP_BIT 14
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#define RTL8366S_CPU_DRP_MSK 0x4000
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#define RTL8366S_CPU_INSTAG_BIT 15
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#define RTL8366S_CPU_INSTAG_MSK 0x8000
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/* LED registers*/
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#define RTL8366S_LED_BLINK_REG 0x420
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#define RTL8366S_LED_BLINKRATE_BIT 0
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#define RTL8366S_LED_BLINKRATE_MSK 0x0007
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#define RTL8366S_LED_INDICATED_CONF_REG 0x421
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#define RTL8366S_LED_0_1_FORCE_REG 0x422
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#define RTL8366S_LED_2_3_FORCE_REG 0x423
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#define RTL8366S_LEDCONF_LEDFORCE 0x1F
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#define RTL8366S_LED_GROUP_MAX 4
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#define RTL8366S_GREEN_FEATURE_REG 0x000A
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#define RTL8366S_GREEN_FEATURE_TX_BIT 3
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#define RTL8366S_GREEN_FEATURE_TX_MSK 0x0008
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#define RTL8366S_GREEN_FEATURE_RX_BIT 4
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#define RTL8366S_GREEN_FEATURE_RX_MSK 0x0010
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#define RTL8366S_MODEL_ID_REG 0x5C
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#define RTL8366S_REV_ID_REG 0x5D
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#define RTL8366S_MODEL_8366SR 0x6027
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#define RTL8366S_MODEL_8366RB 0x5937
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#endif
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