mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 23:07:43 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22774 3c298f89-4303-0410-b956-a3cf2f4a3e73
1079 lines
41 KiB
Diff
1079 lines
41 KiB
Diff
--- a/drivers/net/b44.c
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+++ b/drivers/net/b44.c
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@@ -135,7 +135,6 @@ static void b44_init_rings(struct b44 *)
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static void b44_init_hw(struct b44 *, int);
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-static int dma_desc_align_mask;
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static int dma_desc_sync_size;
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static int instance;
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@@ -150,9 +149,8 @@ static inline void b44_sync_dma_desc_for
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unsigned long offset,
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enum dma_data_direction dir)
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{
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- ssb_dma_sync_single_range_for_device(sdev, dma_base,
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- offset & dma_desc_align_mask,
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- dma_desc_sync_size, dir);
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+ dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
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+ dma_desc_sync_size, dir);
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}
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static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
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@@ -160,9 +158,8 @@ static inline void b44_sync_dma_desc_for
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unsigned long offset,
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enum dma_data_direction dir)
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{
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- ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
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- offset & dma_desc_align_mask,
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- dma_desc_sync_size, dir);
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+ dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
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+ dma_desc_sync_size, dir);
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}
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static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
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@@ -608,10 +605,10 @@ static void b44_tx(struct b44 *bp)
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BUG_ON(skb == NULL);
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- ssb_dma_unmap_single(bp->sdev,
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- rp->mapping,
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- skb->len,
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- DMA_TO_DEVICE);
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+ dma_unmap_single(bp->sdev->dma_dev,
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+ rp->mapping,
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+ skb->len,
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+ DMA_TO_DEVICE);
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rp->skb = NULL;
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dev_kfree_skb_irq(skb);
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}
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@@ -648,29 +645,29 @@ static int b44_alloc_rx_skb(struct b44 *
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if (skb == NULL)
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return -ENOMEM;
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- mapping = ssb_dma_map_single(bp->sdev, skb->data,
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- RX_PKT_BUF_SZ,
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- DMA_FROM_DEVICE);
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+ mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
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+ RX_PKT_BUF_SZ,
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+ DMA_FROM_DEVICE);
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/* Hardware bug work-around, the chip is unable to do PCI DMA
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to/from anything above 1GB :-( */
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- if (ssb_dma_mapping_error(bp->sdev, mapping) ||
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+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
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mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
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/* Sigh... */
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- if (!ssb_dma_mapping_error(bp->sdev, mapping))
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- ssb_dma_unmap_single(bp->sdev, mapping,
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+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
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+ dma_unmap_single(bp->sdev->dma_dev, mapping,
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RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
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dev_kfree_skb_any(skb);
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skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
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if (skb == NULL)
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return -ENOMEM;
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- mapping = ssb_dma_map_single(bp->sdev, skb->data,
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- RX_PKT_BUF_SZ,
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- DMA_FROM_DEVICE);
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- if (ssb_dma_mapping_error(bp->sdev, mapping) ||
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- mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
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- if (!ssb_dma_mapping_error(bp->sdev, mapping))
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- ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
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+ mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
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+ RX_PKT_BUF_SZ,
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+ DMA_FROM_DEVICE);
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+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
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+ mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
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+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
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+ dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
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dev_kfree_skb_any(skb);
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return -ENOMEM;
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}
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@@ -745,9 +742,9 @@ static void b44_recycle_rx(struct b44 *b
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dest_idx * sizeof(*dest_desc),
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DMA_BIDIRECTIONAL);
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- ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
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- RX_PKT_BUF_SZ,
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- DMA_FROM_DEVICE);
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+ dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
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+ RX_PKT_BUF_SZ,
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+ DMA_FROM_DEVICE);
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}
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static int b44_rx(struct b44 *bp, int budget)
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@@ -767,9 +764,9 @@ static int b44_rx(struct b44 *bp, int bu
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struct rx_header *rh;
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u16 len;
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- ssb_dma_sync_single_for_cpu(bp->sdev, map,
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- RX_PKT_BUF_SZ,
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- DMA_FROM_DEVICE);
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+ dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
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+ RX_PKT_BUF_SZ,
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+ DMA_FROM_DEVICE);
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rh = (struct rx_header *) skb->data;
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len = le16_to_cpu(rh->len);
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if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
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@@ -801,8 +798,8 @@ static int b44_rx(struct b44 *bp, int bu
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skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
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if (skb_size < 0)
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goto drop_it;
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- ssb_dma_unmap_single(bp->sdev, map,
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- skb_size, DMA_FROM_DEVICE);
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+ dma_unmap_single(bp->sdev->dma_dev, map,
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+ skb_size, DMA_FROM_DEVICE);
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/* Leave out rx_header */
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skb_put(skb, len + RX_PKT_OFFSET);
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skb_pull(skb, RX_PKT_OFFSET);
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@@ -954,24 +951,24 @@ static netdev_tx_t b44_start_xmit(struct
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goto err_out;
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}
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- mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
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- if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
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+ mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
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+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
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struct sk_buff *bounce_skb;
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/* Chip can't handle DMA to/from >1GB, use bounce buffer */
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- if (!ssb_dma_mapping_error(bp->sdev, mapping))
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- ssb_dma_unmap_single(bp->sdev, mapping, len,
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+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
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+ dma_unmap_single(bp->sdev->dma_dev, mapping, len,
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DMA_TO_DEVICE);
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bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
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if (!bounce_skb)
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goto err_out;
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- mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
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- len, DMA_TO_DEVICE);
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- if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
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- if (!ssb_dma_mapping_error(bp->sdev, mapping))
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- ssb_dma_unmap_single(bp->sdev, mapping,
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+ mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
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+ len, DMA_TO_DEVICE);
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+ if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
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+ if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
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+ dma_unmap_single(bp->sdev->dma_dev, mapping,
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len, DMA_TO_DEVICE);
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dev_kfree_skb_any(bounce_skb);
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goto err_out;
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@@ -1014,8 +1011,6 @@ static netdev_tx_t b44_start_xmit(struct
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if (TX_BUFFS_AVAIL(bp) < 1)
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netif_stop_queue(dev);
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- dev->trans_start = jiffies;
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-
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out_unlock:
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spin_unlock_irqrestore(&bp->lock, flags);
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@@ -1070,8 +1065,8 @@ static void b44_free_rings(struct b44 *b
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if (rp->skb == NULL)
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continue;
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- ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
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- DMA_FROM_DEVICE);
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+ dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
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+ DMA_FROM_DEVICE);
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dev_kfree_skb_any(rp->skb);
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rp->skb = NULL;
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}
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@@ -1082,8 +1077,8 @@ static void b44_free_rings(struct b44 *b
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if (rp->skb == NULL)
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continue;
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- ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
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- DMA_TO_DEVICE);
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+ dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
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+ DMA_TO_DEVICE);
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dev_kfree_skb_any(rp->skb);
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rp->skb = NULL;
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}
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@@ -1105,14 +1100,12 @@ static void b44_init_rings(struct b44 *b
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memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
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if (bp->flags & B44_FLAG_RX_RING_HACK)
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- ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
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- DMA_TABLE_BYTES,
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- DMA_BIDIRECTIONAL);
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+ dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
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+ DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
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if (bp->flags & B44_FLAG_TX_RING_HACK)
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- ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
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- DMA_TABLE_BYTES,
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- DMA_TO_DEVICE);
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+ dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
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+ DMA_TABLE_BYTES, DMA_TO_DEVICE);
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for (i = 0; i < bp->rx_pending; i++) {
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if (b44_alloc_rx_skb(bp, -1, i) < 0)
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@@ -1132,27 +1125,23 @@ static void b44_free_consistent(struct b
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bp->tx_buffers = NULL;
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if (bp->rx_ring) {
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if (bp->flags & B44_FLAG_RX_RING_HACK) {
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- ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
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- DMA_TABLE_BYTES,
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- DMA_BIDIRECTIONAL);
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+ dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
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+ DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
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kfree(bp->rx_ring);
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} else
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- ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
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- bp->rx_ring, bp->rx_ring_dma,
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- GFP_KERNEL);
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+ dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
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+ bp->rx_ring, bp->rx_ring_dma);
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bp->rx_ring = NULL;
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bp->flags &= ~B44_FLAG_RX_RING_HACK;
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}
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if (bp->tx_ring) {
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if (bp->flags & B44_FLAG_TX_RING_HACK) {
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- ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
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- DMA_TABLE_BYTES,
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- DMA_TO_DEVICE);
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+ dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
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+ DMA_TABLE_BYTES, DMA_TO_DEVICE);
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kfree(bp->tx_ring);
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} else
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- ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
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- bp->tx_ring, bp->tx_ring_dma,
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- GFP_KERNEL);
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+ dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
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+ bp->tx_ring, bp->tx_ring_dma);
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bp->tx_ring = NULL;
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bp->flags &= ~B44_FLAG_TX_RING_HACK;
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}
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@@ -1177,7 +1166,8 @@ static int b44_alloc_consistent(struct b
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goto out_err;
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size = DMA_TABLE_BYTES;
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- bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
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+ bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
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+ &bp->rx_ring_dma, gfp);
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if (!bp->rx_ring) {
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/* Allocation may have failed due to pci_alloc_consistent
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insisting on use of GFP_DMA, which is more restrictive
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@@ -1189,11 +1179,11 @@ static int b44_alloc_consistent(struct b
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if (!rx_ring)
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goto out_err;
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- rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
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- DMA_TABLE_BYTES,
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- DMA_BIDIRECTIONAL);
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+ rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
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+ DMA_TABLE_BYTES,
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+ DMA_BIDIRECTIONAL);
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- if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
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+ if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
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rx_ring_dma + size > DMA_BIT_MASK(30)) {
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kfree(rx_ring);
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goto out_err;
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@@ -1204,7 +1194,8 @@ static int b44_alloc_consistent(struct b
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bp->flags |= B44_FLAG_RX_RING_HACK;
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}
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- bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
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+ bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
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+ &bp->tx_ring_dma, gfp);
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if (!bp->tx_ring) {
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/* Allocation may have failed due to ssb_dma_alloc_consistent
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insisting on use of GFP_DMA, which is more restrictive
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@@ -1216,11 +1207,11 @@ static int b44_alloc_consistent(struct b
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if (!tx_ring)
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goto out_err;
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- tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
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- DMA_TABLE_BYTES,
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- DMA_TO_DEVICE);
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+ tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
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+ DMA_TABLE_BYTES,
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+ DMA_TO_DEVICE);
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- if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
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+ if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
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tx_ring_dma + size > DMA_BIT_MASK(30)) {
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kfree(tx_ring);
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goto out_err;
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@@ -2178,12 +2169,14 @@ static int __devinit b44_init_one(struct
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"Failed to powerup the bus\n");
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goto err_out_free_dev;
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}
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- err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
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- if (err) {
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+
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+ if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
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+ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
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dev_err(sdev->dev,
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"Required 30BIT DMA mask unsupported by the system\n");
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goto err_out_powerdown;
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}
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+
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err = b44_get_invariants(bp);
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if (err) {
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dev_err(sdev->dev,
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@@ -2346,7 +2339,6 @@ static int __init b44_init(void)
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int err;
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|
|
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/* Setup paramaters for syncing RX/TX DMA descriptors */
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- dma_desc_align_mask = ~(dma_desc_align_size - 1);
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dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
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|
|
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err = b44_pci_init();
|
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--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str
|
|
}
|
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}
|
|
|
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+/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
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|
+static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
|
|
+{
|
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+ struct ssb_bus *bus = cc->dev->bus;
|
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+
|
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+ switch (bus->chip_id) {
|
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+ case 0x4312:
|
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+ case 0x4322:
|
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+ case 0x4328:
|
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+ return 7000;
|
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+ case 0x4325:
|
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+ /* TODO: */
|
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+ default:
|
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+ return 15000;
|
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+ }
|
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+}
|
|
+
|
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+/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
|
|
static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
|
|
{
|
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struct ssb_bus *bus = cc->dev->bus;
|
|
@@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru
|
|
|
|
if (bus->bustype != SSB_BUSTYPE_PCI)
|
|
return;
|
|
+
|
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
|
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+ cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
|
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+ return;
|
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+ }
|
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+
|
|
if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
|
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return;
|
|
|
|
@@ -373,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
|
|
{
|
|
return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
|
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}
|
|
+EXPORT_SYMBOL(ssb_chipco_gpio_control);
|
|
|
|
u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
|
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{
|
|
--- a/drivers/ssb/driver_chipcommon_pmu.c
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|
+++ b/drivers/ssb/driver_chipcommon_pmu.c
|
|
@@ -502,9 +502,9 @@ static void ssb_pmu_resources_init(struc
|
|
chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
|
|
}
|
|
|
|
+/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
|
|
void ssb_pmu_init(struct ssb_chipcommon *cc)
|
|
{
|
|
- struct ssb_bus *bus = cc->dev->bus;
|
|
u32 pmucap;
|
|
|
|
if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
|
|
@@ -516,15 +516,12 @@ void ssb_pmu_init(struct ssb_chipcommon
|
|
ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
|
|
cc->pmu.rev, pmucap);
|
|
|
|
- if (cc->pmu.rev >= 1) {
|
|
- if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
|
|
- chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
|
|
- ~SSB_CHIPCO_PMU_CTL_NOILPONW);
|
|
- } else {
|
|
- chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
|
|
- SSB_CHIPCO_PMU_CTL_NOILPONW);
|
|
- }
|
|
- }
|
|
+ if (cc->pmu.rev == 1)
|
|
+ chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
|
|
+ ~SSB_CHIPCO_PMU_CTL_NOILPONW);
|
|
+ else
|
|
+ chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
|
|
+ SSB_CHIPCO_PMU_CTL_NOILPONW);
|
|
ssb_pmu_pll_init(cc);
|
|
ssb_pmu_resources_init(cc);
|
|
}
|
|
--- a/drivers/ssb/main.c
|
|
+++ b/drivers/ssb/main.c
|
|
@@ -486,6 +486,7 @@ static int ssb_devices_register(struct s
|
|
#ifdef CONFIG_SSB_PCIHOST
|
|
sdev->irq = bus->host_pci->irq;
|
|
dev->parent = &bus->host_pci->dev;
|
|
+ sdev->dma_dev = dev->parent;
|
|
#endif
|
|
break;
|
|
case SSB_BUSTYPE_PCMCIA:
|
|
@@ -501,6 +502,7 @@ static int ssb_devices_register(struct s
|
|
break;
|
|
case SSB_BUSTYPE_SSB:
|
|
dev->dma_mask = &dev->coherent_dma_mask;
|
|
+ sdev->dma_dev = dev;
|
|
break;
|
|
}
|
|
|
|
@@ -834,6 +836,9 @@ int ssb_bus_pcibus_register(struct ssb_b
|
|
if (!err) {
|
|
ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
|
|
"PCI device %s\n", dev_name(&host_pci->dev));
|
|
+ } else {
|
|
+ ssb_printk(KERN_ERR PFX "Failed to register PCI version"
|
|
+ " of SSB with error %d\n", err);
|
|
}
|
|
|
|
return err;
|
|
@@ -1223,80 +1228,6 @@ u32 ssb_dma_translation(struct ssb_devic
|
|
}
|
|
EXPORT_SYMBOL(ssb_dma_translation);
|
|
|
|
-int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
|
|
-{
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- int err;
|
|
-#endif
|
|
-
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- err = pci_set_dma_mask(dev->bus->host_pci, mask);
|
|
- if (err)
|
|
- return err;
|
|
- err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
|
|
- return err;
|
|
-#endif
|
|
- case SSB_BUSTYPE_SSB:
|
|
- return dma_set_mask(dev->dev, mask);
|
|
- default:
|
|
- __ssb_dma_not_implemented(dev);
|
|
- }
|
|
- return -ENOSYS;
|
|
-}
|
|
-EXPORT_SYMBOL(ssb_dma_set_mask);
|
|
-
|
|
-void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
|
|
- dma_addr_t *dma_handle, gfp_t gfp_flags)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- if (gfp_flags & GFP_DMA) {
|
|
- /* Workaround: The PCI API does not support passing
|
|
- * a GFP flag. */
|
|
- return dma_alloc_coherent(&dev->bus->host_pci->dev,
|
|
- size, dma_handle, gfp_flags);
|
|
- }
|
|
- return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
|
|
-#endif
|
|
- case SSB_BUSTYPE_SSB:
|
|
- return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
|
|
- default:
|
|
- __ssb_dma_not_implemented(dev);
|
|
- }
|
|
- return NULL;
|
|
-}
|
|
-EXPORT_SYMBOL(ssb_dma_alloc_consistent);
|
|
-
|
|
-void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
|
|
- void *vaddr, dma_addr_t dma_handle,
|
|
- gfp_t gfp_flags)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- if (gfp_flags & GFP_DMA) {
|
|
- /* Workaround: The PCI API does not support passing
|
|
- * a GFP flag. */
|
|
- dma_free_coherent(&dev->bus->host_pci->dev,
|
|
- size, vaddr, dma_handle);
|
|
- return;
|
|
- }
|
|
- pci_free_consistent(dev->bus->host_pci, size,
|
|
- vaddr, dma_handle);
|
|
- return;
|
|
-#endif
|
|
- case SSB_BUSTYPE_SSB:
|
|
- dma_free_coherent(dev->dev, size, vaddr, dma_handle);
|
|
- return;
|
|
- default:
|
|
- __ssb_dma_not_implemented(dev);
|
|
- }
|
|
-}
|
|
-EXPORT_SYMBOL(ssb_dma_free_consistent);
|
|
-
|
|
int ssb_bus_may_powerdown(struct ssb_bus *bus)
|
|
{
|
|
struct ssb_chipcommon *cc;
|
|
--- a/drivers/ssb/pci.c
|
|
+++ b/drivers/ssb/pci.c
|
|
@@ -168,7 +168,7 @@ err_pci:
|
|
}
|
|
|
|
/* Get the word-offset for a SSB_SPROM_XXX define. */
|
|
-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
|
|
+#define SPOFF(offset) ((offset) / sizeof(u16))
|
|
/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
|
|
#define SPEX16(_outvar, _offset, _mask, _shift) \
|
|
out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -167,7 +167,7 @@ struct ssb_device {
|
|
* is an optimization. */
|
|
const struct ssb_bus_ops *ops;
|
|
|
|
- struct device *dev;
|
|
+ struct device *dev, *dma_dev;
|
|
|
|
struct ssb_bus *bus;
|
|
struct ssb_device_id id;
|
|
@@ -470,14 +470,6 @@ extern u32 ssb_dma_translation(struct ss
|
|
#define SSB_DMA_TRANSLATION_MASK 0xC0000000
|
|
#define SSB_DMA_TRANSLATION_SHIFT 30
|
|
|
|
-extern int ssb_dma_set_mask(struct ssb_device *dev, u64 mask);
|
|
-
|
|
-extern void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
|
|
- dma_addr_t *dma_handle, gfp_t gfp_flags);
|
|
-extern void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
|
|
- void *vaddr, dma_addr_t dma_handle,
|
|
- gfp_t gfp_flags);
|
|
-
|
|
static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
|
|
{
|
|
#ifdef CONFIG_SSB_DEBUG
|
|
@@ -486,155 +478,6 @@ static inline void __cold __ssb_dma_not_
|
|
#endif /* DEBUG */
|
|
}
|
|
|
|
-static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- return pci_dma_mapping_error(dev->bus->host_pci, addr);
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- return dma_mapping_error(dev->dev, addr);
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
- return -ENOSYS;
|
|
-}
|
|
-
|
|
-static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p,
|
|
- size_t size, enum dma_data_direction dir)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- return pci_map_single(dev->bus->host_pci, p, size, dir);
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- return dma_map_single(dev->dev, p, size, dir);
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
- return 0;
|
|
-}
|
|
-
|
|
-static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_addr,
|
|
- size_t size, enum dma_data_direction dir)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
|
|
- return;
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- dma_unmap_single(dev->dev, dma_addr, size, dir);
|
|
- return;
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
-}
|
|
-
|
|
-static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
|
|
- dma_addr_t dma_addr,
|
|
- size_t size,
|
|
- enum dma_data_direction dir)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
|
|
- size, dir);
|
|
- return;
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
|
|
- return;
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
-}
|
|
-
|
|
-static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
|
|
- dma_addr_t dma_addr,
|
|
- size_t size,
|
|
- enum dma_data_direction dir)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
|
|
- size, dir);
|
|
- return;
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
|
|
- return;
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
-}
|
|
-
|
|
-static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
|
|
- dma_addr_t dma_addr,
|
|
- unsigned long offset,
|
|
- size_t size,
|
|
- enum dma_data_direction dir)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- /* Just sync everything. That's all the PCI API can do. */
|
|
- pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
|
|
- offset + size, dir);
|
|
- return;
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
|
|
- size, dir);
|
|
- return;
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
-}
|
|
-
|
|
-static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
|
|
- dma_addr_t dma_addr,
|
|
- unsigned long offset,
|
|
- size_t size,
|
|
- enum dma_data_direction dir)
|
|
-{
|
|
- switch (dev->bus->bustype) {
|
|
- case SSB_BUSTYPE_PCI:
|
|
-#ifdef CONFIG_SSB_PCIHOST
|
|
- /* Just sync everything. That's all the PCI API can do. */
|
|
- pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
|
|
- offset + size, dir);
|
|
- return;
|
|
-#endif
|
|
- break;
|
|
- case SSB_BUSTYPE_SSB:
|
|
- dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
|
|
- size, dir);
|
|
- return;
|
|
- default:
|
|
- break;
|
|
- }
|
|
- __ssb_dma_not_implemented(dev);
|
|
-}
|
|
-
|
|
-
|
|
#ifdef CONFIG_SSB_PCIHOST
|
|
/* PCI-host wrapper driver */
|
|
extern int ssb_pcihost_register(struct pci_driver *driver);
|
|
--- a/include/linux/ssb/ssb_regs.h
|
|
+++ b/include/linux/ssb/ssb_regs.h
|
|
@@ -172,25 +172,25 @@
|
|
#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
|
|
#define SSB_SPROM_BASE1 0x1000
|
|
#define SSB_SPROM_BASE31 0x0800
|
|
-#define SSB_SPROM_REVISION 0x107E
|
|
+#define SSB_SPROM_REVISION 0x007E
|
|
#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
|
|
#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
|
|
#define SSB_SPROM_REVISION_CRC_SHIFT 8
|
|
|
|
/* SPROM Revision 1 */
|
|
-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
|
|
-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
|
|
-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
|
|
-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
|
|
-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
|
|
-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
|
|
-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
|
|
+#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
|
|
+#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
|
|
+#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
|
|
+#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
|
|
+#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
|
|
+#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
|
|
+#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
|
|
#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
|
|
#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
|
|
#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
|
|
#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
|
#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
|
-#define SSB_SPROM1_BINF 0x105C /* Board info */
|
|
+#define SSB_SPROM1_BINF 0x005C /* Board info */
|
|
#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
|
|
#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
|
|
#define SSB_SPROM1_BINF_CCODE_SHIFT 8
|
|
@@ -198,63 +198,63 @@
|
|
#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
|
|
#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
|
|
#define SSB_SPROM1_BINF_ANTA_SHIFT 14
|
|
-#define SSB_SPROM1_PA0B0 0x105E
|
|
-#define SSB_SPROM1_PA0B1 0x1060
|
|
-#define SSB_SPROM1_PA0B2 0x1062
|
|
-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
|
|
+#define SSB_SPROM1_PA0B0 0x005E
|
|
+#define SSB_SPROM1_PA0B1 0x0060
|
|
+#define SSB_SPROM1_PA0B2 0x0062
|
|
+#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
|
|
#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
|
|
#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
|
|
#define SSB_SPROM1_GPIOA_P1_SHIFT 8
|
|
-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
|
|
+#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
|
|
#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
|
|
#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
|
|
#define SSB_SPROM1_GPIOB_P3_SHIFT 8
|
|
-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
|
|
+#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
|
|
#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
|
|
#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
|
|
#define SSB_SPROM1_MAXPWR_A_SHIFT 8
|
|
-#define SSB_SPROM1_PA1B0 0x106A
|
|
-#define SSB_SPROM1_PA1B1 0x106C
|
|
-#define SSB_SPROM1_PA1B2 0x106E
|
|
-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
|
|
+#define SSB_SPROM1_PA1B0 0x006A
|
|
+#define SSB_SPROM1_PA1B1 0x006C
|
|
+#define SSB_SPROM1_PA1B2 0x006E
|
|
+#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
|
|
#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
|
|
#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
|
|
#define SSB_SPROM1_ITSSI_A_SHIFT 8
|
|
-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
|
|
-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
|
|
+#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
|
|
+#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
|
|
#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
|
|
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
|
|
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
|
|
#define SSB_SPROM1_AGAIN_A_SHIFT 8
|
|
|
|
/* SPROM Revision 2 (inherits from rev 1) */
|
|
-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
|
|
-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
|
|
+#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
|
|
+#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
|
|
#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
|
|
#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
|
|
#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
|
|
-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
|
|
-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
|
|
-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
|
|
-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
|
|
-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
|
|
-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
|
|
-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
|
|
+#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
|
|
+#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
|
|
+#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
|
|
+#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
|
|
+#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
|
|
+#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
|
|
+#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
|
|
#define SSB_SPROM2_OPO_VALUE 0x00FF
|
|
#define SSB_SPROM2_OPO_UNUSED 0xFF00
|
|
-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
|
|
+#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
|
|
|
|
/* SPROM Revision 3 (inherits most data from rev 2) */
|
|
-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
|
|
-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
|
|
-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
|
|
-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
|
|
-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
|
|
+#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
|
|
+#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
|
|
+#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
|
|
+#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
|
|
#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
|
|
#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
|
|
#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
|
|
#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
|
|
-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
|
|
+#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
|
|
+#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
|
|
#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
|
|
#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
|
|
#define SSB_SPROM3_CCKPO_2M_SHIFT 4
|
|
@@ -265,100 +265,100 @@
|
|
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
|
|
|
|
/* SPROM Revision 4 */
|
|
-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
|
|
-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
|
|
+#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
|
|
+#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
|
|
+#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
|
|
+#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
|
|
+#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
|
|
+#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
|
|
+#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
|
|
+#define SSB_SPROM4_GPIOA_P1_SHIFT 8
|
|
+#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
|
|
+#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
|
|
+#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
|
|
+#define SSB_SPROM4_GPIOB_P3_SHIFT 8
|
|
+#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
|
|
#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
|
|
#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
|
|
#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
|
|
#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
|
|
#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
|
|
-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
|
|
-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
|
|
-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
|
-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
|
-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
|
-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
|
-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
|
|
-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
|
|
+#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
|
|
+#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
|
|
+#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
|
|
+#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
|
|
+#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
|
|
+#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
|
|
#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
|
|
#define SSB_SPROM4_AGAIN0_SHIFT 0
|
|
#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
|
|
#define SSB_SPROM4_AGAIN1_SHIFT 8
|
|
-#define SSB_SPROM4_AGAIN23 0x1060
|
|
+#define SSB_SPROM4_AGAIN23 0x0060
|
|
#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
|
|
#define SSB_SPROM4_AGAIN2_SHIFT 0
|
|
#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
|
|
#define SSB_SPROM4_AGAIN3_SHIFT 8
|
|
-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
|
|
-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
|
|
+#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
|
|
#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
|
|
#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
|
#define SSB_SPROM4_ITSSI_BG_SHIFT 8
|
|
-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
|
|
+#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
|
|
#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
|
|
#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
|
|
#define SSB_SPROM4_ITSSI_A_SHIFT 8
|
|
-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
|
|
-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
|
|
-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
|
|
-#define SSB_SPROM4_GPIOA_P1_SHIFT 8
|
|
-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
|
|
-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
|
|
-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
|
|
-#define SSB_SPROM4_GPIOB_P3_SHIFT 8
|
|
-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
|
|
-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
|
|
-#define SSB_SPROM4_PA0B2 0x1086
|
|
-#define SSB_SPROM4_PA1B0 0x108E
|
|
-#define SSB_SPROM4_PA1B1 0x1090
|
|
-#define SSB_SPROM4_PA1B2 0x1092
|
|
+#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
|
|
+#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
|
|
+#define SSB_SPROM4_PA0B2 0x0086
|
|
+#define SSB_SPROM4_PA1B0 0x008E
|
|
+#define SSB_SPROM4_PA1B1 0x0090
|
|
+#define SSB_SPROM4_PA1B2 0x0092
|
|
|
|
/* SPROM Revision 5 (inherits most data from rev 4) */
|
|
-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
|
|
-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
|
|
-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
|
|
-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
|
|
-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
|
|
+#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
|
|
+#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
|
|
+#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
|
|
+#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
|
|
+#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
|
|
#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
|
|
#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
|
|
#define SSB_SPROM5_GPIOA_P1_SHIFT 8
|
|
-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
|
|
+#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
|
|
#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
|
|
#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
|
|
#define SSB_SPROM5_GPIOB_P3_SHIFT 8
|
|
|
|
/* SPROM Revision 8 */
|
|
-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
|
|
-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
|
|
-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
|
|
-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
|
|
-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
|
|
-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
|
|
-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
|
|
-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
|
|
-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
|
|
-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
|
|
-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
|
-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
|
|
-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
|
|
+#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
|
|
+#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
|
|
+#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
|
|
+#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
|
|
+#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
|
|
+#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
|
|
+#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
|
|
+#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
|
|
+#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
|
|
+#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
|
|
+#define SSB_SPROM8_GPIOA_P1_SHIFT 8
|
|
+#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
|
|
+#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
|
|
+#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
|
|
+#define SSB_SPROM8_GPIOB_P3_SHIFT 8
|
|
+#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
|
|
+#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
|
|
+#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
|
|
+#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
|
|
+#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
|
|
+#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
|
|
#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
|
|
#define SSB_SPROM8_AGAIN0_SHIFT 0
|
|
#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
|
|
#define SSB_SPROM8_AGAIN1_SHIFT 8
|
|
-#define SSB_SPROM8_AGAIN23 0x10A0
|
|
+#define SSB_SPROM8_AGAIN23 0x00A0
|
|
#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
|
|
#define SSB_SPROM8_AGAIN2_SHIFT 0
|
|
#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
|
|
#define SSB_SPROM8_AGAIN3_SHIFT 8
|
|
-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
|
|
-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
|
|
-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
|
|
-#define SSB_SPROM8_GPIOA_P1_SHIFT 8
|
|
-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
|
|
-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
|
|
-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
|
|
-#define SSB_SPROM8_GPIOB_P3_SHIFT 8
|
|
-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
|
|
+#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
|
|
#define SSB_SPROM8_RSSISMF2G 0x000F
|
|
#define SSB_SPROM8_RSSISMC2G 0x00F0
|
|
#define SSB_SPROM8_RSSISMC2G_SHIFT 4
|
|
@@ -366,7 +366,7 @@
|
|
#define SSB_SPROM8_RSSISAV2G_SHIFT 8
|
|
#define SSB_SPROM8_BXA2G 0x1800
|
|
#define SSB_SPROM8_BXA2G_SHIFT 11
|
|
-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
|
|
+#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
|
|
#define SSB_SPROM8_RSSISMF5G 0x000F
|
|
#define SSB_SPROM8_RSSISMC5G 0x00F0
|
|
#define SSB_SPROM8_RSSISMC5G_SHIFT 4
|
|
@@ -374,47 +374,47 @@
|
|
#define SSB_SPROM8_RSSISAV5G_SHIFT 8
|
|
#define SSB_SPROM8_BXA5G 0x1800
|
|
#define SSB_SPROM8_BXA5G_SHIFT 11
|
|
-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
|
|
+#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
|
|
#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
|
|
#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
|
|
#define SSB_SPROM8_TRI5G_SHIFT 8
|
|
-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
|
|
+#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
|
|
#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
|
|
#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
|
|
#define SSB_SPROM8_TRI5GH_SHIFT 8
|
|
-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
|
|
+#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
|
|
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
|
|
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
|
|
#define SSB_SPROM8_RXPO5G_SHIFT 8
|
|
-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
|
|
+#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
|
|
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
|
|
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
|
|
#define SSB_SPROM8_ITSSI_BG_SHIFT 8
|
|
-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
|
|
-#define SSB_SPROM8_PA0B1 0x10C4
|
|
-#define SSB_SPROM8_PA0B2 0x10C6
|
|
-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
|
|
+#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
|
|
+#define SSB_SPROM8_PA0B1 0x00C4
|
|
+#define SSB_SPROM8_PA0B2 0x00C6
|
|
+#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
|
|
#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
|
|
#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
|
|
#define SSB_SPROM8_ITSSI_A_SHIFT 8
|
|
-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
|
|
+#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
|
|
#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
|
|
#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
|
|
#define SSB_SPROM8_MAXP_AL_SHIFT 8
|
|
-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
|
|
-#define SSB_SPROM8_PA1B1 0x10CE
|
|
-#define SSB_SPROM8_PA1B2 0x10D0
|
|
-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
|
|
-#define SSB_SPROM8_PA1LOB1 0x10D4
|
|
-#define SSB_SPROM8_PA1LOB2 0x10D6
|
|
-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
|
|
-#define SSB_SPROM8_PA1HIB1 0x10DA
|
|
-#define SSB_SPROM8_PA1HIB2 0x10DC
|
|
-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
|
|
-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
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-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
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-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
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-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
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+#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
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+#define SSB_SPROM8_PA1B1 0x00CE
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+#define SSB_SPROM8_PA1B2 0x00D0
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+#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
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+#define SSB_SPROM8_PA1LOB1 0x00D4
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+#define SSB_SPROM8_PA1LOB2 0x00D6
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+#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
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+#define SSB_SPROM8_PA1HIB1 0x00DA
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+#define SSB_SPROM8_PA1HIB2 0x00DC
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+#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
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+#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
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+#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
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+#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
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+#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
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/* Values for SSB_SPROM1_BINF_CCODE */
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enum {
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