mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 23:24:37 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21438 3c298f89-4303-0410-b956-a3cf2f4a3e73
499 lines
12 KiB
Diff
499 lines
12 KiB
Diff
From 0ba56db361ac905ff2e2d4e6288206c73e3df523 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 24 Apr 2010 12:18:01 +0200
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Subject: [PATCH] Add jz4740 adc driver
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---
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drivers/misc/Kconfig | 11 ++
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drivers/misc/Makefile | 1 +
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drivers/misc/jz4740-adc.c | 410 ++++++++++++++++++++++++++++++++++++++++++++
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include/linux/jz4740-adc.h | 25 +++
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4 files changed, 447 insertions(+), 0 deletions(-)
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create mode 100644 drivers/misc/jz4740-adc.c
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create mode 100644 include/linux/jz4740-adc.h
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diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
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index 0d0d625..c62f615 100644
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--- a/drivers/misc/Kconfig
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+++ b/drivers/misc/Kconfig
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@@ -327,6 +327,17 @@ config VMWARE_BALLOON
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To compile this driver as a module, choose M here: the
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module will be called vmware_balloon.
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+config JZ4740_ADC
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+ tristate "Ingenic JZ4720/JZ4740 SoC ADC driver"
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+ depends on SOC_JZ4740
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+ help
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+ If you say yes here you get support for the Ingenic JZ4720/JZ4740 SoC ADC
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+ core. It is required for the JZ4720/JZ4740 battery and touchscreen driver
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+ and is used to synchronize access to the adc core between those two.
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+
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+ This driver can also be build as a module. If so, the module will be
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+ called jz4740-adc.
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+
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source "drivers/misc/c2port/Kconfig"
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source "drivers/misc/eeprom/Kconfig"
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source "drivers/misc/cb710/Kconfig"
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diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
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index 7b6f7ee..506bcf6 100644
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--- a/drivers/misc/Makefile
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+++ b/drivers/misc/Makefile
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@@ -27,6 +27,7 @@ obj-$(CONFIG_DS1682) += ds1682.o
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obj-$(CONFIG_TI_DAC7512) += ti_dac7512.o
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obj-$(CONFIG_C2PORT) += c2port/
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obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/
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+obj-$(CONFIG_JZ4740_ADC) += jz4740-adc.o
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obj-y += eeprom/
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obj-y += cb710/
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obj-$(CONFIG_VMWARE_BALLOON) += vmware_balloon.o
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diff --git a/drivers/misc/jz4740-adc.c b/drivers/misc/jz4740-adc.c
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new file mode 100644
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index 0000000..a8a735a
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--- /dev/null
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+++ b/drivers/misc/jz4740-adc.c
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@@ -0,0 +1,410 @@
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+/*
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+ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4720/JZ4740 SoC ADC driver
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ * This driver is meant to synchronize access to the adc core for the battery
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+ * and touchscreen driver. Thus these drivers should use the adc driver as a
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+ * parent.
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+ */
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+
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+#include <linux/err.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+#include <linux/interrupt.h>
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+
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+#include <linux/clk.h>
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+
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+#include <linux/jz4740-adc.h>
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+
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+#define JZ_REG_ADC_ENABLE 0x00
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+#define JZ_REG_ADC_CFG 0x04
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+#define JZ_REG_ADC_CTRL 0x08
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+#define JZ_REG_ADC_STATUS 0x0C
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+#define JZ_REG_ADC_SAME 0x10
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+#define JZ_REG_ADC_WAIT 0x14
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+#define JZ_REG_ADC_TOUCH 0x18
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+#define JZ_REG_ADC_BATTERY 0x1C
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+#define JZ_REG_ADC_ADCIN 0x20
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+
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+#define JZ_ADC_ENABLE_TOUCH BIT(2)
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+#define JZ_ADC_ENABLE_BATTERY BIT(1)
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+#define JZ_ADC_ENABLE_ADCIN BIT(0)
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+
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+#define JZ_ADC_CFG_SPZZ BIT(31)
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+#define JZ_ADC_CFG_EX_IN BIT(30)
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+#define JZ_ADC_CFG_DNUM_MASK (0x7 << 16)
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+#define JZ_ADC_CFG_DMA_ENABLE BIT(15)
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+#define JZ_ADC_CFG_XYZ_MASK (0x2 << 13)
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+#define JZ_ADC_CFG_SAMPLE_NUM_MASK (0x7 << 10)
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+#define JZ_ADC_CFG_CLKDIV (0xf << 5)
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+#define JZ_ADC_CFG_BAT_MB BIT(4)
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+
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+#define JZ_ADC_CFG_DNUM_OFFSET 16
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+#define JZ_ADC_CFG_XYZ_OFFSET 13
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+#define JZ_ADC_CFG_SAMPLE_NUM_OFFSET 10
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+#define JZ_ADC_CFG_CLKDIV_OFFSET 5
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+
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+#define JZ_ADC_IRQ_PENDOWN BIT(4)
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+#define JZ_ADC_IRQ_PENUP BIT(3)
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+#define JZ_ADC_IRQ_TOUCH BIT(2)
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+#define JZ_ADC_IRQ_BATTERY BIT(1)
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+#define JZ_ADC_IRQ_ADCIN BIT(0)
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+
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+#define JZ_ADC_TOUCH_TYPE1 BIT(31)
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+#define JZ_ADC_TOUCH_DATA1_MASK 0xfff
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+#define JZ_ADC_TOUCH_TYPE0 BIT(15)
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+#define JZ_ADC_TOUCH_DATA0_MASK 0xfff
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+
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+#define JZ_ADC_BATTERY_MASK 0xfff
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+
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+#define JZ_ADC_ADCIN_MASK 0xfff
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+
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+struct jz4740_adc {
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+ struct resource *mem;
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+ void __iomem *base;
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+
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+ int irq;
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+
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+ struct clk *clk;
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+ unsigned int clk_ref;
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+
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+ struct completion bat_completion;
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+ struct completion adc_completion;
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+
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+ spinlock_t lock;
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+};
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+
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+static irqreturn_t jz4740_adc_irq(int irq, void *data)
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+{
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+ struct jz4740_adc *adc = data;
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+ uint8_t status;
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+
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+ status = readb(adc->base + JZ_REG_ADC_STATUS);
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+
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+ if (status & JZ_ADC_IRQ_BATTERY)
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+ complete(&adc->bat_completion);
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+ if (status & JZ_ADC_IRQ_ADCIN)
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+ complete(&adc->adc_completion);
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+
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+ writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
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+{
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+ unsigned long flags;
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+ uint8_t val;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ val = readb(adc->base + JZ_REG_ADC_CTRL);
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+ val &= ~irq;
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+ writeb(val, adc->base + JZ_REG_ADC_CTRL);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
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+{
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+ unsigned long flags;
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+ uint8_t val;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ val = readb(adc->base + JZ_REG_ADC_CTRL);
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+ val |= irq;
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+ writeb(val, adc->base + JZ_REG_ADC_CTRL);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
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+{
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+ unsigned long flags;
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+ uint8_t val;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ val = readb(adc->base + JZ_REG_ADC_ENABLE);
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+ val |= engine;
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+ writeb(val, adc->base + JZ_REG_ADC_ENABLE);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
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+{
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+ unsigned long flags;
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+ uint8_t val;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ val = readb(adc->base + JZ_REG_ADC_ENABLE);
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+ val &= ~engine;
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+ writeb(val, adc->base + JZ_REG_ADC_ENABLE);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
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+uint32_t val)
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+{
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+ unsigned long flags;
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+ uint32_t cfg;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ cfg = readl(adc->base + JZ_REG_ADC_CFG);
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+
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+ cfg &= ~mask;
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+ cfg |= val;
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+
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+ writel(cfg, adc->base + JZ_REG_ADC_CFG);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+ if (adc->clk_ref++ == 0)
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+ clk_enable(adc->clk);
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+ if (--adc->clk_ref == 0)
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+ clk_disable(adc->clk);
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+long jz4740_adc_read_battery_voltage(struct device *dev,
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+ enum jz_adc_battery_scale scale)
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+{
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+ struct jz4740_adc *adc = dev_get_drvdata(dev);
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+ unsigned long t;
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+ long long voltage;
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+ uint16_t val;
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+
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+ if (!adc)
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+ return -ENODEV;
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+
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+ jz4740_adc_clk_enable(adc);
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+
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+ if (scale == JZ_ADC_BATTERY_SCALE_2V5)
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+ jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
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+ else
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+ jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
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+
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+ jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
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+ jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
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+
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+ t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
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+ HZ);
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+
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+ jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
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+
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+ if (t <= 0) {
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+ jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
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+ return t ? t : -ETIMEDOUT;
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+ }
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+
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+ val = readw(adc->base + JZ_REG_ADC_BATTERY);
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+
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+ jz4740_adc_clk_disable(adc);
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+
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+ if (scale == JZ_ADC_BATTERY_SCALE_2V5)
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+ voltage = (((long long)val) * 2500000LL) >> 12LL;
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+ else
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+ voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
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+
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+ return voltage;
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+}
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+EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
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+
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+static ssize_t jz4740_adc_read_adcin(struct device *dev,
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+ struct device_attribute *dev_attr,
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+ char *buf)
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+{
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+ struct jz4740_adc *adc = dev_get_drvdata(dev);
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+ unsigned long t;
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+ uint16_t val;
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+
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+ jz4740_adc_clk_enable(adc);
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+
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+ jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
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+ jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
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+
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+ t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
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+ HZ);
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+
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+ jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
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+
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+ if (t <= 0) {
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+ jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
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+ return t ? t : -ETIMEDOUT;
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+ }
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+
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+ val = readw(adc->base + JZ_REG_ADC_ADCIN);
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+ jz4740_adc_clk_disable(adc);
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+
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+ return sprintf(buf, "%d\n", val);
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+}
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+
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+static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
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+
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+static int __devinit jz4740_adc_probe(struct platform_device *pdev)
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+{
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+ int ret;
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+ struct jz4740_adc *adc;
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+
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+ adc = kmalloc(sizeof(*adc), GFP_KERNEL);
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+
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+ adc->irq = platform_get_irq(pdev, 0);
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+
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+ if (adc->irq < 0) {
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+ ret = adc->irq;
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+ dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
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+ goto err_free;
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+ }
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+
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+ adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ if (!adc->mem) {
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+ ret = -ENOENT;
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+ dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
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+ goto err_free;
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+ }
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+
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+ adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
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+ pdev->name);
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+
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+ if (!adc->mem) {
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+ ret = -EBUSY;
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+ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
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+ goto err_free;
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+ }
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+
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+ adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
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+
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+ if (!adc->base) {
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+ ret = -EBUSY;
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+ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
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+ goto err_release_mem_region;
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+ }
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+
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+ adc->clk = clk_get(&pdev->dev, "adc");
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+
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+ if (IS_ERR(adc->clk)) {
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+ ret = PTR_ERR(adc->clk);
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+ dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
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+ goto err_iounmap;
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+ }
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+
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+ init_completion(&adc->bat_completion);
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+ init_completion(&adc->adc_completion);
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+
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+ spin_lock_init(&adc->lock);
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+
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+ adc->clk_ref = 0;
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+
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+ platform_set_drvdata(pdev, adc);
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+
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+ ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
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+
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+ if (ret) {
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+ dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
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+ goto err_clk_put;
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+ }
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+
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+ ret = device_create_file(&pdev->dev, &dev_attr_adcin);
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+ if (ret) {
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+ dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
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+ goto err_free_irq;
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+ }
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+
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+ writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
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+ writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
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+
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+ return 0;
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+
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+err_free_irq:
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+ free_irq(adc->irq, adc);
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+err_clk_put:
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+ clk_put(adc->clk);
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+err_iounmap:
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+ platform_set_drvdata(pdev, NULL);
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+ iounmap(adc->base);
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+err_release_mem_region:
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+ release_mem_region(adc->mem->start, resource_size(adc->mem));
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+err_free:
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+ kfree(adc);
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+
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+ return ret;
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+}
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+
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+static int __devexit jz4740_adc_remove(struct platform_device *pdev)
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+{
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+ struct jz4740_adc *adc = platform_get_drvdata(pdev);
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+
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+ device_remove_file(&pdev->dev, &dev_attr_adcin);
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+
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+ free_irq(adc->irq, adc);
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+
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+ iounmap(adc->base);
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+ release_mem_region(adc->mem->start, resource_size(adc->mem));
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+
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+ clk_put(adc->clk);
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+
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+ platform_set_drvdata(pdev, NULL);
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+
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+ kfree(adc);
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+
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+ return 0;
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+}
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+
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+struct platform_driver jz4740_adc_driver = {
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+ .probe = jz4740_adc_probe,
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+ .remove = __devexit_p(jz4740_adc_remove),
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+ .driver = {
|
|
+ .name = "jz4740-adc",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init jz4740_adc_init(void)
|
|
+{
|
|
+ return platform_driver_register(&jz4740_adc_driver);
|
|
+}
|
|
+module_init(jz4740_adc_init);
|
|
+
|
|
+static void __exit jz4740_adc_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&jz4740_adc_driver);
|
|
+}
|
|
+module_exit(jz4740_adc_exit);
|
|
+
|
|
+MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
|
|
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_ALIAS("platform:jz4740-adc");
|
|
+MODULE_ALIAS("platform:jz4720-adc");
|
|
diff --git a/include/linux/jz4740-adc.h b/include/linux/jz4740-adc.h
|
|
new file mode 100644
|
|
index 0000000..59cfe63
|
|
--- /dev/null
|
|
+++ b/include/linux/jz4740-adc.h
|
|
@@ -0,0 +1,25 @@
|
|
+
|
|
+#ifndef __LINUX_JZ4740_ADC
|
|
+#define __LINUX_JZ4740_ADC
|
|
+
|
|
+#include <linux/device.h>
|
|
+
|
|
+enum jz_adc_battery_scale {
|
|
+ JZ_ADC_BATTERY_SCALE_2V5, /* Mesures voltages up to 2.5V */
|
|
+ JZ_ADC_BATTERY_SCALE_7V5, /* Mesures voltages up to 7.5V */
|
|
+};
|
|
+
|
|
+/*
|
|
+ * jz4740_adc_read_battery_voltage - Read battery voltage from the ADC PBAT pin
|
|
+ * @dev: Pointer to a jz4740-adc device
|
|
+ * @scale: Whether to use 2.5V or 7.5V scale
|
|
+ *
|
|
+ * Returns: Battery voltage in mircovolts
|
|
+ *
|
|
+ * Context: Process
|
|
+*/
|
|
+long jz4740_adc_read_battery_voltage(struct device *dev,
|
|
+ enum jz_adc_battery_scale scale);
|
|
+
|
|
+
|
|
+#endif
|
|
--
|
|
1.5.6.5
|
|
|