mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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e2813918b9
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17665 3c298f89-4303-0410-b956-a3cf2f4a3e73
148 lines
8.2 KiB
C
148 lines
8.2 KiB
C
/*
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* Copyright (c) 2004-2007 Atheros Communications Inc.
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* All rights reserved.
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*
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* $ATH_LICENSE_HOSTSDK0_C$
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*
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* This file contains the definitions for AR6001 registers
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* that may be directly manipulated by Host software.
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*/
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#ifndef __AR6KHWREG_H__
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#define __AR6KHWREG_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Host registers */
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#define HOST_INT_STATUS_ADDRESS 0x00000400
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#define CPU_INT_STATUS_ADDRESS 0x00000401
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#define ERROR_INT_STATUS_ADDRESS 0x00000402
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#define INT_STATUS_ENABLE_ADDRESS 0x00000418
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#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
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#define COUNT_ADDRESS 0x00000420
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#define COUNT_DEC_ADDRESS 0x00000440
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#define WINDOW_DATA_ADDRESS 0x00000474
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#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
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#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
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/* Target addresses */
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#define RESET_CONTROL_ADDRESS 0x0c000000
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#define MC_REMAP_VALID_ADDRESS 0x0c004080
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#define MC_REMAP_SIZE_ADDRESS 0x0c004100
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#define MC_REMAP_COMPARE_ADDRESS 0x0c004180
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#define MC_REMAP_TARGET_ADDRESS 0x0c004200
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#define LOCAL_COUNT_ADDRESS 0x0c014080
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#define LOCAL_SCRATCH_ADDRESS 0x0c0140c0
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#define INT_STATUS_ENABLE_ERROR_MSB 7
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#define INT_STATUS_ENABLE_ERROR_LSB 7
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#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
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#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
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#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
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#define INT_STATUS_ENABLE_CPU_MSB 6
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#define INT_STATUS_ENABLE_CPU_LSB 6
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#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
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#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
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#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
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#define INT_STATUS_ENABLE_COUNTER_MSB 4
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#define INT_STATUS_ENABLE_COUNTER_LSB 4
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#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
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#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
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#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
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#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
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#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
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#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
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#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
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#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
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#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
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#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
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#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
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#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
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#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
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#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
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#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
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#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
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#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
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#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
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#define ERROR_INT_STATUS_WAKEUP_MSB 2
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#define ERROR_INT_STATUS_WAKEUP_LSB 2
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#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
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#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
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#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
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#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
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#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
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#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
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#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
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#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
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#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
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#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
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#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
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#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
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#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
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#define HOST_INT_STATUS_ERROR_MSB 7
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#define HOST_INT_STATUS_ERROR_LSB 7
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#define HOST_INT_STATUS_ERROR_MASK 0x00000080
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#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
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#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
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#define HOST_INT_STATUS_CPU_MSB 6
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#define HOST_INT_STATUS_CPU_LSB 6
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#define HOST_INT_STATUS_CPU_MASK 0x00000040
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#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
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#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
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#define HOST_INT_STATUS_COUNTER_MSB 4
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#define HOST_INT_STATUS_COUNTER_LSB 4
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#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
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#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
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#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
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#define RESET_CONTROL_WARM_RST_MSB 7
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#define RESET_CONTROL_WARM_RST_LSB 7
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#define RESET_CONTROL_WARM_RST_MASK 0x00000080
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#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
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#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
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#define RESET_CONTROL_COLD_RST_MSB 8
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#define RESET_CONTROL_COLD_RST_LSB 8
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#define RESET_CONTROL_COLD_RST_MASK 0x00000100
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#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
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#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
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#define RESET_CAUSE_LAST_MSB 2
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#define RESET_CAUSE_LAST_LSB 0
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#define RESET_CAUSE_LAST_MASK 0x00000007
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#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
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#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AR6KHWREG_H__ */
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