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2048e10433
This adds u-boot for nbg460n ar71xx target, as it is required as second stage bootloader. Signed-off-by: Michael Kurz <michi.kurz@googlemail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24418 3c298f89-4303-0410-b956-a3cf2f4a3e73
137 lines
4.3 KiB
C
137 lines
4.3 KiB
C
/*
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* (C) Copyright 2010
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* Michael Kurz <michi.kurz@googlemail.com>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This file contains the configuration parameters for the zyxel nbg460n board. */
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#ifndef _NBG460N_CONFIG_H
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#define _NBG460N_CONFIG_H
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#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_AR71XX 1
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#define CONFIG_AR91XX 1
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
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/* Cache Configuration */
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_ICACHE_SIZE 65536
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/* Cache lock for stack */
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#define CONFIG_SYS_INIT_SP_OFFSET 0x1000
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#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200}
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#define CONFIG_MISC_INIT_R
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/* SPI-Flash support */
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#define CONFIG_SPI_FLASH
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#define CONFIG_AR71XX_SPI
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#define CONFIG_SPI_FLASH_MACRONIX
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#define CONFIG_SF_DEFAULT_HZ 25000000
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#define CONFIG_ENV_SPI_MAX_HZ 25000000
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_ADDR 0xbfc20000
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#define CONFIG_ENV_OFFSET 0x20000
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#define CONFIG_ENV_SIZE 0x01000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 64
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#define CONFIG_SYS_FLASH_BASE 0xbfc00000
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/* Net support */
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#define CONFIG_ETHADDR_ADDR 0xbfc0fff8
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_AG71XX
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#define CONFIG_AG71XX_PORTS { 1, 1 }
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#define CONFIG_AG71XX_MII0_IIF MII0_CTRL_IF_RGMII
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#define CONFIG_AG71XX_MII1_IIF MII1_CTRL_IF_RGMII
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#define CONFIG_NET_MULTI
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#define CONFIG_IPADDR 192.168.1.254
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#define CONFIG_SERVERIP 192.168.1.42
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/* Switch support */
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#define CONFIG_MII
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#define CONFIG_RTL8366_MII
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#define RTL8366_PIN_SDA 16
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#define RTL8366_PIN_SCK 18
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#define MII_GPIOINCLUDE <asm/ar71xx_gpio.h>
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#define MII_SETSDA(x) ar71xx_setpin(RTL8366_PIN_SDA, x)
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#define MII_GETSDA ar71xx_getpin(RTL8366_PIN_SDA)
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#define MII_SETSCK(x) ar71xx_setpin(RTL8366_PIN_SCK, x)
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#define MII_SDAINPUT ar71xx_setpindir(RTL8366_PIN_SDA, 0)
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#define MII_SDAOUTPUT ar71xx_setpindir(RTL8366_PIN_SDA, 1)
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#define MII_SCKINPUT ar71xx_setpindir(RTL8366_PIN_SCK, 0)
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#define MII_SCKOUTPUT ar71xx_setpindir(RTL8366_PIN_SCK, 1)
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttyS0,115200 rootfstype==squashfs,jffs2 noinitrd machtype=NBG460N"
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#define CONFIG_BOOTCOMMAND "bootm 0xbfc70000"
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#define CONFIG_LZMA
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/* Commands */
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#define CONFIG_SYS_NO_FLASH
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SPI
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * 0x10000 + 128*1024, 0x1000)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
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#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
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#define CONFIG_SYS_LOAD_ADDR 0x80060000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x80000800
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#define CONFIG_SYS_MEMTEST_END 0x81E00000
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#endif /* _NBG460N_CONFIG_H */
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