mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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796a9d1091
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15242 3c298f89-4303-0410-b956-a3cf2f4a3e73
508 lines
14 KiB
C
508 lines
14 KiB
C
/*
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* pcicfg.h: PCI configuration constants and structures.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _h_pcicfg_
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#define _h_pcicfg_
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/* The following inside ifndef's so we don't collide with NTDDK.H */
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#ifndef PCI_MAX_BUS
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#define PCI_MAX_BUS 0x100
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#endif
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#ifndef PCI_MAX_DEVICES
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#define PCI_MAX_DEVICES 0x20
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#endif
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#ifndef PCI_MAX_FUNCTION
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#define PCI_MAX_FUNCTION 0x8
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#endif
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#ifndef PCI_INVALID_VENDORID
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#define PCI_INVALID_VENDORID 0xffff
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#endif
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#ifndef PCI_INVALID_DEVICEID
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#define PCI_INVALID_DEVICEID 0xffff
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#endif
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/* Convert between bus-slot-function-register and config addresses */
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#define PCICFG_BUS_SHIFT 16 /* Bus shift */
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#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
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#define PCICFG_FUN_SHIFT 8 /* Function shift */
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#define PCICFG_OFF_SHIFT 0 /* Register shift */
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#define PCICFG_BUS_MASK 0xff /* Bus mask */
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#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
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#define PCICFG_FUN_MASK 7 /* Function mask */
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#define PCICFG_OFF_MASK 0xff /* Bus mask */
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#define PCI_CONFIG_ADDR(b, s, f, o) \
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((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
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| (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
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| (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
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| (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
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#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
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#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
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#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
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#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
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/* PCIE Config space accessing MACROS */
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#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
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#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
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#define PCIECFG_FUN_SHIFT 16 /* Function shift */
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#define PCIECFG_OFF_SHIFT 0 /* Register shift */
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#define PCIECFG_BUS_MASK 0xff /* Bus mask */
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#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
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#define PCIECFG_FUN_MASK 7 /* Function mask */
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#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
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#define PCIE_CONFIG_ADDR(b, s, f, o) \
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((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
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| (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
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| (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
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| (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
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#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
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#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
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#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
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#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
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/* The actual config space */
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#define PCI_BAR_MAX 6
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#define PCI_ROM_BAR 8
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#define PCR_RSVDA_MAX 2
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/* Bits in PCI bars' flags */
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#define PCIBAR_FLAGS 0xf
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#define PCIBAR_IO 0x1
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#define PCIBAR_MEM1M 0x2
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#define PCIBAR_MEM64 0x4
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#define PCIBAR_PREFETCH 0x8
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#define PCIBAR_MEM32_MASK 0xFFFFFF80
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/* pci config status reg has a bit to indicate that capability ptr is present */
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#define PCI_CAPPTR_PRESENT 0x0010
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typedef struct _pci_config_regs {
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unsigned short vendor;
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unsigned short device;
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unsigned short command;
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unsigned short status;
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unsigned char rev_id;
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unsigned char prog_if;
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unsigned char sub_class;
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unsigned char base_class;
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unsigned char cache_line_size;
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unsigned char latency_timer;
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unsigned char header_type;
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unsigned char bist;
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unsigned long base[PCI_BAR_MAX];
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unsigned long cardbus_cis;
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unsigned short subsys_vendor;
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unsigned short subsys_id;
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unsigned long baserom;
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unsigned long rsvd_a[PCR_RSVDA_MAX];
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unsigned char int_line;
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unsigned char int_pin;
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unsigned char min_gnt;
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unsigned char max_lat;
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unsigned char dev_dep[192];
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} pci_config_regs;
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#define SZPCR (sizeof (pci_config_regs))
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#define MINSZPCR 64 /* offsetof (dev_dep[0] */
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/* A structure for the config registers is nice, but in most
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* systems the config space is not memory mapped, so we need
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* filed offsetts. :-(
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*/
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#define PCI_CFG_VID 0
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#define PCI_CFG_DID 2
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#define PCI_CFG_CMD 4
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#define PCI_CFG_STAT 6
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#define PCI_CFG_REV 8
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#define PCI_CFG_PROGIF 9
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#define PCI_CFG_SUBCL 0xa
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#define PCI_CFG_BASECL 0xb
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#define PCI_CFG_CLSZ 0xc
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#define PCI_CFG_LATTIM 0xd
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#define PCI_CFG_HDR 0xe
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#define PCI_CFG_BIST 0xf
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#define PCI_CFG_BAR0 0x10
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#define PCI_CFG_BAR1 0x14
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#define PCI_CFG_BAR2 0x18
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#define PCI_CFG_BAR3 0x1c
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#define PCI_CFG_BAR4 0x20
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#define PCI_CFG_BAR5 0x24
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#define PCI_CFG_CIS 0x28
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#define PCI_CFG_SVID 0x2c
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#define PCI_CFG_SSID 0x2e
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#define PCI_CFG_ROMBAR 0x30
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#define PCI_CFG_CAPPTR 0x34
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#define PCI_CFG_INT 0x3c
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#define PCI_CFG_PIN 0x3d
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#define PCI_CFG_MINGNT 0x3e
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#define PCI_CFG_MAXLAT 0x3f
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#ifdef __NetBSD__
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#undef PCI_CLASS_DISPLAY
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#undef PCI_CLASS_MEMORY
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#undef PCI_CLASS_BRIDGE
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#undef PCI_CLASS_INPUT
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#undef PCI_CLASS_DOCK
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#endif /* __NetBSD__ */
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#ifdef EFI
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#undef PCI_CLASS_BRIDGE
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#undef PCI_CLASS_OLD
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#undef PCI_CLASS_DISPLAY
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#undef PCI_CLASS_SERIAL
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#undef PCI_CLASS_SATELLITE
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#endif /* EFI */
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/* Classes and subclasses */
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typedef enum {
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PCI_CLASS_OLD = 0,
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PCI_CLASS_DASDI,
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PCI_CLASS_NET,
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PCI_CLASS_DISPLAY,
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PCI_CLASS_MMEDIA,
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PCI_CLASS_MEMORY,
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PCI_CLASS_BRIDGE,
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PCI_CLASS_COMM,
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PCI_CLASS_BASE,
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PCI_CLASS_INPUT,
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PCI_CLASS_DOCK,
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PCI_CLASS_CPU,
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PCI_CLASS_SERIAL,
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PCI_CLASS_INTELLIGENT = 0xe,
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PCI_CLASS_SATELLITE,
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PCI_CLASS_CRYPT,
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PCI_CLASS_DSP,
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PCI_CLASS_XOR = 0xfe
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} pci_classes;
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typedef enum {
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PCI_DASDI_SCSI,
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PCI_DASDI_IDE,
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PCI_DASDI_FLOPPY,
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PCI_DASDI_IPI,
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PCI_DASDI_RAID,
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PCI_DASDI_OTHER = 0x80
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} pci_dasdi_subclasses;
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typedef enum {
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PCI_NET_ETHER,
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PCI_NET_TOKEN,
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PCI_NET_FDDI,
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PCI_NET_ATM,
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PCI_NET_OTHER = 0x80
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} pci_net_subclasses;
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typedef enum {
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PCI_DISPLAY_VGA,
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PCI_DISPLAY_XGA,
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PCI_DISPLAY_3D,
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PCI_DISPLAY_OTHER = 0x80
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} pci_display_subclasses;
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typedef enum {
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PCI_MMEDIA_VIDEO,
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PCI_MMEDIA_AUDIO,
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PCI_MMEDIA_PHONE,
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PCI_MEDIA_OTHER = 0x80
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} pci_mmedia_subclasses;
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typedef enum {
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PCI_MEMORY_RAM,
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PCI_MEMORY_FLASH,
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PCI_MEMORY_OTHER = 0x80
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} pci_memory_subclasses;
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typedef enum {
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PCI_BRIDGE_HOST,
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PCI_BRIDGE_ISA,
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PCI_BRIDGE_EISA,
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PCI_BRIDGE_MC,
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PCI_BRIDGE_PCI,
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PCI_BRIDGE_PCMCIA,
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PCI_BRIDGE_NUBUS,
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PCI_BRIDGE_CARDBUS,
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PCI_BRIDGE_RACEWAY,
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PCI_BRIDGE_OTHER = 0x80
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} pci_bridge_subclasses;
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typedef enum {
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PCI_COMM_UART,
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PCI_COMM_PARALLEL,
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PCI_COMM_MULTIUART,
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PCI_COMM_MODEM,
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PCI_COMM_OTHER = 0x80
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} pci_comm_subclasses;
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typedef enum {
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PCI_BASE_PIC,
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PCI_BASE_DMA,
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PCI_BASE_TIMER,
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PCI_BASE_RTC,
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PCI_BASE_PCI_HOTPLUG,
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PCI_BASE_OTHER = 0x80
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} pci_base_subclasses;
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typedef enum {
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PCI_INPUT_KBD,
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PCI_INPUT_PEN,
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PCI_INPUT_MOUSE,
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PCI_INPUT_SCANNER,
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PCI_INPUT_GAMEPORT,
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PCI_INPUT_OTHER = 0x80
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} pci_input_subclasses;
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typedef enum {
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PCI_DOCK_GENERIC,
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PCI_DOCK_OTHER = 0x80
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} pci_dock_subclasses;
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typedef enum {
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PCI_CPU_386,
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PCI_CPU_486,
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PCI_CPU_PENTIUM,
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PCI_CPU_ALPHA = 0x10,
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PCI_CPU_POWERPC = 0x20,
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PCI_CPU_MIPS = 0x30,
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PCI_CPU_COPROC = 0x40,
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PCI_CPU_OTHER = 0x80
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} pci_cpu_subclasses;
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typedef enum {
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PCI_SERIAL_IEEE1394,
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PCI_SERIAL_ACCESS,
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PCI_SERIAL_SSA,
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PCI_SERIAL_USB,
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PCI_SERIAL_FIBER,
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PCI_SERIAL_SMBUS,
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PCI_SERIAL_OTHER = 0x80
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} pci_serial_subclasses;
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typedef enum {
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PCI_INTELLIGENT_I2O
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} pci_intelligent_subclasses;
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typedef enum {
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PCI_SATELLITE_TV,
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PCI_SATELLITE_AUDIO,
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PCI_SATELLITE_VOICE,
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PCI_SATELLITE_DATA,
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PCI_SATELLITE_OTHER = 0x80
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} pci_satellite_subclasses;
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typedef enum {
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PCI_CRYPT_NETWORK,
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PCI_CRYPT_ENTERTAINMENT,
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PCI_CRYPT_OTHER = 0x80
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} pci_crypt_subclasses;
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typedef enum {
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PCI_DSP_DPIO,
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PCI_DSP_OTHER = 0x80
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} pci_dsp_subclasses;
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typedef enum {
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PCI_XOR_QDMA,
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PCI_XOR_OTHER = 0x80
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} pci_xor_subclasses;
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/* Header types */
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typedef enum {
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PCI_HEADER_NORMAL,
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PCI_HEADER_BRIDGE,
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PCI_HEADER_CARDBUS
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} pci_header_types;
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/* Overlay for a PCI-to-PCI bridge */
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#define PPB_RSVDA_MAX 2
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#define PPB_RSVDD_MAX 8
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typedef struct _ppb_config_regs {
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unsigned short vendor;
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unsigned short device;
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unsigned short command;
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unsigned short status;
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unsigned char rev_id;
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unsigned char prog_if;
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unsigned char sub_class;
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unsigned char base_class;
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unsigned char cache_line_size;
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unsigned char latency_timer;
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unsigned char header_type;
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unsigned char bist;
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unsigned long rsvd_a[PPB_RSVDA_MAX];
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unsigned char prim_bus;
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unsigned char sec_bus;
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unsigned char sub_bus;
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unsigned char sec_lat;
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unsigned char io_base;
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unsigned char io_lim;
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unsigned short sec_status;
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unsigned short mem_base;
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unsigned short mem_lim;
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unsigned short pf_mem_base;
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unsigned short pf_mem_lim;
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unsigned long pf_mem_base_hi;
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unsigned long pf_mem_lim_hi;
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unsigned short io_base_hi;
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unsigned short io_lim_hi;
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unsigned short subsys_vendor;
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unsigned short subsys_id;
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unsigned long rsvd_b;
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unsigned char rsvd_c;
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unsigned char int_pin;
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unsigned short bridge_ctrl;
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unsigned char chip_ctrl;
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unsigned char diag_ctrl;
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unsigned short arb_ctrl;
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unsigned long rsvd_d[PPB_RSVDD_MAX];
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unsigned char dev_dep[192];
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} ppb_config_regs;
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/* PCI CAPABILITY DEFINES */
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#define PCI_CAP_POWERMGMTCAP_ID 0x01
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#define PCI_CAP_MSICAP_ID 0x05
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#define PCI_CAP_PCIECAP_ID 0x10
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/* Data structure to define the Message Signalled Interrupt facility
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* Valid for PCI and PCIE configurations
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*/
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typedef struct _pciconfig_cap_msi {
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unsigned char capID;
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unsigned char nextptr;
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unsigned short msgctrl;
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unsigned int msgaddr;
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} pciconfig_cap_msi;
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/* Data structure to define the Power managment facility
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* Valid for PCI and PCIE configurations
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*/
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typedef struct _pciconfig_cap_pwrmgmt {
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unsigned char capID;
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unsigned char nextptr;
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unsigned short pme_cap;
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unsigned short pme_sts_ctrl;
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unsigned char pme_bridge_ext;
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unsigned char data;
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} pciconfig_cap_pwrmgmt;
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#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
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#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
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#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
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#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
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/* Data structure to define the PCIE capability */
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typedef struct _pciconfig_cap_pcie {
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unsigned char capID;
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unsigned char nextptr;
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unsigned short pcie_cap;
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unsigned int dev_cap;
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unsigned short dev_ctrl;
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unsigned short dev_status;
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unsigned int link_cap;
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unsigned short link_ctrl;
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unsigned short link_status;
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} pciconfig_cap_pcie;
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/* PCIE Enhanced CAPABILITY DEFINES */
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#define PCIE_EXTCFG_OFFSET 0x100
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#define PCIE_ADVERRREP_CAPID 0x0001
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#define PCIE_VC_CAPID 0x0002
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#define PCIE_DEVSNUM_CAPID 0x0003
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#define PCIE_PWRBUDGET_CAPID 0x0004
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/* Header to define the PCIE specific capabilities in the extended config space */
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typedef struct _pcie_enhanced_caphdr {
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unsigned short capID;
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unsigned short cap_ver : 4;
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unsigned short next_ptr : 12;
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} pcie_enhanced_caphdr;
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/* Everything below is BRCM HND proprietary */
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/* Brcm PCI configuration registers */
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#define cap_list rsvd_a[0]
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#define bar0_window dev_dep[0x80 - 0x40]
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#define bar1_window dev_dep[0x84 - 0x40]
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#define sprom_control dev_dep[0x88 - 0x40]
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#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
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#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
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#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
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#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
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#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
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#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
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#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
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#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
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#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
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#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
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#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
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#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
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#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
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#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
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#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
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#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
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* 8KB window, so their address is the "regular"
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* address plus 4K
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*/
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#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
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/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
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#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
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#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
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#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
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/* PCI_INT_STATUS */
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#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
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/* PCI_INT_MASK */
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#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
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#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
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#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
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/* PCI_SPROM_CONTROL */
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#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
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#define SPROM_LOCKED 0x08 /* SPROM Locked */
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#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
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#define SPROM_WRITEEN 0x10 /* SPROM write enable */
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#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
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#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
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#define SPROM_SIZE 256 /* sprom size in 16-bit */
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#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
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/* PCI_CFG_CMD_STAT */
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#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
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#endif /* _h_pcicfg_ */
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