mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13291 3c298f89-4303-0410-b956-a3cf2f4a3e73
209 lines
4.7 KiB
C
209 lines
4.7 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/addrspace.h>
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#include <asm/danube.h>
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#ifdef DANUBE_USE_DDR_RAM
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long int initdram(int board_type)
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{
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return (1024*1024*DANUBE_DDR_RAM_SIZE);
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}
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#else
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extern uint danube_get_cpuclk(void);
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static ulong max_sdram_size(void) /* per Chip Select */
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{
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/* The only supported SDRAM data width is 16bit.
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*/
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#define CFG_DW 4
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/* The only supported number of SDRAM banks is 4.
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*/
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#define CFG_NB 4
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ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
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int cols = cfgpb0 & 0xF;
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int rows = (cfgpb0 & 0xF0) >> 4;
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ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
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return size;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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static long int dram_size(long int *base, long int maxsize)
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{
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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long int initdram(int board_type)
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{
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int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
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ulong size, max_size = 0;
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ulong our_address;
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/* load t9 into our_address */
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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* find out whether running from DRAM or Flash.
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*/
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if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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for (cols = 0x8; cols <= 0xC; cols++)
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{
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for (rows = 0xB; rows <= 0xD; rows++)
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{
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*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
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(rows << 4) | cols;
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size = dram_size((ulong *)CFG_SDRAM_BASE,
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max_sdram_size());
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if (size > max_size)
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{
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best_val = *DANUBE_SDRAM_MC_CFGPB0;
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max_size = size;
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}
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}
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}
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*DANUBE_SDRAM_MC_CFGPB0 = best_val;
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return max_size;
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}
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#endif
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int checkboard (void)
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{
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/* No such register in Amazon */
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#if 0
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unsigned long chipid = *AMAZON_MCD_CHIPID;
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int part_num;
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puts ("Board: AMAZON ");
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part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
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switch (part_num) {
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case AMAZON_CHIPID_STANDARD:
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printf ("Standard Version, ");
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break;
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case AMAZON_CHIPID_YANGTSE:
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printf ("Yangtse Version, ");
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break;
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default:
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printf ("Unknown Part Number 0x%x ", part_num);
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break;
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}
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printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid));
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printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000);
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#endif
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return 0;
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}
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/*
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* Disk On Chip (NAND) Millenium initialization.
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* The NAND lives in the CS2* space
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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extern void
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nand_probe(ulong physadr);
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#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
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void
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nand_init(void)
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{
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int devtype;
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/* Configure EBU */
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//TODO: should we keep this?
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//Set GPIO23 to be Flash CS1;
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*DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7);
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*DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7);
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*DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ;
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*DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ;
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*EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31;
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/* byte swap;minimum delay*/
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*EBU_CON_1 = 0x40C155;
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*EBU_NAND_CON = 0x000005F3;
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/* Set bus signals to inactive */
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NAND_READY_CLEAR;
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NAND_CE_CLEAR;
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nand_probe(NAND_BASE_ADDRESS);
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//nand_probe(AT91_SMARTMEDIA_BASE);
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}
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#endif
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