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git://projects.qi-hardware.com/openwrt-xburst.git
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151 lines
3.1 KiB
C
151 lines
3.1 KiB
C
/*
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* linux/arch/mips/jz4740/irq.c
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*
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* JZ4740 interrupt routines.
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*
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* Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
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* Author: <lhhuang@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/jzsoc.h>
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static void __iomem *jz_intc_base;
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#define JZ_REG_BASE_INTC 0x10001000
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#define JZ_REG_INTC_STATUS 0x00
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#define JZ_REG_INTC_MASK 0x04
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#define JZ_REG_INTC_SET_MASK 0x08
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#define JZ_REG_INTC_CLEAR_MASK 0x0c
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#define JZ_REG_INTC_PENDING 0x10
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/*
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* INTC irq type
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*/
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static void intc_irq_unmask(unsigned int irq)
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{
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writel(BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
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}
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static void intc_irq_mask(unsigned int irq)
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{
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writel(BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
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}
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static void intc_irq_ack(unsigned int irq)
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{
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writel(BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
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}
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static void intc_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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intc_irq_unmask(irq);
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}
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}
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static struct irq_chip intc_irq_type = {
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.name = "INTC",
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.mask = intc_irq_mask,
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.unmask = intc_irq_unmask,
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.ack = intc_irq_ack,
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.end = intc_irq_end,
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};
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/*
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* DMA irq type
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*/
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static void enable_dma_irq(unsigned int irq)
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{
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__intc_unmask_irq(IRQ_DMAC);
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__dmac_channel_enable_irq(irq - IRQ_DMA_0);
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}
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static void disable_dma_irq(unsigned int irq)
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{
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__dmac_channel_disable_irq(irq - IRQ_DMA_0);
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}
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static void mask_and_ack_dma_irq(unsigned int irq)
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{
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__intc_ack_irq(IRQ_DMAC);
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__dmac_channel_disable_irq(irq - IRQ_DMA_0);
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}
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static void end_dma_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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enable_dma_irq(irq);
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}
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}
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static struct irq_chip dma_irq_type = {
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.name = "DMA",
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.unmask = enable_dma_irq,
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.mask = disable_dma_irq,
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.ack = mask_and_ack_dma_irq,
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.end = end_dma_irq,
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};
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//----------------------------------------------------------------------
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void __init arch_init_irq(void)
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{
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int i;
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clear_c0_status(0xff04); /* clear ERL */
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set_c0_status(0x0400); /* set IP2 */
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jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
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for (i = 0; i < 32; i++) {
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intc_irq_mask(i);
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set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
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}
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/* Set up DMAC irq
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*/
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for (i = 0; i < NUM_DMA; i++) {
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disable_dma_irq(IRQ_DMA_0 + i);
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set_irq_chip_and_handler(IRQ_DMA_0 + i, &dma_irq_type, handle_level_irq);
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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uint32_t irq_reg;
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irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
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if (irq_reg)
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do_IRQ(ffs(irq_reg) - 1);
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}
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