mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 18:58:37 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@28721 3c298f89-4303-0410-b956-a3cf2f4a3e73
891 lines
22 KiB
Diff
891 lines
22 KiB
Diff
From 6437f41dfdf9475178e22ab0dd886af033f90cc2 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 29 Sep 2011 21:10:16 +0200
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Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
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---
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arch/mips/lantiq/falcon/devices.c | 21 +
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arch/mips/lantiq/falcon/devices.h | 1 +
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drivers/i2c/busses/Kconfig | 4 +
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drivers/i2c/busses/Makefile | 1 +
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drivers/i2c/busses/i2c-falcon.c | 815 +++++++++++++++++++++++++++++++++++++
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5 files changed, 842 insertions(+), 0 deletions(-)
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create mode 100644 drivers/i2c/busses/i2c-falcon.c
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--- a/arch/mips/lantiq/falcon/devices.c
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+++ b/arch/mips/lantiq/falcon/devices.c
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@@ -126,3 +126,24 @@ falcon_register_gpio_extra(void)
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ltq_sysctl_activate(SYSCTL_SYS1,
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ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
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}
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+
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+/* i2c */
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+static struct resource falcon_i2c_resources[] = {
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+ MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
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+ IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
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+ IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
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+ IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
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+ IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
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+};
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+
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+void __init falcon_register_i2c(void)
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+{
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+ platform_device_register_simple("i2c-falcon", 0,
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+ falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
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+ sys1_hw_activate(ACTS_I2C_ACT);
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+}
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+
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+void __init falcon_register_crypto(void)
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+{
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+ platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
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+}
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--- a/arch/mips/lantiq/falcon/devices.h
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+++ b/arch/mips/lantiq/falcon/devices.h
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@@ -16,5 +16,6 @@
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extern void falcon_register_nand(void);
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extern void falcon_register_gpio(void);
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extern void falcon_register_gpio_extra(void);
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+extern void falcon_register_i2c(void);
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#endif
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--- a/drivers/i2c/busses/Kconfig
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+++ b/drivers/i2c/busses/Kconfig
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@@ -284,6 +284,10 @@ config I2C_POWERMAC
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comment "I2C system bus drivers (mostly embedded / system-on-chip)"
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+config I2C_FALCON
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+ tristate "Falcon I2C interface"
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+# depends on SOC_FALCON
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+
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config I2C_AT91
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tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
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depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
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--- a/drivers/i2c/busses/Makefile
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+++ b/drivers/i2c/busses/Makefile
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@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
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obj-$(CONFIG_I2C_STUB) += i2c-stub.o
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obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
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obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
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+obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o
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ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
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--- /dev/null
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+++ b/drivers/i2c/busses/i2c-falcon.c
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@@ -0,0 +1,815 @@
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+/*
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+ * Lantiq FALC(tm) ON - I2C bus adapter
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+ *
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+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+ */
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+
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+/* #define DEBUG */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/delay.h>
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+#include <linux/slab.h> /* for kzalloc, kfree */
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+#include <linux/i2c.h>
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+#include <linux/clk.h>
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+#include <linux/errno.h>
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+#include <linux/sched.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/platform_device.h>
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+#include <linux/io.h>
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+#include <linux/gpio.h>
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+
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+#include <falcon/lantiq_soc.h>
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+
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+/* CURRENT ISSUES:
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+ * - no high speed support
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+ * - supports only master mode
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+ * - ten bit mode is not tested (no slave devices)
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+ */
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+
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+/* mapping for access macros */
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+#define reg_r32(reg) __raw_readl(reg)
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+#define reg_w32(val, reg) __raw_writel(val, reg)
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+#define reg_w32_mask(clear, set, reg) \
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+ reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
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+#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)®)[idx])
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+#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)®)[idx])
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+#define i2c (priv->membase)
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+#include <falcon/i2c_reg.h>
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+
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+#define DRV_NAME "i2c-falcon"
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+#define DRV_VERSION "1.01"
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+
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+#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */
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+
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+#ifdef DEBUG
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+#define FALCON_I2C_XFER_TIMEOUT 25*HZ
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+#else
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+#define FALCON_I2C_XFER_TIMEOUT HZ
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+#endif
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+#if defined(DEBUG) && 0
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+#define PRINTK(arg...) printk(arg)
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+#else
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+#define PRINTK(arg...) do {} while (0)
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+#endif
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+
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+#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \
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+ I2C_IMSC_I2C_ERR_INT_EN)
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+
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+#define FALCON_I2C_ARB_LOST (1 << 0)
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+#define FALCON_I2C_NACK (1 << 1)
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+#define FALCON_I2C_RX_UFL (1 << 2)
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+#define FALCON_I2C_RX_OFL (1 << 3)
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+#define FALCON_I2C_TX_UFL (1 << 4)
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+#define FALCON_I2C_TX_OFL (1 << 5)
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+
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+struct falcon_i2c {
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+ struct mutex mutex;
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+
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+ enum {
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+ FALCON_I2C_MODE_100 = 1,
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+ FALCON_I2C_MODE_400 = 2,
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+ FALCON_I2C_MODE_3400 = 3
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+ } mode; /* current speed mode */
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+
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+ struct clk *clk; /* clock input for i2c hardware block */
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+ struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */
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+ int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error,
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+ protocol IRQs */
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+
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+ struct i2c_adapter adap;
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+ struct device *dev;
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+
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+ struct completion cmd_complete;
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+
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+ /* message transfer data */
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+ /* current message */
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+ struct i2c_msg *current_msg;
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+ /* number of messages to handle */
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+ int msgs_num;
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+ /* current buffer */
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+ u8 *msg_buf;
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+ /* remaining length of current buffer */
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+ u32 msg_buf_len;
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+ /* error status of the current transfer */
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+ int msg_err;
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+
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+ /* master status codes */
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+ enum {
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+ STATUS_IDLE,
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+ STATUS_ADDR, /* address phase */
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+ STATUS_WRITE,
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+ STATUS_READ,
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+ STATUS_READ_END,
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+ STATUS_STOP
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+ } status;
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+};
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+
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+static irqreturn_t falcon_i2c_isr(int irq, void *dev_id);
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+
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+static inline void enable_burst_irq(struct falcon_i2c *priv)
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+{
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+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);
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+}
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+static inline void disable_burst_irq(struct falcon_i2c *priv)
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+{
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+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);
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+}
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+
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+static void prepare_msg_send_addr(struct falcon_i2c *priv)
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+{
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+ struct i2c_msg *msg = priv->current_msg;
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+ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */
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+ u16 addr = msg->addr;
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+
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+ /* new i2c_msg */
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+ priv->msg_buf = msg->buf;
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+ priv->msg_buf_len = msg->len;
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+ if (rd)
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+ priv->status = STATUS_READ;
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+ else
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+ priv->status = STATUS_WRITE;
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+
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+ /* send slave address */
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+ if (msg->flags & I2C_M_TEN) {
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+ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);
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+ i2c_w32(addr & 0xff, txd);
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+ } else
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+ i2c_w32((addr & 0x7f) << 1 | rd, txd);
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+}
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+
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+static void set_tx_len(struct falcon_i2c *priv)
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+{
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+ struct i2c_msg *msg = priv->current_msg;
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+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1;
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+
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+ PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD)?'R':'T');
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+
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+ priv->status = STATUS_ADDR;
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+
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+ if (!(msg->flags & I2C_M_RD)) {
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+ len += msg->len;
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+ } else {
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+ /* set maximum received packet size (before rx int!) */
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+ i2c_w32(msg->len, mrps_ctrl);
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+ }
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+ i2c_w32(len, tps_ctrl);
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+ enable_burst_irq(priv);
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+}
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+
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+static int falcon_i2c_hw_init(struct i2c_adapter *adap)
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+{
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+ struct falcon_i2c *priv = i2c_get_adapdata(adap);
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+
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+ /* disable bus */
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+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
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+
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+#ifndef DEBUG
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+ /* set normal operation clock divider */
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+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);
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+#else
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+ /* for debugging a higher divider value! */
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+ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);
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+#endif
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+
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+ /* set frequency */
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+ if (priv->mode == FALCON_I2C_MODE_100) {
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+ dev_dbg(priv->dev, "set standard mode (100 kHz)\n");
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+ i2c_w32(0, fdiv_high_cfg);
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+ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
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+ (499 << I2C_FDIV_CFG_DEC_OFFSET),
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+ fdiv_cfg);
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+ } else if (priv->mode == FALCON_I2C_MODE_400) {
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+ dev_dbg(priv->dev, "set fast mode (400 kHz)\n");
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+ i2c_w32(0, fdiv_high_cfg);
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+ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) |
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+ (124 << I2C_FDIV_CFG_DEC_OFFSET),
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+ fdiv_cfg);
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+ } else if (priv->mode == FALCON_I2C_MODE_3400) {
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+ dev_dbg(priv->dev, "set high mode (3.4 MHz)\n");
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+ i2c_w32(0, fdiv_cfg);
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+ /* TODO recalculate value for 100MHz input */
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+ i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) |
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+ (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET),
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+ fdiv_high_cfg);
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+ } else {
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+ dev_warn(priv->dev, "unknown mode\n");
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+ return -ENODEV;
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+ }
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+
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+ /* configure fifo */
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+ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */
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+ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */
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+ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */
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+ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */
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+ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */
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+ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */
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+ fifo_cfg);
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+
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+ /* configure address */
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+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in the
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+ fifo */
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+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */
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+ I2C_ADDR_CFG_MnS_EN | /* we are master device */
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+ 0, /* our slave address (not used!) */
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+ addr_cfg);
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+
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+ /* enable bus */
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+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);
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+
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+ return 0;
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+}
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+
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+static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv)
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+{
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+ int timeout = FALCON_I2C_BUSY_TIMEOUT;
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+
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+ while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK)
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+ != I2C_BUS_STAT_BS_FREE) {
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+ if (timeout <= 0) {
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+ dev_warn(priv->dev, "timeout waiting for bus ready\n");
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+ return -ETIMEDOUT;
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+ }
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+ timeout--;
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+ mdelay(1);
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+ }
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+
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+ return 0;
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+}
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+
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+static void falcon_i2c_tx(struct falcon_i2c *priv, int last)
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+{
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+ if (priv->msg_buf_len && priv->msg_buf) {
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+ i2c_w32(*priv->msg_buf, txd);
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+
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+ if (--priv->msg_buf_len)
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+ priv->msg_buf++;
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+ else
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+ priv->msg_buf = NULL;
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+ } else
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+ last = 1;
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+
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+ if (last) {
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+ disable_burst_irq(priv);
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+ }
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+}
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+
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+static void falcon_i2c_rx(struct falcon_i2c *priv, int last)
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+{
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+ u32 fifo_stat,timeout;
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+ if (priv->msg_buf_len && priv->msg_buf) {
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+ timeout = 5000000;
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+ do {
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+ fifo_stat = i2c_r32(ffs_stat);
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+ } while (!fifo_stat && --timeout);
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+ if (!timeout) {
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+ last = 1;
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+ PRINTK("\nrx timeout\n");
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+ goto err;
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+ }
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+ while (fifo_stat) {
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+ *priv->msg_buf = i2c_r32(rxd);
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+ if (--priv->msg_buf_len)
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+ priv->msg_buf++;
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+ else {
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+ priv->msg_buf = NULL;
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+ last = 1;
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+ break;
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+ }
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+ #if 0
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+ fifo_stat = i2c_r32(ffs_stat);
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+ #else
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+ /* do not read more than burst size, otherwise no "last
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+ burst" is generated and the transaction is blocked! */
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+ fifo_stat = 0;
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+ #endif
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+ }
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+ } else {
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+ last = 1;
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+ }
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+err:
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+ if (last) {
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+ disable_burst_irq(priv);
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+
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+ if (priv->status == STATUS_READ_END) {
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+ /* do the STATUS_STOP and complete() here, as sometimes
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+ the tx_end is already seen before this is finished */
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+ priv->status = STATUS_STOP;
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+ complete(&priv->cmd_complete);
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+ } else {
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+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
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+ priv->status = STATUS_READ_END;
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+ }
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+ }
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+}
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+
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+static void falcon_i2c_xfer_init(struct falcon_i2c *priv)
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+{
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+ /* enable interrupts */
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+ i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc);
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+
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+ /* trigger transfer of first msg */
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+ set_tx_len(priv);
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+}
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+
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+static void dump_msgs(struct i2c_msg msgs[], int num, int rx)
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+{
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+#if defined(DEBUG)
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+ int i, j;
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+ printk("Messages %d %s\n", num, rx ? "out" : "in");
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+ for (i = 0; i < num; i++) {
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+ printk("%2d %cX Msg(%d) addr=0x%X: ", i,
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+ (msgs[i].flags & I2C_M_RD)?'R':'T',
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+ msgs[i].len, msgs[i].addr);
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+ if (!(msgs[i].flags & I2C_M_RD) || rx) {
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+ for (j = 0; j < msgs[i].len; j++)
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+ printk("%02X ", msgs[i].buf[j]);
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+ }
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+ printk("\n");
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+ }
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+#endif
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+}
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+
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+static void falcon_i2c_release_bus(struct falcon_i2c *priv)
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+{
|
|
+ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)
|
|
+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);
|
|
+}
|
|
+
|
|
+static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
|
|
+ int num)
|
|
+{
|
|
+ struct falcon_i2c *priv = i2c_get_adapdata(adap);
|
|
+ int ret;
|
|
+
|
|
+ dev_dbg(priv->dev, "xfer %u messages\n", num);
|
|
+ dump_msgs(msgs, num, 0);
|
|
+
|
|
+ mutex_lock(&priv->mutex);
|
|
+
|
|
+ INIT_COMPLETION(priv->cmd_complete);
|
|
+ priv->current_msg = msgs;
|
|
+ priv->msgs_num = num;
|
|
+ priv->msg_err = 0;
|
|
+ priv->status = STATUS_IDLE;
|
|
+
|
|
+ /* wait for the bus to become ready */
|
|
+ ret = falcon_i2c_wait_bus_not_busy(priv);
|
|
+ if (ret)
|
|
+ goto done;
|
|
+
|
|
+ while (priv->msgs_num) {
|
|
+ /* start the transfers */
|
|
+ falcon_i2c_xfer_init(priv);
|
|
+
|
|
+ /* wait for transfers to complete */
|
|
+ ret = wait_for_completion_interruptible_timeout(
|
|
+ &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT);
|
|
+ if (ret == 0) {
|
|
+ dev_err(priv->dev, "controller timed out\n");
|
|
+ falcon_i2c_hw_init(adap);
|
|
+ ret = -ETIMEDOUT;
|
|
+ goto done;
|
|
+ } else if (ret < 0)
|
|
+ goto done;
|
|
+
|
|
+ if (priv->msg_err) {
|
|
+ if (priv->msg_err & FALCON_I2C_NACK)
|
|
+ ret = -ENXIO;
|
|
+ else
|
|
+ ret = -EREMOTEIO;
|
|
+ goto done;
|
|
+ }
|
|
+ if (--priv->msgs_num) {
|
|
+ priv->current_msg++;
|
|
+ }
|
|
+ }
|
|
+ /* no error? */
|
|
+ ret = num;
|
|
+
|
|
+done:
|
|
+ falcon_i2c_release_bus(priv);
|
|
+
|
|
+ mutex_unlock(&priv->mutex);
|
|
+
|
|
+ if (ret>=0)
|
|
+ dump_msgs(msgs, num, 1);
|
|
+
|
|
+ PRINTK("XFER ret %d\n", ret);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id)
|
|
+{
|
|
+ struct falcon_i2c *priv = dev_id;
|
|
+ struct i2c_msg *msg = priv->current_msg;
|
|
+ int last = (irq == priv->irq_lb);
|
|
+
|
|
+ if (last)
|
|
+ PRINTK("LB ");
|
|
+ else
|
|
+ PRINTK("B ");
|
|
+
|
|
+ if (msg->flags & I2C_M_RD) {
|
|
+ switch (priv->status) {
|
|
+ case STATUS_ADDR:
|
|
+ PRINTK("X");
|
|
+ prepare_msg_send_addr(priv);
|
|
+ disable_burst_irq(priv);
|
|
+ break;
|
|
+ case STATUS_READ:
|
|
+ case STATUS_READ_END:
|
|
+ PRINTK("R");
|
|
+ falcon_i2c_rx(priv, last);
|
|
+ break;
|
|
+ default:
|
|
+ disable_burst_irq(priv);
|
|
+ printk("Status R %d\n", priv->status);
|
|
+ break;
|
|
+ }
|
|
+ } else {
|
|
+ switch (priv->status) {
|
|
+ case STATUS_ADDR:
|
|
+ PRINTK("x");
|
|
+ prepare_msg_send_addr(priv);
|
|
+ break;
|
|
+ case STATUS_WRITE:
|
|
+ PRINTK("w");
|
|
+ falcon_i2c_tx(priv, last);
|
|
+ break;
|
|
+ default:
|
|
+ disable_burst_irq(priv);
|
|
+ printk("Status W %d\n", priv->status);
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
|
+static void falcon_i2c_isr_prot(struct falcon_i2c *priv)
|
|
+{
|
|
+ u32 i_pro = i2c_r32(p_irqss);
|
|
+
|
|
+ PRINTK("i2c-p");
|
|
+
|
|
+ /* not acknowledge */
|
|
+ if (i_pro & I2C_P_IRQSS_NACK) {
|
|
+ priv->msg_err |= FALCON_I2C_NACK;
|
|
+ PRINTK(" nack");
|
|
+ }
|
|
+
|
|
+ /* arbitration lost */
|
|
+ if (i_pro & I2C_P_IRQSS_AL) {
|
|
+ priv->msg_err |= FALCON_I2C_ARB_LOST;
|
|
+ PRINTK(" arb-lost");
|
|
+ }
|
|
+ /* tx -> rx switch */
|
|
+ if (i_pro & I2C_P_IRQSS_RX)
|
|
+ PRINTK(" rx");
|
|
+
|
|
+ /* tx end */
|
|
+ if (i_pro & I2C_P_IRQSS_TX_END)
|
|
+ PRINTK(" txend");
|
|
+ PRINTK("\n");
|
|
+
|
|
+ if (!priv->msg_err) {
|
|
+ /* tx -> rx switch */
|
|
+ if (i_pro & I2C_P_IRQSS_RX) {
|
|
+ priv->status = STATUS_READ;
|
|
+ enable_burst_irq(priv);
|
|
+ }
|
|
+ if (i_pro & I2C_P_IRQSS_TX_END) {
|
|
+ if (priv->status == STATUS_READ)
|
|
+ priv->status = STATUS_READ_END;
|
|
+ else {
|
|
+ disable_burst_irq(priv);
|
|
+ priv->status = STATUS_STOP;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ i2c_w32(i_pro, p_irqsc);
|
|
+}
|
|
+
|
|
+static irqreturn_t falcon_i2c_isr(int irq, void *dev_id)
|
|
+{
|
|
+ u32 i_raw, i_err=0;
|
|
+ struct falcon_i2c *priv = dev_id;
|
|
+
|
|
+ i_raw = i2c_r32(mis);
|
|
+ PRINTK("i_raw 0x%08X\n", i_raw);
|
|
+
|
|
+ /* error interrupt */
|
|
+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {
|
|
+ i_err = i2c_r32(err_irqss);
|
|
+ PRINTK("i_err 0x%08X bus_stat 0x%04X\n",
|
|
+ i_err, i2c_r32(bus_stat));
|
|
+
|
|
+ /* tx fifo overflow (8) */
|
|
+ if (i_err & I2C_ERR_IRQSS_TXF_OFL)
|
|
+ priv->msg_err |= FALCON_I2C_TX_OFL;
|
|
+
|
|
+ /* tx fifo underflow (4) */
|
|
+ if (i_err & I2C_ERR_IRQSS_TXF_UFL)
|
|
+ priv->msg_err |= FALCON_I2C_TX_UFL;
|
|
+
|
|
+ /* rx fifo overflow (2) */
|
|
+ if (i_err & I2C_ERR_IRQSS_RXF_OFL)
|
|
+ priv->msg_err |= FALCON_I2C_RX_OFL;
|
|
+
|
|
+ /* rx fifo underflow (1) */
|
|
+ if (i_err & I2C_ERR_IRQSS_RXF_UFL)
|
|
+ priv->msg_err |= FALCON_I2C_RX_UFL;
|
|
+
|
|
+ i2c_w32(i_err, err_irqsc);
|
|
+ }
|
|
+
|
|
+ /* protocol interrupt */
|
|
+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC)
|
|
+ falcon_i2c_isr_prot(priv);
|
|
+
|
|
+ if ((priv->msg_err) || (priv->status == STATUS_STOP))
|
|
+ complete(&priv->cmd_complete);
|
|
+
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
|
+static u32 falcon_i2c_functionality(struct i2c_adapter *adap)
|
|
+{
|
|
+ return I2C_FUNC_I2C |
|
|
+ I2C_FUNC_10BIT_ADDR |
|
|
+ I2C_FUNC_SMBUS_EMUL;
|
|
+}
|
|
+
|
|
+static struct i2c_algorithm falcon_i2c_algorithm = {
|
|
+ .master_xfer = falcon_i2c_xfer,
|
|
+ .functionality = falcon_i2c_functionality,
|
|
+};
|
|
+
|
|
+static int __devinit falcon_i2c_probe(struct platform_device *pdev)
|
|
+{
|
|
+ int ret = 0;
|
|
+ struct falcon_i2c *priv;
|
|
+ struct i2c_adapter *adap;
|
|
+ struct resource *mmres, *ioarea,
|
|
+ *irqres_lb, *irqres_b, *irqres_err, *irqres_p;
|
|
+ struct clk *clk;
|
|
+
|
|
+ dev_dbg(&pdev->dev, "probing\n");
|
|
+
|
|
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
|
|
+ "i2c_lb");
|
|
+ irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b");
|
|
+ irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
|
|
+ "i2c_err");
|
|
+ irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p");
|
|
+
|
|
+ if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) {
|
|
+ dev_err(&pdev->dev, "no resources\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ clk = clk_get(&pdev->dev, "fpi");
|
|
+ if (IS_ERR(clk)) {
|
|
+ dev_err(&pdev->dev, "failed to get fpi clk\n");
|
|
+ return -ENOENT;
|
|
+ }
|
|
+
|
|
+ if (clk_get_rate(clk) != 100000000) {
|
|
+ dev_err(&pdev->dev, "input clock is not 100MHz\n");
|
|
+ return -ENOENT;
|
|
+ }
|
|
+
|
|
+ /* allocate private data */
|
|
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
+ if (!priv) {
|
|
+ dev_err(&pdev->dev, "can't allocate private data\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ adap = &priv->adap;
|
|
+ i2c_set_adapdata(adap, priv);
|
|
+ adap->owner = THIS_MODULE;
|
|
+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
|
+ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name));
|
|
+ adap->algo = &falcon_i2c_algorithm;
|
|
+
|
|
+ priv->mode = FALCON_I2C_MODE_100;
|
|
+ priv->clk = clk;
|
|
+ priv->dev = &pdev->dev;
|
|
+
|
|
+ init_completion(&priv->cmd_complete);
|
|
+ mutex_init(&priv->mutex);
|
|
+
|
|
+ ret = ltq_gpio_request(107, 0, 0, 0, DRV_NAME":sda");
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "I2C gpio 107 (sda) not available\n");
|
|
+ ret = -ENXIO;
|
|
+ goto err_free_priv;
|
|
+ }
|
|
+ ret = ltq_gpio_request(108, 0, 0, 0, DRV_NAME":scl");
|
|
+ if (ret) {
|
|
+ gpio_free(107);
|
|
+ dev_err(&pdev->dev, "I2C gpio 108 (scl) not available\n");
|
|
+ ret = -ENXIO;
|
|
+ goto err_free_priv;
|
|
+ }
|
|
+
|
|
+ ioarea = request_mem_region(mmres->start, resource_size(mmres),
|
|
+ pdev->name);
|
|
+
|
|
+ if (ioarea == NULL) {
|
|
+ dev_err(&pdev->dev, "I2C region already claimed\n");
|
|
+ ret = -ENXIO;
|
|
+ goto err_free_gpio;
|
|
+ }
|
|
+
|
|
+ /* map memory */
|
|
+ priv->membase = ioremap_nocache(mmres->start & ~KSEG1,
|
|
+ resource_size(mmres));
|
|
+ if (priv->membase == NULL) {
|
|
+ ret = -ENOMEM;
|
|
+ goto err_release_region;
|
|
+ }
|
|
+
|
|
+ priv->irq_lb = irqres_lb->start;
|
|
+ ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED,
|
|
+ irqres_lb->name, priv);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start);
|
|
+ ret = -ENODEV;
|
|
+ goto err_unmap_mem;
|
|
+ }
|
|
+
|
|
+ priv->irq_b = irqres_b->start;
|
|
+ ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED,
|
|
+ irqres_b->name, priv);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start);
|
|
+ ret = -ENODEV;
|
|
+ goto err_free_lb_irq;
|
|
+ }
|
|
+
|
|
+ priv->irq_err = irqres_err->start;
|
|
+ ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED,
|
|
+ irqres_err->name, priv);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start);
|
|
+ ret = -ENODEV;
|
|
+ goto err_free_b_irq;
|
|
+ }
|
|
+
|
|
+ priv->irq_p = irqres_p->start;
|
|
+ ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED,
|
|
+ irqres_p->name, priv);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start);
|
|
+ ret = -ENODEV;
|
|
+ goto err_free_err_irq;
|
|
+ }
|
|
+
|
|
+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase);
|
|
+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start,
|
|
+ irqres_b->start, irqres_err->start, irqres_p->start);
|
|
+
|
|
+ /* add our adapter to the i2c stack */
|
|
+ ret = i2c_add_numbered_adapter(adap);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "can't register I2C adapter\n");
|
|
+ goto err_free_p_irq;
|
|
+ }
|
|
+
|
|
+ platform_set_drvdata(pdev, priv);
|
|
+ i2c_set_adapdata(adap, priv);
|
|
+
|
|
+ /* print module version information */
|
|
+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n",
|
|
+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,
|
|
+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);
|
|
+
|
|
+ /* initialize HW */
|
|
+ ret = falcon_i2c_hw_init(adap);
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "can't configure adapter\n");
|
|
+ goto err_remove_adapter;
|
|
+ }
|
|
+
|
|
+ dev_info(&pdev->dev, "version %s\n", DRV_VERSION);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_remove_adapter:
|
|
+ i2c_del_adapter(adap);
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+
|
|
+err_free_p_irq:
|
|
+ free_irq(priv->irq_p, priv);
|
|
+
|
|
+err_free_err_irq:
|
|
+ free_irq(priv->irq_err, priv);
|
|
+
|
|
+err_free_b_irq:
|
|
+ free_irq(priv->irq_b, priv);
|
|
+
|
|
+err_free_lb_irq:
|
|
+ free_irq(priv->irq_lb, priv);
|
|
+
|
|
+err_unmap_mem:
|
|
+ iounmap(priv->membase);
|
|
+
|
|
+err_release_region:
|
|
+ release_mem_region(mmres->start, resource_size(mmres));
|
|
+
|
|
+err_free_gpio:
|
|
+ gpio_free(108);
|
|
+ gpio_free(107);
|
|
+
|
|
+err_free_priv:
|
|
+ kfree(priv);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int __devexit falcon_i2c_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct falcon_i2c *priv = platform_get_drvdata(pdev);
|
|
+ struct resource *mmres;
|
|
+
|
|
+ /* disable bus */
|
|
+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);
|
|
+
|
|
+ /* remove driver */
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+ i2c_del_adapter(&priv->adap);
|
|
+
|
|
+ free_irq(priv->irq_lb, priv);
|
|
+ free_irq(priv->irq_b, priv);
|
|
+ free_irq(priv->irq_err, priv);
|
|
+ free_irq(priv->irq_p, priv);
|
|
+
|
|
+ iounmap(priv->membase);
|
|
+
|
|
+ gpio_free(108);
|
|
+ gpio_free(107);
|
|
+
|
|
+ kfree(priv);
|
|
+
|
|
+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ release_mem_region(mmres->start, resource_size(mmres));
|
|
+
|
|
+ dev_dbg(&pdev->dev, "removed\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver falcon_i2c_driver = {
|
|
+ .probe = falcon_i2c_probe,
|
|
+ .remove = __devexit_p(falcon_i2c_remove),
|
|
+ .driver = {
|
|
+ .name = DRV_NAME,
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init falcon_i2c_init(void)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ ret = platform_driver_register(&falcon_i2c_driver);
|
|
+
|
|
+ if (ret)
|
|
+ pr_debug(DRV_NAME ": can't register platform driver\n");
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void __exit falcon_i2c_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&falcon_i2c_driver);
|
|
+}
|
|
+
|
|
+module_init(falcon_i2c_init);
|
|
+module_exit(falcon_i2c_exit);
|
|
+
|
|
+MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter");
|
|
+MODULE_ALIAS("platform:" DRV_NAME);
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_VERSION(DRV_VERSION);
|