mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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90fba37c49
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
148 lines
4.1 KiB
C
148 lines
4.1 KiB
C
/*
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* BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#ifndef _SBMEMC_H
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#define _SBMEMC_H
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#ifdef _LANGUAGE_ASSEMBLY
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#define MEMC_CONTROL 0x00
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#define MEMC_CONFIG 0x04
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#define MEMC_REFRESH 0x08
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#define MEMC_BISTSTAT 0x0c
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#define MEMC_MODEBUF 0x10
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#define MEMC_BKCLS 0x14
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#define MEMC_PRIORINV 0x18
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#define MEMC_DRAMTIM 0x1c
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#define MEMC_INTSTAT 0x20
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#define MEMC_INTMASK 0x24
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#define MEMC_INTINFO 0x28
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#define MEMC_NCDLCTL 0x30
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#define MEMC_RDNCDLCOR 0x34
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#define MEMC_WRNCDLCOR 0x38
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#define MEMC_MISCDLYCTL 0x3c
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#define MEMC_DQSGATENCDL 0x40
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#define MEMC_SPARE 0x44
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#define MEMC_TPADDR 0x48
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#define MEMC_TPDATA 0x4c
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#define MEMC_BARRIER 0x50
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#define MEMC_CORE 0x54
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#else /* !_LANGUAGE_ASSEMBLY */
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/* Sonics side: MEMC core registers */
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typedef volatile struct sbmemcregs {
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uint32 control;
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uint32 config;
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uint32 refresh;
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uint32 biststat;
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uint32 modebuf;
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uint32 bkcls;
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uint32 priorinv;
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uint32 dramtim;
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uint32 intstat;
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uint32 intmask;
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uint32 intinfo;
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uint32 reserved1;
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uint32 ncdlctl;
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uint32 rdncdlcor;
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uint32 wrncdlcor;
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uint32 miscdlyctl;
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uint32 dqsgatencdl;
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uint32 spare;
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uint32 tpaddr;
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uint32 tpdata;
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uint32 barrier;
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uint32 core;
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} sbmemcregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* MEMC Core Init values (OCP ID 0x80f) */
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/* For sdr: */
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#define MEMC_SD_CONFIG_INIT 0x00048000
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#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
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#define MEMC_SD_DRAMTIM3_INIT 0x000754da
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#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
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#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
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#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
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#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
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#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
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#define MEMC_SD_CONTROL_INIT0 0x00000002
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#define MEMC_SD_CONTROL_INIT1 0x00000008
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#define MEMC_SD_CONTROL_INIT2 0x00000004
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#define MEMC_SD_CONTROL_INIT3 0x00000010
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#define MEMC_SD_CONTROL_INIT4 0x00000001
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#define MEMC_SD_MODEBUF_INIT 0x00000000
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#define MEMC_SD_REFRESH_INIT 0x0000840f
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/* This is for SDRM8X8X4 */
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#define MEMC_SDR_INIT 0x0008
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#define MEMC_SDR_MODE 0x32
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#define MEMC_SDR_NCDL 0x00020032
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#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
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/* For ddr: */
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#define MEMC_CONFIG_INIT 0x00048000
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#define MEMC_DRAMTIM2_INIT 0x000754d8
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#define MEMC_DRAMTIM25_INIT 0x000754d9
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#define MEMC_RDNCDLCOR_INIT 0x00000000
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#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
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#define MEMC_WRNCDLCOR_INIT 0x49351200
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#define MEMC_1_WRNCDLCOR_INIT 0x14500200
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#define MEMC_DQSGATENCDL_INIT 0x00030000
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#define MEMC_MISCDLYCTL_INIT 0x21061c1b
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#define MEMC_1_MISCDLYCTL_INIT 0x21021400
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#define MEMC_NCDLCTL_INIT 0x00002001
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#define MEMC_CONTROL_INIT0 0x00000002
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#define MEMC_CONTROL_INIT1 0x00000008
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#define MEMC_MODEBUF_INIT0 0x00004000
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#define MEMC_CONTROL_INIT2 0x00000010
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#define MEMC_MODEBUF_INIT1 0x00000100
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#define MEMC_CONTROL_INIT3 0x00000010
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#define MEMC_CONTROL_INIT4 0x00000008
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#define MEMC_REFRESH_INIT 0x0000840f
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#define MEMC_CONTROL_INIT5 0x00000004
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#define MEMC_MODEBUF_INIT2 0x00000000
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#define MEMC_CONTROL_INIT6 0x00000010
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#define MEMC_CONTROL_INIT7 0x00000001
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/* This is for DDRM16X16X2 */
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#define MEMC_DDR_INIT 0x0009
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#define MEMC_DDR_MODE 0x62
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#define MEMC_DDR_NCDL 0x0005050a
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#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
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/* mask for sdr/ddr calibration registers */
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#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
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#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
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#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
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/* masks for miscdlyctl registers */
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#define MEMC_MISC_SM_MASK 0x30000000
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#define MEMC_MISC_SM_SHIFT 28
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#define MEMC_MISC_SD_MASK 0x0f000000
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#define MEMC_MISC_SD_SHIFT 24
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/* hw threshhold for calculating wr/rd for sdr memc */
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#define MEMC_CD_THRESHOLD 128
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/* Low bit of init register says if memc is ddr or sdr */
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#define MEMC_CONFIG_DDR 0x00000001
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#endif /* _SBMEMC_H */
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