mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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12b06b0a8d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19013 3c298f89-4303-0410-b956-a3cf2f4a3e73
280 lines
8.2 KiB
C
280 lines
8.2 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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/* FIXME: convert nasty volatile register derefs to readl/writel calls */
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/paccess.h>
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#include <asm/amazon/irq.h>
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#include <asm/amazon/amazon.h>
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#define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr))
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#ifndef AMAZON_PCI_MEM_BASE
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#define AMAZON_PCI_MEM_BASE 0xb2000000
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#endif
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#define AMAZON_PCI_MEM_SIZE 0x00400000
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#define AMAZON_PCI_IO_BASE 0xb2400000
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#define AMAZON_PCI_IO_SIZE 0x00200000
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#define AMAZON_PCI_CFG_BUSNUM_SHF 16
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#define AMAZON_PCI_CFG_DEVNUM_SHF 11
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#define AMAZON_PCI_CFG_FUNNUM_SHF 8
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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static struct resource pci_io_resource = {
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.name = "io pci IO space",
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#if 1
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.start = AMAZON_PCI_IO_BASE,
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.end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1,
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#else
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.start = 0,
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.end = 0x00002000 - 1,
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#endif
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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.name = "ext pci memory space",
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.start = AMAZON_PCI_MEM_BASE,
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.end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static int amazon_pci_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
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{
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unsigned long flags;
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u32 pci_addr;
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u32 val;
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int ret;
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/* Amazon support slot from 0 to 15 */
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/* devfn 0 & 0x20 is itself */
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if ((bus->number != 0) || (devfn > 0x7f) || (devfn == 0) || (devfn == 0x20))
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return 1;
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local_irq_save(flags);
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pci_addr = AMAZON_PCI_CFG_BASE |
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bus->number << AMAZON_PCI_CFG_BUSNUM_SHF |
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devfn << AMAZON_PCI_CFG_FUNNUM_SHF |
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(where & ~0x3);
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if (access_type == PCI_ACCESS_WRITE)
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{
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#ifdef CONFIG_SWAP_IO_SPACE
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val = swab32(*data);
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#endif
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ret = put_dbe(val, (u32 *)pci_addr);
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} else {
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ret = get_dbe(val, (u32 *)pci_addr);
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#ifdef CONFIG_SWAP_IO_SPACE
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*data = swab32(val);
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#else
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*data = val;
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#endif
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}
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amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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amazon_writel(amazon_readl(STATUS_COMMAND_ADDR), STATUS_COMMAND_ADDR);
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amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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mb();
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local_irq_restore(flags);
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if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
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return 1;
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return ret;
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}
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static int amazon_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
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{
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u32 data = 0;
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if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4)
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{
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data = val;
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} else {
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if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops amazon_pci_ops = {
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amazon_pci_read,
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amazon_pci_write
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};
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static struct pci_controller amazon_pci_controller = {
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.pci_ops = &amazon_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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switch (slot) {
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case 13:
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/* IDSEL = AD29 --> USB Host Controller */
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return INT_NUM_IM2_IRL15;
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case 14:
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/* IDSEL = AD30 --> mini PCI connector */
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return INT_NUM_IM2_IRL14;
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default:
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printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
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return 0;
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}
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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switch(dev->irq) {
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case INT_NUM_IM2_IRL15:
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/*
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* IDSEL = AD29 --> USB Host Controller
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* PCI_INTA/B/C--GPIO Port0.2--EXIN3
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* IN/ALT0:1 ALT1:0
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* PULL UP
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*/
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(*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb;
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(*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4;
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(*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb;
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(*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4;
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(*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4;
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//External Interrupt Node
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(*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */
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(*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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break;
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case INT_NUM_IM2_IRL14:
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/*
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* IDSEL = AD30 --> mini PCI connector
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* PCI_INTA--GPIO Port0.1--EXIN2
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* IN/ALT0:1 ALT1:0
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* PULL UP
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*/
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(*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd;
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(*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2;
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(*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd;
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(*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2;
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(*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2;
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//External Interrupt Node
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(*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600;
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(*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4;
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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break;
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default:
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return 1;
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}
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return 0;
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}
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int __init amazon_pci_init(void)
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{
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u32 temp_buffer;
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#ifdef CONFIG_SWAP_IO_SPACE
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AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28);
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wmb();
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#endif
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AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<<ARB_CTRL_bit);
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amazon_writel(amazon_readl(PCI_MODE) & (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) = AMAZON_PCI_REG32(STATUS_COMMAND_ADDR) | (1<<BUS_MASTER_ENABLE_BIT) |(1<<MEM_SPACE_ENABLE_BIT);
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temp_buffer = AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR);
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temp_buffer = temp_buffer | (1<< INTERNAL_ARB_ENABLE_BIT);
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temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_REQ_MASK_2BITS);
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temp_buffer = temp_buffer & ~(3<< PCI_MASTER0_GNT_MASK_2BITS);
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/* flash */
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temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_REQ_MASK_2BITS);
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temp_buffer = temp_buffer & ~(3<< PCI_MASTER1_GNT_MASK_2BITS);
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/* external master */
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temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_REQ_MASK_2BITS);
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temp_buffer = temp_buffer & ~(3<< PCI_MASTER2_GNT_MASK_2BITS);
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AMAZON_PCI_REG32(PCI_ARB_CTRL_STATUS_ADDR) = temp_buffer;
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wmb();
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_0) = 0xb2000000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_1) = 0xb2100000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_2) = 0xb2200000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_3) = 0xb2300000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_4) = 0xb2400000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_5) = 0xb2500000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_6) = 0xb2600000;
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AMAZON_PCI_REG32(FPI_ADDRESS_MAP_7) = 0xb2700000;
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AMAZON_PCI_REG32(BAR11_MASK) = 0x0c000008;
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AMAZON_PCI_REG32(PCI_ADDRESS_MAP_11) = 0x0;
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AMAZON_PCI_REG32(BAR1_ADDR) = 0x0;
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amazon_writel(amazon_readl(PCI_MODE) | (~(1<<PCI_MODE_cfgok_bit)), PCI_MODE);
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//use 8 dw burse length
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AMAZON_PCI_REG32(FPI_BURST_LENGTH) = 0x303;
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amazon_pci_controller.io_map_base = (unsigned long)ioremap(AMAZON_PCI_IO_BASE, AMAZON_PCI_IO_SIZE - 1);
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register_pci_controller(&amazon_pci_controller);
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return 0;
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}
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arch_initcall(amazon_pci_init);
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