mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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95a4336b23
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20082 3c298f89-4303-0410-b956-a3cf2f4a3e73
167 lines
3.9 KiB
C
167 lines
3.9 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform IRQ support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/irq_cpu.h>
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static void __iomem *jz_intc_base;
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static uint32_t jz_intc_wakeup;
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static uint32_t jz_intc_saved;
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#define JZ_REG_BASE_INTC 0x10001000
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#define JZ_REG_INTC_STATUS 0x00
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#define JZ_REG_INTC_MASK 0x04
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#define JZ_REG_INTC_SET_MASK 0x08
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#define JZ_REG_INTC_CLEAR_MASK 0x0c
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#define JZ_REG_INTC_PENDING 0x10
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#define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE)
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static void intc_irq_unmask(unsigned int irq)
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{
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writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
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}
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static void intc_irq_mask(unsigned int irq)
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{
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writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
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}
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static void intc_irq_ack(unsigned int irq)
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{
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writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
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}
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static int intc_irq_set_wake(unsigned int irq, unsigned int on)
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{
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if (on)
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jz_intc_wakeup |= IRQ_BIT(irq);
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else
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jz_intc_wakeup &= ~IRQ_BIT(irq);
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return 0;
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}
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static struct irq_chip intc_irq_type = {
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.name = "INTC",
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.mask = intc_irq_mask,
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.unmask = intc_irq_unmask,
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.ack = intc_irq_ack,
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.set_wake = intc_irq_set_wake,
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};
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static irqreturn_t jz4740_cascade(int irq, void *data)
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{
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uint32_t irq_reg;
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irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
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generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE);
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return IRQ_HANDLED;
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}
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static struct irqaction jz4740_cascade_action = {
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.handler = jz4740_cascade,
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.name = "JZ4740 cascade interrupt",
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.flags = IRQF_DISABLED,
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};
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void __init arch_init_irq(void)
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{
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int i;
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mips_cpu_irq_init();
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jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
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for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) {
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intc_irq_mask(i);
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set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
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}
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setup_irq(2, &jz4740_cascade_action);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP2)
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do_IRQ(2);
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else if(pending & STATUSF_IP3)
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do_IRQ(3);
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else
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spurious_interrupt();
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}
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/* TODO: Use sysdev */
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void jz4740_intc_suspend(void)
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{
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jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
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writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
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writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
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}
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void jz4740_intc_resume(void)
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{
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writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
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writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
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}
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#ifdef CONFIG_DEBUG_FS
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static int intc_regs_show(struct seq_file *s, void *unused)
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{
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seq_printf(s, "Status:\t\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_STATUS));
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seq_printf(s, "Mask\t\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_MASK));
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seq_printf(s, "Pending:\t%08x\n", readl(jz_intc_base + JZ_REG_INTC_PENDING));
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return 0;
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}
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static int intc_regs_open(struct inode *inode, struct file *file)
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{
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return single_open(file, intc_regs_show, NULL);
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}
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static const struct file_operations intc_regs_operations = {
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.open = intc_regs_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init intc_debugfs_init(void)
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{
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(void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
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NULL, NULL, &intc_regs_operations);
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return 0;
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}
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subsys_initcall(intc_debugfs_init);
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#endif
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