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The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33983 3c298f89-4303-0410-b956-a3cf2f4a3e73
229 lines
6.9 KiB
Diff
229 lines
6.9 KiB
Diff
From 6c3ef689e4364dca74eaaecd72384be09e5a6bc8 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 25 Jun 2012 09:19:08 +0200
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Subject: [PATCH 14/34] MIPS: pci-ar71xx: use dynamically allocated PCI controller structure
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/pci/pci-ar71xx.c | 84 +++++++++++++++++++++++++++----------------
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1 files changed, 53 insertions(+), 31 deletions(-)
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--- a/arch/mips/pci/pci-ar71xx.c
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+++ b/arch/mips/pci/pci-ar71xx.c
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@@ -20,6 +20,7 @@
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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+#include <linux/slab.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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@@ -48,8 +49,12 @@
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#define AR71XX_PCI_IRQ_COUNT 5
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-static DEFINE_SPINLOCK(ar71xx_pci_lock);
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-static void __iomem *ar71xx_pcicfg_base;
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+struct ar71xx_pci_controller {
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+ void __iomem *cfg_base;
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+ spinlock_t lock;
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+ int irq;
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+ struct pci_controller pci_ctrl;
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+};
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/* Byte lane enable bits */
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static const u8 ar71xx_pci_ble_table[4][4] = {
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@@ -92,9 +97,18 @@ static inline u32 ar71xx_pci_bus_addr(st
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return ret;
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}
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-static int ar71xx_pci_check_error(int quiet)
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+static inline struct ar71xx_pci_controller *
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+pci_bus_to_ar71xx_controller(struct pci_bus *bus)
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{
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- void __iomem *base = ar71xx_pcicfg_base;
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+ struct pci_controller *hose;
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+
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+ hose = (struct pci_controller *) bus->sysdata;
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+ return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
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+}
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+
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+static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
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+{
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+ void __iomem *base = apc->cfg_base;
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u32 pci_err;
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u32 ahb_err;
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@@ -129,9 +143,10 @@ static int ar71xx_pci_check_error(int qu
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return !!(ahb_err | pci_err);
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}
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-static inline void ar71xx_pci_local_write(int where, int size, u32 value)
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+static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
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+ int where, int size, u32 value)
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{
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- void __iomem *base = ar71xx_pcicfg_base;
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+ void __iomem *base = apc->cfg_base;
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u32 ad_cbe;
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value = value << (8 * (where & 3));
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@@ -147,7 +162,8 @@ static inline int ar71xx_pci_set_cfgaddr
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unsigned int devfn,
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int where, int size, u32 cmd)
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{
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- void __iomem *base = ar71xx_pcicfg_base;
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+ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
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+ void __iomem *base = apc->cfg_base;
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u32 addr;
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addr = ar71xx_pci_bus_addr(bus, devfn, where);
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@@ -156,13 +172,14 @@ static inline int ar71xx_pci_set_cfgaddr
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__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
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base + AR71XX_PCI_REG_CFG_CBE);
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- return ar71xx_pci_check_error(1);
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+ return ar71xx_pci_check_error(apc, 1);
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}
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static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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- void __iomem *base = ar71xx_pcicfg_base;
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+ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
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+ void __iomem *base = apc->cfg_base;
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unsigned long flags;
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u32 data;
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int err;
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@@ -171,7 +188,7 @@ static int ar71xx_pci_read_config(struct
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ret = PCIBIOS_SUCCESSFUL;
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data = ~0;
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- spin_lock_irqsave(&ar71xx_pci_lock, flags);
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+ spin_lock_irqsave(&apc->lock, flags);
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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AR71XX_PCI_CFG_CMD_READ);
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@@ -180,7 +197,7 @@ static int ar71xx_pci_read_config(struct
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else
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data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
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- spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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+ spin_unlock_irqrestore(&apc->lock, flags);
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*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
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@@ -190,7 +207,8 @@ static int ar71xx_pci_read_config(struct
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static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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- void __iomem *base = ar71xx_pcicfg_base;
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+ struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
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+ void __iomem *base = apc->cfg_base;
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unsigned long flags;
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int err;
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int ret;
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@@ -198,7 +216,7 @@ static int ar71xx_pci_write_config(struc
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value = value << (8 * (where & 3));
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ret = PCIBIOS_SUCCESSFUL;
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- spin_lock_irqsave(&ar71xx_pci_lock, flags);
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+ spin_lock_irqsave(&apc->lock, flags);
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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AR71XX_PCI_CFG_CMD_WRITE);
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@@ -207,7 +225,7 @@ static int ar71xx_pci_write_config(struc
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else
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__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
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- spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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+ spin_unlock_irqrestore(&apc->lock, flags);
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return ret;
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}
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@@ -231,12 +249,6 @@ static struct resource ar71xx_pci_mem_re
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.flags = IORESOURCE_MEM
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};
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-static struct pci_controller ar71xx_pci_controller = {
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- .pci_ops = &ar71xx_pci_ops,
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- .mem_resource = &ar71xx_pci_mem_resource,
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- .io_resource = &ar71xx_pci_io_resource,
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-};
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-
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static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ath79_reset_base;
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@@ -294,7 +306,7 @@ static struct irq_chip ar71xx_pci_irq_ch
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.irq_mask_ack = ar71xx_pci_irq_mask,
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};
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-static __devinit void ar71xx_pci_irq_init(int irq)
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+static __devinit void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
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{
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void __iomem *base = ath79_reset_base;
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int i;
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@@ -309,7 +321,7 @@ static __devinit void ar71xx_pci_irq_ini
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irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
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handle_level_irq);
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- irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
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+ irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
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}
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static __devinit void ar71xx_pci_reset(void)
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@@ -336,20 +348,26 @@ static __devinit void ar71xx_pci_reset(v
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static int __devinit ar71xx_pci_probe(struct platform_device *pdev)
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{
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+ struct ar71xx_pci_controller *apc;
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struct resource *res;
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- int irq;
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u32 t;
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+ apc = kzalloc(sizeof(struct ar71xx_pci_controller), GFP_KERNEL);
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+ if (!apc)
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+ return -ENOMEM;
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+
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+ spin_lock_init(&apc->lock);
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+
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
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if (!res)
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return -EINVAL;
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- ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
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- if (!ar71xx_pcicfg_base)
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+ apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
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+ if (!apc->cfg_base)
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return -ENOMEM;
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- irq = platform_get_irq(pdev, 0);
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- if (irq < 0)
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+ apc->irq = platform_get_irq(pdev, 0);
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+ if (apc->irq < 0)
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return -EINVAL;
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ar71xx_pci_reset();
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@@ -357,14 +375,18 @@ static int __devinit ar71xx_pci_probe(st
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/* setup COMMAND register */
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t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
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| PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
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- ar71xx_pci_local_write(PCI_COMMAND, 4, t);
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+ ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
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/* clear bus errors */
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- ar71xx_pci_check_error(1);
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+ ar71xx_pci_check_error(apc, 1);
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+
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+ ar71xx_pci_irq_init(apc);
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- ar71xx_pci_irq_init(irq);
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+ apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
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+ apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
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+ apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
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- register_pci_controller(&ar71xx_pci_controller);
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+ register_pci_controller(&apc->pci_ctrl);
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return 0;
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}
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