mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 08:23:41 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34651 3c298f89-4303-0410-b956-a3cf2f4a3e73
630 lines
18 KiB
Diff
630 lines
18 KiB
Diff
--- a/drivers/ssb/b43_pci_bridge.c
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+++ b/drivers/ssb/b43_pci_bridge.c
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@@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
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--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -4,6 +4,7 @@
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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@@ -12,6 +13,7 @@
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#include <linux/ssb/ssb_regs.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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+#include <linux/bcm47xx_wdt.h>
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#include "ssb_private.h"
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@@ -280,6 +282,69 @@ static void calc_fast_powerup_delay(stru
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cc->fast_pwrup_delay = tmp;
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}
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+static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
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+{
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
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+ return ssb_pmu_get_alp_clock(cc);
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+
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+ return 20000000;
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+}
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+
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+static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
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+{
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+ u32 nb;
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+
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ if (cc->dev->id.revision < 26)
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+ nb = 16;
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+ else
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+ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
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+ } else {
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+ nb = 28;
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+ }
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+ if (nb == 32)
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+ return 0xffffffff;
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+ else
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+ return (1 << nb) - 1;
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+}
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+
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+u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
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+{
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+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
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+
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+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ return ssb_chipco_watchdog_timer_set(cc, ticks);
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+}
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+
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+u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
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+{
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+ struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
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+ u32 ticks;
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+
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+ if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
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+ return ticks / cc->ticks_per_ms;
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+}
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+
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+static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ /* based on 32KHz ILP clock */
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+ return 32;
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+ } else {
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+ if (cc->dev->id.revision < 18)
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+ return ssb_clockspeed(bus) / 1000;
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+ else
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+ return ssb_chipco_alp_clock(cc) / 1000;
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+ }
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+}
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+
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void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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@@ -297,6 +362,11 @@ void ssb_chipcommon_init(struct ssb_chip
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chipco_powercontrol_init(cc);
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ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
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calc_fast_powerup_delay(cc);
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+
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+ if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
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+ cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
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+ cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
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+ }
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}
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void ssb_chipco_suspend(struct ssb_chipcommon *cc)
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@@ -395,10 +465,27 @@ void ssb_chipco_timing_init(struct ssb_c
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}
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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-void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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+u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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{
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- /* instant NMI */
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- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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+ u32 maxt;
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+ enum ssb_clkmode clkmode;
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+
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+ maxt = ssb_chipco_watchdog_get_max_timer(cc);
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ if (ticks == 1)
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+ ticks = 2;
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+ else if (ticks > maxt)
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+ ticks = maxt;
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+ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
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+ } else {
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+ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
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+ ssb_chipco_set_clockmode(cc, clkmode);
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+ if (ticks > maxt)
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+ ticks = maxt;
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+ /* instant NMI */
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+ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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+ }
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+ return ticks;
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}
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void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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@@ -473,12 +560,7 @@ int ssb_chipco_serial_init(struct ssb_ch
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chipco_read32(cc, SSB_CHIPCO_CORECTL)
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| SSB_CHIPCO_CORECTL_UARTCLK0);
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} else if ((ccrev >= 11) && (ccrev != 15)) {
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- /* Fixed ALP clock */
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- baud_base = 20000000;
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- if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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- /* FIXME: baud_base is different for devices with a PMU */
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- SSB_WARN_ON(1);
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- }
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+ baud_base = ssb_chipco_alp_clock(cc);
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div = 1;
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if (ccrev >= 21) {
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/* Turn off UART clock before switching clocksource. */
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--- a/drivers/ssb/driver_chipcommon_pmu.c
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+++ b/drivers/ssb/driver_chipcommon_pmu.c
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@@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
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chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
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}
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break;
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+ case 43222:
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+ break;
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default:
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ssb_printk(KERN_ERR PFX
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"ERROR: PLL init unknown for device %04X\n",
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@@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
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min_msk = 0xCBB;
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break;
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case 0x4322:
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+ case 43222:
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/* We keep the default settings:
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* min_msk = 0xCBB
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* max_msk = 0x7FFFF
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@@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
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EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
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EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
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+static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
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+{
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+ u32 crystalfreq;
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+ const struct pmu0_plltab_entry *e = NULL;
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+
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+ crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
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+ SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
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+ e = pmu0_plltab_find_entry(crystalfreq);
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+ BUG_ON(!e);
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+ return e->freq * 1000;
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+}
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+
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+u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
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+{
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+ struct ssb_bus *bus = cc->dev->bus;
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+
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+ switch (bus->chip_id) {
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+ case 0x5354:
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+ ssb_pmu_get_alp_clock_clk0(cc);
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+ default:
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+ ssb_printk(KERN_ERR PFX
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+ "ERROR: PMU alp clock unknown for device %04X\n",
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+ bus->chip_id);
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+ return 0;
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+ }
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+}
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+
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u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
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{
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struct ssb_bus *bus = cc->dev->bus;
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--- a/drivers/ssb/driver_extif.c
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+++ b/drivers/ssb/driver_extif.c
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@@ -112,10 +112,30 @@ void ssb_extif_get_clockcontrol(struct s
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*m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
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}
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-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
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- u32 ticks)
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+u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
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{
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+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
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+
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+ return ssb_extif_watchdog_timer_set(extif, ticks);
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+}
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+
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+u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
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+{
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+ struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
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+ u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
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+
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+ ticks = ssb_extif_watchdog_timer_set(extif, ticks);
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+
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+ return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
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+}
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+
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+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
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+{
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+ if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
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+ ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
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extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
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+
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+ return ticks;
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}
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u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
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{
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struct ssb_bus *bus = mcore->dev->bus;
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- if (bus->extif.dev)
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+ if (ssb_extif_available(&bus->extif))
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mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
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- else if (bus->chipco.dev)
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+ else if (ssb_chipco_available(&bus->chipco))
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mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
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else
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mcore->nr_serial_ports = 0;
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@@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
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{
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struct ssb_bus *bus = mcore->dev->bus;
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- mcore->flash_buswidth = 2;
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- if (bus->chipco.dev) {
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- mcore->flash_window = 0x1c000000;
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- mcore->flash_window_size = 0x02000000;
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+ /* When there is no chipcommon on the bus there is 4MB flash */
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+ if (!ssb_chipco_available(&bus->chipco)) {
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+ mcore->pflash.present = true;
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+ mcore->pflash.buswidth = 2;
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+ mcore->pflash.window = SSB_FLASH1;
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+ mcore->pflash.window_size = SSB_FLASH1_SZ;
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+ return;
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+ }
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+
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+ /* There is ChipCommon, so use it to read info about flash */
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+ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ pr_err("Serial flash not supported\n");
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+ break;
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+ case SSB_CHIPCO_FLASHT_PARA:
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+ pr_debug("Found parallel flash\n");
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+ mcore->pflash.present = true;
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+ mcore->pflash.window = SSB_FLASH2;
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+ mcore->pflash.window_size = SSB_FLASH2_SZ;
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if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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& SSB_CHIPCO_CFG_DS16) == 0)
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- mcore->flash_buswidth = 1;
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- } else {
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- mcore->flash_window = 0x1fc00000;
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- mcore->flash_window_size = 0x00400000;
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+ mcore->pflash.buswidth = 1;
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+ else
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+ mcore->pflash.buswidth = 2;
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+ break;
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}
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}
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@@ -211,9 +227,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
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if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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return ssb_pmu_get_cpu_clock(&bus->chipco);
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- if (bus->extif.dev) {
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+ if (ssb_extif_available(&bus->extif)) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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- } else if (bus->chipco.dev) {
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+ } else if (ssb_chipco_available(&bus->chipco)) {
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ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
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} else
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return 0;
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@@ -249,9 +265,9 @@ void ssb_mipscore_init(struct ssb_mipsco
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hz = 100000000;
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ns = 1000000000 / hz;
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- if (bus->extif.dev)
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+ if (ssb_extif_available(&bus->extif))
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ssb_extif_timing_init(&bus->extif, ns);
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- else if (bus->chipco.dev)
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+ else if (ssb_chipco_available(&bus->chipco))
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ssb_chipco_timing_init(&bus->chipco, ns);
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/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
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--- a/drivers/ssb/embedded.c
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+++ b/drivers/ssb/embedded.c
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@@ -4,11 +4,13 @@
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*
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* Copyright 2005-2008, Broadcom Corporation
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* Copyright 2006-2008, Michael Buesch <m@bues.ch>
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+ * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/export.h>
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+#include <linux/platform_device.h>
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_embedded.h>
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#include <linux/ssb/ssb_driver_pci.h>
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@@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
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}
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EXPORT_SYMBOL(ssb_watchdog_timer_set);
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+int ssb_watchdog_register(struct ssb_bus *bus)
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+{
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+ struct bcm47xx_wdt wdt = {};
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+ struct platform_device *pdev;
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+
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+ if (ssb_chipco_available(&bus->chipco)) {
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+ wdt.driver_data = &bus->chipco;
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+ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
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+ wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
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+ wdt.max_timer_ms = bus->chipco.max_timer_ms;
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+ } else if (ssb_extif_available(&bus->extif)) {
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+ wdt.driver_data = &bus->extif;
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+ wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
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+ wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
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+ wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
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+ } else {
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+ return -ENODEV;
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+ }
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+
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+ pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
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+ bus->busnumber, &wdt,
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+ sizeof(wdt));
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+ if (IS_ERR(pdev)) {
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+ ssb_dprintk(KERN_INFO PFX
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+ "can not register watchdog device, err: %li\n",
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+ PTR_ERR(pdev));
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+ return PTR_ERR(pdev);
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+ }
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+
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+ bus->watchdog = pdev;
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+ return 0;
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+}
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+
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u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
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{
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unsigned long flags;
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -13,6 +13,7 @@
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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+#include <linux/platform_device.h>
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/ssb/ssb_driver_gige.h>
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@@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
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if (sdev->dev)
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device_unregister(sdev->dev);
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}
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+
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+#ifdef CONFIG_SSB_EMBEDDED
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+ if (bus->bustype == SSB_BUSTYPE_SSB)
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+ platform_device_unregister(bus->watchdog);
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+#endif
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}
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void ssb_bus_unregister(struct ssb_bus *bus)
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@@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
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if (err)
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goto error;
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ssb_pcicore_init(&bus->pcicore);
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+ if (bus->bustype == SSB_BUSTYPE_SSB)
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+ ssb_watchdog_register(bus);
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ssb_bus_may_powerdown(bus);
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err = ssb_devices_register(bus);
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@@ -1118,8 +1126,7 @@ static u32 ssb_tmslow_reject_bitmask(str
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case SSB_IDLOW_SSBREV_27: /* same here */
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return SSB_TMSLOW_REJECT; /* this is a guess */
|
|
default:
|
|
- printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
|
|
- WARN_ON(1);
|
|
+ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
|
|
}
|
|
return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
|
|
}
|
|
--- a/drivers/ssb/ssb_private.h
|
|
+++ b/drivers/ssb/ssb_private.h
|
|
@@ -3,6 +3,7 @@
|
|
|
|
#include <linux/ssb/ssb.h>
|
|
#include <linux/types.h>
|
|
+#include <linux/bcm47xx_wdt.h>
|
|
|
|
|
|
#define PFX "ssb: "
|
|
@@ -210,5 +211,35 @@ static inline void b43_pci_ssb_bridge_ex
|
|
/* driver_chipcommon_pmu.c */
|
|
extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
|
|
extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
|
|
+extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
|
|
+
|
|
+extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
|
+ u32 ticks);
|
|
+extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
|
+
|
|
+#ifdef CONFIG_SSB_DRIVER_EXTIF
|
|
+extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
|
|
+extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
|
+#else
|
|
+static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
|
|
+ u32 ticks)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
|
|
+ u32 ms)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_SSB_EMBEDDED
|
|
+extern int ssb_watchdog_register(struct ssb_bus *bus);
|
|
+#else /* CONFIG_SSB_EMBEDDED */
|
|
+static inline int ssb_watchdog_register(struct ssb_bus *bus)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+#endif /* CONFIG_SSB_EMBEDDED */
|
|
|
|
#endif /* LINUX_SSB_PRIVATE_H_ */
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -8,6 +8,7 @@
|
|
#include <linux/pci.h>
|
|
#include <linux/mod_devicetable.h>
|
|
#include <linux/dma-mapping.h>
|
|
+#include <linux/platform_device.h>
|
|
|
|
#include <linux/ssb/ssb_regs.h>
|
|
|
|
@@ -432,6 +433,7 @@ struct ssb_bus {
|
|
#ifdef CONFIG_SSB_EMBEDDED
|
|
/* Lock for GPIO register access. */
|
|
spinlock_t gpio_lock;
|
|
+ struct platform_device *watchdog;
|
|
#endif /* EMBEDDED */
|
|
|
|
/* Internal-only stuff follows. Do not touch. */
|
|
--- a/include/linux/ssb/ssb_driver_chipcommon.h
|
|
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
|
|
@@ -504,7 +504,9 @@
|
|
#define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
|
|
#define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
|
|
#define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
|
|
-#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
|
|
+#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
|
|
+#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
|
|
+#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
|
|
|
|
/* Status register bits for ST flashes */
|
|
#define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
|
|
@@ -589,6 +591,8 @@ struct ssb_chipcommon {
|
|
/* Fast Powerup Delay constant */
|
|
u16 fast_pwrup_delay;
|
|
struct ssb_chipcommon_pmu pmu;
|
|
+ u32 ticks_per_ms;
|
|
+ u32 max_timer_ms;
|
|
};
|
|
|
|
static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
|
|
@@ -628,8 +632,7 @@ enum ssb_clkmode {
|
|
extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
|
|
enum ssb_clkmode mode);
|
|
|
|
-extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
|
|
- u32 ticks);
|
|
+extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
|
|
|
|
void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
|
|
|
|
--- a/include/linux/ssb/ssb_driver_extif.h
|
|
+++ b/include/linux/ssb/ssb_driver_extif.h
|
|
@@ -152,6 +152,9 @@
|
|
/* watchdog */
|
|
#define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
|
|
|
|
+#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
|
|
+#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
|
|
+ / (SSB_EXTIF_WATCHDOG_CLK / 1000))
|
|
|
|
|
|
#ifdef CONFIG_SSB_DRIVER_EXTIF
|
|
@@ -171,8 +174,7 @@ extern void ssb_extif_get_clockcontrol(s
|
|
extern void ssb_extif_timing_init(struct ssb_extif *extif,
|
|
unsigned long ns);
|
|
|
|
-extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
|
- u32 ticks);
|
|
+extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
|
|
|
|
/* Extif GPIO pin access */
|
|
u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
|
|
@@ -205,10 +207,52 @@ void ssb_extif_get_clockcontrol(struct s
|
|
}
|
|
|
|
static inline
|
|
-void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
|
|
- u32 ticks)
|
|
+void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
|
|
{
|
|
}
|
|
|
|
+static inline
|
|
+u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
|
|
+ u32 value)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
|
|
+ u32 value)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
|
|
+ u32 value)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
|
|
+ u32 value)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_SSB_SERIAL
|
|
+static inline int ssb_extif_serial_init(struct ssb_extif *extif,
|
|
+ struct ssb_serial_port *ports)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+#endif /* CONFIG_SSB_SERIAL */
|
|
+
|
|
#endif /* CONFIG_SSB_DRIVER_EXTIF */
|
|
#endif /* LINUX_SSB_EXTIFCORE_H_ */
|
|
--- a/include/linux/ssb/ssb_driver_mips.h
|
|
+++ b/include/linux/ssb/ssb_driver_mips.h
|
|
@@ -13,6 +13,12 @@ struct ssb_serial_port {
|
|
unsigned int reg_shift;
|
|
};
|
|
|
|
+struct ssb_pflash {
|
|
+ bool present;
|
|
+ u8 buswidth;
|
|
+ u32 window;
|
|
+ u32 window_size;
|
|
+};
|
|
|
|
struct ssb_mipscore {
|
|
struct ssb_device *dev;
|
|
@@ -20,9 +26,7 @@ struct ssb_mipscore {
|
|
int nr_serial_ports;
|
|
struct ssb_serial_port serial_ports[4];
|
|
|
|
- u8 flash_buswidth;
|
|
- u32 flash_window;
|
|
- u32 flash_window_size;
|
|
+ struct ssb_pflash pflash;
|
|
};
|
|
|
|
extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
|
|
--- a/include/linux/ssb/ssb_regs.h
|
|
+++ b/include/linux/ssb/ssb_regs.h
|
|
@@ -485,7 +485,7 @@
|
|
#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
|
|
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
|
|
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
|
|
-#define SSB_SPROM8_TEMPDELTA 0x00BA
|
|
+#define SSB_SPROM8_TEMPDELTA 0x00BC
|
|
#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
|
|
#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
|
|
#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
|