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4f2c17075b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
32 lines
1.1 KiB
Diff
32 lines
1.1 KiB
Diff
From f40e1f9d856ec417468c090c4b56826171daa670 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 16 Aug 2012 08:25:42 +0000
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Subject: [PATCH 8/9] MIPS: lantiq: enable pci clk conditional for xrx200 SoC
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The xrx200 SoC family has the same PCI clock register layout as the AR9.
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Enable the same quirk as for AR9
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4235/
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---
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arch/mips/lantiq/xway/sysctrl.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
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index befbb76..67c3a91 100644
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
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{
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unsigned int val = ltq_cgu_r32(ifccr);
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/* set bus clock speed */
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- if (of_machine_is_compatible("lantiq,ar9")) {
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+ if (of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9")) {
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val &= ~0x1f00000;
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if (clk->rate == CLOCK_33M)
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val |= 0xe00000;
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--
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1.7.10.4
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