mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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809c03fe4c
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19098 3c298f89-4303-0410-b956-a3cf2f4a3e73
86 lines
1.3 KiB
ArmAsm
86 lines
1.3 KiB
ArmAsm
/*
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* linux/arch/mips/boot/compressed/head.S
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*
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* Copyright (C) 2005-2008 Ingenic Semiconductor Inc.
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*/
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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#include <asm/cachectl.h>
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#include <asm/regdef.h>
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#define IndexInvalidate_I 0x00
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#define IndexWriteBack_D 0x01
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.set noreorder
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LEAF(startup)
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startup:
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move s0, a0 /* Save the boot loader transfered args */
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move s1, a1
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move s2, a2
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move s3, a3
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la a0, _edata
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la a1, _end
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1: sw zero, 0(a0) /* Clear BSS section */
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bne a1, a0, 1b
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addu a0, 4
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la sp, (.stack + 8192)
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la a0, __image_begin
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la a1, IMAGESIZE
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la a2, LOADADDR
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la ra, 1f
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la k0, decompress_kernel
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jr k0
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nop
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1:
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move a0, s0
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move a1, s1
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move a2, s2
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move a3, s3
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li k0, KERNEL_ENTRY
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jr k0
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nop
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2:
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b 32
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END(startup)
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LEAF(flushcaches)
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la t0, 1f
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la t1, 0xa0000000
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or t0, t0, t1
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jr t0
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nop
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1:
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li k0, 0x80000000 # start address
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li k1, 0x80004000 # end address (16KB I-Cache)
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subu k1, 128
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2:
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.set mips3
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cache IndexWriteBack_D, 0(k0)
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cache IndexWriteBack_D, 32(k0)
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cache IndexWriteBack_D, 64(k0)
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cache IndexWriteBack_D, 96(k0)
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cache IndexInvalidate_I, 0(k0)
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cache IndexInvalidate_I, 32(k0)
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cache IndexInvalidate_I, 64(k0)
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cache IndexInvalidate_I, 96(k0)
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.set mips0
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bne k0, k1, 2b
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addu k0, k0, 128
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la t0, 3f
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jr t0
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nop
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3:
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jr ra
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nop
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END(flushcaches)
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.comm .stack,4096*2,4
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