mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-27 12:06:28 +02:00
240bf1625e
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11601 3c298f89-4303-0410-b956-a3cf2f4a3e73
221 lines
8.6 KiB
C
221 lines
8.6 KiB
C
/*****************************************************************************
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* DANUBE BootROM
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* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
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* IFAP DC COM SD
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*****************************************************************************/
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#ifndef __ASC_H
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#define __ASC_H
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#define DANUBEASC_TXFIFO_FL 1
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#define DANUBEASC_RXFIFO_FL 1
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#define DANUBEASC_TXFIFO_FULL 16
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x00000003
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#define ASCOPT_CS7 0x00000001
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#define ASCOPT_CS8 0x00000002
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#define ASCOPT_PARENB 0x00000004
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#define ASCOPT_STOPB 0x00000008
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#define ASCOPT_PARODD 0x00000010
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#define ASCOPT_CREAD 0x00000020
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#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
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/* ASC input select (0 or 1) */
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#define CONSOLE_TTY 0
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#define DANUBEASC_TXFIFO_FL 1
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#define DANUBEASC_RXFIFO_FL 1
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#define DANUBEASC_TXFIFO_FULL 16
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/* interrupt lines masks for the ASC device interrupts*/
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/* change these macroses if it's necessary */
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#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
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#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
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#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
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#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
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#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
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#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
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#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
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#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
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/* interrupt controller access macros */
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#define ASC_INTERRUPTS_ENABLE(X) \
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*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
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#define ASC_INTERRUPTS_DISABLE(X) \
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*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
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#define ASC_INTERRUPTS_CLEAR(X) \
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*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
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/* CLC register's bits and bitfields */
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#define ASCCLC_DISR 0x00000001
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#define ASCCLC_DISS 0x00000002
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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/* CON register's bits and bitfields */
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#define ASCCON_MODEMASK 0x0000000f
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#define ASCCON_M_8ASYNC 0x0
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#define ASCCON_M_8IRDA 0x1
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#define ASCCON_M_7ASYNC 0x2
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#define ASCCON_M_7IRDA 0x3
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#define ASCCON_WLSMASK 0x0000000c
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#define ASCCON_WLSOFFSET 2
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#define ASCCON_WLS_8BIT 0x0
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#define ASCCON_WLS_7BIT 0x1
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#define ASCCON_PEN 0x00000010
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#define ASCCON_ODD 0x00000020
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#define ASCCON_SP 0x00000040
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#define ASCCON_STP 0x00000080
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#define ASCCON_BRS 0x00000100
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#define ASCCON_FDE 0x00000200
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#define ASCCON_ERRCLK 0x00000400
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#define ASCCON_EMMASK 0x00001800
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#define ASCCON_EMOFFSET 11
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#define ASCCON_EM_ECHO_OFF 0x0
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#define ASCCON_EM_ECHO_AB 0x1
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#define ASCCON_EM_ECHO_ON 0x2
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#define ASCCON_LB 0x00002000
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#define ASCCON_ACO 0x00004000
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#define ASCCON_R 0x00008000
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#define ASCCON_PAL 0x00010000
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#define ASCCON_FEN 0x00020000
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#define ASCCON_RUEN 0x00040000
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#define ASCCON_ROEN 0x00080000
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#define ASCCON_TOEN 0x00100000
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#define ASCCON_BEN 0x00200000
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#define ASCCON_TXINV 0x01000000
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#define ASCCON_RXINV 0x02000000
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#define ASCCON_TXMSB 0x04000000
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#define ASCCON_RXMSB 0x08000000
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/* STATE register's bits and bitfields */
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#define ASCSTATE_REN 0x00000001
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#define ASCSTATE_PE 0x00010000
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#define ASCSTATE_FE 0x00020000
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#define ASCSTATE_RUE 0x00040000
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#define ASCSTATE_ROE 0x00080000
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#define ASCSTATE_TOE 0x00100000
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#define ASCSTATE_BE 0x00200000
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#define ASCSTATE_TXBVMASK 0x07000000
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#define ASCSTATE_TXBVOFFSET 24
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#define ASCSTATE_TXEOM 0x08000000
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#define ASCSTATE_RXBVMASK 0x70000000
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#define ASCSTATE_RXBVOFFSET 28
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#define ASCSTATE_RXEOM 0x80000000
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/* WHBSTATE register's bits and bitfields */
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#define ASCWHBSTATE_CLRREN 0x00000001
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#define ASCWHBSTATE_SETREN 0x00000002
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#define ASCWHBSTATE_CLRPE 0x00000004
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#define ASCWHBSTATE_CLRFE 0x00000008
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#define ASCWHBSTATE_CLRRUE 0x00000010
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#define ASCWHBSTATE_CLRROE 0x00000020
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#define ASCWHBSTATE_CLRTOE 0x00000040
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#define ASCWHBSTATE_CLRBE 0x00000080
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#define ASCWHBSTATE_SETPE 0x00000100
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#define ASCWHBSTATE_SETFE 0x00000200
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#define ASCWHBSTATE_SETRUE 0x00000400
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#define ASCWHBSTATE_SETROE 0x00000800
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#define ASCWHBSTATE_SETTOE 0x00001000
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#define ASCWHBSTATE_SETBE 0x00002000
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/* ABCON register's bits and bitfields */
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#define ASCABCON_ABEN 0x0001
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#define ASCABCON_AUREN 0x0002
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#define ASCABCON_ABSTEN 0x0004
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#define ASCABCON_ABDETEN 0x0008
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#define ASCABCON_FCDETEN 0x0010
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/* FDV register mask, offset and bitfields*/
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#define ASCFDV_VALUE_MASK 0x000001FF
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/* WHBABCON register's bits and bitfields */
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#define ASCWHBABCON_CLRABEN 0x0001
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#define ASCWHBABCON_SETABEN 0x0002
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/* ABSTAT register's bits and bitfields */
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#define ASCABSTAT_FCSDET 0x0001
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#define ASCABSTAT_FCCDET 0x0002
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#define ASCABSTAT_SCSDET 0x0004
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#define ASCABSTAT_SCCDET 0x0008
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#define ASCABSTAT_DETWAIT 0x0010
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/* WHBABSTAT register's bits and bitfields */
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#define ASCWHBABSTAT_CLRFCSDET 0x0001
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#define ASCWHBABSTAT_SETFCSDET 0x0002
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#define ASCWHBABSTAT_CLRFCCDET 0x0004
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#define ASCWHBABSTAT_SETFCCDET 0x0008
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#define ASCWHBABSTAT_CLRSCSDET 0x0010
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#define ASCWHBABSTAT_SETSCSDET 0x0020
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#define ASCWHBABSTAT_CLRSCCDET 0x0040
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#define ASCWHBABSTAT_SETSCCDET 0x0080
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#define ASCWHBABSTAT_CLRDETWAIT 0x0100
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#define ASCWHBABSTAT_SETDETWAIT 0x0200
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/* TXFCON register's bits and bitfields */
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#define ASCTXFCON_TXFIFO1 0x00000400
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#define ASCTXFCON_TXFEN 0x0001
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#define ASCTXFCON_TXFFLU 0x0002
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#define ASCTXFCON_TXFITLMASK 0x3F00
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#define ASCTXFCON_TXFITLOFF 8
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/* RXFCON register's bits and bitfields */
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#define ASCRXFCON_RXFIFO1 0x00000400
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#define ASCRXFCON_RXFEN 0x0001
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#define ASCRXFCON_RXFFLU 0x0002
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#define ASCRXFCON_RXFITLMASK 0x3F00
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#define ASCRXFCON_RXFITLOFF 8
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/* FSTAT register's bits and bitfields */
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#define ASCFSTAT_RXFFLMASK 0x003F
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFFLOFF 8
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typedef struct /* DanubeAsc_t */
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{
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volatile unsigned long asc_clc; /*0x0000*/
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volatile unsigned long asc_pisel; /*0x0004*/
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volatile unsigned long asc_id; /*0x0008*/
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volatile unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
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volatile unsigned long asc_con; /*0x0010*/
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volatile unsigned long asc_state; /*0x0014*/
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volatile unsigned long asc_whbstate; /*0x0018*/
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volatile unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
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volatile unsigned long asc_tbuf; /*0x0020*/
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volatile unsigned long asc_rbuf; /*0x0024*/
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volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
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volatile unsigned long asc_abcon; /*0x0030*/
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volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
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volatile unsigned long asc_whbabcon; /*0x0038*/
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volatile unsigned long asc_whbabstat; /* not used */ /*0x003C*/
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volatile unsigned long asc_rxfcon; /*0x0040*/
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volatile unsigned long asc_txfcon; /*0x0044*/
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volatile unsigned long asc_fstat; /*0x0048*/
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volatile unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
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volatile unsigned long asc_bg; /*0x0050*/
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volatile unsigned long asc_bg_timer; /*0x0054*/
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volatile unsigned long asc_fdv; /*0x0058*/
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volatile unsigned long asc_pmw; /*0x005C*/
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volatile unsigned long asc_modcon; /*0x0060*/
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volatile unsigned long asc_modstat; /*0x0064*/
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volatile unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
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volatile unsigned long asc_sfcc; /*0x0070*/
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volatile unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
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volatile unsigned long asc_eomcon; /*0x0080*/
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volatile unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
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volatile unsigned long asc_dmacon; /*0x00EC*/
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volatile unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
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volatile unsigned long asc_irnen; /*0x00F4*/
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volatile unsigned long asc_irnicr; /*0x00F8*/
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volatile unsigned long asc_irncr; /*0x00FC*/
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} DanubeAsc_t;
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int asc_init (void);
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void asc_puts (const char *s);
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void asc_putc (const char c);
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int asc_getc (void);
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#endif /* __ASC_H */
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