mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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4e216a7e48
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10275 3c298f89-4303-0410-b956-a3cf2f4a3e73
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/*
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* ADM5120 UART definitions
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*
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* This header file defines the hardware registers of the ADM5120 SoC
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* built-in UARTs.
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef _ADM5120_UART_H_
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#define _ADM5120_UART_H_
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#define UART_BAUDDIV(clk, baud) ((clk/(16 * (baud)))-1)
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#define UART_REG_DATA 0x00
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#define UART_REG_RSR 0x04
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#define UART_REG_ECR UART_REG_RSR
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#define UART_REG_LCRH 0x08
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#define UART_REG_LCRM 0x0C
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#define UART_REG_LCRL 0x10
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#define UART_REG_CTRL 0x14
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#define UART_REG_FLAG 0x18
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/* Receive Status Register bits */
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#define UART_RSR_FE ( 1 << 0 )
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#define UART_RSR_PE ( 1 << 1 )
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#define UART_RSR_BE ( 1 << 2 )
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#define UART_RSR_OE ( 1 << 3 )
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#define UART_RSR_ERR ( UART_RSR_FE | UART_RSR_PE | UART_RSR_BE )
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#define UART_ECR_ALL 0xFF
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/* Line Control High register bits */
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#define UART_LCRH_BRK ( 1 << 0 ) /* send break */
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#define UART_LCRH_PEN ( 1 << 1 ) /* parity enable */
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#define UART_LCRH_EPS ( 1 << 2 ) /* even parity select */
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#define UART_LCRH_STP1 ( 0 << 3 ) /* one stop bits select */
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#define UART_LCRH_STP2 ( 1 << 3 ) /* two stop bits select */
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#define UART_LCRH_FEN ( 1 << 4 ) /* FIFO enable */
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#define UART_LCRH_WLEN5 ( 0 << 5 )
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#define UART_LCRH_WLEN6 ( 1 << 5 )
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#define UART_LCRH_WLEN7 ( 2 << 5 )
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#define UART_LCRH_WLEN8 ( 3 << 5 )
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/* Control register bits */
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#define UART_CTRL_EN ( 1 << 0 )
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/* Flag register bits */
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#define UART_FLAG_CTS ( 1 << 0 )
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#define UART_FLAG_DSR ( 1 << 1 )
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#define UART_FLAG_DCD ( 1 << 2 )
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#define UART_FLAG_BUSY ( 1 << 3 )
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#define UART_FLAG_RXFE ( 1 << 4 )
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#define UART_FLAG_TXFF ( 1 << 5 )
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#define UART_FLAG_RXFF ( 1 << 6 )
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#define UART_FLAG_TXFE ( 1 << 7 )
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#endif /* _ADM5120_UART_H_ */
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