mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 04:11:54 +02:00
284a2e1864
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12311 3c298f89-4303-0410-b956-a3cf2f4a3e73
87 lines
3.3 KiB
Diff
87 lines
3.3 KiB
Diff
--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -403,6 +403,7 @@
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unsigned int irq;
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u32 baud_base, div;
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u32 i, n;
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+ unsigned int ccrev = cc->dev->id.revision;
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plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
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irq = ssb_mips_irq(cc->dev);
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@@ -414,14 +415,39 @@
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chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
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div = 1;
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} else {
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- if (cc->dev->id.revision >= 11) {
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+ if (ccrev == 20) {
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+ /* BCM5354 uses constant 25MHz clock */
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+ baud_base = 25000000;
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+ div = 48;
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+ /* Set the override bit so we don't divide it */
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+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
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+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
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+ | SSB_CHIPCO_CORECTL_UARTCLK0);
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+ } else if ((ccrev >= 11) && (ccrev != 15)) {
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/* Fixed ALP clock */
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baud_base = 20000000;
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ /* FIXME: baud_base is different for devices with a PMU */
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+ SSB_WARN_ON(1);
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+ }
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div = 1;
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+ if (ccrev >= 21) {
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+ /* Turn off UART clock before switching clocksource. */
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+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
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+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
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+ & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
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+ }
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/* Set the override bit so we don't divide it */
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chipco_write32(cc, SSB_CHIPCO_CORECTL,
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- SSB_CHIPCO_CORECTL_UARTCLK0);
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- } else if (cc->dev->id.revision >= 3) {
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+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
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+ | SSB_CHIPCO_CORECTL_UARTCLK0);
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+ if (ccrev >= 21) {
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+ /* Re-enable the UART clock. */
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+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
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+ chipco_read32(cc, SSB_CHIPCO_CORECTL)
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+ | SSB_CHIPCO_CORECTL_UARTCLKEN);
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+ }
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+ } else if (ccrev >= 3) {
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/* Internal backplane clock */
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baud_base = ssb_clockspeed(bus);
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div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
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@@ -433,7 +459,7 @@
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}
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/* Clock source depends on strapping if UartClkOverride is unset */
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- if ((cc->dev->id.revision > 0) &&
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+ if ((ccrev > 0) &&
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!(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
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if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
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SSB_CHIPCO_CAP_UARTCLK_INT) {
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@@ -455,7 +481,7 @@
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cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
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uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
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/* Offset changed at after rev 0 */
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- if (cc->dev->id.revision == 0)
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+ if (ccrev == 0)
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uart_regs += (i * 8);
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else
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uart_regs += (i * 256);
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -51,9 +51,12 @@
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#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
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#define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
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#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
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+#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
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+#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
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#define SSB_CHIPCO_CORECTL 0x0008
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#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
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#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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+#define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
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#define SSB_CHIPCO_BIST 0x000C
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#define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
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#define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
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