mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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33ec8951f8
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30410 3c298f89-4303-0410-b956-a3cf2f4a3e73
436 lines
12 KiB
Diff
436 lines
12 KiB
Diff
From 9f6d46372cf2a493eaeeffbefe0a796379f838fa Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Tue, 22 Nov 2011 22:54:32 +0100
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Subject: [PATCH 16/35] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs
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The Atheros AR71XX SoCs have a built-in PCI Host Controller.
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This patch adds a driver for that, and modifies the relevant
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files in order to allow to register the PCI controller from
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board specific setup.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
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v2: - add missing pci-ar71xx.c
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---
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arch/mips/ath79/Kconfig | 1 +
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arch/mips/include/asm/mach-ath79/pci.h | 6 +
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arch/mips/pci/Makefile | 1 +
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arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++
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4 files changed, 383 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/pci/pci-ar71xx.c
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -52,6 +52,7 @@ endmenu
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config SOC_AR71XX
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select USB_ARCH_HAS_EHCI
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select USB_ARCH_HAS_OHCI
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+ select HW_HAS_PCI
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def_bool n
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config SOC_AR724X
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--- a/arch/mips/include/asm/mach-ath79/pci.h
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+++ b/arch/mips/include/asm/mach-ath79/pci.h
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@@ -11,6 +11,12 @@
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#ifndef __ASM_MACH_ATH79_PCI_H
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#define __ASM_MACH_ATH79_PCI_H
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+#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
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+int ar71xx_pcibios_init(void);
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+#else
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+static inline int ar71xx_pcibios_init(void) { return 0 };
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+#endif
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+
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#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
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int ar724x_pcibios_init(int irq);
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#else
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
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obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
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ops-bcm63xx.o
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obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
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+obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
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obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
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#
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--- /dev/null
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+++ b/arch/mips/pci/pci-ar71xx.c
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@@ -0,0 +1,375 @@
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+/*
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+ * Atheros AR71xx PCI host controller driver
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+ *
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * Parts of this file are based on Atheros' 2.6.15 BSP
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/resource.h>
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+#include <linux/types.h>
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+#include <linux/delay.h>
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+#include <linux/bitops.h>
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+#include <linux/pci.h>
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+#include <linux/pci_regs.h>
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+#include <linux/interrupt.h>
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+
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/pci.h>
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+
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+#define AR71XX_PCI_MEM_BASE 0x10000000
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+#define AR71XX_PCI_MEM_SIZE 0x08000000
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+
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+#define AR71XX_PCI_WIN0_OFFS 0x10000000
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+#define AR71XX_PCI_WIN1_OFFS 0x11000000
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+#define AR71XX_PCI_WIN2_OFFS 0x12000000
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+#define AR71XX_PCI_WIN3_OFFS 0x13000000
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+#define AR71XX_PCI_WIN4_OFFS 0x14000000
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+#define AR71XX_PCI_WIN5_OFFS 0x15000000
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+#define AR71XX_PCI_WIN6_OFFS 0x16000000
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+#define AR71XX_PCI_WIN7_OFFS 0x07000000
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+
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+#define AR71XX_PCI_CFG_BASE \
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+ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
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+#define AR71XX_PCI_CFG_SIZE 0x100
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+
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+#define AR71XX_PCI_REG_CRP_AD_CBE 0x00
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+#define AR71XX_PCI_REG_CRP_WRDATA 0x04
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+#define AR71XX_PCI_REG_CRP_RDDATA 0x08
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+#define AR71XX_PCI_REG_CFG_AD 0x0c
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+#define AR71XX_PCI_REG_CFG_CBE 0x10
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+#define AR71XX_PCI_REG_CFG_WRDATA 0x14
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+#define AR71XX_PCI_REG_CFG_RDDATA 0x18
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+#define AR71XX_PCI_REG_PCI_ERR 0x1c
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+#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20
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+#define AR71XX_PCI_REG_AHB_ERR 0x24
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+#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28
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+
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+#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000
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+#define AR71XX_PCI_CRP_CMD_READ 0x00000000
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+#define AR71XX_PCI_CFG_CMD_READ 0x0000000a
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+#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b
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+
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+#define AR71XX_PCI_INT_CORE BIT(4)
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+#define AR71XX_PCI_INT_DEV2 BIT(2)
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+#define AR71XX_PCI_INT_DEV1 BIT(1)
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+#define AR71XX_PCI_INT_DEV0 BIT(0)
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+
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+#define AR71XX_PCI_IRQ_COUNT 5
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+
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+static DEFINE_SPINLOCK(ar71xx_pci_lock);
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+static void __iomem *ar71xx_pcicfg_base;
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+
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+/* Byte lane enable bits */
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+static const u8 ar71xx_pci_ble_table[4][4] = {
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+ {0x0, 0xf, 0xf, 0xf},
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+ {0xe, 0xd, 0xb, 0x7},
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+ {0xc, 0xf, 0x3, 0xf},
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+ {0xf, 0xf, 0xf, 0xf},
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+};
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+
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+static const u32 ar71xx_pci_read_mask[8] = {
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+ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
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+};
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+
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+static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
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+{
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+ u32 t;
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+
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+ t = ar71xx_pci_ble_table[size & 3][where & 3];
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+ BUG_ON(t == 0xf);
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+ t <<= (local) ? 20 : 4;
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+
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+ return t;
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+}
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+
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+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
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+ int where)
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+{
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+ u32 ret;
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+
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+ if (!bus->number) {
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+ /* type 0 */
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+ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
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+ (where & ~3);
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+ } else {
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+ /* type 1 */
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+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
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+ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
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+ }
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+
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+ return ret;
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+}
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+
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+static int ar71xx_pci_check_error(int quiet)
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+{
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+ void __iomem *base = ar71xx_pcicfg_base;
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+ u32 pci_err;
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+ u32 ahb_err;
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+
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+ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
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+ if (pci_err) {
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+ if (!quiet) {
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+ u32 addr;
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+
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+ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
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+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
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+ "PCI", pci_err, addr);
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+ }
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+
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+ /* clear PCI error status */
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+ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
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+ }
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+
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+ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
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+ if (ahb_err) {
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+ if (!quiet) {
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+ u32 addr;
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+
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+ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
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+ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
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+ "AHB", ahb_err, addr);
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+ }
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+
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+ /* clear AHB error status */
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+ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
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+ }
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+
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+ return !!(ahb_err | pci_err);
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+}
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+
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+static inline void ar71xx_pci_local_write(int where, int size, u32 value)
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+{
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+ void __iomem *base = ar71xx_pcicfg_base;
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+ u32 ad_cbe;
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+
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+ value = value << (8 * (where & 3));
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+
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+ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
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+ ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
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+
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+ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
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+ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
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+}
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+
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+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
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+ unsigned int devfn,
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+ int where, int size, u32 cmd)
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+{
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+ void __iomem *base = ar71xx_pcicfg_base;
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+ u32 addr;
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+
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+ addr = ar71xx_pci_bus_addr(bus, devfn, where);
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+
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+ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
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+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
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+ base + AR71XX_PCI_REG_CFG_CBE);
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+
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+ return ar71xx_pci_check_error(1);
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+}
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+
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+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *value)
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+{
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+ void __iomem *base = ar71xx_pcicfg_base;
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+ unsigned long flags;
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+ u32 data;
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+ int err;
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+ int ret;
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+
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+ ret = PCIBIOS_SUCCESSFUL;
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+ data = ~0;
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+
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+ spin_lock_irqsave(&ar71xx_pci_lock, flags);
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+
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+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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+ AR71XX_PCI_CFG_CMD_READ);
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+ if (err)
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+ ret = PCIBIOS_DEVICE_NOT_FOUND;
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+ else
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+ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
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+
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+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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+
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+ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
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+
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+ return ret;
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+}
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+
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+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 value)
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+{
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+ void __iomem *base = ar71xx_pcicfg_base;
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+ unsigned long flags;
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+ int err;
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+ int ret;
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+
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+ value = value << (8 * (where & 3));
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+ ret = PCIBIOS_SUCCESSFUL;
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+
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+ spin_lock_irqsave(&ar71xx_pci_lock, flags);
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+
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+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
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+ AR71XX_PCI_CFG_CMD_WRITE);
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+ if (err)
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+ ret = PCIBIOS_DEVICE_NOT_FOUND;
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+ else
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+ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
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+
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+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
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+
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+ return ret;
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+}
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+
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+static struct pci_ops ar71xx_pci_ops = {
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+ .read = ar71xx_pci_read_config,
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+ .write = ar71xx_pci_write_config,
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+};
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+
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+static struct resource ar71xx_pci_io_resource = {
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+ .name = "PCI IO space",
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+ .start = 0,
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+ .end = 0,
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+ .flags = IORESOURCE_IO,
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+};
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+
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+static struct resource ar71xx_pci_mem_resource = {
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+ .name = "PCI memory space",
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+ .start = AR71XX_PCI_MEM_BASE,
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+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
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+ .flags = IORESOURCE_MEM
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+};
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+
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+static struct pci_controller ar71xx_pci_controller = {
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+ .pci_ops = &ar71xx_pci_ops,
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+ .mem_resource = &ar71xx_pci_mem_resource,
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+ .io_resource = &ar71xx_pci_io_resource,
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+};
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+
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+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ void __iomem *base = ath79_reset_base;
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+ u32 pending;
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+
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+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
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+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+
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+ if (pending & AR71XX_PCI_INT_DEV0)
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+ generic_handle_irq(ATH79_PCI_IRQ(0));
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+
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+ else if (pending & AR71XX_PCI_INT_DEV1)
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+ generic_handle_irq(ATH79_PCI_IRQ(1));
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+
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+ else if (pending & AR71XX_PCI_INT_DEV2)
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+ generic_handle_irq(ATH79_PCI_IRQ(2));
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+
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+ else if (pending & AR71XX_PCI_INT_CORE)
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+ generic_handle_irq(ATH79_PCI_IRQ(4));
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+
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+ else
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+ spurious_interrupt();
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+}
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+
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+static void ar71xx_pci_irq_unmask(struct irq_data *d)
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+{
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+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
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+ void __iomem *base = ath79_reset_base;
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+ u32 t;
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+
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+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+
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+ /* flush write */
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+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+}
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+
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+static void ar71xx_pci_irq_mask(struct irq_data *d)
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+{
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+ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
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+ void __iomem *base = ath79_reset_base;
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+ u32 t;
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+
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+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+
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+ /* flush write */
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+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+}
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+
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+static struct irq_chip ar71xx_pci_irq_chip = {
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+ .name = "AR71XX PCI",
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+ .irq_mask = ar71xx_pci_irq_mask,
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+ .irq_unmask = ar71xx_pci_irq_unmask,
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+ .irq_mask_ack = ar71xx_pci_irq_mask,
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+};
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+
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+static __init void ar71xx_pci_irq_init(void)
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+{
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+ void __iomem *base = ath79_reset_base;
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+ int i;
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+
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+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
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+
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+ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
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+
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+ for (i = ATH79_PCI_IRQ_BASE;
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+ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
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+ handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
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+}
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+
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+static __init void ar71xx_pci_reset(void)
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+{
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+ void __iomem *ddr_base = ath79_ddr_base;
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+
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+ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
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+ mdelay(100);
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+
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+ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
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+ mdelay(100);
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+
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+ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
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+ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
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+ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
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+ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
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+ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
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+ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
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+ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
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+ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
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+
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+ mdelay(100);
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+}
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+
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+__init int ar71xx_pcibios_init(void)
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+{
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+ u32 t;
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+
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+ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
|
|
+ if (ar71xx_pcicfg_base == NULL)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ ar71xx_pci_reset();
|
|
+
|
|
+ /* setup COMMAND register */
|
|
+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
|
|
+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
|
|
+ ar71xx_pci_local_write(PCI_COMMAND, 4, t);
|
|
+
|
|
+ /* clear bus errors */
|
|
+ ar71xx_pci_check_error(1);
|
|
+
|
|
+ ar71xx_pci_irq_init();
|
|
+
|
|
+ register_pci_controller(&ar71xx_pci_controller);
|
|
+
|
|
+ return 0;
|
|
+}
|