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git://projects.qi-hardware.com/openwrt-xburst.git
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33ec8951f8
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30410 3c298f89-4303-0410-b956-a3cf2f4a3e73
108 lines
3.4 KiB
Diff
108 lines
3.4 KiB
Diff
From 2d832612094b5592641364773c5ab2a3658f7120 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 11 Dec 2011 18:34:13 +0100
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Subject: [PATCH 31/35] MIPS: ath79: add USB platform setup code for AR934X
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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arch/mips/ath79/dev-usb.c | 28 +++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 35 ++++++++++++++++++++++++
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2 files changed, 63 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -180,6 +180,32 @@ static void __init ar933x_usb_setup(void
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platform_device_register(&ath79_ehci_device);
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}
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+static void __init ar934x_usb_setup(void)
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+{
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
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+ return;
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+
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+ ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
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+ udelay(1000);
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+
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+ ath79_device_reset_set(AR934X_RESET_USB_PHY);
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+ udelay(1000);
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+
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+ ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
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+ udelay(1000);
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+
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+ ath79_device_reset_set(AR934X_RESET_USB_HOST);
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+ udelay(1000);
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+
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+ ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
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+ ath79_ehci_resources[0].end = AR934X_EHCI_BASE + AR934X_EHCI_SIZE - 1;
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+ ath79_ehci_device.name = "ar934x-ehci";
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+ platform_device_register(&ath79_ehci_device);
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+}
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+
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void __init ath79_register_usb(void)
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{
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if (soc_is_ar71xx())
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@@ -192,6 +218,8 @@ void __init ath79_register_usb(void)
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ar913x_usb_setup();
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else if (soc_is_ar933x())
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ar933x_usb_setup();
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+ else if (soc_is_ar934x())
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+ ar934x_usb_setup();
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else
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BUG();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -63,6 +63,8 @@
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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+#define AR934X_EHCI_BASE 0x1b000000
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+#define AR934X_EHCI_SIZE 0x1000
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/*
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* DDR_CTRL block
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@@ -288,6 +290,39 @@
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define AR934X_RESET_HOST BIT(31)
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+#define AR934X_RESET_SLIC BIT(30)
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+#define AR934X_RESET_HDMA BIT(29)
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+#define AR934X_RESET_EXTERNAL BIT(28)
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+#define AR934X_RESET_RTC BIT(27)
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+#define AR934X_RESET_PCIE_EP_INT BIT(26)
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+#define AR934X_RESET_CHKSUM_ACC BIT(25)
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+#define AR934X_RESET_FULL_CHIP BIT(24)
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+#define AR934X_RESET_GE1_MDIO BIT(23)
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+#define AR934X_RESET_GE0_MDIO BIT(22)
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+#define AR934X_RESET_CPU_NMI BIT(21)
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+#define AR934X_RESET_CPU_COLD BIT(20)
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+#define AR934X_RESET_HOST_RESET_INT BIT(19)
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+#define AR934X_RESET_PCIE_EP BIT(18)
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+#define AR934X_RESET_UART1 BIT(17)
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+#define AR934X_RESET_DDR BIT(16)
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+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
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+#define AR934X_RESET_NANDF BIT(14)
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+#define AR934X_RESET_GE1_MAC BIT(13)
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+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
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+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
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+#define AR934X_RESET_HOST_DMA_INT BIT(10)
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+#define AR934X_RESET_GE0_MAC BIT(9)
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+#define AR934X_RESET_ETH_SIWTCH BIT(8)
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+#define AR934X_RESET_PCIE_PHY BIT(7)
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+#define AR934X_RESET_PCIE BIT(6)
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+#define AR934X_RESET_USB_HOST BIT(5)
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+#define AR934X_RESET_USB_PHY BIT(4)
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+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
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+#define AR934X_RESET_LUT BIT(2)
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+#define AR934X_RESET_MBOX BIT(1)
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+#define AR934X_RESET_I2S BIT(0)
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+
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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