mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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00f29ce9a4
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34162 3c298f89-4303-0410-b956-a3cf2f4a3e73
653 lines
21 KiB
C
653 lines
21 KiB
C
/* ==========================================================================
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* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
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* $Revision: #45 $
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* $Date: 2008/07/15 $
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* $Change: 1064918 $
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*
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* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
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* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
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* otherwise expressly agreed to in writing between Synopsys and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product under
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* any End User Software License Agreement or Agreement for Licensed Product
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* with Synopsys or any supplement thereto. You are permitted to use and
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* redistribute this Software in source and binary forms, with or without
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* modification, provided that redistributions of source code must retain this
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* notice. You may not view, use, disclose, copy or distribute this file or
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* any information contained herein except pursuant to this license grant from
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* Synopsys. If you do not agree with this notice, including the disclaimer
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* below, then you are not authorized to use the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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* ========================================================================== */
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#ifndef DWC_DEVICE_ONLY
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#ifndef __DWC_HCD_H__
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#define __DWC_HCD_H__
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#include <linux/list.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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struct dwc_otg_device;
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#include "otg_cil.h"
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/**
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* @file
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*
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* This file contains the structures, constants, and interfaces for
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* the Host Contoller Driver (HCD).
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*
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* The Host Controller Driver (HCD) is responsible for translating requests
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* from the USB Driver into the appropriate actions on the DWC_otg controller.
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* It isolates the USBD from the specifics of the controller by providing an
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* API to the USBD.
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*/
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/**
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* Phases for control transfers.
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*/
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typedef enum dwc_otg_control_phase {
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DWC_OTG_CONTROL_SETUP,
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DWC_OTG_CONTROL_DATA,
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DWC_OTG_CONTROL_STATUS
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} dwc_otg_control_phase_e;
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/** Transaction types. */
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typedef enum dwc_otg_transaction_type {
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DWC_OTG_TRANSACTION_NONE,
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DWC_OTG_TRANSACTION_PERIODIC,
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DWC_OTG_TRANSACTION_NON_PERIODIC,
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DWC_OTG_TRANSACTION_ALL
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} dwc_otg_transaction_type_e;
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/**
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* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
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* interrupt, or isochronous transfer. A single QTD is created for each URB
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* (of one of these types) submitted to the HCD. The transfer associated with
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* a QTD may require one or multiple transactions.
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*
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* A QTD is linked to a Queue Head, which is entered in either the
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* non-periodic or periodic schedule for execution. When a QTD is chosen for
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* execution, some or all of its transactions may be executed. After
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* execution, the state of the QTD is updated. The QTD may be retired if all
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* its transactions are complete or if an error occurred. Otherwise, it
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* remains in the schedule so more transactions can be executed later.
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*/
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typedef struct dwc_otg_qtd {
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/**
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* Determines the PID of the next data packet for the data phase of
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* control transfers. Ignored for other transfer types.<br>
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* One of the following values:
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* - DWC_OTG_HC_PID_DATA0
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* - DWC_OTG_HC_PID_DATA1
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*/
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uint8_t data_toggle;
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/** Current phase for control transfers (Setup, Data, or Status). */
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dwc_otg_control_phase_e control_phase;
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/** Keep track of the current split type
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* for FS/LS endpoints on a HS Hub */
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uint8_t complete_split;
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/** How many bytes transferred during SSPLIT OUT */
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uint32_t ssplit_out_xfer_count;
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/**
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* Holds the number of bus errors that have occurred for a transaction
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* within this transfer.
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*/
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uint8_t error_count;
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/**
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* Index of the next frame descriptor for an isochronous transfer. A
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* frame descriptor describes the buffer position and length of the
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* data to be transferred in the next scheduled (micro)frame of an
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* isochronous transfer. It also holds status for that transaction.
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* The frame index starts at 0.
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*/
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int isoc_frame_index;
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/** Position of the ISOC split on full/low speed */
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uint8_t isoc_split_pos;
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/** Position of the ISOC split in the buffer for the current frame */
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uint16_t isoc_split_offset;
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/** URB for this transfer */
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struct urb *urb;
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/** This list of QTDs */
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struct list_head qtd_list_entry;
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} dwc_otg_qtd_t;
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/**
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* A Queue Head (QH) holds the static characteristics of an endpoint and
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* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
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* be entered in either the non-periodic or periodic schedule.
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*/
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typedef struct dwc_otg_qh {
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/**
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* Endpoint type.
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* One of the following values:
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* - USB_ENDPOINT_XFER_CONTROL
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* - USB_ENDPOINT_XFER_ISOC
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* - USB_ENDPOINT_XFER_BULK
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* - USB_ENDPOINT_XFER_INT
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*/
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uint8_t ep_type;
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uint8_t ep_is_in;
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/** wMaxPacketSize Field of Endpoint Descriptor. */
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uint16_t maxp;
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/**
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* Determines the PID of the next data packet for non-control
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* transfers. Ignored for control transfers.<br>
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* One of the following values:
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* - DWC_OTG_HC_PID_DATA0
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* - DWC_OTG_HC_PID_DATA1
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*/
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uint8_t data_toggle;
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/** Ping state if 1. */
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uint8_t ping_state;
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/**
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* List of QTDs for this QH.
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*/
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struct list_head qtd_list;
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/** Host channel currently processing transfers for this QH. */
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dwc_hc_t *channel;
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/** QTD currently assigned to a host channel for this QH. */
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dwc_otg_qtd_t *qtd_in_process;
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/** Full/low speed endpoint on high-speed hub requires split. */
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uint8_t do_split;
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/** @name Periodic schedule information */
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/** @{ */
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/** Bandwidth in microseconds per (micro)frame. */
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uint8_t usecs;
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/** Interval between transfers in (micro)frames. */
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uint16_t interval;
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/**
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* (micro)frame to initialize a periodic transfer. The transfer
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* executes in the following (micro)frame.
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*/
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uint16_t sched_frame;
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/** (micro)frame at which last start split was initialized. */
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uint16_t start_split_frame;
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u16 speed;
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u16 frame_usecs[8];
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/** @} */
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/** Entry for QH in either the periodic or non-periodic schedule. */
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struct list_head qh_list_entry;
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} dwc_otg_qh_t;
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/**
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* This structure holds the state of the HCD, including the non-periodic and
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* periodic schedules.
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*/
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typedef struct dwc_otg_hcd {
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/** The DWC otg device pointer */
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struct dwc_otg_device *otg_dev;
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/** DWC OTG Core Interface Layer */
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dwc_otg_core_if_t *core_if;
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/** Internal DWC HCD Flags */
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volatile union dwc_otg_hcd_internal_flags {
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uint32_t d32;
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struct {
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unsigned port_connect_status_change : 1;
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unsigned port_connect_status : 1;
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unsigned port_reset_change : 1;
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unsigned port_enable_change : 1;
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unsigned port_suspend_change : 1;
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unsigned port_over_current_change : 1;
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unsigned reserved : 27;
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} b;
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} flags;
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/**
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* Inactive items in the non-periodic schedule. This is a list of
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* Queue Heads. Transfers associated with these Queue Heads are not
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* currently assigned to a host channel.
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*/
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struct list_head non_periodic_sched_inactive;
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/**
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* Active items in the non-periodic schedule. This is a list of
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* Queue Heads. Transfers associated with these Queue Heads are
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* currently assigned to a host channel.
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*/
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struct list_head non_periodic_sched_active;
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/**
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* Pointer to the next Queue Head to process in the active
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* non-periodic schedule.
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*/
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struct list_head *non_periodic_qh_ptr;
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/**
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* Inactive items in the periodic schedule. This is a list of QHs for
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* periodic transfers that are _not_ scheduled for the next frame.
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* Each QH in the list has an interval counter that determines when it
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* needs to be scheduled for execution. This scheduling mechanism
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* allows only a simple calculation for periodic bandwidth used (i.e.
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* must assume that all periodic transfers may need to execute in the
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* same frame). However, it greatly simplifies scheduling and should
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* be sufficient for the vast majority of OTG hosts, which need to
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* connect to a small number of peripherals at one time.
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*
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* Items move from this list to periodic_sched_ready when the QH
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* interval counter is 0 at SOF.
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*/
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struct list_head periodic_sched_inactive;
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/**
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* List of periodic QHs that are ready for execution in the next
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* frame, but have not yet been assigned to host channels.
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*
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* Items move from this list to periodic_sched_assigned as host
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* channels become available during the current frame.
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*/
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struct list_head periodic_sched_ready;
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/**
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* List of periodic QHs to be executed in the next frame that are
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* assigned to host channels.
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*
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* Items move from this list to periodic_sched_queued as the
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* transactions for the QH are queued to the DWC_otg controller.
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*/
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struct list_head periodic_sched_assigned;
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/**
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* List of periodic QHs that have been queued for execution.
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*
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* Items move from this list to either periodic_sched_inactive or
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* periodic_sched_ready when the channel associated with the transfer
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* is released. If the interval for the QH is 1, the item moves to
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* periodic_sched_ready because it must be rescheduled for the next
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* frame. Otherwise, the item moves to periodic_sched_inactive.
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*/
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struct list_head periodic_sched_queued;
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/**
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* Total bandwidth claimed so far for periodic transfers. This value
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* is in microseconds per (micro)frame. The assumption is that all
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* periodic transfers may occur in the same (micro)frame.
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*/
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uint16_t periodic_usecs;
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/*
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* Total bandwidth claimed so far for all periodic transfers
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* in a frame.
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* This will include a mixture of HS and FS transfers.
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* Units are microseconds per (micro)frame.
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* We have a budget per frame and have to schedule
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* transactions accordingly.
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* Watch out for the fact that things are actually scheduled for the
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* "next frame".
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*/
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u16 frame_usecs[8];
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/**
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* Frame number read from the core at SOF. The value ranges from 0 to
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* DWC_HFNUM_MAX_FRNUM.
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*/
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uint16_t frame_number;
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/**
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* Free host channels in the controller. This is a list of
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* dwc_hc_t items.
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*/
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struct list_head free_hc_list;
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/**
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* Number of host channels assigned to periodic transfers. Currently
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* assuming that there is a dedicated host channel for each periodic
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* transaction and at least one host channel available for
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* non-periodic transactions.
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*/
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int periodic_channels;
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/**
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* Number of host channels assigned to non-periodic transfers.
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*/
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int non_periodic_channels;
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/**
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* Array of pointers to the host channel descriptors. Allows accessing
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* a host channel descriptor given the host channel number. This is
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* useful in interrupt handlers.
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*/
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dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS];
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/**
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* Buffer to use for any data received during the status phase of a
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* control transfer. Normally no data is transferred during the status
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* phase. This buffer is used as a bit bucket.
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*/
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uint8_t *status_buf;
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/**
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* DMA address for status_buf.
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*/
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dma_addr_t status_buf_dma;
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#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
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/**
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* Structure to allow starting the HCD in a non-interrupt context
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* during an OTG role change.
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*/
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struct delayed_work start_work;
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/**
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* Connection timer. An OTG host must display a message if the device
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* does not connect. Started when the VBus power is turned on via
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* sysfs attribute "buspower".
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*/
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struct timer_list conn_timer;
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/* Tasket to do a reset */
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struct tasklet_struct *reset_tasklet;
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/* */
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spinlock_t lock;
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#ifdef DEBUG
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uint32_t frrem_samples;
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uint64_t frrem_accum;
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uint32_t hfnum_7_samples_a;
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uint64_t hfnum_7_frrem_accum_a;
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uint32_t hfnum_0_samples_a;
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uint64_t hfnum_0_frrem_accum_a;
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uint32_t hfnum_other_samples_a;
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uint64_t hfnum_other_frrem_accum_a;
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uint32_t hfnum_7_samples_b;
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uint64_t hfnum_7_frrem_accum_b;
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uint32_t hfnum_0_samples_b;
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uint64_t hfnum_0_frrem_accum_b;
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uint32_t hfnum_other_samples_b;
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uint64_t hfnum_other_frrem_accum_b;
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#endif
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} dwc_otg_hcd_t;
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/** Gets the dwc_otg_hcd from a struct usb_hcd */
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static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
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{
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return (dwc_otg_hcd_t *)(hcd->hcd_priv);
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}
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/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
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static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd)
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{
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return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv);
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}
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/** @name HCD Create/Destroy Functions */
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/** @{ */
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extern int dwc_otg_hcd_init(struct platform_device *pdev);
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extern void dwc_otg_hcd_remove(struct platform_device *pdev);
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/** @} */
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/** @name Linux HC Driver API Functions */
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/** @{ */
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extern int dwc_otg_hcd_start(struct usb_hcd *hcd);
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extern void dwc_otg_hcd_stop(struct usb_hcd *hcd);
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extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd);
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extern void dwc_otg_hcd_free(struct usb_hcd *hcd);
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extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd,
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// struct usb_host_endpoint *ep,
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struct urb *urb,
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gfp_t mem_flags
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);
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extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd,
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struct urb *urb, int status);
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extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd,
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struct usb_host_endpoint *ep);
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extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
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extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd,
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char *buf);
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extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd,
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u16 typeReq,
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u16 wValue,
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u16 wIndex,
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char *buf,
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u16 wLength);
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/** @} */
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/** @name Transaction Execution Functions */
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/** @{ */
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extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd);
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extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
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dwc_otg_transaction_type_e tr_type);
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extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *urb,
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int status);
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/** @} */
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/** @name Interrupt Handler Functions */
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/** @{ */
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extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num);
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extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *dwc_otg_hcd);
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/** @} */
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/** @name Schedule Queue Functions */
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/** @{ */
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/* Implemented in dwc_otg_hcd_queue.c */
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extern int init_hcd_usecs(dwc_otg_hcd_t *hcd);
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extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t *hcd, struct urb *urb);
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extern void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb);
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extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
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extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
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extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
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extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit);
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/** Remove and free a QH */
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static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t *hcd,
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dwc_otg_qh_t *qh)
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{
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dwc_otg_hcd_qh_remove(hcd, qh);
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dwc_otg_hcd_qh_free(hcd, qh);
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}
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/** Allocates memory for a QH structure.
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* @return Returns the memory allocate or NULL on error. */
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static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
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{
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return (dwc_otg_qh_t *) kmalloc(sizeof(dwc_otg_qh_t), GFP_KERNEL);
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}
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extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(struct urb *urb);
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extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t *qtd, struct urb *urb);
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extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd);
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/** Allocates memory for a QTD structure.
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* @return Returns the memory allocate or NULL on error. */
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static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
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{
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return (dwc_otg_qtd_t *) kmalloc(sizeof(dwc_otg_qtd_t), GFP_KERNEL);
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}
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/** Frees the memory for a QTD structure. QTD should already be removed from
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* list.
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* @param[in] qtd QTD to free.*/
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static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t *qtd)
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{
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kfree(qtd);
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}
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/** Remove and free a QTD */
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static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd)
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{
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list_del(&qtd->qtd_list_entry);
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dwc_otg_hcd_qtd_free(qtd);
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}
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/** @} */
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/** @name Internal Functions */
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/** @{ */
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dwc_otg_qh_t *dwc_urb_to_qh(struct urb *urb);
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void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd);
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void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd);
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/** @} */
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/** Gets the usb_host_endpoint associated with an URB. */
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static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
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{
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struct usb_device *dev = urb->dev;
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int ep_num = usb_pipeendpoint(urb->pipe);
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if (usb_pipein(urb->pipe))
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return dev->ep_in[ep_num];
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else
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return dev->ep_out[ep_num];
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}
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/**
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* Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
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* qualified with its direction (possible 32 endpoints per device).
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*/
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#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
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((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
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/** Gets the QH that contains the list_head */
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#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
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/** Gets the QTD that contains the list_head */
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#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
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/** Check if QH is non-periodic */
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#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \
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(_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL))
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/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
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#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
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/** Packet size for any kind of endpoint descriptor */
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#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
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/**
|
|
* Returns true if _frame1 is less than or equal to _frame2. The comparison is
|
|
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
|
|
* frame number when the max frame number is reached.
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|
*/
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|
static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
|
|
{
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|
return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
|
|
(DWC_HFNUM_MAX_FRNUM >> 1);
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|
}
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|
|
|
/**
|
|
* Returns true if _frame1 is greater than _frame2. The comparison is done
|
|
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
|
|
* number when the max frame number is reached.
|
|
*/
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static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
|
|
{
|
|
return (frame1 != frame2) &&
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|
(((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
|
|
(DWC_HFNUM_MAX_FRNUM >> 1));
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|
}
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|
|
|
/**
|
|
* Increments _frame by the amount specified by _inc. The addition is done
|
|
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
|
|
*/
|
|
static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
|
|
{
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|
return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
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|
}
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|
|
|
static inline uint16_t dwc_full_frame_num(uint16_t frame)
|
|
{
|
|
return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
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|
}
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|
|
|
static inline uint16_t dwc_micro_frame_num(uint16_t frame)
|
|
{
|
|
return frame & 0x7;
|
|
}
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|
|
|
#ifdef DEBUG
|
|
/**
|
|
* Macro to sample the remaining PHY clocks left in the current frame. This
|
|
* may be used during debugging to determine the average time it takes to
|
|
* execute sections of code. There are two possible sample points, "a" and
|
|
* "b", so the _letter argument must be one of these values.
|
|
*
|
|
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
|
|
* example, "cat /sys/devices/lm0/hcd_frrem".
|
|
*/
|
|
#define dwc_sample_frrem(_hcd, _qh, _letter) \
|
|
{ \
|
|
hfnum_data_t hfnum; \
|
|
dwc_otg_qtd_t *qtd; \
|
|
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
|
|
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
|
|
hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
|
|
switch (hfnum.b.frnum & 0x7) { \
|
|
case 7: \
|
|
_hcd->hfnum_7_samples_##_letter++; \
|
|
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
|
|
break; \
|
|
case 0: \
|
|
_hcd->hfnum_0_samples_##_letter++; \
|
|
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
|
|
break; \
|
|
default: \
|
|
_hcd->hfnum_other_samples_##_letter++; \
|
|
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
|
|
break; \
|
|
} \
|
|
} \
|
|
}
|
|
#else
|
|
#define dwc_sample_frrem(_hcd, _qh, _letter)
|
|
#endif
|
|
#endif
|
|
#endif /* DWC_DEVICE_ONLY */
|