mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 04:44:03 +02:00
5a3f291f1a
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6334 3c298f89-4303-0410-b956-a3cf2f4a3e73
565 lines
12 KiB
C
565 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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*/
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/*
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* Platform devices for Atheros SoCs
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*/
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#include <linux/autoconf.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "ar531x.h"
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static int is_5315 = 0;
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static struct resource ar5315_eth_res[] = {
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{
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.name = "eth0_membase",
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.flags = IORESOURCE_MEM,
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.start = AR5315_ENET0,
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.end = AR5315_ENET0 + 0x2000,
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},
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{
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.name = "eth0_irq",
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.flags = IORESOURCE_IRQ,
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.start = AR5315_IRQ_ENET0_INTRS,
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.end = AR5315_IRQ_ENET0_INTRS,
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},
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};
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static struct ar531x_eth ar5315_eth_data = {
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.phy = 1,
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.mac = 0,
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.reset_base = AR5315_RESET,
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.reset_mac = AR5315_RESET_ENET0,
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.reset_phy = AR5315_RESET_EPHY0,
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.phy_base = AR5315_ENET0
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};
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static struct platform_device ar5315_eth = {
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.id = 0,
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.name = "ar531x-eth",
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.dev.platform_data = &ar5315_eth_data,
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.resource = ar5315_eth_res,
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.num_resources = ARRAY_SIZE(ar5315_eth_res)
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};
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static struct platform_device ar5315_wmac = {
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.id = 0,
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.name = "ar531x-wmac",
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/* FIXME: add resources */
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};
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static struct resource ar5315_spiflash_res[] = {
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{
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.name = "flash_base",
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.flags = IORESOURCE_MEM,
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.start = KSEG1ADDR(AR5315_SPI_READ),
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.end = KSEG1ADDR(AR5315_SPI_READ) + 0x800000,
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},
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{
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.name = "flash_regs",
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.flags = IORESOURCE_MEM,
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.start = 0x11300000,
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.end = 0x11300012,
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},
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};
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static struct platform_device ar5315_spiflash = {
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.id = 0,
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.name = "spiflash",
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.resource = ar5315_spiflash_res,
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.num_resources = ARRAY_SIZE(ar5315_spiflash_res)
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};
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static __initdata struct platform_device *ar5315_devs[4];
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static void *flash_regs;
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static inline __u32 spiflash_regread32(int reg)
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{
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volatile __u32 *data = (__u32 *)(flash_regs + reg);
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return (*data);
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}
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static inline void spiflash_regwrite32(int reg, __u32 data)
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{
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volatile __u32 *addr = (__u32 *)(flash_regs + reg);
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*addr = data;
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}
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#define SPI_FLASH_CTL 0x00
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#define SPI_FLASH_OPCODE 0x04
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#define SPI_FLASH_DATA 0x08
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static __u8 spiflash_probe(void)
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{
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__u32 reg;
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do {
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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spiflash_regwrite32(SPI_FLASH_OPCODE, 0xab);
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | 4 |
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(1 << 4) | SPI_CTL_START;
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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do {
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
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reg &= 0xff;
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return (u8) reg;
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}
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#define STM_8MBIT_SIGNATURE 0x13
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#define STM_16MBIT_SIGNATURE 0x14
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#define STM_32MBIT_SIGNATURE 0x15
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#define STM_64MBIT_SIGNATURE 0x16
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#define STM_128MBIT_SIGNATURE 0x17
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static char __init *ar5315_flash_limit(void)
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{
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u8 sig;
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u32 flash_size = 0;
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/* probe the flash chip size */
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flash_regs = ioremap_nocache(ar5315_spiflash_res[1].start, ar5315_spiflash_res[1].end - ar5315_spiflash_res[1].start);
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sig = spiflash_probe();
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iounmap(flash_regs);
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switch(sig) {
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case STM_8MBIT_SIGNATURE:
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flash_size = 0x00100000;
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break;
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case STM_16MBIT_SIGNATURE:
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flash_size = 0x00200000;
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break;
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case STM_32MBIT_SIGNATURE:
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flash_size = 0x00400000;
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break;
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case STM_64MBIT_SIGNATURE:
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flash_size = 0x00800000;
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break;
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case STM_128MBIT_SIGNATURE:
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flash_size = 0x01000000;
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break;
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}
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ar5315_spiflash_res[0].end = ar5315_spiflash_res[0].start + flash_size;
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return (char *) ar5315_spiflash_res[0].end;
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}
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int __init ar5315_init_devices(void)
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{
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struct ar531x_config *config;
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struct ar531x_boarddata *bcfg;
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u32 devid;
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int dev = 0;
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if (!is_5315)
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return 0;
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/* Find board configuration */
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ar531x_find_config(ar5315_flash_limit());
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bcfg = (struct ar531x_boarddata *) board_config;
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#if 0
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/* Detect the hardware based on the device ID */
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devid = sysRegRead(AR5315_SREV) & AR5315_REV_MAJ >> AR5315_REV_MAJ_S;
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switch(devid) {
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case 0x9:
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mips_machtype = MACH_ATHEROS_AR2317;
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break;
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/* FIXME: how can we detect AR2316? */
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case 0x8:
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default:
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mips_machtype = MACH_ATHEROS_AR2315;
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break;
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}
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#endif
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config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
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config->board = board_config;
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config->radio = radio_config;
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config->unit = 0;
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config->tag = (u_int16_t) (sysRegRead(AR5315_SREV) & AR5315_REV_CHIP);
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ar5315_eth_data.board_config = board_config;
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ar5315_eth_data.macaddr = bcfg->enet0Mac;
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ar5315_wmac.dev.platform_data = config;
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ar5315_devs[dev++] = &ar5315_eth;
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ar5315_devs[dev++] = &ar5315_wmac;
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ar5315_devs[dev++] = &ar5315_spiflash;
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return platform_add_devices(ar5315_devs, dev);
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}
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/*
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* Called when an interrupt is received, this function
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* determines exactly which interrupt it was, and it
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* invokes the appropriate handler.
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*
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* Implicitly, we also define interrupt priority by
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* choosing which to dispatch first.
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*/
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asmlinkage void ar5315_irq_dispatch(void)
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{
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int pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP3)
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do_IRQ(AR5315_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR5315_IRQ_ENET0_INTRS);
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else if (pending & CAUSEF_IP2) {
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unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
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if (ar531x_misc_intrs & AR5315_ISR_TIMER)
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do_IRQ(AR531X_MISC_IRQ_TIMER);
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else if (ar531x_misc_intrs & AR5315_ISR_AHB)
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do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
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else if (ar531x_misc_intrs & AR5315_ISR_GPIO) {
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sysRegWrite(AR5315_ISR, sysRegRead(AR5315_IMR) | ~AR5315_ISR_GPIO);
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} else if (ar531x_misc_intrs & AR5315_ISR_UART0)
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do_IRQ(AR531X_MISC_IRQ_UART0);
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else if (ar531x_misc_intrs & AR5315_ISR_WD)
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do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
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else
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do_IRQ(AR531X_MISC_IRQ_NONE);
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} else if (pending & CAUSEF_IP7)
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do_IRQ(AR531X_IRQ_CPU_CLOCK);
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else
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do_IRQ(AR531X_IRQ_NONE);
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}
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static void ar5315_halt(void)
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{
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while (1);
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}
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static void ar5315_power_off(void)
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{
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ar5315_halt();
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}
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static void ar5315_restart(char *command)
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{
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unsigned int reg;
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for(;;) {
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/* reset the system */
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sysRegWrite(AR5315_COLD_RESET,AR5317_RESET_SYSTEM);
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/*
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* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
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*/
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reg = sysRegRead(AR5315_GPIO_DO);
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reg &= ~(1 << AR5315_RESET_GPIO);
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sysRegWrite(AR5315_GPIO_DO, reg);
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(void)sysRegRead(AR5315_GPIO_DO); /* flush write to hardware */
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}
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}
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/*
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* This table is indexed by bits 5..4 of the CLOCKCTL1 register
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* to determine the predevisor value.
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*/
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static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
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1,
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2,
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4,
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5
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};
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static int __initdata PLLC_DIVIDE_TABLE[5] = {
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2,
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3,
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4,
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6,
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3
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};
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static unsigned int __init
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ar5315_sys_clk(unsigned int clockCtl)
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{
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unsigned int pllcCtrl,cpuDiv;
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unsigned int pllcOut,refdiv,fdiv,divby2;
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unsigned int clkDiv;
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pllcCtrl = sysRegRead(AR5315_PLLC_CTL);
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refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
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refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
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fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
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divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
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divby2 += 1;
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pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
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/* clkm input selected */
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switch(clockCtl & CPUCLK_CLK_SEL_M) {
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case 0:
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case 1:
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clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
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break;
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case 2:
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clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
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break;
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default:
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pllcOut = 40000000;
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clkDiv = 1;
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break;
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}
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cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
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cpuDiv = cpuDiv * 2 ?: 1;
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return (pllcOut/(clkDiv * cpuDiv));
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}
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static inline unsigned int ar5315_cpu_frequency(void)
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{
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return ar5315_sys_clk(sysRegRead(AR5315_CPUCLK));
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}
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static inline unsigned int ar5315_apb_frequency(void)
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{
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return ar5315_sys_clk(sysRegRead(AR5315_AMBACLK));
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}
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static void __init ar5315_time_init(void)
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{
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mips_hpt_frequency = ar5315_cpu_frequency() / 2;
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}
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/* Enable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_misc_intr_enable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR5315_IMR);
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switch(irq)
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{
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case AR531X_MISC_IRQ_TIMER:
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imr |= AR5315_ISR_TIMER;
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break;
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case AR531X_MISC_IRQ_AHB_PROC:
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imr |= AR5315_ISR_AHB;
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break;
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case AR531X_MISC_IRQ_AHB_DMA:
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imr |= 0/* ?? */;
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break;
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case AR531X_MISC_IRQ_GPIO:
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imr |= AR5315_ISR_GPIO;
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break;
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case AR531X_MISC_IRQ_UART0:
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imr |= AR5315_ISR_UART0;
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break;
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case AR531X_MISC_IRQ_WATCHDOG:
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imr |= AR5315_ISR_WD;
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break;
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case AR531X_MISC_IRQ_LOCAL:
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imr |= 0/* ?? */;
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break;
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}
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sysRegWrite(AR5315_IMR, imr);
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imr=sysRegRead(AR5315_IMR); /* flush write buffer */
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}
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/* Disable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_misc_intr_disable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR5315_IMR);
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switch(irq)
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{
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case AR531X_MISC_IRQ_TIMER:
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imr &= (~AR5315_ISR_TIMER);
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break;
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case AR531X_MISC_IRQ_AHB_PROC:
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imr &= (~AR5315_ISR_AHB);
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break;
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case AR531X_MISC_IRQ_AHB_DMA:
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imr &= 0/* ?? */;
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break;
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case AR531X_MISC_IRQ_GPIO:
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imr &= ~AR5315_ISR_GPIO;
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break;
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case AR531X_MISC_IRQ_UART0:
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imr &= (~AR5315_ISR_UART0);
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break;
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case AR531X_MISC_IRQ_WATCHDOG:
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imr &= (~AR5315_ISR_WD);
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break;
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case AR531X_MISC_IRQ_LOCAL:
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imr &= ~0/* ?? */;
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break;
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}
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sysRegWrite(AR5315_IMR, imr);
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sysRegRead(AR5315_IMR); /* flush write buffer */
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}
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/* Turn on the specified AR531X_MISC_IRQ interrupt */
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static unsigned int
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ar5315_misc_intr_startup(unsigned int irq)
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{
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ar5315_misc_intr_enable(irq);
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return 0;
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}
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/* Turn off the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5315_misc_intr_shutdown(unsigned int irq)
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{
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ar5315_misc_intr_disable(irq);
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}
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static void
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ar5315_misc_intr_ack(unsigned int irq)
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{
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ar5315_misc_intr_disable(irq);
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}
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static void
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ar5315_misc_intr_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ar5315_misc_intr_enable(irq);
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}
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static struct irq_chip ar5315_misc_intr_controller = {
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.typename = "AR5315 misc",
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.startup = ar5315_misc_intr_startup,
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.shutdown = ar5315_misc_intr_shutdown,
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.enable = ar5315_misc_intr_enable,
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.disable = ar5315_misc_intr_disable,
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.ack = ar5315_misc_intr_ack,
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.end = ar5315_misc_intr_end,
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};
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static irqreturn_t ar5315_ahb_proc_handler(int cpl, void *dev_id)
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{
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sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
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sysRegRead(AR5315_AHB_ERR1);
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printk("AHB fatal error\n");
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static struct irqaction ar5315_ahb_proc_interrupt = {
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.handler = ar5315_ahb_proc_handler,
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.flags = SA_INTERRUPT,
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.name = "ar5315_ahb_proc_interrupt",
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};
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static struct irqaction cascade = {
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.handler = no_action,
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.flags = SA_INTERRUPT,
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.name = "cascade",
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};
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void ar5315_misc_intr_init(int irq_base)
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{
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int i;
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for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &ar5315_misc_intr_controller;
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}
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setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
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setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
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}
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void __init ar5315_prom_init(void)
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{
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u32 memsize, memcfg;
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is_5315 = 1;
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memcfg = sysRegRead(AR5315_MEM_CFG);
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memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
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memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
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memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
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memsize <<= 3;
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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/* Initialize it to AR2315 for now. Real detection will be done
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* in ar5315_init_devices() */
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mips_machtype = MACH_ATHEROS_AR2315;
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}
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void __init ar5315_plat_setup(void)
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{
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unsigned int config = read_c0_config();
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/* Clear any lingering AHB errors */
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write_c0_config(config & ~0x3);
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sysRegWrite(AR5315_AHB_ERR0,AHB_ERROR_DET);
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sysRegRead(AR5315_AHB_ERR1);
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sysRegWrite(AR5315_WDC, WDC_IGNORE_EXPIRATION);
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board_time_init = ar5315_time_init;
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_machine_restart = ar5315_restart;
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_machine_halt = ar5315_halt;
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pm_power_off = ar5315_power_off;
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serial_setup(KSEG1ADDR(AR5315_UART0), ar5315_apb_frequency());
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}
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arch_initcall(ar5315_init_devices);
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